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Merge branch 'omap-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel...
[deliverable/linux.git] / drivers / mtd / onenand / onenand_base.c
CommitLineData
cd5f6346
KP		 1/*
2 * linux/drivers/mtd/onenand/onenand_base.c
3 *
3cf60253
AKS		 4 * Copyright © 2005-2009 Samsung Electronics
5 * Copyright © 2007 Nokia Corporation
6 *
cd5f6346
KP		 7 * Kyungmin Park <kyungmin.park@samsung.com>
8 *
81280d58
AH		 9 * Credits:
10 * Adrian Hunter <ext-adrian.hunter@nokia.com>:
11 * auto-placement support, read-while load support, various fixes
81280d58 12 *
5988af23
RH		 13 * Vishak G <vishak.g at samsung.com>, Rohit Hagargundgi <h.rohit at samsung.com>
14 * Flex-OneNAND support
3cf60253
AKS		 15 * Amul Kumar Saha <amul.saha at samsung.com>
16 * OTP support
5988af23 17 *
cd5f6346
KP		 18 * This program is free software; you can redistribute it and/or modify
19 * it under the terms of the GNU General Public License version 2 as
20 * published by the Free Software Foundation.
21 */
22
23#include <linux/kernel.h>
24#include <linux/module.h>
c90173f0 25#include <linux/moduleparam.h>
5a0e3ad6 26#include <linux/slab.h>
cd5f6346 27#include <linux/init.h>
015953d7 28#include <linux/sched.h>
6c77fd64 29#include <linux/delay.h>
2c22120f 30#include <linux/interrupt.h>
015953d7 31#include <linux/jiffies.h>
cd5f6346
KP		 32#include <linux/mtd/mtd.h>
33#include <linux/mtd/onenand.h>
34#include <linux/mtd/partitions.h>
35
36#include <asm/io.h>
37
72073027
MK		 38/*
39 * Multiblock erase if number of blocks to erase is 2 or more.
40 * Maximum number of blocks for simultaneous erase is 64.
41 */
42#define MB_ERASE_MIN_BLK_COUNT 2
43#define MB_ERASE_MAX_BLK_COUNT 64
44
5988af23
RH		 45/* Default Flex-OneNAND boundary and lock respectively */
46static int flex_bdry[MAX_DIES * 2] = { -1, 0, -1, 0 };
47
c90173f0
AS		 48module_param_array(flex_bdry, int, NULL, 0400);
49MODULE_PARM_DESC(flex_bdry, "SLC Boundary information for Flex-OneNAND"
50 "Syntax:flex_bdry=DIE_BDRY,LOCK,..."
51 "DIE_BDRY: SLC boundary of the die"
52 "LOCK: Locking information for SLC boundary"
53 " : 0->Set boundary in unlocked status"
54 " : 1->Set boundary in locked status");
55
3cf60253
AKS		 56/* Default OneNAND/Flex-OneNAND OTP options*/
57static int otp;
58
59module_param(otp, int, 0400);
60MODULE_PARM_DESC(otp, "Corresponding behaviour of OneNAND in OTP"
61 "Syntax : otp=LOCK_TYPE"
62 "LOCK_TYPE : Keys issued, for specific OTP Lock type"
63 " : 0 -> Default (No Blocks Locked)"
64 " : 1 -> OTP Block lock"
65 " : 2 -> 1st Block lock"
66 " : 3 -> BOTH OTP Block and 1st Block lock");
67
5988af23
RH		 68/**
69 * onenand_oob_128 - oob info for Flex-Onenand with 4KB page
70 * For now, we expose only 64 out of 80 ecc bytes
71 */
72static struct nand_ecclayout onenand_oob_128 = {
73 .eccbytes = 64,
74 .eccpos = {
75 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
76 22, 23, 24, 25, 26, 27, 28, 29, 30, 31,
77 38, 39, 40, 41, 42, 43, 44, 45, 46, 47,
78 54, 55, 56, 57, 58, 59, 60, 61, 62, 63,
79 70, 71, 72, 73, 74, 75, 76, 77, 78, 79,
80 86, 87, 88, 89, 90, 91, 92, 93, 94, 95,
81 102, 103, 104, 105
82 },
83 .oobfree = {
84 {2, 4}, {18, 4}, {34, 4}, {50, 4},
85 {66, 4}, {82, 4}, {98, 4}, {114, 4}
86 }
87};
88
cd5f6346
KP		 89/**
90 * onenand_oob_64 - oob info for large (2KB) page
91 */
5bd34c09 92static struct nand_ecclayout onenand_oob_64 = {
cd5f6346
KP		 93 .eccbytes = 20,
94 .eccpos = {
95 8, 9, 10, 11, 12,
96 24, 25, 26, 27, 28,
97 40, 41, 42, 43, 44,
98 56, 57, 58, 59, 60,
99 },
100 .oobfree = {
101 {2, 3}, {14, 2}, {18, 3}, {30, 2},
d9777f1c
JL		 102 {34, 3}, {46, 2}, {50, 3}, {62, 2}
103 }
cd5f6346
KP		 104};
105
106/**
107 * onenand_oob_32 - oob info for middle (1KB) page
108 */
5bd34c09 109static struct nand_ecclayout onenand_oob_32 = {
cd5f6346
KP		 110 .eccbytes = 10,
111 .eccpos = {
112 8, 9, 10, 11, 12,
113 24, 25, 26, 27, 28,
114 },
115 .oobfree = { {2, 3}, {14, 2}, {18, 3}, {30, 2} }
116};
117
118static const unsigned char ffchars[] = {
119 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
120 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* 16 */
121 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
122 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* 32 */
123 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
124 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* 48 */
125 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
126 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* 64 */
5988af23
RH		 127 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
128 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* 80 */
129 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
130 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* 96 */
131 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
132 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* 112 */
133 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
134 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* 128 */
cd5f6346
KP		 135};
136
137/**
138 * onenand_readw - [OneNAND Interface] Read OneNAND register
139 * @param addr address to read
140 *
141 * Read OneNAND register
142 */
143static unsigned short onenand_readw(void __iomem *addr)
144{
145 return readw(addr);
146}
147
148/**
149 * onenand_writew - [OneNAND Interface] Write OneNAND register with value
150 * @param value value to write
151 * @param addr address to write
152 *
153 * Write OneNAND register with value
154 */
155static void onenand_writew(unsigned short value, void __iomem *addr)
156{
157 writew(value, addr);
158}
159
160/**
161 * onenand_block_address - [DEFAULT] Get block address
83a36838 162 * @param this onenand chip data structure
cd5f6346
KP		 163 * @param block the block
164 * @return translated block address if DDP, otherwise same
165 *
166 * Setup Start Address 1 Register (F100h)
167 */
83a36838 168static int onenand_block_address(struct onenand_chip *this, int block)
cd5f6346 169{
738d61f5
KP		 170 /* Device Flash Core select, NAND Flash Block Address */
171 if (block & this->density_mask)
172 return ONENAND_DDP_CHIP1 | (block ^ this->density_mask);
cd5f6346
KP		 173
174 return block;
175}
176
177/**
178 * onenand_bufferram_address - [DEFAULT] Get bufferram address
83a36838 179 * @param this onenand chip data structure
cd5f6346
KP		 180 * @param block the block
181 * @return set DBS value if DDP, otherwise 0
182 *
183 * Setup Start Address 2 Register (F101h) for DDP
184 */
83a36838 185static int onenand_bufferram_address(struct onenand_chip *this, int block)
cd5f6346 186{
738d61f5
KP		 187 /* Device BufferRAM Select */
188 if (block & this->density_mask)
189 return ONENAND_DDP_CHIP1;
cd5f6346 190
738d61f5 191 return ONENAND_DDP_CHIP0;
cd5f6346
KP		 192}
193
194/**
195 * onenand_page_address - [DEFAULT] Get page address
196 * @param page the page address
197 * @param sector the sector address
198 * @return combined page and sector address
199 *
200 * Setup Start Address 8 Register (F107h)
201 */
202static int onenand_page_address(int page, int sector)
203{
204 /* Flash Page Address, Flash Sector Address */
205 int fpa, fsa;
206
207 fpa = page & ONENAND_FPA_MASK;
208 fsa = sector & ONENAND_FSA_MASK;
209
210 return ((fpa << ONENAND_FPA_SHIFT) | fsa);
211}
212
213/**
214 * onenand_buffer_address - [DEFAULT] Get buffer address
215 * @param dataram1 DataRAM index
216 * @param sectors the sector address
217 * @param count the number of sectors
218 * @return the start buffer value
219 *
220 * Setup Start Buffer Register (F200h)
221 */
222static int onenand_buffer_address(int dataram1, int sectors, int count)
223{
224 int bsa, bsc;
225
226 /* BufferRAM Sector Address */
227 bsa = sectors & ONENAND_BSA_MASK;
228
229 if (dataram1)
230 bsa |= ONENAND_BSA_DATARAM1; /* DataRAM1 */
231 else
232 bsa |= ONENAND_BSA_DATARAM0; /* DataRAM0 */
233
234 /* BufferRAM Sector Count */
235 bsc = count & ONENAND_BSC_MASK;
236
237 return ((bsa << ONENAND_BSA_SHIFT) | bsc);
238}
239
5988af23
RH		 240/**
241 * flexonenand_block- For given address return block number
242 * @param this - OneNAND device structure
243 * @param addr - Address for which block number is needed
244 */
245static unsigned flexonenand_block(struct onenand_chip *this, loff_t addr)
246{
247 unsigned boundary, blk, die = 0;
248
249 if (ONENAND_IS_DDP(this) && addr >= this->diesize[0]) {
250 die = 1;
251 addr -= this->diesize[0];
252 }
253
254 boundary = this->boundary[die];
255
256 blk = addr >> (this->erase_shift - 1);
257 if (blk > boundary)
258 blk = (blk + boundary + 1) >> 1;
259
260 blk += die ? this->density_mask : 0;
261 return blk;
262}
263
264inline unsigned onenand_block(struct onenand_chip *this, loff_t addr)
265{
266 if (!FLEXONENAND(this))
267 return addr >> this->erase_shift;
268 return flexonenand_block(this, addr);
269}
270
271/**
272 * flexonenand_addr - Return address of the block
273 * @this: OneNAND device structure
274 * @block: Block number on Flex-OneNAND
275 *
276 * Return address of the block
277 */
278static loff_t flexonenand_addr(struct onenand_chip *this, int block)
279{
280 loff_t ofs = 0;
281 int die = 0, boundary;
282
283 if (ONENAND_IS_DDP(this) && block >= this->density_mask) {
284 block -= this->density_mask;
285 die = 1;
286 ofs = this->diesize[0];
287 }
288
289 boundary = this->boundary[die];
290 ofs += (loff_t)block << (this->erase_shift - 1);
291 if (block > (boundary + 1))
292 ofs += (loff_t)(block - boundary - 1) << (this->erase_shift - 1);
293 return ofs;
294}
295
296loff_t onenand_addr(struct onenand_chip *this, int block)
297{
298 if (!FLEXONENAND(this))
299 return (loff_t)block << this->erase_shift;
300 return flexonenand_addr(this, block);
301}
302EXPORT_SYMBOL(onenand_addr);
303
e71f04fc
KP		 304/**
305 * onenand_get_density - [DEFAULT] Get OneNAND density
306 * @param dev_id OneNAND device ID
307 *
308 * Get OneNAND density from device ID
309 */
310static inline int onenand_get_density(int dev_id)
311{
312 int density = dev_id >> ONENAND_DEVICE_DENSITY_SHIFT;
313 return (density & ONENAND_DEVICE_DENSITY_MASK);
314}
315
5988af23
RH		 316/**
317 * flexonenand_region - [Flex-OneNAND] Return erase region of addr
318 * @param mtd MTD device structure
319 * @param addr address whose erase region needs to be identified
320 */
321int flexonenand_region(struct mtd_info *mtd, loff_t addr)
322{
323 int i;
324
325 for (i = 0; i < mtd->numeraseregions; i++)
326 if (addr < mtd->eraseregions[i].offset)
327 break;
328 return i - 1;
329}
330EXPORT_SYMBOL(flexonenand_region);
331
cd5f6346
KP		 332/**
333 * onenand_command - [DEFAULT] Send command to OneNAND device
334 * @param mtd MTD device structure
335 * @param cmd the command to be sent
336 * @param addr offset to read from or write to
337 * @param len number of bytes to read or write
338 *
339 * Send command to OneNAND device. This function is used for middle/large page
340 * devices (1KB/2KB Bytes per page)
341 */
342static int onenand_command(struct mtd_info *mtd, int cmd, loff_t addr, size_t len)
343{
344 struct onenand_chip *this = mtd->priv;
b21b72cf 345 int value, block, page;
cd5f6346
KP		 346
347 /* Address translation */
348 switch (cmd) {
349 case ONENAND_CMD_UNLOCK:
350 case ONENAND_CMD_LOCK:
351 case ONENAND_CMD_LOCK_TIGHT:
28b79ff9 352 case ONENAND_CMD_UNLOCK_ALL:
cd5f6346
KP		 353 block = -1;
354 page = -1;
355 break;
356
5988af23
RH		 357 case FLEXONENAND_CMD_PI_ACCESS:
358 /* addr contains die index */
359 block = addr * this->density_mask;
360 page = -1;
361 break;
362
cd5f6346 363 case ONENAND_CMD_ERASE:
72073027
MK		 364 case ONENAND_CMD_MULTIBLOCK_ERASE:
365 case ONENAND_CMD_ERASE_VERIFY:
cd5f6346 366 case ONENAND_CMD_BUFFERRAM:
493c6460 367 case ONENAND_CMD_OTP_ACCESS:
5988af23 368 block = onenand_block(this, addr);
cd5f6346
KP		 369 page = -1;
370 break;
371
5988af23
RH		 372 case FLEXONENAND_CMD_READ_PI:
373 cmd = ONENAND_CMD_READ;
374 block = addr * this->density_mask;
375 page = 0;
376 break;
377
cd5f6346 378 default:
5988af23 379 block = onenand_block(this, addr);
42b0aab1
RHS		 380 if (FLEXONENAND(this))
381 page = (int) (addr - onenand_addr(this, block))>>\
382 this->page_shift;
383 else
384 page = (int) (addr >> this->page_shift);
ee9745fc
KP		 385 if (ONENAND_IS_2PLANE(this)) {
386 /* Make the even block number */
387 block &= ~1;
388 /* Is it the odd plane? */
389 if (addr & this->writesize)
390 block++;
391 page >>= 1;
392 }
cd5f6346
KP		 393 page &= this->page_mask;
394 break;
395 }
396
397 /* NOTE: The setting order of the registers is very important! */
398 if (cmd == ONENAND_CMD_BUFFERRAM) {
399 /* Select DataRAM for DDP */
83a36838 400 value = onenand_bufferram_address(this, block);
cd5f6346
KP		 401 this->write_word(value, this->base + ONENAND_REG_START_ADDRESS2);
402
8a8f632d 403 if (ONENAND_IS_2PLANE(this) || ONENAND_IS_4KB_PAGE(this))
ee9745fc
KP		 404 /* It is always BufferRAM0 */
405 ONENAND_SET_BUFFERRAM0(this);
406 else
407 /* Switch to the next data buffer */
408 ONENAND_SET_NEXT_BUFFERRAM(this);
cd5f6346
KP		 409
410 return 0;
411 }
412
413 if (block != -1) {
414 /* Write 'DFS, FBA' of Flash */
83a36838 415 value = onenand_block_address(this, block);
cd5f6346 416 this->write_word(value, this->base + ONENAND_REG_START_ADDRESS1);
3cecf69e 417
b21b72cf
KP		 418 /* Select DataRAM for DDP */
419 value = onenand_bufferram_address(this, block);
420 this->write_word(value, this->base + ONENAND_REG_START_ADDRESS2);
cd5f6346
KP		 421 }
422
423 if (page != -1) {
60d84f97 424 /* Now we use page size operation */
5988af23 425 int sectors = 0, count = 0;
cd5f6346
KP		 426 int dataram;
427
428 switch (cmd) {
5988af23 429 case FLEXONENAND_CMD_RECOVER_LSB:
cd5f6346
KP		 430 case ONENAND_CMD_READ:
431 case ONENAND_CMD_READOOB:
8a8f632d 432 if (ONENAND_IS_4KB_PAGE(this))
5988af23
RH		 433 /* It is always BufferRAM0 */
434 dataram = ONENAND_SET_BUFFERRAM0(this);
435 else
436 dataram = ONENAND_SET_NEXT_BUFFERRAM(this);
cd5f6346
KP		 437 break;
438
439 default:
ee9745fc
KP		 440 if (ONENAND_IS_2PLANE(this) && cmd == ONENAND_CMD_PROG)
441 cmd = ONENAND_CMD_2X_PROG;
cd5f6346
KP		 442 dataram = ONENAND_CURRENT_BUFFERRAM(this);
443 break;
444 }
445
446 /* Write 'FPA, FSA' of Flash */
447 value = onenand_page_address(page, sectors);
448 this->write_word(value, this->base + ONENAND_REG_START_ADDRESS8);
449
450 /* Write 'BSA, BSC' of DataRAM */
451 value = onenand_buffer_address(dataram, sectors, count);
452 this->write_word(value, this->base + ONENAND_REG_START_BUFFER);
cd5f6346
KP		 453 }
454
455 /* Interrupt clear */
456 this->write_word(ONENAND_INT_CLEAR, this->base + ONENAND_REG_INTERRUPT);
457
458 /* Write command */
459 this->write_word(cmd, this->base + ONENAND_REG_COMMAND);
460
461 return 0;
462}
463
5988af23
RH		 464/**
465 * onenand_read_ecc - return ecc status
466 * @param this onenand chip structure
467 */
468static inline int onenand_read_ecc(struct onenand_chip *this)
469{
470 int ecc, i, result = 0;
471
6a88c47b 472 if (!FLEXONENAND(this) && !ONENAND_IS_4KB_PAGE(this))
5988af23
RH		 473 return this->read_word(this->base + ONENAND_REG_ECC_STATUS);
474
475 for (i = 0; i < 4; i++) {
6a88c47b 476 ecc = this->read_word(this->base + ONENAND_REG_ECC_STATUS + i*2);
5988af23
RH		 477 if (likely(!ecc))
478 continue;
479 if (ecc & FLEXONENAND_UNCORRECTABLE_ERROR)
480 return ONENAND_ECC_2BIT_ALL;
481 else
482 result = ONENAND_ECC_1BIT_ALL;
483 }
484
485 return result;
486}
487
cd5f6346
KP		 488/**
489 * onenand_wait - [DEFAULT] wait until the command is done
490 * @param mtd MTD device structure
491 * @param state state to select the max. timeout value
492 *
493 * Wait for command done. This applies to all OneNAND command
494 * Read can take up to 30us, erase up to 2ms and program up to 350us
495 * according to general OneNAND specs
496 */
497static int onenand_wait(struct mtd_info *mtd, int state)
498{
499 struct onenand_chip * this = mtd->priv;
500 unsigned long timeout;
501 unsigned int flags = ONENAND_INT_MASTER;
502 unsigned int interrupt = 0;
2fd32d4a 503 unsigned int ctrl;
cd5f6346
KP		 504
505 /* The 20 msec is enough */
506 timeout = jiffies + msecs_to_jiffies(20);
507 while (time_before(jiffies, timeout)) {
508 interrupt = this->read_word(this->base + ONENAND_REG_INTERRUPT);
509
510 if (interrupt & flags)
511 break;
512
72073027 513 if (state != FL_READING && state != FL_PREPARING_ERASE)
cd5f6346
KP		 514 cond_resched();
515 }
516 /* To get correct interrupt status in timeout case */
517 interrupt = this->read_word(this->base + ONENAND_REG_INTERRUPT);
518
519 ctrl = this->read_word(this->base + ONENAND_REG_CTRL_STATUS);
520
83973b87
KP		 521 /*
522 * In the Spec. it checks the controller status first
523 * However if you get the correct information in case of
524 * power off recovery (POR) test, it should read ECC status first
525 */
cd5f6346 526 if (interrupt & ONENAND_INT_READ) {
5988af23 527 int ecc = onenand_read_ecc(this);
f4f91ac3 528 if (ecc) {
b3c9f8bf 529 if (ecc & ONENAND_ECC_2BIT_ALL) {
297758f8
AKS		 530 printk(KERN_ERR "%s: ECC error = 0x%04x\n",
531 __func__, ecc);
f4f91ac3 532 mtd->ecc_stats.failed++;
30a7eb29 533 return -EBADMSG;
49dc08ee 534 } else if (ecc & ONENAND_ECC_1BIT_ALL) {
297758f8
AKS		 535 printk(KERN_DEBUG "%s: correctable ECC error = 0x%04x\n",
536 __func__, ecc);
f4f91ac3 537 mtd->ecc_stats.corrected++;
49dc08ee 538 }
cd5f6346 539 }
9d032801 540 } else if (state == FL_READING) {
297758f8
AKS		 541 printk(KERN_ERR "%s: read timeout! ctrl=0x%04x intr=0x%04x\n",
542 __func__, ctrl, interrupt);
9d032801 543 return -EIO;
cd5f6346
KP		 544 }
545
72073027
MK		 546 if (state == FL_PREPARING_ERASE && !(interrupt & ONENAND_INT_ERASE)) {
547 printk(KERN_ERR "%s: mb erase timeout! ctrl=0x%04x intr=0x%04x\n",
548 __func__, ctrl, interrupt);
549 return -EIO;
550 }
551
552 if (!(interrupt & ONENAND_INT_MASTER)) {
553 printk(KERN_ERR "%s: timeout! ctrl=0x%04x intr=0x%04x\n",
554 __func__, ctrl, interrupt);
555 return -EIO;
556 }
557
83973b87
KP		 558 /* If there's controller error, it's a real error */
559 if (ctrl & ONENAND_CTRL_ERROR) {
297758f8
AKS		 560 printk(KERN_ERR "%s: controller error = 0x%04x\n",
561 __func__, ctrl);
83973b87 562 if (ctrl & ONENAND_CTRL_LOCK)
297758f8 563 printk(KERN_ERR "%s: it's locked error.\n", __func__);
83973b87
KP		 564 return -EIO;
565 }
566
cd5f6346
KP		 567 return 0;
568}
569
2c22120f
KP		 570/*
571 * onenand_interrupt - [DEFAULT] onenand interrupt handler
572 * @param irq onenand interrupt number
573 * @param dev_id interrupt data
574 *
575 * complete the work
576 */
577static irqreturn_t onenand_interrupt(int irq, void *data)
578{
06efcad0 579 struct onenand_chip *this = data;
2c22120f
KP		 580
581 /* To handle shared interrupt */
582 if (!this->complete.done)
583 complete(&this->complete);
584
585 return IRQ_HANDLED;
586}
587
588/*
589 * onenand_interrupt_wait - [DEFAULT] wait until the command is done
590 * @param mtd MTD device structure
591 * @param state state to select the max. timeout value
592 *
593 * Wait for command done.
594 */
595static int onenand_interrupt_wait(struct mtd_info *mtd, int state)
596{
597 struct onenand_chip *this = mtd->priv;
598
2c22120f
KP		 599 wait_for_completion(&this->complete);
600
601 return onenand_wait(mtd, state);
602}
603
604/*
605 * onenand_try_interrupt_wait - [DEFAULT] try interrupt wait
606 * @param mtd MTD device structure
607 * @param state state to select the max. timeout value
608 *
609 * Try interrupt based wait (It is used one-time)
610 */
611static int onenand_try_interrupt_wait(struct mtd_info *mtd, int state)
612{
613 struct onenand_chip *this = mtd->priv;
614 unsigned long remain, timeout;
615
616 /* We use interrupt wait first */
617 this->wait = onenand_interrupt_wait;
618
2c22120f
KP		 619 timeout = msecs_to_jiffies(100);
620 remain = wait_for_completion_timeout(&this->complete, timeout);
621 if (!remain) {
622 printk(KERN_INFO "OneNAND: There's no interrupt. "
623 "We use the normal wait\n");
624
625 /* Release the irq */
626 free_irq(this->irq, this);
c9ac5977 627
2c22120f
KP		 628 this->wait = onenand_wait;
629 }
630
631 return onenand_wait(mtd, state);
632}
633
634/*
635 * onenand_setup_wait - [OneNAND Interface] setup onenand wait method
636 * @param mtd MTD device structure
637 *
638 * There's two method to wait onenand work
639 * 1. polling - read interrupt status register
640 * 2. interrupt - use the kernel interrupt method
641 */
642static void onenand_setup_wait(struct mtd_info *mtd)
643{
644 struct onenand_chip *this = mtd->priv;
645 int syscfg;
646
647 init_completion(&this->complete);
648
649 if (this->irq <= 0) {
650 this->wait = onenand_wait;
651 return;
652 }
653
654 if (request_irq(this->irq, &onenand_interrupt,
655 IRQF_SHARED, "onenand", this)) {
656 /* If we can't get irq, use the normal wait */
657 this->wait = onenand_wait;
658 return;
659 }
660
661 /* Enable interrupt */
662 syscfg = this->read_word(this->base + ONENAND_REG_SYS_CFG1);
663 syscfg |= ONENAND_SYS_CFG1_IOBE;
664 this->write_word(syscfg, this->base + ONENAND_REG_SYS_CFG1);
665
666 this->wait = onenand_try_interrupt_wait;
667}
668
cd5f6346
KP		 669/**
670 * onenand_bufferram_offset - [DEFAULT] BufferRAM offset
671 * @param mtd MTD data structure
672 * @param area BufferRAM area
673 * @return offset given area
674 *
675 * Return BufferRAM offset given area
676 */
677static inline int onenand_bufferram_offset(struct mtd_info *mtd, int area)
678{
679 struct onenand_chip *this = mtd->priv;
680
681 if (ONENAND_CURRENT_BUFFERRAM(this)) {
ee9745fc 682 /* Note: the 'this->writesize' is a real page size */
cd5f6346 683 if (area == ONENAND_DATARAM)
ee9745fc 684 return this->writesize;
cd5f6346
KP		 685 if (area == ONENAND_SPARERAM)
686 return mtd->oobsize;
687 }
688
689 return 0;
690}
691
692/**
693 * onenand_read_bufferram - [OneNAND Interface] Read the bufferram area
694 * @param mtd MTD data structure
695 * @param area BufferRAM area
696 * @param buffer the databuffer to put/get data
697 * @param offset offset to read from or write to
698 * @param count number of bytes to read/write
699 *
700 * Read the BufferRAM area
701 */
702static int onenand_read_bufferram(struct mtd_info *mtd, int area,
703 unsigned char *buffer, int offset, size_t count)
704{
705 struct onenand_chip *this = mtd->priv;
706 void __iomem *bufferram;
707
708 bufferram = this->base + area;
709
710 bufferram += onenand_bufferram_offset(mtd, area);
711
9c01f87d
KP		 712 if (ONENAND_CHECK_BYTE_ACCESS(count)) {
713 unsigned short word;
714
715 /* Align with word(16-bit) size */
716 count--;
717
718 /* Read word and save byte */
719 word = this->read_word(bufferram + offset + count);
720 buffer[count] = (word & 0xff);
721 }
722
cd5f6346
KP		 723 memcpy(buffer, bufferram + offset, count);
724
725 return 0;
726}
727
52b0eea7
KP		 728/**
729 * onenand_sync_read_bufferram - [OneNAND Interface] Read the bufferram area with Sync. Burst mode
730 * @param mtd MTD data structure
731 * @param area BufferRAM area
732 * @param buffer the databuffer to put/get data
733 * @param offset offset to read from or write to
734 * @param count number of bytes to read/write
735 *
736 * Read the BufferRAM area with Sync. Burst Mode
737 */
738static int onenand_sync_read_bufferram(struct mtd_info *mtd, int area,
739 unsigned char *buffer, int offset, size_t count)
740{
741 struct onenand_chip *this = mtd->priv;
742 void __iomem *bufferram;
743
744 bufferram = this->base + area;
745
746 bufferram += onenand_bufferram_offset(mtd, area);
747
748 this->mmcontrol(mtd, ONENAND_SYS_CFG1_SYNC_READ);
749
9c01f87d
KP		 750 if (ONENAND_CHECK_BYTE_ACCESS(count)) {
751 unsigned short word;
752
753 /* Align with word(16-bit) size */
754 count--;
755
756 /* Read word and save byte */
757 word = this->read_word(bufferram + offset + count);
758 buffer[count] = (word & 0xff);
759 }
760
52b0eea7
KP		 761 memcpy(buffer, bufferram + offset, count);
762
763 this->mmcontrol(mtd, 0);
764
765 return 0;
766}
767
cd5f6346
KP		 768/**
769 * onenand_write_bufferram - [OneNAND Interface] Write the bufferram area
770 * @param mtd MTD data structure
771 * @param area BufferRAM area
772 * @param buffer the databuffer to put/get data
773 * @param offset offset to read from or write to
774 * @param count number of bytes to read/write
775 *
776 * Write the BufferRAM area
777 */
778static int onenand_write_bufferram(struct mtd_info *mtd, int area,
779 const unsigned char *buffer, int offset, size_t count)
780{
781 struct onenand_chip *this = mtd->priv;
782 void __iomem *bufferram;
783
784 bufferram = this->base + area;
785
786 bufferram += onenand_bufferram_offset(mtd, area);
787
9c01f87d
KP		 788 if (ONENAND_CHECK_BYTE_ACCESS(count)) {
789 unsigned short word;
790 int byte_offset;
791
792 /* Align with word(16-bit) size */
793 count--;
794
795 /* Calculate byte access offset */
796 byte_offset = offset + count;
797
798 /* Read word and save byte */
799 word = this->read_word(bufferram + byte_offset);
800 word = (word & ~0xff) | buffer[count];
801 this->write_word(word, bufferram + byte_offset);
802 }
803
cd5f6346
KP		 804 memcpy(bufferram + offset, buffer, count);
805
806 return 0;
807}
808
ee9745fc
KP		 809/**
810 * onenand_get_2x_blockpage - [GENERIC] Get blockpage at 2x program mode
811 * @param mtd MTD data structure
812 * @param addr address to check
813 * @return blockpage address
814 *
815 * Get blockpage address at 2x program mode
816 */
817static int onenand_get_2x_blockpage(struct mtd_info *mtd, loff_t addr)
818{
819 struct onenand_chip *this = mtd->priv;
820 int blockpage, block, page;
821
822 /* Calculate the even block number */
823 block = (int) (addr >> this->erase_shift) & ~1;
824 /* Is it the odd plane? */
825 if (addr & this->writesize)
826 block++;
827 page = (int) (addr >> (this->page_shift + 1)) & this->page_mask;
828 blockpage = (block << 7) | page;
829
830 return blockpage;
831}
832
cd5f6346
KP		 833/**
834 * onenand_check_bufferram - [GENERIC] Check BufferRAM information
835 * @param mtd MTD data structure
836 * @param addr address to check
d5c5e78a 837 * @return 1 if there are valid data, otherwise 0
cd5f6346
KP		 838 *
839 * Check bufferram if there is data we required
840 */
841static int onenand_check_bufferram(struct mtd_info *mtd, loff_t addr)
842{
843 struct onenand_chip *this = mtd->priv;
cde36b37 844 int blockpage, found = 0;
abf3c0f2 845 unsigned int i;
d5c5e78a 846
ee9745fc
KP		 847 if (ONENAND_IS_2PLANE(this))
848 blockpage = onenand_get_2x_blockpage(mtd, addr);
849 else
850 blockpage = (int) (addr >> this->page_shift);
cd5f6346 851
abf3c0f2 852 /* Is there valid data? */
cd5f6346 853 i = ONENAND_CURRENT_BUFFERRAM(this);
abf3c0f2 854 if (this->bufferram[i].blockpage == blockpage)
cde36b37
AH		 855 found = 1;
856 else {
857 /* Check another BufferRAM */
858 i = ONENAND_NEXT_BUFFERRAM(this);
859 if (this->bufferram[i].blockpage == blockpage) {
860 ONENAND_SET_NEXT_BUFFERRAM(this);
861 found = 1;
862 }
863 }
cd5f6346 864
cde36b37
AH		 865 if (found && ONENAND_IS_DDP(this)) {
866 /* Select DataRAM for DDP */
5988af23 867 int block = onenand_block(this, addr);
cde36b37
AH		 868 int value = onenand_bufferram_address(this, block);
869 this->write_word(value, this->base + ONENAND_REG_START_ADDRESS2);
abf3c0f2 870 }
cd5f6346 871
cde36b37 872 return found;
cd5f6346
KP		 873}
874
875/**
876 * onenand_update_bufferram - [GENERIC] Update BufferRAM information
877 * @param mtd MTD data structure
878 * @param addr address to update
879 * @param valid valid flag
880 *
881 * Update BufferRAM information
882 */
abf3c0f2 883static void onenand_update_bufferram(struct mtd_info *mtd, loff_t addr,
cd5f6346
KP		 884 int valid)
885{
886 struct onenand_chip *this = mtd->priv;
abf3c0f2
KP		 887 int blockpage;
888 unsigned int i;
d5c5e78a 889
ee9745fc
KP		 890 if (ONENAND_IS_2PLANE(this))
891 blockpage = onenand_get_2x_blockpage(mtd, addr);
892 else
893 blockpage = (int) (addr >> this->page_shift);
cd5f6346 894
abf3c0f2
KP		 895 /* Invalidate another BufferRAM */
896 i = ONENAND_NEXT_BUFFERRAM(this);
5b4246f1 897 if (this->bufferram[i].blockpage == blockpage)
abf3c0f2 898 this->bufferram[i].blockpage = -1;
cd5f6346
KP		 899
900 /* Update BufferRAM */
901 i = ONENAND_CURRENT_BUFFERRAM(this);
abf3c0f2
KP		 902 if (valid)
903 this->bufferram[i].blockpage = blockpage;
904 else
905 this->bufferram[i].blockpage = -1;
cd5f6346
KP		 906}
907
480b9dfb
AH		 908/**
909 * onenand_invalidate_bufferram - [GENERIC] Invalidate BufferRAM information
910 * @param mtd MTD data structure
911 * @param addr start address to invalidate
912 * @param len length to invalidate
913 *
914 * Invalidate BufferRAM information
915 */
916static void onenand_invalidate_bufferram(struct mtd_info *mtd, loff_t addr,
917 unsigned int len)
918{
919 struct onenand_chip *this = mtd->priv;
920 int i;
921 loff_t end_addr = addr + len;
922
923 /* Invalidate BufferRAM */
924 for (i = 0; i < MAX_BUFFERRAM; i++) {
925 loff_t buf_addr = this->bufferram[i].blockpage << this->page_shift;
926 if (buf_addr >= addr && buf_addr < end_addr)
927 this->bufferram[i].blockpage = -1;
928 }
929}
930
cd5f6346
KP		 931/**
932 * onenand_get_device - [GENERIC] Get chip for selected access
933 * @param mtd MTD device structure
934 * @param new_state the state which is requested
935 *
936 * Get the device and lock it for exclusive access
937 */
a41371eb 938static int onenand_get_device(struct mtd_info *mtd, int new_state)
cd5f6346
KP		 939{
940 struct onenand_chip *this = mtd->priv;
941 DECLARE_WAITQUEUE(wait, current);
942
943 /*
944 * Grab the lock and see if the device is available
945 */
946 while (1) {
947 spin_lock(&this->chip_lock);
948 if (this->state == FL_READY) {
949 this->state = new_state;
950 spin_unlock(&this->chip_lock);
cf24dc85
AH		 951 if (new_state != FL_PM_SUSPENDED && this->enable)
952 this->enable(mtd);
cd5f6346
KP		 953 break;
954 }
a41371eb
KP		 955 if (new_state == FL_PM_SUSPENDED) {
956 spin_unlock(&this->chip_lock);
957 return (this->state == FL_PM_SUSPENDED) ? 0 : -EAGAIN;
958 }
cd5f6346
KP		 959 set_current_state(TASK_UNINTERRUPTIBLE);
960 add_wait_queue(&this->wq, &wait);
961 spin_unlock(&this->chip_lock);
962 schedule();
963 remove_wait_queue(&this->wq, &wait);
964 }
a41371eb
KP		 965
966 return 0;
cd5f6346
KP		 967}
968
969/**
970 * onenand_release_device - [GENERIC] release chip
971 * @param mtd MTD device structure
972 *
973 * Deselect, release chip lock and wake up anyone waiting on the device
974 */
975static void onenand_release_device(struct mtd_info *mtd)
976{
977 struct onenand_chip *this = mtd->priv;
978
cf24dc85
AH		 979 if (this->state != FL_PM_SUSPENDED && this->disable)
980 this->disable(mtd);
cd5f6346
KP		 981 /* Release the chip */
982 spin_lock(&this->chip_lock);
983 this->state = FL_READY;
984 wake_up(&this->wq);
985 spin_unlock(&this->chip_lock);
986}
987
988/**
d15057b7
KP		 989 * onenand_transfer_auto_oob - [Internal] oob auto-placement transfer
990 * @param mtd MTD device structure
991 * @param buf destination address
992 * @param column oob offset to read from
993 * @param thislen oob length to read
994 */
995static int onenand_transfer_auto_oob(struct mtd_info *mtd, uint8_t *buf, int column,
996 int thislen)
997{
998 struct onenand_chip *this = mtd->priv;
999 struct nand_oobfree *free;
1000 int readcol = column;
1001 int readend = column + thislen;
1002 int lastgap = 0;
1003 unsigned int i;
1004 uint8_t *oob_buf = this->oob_buf;
1005
1006 free = this->ecclayout->oobfree;
1007 for (i = 0; i < MTD_MAX_OOBFREE_ENTRIES && free->length; i++, free++) {
1008 if (readcol >= lastgap)
1009 readcol += free->offset - lastgap;
1010 if (readend >= lastgap)
1011 readend += free->offset - lastgap;
1012 lastgap = free->offset + free->length;
1013 }
1014 this->read_bufferram(mtd, ONENAND_SPARERAM, oob_buf, 0, mtd->oobsize);
1015 free = this->ecclayout->oobfree;
1016 for (i = 0; i < MTD_MAX_OOBFREE_ENTRIES && free->length; i++, free++) {
1017 int free_end = free->offset + free->length;
1018 if (free->offset < readend && free_end > readcol) {
1019 int st = max_t(int,free->offset,readcol);
1020 int ed = min_t(int,free_end,readend);
1021 int n = ed - st;
1022 memcpy(buf, oob_buf + st, n);
1023 buf += n;
1024 } else if (column == 0)
1025 break;
1026 }
1027 return 0;
1028}
1029
5988af23
RH		 1030/**
1031 * onenand_recover_lsb - [Flex-OneNAND] Recover LSB page data
1032 * @param mtd MTD device structure
1033 * @param addr address to recover
1034 * @param status return value from onenand_wait / onenand_bbt_wait
1035 *
1036 * MLC NAND Flash cell has paired pages - LSB page and MSB page. LSB page has
1037 * lower page address and MSB page has higher page address in paired pages.
1038 * If power off occurs during MSB page program, the paired LSB page data can
1039 * become corrupt. LSB page recovery read is a way to read LSB page though page
1040 * data are corrupted. When uncorrectable error occurs as a result of LSB page
1041 * read after power up, issue LSB page recovery read.
1042 */
1043static int onenand_recover_lsb(struct mtd_info *mtd, loff_t addr, int status)
1044{
1045 struct onenand_chip *this = mtd->priv;
1046 int i;
1047
1048 /* Recovery is only for Flex-OneNAND */
1049 if (!FLEXONENAND(this))
1050 return status;
1051
1052 /* check if we failed due to uncorrectable error */
1053 if (status != -EBADMSG && status != ONENAND_BBT_READ_ECC_ERROR)
1054 return status;
1055
1056 /* check if address lies in MLC region */
1057 i = flexonenand_region(mtd, addr);
1058 if (mtd->eraseregions[i].erasesize < (1 << this->erase_shift))
1059 return status;
1060
1061 /* We are attempting to reread, so decrement stats.failed
1062 * which was incremented by onenand_wait due to read failure
1063 */
297758f8
AKS		 1064 printk(KERN_INFO "%s: Attempting to recover from uncorrectable read\n",
1065 __func__);
5988af23
RH		 1066 mtd->ecc_stats.failed--;
1067
1068 /* Issue the LSB page recovery command */
1069 this->command(mtd, FLEXONENAND_CMD_RECOVER_LSB, addr, this->writesize);
1070 return this->wait(mtd, FL_READING);
1071}
1072
1073/**
1074 * onenand_mlc_read_ops_nolock - MLC OneNAND read main and/or out-of-band
1075 * @param mtd MTD device structure
1076 * @param from offset to read from
1077 * @param ops: oob operation description structure
1078 *
1079 * MLC OneNAND / Flex-OneNAND has 4KB page size and 4KB dataram.
1080 * So, read-while-load is not present.
1081 */
1082static int onenand_mlc_read_ops_nolock(struct mtd_info *mtd, loff_t from,
1083 struct mtd_oob_ops *ops)
1084{
1085 struct onenand_chip *this = mtd->priv;
1086 struct mtd_ecc_stats stats;
1087 size_t len = ops->len;
1088 size_t ooblen = ops->ooblen;
1089 u_char *buf = ops->datbuf;
1090 u_char *oobbuf = ops->oobbuf;
1091 int read = 0, column, thislen;
1092 int oobread = 0, oobcolumn, thisooblen, oobsize;
1093 int ret = 0;
1094 int writesize = this->writesize;
1095
297758f8 1096 DEBUG(MTD_DEBUG_LEVEL3, "%s: from = 0x%08x, len = %i\n",
8032747e 1097 __func__, (unsigned int) from, (int) len);
5988af23
RH		 1098
1099 if (ops->mode == MTD_OOB_AUTO)
1100 oobsize = this->ecclayout->oobavail;
1101 else
1102 oobsize = mtd->oobsize;
1103
1104 oobcolumn = from & (mtd->oobsize - 1);
1105
1106 /* Do not allow reads past end of device */
1107 if (from + len > mtd->size) {
297758f8
AKS		 1108 printk(KERN_ERR "%s: Attempt read beyond end of device\n",
1109 __func__);
5988af23
RH		 1110 ops->retlen = 0;
1111 ops->oobretlen = 0;
1112 return -EINVAL;
1113 }
1114
1115 stats = mtd->ecc_stats;
1116
1117 while (read < len) {
1118 cond_resched();
1119
1120 thislen = min_t(int, writesize, len - read);
1121
1122 column = from & (writesize - 1);
1123 if (column + thislen > writesize)
1124 thislen = writesize - column;
1125
1126 if (!onenand_check_bufferram(mtd, from)) {
1127 this->command(mtd, ONENAND_CMD_READ, from, writesize);
1128
1129 ret = this->wait(mtd, FL_READING);
1130 if (unlikely(ret))
1131 ret = onenand_recover_lsb(mtd, from, ret);
1132 onenand_update_bufferram(mtd, from, !ret);
1133 if (ret == -EBADMSG)
1134 ret = 0;
1135 }
1136
1137 this->read_bufferram(mtd, ONENAND_DATARAM, buf, column, thislen);
1138 if (oobbuf) {
1139 thisooblen = oobsize - oobcolumn;
1140 thisooblen = min_t(int, thisooblen, ooblen - oobread);
1141
1142 if (ops->mode == MTD_OOB_AUTO)
1143 onenand_transfer_auto_oob(mtd, oobbuf, oobcolumn, thisooblen);
1144 else
1145 this->read_bufferram(mtd, ONENAND_SPARERAM, oobbuf, oobcolumn, thisooblen);
1146 oobread += thisooblen;
1147 oobbuf += thisooblen;
1148 oobcolumn = 0;
1149 }
1150
1151 read += thislen;
1152 if (read == len)
1153 break;
1154
1155 from += thislen;
1156 buf += thislen;
1157 }
1158
1159 /*
1160 * Return success, if no ECC failures, else -EBADMSG
1161 * fs driver will take care of that, because
1162 * retlen == desired len and result == -EBADMSG
1163 */
1164 ops->retlen = read;
1165 ops->oobretlen = oobread;
1166
1167 if (ret)
1168 return ret;
1169
1170 if (mtd->ecc_stats.failed - stats.failed)
1171 return -EBADMSG;
1172
1173 return mtd->ecc_stats.corrected - stats.corrected ? -EUCLEAN : 0;
1174}
1175
d15057b7 1176/**
49dc08ee 1177 * onenand_read_ops_nolock - [OneNAND Interface] OneNAND read main and/or out-of-band
cd5f6346
KP		 1178 * @param mtd MTD device structure
1179 * @param from offset to read from
d15057b7 1180 * @param ops: oob operation description structure
cd5f6346 1181 *
d15057b7
KP		 1182 * OneNAND read main and/or out-of-band data
1183 */
49dc08ee 1184static int onenand_read_ops_nolock(struct mtd_info *mtd, loff_t from,
d15057b7 1185 struct mtd_oob_ops *ops)
cd5f6346
KP		 1186{
1187 struct onenand_chip *this = mtd->priv;
f4f91ac3 1188 struct mtd_ecc_stats stats;
d15057b7
KP		 1189 size_t len = ops->len;
1190 size_t ooblen = ops->ooblen;
1191 u_char *buf = ops->datbuf;
1192 u_char *oobbuf = ops->oobbuf;
1193 int read = 0, column, thislen;
1194 int oobread = 0, oobcolumn, thisooblen, oobsize;
0fc2ccea 1195 int ret = 0, boundary = 0;
ee9745fc 1196 int writesize = this->writesize;
cd5f6346 1197
297758f8
AKS		 1198 DEBUG(MTD_DEBUG_LEVEL3, "%s: from = 0x%08x, len = %i\n",
1199 __func__, (unsigned int) from, (int) len);
d15057b7
KP		 1200
1201 if (ops->mode == MTD_OOB_AUTO)
1202 oobsize = this->ecclayout->oobavail;
1203 else
1204 oobsize = mtd->oobsize;
1205
1206 oobcolumn = from & (mtd->oobsize - 1);
cd5f6346
KP		 1207
1208 /* Do not allow reads past end of device */
1209 if ((from + len) > mtd->size) {
297758f8
AKS		 1210 printk(KERN_ERR "%s: Attempt read beyond end of device\n",
1211 __func__);
d15057b7
KP		 1212 ops->retlen = 0;
1213 ops->oobretlen = 0;
cd5f6346
KP		 1214 return -EINVAL;
1215 }
1216
f4f91ac3 1217 stats = mtd->ecc_stats;
61a7e198 1218
a8de85d5
AH		 1219 /* Read-while-load method */
1220
1221 /* Do first load to bufferRAM */
1222 if (read < len) {
1223 if (!onenand_check_bufferram(mtd, from)) {
ee9745fc 1224 this->command(mtd, ONENAND_CMD_READ, from, writesize);
a8de85d5
AH		 1225 ret = this->wait(mtd, FL_READING);
1226 onenand_update_bufferram(mtd, from, !ret);
5f4d47d5
AH		 1227 if (ret == -EBADMSG)
1228 ret = 0;
a8de85d5
AH		 1229 }
1230 }
1231
ee9745fc
KP		 1232 thislen = min_t(int, writesize, len - read);
1233 column = from & (writesize - 1);
1234 if (column + thislen > writesize)
1235 thislen = writesize - column;
a8de85d5
AH		 1236
1237 while (!ret) {
1238 /* If there is more to load then start next load */
1239 from += thislen;
1240 if (read + thislen < len) {
ee9745fc 1241 this->command(mtd, ONENAND_CMD_READ, from, writesize);
0fc2ccea
AH		 1242 /*
1243 * Chip boundary handling in DDP
1244 * Now we issued chip 1 read and pointed chip 1
492e1501 1245 * bufferram so we have to point chip 0 bufferram.
0fc2ccea 1246 */
738d61f5
KP		 1247 if (ONENAND_IS_DDP(this) &&
1248 unlikely(from == (this->chipsize >> 1))) {
1249 this->write_word(ONENAND_DDP_CHIP0, this->base + ONENAND_REG_START_ADDRESS2);
0fc2ccea
AH		 1250 boundary = 1;
1251 } else
1252 boundary = 0;
a8de85d5
AH		 1253 ONENAND_SET_PREV_BUFFERRAM(this);
1254 }
1255 /* While load is going, read from last bufferRAM */
1256 this->read_bufferram(mtd, ONENAND_DATARAM, buf, column, thislen);
d15057b7
KP		 1257
1258 /* Read oob area if needed */
1259 if (oobbuf) {
1260 thisooblen = oobsize - oobcolumn;
1261 thisooblen = min_t(int, thisooblen, ooblen - oobread);
1262
1263 if (ops->mode == MTD_OOB_AUTO)
1264 onenand_transfer_auto_oob(mtd, oobbuf, oobcolumn, thisooblen);
1265 else
1266 this->read_bufferram(mtd, ONENAND_SPARERAM, oobbuf, oobcolumn, thisooblen);
1267 oobread += thisooblen;
1268 oobbuf += thisooblen;
1269 oobcolumn = 0;
1270 }
1271
a8de85d5
AH		 1272 /* See if we are done */
1273 read += thislen;
1274 if (read == len)
1275 break;
1276 /* Set up for next read from bufferRAM */
0fc2ccea 1277 if (unlikely(boundary))
738d61f5 1278 this->write_word(ONENAND_DDP_CHIP1, this->base + ONENAND_REG_START_ADDRESS2);
a8de85d5
AH		 1279 ONENAND_SET_NEXT_BUFFERRAM(this);
1280 buf += thislen;
ee9745fc 1281 thislen = min_t(int, writesize, len - read);
a8de85d5
AH		 1282 column = 0;
1283 cond_resched();
1284 /* Now wait for load */
1285 ret = this->wait(mtd, FL_READING);
1286 onenand_update_bufferram(mtd, from, !ret);
5f4d47d5
AH		 1287 if (ret == -EBADMSG)
1288 ret = 0;
a8de85d5 1289 }
cd5f6346 1290
cd5f6346
KP		 1291 /*
1292 * Return success, if no ECC failures, else -EBADMSG
1293 * fs driver will take care of that, because
1294 * retlen == desired len and result == -EBADMSG
1295 */
d15057b7
KP		 1296 ops->retlen = read;
1297 ops->oobretlen = oobread;
f4f91ac3 1298
a8de85d5
AH		 1299 if (ret)
1300 return ret;
1301
5f4d47d5
AH		 1302 if (mtd->ecc_stats.failed - stats.failed)
1303 return -EBADMSG;
1304
f4f91ac3 1305 return mtd->ecc_stats.corrected - stats.corrected ? -EUCLEAN : 0;
cd5f6346
KP		 1306}
1307
cd5f6346 1308/**
49dc08ee 1309 * onenand_read_oob_nolock - [MTD Interface] OneNAND read out-of-band
cd5f6346
KP		 1310 * @param mtd MTD device structure
1311 * @param from offset to read from
d15057b7 1312 * @param ops: oob operation description structure
cd5f6346
KP		 1313 *
1314 * OneNAND read out-of-band data from the spare area
1315 */
49dc08ee 1316static int onenand_read_oob_nolock(struct mtd_info *mtd, loff_t from,
12f77c9e 1317 struct mtd_oob_ops *ops)
cd5f6346
KP		 1318{
1319 struct onenand_chip *this = mtd->priv;
5f4d47d5 1320 struct mtd_ecc_stats stats;
a5e7c7b4 1321 int read = 0, thislen, column, oobsize;
12f77c9e
KP		 1322 size_t len = ops->ooblen;
1323 mtd_oob_mode_t mode = ops->mode;
1324 u_char *buf = ops->oobbuf;
5988af23 1325 int ret = 0, readcmd;
cd5f6346 1326
12f77c9e
KP		 1327 from += ops->ooboffs;
1328
297758f8
AKS		 1329 DEBUG(MTD_DEBUG_LEVEL3, "%s: from = 0x%08x, len = %i\n",
1330 __func__, (unsigned int) from, (int) len);
cd5f6346
KP		 1331
1332 /* Initialize return length value */
12f77c9e 1333 ops->oobretlen = 0;
cd5f6346 1334
a5e7c7b4
AH		 1335 if (mode == MTD_OOB_AUTO)
1336 oobsize = this->ecclayout->oobavail;
1337 else
1338 oobsize = mtd->oobsize;
1339
1340 column = from & (mtd->oobsize - 1);
1341
1342 if (unlikely(column >= oobsize)) {
297758f8
AKS		 1343 printk(KERN_ERR "%s: Attempted to start read outside oob\n",
1344 __func__);
a5e7c7b4
AH		 1345 return -EINVAL;
1346 }
1347
cd5f6346 1348 /* Do not allow reads past end of device */
a5e7c7b4
AH		 1349 if (unlikely(from >= mtd->size ||
1350 column + len > ((mtd->size >> this->page_shift) -
1351 (from >> this->page_shift)) * oobsize)) {
297758f8
AKS		 1352 printk(KERN_ERR "%s: Attempted to read beyond end of device\n",
1353 __func__);
cd5f6346
KP		 1354 return -EINVAL;
1355 }
1356
5f4d47d5
AH		 1357 stats = mtd->ecc_stats;
1358
8a8f632d 1359 readcmd = ONENAND_IS_4KB_PAGE(this) ? ONENAND_CMD_READ : ONENAND_CMD_READOOB;
5988af23 1360
cd5f6346 1361 while (read < len) {
61a7e198
AB		 1362 cond_resched();
1363
a5e7c7b4 1364 thislen = oobsize - column;
cd5f6346
KP		 1365 thislen = min_t(int, thislen, len);
1366
5988af23 1367 this->command(mtd, readcmd, from, mtd->oobsize);
cd5f6346
KP		 1368
1369 onenand_update_bufferram(mtd, from, 0);
1370
1371 ret = this->wait(mtd, FL_READING);
5988af23
RH		 1372 if (unlikely(ret))
1373 ret = onenand_recover_lsb(mtd, from, ret);
1374
5f4d47d5 1375 if (ret && ret != -EBADMSG) {
297758f8
AKS		 1376 printk(KERN_ERR "%s: read failed = 0x%x\n",
1377 __func__, ret);
5f4d47d5
AH		 1378 break;
1379 }
cd5f6346 1380
a5e7c7b4
AH		 1381 if (mode == MTD_OOB_AUTO)
1382 onenand_transfer_auto_oob(mtd, buf, column, thislen);
1383 else
1384 this->read_bufferram(mtd, ONENAND_SPARERAM, buf, column, thislen);
cd5f6346
KP		 1385
1386 read += thislen;
1387
1388 if (read == len)
1389 break;
1390
cd5f6346
KP		 1391 buf += thislen;
1392
1393 /* Read more? */
1394 if (read < len) {
1395 /* Page size */
28318776 1396 from += mtd->writesize;
cd5f6346
KP		 1397 column = 0;
1398 }
1399 }
1400
12f77c9e 1401 ops->oobretlen = read;
5f4d47d5
AH		 1402
1403 if (ret)
1404 return ret;
1405
1406 if (mtd->ecc_stats.failed - stats.failed)
1407 return -EBADMSG;
1408
1409 return 0;
cd5f6346
KP		 1410}
1411
8593fbc6 1412/**
d15057b7
KP		 1413 * onenand_read - [MTD Interface] Read data from flash
1414 * @param mtd MTD device structure
1415 * @param from offset to read from
1416 * @param len number of bytes to read
1417 * @param retlen pointer to variable to store the number of read bytes
1418 * @param buf the databuffer to put data
1419 *
1420 * Read with ecc
1421*/
1422static int onenand_read(struct mtd_info *mtd, loff_t from, size_t len,
1423 size_t *retlen, u_char *buf)
1424{
5988af23 1425 struct onenand_chip *this = mtd->priv;
d15057b7
KP		 1426 struct mtd_oob_ops ops = {
1427 .len = len,
1428 .ooblen = 0,
1429 .datbuf = buf,
1430 .oobbuf = NULL,
1431 };
1432 int ret;
1433
49dc08ee 1434 onenand_get_device(mtd, FL_READING);
8a8f632d 1435 ret = ONENAND_IS_4KB_PAGE(this) ?
5988af23
RH		 1436 onenand_mlc_read_ops_nolock(mtd, from, &ops) :
1437 onenand_read_ops_nolock(mtd, from, &ops);
49dc08ee 1438 onenand_release_device(mtd);
d15057b7 1439
49dc08ee 1440 *retlen = ops.retlen;
d15057b7
KP		 1441 return ret;
1442}
1443
1444/**
1445 * onenand_read_oob - [MTD Interface] Read main and/or out-of-band
e3da8067
KP		 1446 * @param mtd: MTD device structure
1447 * @param from: offset to read from
1448 * @param ops: oob operation description structure
d15057b7
KP		 1449
1450 * Read main and/or out-of-band
8593fbc6
TG		 1451 */
1452static int onenand_read_oob(struct mtd_info *mtd, loff_t from,
1453 struct mtd_oob_ops *ops)
1454{
5988af23 1455 struct onenand_chip *this = mtd->priv;
49dc08ee
AB		 1456 int ret;
1457
4f4fad27 1458 switch (ops->mode) {
a5e7c7b4
AH		 1459 case MTD_OOB_PLACE:
1460 case MTD_OOB_AUTO:
1461 break;
1462 case MTD_OOB_RAW:
4f4fad27 1463 /* Not implemented yet */
a5e7c7b4
AH		 1464 default:
1465 return -EINVAL;
1466 }
d15057b7 1467
49dc08ee 1468 onenand_get_device(mtd, FL_READING);
d15057b7 1469 if (ops->datbuf)
8a8f632d 1470 ret = ONENAND_IS_4KB_PAGE(this) ?
5988af23
RH		 1471 onenand_mlc_read_ops_nolock(mtd, from, ops) :
1472 onenand_read_ops_nolock(mtd, from, ops);
49dc08ee
AB		 1473 else
1474 ret = onenand_read_oob_nolock(mtd, from, ops);
1475 onenand_release_device(mtd);
d15057b7 1476
49dc08ee 1477 return ret;
8593fbc6
TG		 1478}
1479
211ac75f
KP		 1480/**
1481 * onenand_bbt_wait - [DEFAULT] wait until the command is done
1482 * @param mtd MTD device structure
1483 * @param state state to select the max. timeout value
1484 *
1485 * Wait for command done.
1486 */
1487static int onenand_bbt_wait(struct mtd_info *mtd, int state)
1488{
1489 struct onenand_chip *this = mtd->priv;
1490 unsigned long timeout;
e0c1a921 1491 unsigned int interrupt, ctrl, ecc, addr1, addr8;
211ac75f
KP		 1492
1493 /* The 20 msec is enough */
1494 timeout = jiffies + msecs_to_jiffies(20);
1495 while (time_before(jiffies, timeout)) {
1496 interrupt = this->read_word(this->base + ONENAND_REG_INTERRUPT);
1497 if (interrupt & ONENAND_INT_MASTER)
1498 break;
1499 }
1500 /* To get correct interrupt status in timeout case */
1501 interrupt = this->read_word(this->base + ONENAND_REG_INTERRUPT);
1502 ctrl = this->read_word(this->base + ONENAND_REG_CTRL_STATUS);
e0c1a921
AH		 1503 addr1 = this->read_word(this->base + ONENAND_REG_START_ADDRESS1);
1504 addr8 = this->read_word(this->base + ONENAND_REG_START_ADDRESS8);
211ac75f 1505
211ac75f 1506 if (interrupt & ONENAND_INT_READ) {
e0c1a921 1507 ecc = onenand_read_ecc(this);
83973b87 1508 if (ecc & ONENAND_ECC_2BIT_ALL) {
e0c1a921
AH		 1509 printk(KERN_DEBUG "%s: ecc 0x%04x ctrl 0x%04x "
1510 "intr 0x%04x addr1 %#x addr8 %#x\n",
1511 __func__, ecc, ctrl, interrupt, addr1, addr8);
5988af23 1512 return ONENAND_BBT_READ_ECC_ERROR;
83973b87 1513 }
211ac75f 1514 } else {
e0c1a921
AH		 1515 printk(KERN_ERR "%s: read timeout! ctrl 0x%04x "
1516 "intr 0x%04x addr1 %#x addr8 %#x\n",
1517 __func__, ctrl, interrupt, addr1, addr8);
211ac75f
KP		 1518 return ONENAND_BBT_READ_FATAL_ERROR;
1519 }
1520
83973b87
KP		 1521 /* Initial bad block case: 0x2400 or 0x0400 */
1522 if (ctrl & ONENAND_CTRL_ERROR) {
e0c1a921
AH		 1523 printk(KERN_DEBUG "%s: ctrl 0x%04x intr 0x%04x addr1 %#x "
1524 "addr8 %#x\n", __func__, ctrl, interrupt, addr1, addr8);
83973b87
KP		 1525 return ONENAND_BBT_READ_ERROR;
1526 }
1527
211ac75f
KP		 1528 return 0;
1529}
1530
1531/**
1532 * onenand_bbt_read_oob - [MTD Interface] OneNAND read out-of-band for bbt scan
1533 * @param mtd MTD device structure
1534 * @param from offset to read from
e3da8067 1535 * @param ops oob operation description structure
211ac75f
KP		 1536 *
1537 * OneNAND read out-of-band data from the spare area for bbt scan
1538 */
1539int onenand_bbt_read_oob(struct mtd_info *mtd, loff_t from,
1540 struct mtd_oob_ops *ops)
1541{
1542 struct onenand_chip *this = mtd->priv;
1543 int read = 0, thislen, column;
5988af23 1544 int ret = 0, readcmd;
211ac75f
KP		 1545 size_t len = ops->ooblen;
1546 u_char *buf = ops->oobbuf;
1547
297758f8
AKS		 1548 DEBUG(MTD_DEBUG_LEVEL3, "%s: from = 0x%08x, len = %zi\n",
1549 __func__, (unsigned int) from, len);
211ac75f
KP		 1550
1551 /* Initialize return value */
1552 ops->oobretlen = 0;
1553
1554 /* Do not allow reads past end of device */
1555 if (unlikely((from + len) > mtd->size)) {
297758f8
AKS		 1556 printk(KERN_ERR "%s: Attempt read beyond end of device\n",
1557 __func__);
211ac75f
KP		 1558 return ONENAND_BBT_READ_FATAL_ERROR;
1559 }
1560
1561 /* Grab the lock and see if the device is available */
1562 onenand_get_device(mtd, FL_READING);
1563
1564 column = from & (mtd->oobsize - 1);
1565
8a8f632d 1566 readcmd = ONENAND_IS_4KB_PAGE(this) ? ONENAND_CMD_READ : ONENAND_CMD_READOOB;
5988af23 1567
211ac75f
KP		 1568 while (read < len) {
1569 cond_resched();
1570
1571 thislen = mtd->oobsize - column;
1572 thislen = min_t(int, thislen, len);
1573
5988af23 1574 this->command(mtd, readcmd, from, mtd->oobsize);
211ac75f
KP		 1575
1576 onenand_update_bufferram(mtd, from, 0);
1577
31bb999e 1578 ret = this->bbt_wait(mtd, FL_READING);
5988af23
RH		 1579 if (unlikely(ret))
1580 ret = onenand_recover_lsb(mtd, from, ret);
1581
211ac75f
KP		 1582 if (ret)
1583 break;
1584
1585 this->read_bufferram(mtd, ONENAND_SPARERAM, buf, column, thislen);
1586 read += thislen;
1587 if (read == len)
1588 break;
1589
1590 buf += thislen;
1591
1592 /* Read more? */
1593 if (read < len) {
1594 /* Update Page size */
ee9745fc 1595 from += this->writesize;
211ac75f
KP		 1596 column = 0;
1597 }
1598 }
1599
1600 /* Deselect and wake up anyone waiting on the device */
1601 onenand_release_device(mtd);
1602
1603 ops->oobretlen = read;
1604 return ret;
1605}
1606
cd5f6346 1607#ifdef CONFIG_MTD_ONENAND_VERIFY_WRITE
8e6ec690
KP		 1608/**
1609 * onenand_verify_oob - [GENERIC] verify the oob contents after a write
1610 * @param mtd MTD device structure
1611 * @param buf the databuffer to verify
1612 * @param to offset to read from
8e6ec690 1613 */
a5e7c7b4 1614static int onenand_verify_oob(struct mtd_info *mtd, const u_char *buf, loff_t to)
8e6ec690
KP		 1615{
1616 struct onenand_chip *this = mtd->priv;
69d79186 1617 u_char *oob_buf = this->oob_buf;
5988af23
RH		 1618 int status, i, readcmd;
1619
8a8f632d 1620 readcmd = ONENAND_IS_4KB_PAGE(this) ? ONENAND_CMD_READ : ONENAND_CMD_READOOB;
8e6ec690 1621
5988af23 1622 this->command(mtd, readcmd, to, mtd->oobsize);
8e6ec690
KP		 1623 onenand_update_bufferram(mtd, to, 0);
1624 status = this->wait(mtd, FL_READING);
1625 if (status)
1626 return status;
1627
69d79186 1628 this->read_bufferram(mtd, ONENAND_SPARERAM, oob_buf, 0, mtd->oobsize);
91014e9b 1629 for (i = 0; i < mtd->oobsize; i++)
69d79186 1630 if (buf[i] != 0xFF && buf[i] != oob_buf[i])
8e6ec690
KP		 1631 return -EBADMSG;
1632
1633 return 0;
1634}
1635
cd5f6346 1636/**
8b29c0b6
AH		 1637 * onenand_verify - [GENERIC] verify the chip contents after a write
1638 * @param mtd MTD device structure
1639 * @param buf the databuffer to verify
1640 * @param addr offset to read from
1641 * @param len number of bytes to read and compare
cd5f6346 1642 */
8b29c0b6 1643static int onenand_verify(struct mtd_info *mtd, const u_char *buf, loff_t addr, size_t len)
cd5f6346
KP		 1644{
1645 struct onenand_chip *this = mtd->priv;
cd5f6346 1646 int ret = 0;
8b29c0b6 1647 int thislen, column;
cd5f6346 1648
8b29c0b6 1649 while (len != 0) {
ee9745fc
KP		 1650 thislen = min_t(int, this->writesize, len);
1651 column = addr & (this->writesize - 1);
1652 if (column + thislen > this->writesize)
1653 thislen = this->writesize - column;
60d84f97 1654
ee9745fc 1655 this->command(mtd, ONENAND_CMD_READ, addr, this->writesize);
cd5f6346 1656
8b29c0b6
AH		 1657 onenand_update_bufferram(mtd, addr, 0);
1658
1659 ret = this->wait(mtd, FL_READING);
1660 if (ret)
1661 return ret;
cd5f6346 1662
8b29c0b6 1663 onenand_update_bufferram(mtd, addr, 1);
cd5f6346 1664
3328dc31 1665 this->read_bufferram(mtd, ONENAND_DATARAM, this->verify_buf, 0, mtd->writesize);
cd5f6346 1666
3328dc31 1667 if (memcmp(buf, this->verify_buf, thislen))
8b29c0b6
AH		 1668 return -EBADMSG;
1669
1670 len -= thislen;
1671 buf += thislen;
1672 addr += thislen;
1673 }
d5c5e78a 1674
cd5f6346
KP		 1675 return 0;
1676}
1677#else
8b29c0b6 1678#define onenand_verify(...) (0)
8e6ec690 1679#define onenand_verify_oob(...) (0)
cd5f6346
KP		 1680#endif
1681
60d84f97 1682#define NOTALIGNED(x) ((x & (this->subpagesize - 1)) != 0)
cd5f6346 1683
6c77fd64
RP		 1684static void onenand_panic_wait(struct mtd_info *mtd)
1685{
1686 struct onenand_chip *this = mtd->priv;
1687 unsigned int interrupt;
1688 int i;
1689
1690 for (i = 0; i < 2000; i++) {
1691 interrupt = this->read_word(this->base + ONENAND_REG_INTERRUPT);
1692 if (interrupt & ONENAND_INT_MASTER)
1693 break;
1694 udelay(10);
1695 }
1696}
1697
1698/**
1699 * onenand_panic_write - [MTD Interface] write buffer to FLASH in a panic context
1700 * @param mtd MTD device structure
1701 * @param to offset to write to
1702 * @param len number of bytes to write
1703 * @param retlen pointer to variable to store the number of written bytes
1704 * @param buf the data to write
1705 *
1706 * Write with ECC
1707 */
1708static int onenand_panic_write(struct mtd_info *mtd, loff_t to, size_t len,
1709 size_t *retlen, const u_char *buf)
1710{
1711 struct onenand_chip *this = mtd->priv;
1712 int column, subpage;
1713 int written = 0;
1714 int ret = 0;
1715
1716 if (this->state == FL_PM_SUSPENDED)
1717 return -EBUSY;
1718
1719 /* Wait for any existing operation to clear */
1720 onenand_panic_wait(mtd);
1721
297758f8
AKS		 1722 DEBUG(MTD_DEBUG_LEVEL3, "%s: to = 0x%08x, len = %i\n",
1723 __func__, (unsigned int) to, (int) len);
6c77fd64
RP		 1724
1725 /* Initialize retlen, in case of early exit */
1726 *retlen = 0;
1727
1728 /* Do not allow writes past end of device */
1729 if (unlikely((to + len) > mtd->size)) {
297758f8
AKS		 1730 printk(KERN_ERR "%s: Attempt write to past end of device\n",
1731 __func__);
6c77fd64
RP		 1732 return -EINVAL;
1733 }
1734
1735 /* Reject writes, which are not page aligned */
b73d7e43 1736 if (unlikely(NOTALIGNED(to) || NOTALIGNED(len))) {
297758f8
AKS		 1737 printk(KERN_ERR "%s: Attempt to write not page aligned data\n",
1738 __func__);
6c77fd64
RP		 1739 return -EINVAL;
1740 }
1741
1742 column = to & (mtd->writesize - 1);
1743
1744 /* Loop until all data write */
1745 while (written < len) {
1746 int thislen = min_t(int, mtd->writesize - column, len - written);
1747 u_char *wbuf = (u_char *) buf;
1748
1749 this->command(mtd, ONENAND_CMD_BUFFERRAM, to, thislen);
1750
1751 /* Partial page write */
1752 subpage = thislen < mtd->writesize;
1753 if (subpage) {
1754 memset(this->page_buf, 0xff, mtd->writesize);
1755 memcpy(this->page_buf + column, buf, thislen);
1756 wbuf = this->page_buf;
1757 }
1758
1759 this->write_bufferram(mtd, ONENAND_DATARAM, wbuf, 0, mtd->writesize);
1760 this->write_bufferram(mtd, ONENAND_SPARERAM, ffchars, 0, mtd->oobsize);
1761
1762 this->command(mtd, ONENAND_CMD_PROG, to, mtd->writesize);
1763
1764 onenand_panic_wait(mtd);
1765
1766 /* In partial page write we don't update bufferram */
1767 onenand_update_bufferram(mtd, to, !ret && !subpage);
1768 if (ONENAND_IS_2PLANE(this)) {
1769 ONENAND_SET_BUFFERRAM1(this);
1770 onenand_update_bufferram(mtd, to + this->writesize, !ret && !subpage);
1771 }
1772
1773 if (ret) {
297758f8 1774 printk(KERN_ERR "%s: write failed %d\n", __func__, ret);
6c77fd64
RP		 1775 break;
1776 }
1777
1778 written += thislen;
1779
1780 if (written == len)
1781 break;
1782
1783 column = 0;
1784 to += thislen;
1785 buf += thislen;
1786 }
1787
1788 *retlen = written;
1789 return ret;
1790}
1791
cd5f6346 1792/**
d15057b7
KP		 1793 * onenand_fill_auto_oob - [Internal] oob auto-placement transfer
1794 * @param mtd MTD device structure
1795 * @param oob_buf oob buffer
1796 * @param buf source address
1797 * @param column oob offset to write to
1798 * @param thislen oob length to write
1799 */
1800static int onenand_fill_auto_oob(struct mtd_info *mtd, u_char *oob_buf,
1801 const u_char *buf, int column, int thislen)
1802{
1803 struct onenand_chip *this = mtd->priv;
1804 struct nand_oobfree *free;
1805 int writecol = column;
1806 int writeend = column + thislen;
1807 int lastgap = 0;
1808 unsigned int i;
1809
1810 free = this->ecclayout->oobfree;
1811 for (i = 0; i < MTD_MAX_OOBFREE_ENTRIES && free->length; i++, free++) {
1812 if (writecol >= lastgap)
1813 writecol += free->offset - lastgap;
1814 if (writeend >= lastgap)
1815 writeend += free->offset - lastgap;
1816 lastgap = free->offset + free->length;
1817 }
1818 free = this->ecclayout->oobfree;
1819 for (i = 0; i < MTD_MAX_OOBFREE_ENTRIES && free->length; i++, free++) {
1820 int free_end = free->offset + free->length;
1821 if (free->offset < writeend && free_end > writecol) {
1822 int st = max_t(int,free->offset,writecol);
1823 int ed = min_t(int,free_end,writeend);
1824 int n = ed - st;
1825 memcpy(oob_buf + st, buf, n);
1826 buf += n;
1827 } else if (column == 0)
1828 break;
1829 }
1830 return 0;
1831}
1832
1833/**
49dc08ee 1834 * onenand_write_ops_nolock - [OneNAND Interface] write main and/or out-of-band
cd5f6346
KP		 1835 * @param mtd MTD device structure
1836 * @param to offset to write to
d15057b7 1837 * @param ops oob operation description structure
cd5f6346 1838 *
d15057b7 1839 * Write main and/or oob with ECC
cd5f6346 1840 */
49dc08ee 1841static int onenand_write_ops_nolock(struct mtd_info *mtd, loff_t to,
d15057b7 1842 struct mtd_oob_ops *ops)
cd5f6346
KP		 1843{
1844 struct onenand_chip *this = mtd->priv;
9ce96908
KP		 1845 int written = 0, column, thislen = 0, subpage = 0;
1846 int prev = 0, prevlen = 0, prev_subpage = 0, first = 1;
d15057b7
KP		 1847 int oobwritten = 0, oobcolumn, thisooblen, oobsize;
1848 size_t len = ops->len;
1849 size_t ooblen = ops->ooblen;
1850 const u_char *buf = ops->datbuf;
1851 const u_char *oob = ops->oobbuf;
1852 u_char *oobbuf;
ac80dac0 1853 int ret = 0, cmd;
cd5f6346 1854
297758f8
AKS		 1855 DEBUG(MTD_DEBUG_LEVEL3, "%s: to = 0x%08x, len = %i\n",
1856 __func__, (unsigned int) to, (int) len);
cd5f6346
KP		 1857
1858 /* Initialize retlen, in case of early exit */
d15057b7
KP		 1859 ops->retlen = 0;
1860 ops->oobretlen = 0;
cd5f6346
KP		 1861
1862 /* Do not allow writes past end of device */
1863 if (unlikely((to + len) > mtd->size)) {
297758f8
AKS		 1864 printk(KERN_ERR "%s: Attempt write to past end of device\n",
1865 __func__);
cd5f6346
KP		 1866 return -EINVAL;
1867 }
1868
1869 /* Reject writes, which are not page aligned */
b73d7e43 1870 if (unlikely(NOTALIGNED(to) || NOTALIGNED(len))) {
297758f8
AKS		 1871 printk(KERN_ERR "%s: Attempt to write not page aligned data\n",
1872 __func__);
cd5f6346
KP		 1873 return -EINVAL;
1874 }
1875
9ce96908
KP		 1876 /* Check zero length */
1877 if (!len)
1878 return 0;
1879
d15057b7
KP		 1880 if (ops->mode == MTD_OOB_AUTO)
1881 oobsize = this->ecclayout->oobavail;
1882 else
1883 oobsize = mtd->oobsize;
1884
1885 oobcolumn = to & (mtd->oobsize - 1);
1886
60d84f97 1887 column = to & (mtd->writesize - 1);
60d84f97 1888
cd5f6346 1889 /* Loop until all data write */
9ce96908
KP		 1890 while (1) {
1891 if (written < len) {
1892 u_char *wbuf = (u_char *) buf;
60d84f97 1893
9ce96908
KP		 1894 thislen = min_t(int, mtd->writesize - column, len - written);
1895 thisooblen = min_t(int, oobsize - oobcolumn, ooblen - oobwritten);
d15057b7 1896
9ce96908 1897 cond_resched();
61a7e198 1898
9ce96908 1899 this->command(mtd, ONENAND_CMD_BUFFERRAM, to, thislen);
60d84f97 1900
9ce96908
KP		 1901 /* Partial page write */
1902 subpage = thislen < mtd->writesize;
1903 if (subpage) {
1904 memset(this->page_buf, 0xff, mtd->writesize);
1905 memcpy(this->page_buf + column, buf, thislen);
1906 wbuf = this->page_buf;
1907 }
cd5f6346 1908
9ce96908 1909 this->write_bufferram(mtd, ONENAND_DATARAM, wbuf, 0, mtd->writesize);
d15057b7 1910
9ce96908
KP		 1911 if (oob) {
1912 oobbuf = this->oob_buf;
d15057b7 1913
9ce96908
KP		 1914 /* We send data to spare ram with oobsize
1915 * to prevent byte access */
1916 memset(oobbuf, 0xff, mtd->oobsize);
1917 if (ops->mode == MTD_OOB_AUTO)
1918 onenand_fill_auto_oob(mtd, oobbuf, oob, oobcolumn, thisooblen);
1919 else
1920 memcpy(oobbuf + oobcolumn, oob, thisooblen);
d15057b7 1921
9ce96908
KP		 1922 oobwritten += thisooblen;
1923 oob += thisooblen;
1924 oobcolumn = 0;
1925 } else
1926 oobbuf = (u_char *) ffchars;
1927
1928 this->write_bufferram(mtd, ONENAND_SPARERAM, oobbuf, 0, mtd->oobsize);
d15057b7 1929 } else
9ce96908 1930 ONENAND_SET_NEXT_BUFFERRAM(this);
d15057b7 1931
9ce96908 1932 /*
492e1501
MK		 1933 * 2 PLANE, MLC, and Flex-OneNAND do not support
1934 * write-while-program feature.
9ce96908 1935 */
6a88c47b 1936 if (!ONENAND_IS_2PLANE(this) && !ONENAND_IS_4KB_PAGE(this) && !first) {
9ce96908
KP		 1937 ONENAND_SET_PREV_BUFFERRAM(this);
1938
1939 ret = this->wait(mtd, FL_WRITING);
1940
1941 /* In partial page write we don't update bufferram */
1942 onenand_update_bufferram(mtd, prev, !ret && !prev_subpage);
1943 if (ret) {
1944 written -= prevlen;
297758f8
AKS		 1945 printk(KERN_ERR "%s: write failed %d\n",
1946 __func__, ret);
9ce96908
KP		 1947 break;
1948 }
cd5f6346 1949
9ce96908
KP		 1950 if (written == len) {
1951 /* Only check verify write turn on */
1952 ret = onenand_verify(mtd, buf - len, to - len, len);
1953 if (ret)
297758f8
AKS		 1954 printk(KERN_ERR "%s: verify failed %d\n",
1955 __func__, ret);
9ce96908
KP		 1956 break;
1957 }
cd5f6346 1958
9ce96908
KP		 1959 ONENAND_SET_NEXT_BUFFERRAM(this);
1960 }
81f38e11 1961
ac80dac0
RT		 1962 this->ongoing = 0;
1963 cmd = ONENAND_CMD_PROG;
1964
1965 /* Exclude 1st OTP and OTP blocks for cache program feature */
1966 if (ONENAND_IS_CACHE_PROGRAM(this) &&
1967 likely(onenand_block(this, to) != 0) &&
1968 ONENAND_IS_4KB_PAGE(this) &&
1969 ((written + thislen) < len)) {
1970 cmd = ONENAND_CMD_2X_CACHE_PROG;
1971 this->ongoing = 1;
1972 }
1973
1974 this->command(mtd, cmd, to, mtd->writesize);
9ce96908
KP		 1975
1976 /*
1977 * 2 PLANE, MLC, and Flex-OneNAND wait here
1978 */
6a88c47b 1979 if (ONENAND_IS_2PLANE(this) || ONENAND_IS_4KB_PAGE(this)) {
9ce96908 1980 ret = this->wait(mtd, FL_WRITING);
cd5f6346 1981
9ce96908
KP		 1982 /* In partial page write we don't update bufferram */
1983 onenand_update_bufferram(mtd, to, !ret && !subpage);
1984 if (ret) {
297758f8
AKS		 1985 printk(KERN_ERR "%s: write failed %d\n",
1986 __func__, ret);
9ce96908
KP		 1987 break;
1988 }
cd5f6346 1989
9ce96908
KP		 1990 /* Only check verify write turn on */
1991 ret = onenand_verify(mtd, buf, to, thislen);
1992 if (ret) {
297758f8
AKS		 1993 printk(KERN_ERR "%s: verify failed %d\n",
1994 __func__, ret);
9ce96908
KP		 1995 break;
1996 }
cd5f6346 1997
9ce96908 1998 written += thislen;
81f38e11 1999
9ce96908
KP		 2000 if (written == len)
2001 break;
2002
2003 } else
2004 written += thislen;
cd5f6346 2005
60d84f97 2006 column = 0;
9ce96908
KP		 2007 prev_subpage = subpage;
2008 prev = to;
2009 prevlen = thislen;
cd5f6346
KP		 2010 to += thislen;
2011 buf += thislen;
9ce96908 2012 first = 0;
cd5f6346
KP		 2013 }
2014
9ce96908
KP		 2015 /* In error case, clear all bufferrams */
2016 if (written != len)
2017 onenand_invalidate_bufferram(mtd, 0, -1);
2018
d15057b7 2019 ops->retlen = written;
9ce96908 2020 ops->oobretlen = oobwritten;
d5c5e78a 2021
cd5f6346
KP		 2022 return ret;
2023}
2024
a5e7c7b4 2025
cd5f6346 2026/**
49dc08ee 2027 * onenand_write_oob_nolock - [Internal] OneNAND write out-of-band
cd5f6346
KP		 2028 * @param mtd MTD device structure
2029 * @param to offset to write to
2030 * @param len number of bytes to write
2031 * @param retlen pointer to variable to store the number of written bytes
2032 * @param buf the data to write
a5e7c7b4 2033 * @param mode operation mode
cd5f6346
KP		 2034 *
2035 * OneNAND write out-of-band
2036 */
49dc08ee
AB		 2037static int onenand_write_oob_nolock(struct mtd_info *mtd, loff_t to,
2038 struct mtd_oob_ops *ops)
cd5f6346
KP		 2039{
2040 struct onenand_chip *this = mtd->priv;
a5e7c7b4 2041 int column, ret = 0, oobsize;
5988af23 2042 int written = 0, oobcmd;
91014e9b 2043 u_char *oobbuf;
12f77c9e
KP		 2044 size_t len = ops->ooblen;
2045 const u_char *buf = ops->oobbuf;
2046 mtd_oob_mode_t mode = ops->mode;
2047
2048 to += ops->ooboffs;
cd5f6346 2049
297758f8
AKS		 2050 DEBUG(MTD_DEBUG_LEVEL3, "%s: to = 0x%08x, len = %i\n",
2051 __func__, (unsigned int) to, (int) len);
cd5f6346
KP		 2052
2053 /* Initialize retlen, in case of early exit */
12f77c9e 2054 ops->oobretlen = 0;
cd5f6346 2055
a5e7c7b4
AH		 2056 if (mode == MTD_OOB_AUTO)
2057 oobsize = this->ecclayout->oobavail;
2058 else
2059 oobsize = mtd->oobsize;
2060
2061 column = to & (mtd->oobsize - 1);
2062
2063 if (unlikely(column >= oobsize)) {
297758f8
AKS		 2064 printk(KERN_ERR "%s: Attempted to start write outside oob\n",
2065 __func__);
a5e7c7b4
AH		 2066 return -EINVAL;
2067 }
2068
52e4200a 2069 /* For compatibility with NAND: Do not allow write past end of page */
91014e9b 2070 if (unlikely(column + len > oobsize)) {
297758f8
AKS		 2071 printk(KERN_ERR "%s: Attempt to write past end of page\n",
2072 __func__);
52e4200a
AH		 2073 return -EINVAL;
2074 }
2075
a5e7c7b4
AH		 2076 /* Do not allow reads past end of device */
2077 if (unlikely(to >= mtd->size ||
2078 column + len > ((mtd->size >> this->page_shift) -
2079 (to >> this->page_shift)) * oobsize)) {
8032747e
DW		 2080 printk(KERN_ERR "%s: Attempted to write past end of device\n",
2081 __func__);
cd5f6346
KP		 2082 return -EINVAL;
2083 }
2084
470bc844 2085 oobbuf = this->oob_buf;
91014e9b 2086
8a8f632d 2087 oobcmd = ONENAND_IS_4KB_PAGE(this) ? ONENAND_CMD_PROG : ONENAND_CMD_PROGOOB;
5988af23 2088
cd5f6346
KP		 2089 /* Loop until all data write */
2090 while (written < len) {
a5e7c7b4 2091 int thislen = min_t(int, oobsize, len - written);
cd5f6346 2092
61a7e198
AB		 2093 cond_resched();
2094
cd5f6346
KP		 2095 this->command(mtd, ONENAND_CMD_BUFFERRAM, to, mtd->oobsize);
2096
34c10609
KP		 2097 /* We send data to spare ram with oobsize
2098 * to prevent byte access */
91014e9b 2099 memset(oobbuf, 0xff, mtd->oobsize);
a5e7c7b4 2100 if (mode == MTD_OOB_AUTO)
91014e9b 2101 onenand_fill_auto_oob(mtd, oobbuf, buf, column, thislen);
a5e7c7b4 2102 else
91014e9b
KP		 2103 memcpy(oobbuf + column, buf, thislen);
2104 this->write_bufferram(mtd, ONENAND_SPARERAM, oobbuf, 0, mtd->oobsize);
cd5f6346 2105
8a8f632d 2106 if (ONENAND_IS_4KB_PAGE(this)) {
5988af23
RH		 2107 /* Set main area of DataRAM to 0xff*/
2108 memset(this->page_buf, 0xff, mtd->writesize);
2109 this->write_bufferram(mtd, ONENAND_DATARAM,
2110 this->page_buf, 0, mtd->writesize);
2111 }
2112
2113 this->command(mtd, oobcmd, to, mtd->oobsize);
cd5f6346
KP		 2114
2115 onenand_update_bufferram(mtd, to, 0);
ee9745fc
KP		 2116 if (ONENAND_IS_2PLANE(this)) {
2117 ONENAND_SET_BUFFERRAM1(this);
2118 onenand_update_bufferram(mtd, to + this->writesize, 0);
2119 }
cd5f6346 2120
8e6ec690
KP		 2121 ret = this->wait(mtd, FL_WRITING);
2122 if (ret) {
297758f8 2123 printk(KERN_ERR "%s: write failed %d\n", __func__, ret);
5b4246f1 2124 break;
8e6ec690
KP		 2125 }
2126
91014e9b 2127 ret = onenand_verify_oob(mtd, oobbuf, to);
8e6ec690 2128 if (ret) {
297758f8
AKS		 2129 printk(KERN_ERR "%s: verify failed %d\n",
2130 __func__, ret);
5b4246f1 2131 break;
8e6ec690 2132 }
cd5f6346
KP		 2133
2134 written += thislen;
cd5f6346
KP		 2135 if (written == len)
2136 break;
2137
a5e7c7b4 2138 to += mtd->writesize;
cd5f6346 2139 buf += thislen;
a5e7c7b4 2140 column = 0;
cd5f6346
KP		 2141 }
2142
12f77c9e 2143 ops->oobretlen = written;
d5c5e78a 2144
8e6ec690 2145 return ret;
cd5f6346
KP		 2146}
2147
d15057b7
KP		 2148/**
2149 * onenand_write - [MTD Interface] write buffer to FLASH
2150 * @param mtd MTD device structure
2151 * @param to offset to write to
2152 * @param len number of bytes to write
2153 * @param retlen pointer to variable to store the number of written bytes
2154 * @param buf the data to write
2155 *
2156 * Write with ECC
2157 */
2158static int onenand_write(struct mtd_info *mtd, loff_t to, size_t len,
2159 size_t *retlen, const u_char *buf)
2160{
2161 struct mtd_oob_ops ops = {
2162 .len = len,
2163 .ooblen = 0,
2164 .datbuf = (u_char *) buf,
2165 .oobbuf = NULL,
2166 };
2167 int ret;
2168
49dc08ee
AB		 2169 onenand_get_device(mtd, FL_WRITING);
2170 ret = onenand_write_ops_nolock(mtd, to, &ops);
2171 onenand_release_device(mtd);
d15057b7 2172
49dc08ee 2173 *retlen = ops.retlen;
d15057b7
KP		 2174 return ret;
2175}
2176
8593fbc6
TG		 2177/**
2178 * onenand_write_oob - [MTD Interface] NAND write data and/or out-of-band
e3da8067
KP		 2179 * @param mtd: MTD device structure
2180 * @param to: offset to write
2181 * @param ops: oob operation description structure
8593fbc6
TG		 2182 */
2183static int onenand_write_oob(struct mtd_info *mtd, loff_t to,
2184 struct mtd_oob_ops *ops)
2185{
49dc08ee
AB		 2186 int ret;
2187
4f4fad27 2188 switch (ops->mode) {
a5e7c7b4
AH		 2189 case MTD_OOB_PLACE:
2190 case MTD_OOB_AUTO:
2191 break;
2192 case MTD_OOB_RAW:
4f4fad27 2193 /* Not implemented yet */
a5e7c7b4
AH		 2194 default:
2195 return -EINVAL;
2196 }
d15057b7 2197
49dc08ee 2198 onenand_get_device(mtd, FL_WRITING);
d15057b7 2199 if (ops->datbuf)
49dc08ee
AB		 2200 ret = onenand_write_ops_nolock(mtd, to, ops);
2201 else
2202 ret = onenand_write_oob_nolock(mtd, to, ops);
2203 onenand_release_device(mtd);
d15057b7 2204
49dc08ee 2205 return ret;
8593fbc6
TG		 2206}
2207
cdc00130 2208/**
49dc08ee 2209 * onenand_block_isbad_nolock - [GENERIC] Check if a block is marked bad
cdc00130
KP		 2210 * @param mtd MTD device structure
2211 * @param ofs offset from device start
cdc00130
KP		 2212 * @param allowbbt 1, if its allowed to access the bbt area
2213 *
2214 * Check, if the block is bad. Either by reading the bad block table or
2215 * calling of the scan function.
2216 */
49dc08ee 2217static int onenand_block_isbad_nolock(struct mtd_info *mtd, loff_t ofs, int allowbbt)
cdc00130
KP		 2218{
2219 struct onenand_chip *this = mtd->priv;
2220 struct bbm_info *bbm = this->bbm;
2221
2222 /* Return info from the table */
2223 return bbm->isbad_bbt(mtd, ofs, allowbbt);
2224}
2225
72073027
MK		 2226
2227static int onenand_multiblock_erase_verify(struct mtd_info *mtd,
2228 struct erase_info *instr)
2229{
2230 struct onenand_chip *this = mtd->priv;
2231 loff_t addr = instr->addr;
2232 int len = instr->len;
2233 unsigned int block_size = (1 << this->erase_shift);
2234 int ret = 0;
2235
2236 while (len) {
2237 this->command(mtd, ONENAND_CMD_ERASE_VERIFY, addr, block_size);
2238 ret = this->wait(mtd, FL_VERIFYING_ERASE);
2239 if (ret) {
2240 printk(KERN_ERR "%s: Failed verify, block %d\n",
2241 __func__, onenand_block(this, addr));
2242 instr->state = MTD_ERASE_FAILED;
2243 instr->fail_addr = addr;
2244 return -1;
2245 }
2246 len -= block_size;
2247 addr += block_size;
2248 }
2249 return 0;
2250}
2251
2252/**
2253 * onenand_multiblock_erase - [Internal] erase block(s) using multiblock erase
2254 * @param mtd MTD device structure
2255 * @param instr erase instruction
2256 * @param region erase region
2257 *
2258 * Erase one or more blocks up to 64 block at a time
2259 */
2260static int onenand_multiblock_erase(struct mtd_info *mtd,
2261 struct erase_info *instr,
2262 unsigned int block_size)
2263{
2264 struct onenand_chip *this = mtd->priv;
2265 loff_t addr = instr->addr;
2266 int len = instr->len;
2267 int eb_count = 0;
2268 int ret = 0;
2269 int bdry_block = 0;
2270
2271 instr->state = MTD_ERASING;
2272
2273 if (ONENAND_IS_DDP(this)) {
2274 loff_t bdry_addr = this->chipsize >> 1;
2275 if (addr < bdry_addr && (addr + len) > bdry_addr)
2276 bdry_block = bdry_addr >> this->erase_shift;
2277 }
2278
2279 /* Pre-check bbs */
2280 while (len) {
2281 /* Check if we have a bad block, we do not erase bad blocks */
2282 if (onenand_block_isbad_nolock(mtd, addr, 0)) {
2283 printk(KERN_WARNING "%s: attempt to erase a bad block "
2284 "at addr 0x%012llx\n",
2285 __func__, (unsigned long long) addr);
2286 instr->state = MTD_ERASE_FAILED;
2287 return -EIO;
2288 }
2289 len -= block_size;
2290 addr += block_size;
2291 }
2292
2293 len = instr->len;
2294 addr = instr->addr;
2295
2296 /* loop over 64 eb batches */
2297 while (len) {
2298 struct erase_info verify_instr = *instr;
2299 int max_eb_count = MB_ERASE_MAX_BLK_COUNT;
2300
2301 verify_instr.addr = addr;
2302 verify_instr.len = 0;
2303
2304 /* do not cross chip boundary */
2305 if (bdry_block) {
2306 int this_block = (addr >> this->erase_shift);
2307
2308 if (this_block < bdry_block) {
2309 max_eb_count = min(max_eb_count,
2310 (bdry_block - this_block));
2311 }
2312 }
2313
2314 eb_count = 0;
2315
2316 while (len > block_size && eb_count < (max_eb_count - 1)) {
2317 this->command(mtd, ONENAND_CMD_MULTIBLOCK_ERASE,
2318 addr, block_size);
2319 onenand_invalidate_bufferram(mtd, addr, block_size);
2320
2321 ret = this->wait(mtd, FL_PREPARING_ERASE);
2322 if (ret) {
2323 printk(KERN_ERR "%s: Failed multiblock erase, "
2324 "block %d\n", __func__,
2325 onenand_block(this, addr));
2326 instr->state = MTD_ERASE_FAILED;
2327 instr->fail_addr = MTD_FAIL_ADDR_UNKNOWN;
2328 return -EIO;
2329 }
2330
2331 len -= block_size;
2332 addr += block_size;
2333 eb_count++;
2334 }
2335
2336 /* last block of 64-eb series */
2337 cond_resched();
2338 this->command(mtd, ONENAND_CMD_ERASE, addr, block_size);
2339 onenand_invalidate_bufferram(mtd, addr, block_size);
2340
2341 ret = this->wait(mtd, FL_ERASING);
2342 /* Check if it is write protected */
2343 if (ret) {
2344 printk(KERN_ERR "%s: Failed erase, block %d\n",
2345 __func__, onenand_block(this, addr));
2346 instr->state = MTD_ERASE_FAILED;
2347 instr->fail_addr = MTD_FAIL_ADDR_UNKNOWN;
2348 return -EIO;
2349 }
2350
2351 len -= block_size;
2352 addr += block_size;
2353 eb_count++;
2354
2355 /* verify */
2356 verify_instr.len = eb_count * block_size;
2357 if (onenand_multiblock_erase_verify(mtd, &verify_instr)) {
2358 instr->state = verify_instr.state;
2359 instr->fail_addr = verify_instr.fail_addr;
2360 return -EIO;
2361 }
2362
2363 }
2364 return 0;
2365}
2366
2367
cd5f6346 2368/**
73885aea 2369 * onenand_block_by_block_erase - [Internal] erase block(s) using regular erase
cd5f6346
KP		 2370 * @param mtd MTD device structure
2371 * @param instr erase instruction
73885aea
MK		 2372 * @param region erase region
2373 * @param block_size erase block size
cd5f6346 2374 *
73885aea 2375 * Erase one or more blocks one block at a time
cd5f6346 2376 */
73885aea
MK		 2377static int onenand_block_by_block_erase(struct mtd_info *mtd,
2378 struct erase_info *instr,
2379 struct mtd_erase_region_info *region,
2380 unsigned int block_size)
cd5f6346
KP		 2381{
2382 struct onenand_chip *this = mtd->priv;
5988af23 2383 loff_t addr = instr->addr;
73885aea 2384 int len = instr->len;
5988af23 2385 loff_t region_end = 0;
73885aea 2386 int ret = 0;
cd5f6346 2387
73885aea
MK		 2388 if (region) {
2389 /* region is set for Flex-OneNAND */
5988af23 2390 region_end = region->offset + region->erasesize * region->numblocks;
cd5f6346
KP		 2391 }
2392
cd5f6346
KP		 2393 instr->state = MTD_ERASING;
2394
73885aea 2395 /* Loop through the blocks */
cd5f6346 2396 while (len) {
61a7e198 2397 cond_resched();
cd5f6346 2398
cdc00130 2399 /* Check if we have a bad block, we do not erase bad blocks */
49dc08ee 2400 if (onenand_block_isbad_nolock(mtd, addr, 0)) {
297758f8
AKS		 2401 printk(KERN_WARNING "%s: attempt to erase a bad block "
2402 "at addr 0x%012llx\n",
2403 __func__, (unsigned long long) addr);
cdc00130 2404 instr->state = MTD_ERASE_FAILED;
73885aea 2405 return -EIO;
cdc00130 2406 }
cd5f6346
KP		 2407
2408 this->command(mtd, ONENAND_CMD_ERASE, addr, block_size);
2409
480b9dfb
AH		 2410 onenand_invalidate_bufferram(mtd, addr, block_size);
2411
cd5f6346
KP		 2412 ret = this->wait(mtd, FL_ERASING);
2413 /* Check, if it is write protected */
2414 if (ret) {
297758f8
AKS		 2415 printk(KERN_ERR "%s: Failed erase, block %d\n",
2416 __func__, onenand_block(this, addr));
cd5f6346
KP		 2417 instr->state = MTD_ERASE_FAILED;
2418 instr->fail_addr = addr;
73885aea 2419 return -EIO;
cd5f6346
KP		 2420 }
2421
2422 len -= block_size;
2423 addr += block_size;
5988af23
RH		 2424
2425 if (addr == region_end) {
2426 if (!len)
2427 break;
2428 region++;
2429
2430 block_size = region->erasesize;
2431 region_end = region->offset + region->erasesize * region->numblocks;
2432
2433 if (len & (block_size - 1)) {
2434 /* FIXME: This should be handled at MTD partitioning level. */
297758f8
AKS		 2435 printk(KERN_ERR "%s: Unaligned address\n",
2436 __func__);
73885aea 2437 return -EIO;
5988af23
RH		 2438 }
2439 }
73885aea
MK		 2440 }
2441 return 0;
2442}
5988af23 2443
73885aea
MK		 2444/**
2445 * onenand_erase - [MTD Interface] erase block(s)
2446 * @param mtd MTD device structure
2447 * @param instr erase instruction
2448 *
2449 * Erase one or more blocks
2450 */
2451static int onenand_erase(struct mtd_info *mtd, struct erase_info *instr)
2452{
2453 struct onenand_chip *this = mtd->priv;
2454 unsigned int block_size;
2455 loff_t addr = instr->addr;
2456 loff_t len = instr->len;
2457 int ret = 0;
2458 struct mtd_erase_region_info *region = NULL;
2459 loff_t region_offset = 0;
2460
2461 DEBUG(MTD_DEBUG_LEVEL3, "%s: start=0x%012llx, len=%llu\n", __func__,
2462 (unsigned long long) instr->addr, (unsigned long long) instr->len);
2463
2464 /* Do not allow erase past end of device */
2465 if (unlikely((len + addr) > mtd->size)) {
2466 printk(KERN_ERR "%s: Erase past end of device\n", __func__);
2467 return -EINVAL;
cd5f6346
KP		 2468 }
2469
73885aea
MK		 2470 if (FLEXONENAND(this)) {
2471 /* Find the eraseregion of this address */
2472 int i = flexonenand_region(mtd, addr);
cd5f6346 2473
73885aea
MK		 2474 region = &mtd->eraseregions[i];
2475 block_size = region->erasesize;
cd5f6346 2476
73885aea
MK		 2477 /* Start address within region must align on block boundary.
2478 * Erase region's start offset is always block start address.
2479 */
2480 region_offset = region->offset;
2481 } else
2482 block_size = 1 << this->erase_shift;
2483
2484 /* Start address must align on block boundary */
2485 if (unlikely((addr - region_offset) & (block_size - 1))) {
2486 printk(KERN_ERR "%s: Unaligned address\n", __func__);
2487 return -EINVAL;
2488 }
2489
2490 /* Length must align on block boundary */
2491 if (unlikely(len & (block_size - 1))) {
2492 printk(KERN_ERR "%s: Length not block aligned\n", __func__);
2493 return -EINVAL;
2494 }
2495
2496 instr->fail_addr = MTD_FAIL_ADDR_UNKNOWN;
2497
2498 /* Grab the lock and see if the device is available */
2499 onenand_get_device(mtd, FL_ERASING);
2500
d983c54e
KP		 2501 if (ONENAND_IS_4KB_PAGE(this) || region ||
2502 instr->len < MB_ERASE_MIN_BLK_COUNT * block_size) {
72073027
MK		 2503 /* region is set for Flex-OneNAND (no mb erase) */
2504 ret = onenand_block_by_block_erase(mtd, instr,
2505 region, block_size);
2506 } else {
2507 ret = onenand_multiblock_erase(mtd, instr, block_size);
2508 }
cd5f6346
KP		 2509
2510 /* Deselect and wake up anyone waiting on the device */
2511 onenand_release_device(mtd);
2512
3cd3a86b 2513 /* Do call back function */
73885aea
MK		 2514 if (!ret) {
2515 instr->state = MTD_ERASE_DONE;
3cd3a86b 2516 mtd_erase_callback(instr);
73885aea 2517 }
3cd3a86b 2518
cd5f6346
KP		 2519 return ret;
2520}
2521
2522/**
2523 * onenand_sync - [MTD Interface] sync
2524 * @param mtd MTD device structure
2525 *
2526 * Sync is actually a wait for chip ready function
2527 */
2528static void onenand_sync(struct mtd_info *mtd)
2529{
297758f8 2530 DEBUG(MTD_DEBUG_LEVEL3, "%s: called\n", __func__);
cd5f6346
KP		 2531
2532 /* Grab the lock and see if the device is available */
2533 onenand_get_device(mtd, FL_SYNCING);
2534
2535 /* Release it and go back */
2536 onenand_release_device(mtd);
2537}
2538
2539/**
2540 * onenand_block_isbad - [MTD Interface] Check whether the block at the given offset is bad
2541 * @param mtd MTD device structure
2542 * @param ofs offset relative to mtd start
cdc00130
KP		 2543 *
2544 * Check whether the block is bad
cd5f6346
KP		 2545 */
2546static int onenand_block_isbad(struct mtd_info *mtd, loff_t ofs)
2547{
49dc08ee
AB		 2548 int ret;
2549
cdc00130
KP		 2550 /* Check for invalid offset */
2551 if (ofs > mtd->size)
2552 return -EINVAL;
2553
49dc08ee
AB		 2554 onenand_get_device(mtd, FL_READING);
2555 ret = onenand_block_isbad_nolock(mtd, ofs, 0);
2556 onenand_release_device(mtd);
2557 return ret;
cdc00130
KP		 2558}
2559
2560/**
2561 * onenand_default_block_markbad - [DEFAULT] mark a block bad
2562 * @param mtd MTD device structure
2563 * @param ofs offset from device start
2564 *
2565 * This is the default implementation, which can be overridden by
2566 * a hardware specific driver.
2567 */
2568static int onenand_default_block_markbad(struct mtd_info *mtd, loff_t ofs)
2569{
2570 struct onenand_chip *this = mtd->priv;
2571 struct bbm_info *bbm = this->bbm;
2572 u_char buf[2] = {0, 0};
12f77c9e
KP		 2573 struct mtd_oob_ops ops = {
2574 .mode = MTD_OOB_PLACE,
2575 .ooblen = 2,
2576 .oobbuf = buf,
2577 .ooboffs = 0,
2578 };
cdc00130
KP		 2579 int block;
2580
2581 /* Get block number */
5988af23 2582 block = onenand_block(this, ofs);
cdc00130
KP		 2583 if (bbm->bbt)
2584 bbm->bbt[block >> 2] |= 0x01 << ((block & 0x03) << 1);
2585
492e1501 2586 /* We write two bytes, so we don't have to mess with 16-bit access */
cdc00130 2587 ofs += mtd->oobsize + (bbm->badblockpos & ~0x01);
5988af23
RH		 2588 /* FIXME : What to do when marking SLC block in partition
2589 * with MLC erasesize? For now, it is not advisable to
2590 * create partitions containing both SLC and MLC regions.
2591 */
2592 return onenand_write_oob_nolock(mtd, ofs, &ops);
cd5f6346
KP		 2593}
2594
2595/**
2596 * onenand_block_markbad - [MTD Interface] Mark the block at the given offset as bad
2597 * @param mtd MTD device structure
2598 * @param ofs offset relative to mtd start
cdc00130
KP		 2599 *
2600 * Mark the block as bad
cd5f6346
KP		 2601 */
2602static int onenand_block_markbad(struct mtd_info *mtd, loff_t ofs)
2603{
cdc00130
KP		 2604 struct onenand_chip *this = mtd->priv;
2605 int ret;
2606
2607 ret = onenand_block_isbad(mtd, ofs);
2608 if (ret) {
2609 /* If it was bad already, return success and do nothing */
2610 if (ret > 0)
2611 return 0;
2612 return ret;
2613 }
2614
49dc08ee
AB		 2615 onenand_get_device(mtd, FL_WRITING);
2616 ret = this->block_markbad(mtd, ofs);
2617 onenand_release_device(mtd);
2618 return ret;
cd5f6346
KP		 2619}
2620
2621/**
08f782b6 2622 * onenand_do_lock_cmd - [OneNAND Interface] Lock or unlock block(s)
cd5f6346
KP		 2623 * @param mtd MTD device structure
2624 * @param ofs offset relative to mtd start
08f782b6 2625 * @param len number of bytes to lock or unlock
e3da8067 2626 * @param cmd lock or unlock command
cd5f6346 2627 *
08f782b6 2628 * Lock or unlock one or more blocks
cd5f6346 2629 */
08f782b6 2630static int onenand_do_lock_cmd(struct mtd_info *mtd, loff_t ofs, size_t len, int cmd)
cd5f6346
KP		 2631{
2632 struct onenand_chip *this = mtd->priv;
2633 int start, end, block, value, status;
08f782b6 2634 int wp_status_mask;
cd5f6346 2635
5988af23
RH		 2636 start = onenand_block(this, ofs);
2637 end = onenand_block(this, ofs + len) - 1;
cd5f6346 2638
08f782b6
KP		 2639 if (cmd == ONENAND_CMD_LOCK)
2640 wp_status_mask = ONENAND_WP_LS;
2641 else
2642 wp_status_mask = ONENAND_WP_US;
2643
cd5f6346 2644 /* Continuous lock scheme */
28b79ff9 2645 if (this->options & ONENAND_HAS_CONT_LOCK) {
cd5f6346
KP		 2646 /* Set start block address */
2647 this->write_word(start, this->base + ONENAND_REG_START_BLOCK_ADDRESS);
2648 /* Set end block address */
5988af23 2649 this->write_word(end, this->base + ONENAND_REG_END_BLOCK_ADDRESS);
08f782b6
KP		 2650 /* Write lock command */
2651 this->command(mtd, cmd, 0, 0);
cd5f6346
KP		 2652
2653 /* There's no return value */
08f782b6 2654 this->wait(mtd, FL_LOCKING);
cd5f6346
KP		 2655
2656 /* Sanity check */
2657 while (this->read_word(this->base + ONENAND_REG_CTRL_STATUS)
2658 & ONENAND_CTRL_ONGO)
2659 continue;
2660
2661 /* Check lock status */
2662 status = this->read_word(this->base + ONENAND_REG_WP_STATUS);
08f782b6 2663 if (!(status & wp_status_mask))
297758f8
AKS		 2664 printk(KERN_ERR "%s: wp status = 0x%x\n",
2665 __func__, status);
cd5f6346
KP		 2666
2667 return 0;
2668 }
2669
2670 /* Block lock scheme */
5988af23 2671 for (block = start; block < end + 1; block++) {
20ba89a3
KP		 2672 /* Set block address */
2673 value = onenand_block_address(this, block);
2674 this->write_word(value, this->base + ONENAND_REG_START_ADDRESS1);
2675 /* Select DataRAM for DDP */
2676 value = onenand_bufferram_address(this, block);
2677 this->write_word(value, this->base + ONENAND_REG_START_ADDRESS2);
cd5f6346
KP		 2678 /* Set start block address */
2679 this->write_word(block, this->base + ONENAND_REG_START_BLOCK_ADDRESS);
08f782b6
KP		 2680 /* Write lock command */
2681 this->command(mtd, cmd, 0, 0);
cd5f6346
KP		 2682
2683 /* There's no return value */
08f782b6 2684 this->wait(mtd, FL_LOCKING);
cd5f6346
KP		 2685
2686 /* Sanity check */
2687 while (this->read_word(this->base + ONENAND_REG_CTRL_STATUS)
2688 & ONENAND_CTRL_ONGO)
2689 continue;
2690
cd5f6346
KP		 2691 /* Check lock status */
2692 status = this->read_word(this->base + ONENAND_REG_WP_STATUS);
08f782b6 2693 if (!(status & wp_status_mask))
297758f8
AKS		 2694 printk(KERN_ERR "%s: block = %d, wp status = 0x%x\n",
2695 __func__, block, status);
cd5f6346 2696 }
d5c5e78a 2697
cd5f6346
KP		 2698 return 0;
2699}
2700
08f782b6
KP		 2701/**
2702 * onenand_lock - [MTD Interface] Lock block(s)
2703 * @param mtd MTD device structure
2704 * @param ofs offset relative to mtd start
2705 * @param len number of bytes to unlock
2706 *
2707 * Lock one or more blocks
2708 */
69423d99 2709static int onenand_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
08f782b6 2710{
34627f0e
AH		 2711 int ret;
2712
2713 onenand_get_device(mtd, FL_LOCKING);
2714 ret = onenand_do_lock_cmd(mtd, ofs, len, ONENAND_CMD_LOCK);
2715 onenand_release_device(mtd);
2716 return ret;
08f782b6
KP		 2717}
2718
08f782b6
KP		 2719/**
2720 * onenand_unlock - [MTD Interface] Unlock block(s)
2721 * @param mtd MTD device structure
2722 * @param ofs offset relative to mtd start
2723 * @param len number of bytes to unlock
2724 *
2725 * Unlock one or more blocks
2726 */
69423d99 2727static int onenand_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
08f782b6 2728{
34627f0e
AH		 2729 int ret;
2730
2731 onenand_get_device(mtd, FL_LOCKING);
2732 ret = onenand_do_lock_cmd(mtd, ofs, len, ONENAND_CMD_UNLOCK);
2733 onenand_release_device(mtd);
2734 return ret;
08f782b6
KP		 2735}
2736
28b79ff9
KP		 2737/**
2738 * onenand_check_lock_status - [OneNAND Interface] Check lock status
2739 * @param this onenand chip data structure
2740 *
2741 * Check lock status
2742 */
66a10506 2743static int onenand_check_lock_status(struct onenand_chip *this)
28b79ff9
KP		 2744{
2745 unsigned int value, block, status;
2746 unsigned int end;
2747
2748 end = this->chipsize >> this->erase_shift;
2749 for (block = 0; block < end; block++) {
2750 /* Set block address */
2751 value = onenand_block_address(this, block);
2752 this->write_word(value, this->base + ONENAND_REG_START_ADDRESS1);
2753 /* Select DataRAM for DDP */
2754 value = onenand_bufferram_address(this, block);
2755 this->write_word(value, this->base + ONENAND_REG_START_ADDRESS2);
2756 /* Set start block address */
2757 this->write_word(block, this->base + ONENAND_REG_START_BLOCK_ADDRESS);
2758
2759 /* Check lock status */
2760 status = this->read_word(this->base + ONENAND_REG_WP_STATUS);
66a10506 2761 if (!(status & ONENAND_WP_US)) {
297758f8
AKS		 2762 printk(KERN_ERR "%s: block = %d, wp status = 0x%x\n",
2763 __func__, block, status);
66a10506
KP		 2764 return 0;
2765 }
28b79ff9 2766 }
66a10506
KP		 2767
2768 return 1;
28b79ff9
KP		 2769}
2770
2771/**
2772 * onenand_unlock_all - [OneNAND Interface] unlock all blocks
2773 * @param mtd MTD device structure
2774 *
2775 * Unlock all blocks
2776 */
66a10506 2777static void onenand_unlock_all(struct mtd_info *mtd)
28b79ff9
KP		 2778{
2779 struct onenand_chip *this = mtd->priv;
66a10506 2780 loff_t ofs = 0;
5988af23 2781 loff_t len = mtd->size;
28b79ff9
KP		 2782
2783 if (this->options & ONENAND_HAS_UNLOCK_ALL) {
10b7a2bd
KP		 2784 /* Set start block address */
2785 this->write_word(0, this->base + ONENAND_REG_START_BLOCK_ADDRESS);
28b79ff9
KP		 2786 /* Write unlock command */
2787 this->command(mtd, ONENAND_CMD_UNLOCK_ALL, 0, 0);
2788
2789 /* There's no return value */
08f782b6 2790 this->wait(mtd, FL_LOCKING);
28b79ff9
KP		 2791
2792 /* Sanity check */
2793 while (this->read_word(this->base + ONENAND_REG_CTRL_STATUS)
2794 & ONENAND_CTRL_ONGO)
2795 continue;
2796
31bb999e
KP		 2797 /* Don't check lock status */
2798 if (this->options & ONENAND_SKIP_UNLOCK_CHECK)
2799 return;
2800
66a10506
KP		 2801 /* Check lock status */
2802 if (onenand_check_lock_status(this))
2803 return;
2804
28b79ff9 2805 /* Workaround for all block unlock in DDP */
5988af23 2806 if (ONENAND_IS_DDP(this) && !FLEXONENAND(this)) {
66a10506
KP		 2807 /* All blocks on another chip */
2808 ofs = this->chipsize >> 1;
2809 len = this->chipsize >> 1;
28b79ff9 2810 }
28b79ff9
KP		 2811 }
2812
66a10506 2813 onenand_do_lock_cmd(mtd, ofs, len, ONENAND_CMD_UNLOCK);
28b79ff9
KP		 2814}
2815
493c6460
KP		 2816#ifdef CONFIG_MTD_ONENAND_OTP
2817
3cf60253
AKS		 2818/**
2819 * onenand_otp_command - Send OTP specific command to OneNAND device
2820 * @param mtd MTD device structure
2821 * @param cmd the command to be sent
2822 * @param addr offset to read from or write to
2823 * @param len number of bytes to read or write
2824 */
2825static int onenand_otp_command(struct mtd_info *mtd, int cmd, loff_t addr,
2826 size_t len)
2827{
2828 struct onenand_chip *this = mtd->priv;
2829 int value, block, page;
2830
2831 /* Address translation */
2832 switch (cmd) {
2833 case ONENAND_CMD_OTP_ACCESS:
2834 block = (int) (addr >> this->erase_shift);
2835 page = -1;
2836 break;
2837
2838 default:
2839 block = (int) (addr >> this->erase_shift);
2840 page = (int) (addr >> this->page_shift);
2841
2842 if (ONENAND_IS_2PLANE(this)) {
2843 /* Make the even block number */
2844 block &= ~1;
2845 /* Is it the odd plane? */
2846 if (addr & this->writesize)
2847 block++;
2848 page >>= 1;
2849 }
2850 page &= this->page_mask;
2851 break;
2852 }
2853
2854 if (block != -1) {
2855 /* Write 'DFS, FBA' of Flash */
2856 value = onenand_block_address(this, block);
2857 this->write_word(value, this->base +
2858 ONENAND_REG_START_ADDRESS1);
2859 }
2860
2861 if (page != -1) {
2862 /* Now we use page size operation */
2863 int sectors = 4, count = 4;
2864 int dataram;
2865
2866 switch (cmd) {
2867 default:
2868 if (ONENAND_IS_2PLANE(this) && cmd == ONENAND_CMD_PROG)
2869 cmd = ONENAND_CMD_2X_PROG;
2870 dataram = ONENAND_CURRENT_BUFFERRAM(this);
2871 break;
2872 }
2873
2874 /* Write 'FPA, FSA' of Flash */
2875 value = onenand_page_address(page, sectors);
2876 this->write_word(value, this->base +
2877 ONENAND_REG_START_ADDRESS8);
2878
2879 /* Write 'BSA, BSC' of DataRAM */
2880 value = onenand_buffer_address(dataram, sectors, count);
2881 this->write_word(value, this->base + ONENAND_REG_START_BUFFER);
2882 }
2883
2884 /* Interrupt clear */
2885 this->write_word(ONENAND_INT_CLEAR, this->base + ONENAND_REG_INTERRUPT);
2886
2887 /* Write command */
2888 this->write_word(cmd, this->base + ONENAND_REG_COMMAND);
2889
2890 return 0;
2891}
2892
2893/**
2894 * onenand_otp_write_oob_nolock - [Internal] OneNAND write out-of-band, specific to OTP
2895 * @param mtd MTD device structure
2896 * @param to offset to write to
2897 * @param len number of bytes to write
2898 * @param retlen pointer to variable to store the number of written bytes
2899 * @param buf the data to write
2900 *
2901 * OneNAND write out-of-band only for OTP
2902 */
2903static int onenand_otp_write_oob_nolock(struct mtd_info *mtd, loff_t to,
2904 struct mtd_oob_ops *ops)
2905{
2906 struct onenand_chip *this = mtd->priv;
2907 int column, ret = 0, oobsize;
2908 int written = 0;
2909 u_char *oobbuf;
2910 size_t len = ops->ooblen;
2911 const u_char *buf = ops->oobbuf;
2912 int block, value, status;
2913
2914 to += ops->ooboffs;
2915
2916 /* Initialize retlen, in case of early exit */
2917 ops->oobretlen = 0;
2918
2919 oobsize = mtd->oobsize;
2920
2921 column = to & (mtd->oobsize - 1);
2922
2923 oobbuf = this->oob_buf;
2924
2925 /* Loop until all data write */
2926 while (written < len) {
2927 int thislen = min_t(int, oobsize, len - written);
2928
2929 cond_resched();
2930
2931 block = (int) (to >> this->erase_shift);
2932 /*
2933 * Write 'DFS, FBA' of Flash
2934 * Add: F100h DQ=DFS, FBA
2935 */
2936
2937 value = onenand_block_address(this, block);
2938 this->write_word(value, this->base +
2939 ONENAND_REG_START_ADDRESS1);
2940
2941 /*
2942 * Select DataRAM for DDP
2943 * Add: F101h DQ=DBS
2944 */
2945
2946 value = onenand_bufferram_address(this, block);
2947 this->write_word(value, this->base +
2948 ONENAND_REG_START_ADDRESS2);
2949 ONENAND_SET_NEXT_BUFFERRAM(this);
2950
2951 /*
2952 * Enter OTP access mode
2953 */
2954 this->command(mtd, ONENAND_CMD_OTP_ACCESS, 0, 0);
2955 this->wait(mtd, FL_OTPING);
2956
2957 /* We send data to spare ram with oobsize
2958 * to prevent byte access */
2959 memcpy(oobbuf + column, buf, thislen);
2960
2961 /*
2962 * Write Data into DataRAM
2963 * Add: 8th Word
2964 * in sector0/spare/page0
2965 * DQ=XXFCh
2966 */
2967 this->write_bufferram(mtd, ONENAND_SPARERAM,
2968 oobbuf, 0, mtd->oobsize);
2969
2970 onenand_otp_command(mtd, ONENAND_CMD_PROGOOB, to, mtd->oobsize);
2971 onenand_update_bufferram(mtd, to, 0);
2972 if (ONENAND_IS_2PLANE(this)) {
2973 ONENAND_SET_BUFFERRAM1(this);
2974 onenand_update_bufferram(mtd, to + this->writesize, 0);
2975 }
2976
2977 ret = this->wait(mtd, FL_WRITING);
2978 if (ret) {
2979 printk(KERN_ERR "%s: write failed %d\n", __func__, ret);
2980 break;
2981 }
2982
2983 /* Exit OTP access mode */
2984 this->command(mtd, ONENAND_CMD_RESET, 0, 0);
2985 this->wait(mtd, FL_RESETING);
2986
2987 status = this->read_word(this->base + ONENAND_REG_CTRL_STATUS);
2988 status &= 0x60;
2989
2990 if (status == 0x60) {
2991 printk(KERN_DEBUG "\nBLOCK\tSTATUS\n");
2992 printk(KERN_DEBUG "1st Block\tLOCKED\n");
2993 printk(KERN_DEBUG "OTP Block\tLOCKED\n");
2994 } else if (status == 0x20) {
2995 printk(KERN_DEBUG "\nBLOCK\tSTATUS\n");
2996 printk(KERN_DEBUG "1st Block\tLOCKED\n");
2997 printk(KERN_DEBUG "OTP Block\tUN-LOCKED\n");
2998 } else if (status == 0x40) {
2999 printk(KERN_DEBUG "\nBLOCK\tSTATUS\n");
3000 printk(KERN_DEBUG "1st Block\tUN-LOCKED\n");
3001 printk(KERN_DEBUG "OTP Block\tLOCKED\n");
3002 } else {
3003 printk(KERN_DEBUG "Reboot to check\n");
3004 }
3005
3006 written += thislen;
3007 if (written == len)
3008 break;
3009
3010 to += mtd->writesize;
3011 buf += thislen;
3012 column = 0;
3013 }
3014
3015 ops->oobretlen = written;
3016
3017 return ret;
3018}
3019
492e1501 3020/* Internal OTP operation */
493c6460
KP		 3021typedef int (*otp_op_t)(struct mtd_info *mtd, loff_t form, size_t len,
3022 size_t *retlen, u_char *buf);
3023
3024/**
3025 * do_otp_read - [DEFAULT] Read OTP block area
3026 * @param mtd MTD device structure
3027 * @param from The offset to read
3028 * @param len number of bytes to read
3029 * @param retlen pointer to variable to store the number of readbytes
3030 * @param buf the databuffer to put/get data
3031 *
3032 * Read OTP block area.
3033 */
3034static int do_otp_read(struct mtd_info *mtd, loff_t from, size_t len,
3035 size_t *retlen, u_char *buf)
3036{
3037 struct onenand_chip *this = mtd->priv;
49dc08ee
AB		 3038 struct mtd_oob_ops ops = {
3039 .len = len,
3040 .ooblen = 0,
3041 .datbuf = buf,
3042 .oobbuf = NULL,
3043 };
493c6460
KP		 3044 int ret;
3045
3046 /* Enter OTP access mode */
3047 this->command(mtd, ONENAND_CMD_OTP_ACCESS, 0, 0);
3048 this->wait(mtd, FL_OTPING);
3049
8a8f632d 3050 ret = ONENAND_IS_4KB_PAGE(this) ?
5988af23
RH		 3051 onenand_mlc_read_ops_nolock(mtd, from, &ops) :
3052 onenand_read_ops_nolock(mtd, from, &ops);
493c6460
KP		 3053
3054 /* Exit OTP access mode */
3055 this->command(mtd, ONENAND_CMD_RESET, 0, 0);
3056 this->wait(mtd, FL_RESETING);
3057
3058 return ret;
3059}
3060
3061/**
3062 * do_otp_write - [DEFAULT] Write OTP block area
3063 * @param mtd MTD device structure
49dc08ee 3064 * @param to The offset to write
493c6460
KP		 3065 * @param len number of bytes to write
3066 * @param retlen pointer to variable to store the number of write bytes
3067 * @param buf the databuffer to put/get data
3068 *
3069 * Write OTP block area.
3070 */
49dc08ee 3071static int do_otp_write(struct mtd_info *mtd, loff_t to, size_t len,
493c6460
KP		 3072 size_t *retlen, u_char *buf)
3073{
3074 struct onenand_chip *this = mtd->priv;
3075 unsigned char *pbuf = buf;
3076 int ret;
49dc08ee 3077 struct mtd_oob_ops ops;
493c6460
KP		 3078
3079 /* Force buffer page aligned */
28318776 3080 if (len < mtd->writesize) {
493c6460 3081 memcpy(this->page_buf, buf, len);
28318776 3082 memset(this->page_buf + len, 0xff, mtd->writesize - len);
493c6460 3083 pbuf = this->page_buf;
28318776 3084 len = mtd->writesize;
493c6460
KP		 3085 }
3086
3087 /* Enter OTP access mode */
3088 this->command(mtd, ONENAND_CMD_OTP_ACCESS, 0, 0);
3089 this->wait(mtd, FL_OTPING);
3090
49dc08ee
AB		 3091 ops.len = len;
3092 ops.ooblen = 0;
1437085c 3093 ops.datbuf = pbuf;
49dc08ee
AB		 3094 ops.oobbuf = NULL;
3095 ret = onenand_write_ops_nolock(mtd, to, &ops);
3096 *retlen = ops.retlen;
493c6460
KP		 3097
3098 /* Exit OTP access mode */
3099 this->command(mtd, ONENAND_CMD_RESET, 0, 0);
3100 this->wait(mtd, FL_RESETING);
3101
3102 return ret;
3103}
3104
3105/**
3106 * do_otp_lock - [DEFAULT] Lock OTP block area
3107 * @param mtd MTD device structure
3108 * @param from The offset to lock
3109 * @param len number of bytes to lock
3110 * @param retlen pointer to variable to store the number of lock bytes
3111 * @param buf the databuffer to put/get data
3112 *
3113 * Lock OTP block area.
3114 */
3115static int do_otp_lock(struct mtd_info *mtd, loff_t from, size_t len,
3116 size_t *retlen, u_char *buf)
3117{
3118 struct onenand_chip *this = mtd->priv;
5988af23 3119 struct mtd_oob_ops ops;
493c6460
KP		 3120 int ret;
3121
5988af23 3122 if (FLEXONENAND(this)) {
3cf60253
AKS		 3123
3124 /* Enter OTP access mode */
3125 this->command(mtd, ONENAND_CMD_OTP_ACCESS, 0, 0);
3126 this->wait(mtd, FL_OTPING);
5988af23
RH		 3127 /*
3128 * For Flex-OneNAND, we write lock mark to 1st word of sector 4 of
3129 * main area of page 49.
3130 */
3131 ops.len = mtd->writesize;
3132 ops.ooblen = 0;
3133 ops.datbuf = buf;
3134 ops.oobbuf = NULL;
3135 ret = onenand_write_ops_nolock(mtd, mtd->writesize * 49, &ops);
3136 *retlen = ops.retlen;
3cf60253
AKS		 3137
3138 /* Exit OTP access mode */
3139 this->command(mtd, ONENAND_CMD_RESET, 0, 0);
3140 this->wait(mtd, FL_RESETING);
5988af23
RH		 3141 } else {
3142 ops.mode = MTD_OOB_PLACE;
3143 ops.ooblen = len;
3144 ops.oobbuf = buf;
3145 ops.ooboffs = 0;
3cf60253 3146 ret = onenand_otp_write_oob_nolock(mtd, from, &ops);
5988af23
RH		 3147 *retlen = ops.oobretlen;
3148 }
493c6460 3149
493c6460
KP		 3150 return ret;
3151}
3152
3153/**
3154 * onenand_otp_walk - [DEFAULT] Handle OTP operation
3155 * @param mtd MTD device structure
3156 * @param from The offset to read/write
3157 * @param len number of bytes to read/write
3158 * @param retlen pointer to variable to store the number of read bytes
3159 * @param buf the databuffer to put/get data
3160 * @param action do given action
3161 * @param mode specify user and factory
3162 *
3163 * Handle OTP operation.
3164 */
3165static int onenand_otp_walk(struct mtd_info *mtd, loff_t from, size_t len,
3166 size_t *retlen, u_char *buf,
3167 otp_op_t action, int mode)
3168{
3169 struct onenand_chip *this = mtd->priv;
3170 int otp_pages;
3171 int density;
3172 int ret = 0;
3173
3174 *retlen = 0;
3175
e71f04fc 3176 density = onenand_get_density(this->device_id);
493c6460
KP		 3177 if (density < ONENAND_DEVICE_DENSITY_512Mb)
3178 otp_pages = 20;
3179 else
3cf60253 3180 otp_pages = 50;
493c6460
KP		 3181
3182 if (mode == MTD_OTP_FACTORY) {
28318776 3183 from += mtd->writesize * otp_pages;
3cf60253 3184 otp_pages = ONENAND_PAGES_PER_BLOCK - otp_pages;
493c6460
KP		 3185 }
3186
3187 /* Check User/Factory boundary */
3cf60253 3188 if (mode == MTD_OTP_USER) {
0a032a4d 3189 if (mtd->writesize * otp_pages < from + len)
3cf60253
AKS		 3190 return 0;
3191 } else {
0a032a4d 3192 if (mtd->writesize * otp_pages < len)
3cf60253
AKS		 3193 return 0;
3194 }
493c6460 3195
49dc08ee 3196 onenand_get_device(mtd, FL_OTPING);
493c6460
KP		 3197 while (len > 0 && otp_pages > 0) {
3198 if (!action) { /* OTP Info functions */
3199 struct otp_info *otpinfo;
3200
3201 len -= sizeof(struct otp_info);
49dc08ee
AB		 3202 if (len <= 0) {
3203 ret = -ENOSPC;
3204 break;
3205 }
493c6460
KP		 3206
3207 otpinfo = (struct otp_info *) buf;
3208 otpinfo->start = from;
28318776 3209 otpinfo->length = mtd->writesize;
493c6460
KP		 3210 otpinfo->locked = 0;
3211
28318776 3212 from += mtd->writesize;
493c6460
KP		 3213 buf += sizeof(struct otp_info);
3214 *retlen += sizeof(struct otp_info);
3215 } else {
3216 size_t tmp_retlen;
493c6460
KP		 3217
3218 ret = action(mtd, from, len, &tmp_retlen, buf);
3219
3cf60253
AKS		 3220 buf += tmp_retlen;
3221 len -= tmp_retlen;
3222 *retlen += tmp_retlen;
493c6460 3223
49dc08ee
AB		 3224 if (ret)
3225 break;
493c6460
KP		 3226 }
3227 otp_pages--;
3228 }
49dc08ee 3229 onenand_release_device(mtd);
493c6460 3230
49dc08ee 3231 return ret;
493c6460
KP		 3232}
3233
3234/**
3235 * onenand_get_fact_prot_info - [MTD Interface] Read factory OTP info
3236 * @param mtd MTD device structure
3237 * @param buf the databuffer to put/get data
3238 * @param len number of bytes to read
3239 *
3240 * Read factory OTP info.
3241 */
3242static int onenand_get_fact_prot_info(struct mtd_info *mtd,
3243 struct otp_info *buf, size_t len)
3244{
3245 size_t retlen;
3246 int ret;
3247
3248 ret = onenand_otp_walk(mtd, 0, len, &retlen, (u_char *) buf, NULL, MTD_OTP_FACTORY);
3249
3250 return ret ? : retlen;
3251}
3252
3253/**
3254 * onenand_read_fact_prot_reg - [MTD Interface] Read factory OTP area
3255 * @param mtd MTD device structure
3256 * @param from The offset to read
3257 * @param len number of bytes to read
3258 * @param retlen pointer to variable to store the number of read bytes
3259 * @param buf the databuffer to put/get data
3260 *
3261 * Read factory OTP area.
3262 */
3263static int onenand_read_fact_prot_reg(struct mtd_info *mtd, loff_t from,
3264 size_t len, size_t *retlen, u_char *buf)
3265{
3266 return onenand_otp_walk(mtd, from, len, retlen, buf, do_otp_read, MTD_OTP_FACTORY);
3267}
3268
3269/**
3270 * onenand_get_user_prot_info - [MTD Interface] Read user OTP info
3271 * @param mtd MTD device structure
3272 * @param buf the databuffer to put/get data
3273 * @param len number of bytes to read
3274 *
3275 * Read user OTP info.
3276 */
3277static int onenand_get_user_prot_info(struct mtd_info *mtd,
3278 struct otp_info *buf, size_t len)
3279{
3280 size_t retlen;
3281 int ret;
3282
3283 ret = onenand_otp_walk(mtd, 0, len, &retlen, (u_char *) buf, NULL, MTD_OTP_USER);
3284
3285 return ret ? : retlen;
3286}
3287
3288/**
3289 * onenand_read_user_prot_reg - [MTD Interface] Read user OTP area
3290 * @param mtd MTD device structure
3291 * @param from The offset to read
3292 * @param len number of bytes to read
3293 * @param retlen pointer to variable to store the number of read bytes
3294 * @param buf the databuffer to put/get data
3295 *
3296 * Read user OTP area.
3297 */
3298static int onenand_read_user_prot_reg(struct mtd_info *mtd, loff_t from,
3299 size_t len, size_t *retlen, u_char *buf)
3300{
3301 return onenand_otp_walk(mtd, from, len, retlen, buf, do_otp_read, MTD_OTP_USER);
3302}
3303
3304/**
3305 * onenand_write_user_prot_reg - [MTD Interface] Write user OTP area
3306 * @param mtd MTD device structure
3307 * @param from The offset to write
3308 * @param len number of bytes to write
3309 * @param retlen pointer to variable to store the number of write bytes
3310 * @param buf the databuffer to put/get data
3311 *
3312 * Write user OTP area.
3313 */
3314static int onenand_write_user_prot_reg(struct mtd_info *mtd, loff_t from,
3315 size_t len, size_t *retlen, u_char *buf)
3316{
3317 return onenand_otp_walk(mtd, from, len, retlen, buf, do_otp_write, MTD_OTP_USER);
3318}
3319
3320/**
3321 * onenand_lock_user_prot_reg - [MTD Interface] Lock user OTP area
3322 * @param mtd MTD device structure
3323 * @param from The offset to lock
3324 * @param len number of bytes to unlock
3325 *
3326 * Write lock mark on spare area in page 0 in OTP block
3327 */
3328static int onenand_lock_user_prot_reg(struct mtd_info *mtd, loff_t from,
3329 size_t len)
3330{
69d79186 3331 struct onenand_chip *this = mtd->priv;
5988af23 3332 u_char *buf = FLEXONENAND(this) ? this->page_buf : this->oob_buf;
493c6460
KP		 3333 size_t retlen;
3334 int ret;
3cf60253 3335 unsigned int otp_lock_offset = ONENAND_OTP_LOCK_OFFSET;
493c6460 3336
5988af23
RH		 3337 memset(buf, 0xff, FLEXONENAND(this) ? this->writesize
3338 : mtd->oobsize);
493c6460
KP		 3339 /*
3340 * Write lock mark to 8th word of sector0 of page0 of the spare0.
3341 * We write 16 bytes spare area instead of 2 bytes.
5988af23
RH		 3342 * For Flex-OneNAND, we write lock mark to 1st word of sector 4 of
3343 * main area of page 49.
493c6460 3344 */
5988af23 3345
493c6460 3346 from = 0;
5988af23 3347 len = FLEXONENAND(this) ? mtd->writesize : 16;
493c6460 3348
3cf60253
AKS		 3349 /*
3350 * Note: OTP lock operation
3351 * OTP block : 0xXXFC XX 1111 1100
3352 * 1st block : 0xXXF3 (If chip support) XX 1111 0011
3353 * Both : 0xXXF0 (If chip support) XX 1111 0000
3354 */
3355 if (FLEXONENAND(this))
3356 otp_lock_offset = FLEXONENAND_OTP_LOCK_OFFSET;
3357
3358 /* ONENAND_OTP_AREA | ONENAND_OTP_BLOCK0 | ONENAND_OTP_AREA_BLOCK0 */
3359 if (otp == 1)
3360 buf[otp_lock_offset] = 0xFC;
3361 else if (otp == 2)
3362 buf[otp_lock_offset] = 0xF3;
3363 else if (otp == 3)
3364 buf[otp_lock_offset] = 0xF0;
3365 else if (otp != 0)
3366 printk(KERN_DEBUG "[OneNAND] Invalid option selected for OTP\n");
3367
5988af23 3368 ret = onenand_otp_walk(mtd, from, len, &retlen, buf, do_otp_lock, MTD_OTP_USER);
493c6460
KP		 3369
3370 return ret ? : retlen;
3371}
3cf60253 3372
493c6460
KP		 3373#endif /* CONFIG_MTD_ONENAND_OTP */
3374
28b79ff9 3375/**
75384b0d 3376 * onenand_check_features - Check and set OneNAND features
28b79ff9
KP		 3377 * @param mtd MTD data structure
3378 *
75384b0d
KP		 3379 * Check and set OneNAND features
3380 * - lock scheme
ee9745fc 3381 * - two plane
28b79ff9 3382 */
75384b0d 3383static void onenand_check_features(struct mtd_info *mtd)
28b79ff9
KP		 3384{
3385 struct onenand_chip *this = mtd->priv;
edb44b9b 3386 unsigned int density, process, numbufs;
28b79ff9
KP		 3387
3388 /* Lock scheme depends on density and process */
e71f04fc 3389 density = onenand_get_density(this->device_id);
28b79ff9 3390 process = this->version_id >> ONENAND_VERSION_PROCESS_SHIFT;
edb44b9b 3391 numbufs = this->read_word(this->base + ONENAND_REG_NUM_BUFFERS) >> 8;
28b79ff9
KP		 3392
3393 /* Lock scheme */
ee9745fc
KP		 3394 switch (density) {
3395 case ONENAND_DEVICE_DENSITY_4Gb:
6a88c47b
KP		 3396 if (ONENAND_IS_DDP(this))
3397 this->options |= ONENAND_HAS_2PLANE;
ac80dac0 3398 else if (numbufs == 1) {
6a88c47b 3399 this->options |= ONENAND_HAS_4KB_PAGE;
ac80dac0
RT		 3400 this->options |= ONENAND_HAS_CACHE_PROGRAM;
3401 }
ee9745fc
KP		 3402
3403 case ONENAND_DEVICE_DENSITY_2Gb:
492e1501 3404 /* 2Gb DDP does not have 2 plane */
ee9745fc
KP		 3405 if (!ONENAND_IS_DDP(this))
3406 this->options |= ONENAND_HAS_2PLANE;
3407 this->options |= ONENAND_HAS_UNLOCK_ALL;
3408
3409 case ONENAND_DEVICE_DENSITY_1Gb:
28b79ff9 3410 /* A-Die has all block unlock */
ee9745fc 3411 if (process)
28b79ff9 3412 this->options |= ONENAND_HAS_UNLOCK_ALL;
ee9745fc
KP		 3413 break;
3414
3415 default:
3416 /* Some OneNAND has continuous lock scheme */
3417 if (!process)
28b79ff9 3418 this->options |= ONENAND_HAS_CONT_LOCK;
ee9745fc 3419 break;
28b79ff9 3420 }
ee9745fc 3421
8a8f632d
KP		 3422 /* The MLC has 4KiB pagesize. */
3423 if (ONENAND_IS_MLC(this))
3424 this->options |= ONENAND_HAS_4KB_PAGE;
3425
3426 if (ONENAND_IS_4KB_PAGE(this))
5988af23
RH		 3427 this->options &= ~ONENAND_HAS_2PLANE;
3428
3429 if (FLEXONENAND(this)) {
3430 this->options &= ~ONENAND_HAS_CONT_LOCK;
3431 this->options |= ONENAND_HAS_UNLOCK_ALL;
3432 }
3433
ee9745fc
KP		 3434 if (this->options & ONENAND_HAS_CONT_LOCK)
3435 printk(KERN_DEBUG "Lock scheme is Continuous Lock\n");
3436 if (this->options & ONENAND_HAS_UNLOCK_ALL)
3437 printk(KERN_DEBUG "Chip support all block unlock\n");
3438 if (this->options & ONENAND_HAS_2PLANE)
3439 printk(KERN_DEBUG "Chip has 2 plane\n");
6a88c47b
KP		 3440 if (this->options & ONENAND_HAS_4KB_PAGE)
3441 printk(KERN_DEBUG "Chip has 4KiB pagesize\n");
ac80dac0
RT		 3442 if (this->options & ONENAND_HAS_CACHE_PROGRAM)
3443 printk(KERN_DEBUG "Chip has cache program feature\n");
28b79ff9
KP		 3444}
3445
cd5f6346 3446/**
e3da8067 3447 * onenand_print_device_info - Print device & version ID
cd5f6346 3448 * @param device device ID
e3da8067 3449 * @param version version ID
cd5f6346 3450 *
e3da8067 3451 * Print device & version ID
cd5f6346 3452 */
28b79ff9 3453static void onenand_print_device_info(int device, int version)
cd5f6346 3454{
5988af23 3455 int vcc, demuxed, ddp, density, flexonenand;
cd5f6346
KP		 3456
3457 vcc = device & ONENAND_DEVICE_VCC_MASK;
3458 demuxed = device & ONENAND_DEVICE_IS_DEMUX;
3459 ddp = device & ONENAND_DEVICE_IS_DDP;
e71f04fc 3460 density = onenand_get_density(device);
5988af23
RH		 3461 flexonenand = device & DEVICE_IS_FLEXONENAND;
3462 printk(KERN_INFO "%s%sOneNAND%s %dMB %sV 16-bit (0x%02x)\n",
3463 demuxed ? "" : "Muxed ",
3464 flexonenand ? "Flex-" : "",
cd5f6346
KP		 3465 ddp ? "(DDP)" : "",
3466 (16 << density),
3467 vcc ? "2.65/3.3" : "1.8",
3468 device);
49dc08ee 3469 printk(KERN_INFO "OneNAND version = 0x%04x\n", version);
cd5f6346
KP		 3470}
3471
3472static const struct onenand_manufacturers onenand_manuf_ids[] = {
3473 {ONENAND_MFR_SAMSUNG, "Samsung"},
ee8f3768 3474 {ONENAND_MFR_NUMONYX, "Numonyx"},
cd5f6346
KP		 3475};
3476
3477/**
3478 * onenand_check_maf - Check manufacturer ID
3479 * @param manuf manufacturer ID
3480 *
3481 * Check manufacturer ID
3482 */
3483static int onenand_check_maf(int manuf)
3484{
37b1cc39
KP		 3485 int size = ARRAY_SIZE(onenand_manuf_ids);
3486 char *name;
cd5f6346
KP		 3487 int i;
3488
37b1cc39 3489 for (i = 0; i < size; i++)
cd5f6346
KP		 3490 if (manuf == onenand_manuf_ids[i].id)
3491 break;
cd5f6346 3492
37b1cc39
KP		 3493 if (i < size)
3494 name = onenand_manuf_ids[i].name;
3495 else
3496 name = "Unknown";
3497
3498 printk(KERN_DEBUG "OneNAND Manufacturer: %s (0x%0x)\n", name, manuf);
cd5f6346 3499
37b1cc39 3500 return (i == size);
cd5f6346
KP		 3501}
3502
5988af23
RH		 3503/**
3504* flexonenand_get_boundary - Reads the SLC boundary
3505* @param onenand_info - onenand info structure
3506**/
3507static int flexonenand_get_boundary(struct mtd_info *mtd)
3508{
3509 struct onenand_chip *this = mtd->priv;
3510 unsigned die, bdry;
3511 int ret, syscfg, locked;
3512
3513 /* Disable ECC */
3514 syscfg = this->read_word(this->base + ONENAND_REG_SYS_CFG1);
3515 this->write_word((syscfg | 0x0100), this->base + ONENAND_REG_SYS_CFG1);
3516
3517 for (die = 0; die < this->dies; die++) {
3518 this->command(mtd, FLEXONENAND_CMD_PI_ACCESS, die, 0);
3519 this->wait(mtd, FL_SYNCING);
3520
3521 this->command(mtd, FLEXONENAND_CMD_READ_PI, die, 0);
3522 ret = this->wait(mtd, FL_READING);
3523
3524 bdry = this->read_word(this->base + ONENAND_DATARAM);
3525 if ((bdry >> FLEXONENAND_PI_UNLOCK_SHIFT) == 3)
3526 locked = 0;
3527 else
3528 locked = 1;
3529 this->boundary[die] = bdry & FLEXONENAND_PI_MASK;
3530
3531 this->command(mtd, ONENAND_CMD_RESET, 0, 0);
3532 ret = this->wait(mtd, FL_RESETING);
3533
3534 printk(KERN_INFO "Die %d boundary: %d%s\n", die,
3535 this->boundary[die], locked ? "(Locked)" : "(Unlocked)");
3536 }
3537
3538 /* Enable ECC */
3539 this->write_word(syscfg, this->base + ONENAND_REG_SYS_CFG1);
3540 return 0;
3541}
3542
3543/**
3544 * flexonenand_get_size - Fill up fields in onenand_chip and mtd_info
3545 * boundary[], diesize[], mtd->size, mtd->erasesize
3546 * @param mtd - MTD device structure
3547 */
3548static void flexonenand_get_size(struct mtd_info *mtd)
3549{
3550 struct onenand_chip *this = mtd->priv;
3551 int die, i, eraseshift, density;
3552 int blksperdie, maxbdry;
3553 loff_t ofs;
3554
3555 density = onenand_get_density(this->device_id);
3556 blksperdie = ((loff_t)(16 << density) << 20) >> (this->erase_shift);
3557 blksperdie >>= ONENAND_IS_DDP(this) ? 1 : 0;
3558 maxbdry = blksperdie - 1;
3559 eraseshift = this->erase_shift - 1;
3560
3561 mtd->numeraseregions = this->dies << 1;
3562
3563 /* This fills up the device boundary */
3564 flexonenand_get_boundary(mtd);
3565 die = ofs = 0;
3566 i = -1;
3567 for (; die < this->dies; die++) {
3568 if (!die || this->boundary[die-1] != maxbdry) {
3569 i++;
3570 mtd->eraseregions[i].offset = ofs;
3571 mtd->eraseregions[i].erasesize = 1 << eraseshift;
3572 mtd->eraseregions[i].numblocks =
3573 this->boundary[die] + 1;
3574 ofs += mtd->eraseregions[i].numblocks << eraseshift;
3575 eraseshift++;
3576 } else {
3577 mtd->numeraseregions -= 1;
3578 mtd->eraseregions[i].numblocks +=
3579 this->boundary[die] + 1;
3580 ofs += (this->boundary[die] + 1) << (eraseshift - 1);
3581 }
3582 if (this->boundary[die] != maxbdry) {
3583 i++;
3584 mtd->eraseregions[i].offset = ofs;
3585 mtd->eraseregions[i].erasesize = 1 << eraseshift;
3586 mtd->eraseregions[i].numblocks = maxbdry ^
3587 this->boundary[die];
3588 ofs += mtd->eraseregions[i].numblocks << eraseshift;
3589 eraseshift--;
3590 } else
3591 mtd->numeraseregions -= 1;
3592 }
3593
3594 /* Expose MLC erase size except when all blocks are SLC */
3595 mtd->erasesize = 1 << this->erase_shift;
3596 if (mtd->numeraseregions == 1)
3597 mtd->erasesize >>= 1;
3598
3599 printk(KERN_INFO "Device has %d eraseregions\n", mtd->numeraseregions);
3600 for (i = 0; i < mtd->numeraseregions; i++)
3601 printk(KERN_INFO "[offset: 0x%08x, erasesize: 0x%05x,"
3602 " numblocks: %04u]\n",
3603 (unsigned int) mtd->eraseregions[i].offset,
3604 mtd->eraseregions[i].erasesize,
3605 mtd->eraseregions[i].numblocks);
3606
3607 for (die = 0, mtd->size = 0; die < this->dies; die++) {
3608 this->diesize[die] = (loff_t)blksperdie << this->erase_shift;
3609 this->diesize[die] -= (loff_t)(this->boundary[die] + 1)
3610 << (this->erase_shift - 1);
3611 mtd->size += this->diesize[die];
3612 }
3613}
3614
3615/**
3616 * flexonenand_check_blocks_erased - Check if blocks are erased
3617 * @param mtd_info - mtd info structure
3618 * @param start - first erase block to check
3619 * @param end - last erase block to check
3620 *
3621 * Converting an unerased block from MLC to SLC
3622 * causes byte values to change. Since both data and its ECC
3623 * have changed, reads on the block give uncorrectable error.
3624 * This might lead to the block being detected as bad.
3625 *
3626 * Avoid this by ensuring that the block to be converted is
3627 * erased.
3628 */
3629static int flexonenand_check_blocks_erased(struct mtd_info *mtd, int start, int end)
3630{
3631 struct onenand_chip *this = mtd->priv;
3632 int i, ret;
3633 int block;
3634 struct mtd_oob_ops ops = {
3635 .mode = MTD_OOB_PLACE,
3636 .ooboffs = 0,
3637 .ooblen = mtd->oobsize,
3638 .datbuf = NULL,
3639 .oobbuf = this->oob_buf,
3640 };
3641 loff_t addr;
3642
3643 printk(KERN_DEBUG "Check blocks from %d to %d\n", start, end);
3644
3645 for (block = start; block <= end; block++) {
3646 addr = flexonenand_addr(this, block);
3647 if (onenand_block_isbad_nolock(mtd, addr, 0))
3648 continue;
3649
3650 /*
3651 * Since main area write results in ECC write to spare,
3652 * it is sufficient to check only ECC bytes for change.
3653 */
3654 ret = onenand_read_oob_nolock(mtd, addr, &ops);
3655 if (ret)
3656 return ret;
3657
3658 for (i = 0; i < mtd->oobsize; i++)
3659 if (this->oob_buf[i] != 0xff)
3660 break;
3661
3662 if (i != mtd->oobsize) {
297758f8
AKS		 3663 printk(KERN_WARNING "%s: Block %d not erased.\n",
3664 __func__, block);
5988af23
RH		 3665 return 1;
3666 }
3667 }
3668
3669 return 0;
3670}
3671
3672/**
3673 * flexonenand_set_boundary - Writes the SLC boundary
3674 * @param mtd - mtd info structure
3675 */
3676int flexonenand_set_boundary(struct mtd_info *mtd, int die,
3677 int boundary, int lock)
3678{
3679 struct onenand_chip *this = mtd->priv;
3680 int ret, density, blksperdie, old, new, thisboundary;
3681 loff_t addr;
3682
3683 /* Change only once for SDP Flex-OneNAND */
3684 if (die && (!ONENAND_IS_DDP(this)))
3685 return 0;
3686
3687 /* boundary value of -1 indicates no required change */
3688 if (boundary < 0 || boundary == this->boundary[die])
3689 return 0;
3690
3691 density = onenand_get_density(this->device_id);
3692 blksperdie = ((16 << density) << 20) >> this->erase_shift;
3693 blksperdie >>= ONENAND_IS_DDP(this) ? 1 : 0;
3694
3695 if (boundary >= blksperdie) {
297758f8
AKS		 3696 printk(KERN_ERR "%s: Invalid boundary value. "
3697 "Boundary not changed.\n", __func__);
5988af23
RH		 3698 return -EINVAL;
3699 }
3700
3701 /* Check if converting blocks are erased */
3702 old = this->boundary[die] + (die * this->density_mask);
3703 new = boundary + (die * this->density_mask);
3704 ret = flexonenand_check_blocks_erased(mtd, min(old, new) + 1, max(old, new));
3705 if (ret) {
297758f8
AKS		 3706 printk(KERN_ERR "%s: Please erase blocks "
3707 "before boundary change\n", __func__);
5988af23
RH		 3708 return ret;
3709 }
3710
3711 this->command(mtd, FLEXONENAND_CMD_PI_ACCESS, die, 0);
3712 this->wait(mtd, FL_SYNCING);
3713
3714 /* Check is boundary is locked */
3715 this->command(mtd, FLEXONENAND_CMD_READ_PI, die, 0);
3716 ret = this->wait(mtd, FL_READING);
3717
3718 thisboundary = this->read_word(this->base + ONENAND_DATARAM);
3719 if ((thisboundary >> FLEXONENAND_PI_UNLOCK_SHIFT) != 3) {
297758f8 3720 printk(KERN_ERR "%s: boundary locked\n", __func__);
5988af23
RH		 3721 ret = 1;
3722 goto out;
3723 }
3724
297758f8 3725 printk(KERN_INFO "Changing die %d boundary: %d%s\n",
5988af23
RH		 3726 die, boundary, lock ? "(Locked)" : "(Unlocked)");
3727
3728 addr = die ? this->diesize[0] : 0;
3729
3730 boundary &= FLEXONENAND_PI_MASK;
3731 boundary |= lock ? 0 : (3 << FLEXONENAND_PI_UNLOCK_SHIFT);
3732
3733 this->command(mtd, ONENAND_CMD_ERASE, addr, 0);
3734 ret = this->wait(mtd, FL_ERASING);
3735 if (ret) {
f369c7ec
MK		 3736 printk(KERN_ERR "%s: Failed PI erase for Die %d\n",
3737 __func__, die);
5988af23
RH		 3738 goto out;
3739 }
3740
3741 this->write_word(boundary, this->base + ONENAND_DATARAM);
3742 this->command(mtd, ONENAND_CMD_PROG, addr, 0);
3743 ret = this->wait(mtd, FL_WRITING);
3744 if (ret) {
297758f8
AKS		 3745 printk(KERN_ERR "%s: Failed PI write for Die %d\n",
3746 __func__, die);
5988af23
RH		 3747 goto out;
3748 }
3749
3750 this->command(mtd, FLEXONENAND_CMD_PI_UPDATE, die, 0);
3751 ret = this->wait(mtd, FL_WRITING);
3752out:
3753 this->write_word(ONENAND_CMD_RESET, this->base + ONENAND_REG_COMMAND);
3754 this->wait(mtd, FL_RESETING);
3755 if (!ret)
3756 /* Recalculate device size on boundary change*/
3757 flexonenand_get_size(mtd);
3758
3759 return ret;
3760}
3761
cd5f6346 3762/**
ad0d363b 3763 * onenand_chip_probe - [OneNAND Interface] The generic chip probe
cd5f6346
KP		 3764 * @param mtd MTD device structure
3765 *
3766 * OneNAND detection method:
59c51591 3767 * Compare the values from command with ones from register
cd5f6346 3768 */
ad0d363b 3769static int onenand_chip_probe(struct mtd_info *mtd)
cd5f6346
KP		 3770{
3771 struct onenand_chip *this = mtd->priv;
ad0d363b 3772 int bram_maf_id, bram_dev_id, maf_id, dev_id;
47e777e0
KP		 3773 int syscfg;
3774
3775 /* Save system configuration 1 */
3776 syscfg = this->read_word(this->base + ONENAND_REG_SYS_CFG1);
3777 /* Clear Sync. Burst Read mode to read BootRAM */
ee8f3768 3778 this->write_word((syscfg & ~ONENAND_SYS_CFG1_SYNC_READ & ~ONENAND_SYS_CFG1_SYNC_WRITE), this->base + ONENAND_REG_SYS_CFG1);
cd5f6346
KP		 3779
3780 /* Send the command for reading device ID from BootRAM */
3781 this->write_word(ONENAND_CMD_READID, this->base + ONENAND_BOOTRAM);
3782
3783 /* Read manufacturer and device IDs from BootRAM */
3784 bram_maf_id = this->read_word(this->base + ONENAND_BOOTRAM + 0x0);
3785 bram_dev_id = this->read_word(this->base + ONENAND_BOOTRAM + 0x2);
3786
47e777e0
KP		 3787 /* Reset OneNAND to read default register values */
3788 this->write_word(ONENAND_CMD_RESET, this->base + ONENAND_BOOTRAM);
3789 /* Wait reset */
3790 this->wait(mtd, FL_RESETING);
3791
3792 /* Restore system configuration 1 */
3793 this->write_word(syscfg, this->base + ONENAND_REG_SYS_CFG1);
3794
cd5f6346
KP		 3795 /* Check manufacturer ID */
3796 if (onenand_check_maf(bram_maf_id))
3797 return -ENXIO;
3798
cd5f6346
KP		 3799 /* Read manufacturer and device IDs from Register */
3800 maf_id = this->read_word(this->base + ONENAND_REG_MANUFACTURER_ID);
3801 dev_id = this->read_word(this->base + ONENAND_REG_DEVICE_ID);
3802
3803 /* Check OneNAND device */
3804 if (maf_id != bram_maf_id || dev_id != bram_dev_id)
3805 return -ENXIO;
3806
ad0d363b
KP		 3807 return 0;
3808}
3809
3810/**
3811 * onenand_probe - [OneNAND Interface] Probe the OneNAND device
3812 * @param mtd MTD device structure
3813 */
3814static int onenand_probe(struct mtd_info *mtd)
3815{
3816 struct onenand_chip *this = mtd->priv;
3817 int maf_id, dev_id, ver_id;
3818 int density;
3819 int ret;
3820
3821 ret = this->chip_probe(mtd);
3822 if (ret)
3823 return ret;
3824
3825 /* Read manufacturer and device IDs from Register */
3826 maf_id = this->read_word(this->base + ONENAND_REG_MANUFACTURER_ID);
3827 dev_id = this->read_word(this->base + ONENAND_REG_DEVICE_ID);
3828 ver_id = this->read_word(this->base + ONENAND_REG_VERSION_ID);
3829 this->technology = this->read_word(this->base + ONENAND_REG_TECHNOLOGY);
3830
cd5f6346 3831 /* Flash device information */
28b79ff9 3832 onenand_print_device_info(dev_id, ver_id);
cd5f6346 3833 this->device_id = dev_id;
28b79ff9 3834 this->version_id = ver_id;
cd5f6346 3835
c37cb56f
KP		 3836 /* Check OneNAND features */
3837 onenand_check_features(mtd);
3838
e71f04fc 3839 density = onenand_get_density(dev_id);
5988af23
RH		 3840 if (FLEXONENAND(this)) {
3841 this->dies = ONENAND_IS_DDP(this) ? 2 : 1;
3842 /* Maximum possible erase regions */
3843 mtd->numeraseregions = this->dies << 1;
3844 mtd->eraseregions = kzalloc(sizeof(struct mtd_erase_region_info)
3845 * (this->dies << 1), GFP_KERNEL);
3846 if (!mtd->eraseregions)
3847 return -ENOMEM;
3848 }
3849
3850 /*
3851 * For Flex-OneNAND, chipsize represents maximum possible device size.
3852 * mtd->size represents the actual device size.
3853 */
cd5f6346
KP		 3854 this->chipsize = (16 << density) << 20;
3855
3856 /* OneNAND page size & block size */
3857 /* The data buffer size is equal to page size */
28318776 3858 mtd->writesize = this->read_word(this->base + ONENAND_REG_DATA_BUFFER_SIZE);
5988af23 3859 /* We use the full BufferRAM */
8a8f632d 3860 if (ONENAND_IS_4KB_PAGE(this))
5988af23
RH		 3861 mtd->writesize <<= 1;
3862
28318776 3863 mtd->oobsize = mtd->writesize >> 5;
9bfbc9b2 3864 /* Pages per a block are always 64 in OneNAND */
28318776 3865 mtd->erasesize = mtd->writesize << 6;
5988af23
RH		 3866 /*
3867 * Flex-OneNAND SLC area has 64 pages per block.
3868 * Flex-OneNAND MLC area has 128 pages per block.
3869 * Expose MLC erase size to find erase_shift and page_mask.
3870 */
3871 if (FLEXONENAND(this))
3872 mtd->erasesize <<= 1;
cd5f6346
KP		 3873
3874 this->erase_shift = ffs(mtd->erasesize) - 1;
28318776 3875 this->page_shift = ffs(mtd->writesize) - 1;
9bfbc9b2 3876 this->page_mask = (1 << (this->erase_shift - this->page_shift)) - 1;
5988af23
RH		 3877 /* Set density mask. it is used for DDP */
3878 if (ONENAND_IS_DDP(this))
3879 this->density_mask = this->chipsize >> (this->erase_shift + 1);
ee9745fc
KP		 3880 /* It's real page size */
3881 this->writesize = mtd->writesize;
cd5f6346 3882
492e1501 3883 /* REVISIT: Multichip handling */
cd5f6346 3884
5988af23
RH		 3885 if (FLEXONENAND(this))
3886 flexonenand_get_size(mtd);
3887 else
3888 mtd->size = this->chipsize;
cd5f6346 3889
ee9745fc
KP		 3890 /*
3891 * We emulate the 4KiB page and 256KiB erase block size
3892 * But oobsize is still 64 bytes.
3893 * It is only valid if you turn on 2X program support,
3894 * Otherwise it will be ignored by compiler.
3895 */
3896 if (ONENAND_IS_2PLANE(this)) {
3897 mtd->writesize <<= 1;
3898 mtd->erasesize <<= 1;
3899 }
3900
cd5f6346
KP		 3901 return 0;
3902}
3903
a41371eb
KP		 3904/**
3905 * onenand_suspend - [MTD Interface] Suspend the OneNAND flash
3906 * @param mtd MTD device structure
3907 */
3908static int onenand_suspend(struct mtd_info *mtd)
3909{
3910 return onenand_get_device(mtd, FL_PM_SUSPENDED);
3911}
3912
3913/**
3914 * onenand_resume - [MTD Interface] Resume the OneNAND flash
3915 * @param mtd MTD device structure
3916 */
3917static void onenand_resume(struct mtd_info *mtd)
3918{
3919 struct onenand_chip *this = mtd->priv;
3920
3921 if (this->state == FL_PM_SUSPENDED)
3922 onenand_release_device(mtd);
3923 else
297758f8
AKS		 3924 printk(KERN_ERR "%s: resume() called for the chip which is not "
3925 "in suspended state\n", __func__);
a41371eb
KP		 3926}
3927
cd5f6346
KP		 3928/**
3929 * onenand_scan - [OneNAND Interface] Scan for the OneNAND device
3930 * @param mtd MTD device structure
3931 * @param maxchips Number of chips to scan for
3932 *
3933 * This fills out all the not initialized function pointers
3934 * with the defaults.
3935 * The flash ID is read and the mtd/chip structures are
3936 * filled with the appropriate values.
3937 */
3938int onenand_scan(struct mtd_info *mtd, int maxchips)
3939{
5988af23 3940 int i, ret;
cd5f6346
KP		 3941 struct onenand_chip *this = mtd->priv;
3942
3943 if (!this->read_word)
3944 this->read_word = onenand_readw;
3945 if (!this->write_word)
3946 this->write_word = onenand_writew;
3947
3948 if (!this->command)
3949 this->command = onenand_command;
3950 if (!this->wait)
2c22120f 3951 onenand_setup_wait(mtd);
31bb999e
KP		 3952 if (!this->bbt_wait)
3953 this->bbt_wait = onenand_bbt_wait;
3954 if (!this->unlock_all)
3955 this->unlock_all = onenand_unlock_all;
cd5f6346 3956
ad0d363b
KP		 3957 if (!this->chip_probe)
3958 this->chip_probe = onenand_chip_probe;
3959
cd5f6346
KP		 3960 if (!this->read_bufferram)
3961 this->read_bufferram = onenand_read_bufferram;
3962 if (!this->write_bufferram)
3963 this->write_bufferram = onenand_write_bufferram;
3964
cdc00130
KP		 3965 if (!this->block_markbad)
3966 this->block_markbad = onenand_default_block_markbad;
3967 if (!this->scan_bbt)
3968 this->scan_bbt = onenand_default_bbt;
3969
cd5f6346
KP		 3970 if (onenand_probe(mtd))
3971 return -ENXIO;
3972
52b0eea7
KP		 3973 /* Set Sync. Burst Read after probing */
3974 if (this->mmcontrol) {
3975 printk(KERN_INFO "OneNAND Sync. Burst Read support\n");
3976 this->read_bufferram = onenand_sync_read_bufferram;
3977 }
3978
532a37cf
KP		 3979 /* Allocate buffers, if necessary */
3980 if (!this->page_buf) {
470bc844 3981 this->page_buf = kzalloc(mtd->writesize, GFP_KERNEL);
532a37cf 3982 if (!this->page_buf) {
297758f8
AKS		 3983 printk(KERN_ERR "%s: Can't allocate page_buf\n",
3984 __func__);
532a37cf
KP		 3985 return -ENOMEM;
3986 }
4a8ce0b0
KP		 3987#ifdef CONFIG_MTD_ONENAND_VERIFY_WRITE
3988 this->verify_buf = kzalloc(mtd->writesize, GFP_KERNEL);
3989 if (!this->verify_buf) {
3990 kfree(this->page_buf);
3991 return -ENOMEM;
3992 }
3993#endif
532a37cf
KP		 3994 this->options |= ONENAND_PAGEBUF_ALLOC;
3995 }
470bc844
KP		 3996 if (!this->oob_buf) {
3997 this->oob_buf = kzalloc(mtd->oobsize, GFP_KERNEL);
3998 if (!this->oob_buf) {
297758f8
AKS		 3999 printk(KERN_ERR "%s: Can't allocate oob_buf\n",
4000 __func__);
470bc844
KP		 4001 if (this->options & ONENAND_PAGEBUF_ALLOC) {
4002 this->options &= ~ONENAND_PAGEBUF_ALLOC;
4003 kfree(this->page_buf);
4004 }
4005 return -ENOMEM;
4006 }
4007 this->options |= ONENAND_OOBBUF_ALLOC;
4008 }
532a37cf 4009
cd5f6346
KP		 4010 this->state = FL_READY;
4011 init_waitqueue_head(&this->wq);
4012 spin_lock_init(&this->chip_lock);
4013
60d84f97
KP		 4014 /*
4015 * Allow subpage writes up to oobsize.
4016 */
cd5f6346 4017 switch (mtd->oobsize) {
5988af23
RH		 4018 case 128:
4019 this->ecclayout = &onenand_oob_128;
4020 mtd->subpage_sft = 0;
4021 break;
cd5f6346 4022 case 64:
5bd34c09 4023 this->ecclayout = &onenand_oob_64;
60d84f97 4024 mtd->subpage_sft = 2;
cd5f6346
KP		 4025 break;
4026
4027 case 32:
5bd34c09 4028 this->ecclayout = &onenand_oob_32;
60d84f97 4029 mtd->subpage_sft = 1;
cd5f6346
KP		 4030 break;
4031
4032 default:
297758f8
AKS		 4033 printk(KERN_WARNING "%s: No OOB scheme defined for oobsize %d\n",
4034 __func__, mtd->oobsize);
60d84f97 4035 mtd->subpage_sft = 0;
cd5f6346 4036 /* To prevent kernel oops */
5bd34c09 4037 this->ecclayout = &onenand_oob_32;
cd5f6346
KP		 4038 break;
4039 }
4040
60d84f97 4041 this->subpagesize = mtd->writesize >> mtd->subpage_sft;
a5e7c7b4
AH		 4042
4043 /*
4044 * The number of bytes available for a client to place data into
4045 * the out of band area
4046 */
4047 this->ecclayout->oobavail = 0;
ad286343
KP		 4048 for (i = 0; i < MTD_MAX_OOBFREE_ENTRIES &&
4049 this->ecclayout->oobfree[i].length; i++)
a5e7c7b4
AH		 4050 this->ecclayout->oobavail +=
4051 this->ecclayout->oobfree[i].length;
1f92267c 4052 mtd->oobavail = this->ecclayout->oobavail;
a5e7c7b4 4053
5bd34c09 4054 mtd->ecclayout = this->ecclayout;
d5c5e78a 4055
cd5f6346 4056 /* Fill in remaining MTD driver data */
c7626802 4057 mtd->type = ONENAND_IS_MLC(this) ? MTD_MLCNANDFLASH : MTD_NANDFLASH;
5fa43394 4058 mtd->flags = MTD_CAP_NANDFLASH;
cd5f6346
KP		 4059 mtd->erase = onenand_erase;
4060 mtd->point = NULL;
4061 mtd->unpoint = NULL;
4062 mtd->read = onenand_read;
4063 mtd->write = onenand_write;
cd5f6346
KP		 4064 mtd->read_oob = onenand_read_oob;
4065 mtd->write_oob = onenand_write_oob;
6c77fd64 4066 mtd->panic_write = onenand_panic_write;
493c6460
KP		 4067#ifdef CONFIG_MTD_ONENAND_OTP
4068 mtd->get_fact_prot_info = onenand_get_fact_prot_info;
4069 mtd->read_fact_prot_reg = onenand_read_fact_prot_reg;
4070 mtd->get_user_prot_info = onenand_get_user_prot_info;
4071 mtd->read_user_prot_reg = onenand_read_user_prot_reg;
4072 mtd->write_user_prot_reg = onenand_write_user_prot_reg;
4073 mtd->lock_user_prot_reg = onenand_lock_user_prot_reg;
4074#endif
cd5f6346 4075 mtd->sync = onenand_sync;
08f782b6 4076 mtd->lock = onenand_lock;
cd5f6346 4077 mtd->unlock = onenand_unlock;
a41371eb
KP		 4078 mtd->suspend = onenand_suspend;
4079 mtd->resume = onenand_resume;
cd5f6346
KP		 4080 mtd->block_isbad = onenand_block_isbad;
4081 mtd->block_markbad = onenand_block_markbad;
4082 mtd->owner = THIS_MODULE;
25dcd297 4083 mtd->writebufsize = mtd->writesize;
cd5f6346
KP		 4084
4085 /* Unlock whole block */
31bb999e 4086 this->unlock_all(mtd);
cd5f6346 4087
5988af23
RH		 4088 ret = this->scan_bbt(mtd);
4089 if ((!FLEXONENAND(this)) || ret)
4090 return ret;
4091
4092 /* Change Flex-OneNAND boundaries if required */
4093 for (i = 0; i < MAX_DIES; i++)
4094 flexonenand_set_boundary(mtd, i, flex_bdry[2 * i],
4095 flex_bdry[(2 * i) + 1]);
4096
4097 return 0;
cd5f6346
KP		 4098}
4099
4100/**
4101 * onenand_release - [OneNAND Interface] Free resources held by the OneNAND device
4102 * @param mtd MTD device structure
4103 */
4104void onenand_release(struct mtd_info *mtd)
4105{
532a37cf
KP		 4106 struct onenand_chip *this = mtd->priv;
4107
cd5f6346
KP		 4108#ifdef CONFIG_MTD_PARTITIONS
4109 /* Deregister partitions */
4110 del_mtd_partitions (mtd);
4111#endif
4112 /* Deregister the device */
4113 del_mtd_device (mtd);
532a37cf
KP		 4114
4115 /* Free bad block table memory, if allocated */
f00b0046
AH		 4116 if (this->bbm) {
4117 struct bbm_info *bbm = this->bbm;
4118 kfree(bbm->bbt);
532a37cf 4119 kfree(this->bbm);
f00b0046 4120 }
470bc844 4121 /* Buffers allocated by onenand_scan */
4a8ce0b0 4122 if (this->options & ONENAND_PAGEBUF_ALLOC) {
532a37cf 4123 kfree(this->page_buf);
4a8ce0b0
KP		 4124#ifdef CONFIG_MTD_ONENAND_VERIFY_WRITE
4125 kfree(this->verify_buf);
4126#endif
4127 }
470bc844
KP		 4128 if (this->options & ONENAND_OOBBUF_ALLOC)
4129 kfree(this->oob_buf);
5988af23 4130 kfree(mtd->eraseregions);
cd5f6346
KP		 4131}
4132
4133EXPORT_SYMBOL_GPL(onenand_scan);
4134EXPORT_SYMBOL_GPL(onenand_release);
4135
4136MODULE_LICENSE("GPL");
4137MODULE_AUTHOR("Kyungmin Park <kyungmin.park@samsung.com>");
4138MODULE_DESCRIPTION("Generic OneNAND flash driver code");
Linux kernel - Deliverables
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