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3ce351b5 BC |
1 | /* |
2 | * Copyright (c) 2015 MediaTek Inc. | |
3 | * Author: Bayi Cheng <bayi.cheng@mediatek.com> | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License version 2 as | |
7 | * published by the Free Software Foundation. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, | |
10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
12 | * GNU General Public License for more details. | |
13 | */ | |
14 | ||
15 | #include <linux/clk.h> | |
16 | #include <linux/delay.h> | |
17 | #include <linux/device.h> | |
18 | #include <linux/init.h> | |
19 | #include <linux/io.h> | |
20 | #include <linux/iopoll.h> | |
21 | #include <linux/ioport.h> | |
22 | #include <linux/math64.h> | |
23 | #include <linux/module.h> | |
24 | #include <linux/mtd/mtd.h> | |
25 | #include <linux/mutex.h> | |
26 | #include <linux/of.h> | |
27 | #include <linux/of_device.h> | |
28 | #include <linux/pinctrl/consumer.h> | |
29 | #include <linux/platform_device.h> | |
30 | #include <linux/slab.h> | |
31 | #include <linux/mtd/mtd.h> | |
32 | #include <linux/mtd/partitions.h> | |
33 | #include <linux/mtd/spi-nor.h> | |
34 | ||
35 | #define MTK_NOR_CMD_REG 0x00 | |
36 | #define MTK_NOR_CNT_REG 0x04 | |
37 | #define MTK_NOR_RDSR_REG 0x08 | |
38 | #define MTK_NOR_RDATA_REG 0x0c | |
39 | #define MTK_NOR_RADR0_REG 0x10 | |
40 | #define MTK_NOR_RADR1_REG 0x14 | |
41 | #define MTK_NOR_RADR2_REG 0x18 | |
42 | #define MTK_NOR_WDATA_REG 0x1c | |
43 | #define MTK_NOR_PRGDATA0_REG 0x20 | |
44 | #define MTK_NOR_PRGDATA1_REG 0x24 | |
45 | #define MTK_NOR_PRGDATA2_REG 0x28 | |
46 | #define MTK_NOR_PRGDATA3_REG 0x2c | |
47 | #define MTK_NOR_PRGDATA4_REG 0x30 | |
48 | #define MTK_NOR_PRGDATA5_REG 0x34 | |
49 | #define MTK_NOR_SHREG0_REG 0x38 | |
50 | #define MTK_NOR_SHREG1_REG 0x3c | |
51 | #define MTK_NOR_SHREG2_REG 0x40 | |
52 | #define MTK_NOR_SHREG3_REG 0x44 | |
53 | #define MTK_NOR_SHREG4_REG 0x48 | |
54 | #define MTK_NOR_SHREG5_REG 0x4c | |
55 | #define MTK_NOR_SHREG6_REG 0x50 | |
56 | #define MTK_NOR_SHREG7_REG 0x54 | |
57 | #define MTK_NOR_SHREG8_REG 0x58 | |
58 | #define MTK_NOR_SHREG9_REG 0x5c | |
59 | #define MTK_NOR_CFG1_REG 0x60 | |
60 | #define MTK_NOR_CFG2_REG 0x64 | |
61 | #define MTK_NOR_CFG3_REG 0x68 | |
62 | #define MTK_NOR_STATUS0_REG 0x70 | |
63 | #define MTK_NOR_STATUS1_REG 0x74 | |
64 | #define MTK_NOR_STATUS2_REG 0x78 | |
65 | #define MTK_NOR_STATUS3_REG 0x7c | |
66 | #define MTK_NOR_FLHCFG_REG 0x84 | |
67 | #define MTK_NOR_TIME_REG 0x94 | |
68 | #define MTK_NOR_PP_DATA_REG 0x98 | |
69 | #define MTK_NOR_PREBUF_STUS_REG 0x9c | |
70 | #define MTK_NOR_DELSEL0_REG 0xa0 | |
71 | #define MTK_NOR_DELSEL1_REG 0xa4 | |
72 | #define MTK_NOR_INTRSTUS_REG 0xa8 | |
73 | #define MTK_NOR_INTREN_REG 0xac | |
74 | #define MTK_NOR_CHKSUM_CTL_REG 0xb8 | |
75 | #define MTK_NOR_CHKSUM_REG 0xbc | |
76 | #define MTK_NOR_CMD2_REG 0xc0 | |
77 | #define MTK_NOR_WRPROT_REG 0xc4 | |
78 | #define MTK_NOR_RADR3_REG 0xc8 | |
79 | #define MTK_NOR_DUAL_REG 0xcc | |
80 | #define MTK_NOR_DELSEL2_REG 0xd0 | |
81 | #define MTK_NOR_DELSEL3_REG 0xd4 | |
82 | #define MTK_NOR_DELSEL4_REG 0xd8 | |
83 | ||
84 | /* commands for mtk nor controller */ | |
85 | #define MTK_NOR_READ_CMD 0x0 | |
86 | #define MTK_NOR_RDSR_CMD 0x2 | |
87 | #define MTK_NOR_PRG_CMD 0x4 | |
88 | #define MTK_NOR_WR_CMD 0x10 | |
89 | #define MTK_NOR_PIO_WR_CMD 0x90 | |
90 | #define MTK_NOR_WRSR_CMD 0x20 | |
91 | #define MTK_NOR_PIO_READ_CMD 0x81 | |
92 | #define MTK_NOR_WR_BUF_ENABLE 0x1 | |
93 | #define MTK_NOR_WR_BUF_DISABLE 0x0 | |
94 | #define MTK_NOR_ENABLE_SF_CMD 0x30 | |
95 | #define MTK_NOR_DUAD_ADDR_EN 0x8 | |
96 | #define MTK_NOR_QUAD_READ_EN 0x4 | |
97 | #define MTK_NOR_DUAL_ADDR_EN 0x2 | |
98 | #define MTK_NOR_DUAL_READ_EN 0x1 | |
99 | #define MTK_NOR_DUAL_DISABLE 0x0 | |
100 | #define MTK_NOR_FAST_READ 0x1 | |
101 | ||
102 | #define SFLASH_WRBUF_SIZE 128 | |
103 | ||
104 | /* Can shift up to 48 bits (6 bytes) of TX/RX */ | |
105 | #define MTK_NOR_MAX_RX_TX_SHIFT 6 | |
106 | /* can shift up to 56 bits (7 bytes) transfer by MTK_NOR_PRG_CMD */ | |
107 | #define MTK_NOR_MAX_SHIFT 7 | |
108 | ||
109 | /* Helpers for accessing the program data / shift data registers */ | |
110 | #define MTK_NOR_PRG_REG(n) (MTK_NOR_PRGDATA0_REG + 4 * (n)) | |
111 | #define MTK_NOR_SHREG(n) (MTK_NOR_SHREG0_REG + 4 * (n)) | |
112 | ||
113 | struct mt8173_nor { | |
114 | struct spi_nor nor; | |
115 | struct device *dev; | |
116 | void __iomem *base; /* nor flash base address */ | |
117 | struct clk *spi_clk; | |
118 | struct clk *nor_clk; | |
119 | }; | |
120 | ||
121 | static void mt8173_nor_set_read_mode(struct mt8173_nor *mt8173_nor) | |
122 | { | |
123 | struct spi_nor *nor = &mt8173_nor->nor; | |
124 | ||
125 | switch (nor->flash_read) { | |
126 | case SPI_NOR_FAST: | |
127 | writeb(nor->read_opcode, mt8173_nor->base + | |
128 | MTK_NOR_PRGDATA3_REG); | |
129 | writeb(MTK_NOR_FAST_READ, mt8173_nor->base + | |
130 | MTK_NOR_CFG1_REG); | |
131 | break; | |
132 | case SPI_NOR_DUAL: | |
133 | writeb(nor->read_opcode, mt8173_nor->base + | |
134 | MTK_NOR_PRGDATA3_REG); | |
135 | writeb(MTK_NOR_DUAL_READ_EN, mt8173_nor->base + | |
136 | MTK_NOR_DUAL_REG); | |
137 | break; | |
138 | case SPI_NOR_QUAD: | |
139 | writeb(nor->read_opcode, mt8173_nor->base + | |
140 | MTK_NOR_PRGDATA4_REG); | |
141 | writeb(MTK_NOR_QUAD_READ_EN, mt8173_nor->base + | |
142 | MTK_NOR_DUAL_REG); | |
143 | break; | |
144 | default: | |
145 | writeb(MTK_NOR_DUAL_DISABLE, mt8173_nor->base + | |
146 | MTK_NOR_DUAL_REG); | |
147 | break; | |
148 | } | |
149 | } | |
150 | ||
151 | static int mt8173_nor_execute_cmd(struct mt8173_nor *mt8173_nor, u8 cmdval) | |
152 | { | |
153 | int reg; | |
154 | u8 val = cmdval & 0x1f; | |
155 | ||
156 | writeb(cmdval, mt8173_nor->base + MTK_NOR_CMD_REG); | |
157 | return readl_poll_timeout(mt8173_nor->base + MTK_NOR_CMD_REG, reg, | |
158 | !(reg & val), 100, 10000); | |
159 | } | |
160 | ||
161 | static int mt8173_nor_do_tx_rx(struct mt8173_nor *mt8173_nor, u8 op, | |
162 | u8 *tx, int txlen, u8 *rx, int rxlen) | |
163 | { | |
164 | int len = 1 + txlen + rxlen; | |
165 | int i, ret, idx; | |
166 | ||
167 | if (len > MTK_NOR_MAX_SHIFT) | |
168 | return -EINVAL; | |
169 | ||
170 | writeb(len * 8, mt8173_nor->base + MTK_NOR_CNT_REG); | |
171 | ||
172 | /* start at PRGDATA5, go down to PRGDATA0 */ | |
173 | idx = MTK_NOR_MAX_RX_TX_SHIFT - 1; | |
174 | ||
175 | /* opcode */ | |
176 | writeb(op, mt8173_nor->base + MTK_NOR_PRG_REG(idx)); | |
177 | idx--; | |
178 | ||
179 | /* program TX data */ | |
180 | for (i = 0; i < txlen; i++, idx--) | |
181 | writeb(tx[i], mt8173_nor->base + MTK_NOR_PRG_REG(idx)); | |
182 | ||
183 | /* clear out rest of TX registers */ | |
184 | while (idx >= 0) { | |
185 | writeb(0, mt8173_nor->base + MTK_NOR_PRG_REG(idx)); | |
186 | idx--; | |
187 | } | |
188 | ||
189 | ret = mt8173_nor_execute_cmd(mt8173_nor, MTK_NOR_PRG_CMD); | |
190 | if (ret) | |
191 | return ret; | |
192 | ||
193 | /* restart at first RX byte */ | |
194 | idx = rxlen - 1; | |
195 | ||
196 | /* read out RX data */ | |
197 | for (i = 0; i < rxlen; i++, idx--) | |
198 | rx[i] = readb(mt8173_nor->base + MTK_NOR_SHREG(idx)); | |
199 | ||
200 | return 0; | |
201 | } | |
202 | ||
203 | /* Do a WRSR (Write Status Register) command */ | |
204 | static int mt8173_nor_wr_sr(struct mt8173_nor *mt8173_nor, u8 sr) | |
205 | { | |
206 | writeb(sr, mt8173_nor->base + MTK_NOR_PRGDATA5_REG); | |
207 | writeb(8, mt8173_nor->base + MTK_NOR_CNT_REG); | |
208 | return mt8173_nor_execute_cmd(mt8173_nor, MTK_NOR_WRSR_CMD); | |
209 | } | |
210 | ||
211 | static int mt8173_nor_write_buffer_enable(struct mt8173_nor *mt8173_nor) | |
212 | { | |
213 | u8 reg; | |
214 | ||
215 | /* the bit0 of MTK_NOR_CFG2_REG is pre-fetch buffer | |
216 | * 0: pre-fetch buffer use for read | |
217 | * 1: pre-fetch buffer use for page program | |
218 | */ | |
219 | writel(MTK_NOR_WR_BUF_ENABLE, mt8173_nor->base + MTK_NOR_CFG2_REG); | |
220 | return readb_poll_timeout(mt8173_nor->base + MTK_NOR_CFG2_REG, reg, | |
221 | 0x01 == (reg & 0x01), 100, 10000); | |
222 | } | |
223 | ||
224 | static int mt8173_nor_write_buffer_disable(struct mt8173_nor *mt8173_nor) | |
225 | { | |
226 | u8 reg; | |
227 | ||
228 | writel(MTK_NOR_WR_BUF_DISABLE, mt8173_nor->base + MTK_NOR_CFG2_REG); | |
229 | return readb_poll_timeout(mt8173_nor->base + MTK_NOR_CFG2_REG, reg, | |
230 | MTK_NOR_WR_BUF_DISABLE == (reg & 0x1), 100, | |
231 | 10000); | |
232 | } | |
233 | ||
234 | static void mt8173_nor_set_addr(struct mt8173_nor *mt8173_nor, u32 addr) | |
235 | { | |
236 | int i; | |
237 | ||
238 | for (i = 0; i < 3; i++) { | |
239 | writeb(addr & 0xff, mt8173_nor->base + MTK_NOR_RADR0_REG + i * 4); | |
240 | addr >>= 8; | |
241 | } | |
242 | /* Last register is non-contiguous */ | |
243 | writeb(addr & 0xff, mt8173_nor->base + MTK_NOR_RADR3_REG); | |
244 | } | |
245 | ||
246 | static int mt8173_nor_read(struct spi_nor *nor, loff_t from, size_t length, | |
247 | size_t *retlen, u_char *buffer) | |
248 | { | |
249 | int i, ret; | |
250 | int addr = (int)from; | |
251 | u8 *buf = (u8 *)buffer; | |
252 | struct mt8173_nor *mt8173_nor = nor->priv; | |
253 | ||
254 | /* set mode for fast read mode ,dual mode or quad mode */ | |
255 | mt8173_nor_set_read_mode(mt8173_nor); | |
256 | mt8173_nor_set_addr(mt8173_nor, addr); | |
257 | ||
258 | for (i = 0; i < length; i++, (*retlen)++) { | |
259 | ret = mt8173_nor_execute_cmd(mt8173_nor, MTK_NOR_PIO_READ_CMD); | |
260 | if (ret < 0) | |
261 | return ret; | |
262 | buf[i] = readb(mt8173_nor->base + MTK_NOR_RDATA_REG); | |
263 | } | |
264 | return 0; | |
265 | } | |
266 | ||
267 | static int mt8173_nor_write_single_byte(struct mt8173_nor *mt8173_nor, | |
268 | int addr, int length, u8 *data) | |
269 | { | |
270 | int i, ret; | |
271 | ||
272 | mt8173_nor_set_addr(mt8173_nor, addr); | |
273 | ||
274 | for (i = 0; i < length; i++) { | |
80e1ca69 | 275 | writeb(*data++, mt8173_nor->base + MTK_NOR_WDATA_REG); |
3ce351b5 BC |
276 | ret = mt8173_nor_execute_cmd(mt8173_nor, MTK_NOR_PIO_WR_CMD); |
277 | if (ret < 0) | |
278 | return ret; | |
3ce351b5 BC |
279 | } |
280 | return 0; | |
281 | } | |
282 | ||
283 | static int mt8173_nor_write_buffer(struct mt8173_nor *mt8173_nor, int addr, | |
284 | const u8 *buf) | |
285 | { | |
286 | int i, bufidx, data; | |
287 | ||
288 | mt8173_nor_set_addr(mt8173_nor, addr); | |
289 | ||
290 | bufidx = 0; | |
291 | for (i = 0; i < SFLASH_WRBUF_SIZE; i += 4) { | |
292 | data = buf[bufidx + 3]<<24 | buf[bufidx + 2]<<16 | | |
293 | buf[bufidx + 1]<<8 | buf[bufidx]; | |
294 | bufidx += 4; | |
295 | writel(data, mt8173_nor->base + MTK_NOR_PP_DATA_REG); | |
296 | } | |
297 | return mt8173_nor_execute_cmd(mt8173_nor, MTK_NOR_WR_CMD); | |
298 | } | |
299 | ||
300 | static void mt8173_nor_write(struct spi_nor *nor, loff_t to, size_t len, | |
301 | size_t *retlen, const u_char *buf) | |
302 | { | |
303 | int ret; | |
304 | struct mt8173_nor *mt8173_nor = nor->priv; | |
305 | ||
306 | ret = mt8173_nor_write_buffer_enable(mt8173_nor); | |
307 | if (ret < 0) | |
308 | dev_warn(mt8173_nor->dev, "write buffer enable failed!\n"); | |
309 | ||
310 | while (len >= SFLASH_WRBUF_SIZE) { | |
311 | ret = mt8173_nor_write_buffer(mt8173_nor, to, buf); | |
312 | if (ret < 0) | |
313 | dev_err(mt8173_nor->dev, "write buffer failed!\n"); | |
314 | len -= SFLASH_WRBUF_SIZE; | |
315 | to += SFLASH_WRBUF_SIZE; | |
316 | buf += SFLASH_WRBUF_SIZE; | |
317 | (*retlen) += SFLASH_WRBUF_SIZE; | |
318 | } | |
319 | ret = mt8173_nor_write_buffer_disable(mt8173_nor); | |
320 | if (ret < 0) | |
321 | dev_warn(mt8173_nor->dev, "write buffer disable failed!\n"); | |
322 | ||
323 | if (len) { | |
324 | ret = mt8173_nor_write_single_byte(mt8173_nor, to, (int)len, | |
325 | (u8 *)buf); | |
326 | if (ret < 0) | |
327 | dev_err(mt8173_nor->dev, "write single byte failed!\n"); | |
328 | (*retlen) += len; | |
329 | } | |
330 | } | |
331 | ||
332 | static int mt8173_nor_read_reg(struct spi_nor *nor, u8 opcode, u8 *buf, int len) | |
333 | { | |
334 | int ret; | |
335 | struct mt8173_nor *mt8173_nor = nor->priv; | |
336 | ||
337 | switch (opcode) { | |
338 | case SPINOR_OP_RDSR: | |
339 | ret = mt8173_nor_execute_cmd(mt8173_nor, MTK_NOR_RDSR_CMD); | |
340 | if (ret < 0) | |
341 | return ret; | |
342 | if (len == 1) | |
343 | *buf = readb(mt8173_nor->base + MTK_NOR_RDSR_REG); | |
344 | else | |
345 | dev_err(mt8173_nor->dev, "len should be 1 for read status!\n"); | |
346 | break; | |
347 | default: | |
348 | ret = mt8173_nor_do_tx_rx(mt8173_nor, opcode, NULL, 0, buf, len); | |
349 | break; | |
350 | } | |
351 | return ret; | |
352 | } | |
353 | ||
354 | static int mt8173_nor_write_reg(struct spi_nor *nor, u8 opcode, u8 *buf, | |
355 | int len) | |
356 | { | |
357 | int ret; | |
358 | struct mt8173_nor *mt8173_nor = nor->priv; | |
359 | ||
360 | switch (opcode) { | |
361 | case SPINOR_OP_WRSR: | |
362 | /* We only handle 1 byte */ | |
363 | ret = mt8173_nor_wr_sr(mt8173_nor, *buf); | |
364 | break; | |
365 | default: | |
366 | ret = mt8173_nor_do_tx_rx(mt8173_nor, opcode, buf, len, NULL, 0); | |
367 | if (ret) | |
368 | dev_warn(mt8173_nor->dev, "write reg failure!\n"); | |
369 | break; | |
370 | } | |
371 | return ret; | |
372 | } | |
373 | ||
92752d99 GU |
374 | static int mtk_nor_init(struct mt8173_nor *mt8173_nor, |
375 | struct device_node *flash_node) | |
3ce351b5 BC |
376 | { |
377 | int ret; | |
378 | struct spi_nor *nor; | |
379 | ||
380 | /* initialize controller to accept commands */ | |
381 | writel(MTK_NOR_ENABLE_SF_CMD, mt8173_nor->base + MTK_NOR_WRPROT_REG); | |
382 | ||
383 | nor = &mt8173_nor->nor; | |
384 | nor->dev = mt8173_nor->dev; | |
385 | nor->priv = mt8173_nor; | |
386 | spi_nor_set_flash_node(nor, flash_node); | |
387 | ||
388 | /* fill the hooks to spi nor */ | |
389 | nor->read = mt8173_nor_read; | |
390 | nor->read_reg = mt8173_nor_read_reg; | |
391 | nor->write = mt8173_nor_write; | |
392 | nor->write_reg = mt8173_nor_write_reg; | |
3ce351b5 BC |
393 | nor->mtd.name = "mtk_nor"; |
394 | /* initialized with NULL */ | |
395 | ret = spi_nor_scan(nor, NULL, SPI_NOR_DUAL); | |
396 | if (ret) | |
397 | return ret; | |
398 | ||
399 | return mtd_device_register(&nor->mtd, NULL, 0); | |
400 | } | |
401 | ||
402 | static int mtk_nor_drv_probe(struct platform_device *pdev) | |
403 | { | |
404 | struct device_node *flash_np; | |
405 | struct resource *res; | |
406 | int ret; | |
407 | struct mt8173_nor *mt8173_nor; | |
408 | ||
409 | if (!pdev->dev.of_node) { | |
410 | dev_err(&pdev->dev, "No DT found\n"); | |
411 | return -EINVAL; | |
412 | } | |
413 | ||
414 | mt8173_nor = devm_kzalloc(&pdev->dev, sizeof(*mt8173_nor), GFP_KERNEL); | |
415 | if (!mt8173_nor) | |
416 | return -ENOMEM; | |
417 | platform_set_drvdata(pdev, mt8173_nor); | |
418 | ||
419 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
420 | mt8173_nor->base = devm_ioremap_resource(&pdev->dev, res); | |
421 | if (IS_ERR(mt8173_nor->base)) | |
422 | return PTR_ERR(mt8173_nor->base); | |
423 | ||
424 | mt8173_nor->spi_clk = devm_clk_get(&pdev->dev, "spi"); | |
425 | if (IS_ERR(mt8173_nor->spi_clk)) | |
426 | return PTR_ERR(mt8173_nor->spi_clk); | |
427 | ||
428 | mt8173_nor->nor_clk = devm_clk_get(&pdev->dev, "sf"); | |
429 | if (IS_ERR(mt8173_nor->nor_clk)) | |
430 | return PTR_ERR(mt8173_nor->nor_clk); | |
431 | ||
432 | mt8173_nor->dev = &pdev->dev; | |
433 | ret = clk_prepare_enable(mt8173_nor->spi_clk); | |
434 | if (ret) | |
435 | return ret; | |
436 | ||
437 | ret = clk_prepare_enable(mt8173_nor->nor_clk); | |
438 | if (ret) { | |
439 | clk_disable_unprepare(mt8173_nor->spi_clk); | |
440 | return ret; | |
441 | } | |
442 | /* only support one attached flash */ | |
443 | flash_np = of_get_next_available_child(pdev->dev.of_node, NULL); | |
444 | if (!flash_np) { | |
445 | dev_err(&pdev->dev, "no SPI flash device to configure\n"); | |
446 | ret = -ENODEV; | |
447 | goto nor_free; | |
448 | } | |
449 | ret = mtk_nor_init(mt8173_nor, flash_np); | |
450 | ||
451 | nor_free: | |
452 | if (ret) { | |
453 | clk_disable_unprepare(mt8173_nor->spi_clk); | |
454 | clk_disable_unprepare(mt8173_nor->nor_clk); | |
455 | } | |
456 | return ret; | |
457 | } | |
458 | ||
459 | static int mtk_nor_drv_remove(struct platform_device *pdev) | |
460 | { | |
461 | struct mt8173_nor *mt8173_nor = platform_get_drvdata(pdev); | |
462 | ||
463 | clk_disable_unprepare(mt8173_nor->spi_clk); | |
464 | clk_disable_unprepare(mt8173_nor->nor_clk); | |
465 | return 0; | |
466 | } | |
467 | ||
468 | static const struct of_device_id mtk_nor_of_ids[] = { | |
469 | { .compatible = "mediatek,mt8173-nor"}, | |
470 | { /* sentinel */ } | |
471 | }; | |
472 | MODULE_DEVICE_TABLE(of, mtk_nor_of_ids); | |
473 | ||
474 | static struct platform_driver mtk_nor_driver = { | |
475 | .probe = mtk_nor_drv_probe, | |
476 | .remove = mtk_nor_drv_remove, | |
477 | .driver = { | |
478 | .name = "mtk-nor", | |
479 | .of_match_table = mtk_nor_of_ids, | |
480 | }, | |
481 | }; | |
482 | ||
483 | module_platform_driver(mtk_nor_driver); | |
484 | MODULE_LICENSE("GPL v2"); | |
485 | MODULE_DESCRIPTION("MediaTek SPI NOR Flash Driver"); |