[deliverable/linux.git] / drivers / mtd / spi-nor / mtk-quadspi.c

/*
 * Copyright (c) 2015 MediaTek Inc.
 * Author: Bayi Cheng <bayi.cheng@mediatek.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/device.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/iopoll.h>
#include <linux/ioport.h>
#include <linux/math64.h>
#include <linux/module.h>
#include <linux/mutex.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/pinctrl/consumer.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/partitions.h>
#include <linux/mtd/spi-nor.h>

#define MTK_NOR_CMD_REG			0x00
#define MTK_NOR_CNT_REG			0x04
#define MTK_NOR_RDSR_REG		0x08
#define MTK_NOR_RDATA_REG		0x0c
#define MTK_NOR_RADR0_REG		0x10
#define MTK_NOR_RADR1_REG		0x14
#define MTK_NOR_RADR2_REG		0x18
#define MTK_NOR_WDATA_REG		0x1c
#define MTK_NOR_PRGDATA0_REG		0x20
#define MTK_NOR_PRGDATA1_REG		0x24
#define MTK_NOR_PRGDATA2_REG		0x28
#define MTK_NOR_PRGDATA3_REG		0x2c
#define MTK_NOR_PRGDATA4_REG		0x30
#define MTK_NOR_PRGDATA5_REG		0x34
#define MTK_NOR_SHREG0_REG		0x38
#define MTK_NOR_SHREG1_REG		0x3c
#define MTK_NOR_SHREG2_REG		0x40
#define MTK_NOR_SHREG3_REG		0x44
#define MTK_NOR_SHREG4_REG		0x48
#define MTK_NOR_SHREG5_REG		0x4c
#define MTK_NOR_SHREG6_REG		0x50
#define MTK_NOR_SHREG7_REG		0x54
#define MTK_NOR_SHREG8_REG		0x58
#define MTK_NOR_SHREG9_REG		0x5c
#define MTK_NOR_CFG1_REG		0x60
#define MTK_NOR_CFG2_REG		0x64
#define MTK_NOR_CFG3_REG		0x68
#define MTK_NOR_STATUS0_REG		0x70
#define MTK_NOR_STATUS1_REG		0x74
#define MTK_NOR_STATUS2_REG		0x78
#define MTK_NOR_STATUS3_REG		0x7c
#define MTK_NOR_FLHCFG_REG		0x84
#define MTK_NOR_TIME_REG		0x94
#define MTK_NOR_PP_DATA_REG		0x98
#define MTK_NOR_PREBUF_STUS_REG		0x9c
#define MTK_NOR_DELSEL0_REG		0xa0
#define MTK_NOR_DELSEL1_REG		0xa4
#define MTK_NOR_INTRSTUS_REG		0xa8
#define MTK_NOR_INTREN_REG		0xac
#define MTK_NOR_CHKSUM_CTL_REG		0xb8
#define MTK_NOR_CHKSUM_REG		0xbc
#define MTK_NOR_CMD2_REG		0xc0
#define MTK_NOR_WRPROT_REG		0xc4
#define MTK_NOR_RADR3_REG		0xc8
#define MTK_NOR_DUAL_REG		0xcc
#define MTK_NOR_DELSEL2_REG		0xd0
#define MTK_NOR_DELSEL3_REG		0xd4
#define MTK_NOR_DELSEL4_REG		0xd8

/* commands for mtk nor controller */
#define MTK_NOR_READ_CMD		0x0
#define MTK_NOR_RDSR_CMD		0x2
#define MTK_NOR_PRG_CMD			0x4
#define MTK_NOR_WR_CMD			0x10
#define MTK_NOR_PIO_WR_CMD		0x90
#define MTK_NOR_WRSR_CMD		0x20
#define MTK_NOR_PIO_READ_CMD		0x81
#define MTK_NOR_WR_BUF_ENABLE		0x1
#define MTK_NOR_WR_BUF_DISABLE		0x0
#define MTK_NOR_ENABLE_SF_CMD		0x30
#define MTK_NOR_DUAD_ADDR_EN		0x8
#define MTK_NOR_QUAD_READ_EN		0x4
#define MTK_NOR_DUAL_ADDR_EN		0x2
#define MTK_NOR_DUAL_READ_EN		0x1
#define MTK_NOR_DUAL_DISABLE		0x0
#define MTK_NOR_FAST_READ		0x1

#define SFLASH_WRBUF_SIZE		128

/* Can shift up to 48 bits (6 bytes) of TX/RX */
#define MTK_NOR_MAX_RX_TX_SHIFT		6
/* can shift up to 56 bits (7 bytes) transfer by MTK_NOR_PRG_CMD */
#define MTK_NOR_MAX_SHIFT		7

/* Helpers for accessing the program data / shift data registers */
#define MTK_NOR_PRG_REG(n)		(MTK_NOR_PRGDATA0_REG + 4 * (n))
#define MTK_NOR_SHREG(n)		(MTK_NOR_SHREG0_REG + 4 * (n))

struct mt8173_nor {
	struct spi_nor nor;
	struct device *dev;
	void __iomem *base;	/* nor flash base address */
	struct clk *spi_clk;
	struct clk *nor_clk;
};

static void mt8173_nor_set_read_mode(struct mt8173_nor *mt8173_nor)
{
	struct spi_nor *nor = &mt8173_nor->nor;

	switch (nor->flash_read) {
	case SPI_NOR_FAST:
		writeb(nor->read_opcode, mt8173_nor->base +
		       MTK_NOR_PRGDATA3_REG);
		writeb(MTK_NOR_FAST_READ, mt8173_nor->base +
		       MTK_NOR_CFG1_REG);
		break;
	case SPI_NOR_DUAL:
		writeb(nor->read_opcode, mt8173_nor->base +
		       MTK_NOR_PRGDATA3_REG);
		writeb(MTK_NOR_DUAL_READ_EN, mt8173_nor->base +
		       MTK_NOR_DUAL_REG);
		break;
	case SPI_NOR_QUAD:
		writeb(nor->read_opcode, mt8173_nor->base +
		       MTK_NOR_PRGDATA4_REG);
		writeb(MTK_NOR_QUAD_READ_EN, mt8173_nor->base +
		       MTK_NOR_DUAL_REG);
		break;
	default:
		writeb(MTK_NOR_DUAL_DISABLE, mt8173_nor->base +
		       MTK_NOR_DUAL_REG);
		break;
	}
}

static int mt8173_nor_execute_cmd(struct mt8173_nor *mt8173_nor, u8 cmdval)
{
	int reg;
	u8 val = cmdval & 0x1f;

	writeb(cmdval, mt8173_nor->base + MTK_NOR_CMD_REG);
	return readl_poll_timeout(mt8173_nor->base + MTK_NOR_CMD_REG, reg,
				  !(reg & val), 100, 10000);
}

static int mt8173_nor_do_tx_rx(struct mt8173_nor *mt8173_nor, u8 op,
			       u8 *tx, int txlen, u8 *rx, int rxlen)
{
	int len = 1 + txlen + rxlen;
	int i, ret, idx;

	if (len > MTK_NOR_MAX_SHIFT)
		return -EINVAL;

	writeb(len * 8, mt8173_nor->base + MTK_NOR_CNT_REG);

	/* start at PRGDATA5, go down to PRGDATA0 */
	idx = MTK_NOR_MAX_RX_TX_SHIFT - 1;

	/* opcode */
	writeb(op, mt8173_nor->base + MTK_NOR_PRG_REG(idx));
	idx--;

	/* program TX data */
	for (i = 0; i < txlen; i++, idx--)
		writeb(tx[i], mt8173_nor->base + MTK_NOR_PRG_REG(idx));

	/* clear out rest of TX registers */
	while (idx >= 0) {
		writeb(0, mt8173_nor->base + MTK_NOR_PRG_REG(idx));
		idx--;
	}

	ret = mt8173_nor_execute_cmd(mt8173_nor, MTK_NOR_PRG_CMD);
	if (ret)
		return ret;

	/* restart at first RX byte */
	idx = rxlen - 1;

	/* read out RX data */
	for (i = 0; i < rxlen; i++, idx--)
		rx[i] = readb(mt8173_nor->base + MTK_NOR_SHREG(idx));

	return 0;
}

/* Do a WRSR (Write Status Register) command */
static int mt8173_nor_wr_sr(struct mt8173_nor *mt8173_nor, u8 sr)
{
	writeb(sr, mt8173_nor->base + MTK_NOR_PRGDATA5_REG);
	writeb(8, mt8173_nor->base + MTK_NOR_CNT_REG);
	return mt8173_nor_execute_cmd(mt8173_nor, MTK_NOR_WRSR_CMD);
}

static int mt8173_nor_write_buffer_enable(struct mt8173_nor *mt8173_nor)
{
	u8 reg;

	/* the bit0 of MTK_NOR_CFG2_REG is pre-fetch buffer
	 * 0: pre-fetch buffer use for read
	 * 1: pre-fetch buffer use for page program
	 */
	writel(MTK_NOR_WR_BUF_ENABLE, mt8173_nor->base + MTK_NOR_CFG2_REG);
	return readb_poll_timeout(mt8173_nor->base + MTK_NOR_CFG2_REG, reg,
				  0x01 == (reg & 0x01), 100, 10000);
}

static int mt8173_nor_write_buffer_disable(struct mt8173_nor *mt8173_nor)
{
	u8 reg;

	writel(MTK_NOR_WR_BUF_DISABLE, mt8173_nor->base + MTK_NOR_CFG2_REG);
	return readb_poll_timeout(mt8173_nor->base + MTK_NOR_CFG2_REG, reg,
				  MTK_NOR_WR_BUF_DISABLE == (reg & 0x1), 100,
				  10000);
}

static void mt8173_nor_set_addr(struct mt8173_nor *mt8173_nor, u32 addr)
{
	int i;

	for (i = 0; i < 3; i++) {
		writeb(addr & 0xff, mt8173_nor->base + MTK_NOR_RADR0_REG + i * 4);
		addr >>= 8;
	}
	/* Last register is non-contiguous */
	writeb(addr & 0xff, mt8173_nor->base + MTK_NOR_RADR3_REG);
}

static ssize_t mt8173_nor_read(struct spi_nor *nor, loff_t from, size_t length,
			       u_char *buffer)
{
	int i, ret;
	int addr = (int)from;
	u8 *buf = (u8 *)buffer;
	struct mt8173_nor *mt8173_nor = nor->priv;

	/* set mode for fast read mode ,dual mode or quad mode */
	mt8173_nor_set_read_mode(mt8173_nor);
	mt8173_nor_set_addr(mt8173_nor, addr);

	for (i = 0; i < length; i++) {
		ret = mt8173_nor_execute_cmd(mt8173_nor, MTK_NOR_PIO_READ_CMD);
		if (ret < 0)
			return ret;
		buf[i] = readb(mt8173_nor->base + MTK_NOR_RDATA_REG);
	}
	return length;
}

static int mt8173_nor_write_single_byte(struct mt8173_nor *mt8173_nor,
					int addr, int length, u8 *data)
{
	int i, ret;

	mt8173_nor_set_addr(mt8173_nor, addr);

	for (i = 0; i < length; i++) {
		writeb(*data++, mt8173_nor->base + MTK_NOR_WDATA_REG);
		ret = mt8173_nor_execute_cmd(mt8173_nor, MTK_NOR_PIO_WR_CMD);
		if (ret < 0)
			return ret;
	}
	return 0;
}

static int mt8173_nor_write_buffer(struct mt8173_nor *mt8173_nor, int addr,
				   const u8 *buf)
{
	int i, bufidx, data;

	mt8173_nor_set_addr(mt8173_nor, addr);

	bufidx = 0;
	for (i = 0; i < SFLASH_WRBUF_SIZE; i += 4) {
		data = buf[bufidx + 3]<<24 | buf[bufidx + 2]<<16 |
		       buf[bufidx + 1]<<8 | buf[bufidx];
		bufidx += 4;
		writel(data, mt8173_nor->base + MTK_NOR_PP_DATA_REG);
	}
	return mt8173_nor_execute_cmd(mt8173_nor, MTK_NOR_WR_CMD);
}

static ssize_t mt8173_nor_write(struct spi_nor *nor, loff_t to, size_t len,
				const u_char *buf)
{
	int ret;
	struct mt8173_nor *mt8173_nor = nor->priv;
	size_t i;

	ret = mt8173_nor_write_buffer_enable(mt8173_nor);
	if (ret < 0) {
		dev_warn(mt8173_nor->dev, "write buffer enable failed!\n");
		return ret;
	}

	for (i = 0; i + SFLASH_WRBUF_SIZE <= len; i += SFLASH_WRBUF_SIZE) {
		ret = mt8173_nor_write_buffer(mt8173_nor, to, buf);
		if (ret < 0) {
			dev_err(mt8173_nor->dev, "write buffer failed!\n");
			return ret;
		}
		to += SFLASH_WRBUF_SIZE;
		buf += SFLASH_WRBUF_SIZE;
	}
	ret = mt8173_nor_write_buffer_disable(mt8173_nor);
	if (ret < 0) {
		dev_warn(mt8173_nor->dev, "write buffer disable failed!\n");
		return ret;
	}

	if (i < len) {
		ret = mt8173_nor_write_single_byte(mt8173_nor, to,
						   (int)(len - i), (u8 *)buf);
		if (ret < 0) {
			dev_err(mt8173_nor->dev, "write single byte failed!\n");
			return ret;
		}
	}

	return len;
}

static int mt8173_nor_read_reg(struct spi_nor *nor, u8 opcode, u8 *buf, int len)
{
	int ret;
	struct mt8173_nor *mt8173_nor = nor->priv;

	switch (opcode) {
	case SPINOR_OP_RDSR:
		ret = mt8173_nor_execute_cmd(mt8173_nor, MTK_NOR_RDSR_CMD);
		if (ret < 0)
			return ret;
		if (len == 1)
			*buf = readb(mt8173_nor->base + MTK_NOR_RDSR_REG);
		else
			dev_err(mt8173_nor->dev, "len should be 1 for read status!\n");
		break;
	default:
		ret = mt8173_nor_do_tx_rx(mt8173_nor, opcode, NULL, 0, buf, len);
		break;
	}
	return ret;
}

static int mt8173_nor_write_reg(struct spi_nor *nor, u8 opcode, u8 *buf,
				int len)
{
	int ret;
	struct mt8173_nor *mt8173_nor = nor->priv;

	switch (opcode) {
	case SPINOR_OP_WRSR:
		/* We only handle 1 byte */
		ret = mt8173_nor_wr_sr(mt8173_nor, *buf);
		break;
	default:
		ret = mt8173_nor_do_tx_rx(mt8173_nor, opcode, buf, len, NULL, 0);
		if (ret)
			dev_warn(mt8173_nor->dev, "write reg failure!\n");
		break;
	}
	return ret;
}

static int mtk_nor_init(struct mt8173_nor *mt8173_nor,
			struct device_node *flash_node)
{
	int ret;
	struct spi_nor *nor;

	/* initialize controller to accept commands */
	writel(MTK_NOR_ENABLE_SF_CMD, mt8173_nor->base + MTK_NOR_WRPROT_REG);

	nor = &mt8173_nor->nor;
	nor->dev = mt8173_nor->dev;
	nor->priv = mt8173_nor;
	spi_nor_set_flash_node(nor, flash_node);

	/* fill the hooks to spi nor */
	nor->read = mt8173_nor_read;
	nor->read_reg = mt8173_nor_read_reg;
	nor->write = mt8173_nor_write;
	nor->write_reg = mt8173_nor_write_reg;
	nor->mtd.name = "mtk_nor";
	/* initialized with NULL */
	ret = spi_nor_scan(nor, NULL, SPI_NOR_DUAL);
	if (ret)
		return ret;

	return mtd_device_register(&nor->mtd, NULL, 0);
}

static int mtk_nor_drv_probe(struct platform_device *pdev)
{
	struct device_node *flash_np;
	struct resource *res;
	int ret;
	struct mt8173_nor *mt8173_nor;

	if (!pdev->dev.of_node) {
		dev_err(&pdev->dev, "No DT found\n");
		return -EINVAL;
	}

	mt8173_nor = devm_kzalloc(&pdev->dev, sizeof(*mt8173_nor), GFP_KERNEL);
	if (!mt8173_nor)
		return -ENOMEM;
	platform_set_drvdata(pdev, mt8173_nor);

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	mt8173_nor->base = devm_ioremap_resource(&pdev->dev, res);
	if (IS_ERR(mt8173_nor->base))
		return PTR_ERR(mt8173_nor->base);

	mt8173_nor->spi_clk = devm_clk_get(&pdev->dev, "spi");
	if (IS_ERR(mt8173_nor->spi_clk))
		return PTR_ERR(mt8173_nor->spi_clk);

	mt8173_nor->nor_clk = devm_clk_get(&pdev->dev, "sf");
	if (IS_ERR(mt8173_nor->nor_clk))
		return PTR_ERR(mt8173_nor->nor_clk);

	mt8173_nor->dev = &pdev->dev;
	ret = clk_prepare_enable(mt8173_nor->spi_clk);
	if (ret)
		return ret;

	ret = clk_prepare_enable(mt8173_nor->nor_clk);
	if (ret) {
		clk_disable_unprepare(mt8173_nor->spi_clk);
		return ret;
	}
	/* only support one attached flash */
	flash_np = of_get_next_available_child(pdev->dev.of_node, NULL);
	if (!flash_np) {
		dev_err(&pdev->dev, "no SPI flash device to configure\n");
		ret = -ENODEV;
		goto nor_free;
	}
	ret = mtk_nor_init(mt8173_nor, flash_np);

nor_free:
	if (ret) {
		clk_disable_unprepare(mt8173_nor->spi_clk);
		clk_disable_unprepare(mt8173_nor->nor_clk);
	}
	return ret;
}

static int mtk_nor_drv_remove(struct platform_device *pdev)
{
	struct mt8173_nor *mt8173_nor = platform_get_drvdata(pdev);

	clk_disable_unprepare(mt8173_nor->spi_clk);
	clk_disable_unprepare(mt8173_nor->nor_clk);
	return 0;
}

static const struct of_device_id mtk_nor_of_ids[] = {
	{ .compatible = "mediatek,mt8173-nor"},
	{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, mtk_nor_of_ids);

static struct platform_driver mtk_nor_driver = {
	.probe = mtk_nor_drv_probe,
	.remove = mtk_nor_drv_remove,
	.driver = {
		.name = "mtk-nor",
		.of_match_table = mtk_nor_of_ids,
	},
};

module_platform_driver(mtk_nor_driver);
MODULE_LICENSE("GPL v2");
MODULE_DESCRIPTION("MediaTek SPI NOR Flash Driver");
Commit	Line	Data
3ce351b5 BC	1	/*
	2	* Copyright (c) 2015 MediaTek Inc.
	3	* Author: Bayi Cheng <bayi.cheng@mediatek.com>
	4	*
	5	* This program is free software; you can redistribute it and/or modify
	6	* it under the terms of the GNU General Public License version 2 as
	7	* published by the Free Software Foundation.
	8	*
	9	* This program is distributed in the hope that it will be useful,
	10	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	11	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	12	* GNU General Public License for more details.
	13	*/
	14
	15	#include <linux/clk.h>
	16	#include <linux/delay.h>
	17	#include <linux/device.h>
	18	#include <linux/init.h>
	19	#include <linux/io.h>
	20	#include <linux/iopoll.h>
	21	#include <linux/ioport.h>
	22	#include <linux/math64.h>
	23	#include <linux/module.h>
3ce351b5 BC	24	#include <linux/mutex.h>
	25	#include <linux/of.h>
	26	#include <linux/of_device.h>
	27	#include <linux/pinctrl/consumer.h>
	28	#include <linux/platform_device.h>
	29	#include <linux/slab.h>
	30	#include <linux/mtd/mtd.h>
	31	#include <linux/mtd/partitions.h>
	32	#include <linux/mtd/spi-nor.h>
	33
	34	#define MTK_NOR_CMD_REG 0x00
	35	#define MTK_NOR_CNT_REG 0x04
	36	#define MTK_NOR_RDSR_REG 0x08
	37	#define MTK_NOR_RDATA_REG 0x0c
	38	#define MTK_NOR_RADR0_REG 0x10
	39	#define MTK_NOR_RADR1_REG 0x14
	40	#define MTK_NOR_RADR2_REG 0x18
	41	#define MTK_NOR_WDATA_REG 0x1c
	42	#define MTK_NOR_PRGDATA0_REG 0x20
	43	#define MTK_NOR_PRGDATA1_REG 0x24
	44	#define MTK_NOR_PRGDATA2_REG 0x28
	45	#define MTK_NOR_PRGDATA3_REG 0x2c
	46	#define MTK_NOR_PRGDATA4_REG 0x30
	47	#define MTK_NOR_PRGDATA5_REG 0x34
	48	#define MTK_NOR_SHREG0_REG 0x38
	49	#define MTK_NOR_SHREG1_REG 0x3c
	50	#define MTK_NOR_SHREG2_REG 0x40
	51	#define MTK_NOR_SHREG3_REG 0x44
	52	#define MTK_NOR_SHREG4_REG 0x48
	53	#define MTK_NOR_SHREG5_REG 0x4c
	54	#define MTK_NOR_SHREG6_REG 0x50
	55	#define MTK_NOR_SHREG7_REG 0x54
	56	#define MTK_NOR_SHREG8_REG 0x58
	57	#define MTK_NOR_SHREG9_REG 0x5c
	58	#define MTK_NOR_CFG1_REG 0x60
	59	#define MTK_NOR_CFG2_REG 0x64
	60	#define MTK_NOR_CFG3_REG 0x68
	61	#define MTK_NOR_STATUS0_REG 0x70
	62	#define MTK_NOR_STATUS1_REG 0x74
	63	#define MTK_NOR_STATUS2_REG 0x78
	64	#define MTK_NOR_STATUS3_REG 0x7c
	65	#define MTK_NOR_FLHCFG_REG 0x84
	66	#define MTK_NOR_TIME_REG 0x94
	67	#define MTK_NOR_PP_DATA_REG 0x98
	68	#define MTK_NOR_PREBUF_STUS_REG 0x9c
	69	#define MTK_NOR_DELSEL0_REG 0xa0
	70	#define MTK_NOR_DELSEL1_REG 0xa4
	71	#define MTK_NOR_INTRSTUS_REG 0xa8
	72	#define MTK_NOR_INTREN_REG 0xac
	73	#define MTK_NOR_CHKSUM_CTL_REG 0xb8
	74	#define MTK_NOR_CHKSUM_REG 0xbc
	75	#define MTK_NOR_CMD2_REG 0xc0
	76	#define MTK_NOR_WRPROT_REG 0xc4
	77	#define MTK_NOR_RADR3_REG 0xc8
	78	#define MTK_NOR_DUAL_REG 0xcc
	79	#define MTK_NOR_DELSEL2_REG 0xd0
	80	#define MTK_NOR_DELSEL3_REG 0xd4
	81	#define MTK_NOR_DELSEL4_REG 0xd8
	82
	83	/* commands for mtk nor controller */
	84	#define MTK_NOR_READ_CMD 0x0
	85	#define MTK_NOR_RDSR_CMD 0x2
	86	#define MTK_NOR_PRG_CMD 0x4
	87	#define MTK_NOR_WR_CMD 0x10
88	#define MTK_NOR_PIO_WR_CMD 0x90
89	#define MTK_NOR_WRSR_CMD 0x20
90	#define MTK_NOR_PIO_READ_CMD 0x81
91	#define MTK_NOR_WR_BUF_ENABLE 0x1
92	#define MTK_NOR_WR_BUF_DISABLE 0x0
93	#define MTK_NOR_ENABLE_SF_CMD 0x30
94	#define MTK_NOR_DUAD_ADDR_EN 0x8
95	#define MTK_NOR_QUAD_READ_EN 0x4
96	#define MTK_NOR_DUAL_ADDR_EN 0x2
97	#define MTK_NOR_DUAL_READ_EN 0x1
98	#define MTK_NOR_DUAL_DISABLE 0x0
99	#define MTK_NOR_FAST_READ 0x1
100
101	#define SFLASH_WRBUF_SIZE 128
102
103	/* Can shift up to 48 bits (6 bytes) of TX/RX */
104	#define MTK_NOR_MAX_RX_TX_SHIFT 6
105	/* can shift up to 56 bits (7 bytes) transfer by MTK_NOR_PRG_CMD */
106	#define MTK_NOR_MAX_SHIFT 7
107
108	/* Helpers for accessing the program data / shift data registers */
109	#define MTK_NOR_PRG_REG(n) (MTK_NOR_PRGDATA0_REG + 4 * (n))
110	#define MTK_NOR_SHREG(n) (MTK_NOR_SHREG0_REG + 4 * (n))
111
112	struct mt8173_nor {
113	struct spi_nor nor;
114	struct device *dev;
115	void __iomem base; / nor flash base address */
116	struct clk *spi_clk;
117	struct clk *nor_clk;
118	};
119
120	static void mt8173_nor_set_read_mode(struct mt8173_nor *mt8173_nor)
121	{
122	struct spi_nor *nor = &mt8173_nor->nor;
123
124	switch (nor->flash_read) {
125	case SPI_NOR_FAST:
126	writeb(nor->read_opcode, mt8173_nor->base +
127	MTK_NOR_PRGDATA3_REG);
128	writeb(MTK_NOR_FAST_READ, mt8173_nor->base +
129	MTK_NOR_CFG1_REG);
130	break;
131	case SPI_NOR_DUAL:
132	writeb(nor->read_opcode, mt8173_nor->base +
133	MTK_NOR_PRGDATA3_REG);
134	writeb(MTK_NOR_DUAL_READ_EN, mt8173_nor->base +
135	MTK_NOR_DUAL_REG);
136	break;
137	case SPI_NOR_QUAD:
138	writeb(nor->read_opcode, mt8173_nor->base +
139	MTK_NOR_PRGDATA4_REG);
140	writeb(MTK_NOR_QUAD_READ_EN, mt8173_nor->base +
141	MTK_NOR_DUAL_REG);
142	break;
143	default:
144	writeb(MTK_NOR_DUAL_DISABLE, mt8173_nor->base +
145	MTK_NOR_DUAL_REG);
146	break;
147	}
148	}
149
150	static int mt8173_nor_execute_cmd(struct mt8173_nor *mt8173_nor, u8 cmdval)
151	{
152	int reg;
153	u8 val = cmdval & 0x1f;
154
155	writeb(cmdval, mt8173_nor->base + MTK_NOR_CMD_REG);
156	return readl_poll_timeout(mt8173_nor->base + MTK_NOR_CMD_REG, reg,
157	!(reg & val), 100, 10000);
158	}
159
160	static int mt8173_nor_do_tx_rx(struct mt8173_nor *mt8173_nor, u8 op,
161	u8 tx, int txlen, u8 rx, int rxlen)
162	{
163	int len = 1 + txlen + rxlen;
164	int i, ret, idx;
165
166	if (len > MTK_NOR_MAX_SHIFT)
167	return -EINVAL;
168
169	writeb(len * 8, mt8173_nor->base + MTK_NOR_CNT_REG);
170
171	/* start at PRGDATA5, go down to PRGDATA0 */
172	idx = MTK_NOR_MAX_RX_TX_SHIFT - 1;
173
174	/* opcode */
175	writeb(op, mt8173_nor->base + MTK_NOR_PRG_REG(idx));
176	idx--;
177
178	/* program TX data */
179	for (i = 0; i < txlen; i++, idx--)
180	writeb(tx[i], mt8173_nor->base + MTK_NOR_PRG_REG(idx));
181
182	/* clear out rest of TX registers */
183	while (idx >= 0) {
184	writeb(0, mt8173_nor->base + MTK_NOR_PRG_REG(idx));
185	idx--;
186	}
187
188	ret = mt8173_nor_execute_cmd(mt8173_nor, MTK_NOR_PRG_CMD);
189	if (ret)
190	return ret;
191
192	/* restart at first RX byte */
193	idx = rxlen - 1;
194
195	/* read out RX data */
196	for (i = 0; i < rxlen; i++, idx--)
197	rx[i] = readb(mt8173_nor->base + MTK_NOR_SHREG(idx));
198
199	return 0;
200	}
201
202	/* Do a WRSR (Write Status Register) command */
203	static int mt8173_nor_wr_sr(struct mt8173_nor *mt8173_nor, u8 sr)
204	{
205	writeb(sr, mt8173_nor->base + MTK_NOR_PRGDATA5_REG);
206	writeb(8, mt8173_nor->base + MTK_NOR_CNT_REG);
207	return mt8173_nor_execute_cmd(mt8173_nor, MTK_NOR_WRSR_CMD);
208	}
209
210	static int mt8173_nor_write_buffer_enable(struct mt8173_nor *mt8173_nor)
211	{
212	u8 reg;
213
214	/* the bit0 of MTK_NOR_CFG2_REG is pre-fetch buffer
215	* 0: pre-fetch buffer use for read
216	* 1: pre-fetch buffer use for page program
217	*/
218	writel(MTK_NOR_WR_BUF_ENABLE, mt8173_nor->base + MTK_NOR_CFG2_REG);
219	return readb_poll_timeout(mt8173_nor->base + MTK_NOR_CFG2_REG, reg,
220	0x01 == (reg & 0x01), 100, 10000);
221	}
222
223	static int mt8173_nor_write_buffer_disable(struct mt8173_nor *mt8173_nor)
224	{
225	u8 reg;
226
227	writel(MTK_NOR_WR_BUF_DISABLE, mt8173_nor->base + MTK_NOR_CFG2_REG);
228	return readb_poll_timeout(mt8173_nor->base + MTK_NOR_CFG2_REG, reg,
229	MTK_NOR_WR_BUF_DISABLE == (reg & 0x1), 100,
230	10000);
231	}
232
233	static void mt8173_nor_set_addr(struct mt8173_nor *mt8173_nor, u32 addr)
234	{
235	int i;
236
237	for (i = 0; i < 3; i++) {
238	writeb(addr & 0xff, mt8173_nor->base + MTK_NOR_RADR0_REG + i * 4);
239	addr >>= 8;
240	}
241	/* Last register is non-contiguous */
242	writeb(addr & 0xff, mt8173_nor->base + MTK_NOR_RADR3_REG);
243	}
244
59451e12	245	static ssize_t mt8173_nor_read(struct spi_nor *nor, loff_t from, size_t length,
2dd087b1	246	u_char *buffer)
3ce351b5 BC	247	{
	248	int i, ret;
	249	int addr = (int)from;
	250	u8 buf = (u8 )buffer;
	251	struct mt8173_nor *mt8173_nor = nor->priv;
	252
	253	/* set mode for fast read mode ,dual mode or quad mode */
	254	mt8173_nor_set_read_mode(mt8173_nor);
	255	mt8173_nor_set_addr(mt8173_nor, addr);
	256
2dd087b1	257	for (i = 0; i < length; i++) {
3ce351b5 BC	258	ret = mt8173_nor_execute_cmd(mt8173_nor, MTK_NOR_PIO_READ_CMD);
	259	if (ret < 0)
	260	return ret;
	261	buf[i] = readb(mt8173_nor->base + MTK_NOR_RDATA_REG);
	262	}
78b400fd	263	return length;
3ce351b5 BC	264	}
	265
	266	static int mt8173_nor_write_single_byte(struct mt8173_nor *mt8173_nor,
	267	int addr, int length, u8 *data)
	268	{
	269	int i, ret;
	270
	271	mt8173_nor_set_addr(mt8173_nor, addr);
	272
	273	for (i = 0; i < length; i++) {
80e1ca69	274	writeb(*data++, mt8173_nor->base + MTK_NOR_WDATA_REG);
3ce351b5 BC	275	ret = mt8173_nor_execute_cmd(mt8173_nor, MTK_NOR_PIO_WR_CMD);
	276	if (ret < 0)
	277	return ret;
3ce351b5 BC	278	}
	279	return 0;
	280	}
	281
	282	static int mt8173_nor_write_buffer(struct mt8173_nor *mt8173_nor, int addr,
	283	const u8 *buf)
	284	{
	285	int i, bufidx, data;
	286
	287	mt8173_nor_set_addr(mt8173_nor, addr);
	288
	289	bufidx = 0;
	290	for (i = 0; i < SFLASH_WRBUF_SIZE; i += 4) {
	291	data = buf[bufidx + 3]<<24 \| buf[bufidx + 2]<<16 \|
	292	buf[bufidx + 1]<<8 \| buf[bufidx];
	293	bufidx += 4;
	294	writel(data, mt8173_nor->base + MTK_NOR_PP_DATA_REG);
	295	}
	296	return mt8173_nor_execute_cmd(mt8173_nor, MTK_NOR_WR_CMD);
	297	}
	298
59451e12	299	static ssize_t mt8173_nor_write(struct spi_nor *nor, loff_t to, size_t len,
2dd087b1	300	const u_char *buf)
3ce351b5 BC	301	{
	302	int ret;
	303	struct mt8173_nor *mt8173_nor = nor->priv;
78b400fd	304	size_t i;
3ce351b5 BC	305
3ce351b5 BC	306	ret = mt8173_nor_write_buffer_enable(mt8173_nor);
59451e12	307	if (ret < 0) {
3ce351b5	308	dev_warn(mt8173_nor->dev, "write buffer enable failed!\n");
59451e12 MS	309	return ret;
59451e12 MS	310	}
3ce351b5	311
78b400fd	312	for (i = 0; i + SFLASH_WRBUF_SIZE <= len; i += SFLASH_WRBUF_SIZE) {
3ce351b5	313	ret = mt8173_nor_write_buffer(mt8173_nor, to, buf);
59451e12	314	if (ret < 0) {
3ce351b5	315	dev_err(mt8173_nor->dev, "write buffer failed!\n");
59451e12 MS	316	return ret;
59451e12 MS	317	}
3ce351b5 BC	318	to += SFLASH_WRBUF_SIZE;
3ce351b5 BC	319	buf += SFLASH_WRBUF_SIZE;
3ce351b5 BC	320	}
3ce351b5 BC	321	ret = mt8173_nor_write_buffer_disable(mt8173_nor);
59451e12	322	if (ret < 0) {
3ce351b5	323	dev_warn(mt8173_nor->dev, "write buffer disable failed!\n");
59451e12 MS	324	return ret;
59451e12 MS	325	}
3ce351b5	326
78b400fd BN	327	if (i < len) {
	328	ret = mt8173_nor_write_single_byte(mt8173_nor, to,
	329	(int)(len - i), (u8 *)buf);
59451e12	330	if (ret < 0) {
3ce351b5	331	dev_err(mt8173_nor->dev, "write single byte failed!\n");
59451e12 MS	332	return ret;
59451e12 MS	333	}
3ce351b5	334	}
59451e12	335
78b400fd	336	return len;
3ce351b5 BC	337	}
	338
	339	static int mt8173_nor_read_reg(struct spi_nor nor, u8 opcode, u8 buf, int len)
	340	{
	341	int ret;
	342	struct mt8173_nor *mt8173_nor = nor->priv;
	343
	344	switch (opcode) {
	345	case SPINOR_OP_RDSR:
	346	ret = mt8173_nor_execute_cmd(mt8173_nor, MTK_NOR_RDSR_CMD);
	347	if (ret < 0)
	348	return ret;
	349	if (len == 1)
	350	*buf = readb(mt8173_nor->base + MTK_NOR_RDSR_REG);
	351	else
	352	dev_err(mt8173_nor->dev, "len should be 1 for read status!\n");
	353	break;
	354	default:
	355	ret = mt8173_nor_do_tx_rx(mt8173_nor, opcode, NULL, 0, buf, len);
	356	break;
	357	}
	358	return ret;
	359	}
	360
	361	static int mt8173_nor_write_reg(struct spi_nor nor, u8 opcode, u8 buf,
	362	int len)
	363	{
	364	int ret;
	365	struct mt8173_nor *mt8173_nor = nor->priv;
	366
	367	switch (opcode) {
	368	case SPINOR_OP_WRSR:
	369	/* We only handle 1 byte */
	370	ret = mt8173_nor_wr_sr(mt8173_nor, *buf);
	371	break;
	372	default:
	373	ret = mt8173_nor_do_tx_rx(mt8173_nor, opcode, buf, len, NULL, 0);
	374	if (ret)
	375	dev_warn(mt8173_nor->dev, "write reg failure!\n");
	376	break;
	377	}
	378	return ret;
	379	}
	380
92752d99 GU	381	static int mtk_nor_init(struct mt8173_nor *mt8173_nor,
92752d99 GU	382	struct device_node *flash_node)
3ce351b5 BC	383	{
	384	int ret;
	385	struct spi_nor *nor;
	386
	387	/* initialize controller to accept commands */
	388	writel(MTK_NOR_ENABLE_SF_CMD, mt8173_nor->base + MTK_NOR_WRPROT_REG);
	389
	390	nor = &mt8173_nor->nor;
	391	nor->dev = mt8173_nor->dev;
	392	nor->priv = mt8173_nor;
	393	spi_nor_set_flash_node(nor, flash_node);
	394
	395	/* fill the hooks to spi nor */
	396	nor->read = mt8173_nor_read;
	397	nor->read_reg = mt8173_nor_read_reg;
	398	nor->write = mt8173_nor_write;
	399	nor->write_reg = mt8173_nor_write_reg;
3ce351b5 BC	400	nor->mtd.name = "mtk_nor";
	401	/* initialized with NULL */
	402	ret = spi_nor_scan(nor, NULL, SPI_NOR_DUAL);
	403	if (ret)
	404	return ret;
	405
	406	return mtd_device_register(&nor->mtd, NULL, 0);
	407	}
	408
	409	static int mtk_nor_drv_probe(struct platform_device *pdev)
	410	{
	411	struct device_node *flash_np;
	412	struct resource *res;
	413	int ret;
	414	struct mt8173_nor *mt8173_nor;
	415
	416	if (!pdev->dev.of_node) {
	417	dev_err(&pdev->dev, "No DT found\n");
	418	return -EINVAL;
	419	}
	420
	421	mt8173_nor = devm_kzalloc(&pdev->dev, sizeof(*mt8173_nor), GFP_KERNEL);
	422	if (!mt8173_nor)
	423	return -ENOMEM;
	424	platform_set_drvdata(pdev, mt8173_nor);
	425
	426	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	427	mt8173_nor->base = devm_ioremap_resource(&pdev->dev, res);
	428	if (IS_ERR(mt8173_nor->base))
	429	return PTR_ERR(mt8173_nor->base);
	430
	431	mt8173_nor->spi_clk = devm_clk_get(&pdev->dev, "spi");
	432	if (IS_ERR(mt8173_nor->spi_clk))
	433	return PTR_ERR(mt8173_nor->spi_clk);
	434
	435	mt8173_nor->nor_clk = devm_clk_get(&pdev->dev, "sf");
	436	if (IS_ERR(mt8173_nor->nor_clk))
	437	return PTR_ERR(mt8173_nor->nor_clk);
	438
	439	mt8173_nor->dev = &pdev->dev;
	440	ret = clk_prepare_enable(mt8173_nor->spi_clk);
	441	if (ret)
	442	return ret;
	443
	444	ret = clk_prepare_enable(mt8173_nor->nor_clk);
	445	if (ret) {
	446	clk_disable_unprepare(mt8173_nor->spi_clk);
	447	return ret;
	448	}
	449	/* only support one attached flash */
	450	flash_np = of_get_next_available_child(pdev->dev.of_node, NULL);
	451	if (!flash_np) {
	452	dev_err(&pdev->dev, "no SPI flash device to configure\n");
	453	ret = -ENODEV;
	454	goto nor_free;
	455	}
	456	ret = mtk_nor_init(mt8173_nor, flash_np);
	457
	458	nor_free:
	459	if (ret) {
	460	clk_disable_unprepare(mt8173_nor->spi_clk);
	461	clk_disable_unprepare(mt8173_nor->nor_clk);
	462	}
	463	return ret;
464	}
465
466	static int mtk_nor_drv_remove(struct platform_device *pdev)
467	{
468	struct mt8173_nor *mt8173_nor = platform_get_drvdata(pdev);
469
470	clk_disable_unprepare(mt8173_nor->spi_clk);
471	clk_disable_unprepare(mt8173_nor->nor_clk);
472	return 0;
473	}
474
475	static const struct of_device_id mtk_nor_of_ids[] = {
476	{ .compatible = "mediatek,mt8173-nor"},
477	{ /* sentinel */ }
478	};
479	MODULE_DEVICE_TABLE(of, mtk_nor_of_ids);
480
481	static struct platform_driver mtk_nor_driver = {
482	.probe = mtk_nor_drv_probe,
483	.remove = mtk_nor_drv_remove,
484	.driver = {
485	.name = "mtk-nor",
486	.of_match_table = mtk_nor_of_ids,
487	},
488	};
489
490	module_platform_driver(mtk_nor_driver);
491	MODULE_LICENSE("GPL v2");
492	MODULE_DESCRIPTION("MediaTek SPI NOR Flash Driver");