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mtd: spi-nor: drop jedec_probe /helper/ function
[deliverable/linux.git] / drivers / mtd / spi-nor / spi-nor.c
CommitLineData
b199489d 1/*
8eabdd1e
HS		 2 * Based on m25p80.c, by Mike Lavender (mike@steroidmicros.com), with
3 * influence from lart.c (Abraham Van Der Merwe) and mtd_dataflash.c
4 *
5 * Copyright (C) 2005, Intec Automation Inc.
6 * Copyright (C) 2014, Freescale Semiconductor, Inc.
b199489d
HS		 7 *
8 * This code is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13#include <linux/err.h>
14#include <linux/errno.h>
15#include <linux/module.h>
16#include <linux/device.h>
17#include <linux/mutex.h>
18#include <linux/math64.h>
19
20#include <linux/mtd/cfi.h>
21#include <linux/mtd/mtd.h>
22#include <linux/of_platform.h>
23#include <linux/spi/flash.h>
24#include <linux/mtd/spi-nor.h>
25
26/* Define max times to check status register before we give up. */
27#define MAX_READY_WAIT_JIFFIES (40 * HZ) /* M25P16 specs 40s max chip erase */
28
29#define JEDEC_MFR(_jedec_id) ((_jedec_id) >> 16)
30
31/*
32 * Read the status register, returning its value in the location
33 * Return the status register value.
34 * Returns negative if error occurred.
35 */
36static int read_sr(struct spi_nor *nor)
37{
38 int ret;
39 u8 val;
40
b02e7f3e 41 ret = nor->read_reg(nor, SPINOR_OP_RDSR, &val, 1);
b199489d
HS		 42 if (ret < 0) {
43 pr_err("error %d reading SR\n", (int) ret);
44 return ret;
45 }
46
47 return val;
48}
49
c14dedde 50/*
51 * Read the flag status register, returning its value in the location
52 * Return the status register value.
53 * Returns negative if error occurred.
54 */
55static int read_fsr(struct spi_nor *nor)
56{
57 int ret;
58 u8 val;
59
60 ret = nor->read_reg(nor, SPINOR_OP_RDFSR, &val, 1);
61 if (ret < 0) {
62 pr_err("error %d reading FSR\n", ret);
63 return ret;
64 }
65
66 return val;
67}
68
b199489d
HS		 69/*
70 * Read configuration register, returning its value in the
71 * location. Return the configuration register value.
72 * Returns negative if error occured.
73 */
74static int read_cr(struct spi_nor *nor)
75{
76 int ret;
77 u8 val;
78
b02e7f3e 79 ret = nor->read_reg(nor, SPINOR_OP_RDCR, &val, 1);
b199489d
HS		 80 if (ret < 0) {
81 dev_err(nor->dev, "error %d reading CR\n", ret);
82 return ret;
83 }
84
85 return val;
86}
87
88/*
89 * Dummy Cycle calculation for different type of read.
90 * It can be used to support more commands with
91 * different dummy cycle requirements.
92 */
93static inline int spi_nor_read_dummy_cycles(struct spi_nor *nor)
94{
95 switch (nor->flash_read) {
96 case SPI_NOR_FAST:
97 case SPI_NOR_DUAL:
98 case SPI_NOR_QUAD:
99 return 1;
100 case SPI_NOR_NORMAL:
101 return 0;
102 }
103 return 0;
104}
105
106/*
107 * Write status register 1 byte
108 * Returns negative if error occurred.
109 */
110static inline int write_sr(struct spi_nor *nor, u8 val)
111{
112 nor->cmd_buf[0] = val;
b02e7f3e 113 return nor->write_reg(nor, SPINOR_OP_WRSR, nor->cmd_buf, 1, 0);
b199489d
HS		 114}
115
116/*
117 * Set write enable latch with Write Enable command.
118 * Returns negative if error occurred.
119 */
120static inline int write_enable(struct spi_nor *nor)
121{
b02e7f3e 122 return nor->write_reg(nor, SPINOR_OP_WREN, NULL, 0, 0);
b199489d
HS		 123}
124
125/*
126 * Send write disble instruction to the chip.
127 */
128static inline int write_disable(struct spi_nor *nor)
129{
b02e7f3e 130 return nor->write_reg(nor, SPINOR_OP_WRDI, NULL, 0, 0);
b199489d
HS		 131}
132
133static inline struct spi_nor *mtd_to_spi_nor(struct mtd_info *mtd)
134{
135 return mtd->priv;
136}
137
138/* Enable/disable 4-byte addressing mode. */
139static inline int set_4byte(struct spi_nor *nor, u32 jedec_id, int enable)
140{
141 int status;
142 bool need_wren = false;
143 u8 cmd;
144
145 switch (JEDEC_MFR(jedec_id)) {
146 case CFI_MFR_ST: /* Micron, actually */
147 /* Some Micron need WREN command; all will accept it */
148 need_wren = true;
149 case CFI_MFR_MACRONIX:
150 case 0xEF /* winbond */:
151 if (need_wren)
152 write_enable(nor);
153
b02e7f3e 154 cmd = enable ? SPINOR_OP_EN4B : SPINOR_OP_EX4B;
b199489d
HS		 155 status = nor->write_reg(nor, cmd, NULL, 0, 0);
156 if (need_wren)
157 write_disable(nor);
158
159 return status;
160 default:
161 /* Spansion style */
162 nor->cmd_buf[0] = enable << 7;
b02e7f3e 163 return nor->write_reg(nor, SPINOR_OP_BRWR, nor->cmd_buf, 1, 0);
b199489d
HS		 164 }
165}
166
167static int spi_nor_wait_till_ready(struct spi_nor *nor)
168{
169 unsigned long deadline;
170 int sr;
171
172 deadline = jiffies + MAX_READY_WAIT_JIFFIES;
173
174 do {
175 cond_resched();
176
177 sr = read_sr(nor);
178 if (sr < 0)
179 break;
180 else if (!(sr & SR_WIP))
181 return 0;
182 } while (!time_after_eq(jiffies, deadline));
183
184 return -ETIMEDOUT;
185}
186
c14dedde 187static int spi_nor_wait_till_fsr_ready(struct spi_nor *nor)
188{
189 unsigned long deadline;
190 int sr;
191 int fsr;
192
193 deadline = jiffies + MAX_READY_WAIT_JIFFIES;
194
195 do {
196 cond_resched();
197
198 sr = read_sr(nor);
199 if (sr < 0) {
200 break;
201 } else if (!(sr & SR_WIP)) {
202 fsr = read_fsr(nor);
203 if (fsr < 0)
204 break;
205 if (fsr & FSR_READY)
206 return 0;
207 }
208 } while (!time_after_eq(jiffies, deadline));
209
210 return -ETIMEDOUT;
211}
212
b199489d
HS		 213/*
214 * Service routine to read status register until ready, or timeout occurs.
215 * Returns non-zero if error.
216 */
217static int wait_till_ready(struct spi_nor *nor)
218{
219 return nor->wait_till_ready(nor);
220}
221
222/*
223 * Erase the whole flash memory
224 *
225 * Returns 0 if successful, non-zero otherwise.
226 */
227static int erase_chip(struct spi_nor *nor)
228{
229 int ret;
230
231 dev_dbg(nor->dev, " %lldKiB\n", (long long)(nor->mtd->size >> 10));
232
233 /* Wait until finished previous write command. */
234 ret = wait_till_ready(nor);
235 if (ret)
236 return ret;
237
238 /* Send write enable, then erase commands. */
239 write_enable(nor);
240
b02e7f3e 241 return nor->write_reg(nor, SPINOR_OP_CHIP_ERASE, NULL, 0, 0);
b199489d
HS		 242}
243
244static int spi_nor_lock_and_prep(struct spi_nor *nor, enum spi_nor_ops ops)
245{
246 int ret = 0;
247
248 mutex_lock(&nor->lock);
249
250 if (nor->prepare) {
251 ret = nor->prepare(nor, ops);
252 if (ret) {
253 dev_err(nor->dev, "failed in the preparation.\n");
254 mutex_unlock(&nor->lock);
255 return ret;
256 }
257 }
258 return ret;
259}
260
261static void spi_nor_unlock_and_unprep(struct spi_nor *nor, enum spi_nor_ops ops)
262{
263 if (nor->unprepare)
264 nor->unprepare(nor, ops);
265 mutex_unlock(&nor->lock);
266}
267
268/*
269 * Erase an address range on the nor chip. The address range may extend
270 * one or more erase sectors. Return an error is there is a problem erasing.
271 */
272static int spi_nor_erase(struct mtd_info *mtd, struct erase_info *instr)
273{
274 struct spi_nor *nor = mtd_to_spi_nor(mtd);
275 u32 addr, len;
276 uint32_t rem;
277 int ret;
278
279 dev_dbg(nor->dev, "at 0x%llx, len %lld\n", (long long)instr->addr,
280 (long long)instr->len);
281
282 div_u64_rem(instr->len, mtd->erasesize, &rem);
283 if (rem)
284 return -EINVAL;
285
286 addr = instr->addr;
287 len = instr->len;
288
289 ret = spi_nor_lock_and_prep(nor, SPI_NOR_OPS_ERASE);
290 if (ret)
291 return ret;
292
293 /* whole-chip erase? */
294 if (len == mtd->size) {
295 if (erase_chip(nor)) {
296 ret = -EIO;
297 goto erase_err;
298 }
299
300 /* REVISIT in some cases we could speed up erasing large regions
b02e7f3e 301 * by using SPINOR_OP_SE instead of SPINOR_OP_BE_4K. We may have set up
b199489d
HS		 302 * to use "small sector erase", but that's not always optimal.
303 */
304
305 /* "sector"-at-a-time erase */
306 } else {
307 while (len) {
308 if (nor->erase(nor, addr)) {
309 ret = -EIO;
310 goto erase_err;
311 }
312
313 addr += mtd->erasesize;
314 len -= mtd->erasesize;
315 }
316 }
317
318 spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_ERASE);
319
320 instr->state = MTD_ERASE_DONE;
321 mtd_erase_callback(instr);
322
323 return ret;
324
325erase_err:
326 spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_ERASE);
327 instr->state = MTD_ERASE_FAILED;
328 return ret;
329}
330
331static int spi_nor_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
332{
333 struct spi_nor *nor = mtd_to_spi_nor(mtd);
334 uint32_t offset = ofs;
335 uint8_t status_old, status_new;
336 int ret = 0;
337
338 ret = spi_nor_lock_and_prep(nor, SPI_NOR_OPS_LOCK);
339 if (ret)
340 return ret;
341
342 /* Wait until finished previous command */
343 ret = wait_till_ready(nor);
344 if (ret)
345 goto err;
346
347 status_old = read_sr(nor);
348
349 if (offset < mtd->size - (mtd->size / 2))
350 status_new = status_old | SR_BP2 | SR_BP1 | SR_BP0;
351 else if (offset < mtd->size - (mtd->size / 4))
352 status_new = (status_old & ~SR_BP0) | SR_BP2 | SR_BP1;
353 else if (offset < mtd->size - (mtd->size / 8))
354 status_new = (status_old & ~SR_BP1) | SR_BP2 | SR_BP0;
355 else if (offset < mtd->size - (mtd->size / 16))
356 status_new = (status_old & ~(SR_BP0 | SR_BP1)) | SR_BP2;
357 else if (offset < mtd->size - (mtd->size / 32))
358 status_new = (status_old & ~SR_BP2) | SR_BP1 | SR_BP0;
359 else if (offset < mtd->size - (mtd->size / 64))
360 status_new = (status_old & ~(SR_BP2 | SR_BP0)) | SR_BP1;
361 else
362 status_new = (status_old & ~(SR_BP2 | SR_BP1)) | SR_BP0;
363
364 /* Only modify protection if it will not unlock other areas */
365 if ((status_new & (SR_BP2 | SR_BP1 | SR_BP0)) >
366 (status_old & (SR_BP2 | SR_BP1 | SR_BP0))) {
367 write_enable(nor);
368 ret = write_sr(nor, status_new);
369 if (ret)
370 goto err;
371 }
372
373err:
374 spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_LOCK);
375 return ret;
376}
377
378static int spi_nor_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
379{
380 struct spi_nor *nor = mtd_to_spi_nor(mtd);
381 uint32_t offset = ofs;
382 uint8_t status_old, status_new;
383 int ret = 0;
384
385 ret = spi_nor_lock_and_prep(nor, SPI_NOR_OPS_UNLOCK);
386 if (ret)
387 return ret;
388
389 /* Wait until finished previous command */
390 ret = wait_till_ready(nor);
391 if (ret)
392 goto err;
393
394 status_old = read_sr(nor);
395
396 if (offset+len > mtd->size - (mtd->size / 64))
397 status_new = status_old & ~(SR_BP2 | SR_BP1 | SR_BP0);
398 else if (offset+len > mtd->size - (mtd->size / 32))
399 status_new = (status_old & ~(SR_BP2 | SR_BP1)) | SR_BP0;
400 else if (offset+len > mtd->size - (mtd->size / 16))
401 status_new = (status_old & ~(SR_BP2 | SR_BP0)) | SR_BP1;
402 else if (offset+len > mtd->size - (mtd->size / 8))
403 status_new = (status_old & ~SR_BP2) | SR_BP1 | SR_BP0;
404 else if (offset+len > mtd->size - (mtd->size / 4))
405 status_new = (status_old & ~(SR_BP0 | SR_BP1)) | SR_BP2;
406 else if (offset+len > mtd->size - (mtd->size / 2))
407 status_new = (status_old & ~SR_BP1) | SR_BP2 | SR_BP0;
408 else
409 status_new = (status_old & ~SR_BP0) | SR_BP2 | SR_BP1;
410
411 /* Only modify protection if it will not lock other areas */
412 if ((status_new & (SR_BP2 | SR_BP1 | SR_BP0)) <
413 (status_old & (SR_BP2 | SR_BP1 | SR_BP0))) {
414 write_enable(nor);
415 ret = write_sr(nor, status_new);
416 if (ret)
417 goto err;
418 }
419
420err:
421 spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_UNLOCK);
422 return ret;
423}
424
425struct flash_info {
426 /* JEDEC id zero means "no ID" (most older chips); otherwise it has
427 * a high byte of zero plus three data bytes: the manufacturer id,
428 * then a two byte device id.
429 */
430 u32 jedec_id;
431 u16 ext_id;
432
b02e7f3e 433 /* The size listed here is what works with SPINOR_OP_SE, which isn't
b199489d
HS		 434 * necessarily called a "sector" by the vendor.
435 */
436 unsigned sector_size;
437 u16 n_sectors;
438
439 u16 page_size;
440 u16 addr_width;
441
442 u16 flags;
b02e7f3e 443#define SECT_4K 0x01 /* SPINOR_OP_BE_4K works uniformly */
b199489d
HS		 444#define SPI_NOR_NO_ERASE 0x02 /* No erase command needed */
445#define SST_WRITE 0x04 /* use SST byte programming */
446#define SPI_NOR_NO_FR 0x08 /* Can't do fastread */
b02e7f3e 447#define SECT_4K_PMC 0x10 /* SPINOR_OP_BE_4K_PMC works uniformly */
b199489d
HS		 448#define SPI_NOR_DUAL_READ 0x20 /* Flash supports Dual Read */
449#define SPI_NOR_QUAD_READ 0x40 /* Flash supports Quad Read */
c14dedde 450#define USE_FSR 0x80 /* use flag status register */
b199489d
HS		 451};
452
453#define INFO(_jedec_id, _ext_id, _sector_size, _n_sectors, _flags) \
454 ((kernel_ulong_t)&(struct flash_info) { \
455 .jedec_id = (_jedec_id), \
456 .ext_id = (_ext_id), \
457 .sector_size = (_sector_size), \
458 .n_sectors = (_n_sectors), \
459 .page_size = 256, \
460 .flags = (_flags), \
461 })
462
463#define CAT25_INFO(_sector_size, _n_sectors, _page_size, _addr_width, _flags) \
464 ((kernel_ulong_t)&(struct flash_info) { \
465 .sector_size = (_sector_size), \
466 .n_sectors = (_n_sectors), \
467 .page_size = (_page_size), \
468 .addr_width = (_addr_width), \
469 .flags = (_flags), \
470 })
471
472/* NOTE: double check command sets and memory organization when you add
473 * more nor chips. This current list focusses on newer chips, which
474 * have been converging on command sets which including JEDEC ID.
475 */
476const struct spi_device_id spi_nor_ids[] = {
477 /* Atmel -- some are (confusingly) marketed as "DataFlash" */
478 { "at25fs010", INFO(0x1f6601, 0, 32 * 1024, 4, SECT_4K) },
479 { "at25fs040", INFO(0x1f6604, 0, 64 * 1024, 8, SECT_4K) },
480
481 { "at25df041a", INFO(0x1f4401, 0, 64 * 1024, 8, SECT_4K) },
482 { "at25df321a", INFO(0x1f4701, 0, 64 * 1024, 64, SECT_4K) },
483 { "at25df641", INFO(0x1f4800, 0, 64 * 1024, 128, SECT_4K) },
484
485 { "at26f004", INFO(0x1f0400, 0, 64 * 1024, 8, SECT_4K) },
486 { "at26df081a", INFO(0x1f4501, 0, 64 * 1024, 16, SECT_4K) },
487 { "at26df161a", INFO(0x1f4601, 0, 64 * 1024, 32, SECT_4K) },
488 { "at26df321", INFO(0x1f4700, 0, 64 * 1024, 64, SECT_4K) },
489
490 { "at45db081d", INFO(0x1f2500, 0, 64 * 1024, 16, SECT_4K) },
491
492 /* EON -- en25xxx */
493 { "en25f32", INFO(0x1c3116, 0, 64 * 1024, 64, SECT_4K) },
494 { "en25p32", INFO(0x1c2016, 0, 64 * 1024, 64, 0) },
495 { "en25q32b", INFO(0x1c3016, 0, 64 * 1024, 64, 0) },
496 { "en25p64", INFO(0x1c2017, 0, 64 * 1024, 128, 0) },
497 { "en25q64", INFO(0x1c3017, 0, 64 * 1024, 128, SECT_4K) },
a41595b3 498 { "en25qh128", INFO(0x1c7018, 0, 64 * 1024, 256, 0) },
b199489d
HS		 499 { "en25qh256", INFO(0x1c7019, 0, 64 * 1024, 512, 0) },
500
501 /* ESMT */
502 { "f25l32pa", INFO(0x8c2016, 0, 64 * 1024, 64, SECT_4K) },
503
504 /* Everspin */
505 { "mr25h256", CAT25_INFO( 32 * 1024, 1, 256, 2, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) },
506 { "mr25h10", CAT25_INFO(128 * 1024, 1, 256, 3, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) },
507
508 /* GigaDevice */
509 { "gd25q32", INFO(0xc84016, 0, 64 * 1024, 64, SECT_4K) },
510 { "gd25q64", INFO(0xc84017, 0, 64 * 1024, 128, SECT_4K) },
511
512 /* Intel/Numonyx -- xxxs33b */
513 { "160s33b", INFO(0x898911, 0, 64 * 1024, 32, 0) },
514 { "320s33b", INFO(0x898912, 0, 64 * 1024, 64, 0) },
515 { "640s33b", INFO(0x898913, 0, 64 * 1024, 128, 0) },
516
517 /* Macronix */
518 { "mx25l2005a", INFO(0xc22012, 0, 64 * 1024, 4, SECT_4K) },
519 { "mx25l4005a", INFO(0xc22013, 0, 64 * 1024, 8, SECT_4K) },
520 { "mx25l8005", INFO(0xc22014, 0, 64 * 1024, 16, 0) },
521 { "mx25l1606e", INFO(0xc22015, 0, 64 * 1024, 32, SECT_4K) },
522 { "mx25l3205d", INFO(0xc22016, 0, 64 * 1024, 64, 0) },
523 { "mx25l3255e", INFO(0xc29e16, 0, 64 * 1024, 64, SECT_4K) },
524 { "mx25l6405d", INFO(0xc22017, 0, 64 * 1024, 128, 0) },
525 { "mx25l12805d", INFO(0xc22018, 0, 64 * 1024, 256, 0) },
526 { "mx25l12855e", INFO(0xc22618, 0, 64 * 1024, 256, 0) },
527 { "mx25l25635e", INFO(0xc22019, 0, 64 * 1024, 512, 0) },
528 { "mx25l25655e", INFO(0xc22619, 0, 64 * 1024, 512, 0) },
529 { "mx66l51235l", INFO(0xc2201a, 0, 64 * 1024, 1024, SPI_NOR_QUAD_READ) },
530 { "mx66l1g55g", INFO(0xc2261b, 0, 64 * 1024, 2048, SPI_NOR_QUAD_READ) },
531
532 /* Micron */
533 { "n25q064", INFO(0x20ba17, 0, 64 * 1024, 128, 0) },
534 { "n25q128a11", INFO(0x20bb18, 0, 64 * 1024, 256, 0) },
535 { "n25q128a13", INFO(0x20ba18, 0, 64 * 1024, 256, 0) },
536 { "n25q256a", INFO(0x20ba19, 0, 64 * 1024, 512, SECT_4K) },
537 { "n25q512a", INFO(0x20bb20, 0, 64 * 1024, 1024, SECT_4K) },
c14dedde 538 { "n25q512ax3", INFO(0x20ba20, 0, 64 * 1024, 1024, USE_FSR) },
539 { "n25q00", INFO(0x20ba21, 0, 64 * 1024, 2048, USE_FSR) },
b199489d
HS		 540
541 /* PMC */
542 { "pm25lv512", INFO(0, 0, 32 * 1024, 2, SECT_4K_PMC) },
543 { "pm25lv010", INFO(0, 0, 32 * 1024, 4, SECT_4K_PMC) },
544 { "pm25lq032", INFO(0x7f9d46, 0, 64 * 1024, 64, SECT_4K) },
545
546 /* Spansion -- single (large) sector size only, at least
547 * for the chips listed here (without boot sectors).
548 */
9ab86995 549 { "s25sl032p", INFO(0x010215, 0x4d00, 64 * 1024, 64, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
b199489d
HS		 550 { "s25sl064p", INFO(0x010216, 0x4d00, 64 * 1024, 128, 0) },
551 { "s25fl256s0", INFO(0x010219, 0x4d00, 256 * 1024, 128, 0) },
552 { "s25fl256s1", INFO(0x010219, 0x4d01, 64 * 1024, 512, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
553 { "s25fl512s", INFO(0x010220, 0x4d00, 256 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
554 { "s70fl01gs", INFO(0x010221, 0x4d00, 256 * 1024, 256, 0) },
555 { "s25sl12800", INFO(0x012018, 0x0300, 256 * 1024, 64, 0) },
556 { "s25sl12801", INFO(0x012018, 0x0301, 64 * 1024, 256, 0) },
557 { "s25fl129p0", INFO(0x012018, 0x4d00, 256 * 1024, 64, 0) },
558 { "s25fl129p1", INFO(0x012018, 0x4d01, 64 * 1024, 256, 0) },
559 { "s25sl004a", INFO(0x010212, 0, 64 * 1024, 8, 0) },
560 { "s25sl008a", INFO(0x010213, 0, 64 * 1024, 16, 0) },
561 { "s25sl016a", INFO(0x010214, 0, 64 * 1024, 32, 0) },
562 { "s25sl032a", INFO(0x010215, 0, 64 * 1024, 64, 0) },
563 { "s25sl064a", INFO(0x010216, 0, 64 * 1024, 128, 0) },
564 { "s25fl008k", INFO(0xef4014, 0, 64 * 1024, 16, SECT_4K) },
565 { "s25fl016k", INFO(0xef4015, 0, 64 * 1024, 32, SECT_4K) },
566 { "s25fl064k", INFO(0xef4017, 0, 64 * 1024, 128, SECT_4K) },
567
568 /* SST -- large erase sizes are "overlays", "sectors" are 4K */
569 { "sst25vf040b", INFO(0xbf258d, 0, 64 * 1024, 8, SECT_4K | SST_WRITE) },
570 { "sst25vf080b", INFO(0xbf258e, 0, 64 * 1024, 16, SECT_4K | SST_WRITE) },
571 { "sst25vf016b", INFO(0xbf2541, 0, 64 * 1024, 32, SECT_4K | SST_WRITE) },
572 { "sst25vf032b", INFO(0xbf254a, 0, 64 * 1024, 64, SECT_4K | SST_WRITE) },
573 { "sst25vf064c", INFO(0xbf254b, 0, 64 * 1024, 128, SECT_4K) },
574 { "sst25wf512", INFO(0xbf2501, 0, 64 * 1024, 1, SECT_4K | SST_WRITE) },
575 { "sst25wf010", INFO(0xbf2502, 0, 64 * 1024, 2, SECT_4K | SST_WRITE) },
576 { "sst25wf020", INFO(0xbf2503, 0, 64 * 1024, 4, SECT_4K | SST_WRITE) },
577 { "sst25wf040", INFO(0xbf2504, 0, 64 * 1024, 8, SECT_4K | SST_WRITE) },
578
579 /* ST Microelectronics -- newer production may have feature updates */
580 { "m25p05", INFO(0x202010, 0, 32 * 1024, 2, 0) },
581 { "m25p10", INFO(0x202011, 0, 32 * 1024, 4, 0) },
582 { "m25p20", INFO(0x202012, 0, 64 * 1024, 4, 0) },
583 { "m25p40", INFO(0x202013, 0, 64 * 1024, 8, 0) },
584 { "m25p80", INFO(0x202014, 0, 64 * 1024, 16, 0) },
585 { "m25p16", INFO(0x202015, 0, 64 * 1024, 32, 0) },
586 { "m25p32", INFO(0x202016, 0, 64 * 1024, 64, 0) },
587 { "m25p64", INFO(0x202017, 0, 64 * 1024, 128, 0) },
588 { "m25p128", INFO(0x202018, 0, 256 * 1024, 64, 0) },
589 { "n25q032", INFO(0x20ba16, 0, 64 * 1024, 64, 0) },
590
591 { "m25p05-nonjedec", INFO(0, 0, 32 * 1024, 2, 0) },
592 { "m25p10-nonjedec", INFO(0, 0, 32 * 1024, 4, 0) },
593 { "m25p20-nonjedec", INFO(0, 0, 64 * 1024, 4, 0) },
594 { "m25p40-nonjedec", INFO(0, 0, 64 * 1024, 8, 0) },
595 { "m25p80-nonjedec", INFO(0, 0, 64 * 1024, 16, 0) },
596 { "m25p16-nonjedec", INFO(0, 0, 64 * 1024, 32, 0) },
597 { "m25p32-nonjedec", INFO(0, 0, 64 * 1024, 64, 0) },
598 { "m25p64-nonjedec", INFO(0, 0, 64 * 1024, 128, 0) },
599 { "m25p128-nonjedec", INFO(0, 0, 256 * 1024, 64, 0) },
600
601 { "m45pe10", INFO(0x204011, 0, 64 * 1024, 2, 0) },
602 { "m45pe80", INFO(0x204014, 0, 64 * 1024, 16, 0) },
603 { "m45pe16", INFO(0x204015, 0, 64 * 1024, 32, 0) },
604
605 { "m25pe20", INFO(0x208012, 0, 64 * 1024, 4, 0) },
606 { "m25pe80", INFO(0x208014, 0, 64 * 1024, 16, 0) },
607 { "m25pe16", INFO(0x208015, 0, 64 * 1024, 32, SECT_4K) },
608
609 { "m25px16", INFO(0x207115, 0, 64 * 1024, 32, SECT_4K) },
610 { "m25px32", INFO(0x207116, 0, 64 * 1024, 64, SECT_4K) },
611 { "m25px32-s0", INFO(0x207316, 0, 64 * 1024, 64, SECT_4K) },
612 { "m25px32-s1", INFO(0x206316, 0, 64 * 1024, 64, SECT_4K) },
613 { "m25px64", INFO(0x207117, 0, 64 * 1024, 128, 0) },
f2fabe16 614 { "m25px80", INFO(0x207114, 0, 64 * 1024, 16, 0) },
b199489d
HS		 615
616 /* Winbond -- w25x "blocks" are 64K, "sectors" are 4KiB */
617 { "w25x10", INFO(0xef3011, 0, 64 * 1024, 2, SECT_4K) },
618 { "w25x20", INFO(0xef3012, 0, 64 * 1024, 4, SECT_4K) },
619 { "w25x40", INFO(0xef3013, 0, 64 * 1024, 8, SECT_4K) },
620 { "w25x80", INFO(0xef3014, 0, 64 * 1024, 16, SECT_4K) },
621 { "w25x16", INFO(0xef3015, 0, 64 * 1024, 32, SECT_4K) },
622 { "w25x32", INFO(0xef3016, 0, 64 * 1024, 64, SECT_4K) },
623 { "w25q32", INFO(0xef4016, 0, 64 * 1024, 64, SECT_4K) },
624 { "w25q32dw", INFO(0xef6016, 0, 64 * 1024, 64, SECT_4K) },
625 { "w25x64", INFO(0xef3017, 0, 64 * 1024, 128, SECT_4K) },
626 { "w25q64", INFO(0xef4017, 0, 64 * 1024, 128, SECT_4K) },
b199489d
HS		 627 { "w25q80", INFO(0xef5014, 0, 64 * 1024, 16, SECT_4K) },
628 { "w25q80bl", INFO(0xef4014, 0, 64 * 1024, 16, SECT_4K) },
629 { "w25q128", INFO(0xef4018, 0, 64 * 1024, 256, SECT_4K) },
630 { "w25q256", INFO(0xef4019, 0, 64 * 1024, 512, SECT_4K) },
631
632 /* Catalyst / On Semiconductor -- non-JEDEC */
633 { "cat25c11", CAT25_INFO( 16, 8, 16, 1, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) },
634 { "cat25c03", CAT25_INFO( 32, 8, 16, 2, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) },
635 { "cat25c09", CAT25_INFO( 128, 8, 32, 2, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) },
636 { "cat25c17", CAT25_INFO( 256, 8, 32, 2, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) },
637 { "cat25128", CAT25_INFO(2048, 8, 64, 2, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) },
638 { },
639};
b61834b0 640EXPORT_SYMBOL_GPL(spi_nor_ids);
b199489d
HS		 641
642static const struct spi_device_id *spi_nor_read_id(struct spi_nor *nor)
643{
644 int tmp;
645 u8 id[5];
646 u32 jedec;
647 u16 ext_jedec;
648 struct flash_info *info;
649
b02e7f3e 650 tmp = nor->read_reg(nor, SPINOR_OP_RDID, id, 5);
b199489d
HS		 651 if (tmp < 0) {
652 dev_dbg(nor->dev, " error %d reading JEDEC ID\n", tmp);
653 return ERR_PTR(tmp);
654 }
655 jedec = id[0];
656 jedec = jedec << 8;
657 jedec |= id[1];
658 jedec = jedec << 8;
659 jedec |= id[2];
660
661 ext_jedec = id[3] << 8 | id[4];
662
663 for (tmp = 0; tmp < ARRAY_SIZE(spi_nor_ids) - 1; tmp++) {
664 info = (void *)spi_nor_ids[tmp].driver_data;
665 if (info->jedec_id == jedec) {
666 if (info->ext_id == 0 || info->ext_id == ext_jedec)
667 return &spi_nor_ids[tmp];
668 }
669 }
670 dev_err(nor->dev, "unrecognized JEDEC id %06x\n", jedec);
671 return ERR_PTR(-ENODEV);
672}
673
b199489d
HS		 674static int spi_nor_read(struct mtd_info *mtd, loff_t from, size_t len,
675 size_t *retlen, u_char *buf)
676{
677 struct spi_nor *nor = mtd_to_spi_nor(mtd);
678 int ret;
679
680 dev_dbg(nor->dev, "from 0x%08x, len %zd\n", (u32)from, len);
681
682 ret = spi_nor_lock_and_prep(nor, SPI_NOR_OPS_READ);
683 if (ret)
684 return ret;
685
686 ret = nor->read(nor, from, len, retlen, buf);
687
688 spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_READ);
689 return ret;
690}
691
692static int sst_write(struct mtd_info *mtd, loff_t to, size_t len,
693 size_t *retlen, const u_char *buf)
694{
695 struct spi_nor *nor = mtd_to_spi_nor(mtd);
696 size_t actual;
697 int ret;
698
699 dev_dbg(nor->dev, "to 0x%08x, len %zd\n", (u32)to, len);
700
701 ret = spi_nor_lock_and_prep(nor, SPI_NOR_OPS_WRITE);
702 if (ret)
703 return ret;
704
705 /* Wait until finished previous write command. */
706 ret = wait_till_ready(nor);
707 if (ret)
708 goto time_out;
709
710 write_enable(nor);
711
712 nor->sst_write_second = false;
713
714 actual = to % 2;
715 /* Start write from odd address. */
716 if (actual) {
b02e7f3e 717 nor->program_opcode = SPINOR_OP_BP;
b199489d
HS		 718
719 /* write one byte. */
720 nor->write(nor, to, 1, retlen, buf);
721 ret = wait_till_ready(nor);
722 if (ret)
723 goto time_out;
724 }
725 to += actual;
726
727 /* Write out most of the data here. */
728 for (; actual < len - 1; actual += 2) {
b02e7f3e 729 nor->program_opcode = SPINOR_OP_AAI_WP;
b199489d
HS		 730
731 /* write two bytes. */
732 nor->write(nor, to, 2, retlen, buf + actual);
733 ret = wait_till_ready(nor);
734 if (ret)
735 goto time_out;
736 to += 2;
737 nor->sst_write_second = true;
738 }
739 nor->sst_write_second = false;
740
741 write_disable(nor);
742 ret = wait_till_ready(nor);
743 if (ret)
744 goto time_out;
745
746 /* Write out trailing byte if it exists. */
747 if (actual != len) {
748 write_enable(nor);
749
b02e7f3e 750 nor->program_opcode = SPINOR_OP_BP;
b199489d
HS		 751 nor->write(nor, to, 1, retlen, buf + actual);
752
753 ret = wait_till_ready(nor);
754 if (ret)
755 goto time_out;
756 write_disable(nor);
757 }
758time_out:
759 spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_WRITE);
760 return ret;
761}
762
763/*
764 * Write an address range to the nor chip. Data must be written in
765 * FLASH_PAGESIZE chunks. The address range may be any size provided
766 * it is within the physical boundaries.
767 */
768static int spi_nor_write(struct mtd_info *mtd, loff_t to, size_t len,
769 size_t *retlen, const u_char *buf)
770{
771 struct spi_nor *nor = mtd_to_spi_nor(mtd);
772 u32 page_offset, page_size, i;
773 int ret;
774
775 dev_dbg(nor->dev, "to 0x%08x, len %zd\n", (u32)to, len);
776
777 ret = spi_nor_lock_and_prep(nor, SPI_NOR_OPS_WRITE);
778 if (ret)
779 return ret;
780
781 /* Wait until finished previous write command. */
782 ret = wait_till_ready(nor);
783 if (ret)
784 goto write_err;
785
786 write_enable(nor);
787
788 page_offset = to & (nor->page_size - 1);
789
790 /* do all the bytes fit onto one page? */
791 if (page_offset + len <= nor->page_size) {
792 nor->write(nor, to, len, retlen, buf);
793 } else {
794 /* the size of data remaining on the first page */
795 page_size = nor->page_size - page_offset;
796 nor->write(nor, to, page_size, retlen, buf);
797
798 /* write everything in nor->page_size chunks */
799 for (i = page_size; i < len; i += page_size) {
800 page_size = len - i;
801 if (page_size > nor->page_size)
802 page_size = nor->page_size;
803
804 wait_till_ready(nor);
805 write_enable(nor);
806
807 nor->write(nor, to + i, page_size, retlen, buf + i);
808 }
809 }
810
811write_err:
812 spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_WRITE);
813 return 0;
814}
815
816static int macronix_quad_enable(struct spi_nor *nor)
817{
818 int ret, val;
819
820 val = read_sr(nor);
821 write_enable(nor);
822
823 nor->cmd_buf[0] = val | SR_QUAD_EN_MX;
b02e7f3e 824 nor->write_reg(nor, SPINOR_OP_WRSR, nor->cmd_buf, 1, 0);
b199489d
HS		 825
826 if (wait_till_ready(nor))
827 return 1;
828
829 ret = read_sr(nor);
830 if (!(ret > 0 && (ret & SR_QUAD_EN_MX))) {
831 dev_err(nor->dev, "Macronix Quad bit not set\n");
832 return -EINVAL;
833 }
834
835 return 0;
836}
837
838/*
839 * Write status Register and configuration register with 2 bytes
840 * The first byte will be written to the status register, while the
841 * second byte will be written to the configuration register.
842 * Return negative if error occured.
843 */
844static int write_sr_cr(struct spi_nor *nor, u16 val)
845{
846 nor->cmd_buf[0] = val & 0xff;
847 nor->cmd_buf[1] = (val >> 8);
848
b02e7f3e 849 return nor->write_reg(nor, SPINOR_OP_WRSR, nor->cmd_buf, 2, 0);
b199489d
HS		 850}
851
852static int spansion_quad_enable(struct spi_nor *nor)
853{
854 int ret;
855 int quad_en = CR_QUAD_EN_SPAN << 8;
856
857 write_enable(nor);
858
859 ret = write_sr_cr(nor, quad_en);
860 if (ret < 0) {
861 dev_err(nor->dev,
862 "error while writing configuration register\n");
863 return -EINVAL;
864 }
865
866 /* read back and check it */
867 ret = read_cr(nor);
868 if (!(ret > 0 && (ret & CR_QUAD_EN_SPAN))) {
869 dev_err(nor->dev, "Spansion Quad bit not set\n");
870 return -EINVAL;
871 }
872
873 return 0;
874}
875
876static int set_quad_mode(struct spi_nor *nor, u32 jedec_id)
877{
878 int status;
879
880 switch (JEDEC_MFR(jedec_id)) {
881 case CFI_MFR_MACRONIX:
882 status = macronix_quad_enable(nor);
883 if (status) {
884 dev_err(nor->dev, "Macronix quad-read not enabled\n");
885 return -EINVAL;
886 }
887 return status;
888 default:
889 status = spansion_quad_enable(nor);
890 if (status) {
891 dev_err(nor->dev, "Spansion quad-read not enabled\n");
892 return -EINVAL;
893 }
894 return status;
895 }
896}
897
898static int spi_nor_check(struct spi_nor *nor)
899{
900 if (!nor->dev || !nor->read || !nor->write ||
901 !nor->read_reg || !nor->write_reg || !nor->erase) {
902 pr_err("spi-nor: please fill all the necessary fields!\n");
903 return -EINVAL;
904 }
905
906 if (!nor->read_id)
907 nor->read_id = spi_nor_read_id;
908 if (!nor->wait_till_ready)
909 nor->wait_till_ready = spi_nor_wait_till_ready;
910
911 return 0;
912}
913
914int spi_nor_scan(struct spi_nor *nor, const struct spi_device_id *id,
915 enum read_mode mode)
916{
917 struct flash_info *info;
918 struct flash_platform_data *data;
919 struct device *dev = nor->dev;
920 struct mtd_info *mtd = nor->mtd;
921 struct device_node *np = dev->of_node;
922 int ret;
923 int i;
924
925 ret = spi_nor_check(nor);
926 if (ret)
927 return ret;
928
929 /* Platform data helps sort out which chip type we have, as
930 * well as how this board partitions it. If we don't have
931 * a chip ID, try the JEDEC id commands; they'll work for most
932 * newer chips, even if we don't recognize the particular chip.
933 */
934 data = dev_get_platdata(dev);
935 if (data && data->type) {
936 const struct spi_device_id *plat_id;
937
938 for (i = 0; i < ARRAY_SIZE(spi_nor_ids) - 1; i++) {
939 plat_id = &spi_nor_ids[i];
940 if (strcmp(data->type, plat_id->name))
941 continue;
942 break;
943 }
944
945 if (i < ARRAY_SIZE(spi_nor_ids) - 1)
946 id = plat_id;
947 else
948 dev_warn(dev, "unrecognized id %s\n", data->type);
949 }
950
951 info = (void *)id->driver_data;
952
953 if (info->jedec_id) {
954 const struct spi_device_id *jid;
955
54ea17a5 956 jid = nor->read_id(nor);
b199489d
HS		 957 if (IS_ERR(jid)) {
958 return PTR_ERR(jid);
959 } else if (jid != id) {
960 /*
961 * JEDEC knows better, so overwrite platform ID. We
962 * can't trust partitions any longer, but we'll let
963 * mtd apply them anyway, since some partitions may be
964 * marked read-only, and we don't want to lose that
965 * information, even if it's not 100% accurate.
966 */
967 dev_warn(dev, "found %s, expected %s\n",
968 jid->name, id->name);
969 id = jid;
970 info = (void *)jid->driver_data;
971 }
972 }
973
974 mutex_init(&nor->lock);
975
976 /*
977 * Atmel, SST and Intel/Numonyx serial nor tend to power
978 * up with the software protection bits set
979 */
980
981 if (JEDEC_MFR(info->jedec_id) == CFI_MFR_ATMEL ||
982 JEDEC_MFR(info->jedec_id) == CFI_MFR_INTEL ||
983 JEDEC_MFR(info->jedec_id) == CFI_MFR_SST) {
984 write_enable(nor);
985 write_sr(nor, 0);
986 }
987
988 if (data && data->name)
989 mtd->name = data->name;
990 else
991 mtd->name = dev_name(dev);
992
993 mtd->type = MTD_NORFLASH;
994 mtd->writesize = 1;
995 mtd->flags = MTD_CAP_NORFLASH;
996 mtd->size = info->sector_size * info->n_sectors;
997 mtd->_erase = spi_nor_erase;
998 mtd->_read = spi_nor_read;
999
1000 /* nor protection support for STmicro chips */
1001 if (JEDEC_MFR(info->jedec_id) == CFI_MFR_ST) {
1002 mtd->_lock = spi_nor_lock;
1003 mtd->_unlock = spi_nor_unlock;
1004 }
1005
1006 /* sst nor chips use AAI word program */
1007 if (info->flags & SST_WRITE)
1008 mtd->_write = sst_write;
1009 else
1010 mtd->_write = spi_nor_write;
1011
c14dedde 1012 if ((info->flags & USE_FSR) &&
1013 nor->wait_till_ready == spi_nor_wait_till_ready)
1014 nor->wait_till_ready = spi_nor_wait_till_fsr_ready;
1015
b199489d
HS		 1016 /* prefer "small sector" erase if possible */
1017 if (info->flags & SECT_4K) {
b02e7f3e 1018 nor->erase_opcode = SPINOR_OP_BE_4K;
b199489d
HS		 1019 mtd->erasesize = 4096;
1020 } else if (info->flags & SECT_4K_PMC) {
b02e7f3e 1021 nor->erase_opcode = SPINOR_OP_BE_4K_PMC;
b199489d
HS		 1022 mtd->erasesize = 4096;
1023 } else {
b02e7f3e 1024 nor->erase_opcode = SPINOR_OP_SE;
b199489d
HS		 1025 mtd->erasesize = info->sector_size;
1026 }
1027
1028 if (info->flags & SPI_NOR_NO_ERASE)
1029 mtd->flags |= MTD_NO_ERASE;
1030
1031 mtd->dev.parent = dev;
1032 nor->page_size = info->page_size;
1033 mtd->writebufsize = nor->page_size;
1034
1035 if (np) {
1036 /* If we were instantiated by DT, use it */
1037 if (of_property_read_bool(np, "m25p,fast-read"))
1038 nor->flash_read = SPI_NOR_FAST;
1039 else
1040 nor->flash_read = SPI_NOR_NORMAL;
1041 } else {
1042 /* If we weren't instantiated by DT, default to fast-read */
1043 nor->flash_read = SPI_NOR_FAST;
1044 }
1045
1046 /* Some devices cannot do fast-read, no matter what DT tells us */
1047 if (info->flags & SPI_NOR_NO_FR)
1048 nor->flash_read = SPI_NOR_NORMAL;
1049
1050 /* Quad/Dual-read mode takes precedence over fast/normal */
1051 if (mode == SPI_NOR_QUAD && info->flags & SPI_NOR_QUAD_READ) {
1052 ret = set_quad_mode(nor, info->jedec_id);
1053 if (ret) {
1054 dev_err(dev, "quad mode not supported\n");
1055 return ret;
1056 }
1057 nor->flash_read = SPI_NOR_QUAD;
1058 } else if (mode == SPI_NOR_DUAL && info->flags & SPI_NOR_DUAL_READ) {
1059 nor->flash_read = SPI_NOR_DUAL;
1060 }
1061
1062 /* Default commands */
1063 switch (nor->flash_read) {
1064 case SPI_NOR_QUAD:
58b89a1f 1065 nor->read_opcode = SPINOR_OP_READ_1_1_4;
b199489d
HS		 1066 break;
1067 case SPI_NOR_DUAL:
58b89a1f 1068 nor->read_opcode = SPINOR_OP_READ_1_1_2;
b199489d
HS		 1069 break;
1070 case SPI_NOR_FAST:
58b89a1f 1071 nor->read_opcode = SPINOR_OP_READ_FAST;
b199489d
HS		 1072 break;
1073 case SPI_NOR_NORMAL:
58b89a1f 1074 nor->read_opcode = SPINOR_OP_READ;
b199489d
HS		 1075 break;
1076 default:
1077 dev_err(dev, "No Read opcode defined\n");
1078 return -EINVAL;
1079 }
1080
b02e7f3e 1081 nor->program_opcode = SPINOR_OP_PP;
b199489d
HS		 1082
1083 if (info->addr_width)
1084 nor->addr_width = info->addr_width;
1085 else if (mtd->size > 0x1000000) {
1086 /* enable 4-byte addressing if the device exceeds 16MiB */
1087 nor->addr_width = 4;
1088 if (JEDEC_MFR(info->jedec_id) == CFI_MFR_AMD) {
1089 /* Dedicated 4-byte command set */
1090 switch (nor->flash_read) {
1091 case SPI_NOR_QUAD:
58b89a1f 1092 nor->read_opcode = SPINOR_OP_READ4_1_1_4;
b199489d
HS		 1093 break;
1094 case SPI_NOR_DUAL:
58b89a1f 1095 nor->read_opcode = SPINOR_OP_READ4_1_1_2;
b199489d
HS		 1096 break;
1097 case SPI_NOR_FAST:
58b89a1f 1098 nor->read_opcode = SPINOR_OP_READ4_FAST;
b199489d
HS		 1099 break;
1100 case SPI_NOR_NORMAL:
58b89a1f 1101 nor->read_opcode = SPINOR_OP_READ4;
b199489d
HS		 1102 break;
1103 }
b02e7f3e 1104 nor->program_opcode = SPINOR_OP_PP_4B;
b199489d 1105 /* No small sector erase for 4-byte command set */
b02e7f3e 1106 nor->erase_opcode = SPINOR_OP_SE_4B;
b199489d
HS		 1107 mtd->erasesize = info->sector_size;
1108 } else
1109 set_4byte(nor, info->jedec_id, 1);
1110 } else {
1111 nor->addr_width = 3;
1112 }
1113
1114 nor->read_dummy = spi_nor_read_dummy_cycles(nor);
1115
1116 dev_info(dev, "%s (%lld Kbytes)\n", id->name,
1117 (long long)mtd->size >> 10);
1118
1119 dev_dbg(dev,
1120 "mtd .name = %s, .size = 0x%llx (%lldMiB), "
1121 ".erasesize = 0x%.8x (%uKiB) .numeraseregions = %d\n",
1122 mtd->name, (long long)mtd->size, (long long)(mtd->size >> 20),
1123 mtd->erasesize, mtd->erasesize / 1024, mtd->numeraseregions);
1124
1125 if (mtd->numeraseregions)
1126 for (i = 0; i < mtd->numeraseregions; i++)
1127 dev_dbg(dev,
1128 "mtd.eraseregions[%d] = { .offset = 0x%llx, "
1129 ".erasesize = 0x%.8x (%uKiB), "
1130 ".numblocks = %d }\n",
1131 i, (long long)mtd->eraseregions[i].offset,
1132 mtd->eraseregions[i].erasesize,
1133 mtd->eraseregions[i].erasesize / 1024,
1134 mtd->eraseregions[i].numblocks);
1135 return 0;
1136}
b61834b0 1137EXPORT_SYMBOL_GPL(spi_nor_scan);
b199489d 1138
0d8c11c0
HS		 1139const struct spi_device_id *spi_nor_match_id(char *name)
1140{
1141 const struct spi_device_id *id = spi_nor_ids;
1142
1143 while (id->name[0]) {
1144 if (!strcmp(name, id->name))
1145 return id;
1146 id++;
1147 }
1148 return NULL;
1149}
b61834b0 1150EXPORT_SYMBOL_GPL(spi_nor_match_id);
0d8c11c0 1151
b199489d
HS		 1152MODULE_LICENSE("GPL");
1153MODULE_AUTHOR("Huang Shijie <shijie8@gmail.com>");
1154MODULE_AUTHOR("Mike Lavender");
1155MODULE_DESCRIPTION("framework for SPI NOR");
Linux kernel - Deliverables
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