projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
net: trans_start cleanups
[deliverable/linux.git] / drivers / net / 3c59x.c
CommitLineData
1da177e4
LT		 1/* EtherLinkXL.c: A 3Com EtherLink PCI III/XL ethernet driver for linux. */
2/*
3 Written 1996-1999 by Donald Becker.
4
5 This software may be used and distributed according to the terms
6 of the GNU General Public License, incorporated herein by reference.
7
8 This driver is for the 3Com "Vortex" and "Boomerang" series ethercards.
9 Members of the series include Fast EtherLink 3c590/3c592/3c595/3c597
10 and the EtherLink XL 3c900 and 3c905 cards.
11
12 Problem reports and questions should be directed to
13 vortex@scyld.com
14
15 The author may be reached as becker@scyld.com, or C/O
16 Scyld Computing Corporation
17 410 Severn Ave., Suite 210
18 Annapolis MD 21403
19
1da177e4
LT		 20*/
21
22/*
23 * FIXME: This driver _could_ support MTU changing, but doesn't. See Don's hamachi.c implementation
24 * as well as other drivers
25 *
26 * NOTE: If you make 'vortex_debug' a constant (#define vortex_debug 0) the driver shrinks by 2k
27 * due to dead code elimination. There will be some performance benefits from this due to
28 * elimination of all the tests and reduced cache footprint.
29 */
30
31
32#define DRV_NAME "3c59x"
1da177e4
LT		 33
34
35
36/* A few values that may be tweaked. */
37/* Keep the ring sizes a power of two for efficiency. */
38#define TX_RING_SIZE 16
39#define RX_RING_SIZE 32
40#define PKT_BUF_SZ 1536 /* Size of each temporary Rx buffer.*/
41
42/* "Knobs" that adjust features and parameters. */
43/* Set the copy breakpoint for the copy-only-tiny-frames scheme.
44 Setting to > 1512 effectively disables this feature. */
45#ifndef __arm__
46static int rx_copybreak = 200;
47#else
48/* ARM systems perform better by disregarding the bus-master
49 transfer capability of these cards. -- rmk */
50static int rx_copybreak = 1513;
51#endif
52/* Allow setting MTU to a larger size, bypassing the normal ethernet setup. */
53static const int mtu = 1500;
54/* Maximum events (Rx packets, etc.) to handle at each interrupt. */
55static int max_interrupt_work = 32;
56/* Tx timeout interval (millisecs) */
57static int watchdog = 5000;
58
59/* Allow aggregation of Tx interrupts. Saves CPU load at the cost
60 * of possible Tx stalls if the system is blocking interrupts
61 * somewhere else. Undefine this to disable.
62 */
63#define tx_interrupt_mitigation 1
64
65/* Put out somewhat more debugging messages. (0: no msg, 1 minimal .. 6). */
66#define vortex_debug debug
67#ifdef VORTEX_DEBUG
68static int vortex_debug = VORTEX_DEBUG;
69#else
70static int vortex_debug = 1;
71#endif
72
1da177e4
LT		 73#include <linux/module.h>
74#include <linux/kernel.h>
75#include <linux/string.h>
76#include <linux/timer.h>
77#include <linux/errno.h>
78#include <linux/in.h>
79#include <linux/ioport.h>
1da177e4
LT		 80#include <linux/interrupt.h>
81#include <linux/pci.h>
82#include <linux/mii.h>
83#include <linux/init.h>
84#include <linux/netdevice.h>
85#include <linux/etherdevice.h>
86#include <linux/skbuff.h>
87#include <linux/ethtool.h>
88#include <linux/highmem.h>
89#include <linux/eisa.h>
90#include <linux/bitops.h>
ff5688ae 91#include <linux/jiffies.h>
5a0e3ad6 92#include <linux/gfp.h>
60e4ad7a 93#include <asm/irq.h> /* For nr_irqs only. */
1da177e4
LT		 94#include <asm/io.h>
95#include <asm/uaccess.h>
96
97/* Kernel compatibility defines, some common to David Hinds' PCMCIA package.
98 This is only in the support-all-kernels source code. */
99
100#define RUN_AT(x) (jiffies + (x))
101
102#include <linux/delay.h>
103
104
86de79b6
SH		 105static const char version[] __devinitconst =
106 DRV_NAME ": Donald Becker and others.\n";
1da177e4
LT		 107
108MODULE_AUTHOR("Donald Becker <becker@scyld.com>");
61238602 109MODULE_DESCRIPTION("3Com 3c59x/3c9xx ethernet driver ");
1da177e4 110MODULE_LICENSE("GPL");
1da177e4
LT		 111
112
113/* Operational parameter that usually are not changed. */
114
115/* The Vortex size is twice that of the original EtherLinkIII series: the
116 runtime register window, window 1, is now always mapped in.
117 The Boomerang size is twice as large as the Vortex -- it has additional
118 bus master control registers. */
119#define VORTEX_TOTAL_SIZE 0x20
120#define BOOMERANG_TOTAL_SIZE 0x40
121
122/* Set iff a MII transceiver on any interface requires mdio preamble.
123 This only set with the original DP83840 on older 3c905 boards, so the extra
124 code size of a per-interface flag is not worthwhile. */
125static char mii_preamble_required;
126
127#define PFX DRV_NAME ": "
128
129
130
131/*
132 Theory of Operation
133
134I. Board Compatibility
135
136This device driver is designed for the 3Com FastEtherLink and FastEtherLink
137XL, 3Com's PCI to 10/100baseT adapters. It also works with the 10Mbs
138versions of the FastEtherLink cards. The supported product IDs are
139 3c590, 3c592, 3c595, 3c597, 3c900, 3c905
140
141The related ISA 3c515 is supported with a separate driver, 3c515.c, included
142with the kernel source or available from
143 cesdis.gsfc.nasa.gov:/pub/linux/drivers/3c515.html
144
145II. Board-specific settings
146
147PCI bus devices are configured by the system at boot time, so no jumpers
148need to be set on the board. The system BIOS should be set to assign the
149PCI INTA signal to an otherwise unused system IRQ line.
150
151The EEPROM settings for media type and forced-full-duplex are observed.
152The EEPROM media type should be left at the default "autoselect" unless using
15310base2 or AUI connections which cannot be reliably detected.
154
155III. Driver operation
156
157The 3c59x series use an interface that's very similar to the previous 3c5x9
158series. The primary interface is two programmed-I/O FIFOs, with an
159alternate single-contiguous-region bus-master transfer (see next).
160
161The 3c900 "Boomerang" series uses a full-bus-master interface with separate
162lists of transmit and receive descriptors, similar to the AMD LANCE/PCnet,
163DEC Tulip and Intel Speedo3. The first chip version retains a compatible
164programmed-I/O interface that has been removed in 'B' and subsequent board
165revisions.
166
167One extension that is advertised in a very large font is that the adapters
168are capable of being bus masters. On the Vortex chip this capability was
169only for a single contiguous region making it far less useful than the full
170bus master capability. There is a significant performance impact of taking
171an extra interrupt or polling for the completion of each transfer, as well
172as difficulty sharing the single transfer engine between the transmit and
173receive threads. Using DMA transfers is a win only with large blocks or
174with the flawed versions of the Intel Orion motherboard PCI controller.
175
176The Boomerang chip's full-bus-master interface is useful, and has the
177currently-unused advantages over other similar chips that queued transmit
178packets may be reordered and receive buffer groups are associated with a
179single frame.
180
181With full-bus-master support, this driver uses a "RX_COPYBREAK" scheme.
182Rather than a fixed intermediate receive buffer, this scheme allocates
183full-sized skbuffs as receive buffers. The value RX_COPYBREAK is used as
184the copying breakpoint: it is chosen to trade-off the memory wasted by
185passing the full-sized skbuff to the queue layer for all frames vs. the
186copying cost of copying a frame to a correctly-sized skbuff.
187
188IIIC. Synchronization
189The driver runs as two independent, single-threaded flows of control. One
190is the send-packet routine, which enforces single-threaded use by the
191dev->tbusy flag. The other thread is the interrupt handler, which is single
192threaded by the hardware and other software.
193
194IV. Notes
195
196Thanks to Cameron Spitzer and Terry Murphy of 3Com for providing development
1973c590, 3c595, and 3c900 boards.
198The name "Vortex" is the internal 3Com project name for the PCI ASIC, and
199the EISA version is called "Demon". According to Terry these names come
200from rides at the local amusement park.
201
202The new chips support both ethernet (1.5K) and FDDI (4.5K) packet sizes!
203This driver only supports ethernet packets because of the skbuff allocation
204limit of 4K.
205*/
206
207/* This table drives the PCI probe routines. It's mostly boilerplate in all
208 of the drivers, and will likely be provided by some future kernel.
209*/
210enum pci_flags_bit {
1f1bd5fc 211 PCI_USES_MASTER=4,
1da177e4
LT		 212};
213
214enum { IS_VORTEX=1, IS_BOOMERANG=2, IS_CYCLONE=4, IS_TORNADO=8,
215 EEPROM_8BIT=0x10, /* AKPM: Uses 0x230 as the base bitmaps for EEPROM reads */
216 HAS_PWR_CTRL=0x20, HAS_MII=0x40, HAS_NWAY=0x80, HAS_CB_FNS=0x100,
217 INVERT_MII_PWR=0x200, INVERT_LED_PWR=0x400, MAX_COLLISION_RESET=0x800,
218 EEPROM_OFFSET=0x1000, HAS_HWCKSM=0x2000, WNO_XCVR_PWR=0x4000,
219 EXTRA_PREAMBLE=0x8000, EEPROM_RESET=0x10000, };
220
221enum vortex_chips {
222 CH_3C590 = 0,
223 CH_3C592,
224 CH_3C597,
225 CH_3C595_1,
226 CH_3C595_2,
227
228 CH_3C595_3,
229 CH_3C900_1,
230 CH_3C900_2,
231 CH_3C900_3,
232 CH_3C900_4,
233
234 CH_3C900_5,
235 CH_3C900B_FL,
236 CH_3C905_1,
237 CH_3C905_2,
b4adbb4d 238 CH_3C905B_TX,
1da177e4
LT		 239 CH_3C905B_1,
240
241 CH_3C905B_2,
242 CH_3C905B_FX,
243 CH_3C905C,
244 CH_3C9202,
245 CH_3C980,
246 CH_3C9805,
247
248 CH_3CSOHO100_TX,
249 CH_3C555,
250 CH_3C556,
251 CH_3C556B,
252 CH_3C575,
253
254 CH_3C575_1,
255 CH_3CCFE575,
256 CH_3CCFE575CT,
257 CH_3CCFE656,
258 CH_3CCFEM656,
259
260 CH_3CCFEM656_1,
261 CH_3C450,
262 CH_3C920,
263 CH_3C982A,
264 CH_3C982B,
265
266 CH_905BT4,
267 CH_920B_EMB_WNM,
268};
269
270
271/* note: this array directly indexed by above enums, and MUST
272 * be kept in sync with both the enums above, and the PCI device
273 * table below
274 */
275static struct vortex_chip_info {
276 const char *name;
277 int flags;
278 int drv_flags;
279 int io_size;
280} vortex_info_tbl[] __devinitdata = {
281 {"3c590 Vortex 10Mbps",
1f1bd5fc 282 PCI_USES_MASTER, IS_VORTEX, 32, },
1da177e4 283 {"3c592 EISA 10Mbps Demon/Vortex", /* AKPM: from Don's 3c59x_cb.c 0.49H */
1f1bd5fc 284 PCI_USES_MASTER, IS_VORTEX, 32, },
1da177e4 285 {"3c597 EISA Fast Demon/Vortex", /* AKPM: from Don's 3c59x_cb.c 0.49H */
1f1bd5fc 286 PCI_USES_MASTER, IS_VORTEX, 32, },
1da177e4 287 {"3c595 Vortex 100baseTx",
1f1bd5fc 288 PCI_USES_MASTER, IS_VORTEX, 32, },
1da177e4 289 {"3c595 Vortex 100baseT4",
1f1bd5fc 290 PCI_USES_MASTER, IS_VORTEX, 32, },
1da177e4
LT		 291
292 {"3c595 Vortex 100base-MII",
1f1bd5fc 293 PCI_USES_MASTER, IS_VORTEX, 32, },
1da177e4 294 {"3c900 Boomerang 10baseT",
1f1bd5fc 295 PCI_USES_MASTER, IS_BOOMERANG|EEPROM_RESET, 64, },
1da177e4 296 {"3c900 Boomerang 10Mbps Combo",
1f1bd5fc 297 PCI_USES_MASTER, IS_BOOMERANG|EEPROM_RESET, 64, },
1da177e4 298 {"3c900 Cyclone 10Mbps TPO", /* AKPM: from Don's 0.99M */
1f1bd5fc 299 PCI_USES_MASTER, IS_CYCLONE|HAS_HWCKSM, 128, },
1da177e4 300 {"3c900 Cyclone 10Mbps Combo",
1f1bd5fc 301 PCI_USES_MASTER, IS_CYCLONE|HAS_HWCKSM, 128, },
1da177e4
LT		 302
303 {"3c900 Cyclone 10Mbps TPC", /* AKPM: from Don's 0.99M */
1f1bd5fc 304 PCI_USES_MASTER, IS_CYCLONE|HAS_HWCKSM, 128, },
1da177e4 305 {"3c900B-FL Cyclone 10base-FL",
1f1bd5fc 306 PCI_USES_MASTER, IS_CYCLONE|HAS_HWCKSM, 128, },
1da177e4 307 {"3c905 Boomerang 100baseTx",
1f1bd5fc 308 PCI_USES_MASTER, IS_BOOMERANG|HAS_MII|EEPROM_RESET, 64, },
1da177e4 309 {"3c905 Boomerang 100baseT4",
1f1bd5fc 310 PCI_USES_MASTER, IS_BOOMERANG|HAS_MII|EEPROM_RESET, 64, },
b4adbb4d
PT		 311 {"3C905B-TX Fast Etherlink XL PCI",
312 PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_HWCKSM|EXTRA_PREAMBLE, 128, },
1da177e4 313 {"3c905B Cyclone 100baseTx",
1f1bd5fc 314 PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_HWCKSM|EXTRA_PREAMBLE, 128, },
1da177e4
LT		 315
316 {"3c905B Cyclone 10/100/BNC",
1f1bd5fc 317 PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_HWCKSM, 128, },
1da177e4 318 {"3c905B-FX Cyclone 100baseFx",
1f1bd5fc 319 PCI_USES_MASTER, IS_CYCLONE|HAS_HWCKSM, 128, },
1da177e4 320 {"3c905C Tornado",
1f1bd5fc 321 PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|HAS_HWCKSM|EXTRA_PREAMBLE, 128, },
1da177e4 322 {"3c920B-EMB-WNM (ATI Radeon 9100 IGP)",
1f1bd5fc 323 PCI_USES_MASTER, IS_TORNADO|HAS_MII|HAS_HWCKSM, 128, },
1da177e4 324 {"3c980 Cyclone",
aa807f79 325 PCI_USES_MASTER, IS_CYCLONE|HAS_HWCKSM|EXTRA_PREAMBLE, 128, },
1da177e4
LT		 326
327 {"3c980C Python-T",
1f1bd5fc 328 PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_HWCKSM, 128, },
1da177e4 329 {"3cSOHO100-TX Hurricane",
b8a1fcee 330 PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_HWCKSM|EXTRA_PREAMBLE, 128, },
1da177e4 331 {"3c555 Laptop Hurricane",
1f1bd5fc 332 PCI_USES_MASTER, IS_CYCLONE|EEPROM_8BIT|HAS_HWCKSM, 128, },
1da177e4 333 {"3c556 Laptop Tornado",
1f1bd5fc 334 PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|EEPROM_8BIT|HAS_CB_FNS|INVERT_MII_PWR|
1da177e4
LT		 335 HAS_HWCKSM, 128, },
336 {"3c556B Laptop Hurricane",
1f1bd5fc 337 PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|EEPROM_OFFSET|HAS_CB_FNS|INVERT_MII_PWR|
1da177e4
LT		 338 WNO_XCVR_PWR|HAS_HWCKSM, 128, },
339
340 {"3c575 [Megahertz] 10/100 LAN CardBus",
1f1bd5fc 341 PCI_USES_MASTER, IS_BOOMERANG|HAS_MII|EEPROM_8BIT, 128, },
1da177e4 342 {"3c575 Boomerang CardBus",
1f1bd5fc 343 PCI_USES_MASTER, IS_BOOMERANG|HAS_MII|EEPROM_8BIT, 128, },
1da177e4 344 {"3CCFE575BT Cyclone CardBus",
1f1bd5fc 345 PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_CB_FNS|EEPROM_8BIT|
1da177e4
LT		 346 INVERT_LED_PWR|HAS_HWCKSM, 128, },
347 {"3CCFE575CT Tornado CardBus",
1f1bd5fc 348 PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|HAS_CB_FNS|EEPROM_8BIT|INVERT_MII_PWR|
1da177e4
LT		 349 MAX_COLLISION_RESET|HAS_HWCKSM, 128, },
350 {"3CCFE656 Cyclone CardBus",
1f1bd5fc 351 PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_CB_FNS|EEPROM_8BIT|INVERT_MII_PWR|
1da177e4
LT		 352 INVERT_LED_PWR|HAS_HWCKSM, 128, },
353
354 {"3CCFEM656B Cyclone+Winmodem CardBus",
1f1bd5fc 355 PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_CB_FNS|EEPROM_8BIT|INVERT_MII_PWR|
1da177e4
LT		 356 INVERT_LED_PWR|HAS_HWCKSM, 128, },
357 {"3CXFEM656C Tornado+Winmodem CardBus", /* From pcmcia-cs-3.1.5 */
1f1bd5fc 358 PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|HAS_CB_FNS|EEPROM_8BIT|INVERT_MII_PWR|
1da177e4
LT		 359 MAX_COLLISION_RESET|HAS_HWCKSM, 128, },
360 {"3c450 HomePNA Tornado", /* AKPM: from Don's 0.99Q */
1f1bd5fc 361 PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|HAS_HWCKSM, 128, },
1da177e4 362 {"3c920 Tornado",
1f1bd5fc 363 PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|HAS_HWCKSM, 128, },
1da177e4 364 {"3c982 Hydra Dual Port A",
1f1bd5fc 365 PCI_USES_MASTER, IS_TORNADO|HAS_HWCKSM|HAS_NWAY, 128, },
1da177e4
LT		 366
367 {"3c982 Hydra Dual Port B",
1f1bd5fc 368 PCI_USES_MASTER, IS_TORNADO|HAS_HWCKSM|HAS_NWAY, 128, },
1da177e4 369 {"3c905B-T4",
1f1bd5fc 370 PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_HWCKSM|EXTRA_PREAMBLE, 128, },
1da177e4 371 {"3c920B-EMB-WNM Tornado",
1f1bd5fc 372 PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|HAS_HWCKSM, 128, },
1da177e4
LT		 373
374 {NULL,}, /* NULL terminated list. */
375};
376
377
a3aa1884 378static DEFINE_PCI_DEVICE_TABLE(vortex_pci_tbl) = {
1da177e4
LT		 379 { 0x10B7, 0x5900, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C590 },
380 { 0x10B7, 0x5920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C592 },
381 { 0x10B7, 0x5970, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C597 },
382 { 0x10B7, 0x5950, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C595_1 },
383 { 0x10B7, 0x5951, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C595_2 },
384
385 { 0x10B7, 0x5952, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C595_3 },
386 { 0x10B7, 0x9000, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C900_1 },
387 { 0x10B7, 0x9001, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C900_2 },
388 { 0x10B7, 0x9004, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C900_3 },
389 { 0x10B7, 0x9005, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C900_4 },
390
391 { 0x10B7, 0x9006, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C900_5 },
392 { 0x10B7, 0x900A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C900B_FL },
393 { 0x10B7, 0x9050, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905_1 },
394 { 0x10B7, 0x9051, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905_2 },
b4adbb4d 395 { 0x10B7, 0x9054, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905B_TX },
1da177e4
LT		 396 { 0x10B7, 0x9055, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905B_1 },
397
398 { 0x10B7, 0x9058, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905B_2 },
399 { 0x10B7, 0x905A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905B_FX },
400 { 0x10B7, 0x9200, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905C },
401 { 0x10B7, 0x9202, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C9202 },
402 { 0x10B7, 0x9800, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C980 },
403 { 0x10B7, 0x9805, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C9805 },
404
405 { 0x10B7, 0x7646, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3CSOHO100_TX },
406 { 0x10B7, 0x5055, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C555 },
407 { 0x10B7, 0x6055, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C556 },
408 { 0x10B7, 0x6056, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C556B },
409 { 0x10B7, 0x5b57, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C575 },
410
411 { 0x10B7, 0x5057, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C575_1 },
412 { 0x10B7, 0x5157, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3CCFE575 },
413 { 0x10B7, 0x5257, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3CCFE575CT },
414 { 0x10B7, 0x6560, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3CCFE656 },
415 { 0x10B7, 0x6562, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3CCFEM656 },
416
417 { 0x10B7, 0x6564, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3CCFEM656_1 },
418 { 0x10B7, 0x4500, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C450 },
419 { 0x10B7, 0x9201, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C920 },
420 { 0x10B7, 0x1201, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C982A },
421 { 0x10B7, 0x1202, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C982B },
422
423 { 0x10B7, 0x9056, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_905BT4 },
424 { 0x10B7, 0x9210, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_920B_EMB_WNM },
425
426 {0,} /* 0 terminated list. */
427};
428MODULE_DEVICE_TABLE(pci, vortex_pci_tbl);
429
430
431/* Operational definitions.
432 These are not used by other compilation units and thus are not
433 exported in a ".h" file.
434
435 First the windows. There are eight register windows, with the command
436 and status registers available in each.
437 */
62afe595 438#define EL3WINDOW(win_num) iowrite16(SelectWindow + (win_num), ioaddr + EL3_CMD)
1da177e4
LT		 439#define EL3_CMD 0x0e
440#define EL3_STATUS 0x0e
441
442/* The top five bits written to EL3_CMD are a command, the lower
443 11 bits are the parameter, if applicable.
444 Note that 11 parameters bits was fine for ethernet, but the new chip
445 can handle FDDI length frames (~4500 octets) and now parameters count
446 32-bit 'Dwords' rather than octets. */
447
448enum vortex_cmd {
449 TotalReset = 0<<11, SelectWindow = 1<<11, StartCoax = 2<<11,
450 RxDisable = 3<<11, RxEnable = 4<<11, RxReset = 5<<11,
451 UpStall = 6<<11, UpUnstall = (6<<11)+1,
452 DownStall = (6<<11)+2, DownUnstall = (6<<11)+3,
453 RxDiscard = 8<<11, TxEnable = 9<<11, TxDisable = 10<<11, TxReset = 11<<11,
454 FakeIntr = 12<<11, AckIntr = 13<<11, SetIntrEnb = 14<<11,
455 SetStatusEnb = 15<<11, SetRxFilter = 16<<11, SetRxThreshold = 17<<11,
456 SetTxThreshold = 18<<11, SetTxStart = 19<<11,
457 StartDMAUp = 20<<11, StartDMADown = (20<<11)+1, StatsEnable = 21<<11,
458 StatsDisable = 22<<11, StopCoax = 23<<11, SetFilterBit = 25<<11,};
459
460/* The SetRxFilter command accepts the following classes: */
461enum RxFilter {
462 RxStation = 1, RxMulticast = 2, RxBroadcast = 4, RxProm = 8 };
463
464/* Bits in the general status register. */
465enum vortex_status {
466 IntLatch = 0x0001, HostError = 0x0002, TxComplete = 0x0004,
467 TxAvailable = 0x0008, RxComplete = 0x0010, RxEarly = 0x0020,
468 IntReq = 0x0040, StatsFull = 0x0080,
469 DMADone = 1<<8, DownComplete = 1<<9, UpComplete = 1<<10,
470 DMAInProgress = 1<<11, /* DMA controller is still busy.*/
471 CmdInProgress = 1<<12, /* EL3_CMD is still busy.*/
472};
473
474/* Register window 1 offsets, the window used in normal operation.
475 On the Vortex this window is always mapped at offsets 0x10-0x1f. */
476enum Window1 {
477 TX_FIFO = 0x10, RX_FIFO = 0x10, RxErrors = 0x14,
478 RxStatus = 0x18, Timer=0x1A, TxStatus = 0x1B,
479 TxFree = 0x1C, /* Remaining free bytes in Tx buffer. */
480};
481enum Window0 {
482 Wn0EepromCmd = 10, /* Window 0: EEPROM command register. */
483 Wn0EepromData = 12, /* Window 0: EEPROM results register. */
484 IntrStatus=0x0E, /* Valid in all windows. */
485};
486enum Win0_EEPROM_bits {
487 EEPROM_Read = 0x80, EEPROM_WRITE = 0x40, EEPROM_ERASE = 0xC0,
488 EEPROM_EWENB = 0x30, /* Enable erasing/writing for 10 msec. */
489 EEPROM_EWDIS = 0x00, /* Disable EWENB before 10 msec timeout. */
490};
491/* EEPROM locations. */
492enum eeprom_offset {
493 PhysAddr01=0, PhysAddr23=1, PhysAddr45=2, ModelID=3,
494 EtherLink3ID=7, IFXcvrIO=8, IRQLine=9,
495 NodeAddr01=10, NodeAddr23=11, NodeAddr45=12,
496 DriverTune=13, Checksum=15};
497
498enum Window2 { /* Window 2. */
499 Wn2_ResetOptions=12,
500};
501enum Window3 { /* Window 3: MAC/config bits. */
502 Wn3_Config=0, Wn3_MaxPktSize=4, Wn3_MAC_Ctrl=6, Wn3_Options=8,
503};
504
505#define BFEXT(value, offset, bitcount) \
506 ((((unsigned long)(value)) >> (offset)) & ((1 << (bitcount)) - 1))
507
508#define BFINS(lhs, rhs, offset, bitcount) \
509 (((lhs) & ~((((1 << (bitcount)) - 1)) << (offset))) | \
510 (((rhs) & ((1 << (bitcount)) - 1)) << (offset)))
511
512#define RAM_SIZE(v) BFEXT(v, 0, 3)
513#define RAM_WIDTH(v) BFEXT(v, 3, 1)
514#define RAM_SPEED(v) BFEXT(v, 4, 2)
515#define ROM_SIZE(v) BFEXT(v, 6, 2)
516#define RAM_SPLIT(v) BFEXT(v, 16, 2)
517#define XCVR(v) BFEXT(v, 20, 4)
518#define AUTOSELECT(v) BFEXT(v, 24, 1)
519
520enum Window4 { /* Window 4: Xcvr/media bits. */
521 Wn4_FIFODiag = 4, Wn4_NetDiag = 6, Wn4_PhysicalMgmt=8, Wn4_Media = 10,
522};
523enum Win4_Media_bits {
524 Media_SQE = 0x0008, /* Enable SQE error counting for AUI. */
525 Media_10TP = 0x00C0, /* Enable link beat and jabber for 10baseT. */
526 Media_Lnk = 0x0080, /* Enable just link beat for 100TX/100FX. */
527 Media_LnkBeat = 0x0800,
528};
529enum Window7 { /* Window 7: Bus Master control. */
530 Wn7_MasterAddr = 0, Wn7_VlanEtherType=4, Wn7_MasterLen = 6,
531 Wn7_MasterStatus = 12,
532};
533/* Boomerang bus master control registers. */
534enum MasterCtrl {
535 PktStatus = 0x20, DownListPtr = 0x24, FragAddr = 0x28, FragLen = 0x2c,
536 TxFreeThreshold = 0x2f, UpPktStatus = 0x30, UpListPtr = 0x38,
537};
538
539/* The Rx and Tx descriptor lists.
540 Caution Alpha hackers: these types are 32 bits! Note also the 8 byte
541 alignment contraint on tx_ring[] and rx_ring[]. */
542#define LAST_FRAG 0x80000000 /* Last Addr/Len pair in descriptor. */
543#define DN_COMPLETE 0x00010000 /* This packet has been downloaded */
544struct boom_rx_desc {
cc2d6596
AV		 545 __le32 next; /* Last entry points to 0. */
546 __le32 status;
547 __le32 addr; /* Up to 63 addr/len pairs possible. */
548 __le32 length; /* Set LAST_FRAG to indicate last pair. */
1da177e4
LT		 549};
550/* Values for the Rx status entry. */
551enum rx_desc_status {
552 RxDComplete=0x00008000, RxDError=0x4000,
553 /* See boomerang_rx() for actual error bits */
554 IPChksumErr=1<<25, TCPChksumErr=1<<26, UDPChksumErr=1<<27,
555 IPChksumValid=1<<29, TCPChksumValid=1<<30, UDPChksumValid=1<<31,
556};
557
558#ifdef MAX_SKB_FRAGS
559#define DO_ZEROCOPY 1
560#else
561#define DO_ZEROCOPY 0
562#endif
563
564struct boom_tx_desc {
cc2d6596
AV		 565 __le32 next; /* Last entry points to 0. */
566 __le32 status; /* bits 0:12 length, others see below. */
1da177e4
LT		 567#if DO_ZEROCOPY
568 struct {
cc2d6596
AV		 569 __le32 addr;
570 __le32 length;
1da177e4
LT		 571 } frag[1+MAX_SKB_FRAGS];
572#else
cc2d6596
AV		 573 __le32 addr;
574 __le32 length;
1da177e4
LT		 575#endif
576};
577
578/* Values for the Tx status entry. */
579enum tx_desc_status {
580 CRCDisable=0x2000, TxDComplete=0x8000,
581 AddIPChksum=0x02000000, AddTCPChksum=0x04000000, AddUDPChksum=0x08000000,
582 TxIntrUploaded=0x80000000, /* IRQ when in FIFO, but maybe not sent. */
583};
584
585/* Chip features we care about in vp->capabilities, read from the EEPROM. */
586enum ChipCaps { CapBusMaster=0x20, CapPwrMgmt=0x2000 };
587
588struct vortex_extra_stats {
8d1d0340
SK		 589 unsigned long tx_deferred;
590 unsigned long tx_max_collisions;
591 unsigned long tx_multiple_collisions;
592 unsigned long tx_single_collisions;
593 unsigned long rx_bad_ssd;
1da177e4
LT		 594};
595
596struct vortex_private {
597 /* The Rx and Tx rings should be quad-word-aligned. */
598 struct boom_rx_desc* rx_ring;
599 struct boom_tx_desc* tx_ring;
600 dma_addr_t rx_ring_dma;
601 dma_addr_t tx_ring_dma;
602 /* The addresses of transmit- and receive-in-place skbuffs. */
603 struct sk_buff* rx_skbuff[RX_RING_SIZE];
604 struct sk_buff* tx_skbuff[TX_RING_SIZE];
605 unsigned int cur_rx, cur_tx; /* The next free ring entry */
606 unsigned int dirty_rx, dirty_tx; /* The ring entries to be free()ed. */
1da177e4
LT		 607 struct vortex_extra_stats xstats; /* NIC-specific extra stats */
608 struct sk_buff *tx_skb; /* Packet being eaten by bus master ctrl. */
609 dma_addr_t tx_skb_dma; /* Allocated DMA address for bus master ctrl DMA. */
610
611 /* PCI configuration space information. */
612 struct device *gendev;
62afe595
JL		 613 void __iomem *ioaddr; /* IO address space */
614 void __iomem *cb_fn_base; /* CardBus function status addr space. */
1da177e4
LT		 615
616 /* Some values here only for performance evaluation and path-coverage */
617 int rx_nocopy, rx_copy, queued_packet, rx_csumhits;
618 int card_idx;
619
620 /* The remainder are related to chip state, mostly media selection. */
621 struct timer_list timer; /* Media selection timer. */
622 struct timer_list rx_oom_timer; /* Rx skb allocation retry timer */
623 int options; /* User-settable misc. driver options. */
624 unsigned int media_override:4, /* Passed-in media type. */
625 default_media:4, /* Read from the EEPROM/Wn3_Config. */
09ce3512 626 full_duplex:1, autoselect:1,
1da177e4
LT		 627 bus_master:1, /* Vortex can only do a fragment bus-m. */
628 full_bus_master_tx:1, full_bus_master_rx:2, /* Boomerang */
629 flow_ctrl:1, /* Use 802.3x flow control (PAUSE only) */
630 partner_flow_ctrl:1, /* Partner supports flow control */
631 has_nway:1,
632 enable_wol:1, /* Wake-on-LAN is enabled */
633 pm_state_valid:1, /* pci_dev->saved_config_space has sane contents */
634 open:1,
635 medialock:1,
636 must_free_region:1, /* Flag: if zero, Cardbus owns the I/O region */
637 large_frames:1; /* accept large frames */
638 int drv_flags;
639 u16 status_enable;
640 u16 intr_enable;
641 u16 available_media; /* From Wn3_Options. */
642 u16 capabilities, info1, info2; /* Various, from EEPROM. */
643 u16 advertising; /* NWay media advertisement */
644 unsigned char phys[2]; /* MII device addresses. */
645 u16 deferred; /* Resend these interrupts when we
646 * bale from the ISR */
647 u16 io_size; /* Size of PCI region (for release_region) */
648 spinlock_t lock; /* Serialise access to device & its vortex_private */
649 struct mii_if_info mii; /* MII lib hooks/info */
650};
651
652#ifdef CONFIG_PCI
653#define DEVICE_PCI(dev) (((dev)->bus == &pci_bus_type) ? to_pci_dev((dev)) : NULL)
654#else
655#define DEVICE_PCI(dev) NULL
656#endif
657
658#define VORTEX_PCI(vp) (((vp)->gendev) ? DEVICE_PCI((vp)->gendev) : NULL)
659
660#ifdef CONFIG_EISA
661#define DEVICE_EISA(dev) (((dev)->bus == &eisa_bus_type) ? to_eisa_device((dev)) : NULL)
662#else
663#define DEVICE_EISA(dev) NULL
664#endif
665
666#define VORTEX_EISA(vp) (((vp)->gendev) ? DEVICE_EISA((vp)->gendev) : NULL)
667
668/* The action to take with a media selection timer tick.
669 Note that we deviate from the 3Com order by checking 10base2 before AUI.
670 */
671enum xcvr_types {
672 XCVR_10baseT=0, XCVR_AUI, XCVR_10baseTOnly, XCVR_10base2, XCVR_100baseTx,
673 XCVR_100baseFx, XCVR_MII=6, XCVR_NWAY=8, XCVR_ExtMII=9, XCVR_Default=10,
674};
675
f71e1309 676static const struct media_table {
1da177e4
LT		 677 char *name;
678 unsigned int media_bits:16, /* Bits to set in Wn4_Media register. */
679 mask:8, /* The transceiver-present bit in Wn3_Config.*/
680 next:8; /* The media type to try next. */
681 int wait; /* Time before we check media status. */
682} media_tbl[] = {
683 { "10baseT", Media_10TP,0x08, XCVR_10base2, (14*HZ)/10},
684 { "10Mbs AUI", Media_SQE, 0x20, XCVR_Default, (1*HZ)/10},
685 { "undefined", 0, 0x80, XCVR_10baseT, 10000},
686 { "10base2", 0, 0x10, XCVR_AUI, (1*HZ)/10},
687 { "100baseTX", Media_Lnk, 0x02, XCVR_100baseFx, (14*HZ)/10},
688 { "100baseFX", Media_Lnk, 0x04, XCVR_MII, (14*HZ)/10},
689 { "MII", 0, 0x41, XCVR_10baseT, 3*HZ },
690 { "undefined", 0, 0x01, XCVR_10baseT, 10000},
691 { "Autonegotiate", 0, 0x41, XCVR_10baseT, 3*HZ},
692 { "MII-External", 0, 0x41, XCVR_10baseT, 3*HZ },
693 { "Default", 0, 0xFF, XCVR_10baseT, 10000},
694};
695
696static struct {
697 const char str[ETH_GSTRING_LEN];
698} ethtool_stats_keys[] = {
699 { "tx_deferred" },
8d1d0340 700 { "tx_max_collisions" },
1da177e4 701 { "tx_multiple_collisions" },
8d1d0340 702 { "tx_single_collisions" },
1da177e4
LT		 703 { "rx_bad_ssd" },
704};
705
706/* number of ETHTOOL_GSTATS u64's */
8d1d0340 707#define VORTEX_NUM_STATS 5
1da177e4 708
62afe595 709static int vortex_probe1(struct device *gendev, void __iomem *ioaddr, int irq,
1da177e4 710 int chip_idx, int card_idx);
c8303d10 711static int vortex_up(struct net_device *dev);
1da177e4
LT		 712static void vortex_down(struct net_device *dev, int final);
713static int vortex_open(struct net_device *dev);
62afe595 714static void mdio_sync(void __iomem *ioaddr, int bits);
1da177e4
LT		 715static int mdio_read(struct net_device *dev, int phy_id, int location);
716static void mdio_write(struct net_device *vp, int phy_id, int location, int value);
717static void vortex_timer(unsigned long arg);
718static void rx_oom_timer(unsigned long arg);
27a1de95
SH		 719static netdev_tx_t vortex_start_xmit(struct sk_buff *skb,
720 struct net_device *dev);
721static netdev_tx_t boomerang_start_xmit(struct sk_buff *skb,
722 struct net_device *dev);
1da177e4
LT		 723static int vortex_rx(struct net_device *dev);
724static int boomerang_rx(struct net_device *dev);
7d12e780
DH		 725static irqreturn_t vortex_interrupt(int irq, void *dev_id);
726static irqreturn_t boomerang_interrupt(int irq, void *dev_id);
1da177e4
LT		 727static int vortex_close(struct net_device *dev);
728static void dump_tx_ring(struct net_device *dev);
62afe595 729static void update_stats(void __iomem *ioaddr, struct net_device *dev);
1da177e4
LT		 730static struct net_device_stats *vortex_get_stats(struct net_device *dev);
731static void set_rx_mode(struct net_device *dev);
732#ifdef CONFIG_PCI
733static int vortex_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
734#endif
735static void vortex_tx_timeout(struct net_device *dev);
736static void acpi_set_WOL(struct net_device *dev);
7282d491 737static const struct ethtool_ops vortex_ethtool_ops;
1da177e4
LT		 738static void set_8021q_mode(struct net_device *dev, int enable);
739
1da177e4
LT		 740/* This driver uses 'options' to pass the media type, full-duplex flag, etc. */
741/* Option count limit only -- unlimited interfaces are supported. */
742#define MAX_UNITS 8
9954ab7f
JL		 743static int options[MAX_UNITS] = { [0 ... MAX_UNITS-1] = -1 };
744static int full_duplex[MAX_UNITS] = {[0 ... MAX_UNITS-1] = -1 };
745static int hw_checksums[MAX_UNITS] = {[0 ... MAX_UNITS-1] = -1 };
746static int flow_ctrl[MAX_UNITS] = {[0 ... MAX_UNITS-1] = -1 };
747static int enable_wol[MAX_UNITS] = {[0 ... MAX_UNITS-1] = -1 };
900fd17d 748static int use_mmio[MAX_UNITS] = {[0 ... MAX_UNITS-1] = -1 };
1da177e4
LT		 749static int global_options = -1;
750static int global_full_duplex = -1;
751static int global_enable_wol = -1;
900fd17d 752static int global_use_mmio = -1;
1da177e4 753
1da177e4
LT		 754/* Variables to work-around the Compaq PCI BIOS32 problem. */
755static int compaq_ioaddr, compaq_irq, compaq_device_id = 0x5900;
756static struct net_device *compaq_net_device;
757
758static int vortex_cards_found;
759
760module_param(debug, int, 0);
761module_param(global_options, int, 0);
762module_param_array(options, int, NULL, 0);
763module_param(global_full_duplex, int, 0);
764module_param_array(full_duplex, int, NULL, 0);
765module_param_array(hw_checksums, int, NULL, 0);
766module_param_array(flow_ctrl, int, NULL, 0);
767module_param(global_enable_wol, int, 0);
768module_param_array(enable_wol, int, NULL, 0);
769module_param(rx_copybreak, int, 0);
770module_param(max_interrupt_work, int, 0);
771module_param(compaq_ioaddr, int, 0);
772module_param(compaq_irq, int, 0);
773module_param(compaq_device_id, int, 0);
774module_param(watchdog, int, 0);
900fd17d
JL		 775module_param(global_use_mmio, int, 0);
776module_param_array(use_mmio, int, NULL, 0);
1da177e4
LT		 777MODULE_PARM_DESC(debug, "3c59x debug level (0-6)");
778MODULE_PARM_DESC(options, "3c59x: Bits 0-3: media type, bit 4: bus mastering, bit 9: full duplex");
779MODULE_PARM_DESC(global_options, "3c59x: same as options, but applies to all NICs if options is unset");
780MODULE_PARM_DESC(full_duplex, "3c59x full duplex setting(s) (1)");
46e5e4a8 781MODULE_PARM_DESC(global_full_duplex, "3c59x: same as full_duplex, but applies to all NICs if full_duplex is unset");
1da177e4
LT		 782MODULE_PARM_DESC(hw_checksums, "3c59x Hardware checksum checking by adapter(s) (0-1)");
783MODULE_PARM_DESC(flow_ctrl, "3c59x 802.3x flow control usage (PAUSE only) (0-1)");
784MODULE_PARM_DESC(enable_wol, "3c59x: Turn on Wake-on-LAN for adapter(s) (0-1)");
46e5e4a8 785MODULE_PARM_DESC(global_enable_wol, "3c59x: same as enable_wol, but applies to all NICs if enable_wol is unset");
1da177e4
LT		 786MODULE_PARM_DESC(rx_copybreak, "3c59x copy breakpoint for copy-only-tiny-frames");
787MODULE_PARM_DESC(max_interrupt_work, "3c59x maximum events handled per interrupt");
788MODULE_PARM_DESC(compaq_ioaddr, "3c59x PCI I/O base address (Compaq BIOS problem workaround)");
789MODULE_PARM_DESC(compaq_irq, "3c59x PCI IRQ number (Compaq BIOS problem workaround)");
790MODULE_PARM_DESC(compaq_device_id, "3c59x PCI device ID (Compaq BIOS problem workaround)");
791MODULE_PARM_DESC(watchdog, "3c59x transmit timeout in milliseconds");
900fd17d
JL		 792MODULE_PARM_DESC(global_use_mmio, "3c59x: same as use_mmio, but applies to all NICs if options is unset");
793MODULE_PARM_DESC(use_mmio, "3c59x: use memory-mapped PCI I/O resource (0-1)");
1da177e4
LT		 794
795#ifdef CONFIG_NET_POLL_CONTROLLER
796static void poll_vortex(struct net_device *dev)
797{
798 struct vortex_private *vp = netdev_priv(dev);
799 unsigned long flags;
0d38ff1d 800 local_irq_save(flags);
7d12e780 801 (vp->full_bus_master_rx ? boomerang_interrupt:vortex_interrupt)(dev->irq,dev);
1da177e4 802 local_irq_restore(flags);
6aa20a22 803}
1da177e4
LT		 804#endif
805
806#ifdef CONFIG_PM
807
7bfc4ab5 808static int vortex_suspend(struct device *dev)
1da177e4 809{
7bfc4ab5
AV		 810 struct pci_dev *pdev = to_pci_dev(dev);
811 struct net_device *ndev = pci_get_drvdata(pdev);
812
813 if (!ndev || !netif_running(ndev))
814 return 0;
815
816 netif_device_detach(ndev);
817 vortex_down(ndev, 1);
1da177e4 818
1da177e4
LT		 819 return 0;
820}
821
7bfc4ab5 822static int vortex_resume(struct device *dev)
1da177e4 823{
7bfc4ab5
AV		 824 struct pci_dev *pdev = to_pci_dev(dev);
825 struct net_device *ndev = pci_get_drvdata(pdev);
e1265153 826 int err;
1da177e4 827
7bfc4ab5
AV		 828 if (!ndev || !netif_running(ndev))
829 return 0;
830
831 err = vortex_up(ndev);
832 if (err)
833 return err;
834
835 netif_device_attach(ndev);
836
1da177e4
LT		 837 return 0;
838}
839
47145210 840static const struct dev_pm_ops vortex_pm_ops = {
7bfc4ab5
AV		 841 .suspend = vortex_suspend,
842 .resume = vortex_resume,
843 .freeze = vortex_suspend,
844 .thaw = vortex_resume,
845 .poweroff = vortex_suspend,
846 .restore = vortex_resume,
847};
848
849#define VORTEX_PM_OPS (&vortex_pm_ops)
850
851#else /* !CONFIG_PM */
852
853#define VORTEX_PM_OPS NULL
854
855#endif /* !CONFIG_PM */
1da177e4
LT		 856
857#ifdef CONFIG_EISA
858static struct eisa_device_id vortex_eisa_ids[] = {
859 { "TCM5920", CH_3C592 },
860 { "TCM5970", CH_3C597 },
861 { "" }
862};
07563c71 863MODULE_DEVICE_TABLE(eisa, vortex_eisa_ids);
1da177e4 864
95c408a9 865static int __init vortex_eisa_probe(struct device *device)
1da177e4 866{
62afe595 867 void __iomem *ioaddr;
1da177e4
LT		 868 struct eisa_device *edev;
869
a880c4cd 870 edev = to_eisa_device(device);
1da177e4 871
62afe595 872 if (!request_region(edev->base_addr, VORTEX_TOTAL_SIZE, DRV_NAME))
1da177e4
LT		 873 return -EBUSY;
874
62afe595
JL		 875 ioaddr = ioport_map(edev->base_addr, VORTEX_TOTAL_SIZE);
876
877 if (vortex_probe1(device, ioaddr, ioread16(ioaddr + 0xC88) >> 12,
1da177e4 878 edev->id.driver_data, vortex_cards_found)) {
a880c4cd 879 release_region(edev->base_addr, VORTEX_TOTAL_SIZE);
1da177e4
LT		 880 return -ENODEV;
881 }
882
883 vortex_cards_found++;
884
885 return 0;
886}
887
95c408a9 888static int __devexit vortex_eisa_remove(struct device *device)
1da177e4
LT		 889{
890 struct eisa_device *edev;
891 struct net_device *dev;
892 struct vortex_private *vp;
62afe595 893 void __iomem *ioaddr;
1da177e4 894
a880c4cd
SK		 895 edev = to_eisa_device(device);
896 dev = eisa_get_drvdata(edev);
1da177e4
LT		 897
898 if (!dev) {
39738e16 899 pr_err("vortex_eisa_remove called for Compaq device!\n");
1da177e4
LT		 900 BUG();
901 }
902
903 vp = netdev_priv(dev);
62afe595 904 ioaddr = vp->ioaddr;
6aa20a22 905
a880c4cd
SK		 906 unregister_netdev(dev);
907 iowrite16(TotalReset|0x14, ioaddr + EL3_CMD);
908 release_region(dev->base_addr, VORTEX_TOTAL_SIZE);
1da177e4 909
a880c4cd 910 free_netdev(dev);
1da177e4
LT		 911 return 0;
912}
95c408a9
RB		 913
914static struct eisa_driver vortex_eisa_driver = {
915 .id_table = vortex_eisa_ids,
916 .driver = {
917 .name = "3c59x",
918 .probe = vortex_eisa_probe,
919 .remove = __devexit_p(vortex_eisa_remove)
920 }
921};
922
923#endif /* CONFIG_EISA */
1da177e4
LT		 924
925/* returns count found (>= 0), or negative on error */
a880c4cd 926static int __init vortex_eisa_init(void)
1da177e4
LT		 927{
928 int eisa_found = 0;
929 int orig_cards_found = vortex_cards_found;
930
931#ifdef CONFIG_EISA
c2f6fabb
BH		 932 int err;
933
934 err = eisa_driver_register (&vortex_eisa_driver);
935 if (!err) {
936 /*
937 * Because of the way EISA bus is probed, we cannot assume
938 * any device have been found when we exit from
939 * eisa_driver_register (the bus root driver may not be
940 * initialized yet). So we blindly assume something was
941 * found, and let the sysfs magic happend...
942 */
943 eisa_found = 1;
1da177e4
LT		 944 }
945#endif
6aa20a22 946
1da177e4
LT		 947 /* Special code to work-around the Compaq PCI BIOS32 problem. */
948 if (compaq_ioaddr) {
62afe595
JL		 949 vortex_probe1(NULL, ioport_map(compaq_ioaddr, VORTEX_TOTAL_SIZE),
950 compaq_irq, compaq_device_id, vortex_cards_found++);
1da177e4
LT		 951 }
952
953 return vortex_cards_found - orig_cards_found + eisa_found;
954}
955
956/* returns count (>= 0), or negative on error */
a880c4cd 957static int __devinit vortex_init_one(struct pci_dev *pdev,
1da177e4
LT		 958 const struct pci_device_id *ent)
959{
900fd17d
JL		 960 int rc, unit, pci_bar;
961 struct vortex_chip_info *vci;
962 void __iomem *ioaddr;
1da177e4 963
6aa20a22 964 /* wake up and enable device */
a880c4cd 965 rc = pci_enable_device(pdev);
1da177e4
LT		 966 if (rc < 0)
967 goto out;
968
900fd17d
JL		 969 unit = vortex_cards_found;
970
971 if (global_use_mmio < 0 && (unit >= MAX_UNITS || use_mmio[unit] < 0)) {
972 /* Determine the default if the user didn't override us */
973 vci = &vortex_info_tbl[ent->driver_data];
974 pci_bar = vci->drv_flags & (IS_CYCLONE | IS_TORNADO) ? 1 : 0;
975 } else if (unit < MAX_UNITS && use_mmio[unit] >= 0)
976 pci_bar = use_mmio[unit] ? 1 : 0;
977 else
978 pci_bar = global_use_mmio ? 1 : 0;
979
980 ioaddr = pci_iomap(pdev, pci_bar, 0);
981 if (!ioaddr) /* If mapping fails, fall-back to BAR 0... */
982 ioaddr = pci_iomap(pdev, 0, 0);
983
984 rc = vortex_probe1(&pdev->dev, ioaddr, pdev->irq,
985 ent->driver_data, unit);
1da177e4 986 if (rc < 0) {
a880c4cd 987 pci_disable_device(pdev);
1da177e4
LT		 988 goto out;
989 }
990
991 vortex_cards_found++;
992
993out:
994 return rc;
995}
996
48b47a5e
SH		 997static const struct net_device_ops boomrang_netdev_ops = {
998 .ndo_open = vortex_open,
999 .ndo_stop = vortex_close,
1000 .ndo_start_xmit = boomerang_start_xmit,
1001 .ndo_tx_timeout = vortex_tx_timeout,
1002 .ndo_get_stats = vortex_get_stats,
1003#ifdef CONFIG_PCI
1004 .ndo_do_ioctl = vortex_ioctl,
1005#endif
1006 .ndo_set_multicast_list = set_rx_mode,
1007 .ndo_change_mtu = eth_change_mtu,
1008 .ndo_set_mac_address = eth_mac_addr,
1009 .ndo_validate_addr = eth_validate_addr,
1010#ifdef CONFIG_NET_POLL_CONTROLLER
1011 .ndo_poll_controller = poll_vortex,
1012#endif
1013};
1014
1015static const struct net_device_ops vortex_netdev_ops = {
1016 .ndo_open = vortex_open,
1017 .ndo_stop = vortex_close,
1018 .ndo_start_xmit = vortex_start_xmit,
1019 .ndo_tx_timeout = vortex_tx_timeout,
1020 .ndo_get_stats = vortex_get_stats,
1021#ifdef CONFIG_PCI
1022 .ndo_do_ioctl = vortex_ioctl,
1023#endif
1024 .ndo_set_multicast_list = set_rx_mode,
1025 .ndo_change_mtu = eth_change_mtu,
1026 .ndo_set_mac_address = eth_mac_addr,
1027 .ndo_validate_addr = eth_validate_addr,
1028#ifdef CONFIG_NET_POLL_CONTROLLER
1029 .ndo_poll_controller = poll_vortex,
1030#endif
1031};
1032
1da177e4
LT		 1033/*
1034 * Start up the PCI/EISA device which is described by *gendev.
1035 * Return 0 on success.
1036 *
1037 * NOTE: pdev can be NULL, for the case of a Compaq device
1038 */
1039static int __devinit vortex_probe1(struct device *gendev,
62afe595 1040 void __iomem *ioaddr, int irq,
1da177e4
LT		 1041 int chip_idx, int card_idx)
1042{
1043 struct vortex_private *vp;
1044 int option;
1045 unsigned int eeprom[0x40], checksum = 0; /* EEPROM contents */
1046 int i, step;
1047 struct net_device *dev;
1048 static int printed_version;
1049 int retval, print_info;
1050 struct vortex_chip_info * const vci = &vortex_info_tbl[chip_idx];
361d5ee3 1051 const char *print_name = "3c59x";
1da177e4
LT		 1052 struct pci_dev *pdev = NULL;
1053 struct eisa_device *edev = NULL;
1054
1055 if (!printed_version) {
39738e16 1056 pr_info("%s", version);
1da177e4
LT		 1057 printed_version = 1;
1058 }
1059
1060 if (gendev) {
1061 if ((pdev = DEVICE_PCI(gendev))) {
1062 print_name = pci_name(pdev);
1063 }
1064
1065 if ((edev = DEVICE_EISA(gendev))) {
fb28ad35 1066 print_name = dev_name(&edev->dev);
1da177e4
LT		 1067 }
1068 }
1069
1070 dev = alloc_etherdev(sizeof(*vp));
1071 retval = -ENOMEM;
1072 if (!dev) {
39738e16 1073 pr_err(PFX "unable to allocate etherdev, aborting\n");
1da177e4
LT		 1074 goto out;
1075 }
1da177e4
LT		 1076 SET_NETDEV_DEV(dev, gendev);
1077 vp = netdev_priv(dev);
1078
1079 option = global_options;
1080
1081 /* The lower four bits are the media type. */
1082 if (dev->mem_start) {
1083 /*
1084 * The 'options' param is passed in as the third arg to the
1085 * LILO 'ether=' argument for non-modular use
1086 */
1087 option = dev->mem_start;
1088 }
1089 else if (card_idx < MAX_UNITS) {
1090 if (options[card_idx] >= 0)
1091 option = options[card_idx];
1092 }
1093
1094 if (option > 0) {
1095 if (option & 0x8000)
1096 vortex_debug = 7;
1097 if (option & 0x4000)
1098 vortex_debug = 2;
1099 if (option & 0x0400)
1100 vp->enable_wol = 1;
1101 }
1102
1103 print_info = (vortex_debug > 1);
1104 if (print_info)
39738e16 1105 pr_info("See Documentation/networking/vortex.txt\n");
1da177e4 1106
39738e16 1107 pr_info("%s: 3Com %s %s at %p.\n",
1da177e4
LT		 1108 print_name,
1109 pdev ? "PCI" : "EISA",
1110 vci->name,
1111 ioaddr);
1112
62afe595 1113 dev->base_addr = (unsigned long)ioaddr;
1da177e4
LT		 1114 dev->irq = irq;
1115 dev->mtu = mtu;
62afe595 1116 vp->ioaddr = ioaddr;
1da177e4
LT		 1117 vp->large_frames = mtu > 1500;
1118 vp->drv_flags = vci->drv_flags;
1119 vp->has_nway = (vci->drv_flags & HAS_NWAY) ? 1 : 0;
1120 vp->io_size = vci->io_size;
1121 vp->card_idx = card_idx;
1122
1123 /* module list only for Compaq device */
1124 if (gendev == NULL) {
1125 compaq_net_device = dev;
1126 }
1127
1128 /* PCI-only startup logic */
1129 if (pdev) {
1130 /* EISA resources already marked, so only PCI needs to do this here */
1131 /* Ignore return value, because Cardbus drivers already allocate for us */
62afe595 1132 if (request_region(dev->base_addr, vci->io_size, print_name) != NULL)
1da177e4
LT		 1133 vp->must_free_region = 1;
1134
6aa20a22 1135 /* enable bus-mastering if necessary */
1da177e4 1136 if (vci->flags & PCI_USES_MASTER)
a880c4cd 1137 pci_set_master(pdev);
1da177e4
LT		 1138
1139 if (vci->drv_flags & IS_VORTEX) {
1140 u8 pci_latency;
1141 u8 new_latency = 248;
1142
1143 /* Check the PCI latency value. On the 3c590 series the latency timer
1144 must be set to the maximum value to avoid data corruption that occurs
1145 when the timer expires during a transfer. This bug exists the Vortex
1146 chip only. */
1147 pci_read_config_byte(pdev, PCI_LATENCY_TIMER, &pci_latency);
1148 if (pci_latency < new_latency) {
39738e16 1149 pr_info("%s: Overriding PCI latency timer (CFLT) setting of %d, new value is %d.\n",
1da177e4 1150 print_name, pci_latency, new_latency);
39738e16 1151 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, new_latency);
1da177e4
LT		 1152 }
1153 }
1154 }
1155
1156 spin_lock_init(&vp->lock);
1157 vp->gendev = gendev;
1158 vp->mii.dev = dev;
1159 vp->mii.mdio_read = mdio_read;
1160 vp->mii.mdio_write = mdio_write;
1161 vp->mii.phy_id_mask = 0x1f;
1162 vp->mii.reg_num_mask = 0x1f;
1163
1164 /* Makes sure rings are at least 16 byte aligned. */
1165 vp->rx_ring = pci_alloc_consistent(pdev, sizeof(struct boom_rx_desc) * RX_RING_SIZE
1166 + sizeof(struct boom_tx_desc) * TX_RING_SIZE,
1167 &vp->rx_ring_dma);
1168 retval = -ENOMEM;
cc2d6596 1169 if (!vp->rx_ring)
1da177e4
LT		 1170 goto free_region;
1171
1172 vp->tx_ring = (struct boom_tx_desc *)(vp->rx_ring + RX_RING_SIZE);
1173 vp->tx_ring_dma = vp->rx_ring_dma + sizeof(struct boom_rx_desc) * RX_RING_SIZE;
1174
1175 /* if we are a PCI driver, we store info in pdev->driver_data
6aa20a22 1176 * instead of a module list */
1da177e4
LT		 1177 if (pdev)
1178 pci_set_drvdata(pdev, dev);
1179 if (edev)
a880c4cd 1180 eisa_set_drvdata(edev, dev);
1da177e4
LT		 1181
1182 vp->media_override = 7;
1183 if (option >= 0) {
1184 vp->media_override = ((option & 7) == 2) ? 0 : option & 15;
1185 if (vp->media_override != 7)
1186 vp->medialock = 1;
1187 vp->full_duplex = (option & 0x200) ? 1 : 0;
1188 vp->bus_master = (option & 16) ? 1 : 0;
1189 }
1190
1191 if (global_full_duplex > 0)
1192 vp->full_duplex = 1;
1193 if (global_enable_wol > 0)
1194 vp->enable_wol = 1;
1195
1196 if (card_idx < MAX_UNITS) {
1197 if (full_duplex[card_idx] > 0)
1198 vp->full_duplex = 1;
1199 if (flow_ctrl[card_idx] > 0)
1200 vp->flow_ctrl = 1;
1201 if (enable_wol[card_idx] > 0)
1202 vp->enable_wol = 1;
1203 }
1204
125d5ce8 1205 vp->mii.force_media = vp->full_duplex;
1da177e4
LT		 1206 vp->options = option;
1207 /* Read the station address from the EEPROM. */
1208 EL3WINDOW(0);
1209 {
1210 int base;
1211
1212 if (vci->drv_flags & EEPROM_8BIT)
1213 base = 0x230;
1214 else if (vci->drv_flags & EEPROM_OFFSET)
1215 base = EEPROM_Read + 0x30;
1216 else
1217 base = EEPROM_Read;
1218
1219 for (i = 0; i < 0x40; i++) {
1220 int timer;
62afe595 1221 iowrite16(base + i, ioaddr + Wn0EepromCmd);
1da177e4
LT		 1222 /* Pause for at least 162 us. for the read to take place. */
1223 for (timer = 10; timer >= 0; timer--) {
1224 udelay(162);
62afe595 1225 if ((ioread16(ioaddr + Wn0EepromCmd) & 0x8000) == 0)
1da177e4
LT		 1226 break;
1227 }
62afe595 1228 eeprom[i] = ioread16(ioaddr + Wn0EepromData);
1da177e4
LT		 1229 }
1230 }
1231 for (i = 0; i < 0x18; i++)
1232 checksum ^= eeprom[i];
1233 checksum = (checksum ^ (checksum >> 8)) & 0xff;
1234 if (checksum != 0x00) { /* Grrr, needless incompatible change 3Com. */
1235 while (i < 0x21)
1236 checksum ^= eeprom[i++];
1237 checksum = (checksum ^ (checksum >> 8)) & 0xff;
1238 }
1239 if ((checksum != 0x00) && !(vci->drv_flags & IS_TORNADO))
39738e16 1240 pr_cont(" ***INVALID CHECKSUM %4.4x*** ", checksum);
1da177e4 1241 for (i = 0; i < 3; i++)
cc2d6596 1242 ((__be16 *)dev->dev_addr)[i] = htons(eeprom[i + 10]);
bb531fc0 1243 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
0795af57 1244 if (print_info)
39738e16 1245 pr_cont(" %pM", dev->dev_addr);
1da177e4
LT		 1246 /* Unfortunately an all zero eeprom passes the checksum and this
1247 gets found in the wild in failure cases. Crypto is hard 8) */
1248 if (!is_valid_ether_addr(dev->dev_addr)) {
1249 retval = -EINVAL;
39738e16 1250 pr_err("*** EEPROM MAC address is invalid.\n");
1da177e4
LT		 1251 goto free_ring; /* With every pack */
1252 }
1253 EL3WINDOW(2);
1254 for (i = 0; i < 6; i++)
62afe595 1255 iowrite8(dev->dev_addr[i], ioaddr + i);
1da177e4 1256
1da177e4 1257 if (print_info)
39738e16 1258 pr_cont(", IRQ %d\n", dev->irq);
1da177e4 1259 /* Tell them about an invalid IRQ. */
60e4ad7a 1260 if (dev->irq <= 0 || dev->irq >= nr_irqs)
39738e16 1261 pr_warning(" *** Warning: IRQ %d is unlikely to work! ***\n",
1da177e4 1262 dev->irq);
1da177e4
LT		 1263
1264 EL3WINDOW(4);
62afe595 1265 step = (ioread8(ioaddr + Wn4_NetDiag) & 0x1e) >> 1;
1da177e4 1266 if (print_info) {
39738e16
AB		 1267 pr_info(" product code %02x%02x rev %02x.%d date %02d-%02d-%02d\n",
1268 eeprom[6]&0xff, eeprom[6]>>8, eeprom[0x14],
1da177e4
LT		 1269 step, (eeprom[4]>>5) & 15, eeprom[4] & 31, eeprom[4]>>9);
1270 }
1271
1272
1273 if (pdev && vci->drv_flags & HAS_CB_FNS) {
1da177e4
LT		 1274 unsigned short n;
1275
62afe595
JL		 1276 vp->cb_fn_base = pci_iomap(pdev, 2, 0);
1277 if (!vp->cb_fn_base) {
1da177e4 1278 retval = -ENOMEM;
62afe595 1279 goto free_ring;
1da177e4 1280 }
62afe595 1281
1da177e4 1282 if (print_info) {
39738e16 1283 pr_info("%s: CardBus functions mapped %16.16llx->%p\n",
7c7459d1
GKH		 1284 print_name,
1285 (unsigned long long)pci_resource_start(pdev, 2),
62afe595 1286 vp->cb_fn_base);
1da177e4
LT		 1287 }
1288 EL3WINDOW(2);
1289
62afe595 1290 n = ioread16(ioaddr + Wn2_ResetOptions) & ~0x4010;
1da177e4
LT		 1291 if (vp->drv_flags & INVERT_LED_PWR)
1292 n |= 0x10;
1293 if (vp->drv_flags & INVERT_MII_PWR)
1294 n |= 0x4000;
62afe595 1295 iowrite16(n, ioaddr + Wn2_ResetOptions);
1da177e4
LT		 1296 if (vp->drv_flags & WNO_XCVR_PWR) {
1297 EL3WINDOW(0);
62afe595 1298 iowrite16(0x0800, ioaddr);
1da177e4
LT		 1299 }
1300 }
1301
1302 /* Extract our information from the EEPROM data. */
1303 vp->info1 = eeprom[13];
1304 vp->info2 = eeprom[15];
1305 vp->capabilities = eeprom[16];
1306
1307 if (vp->info1 & 0x8000) {
1308 vp->full_duplex = 1;
1309 if (print_info)
39738e16 1310 pr_info("Full duplex capable\n");
1da177e4
LT		 1311 }
1312
1313 {
f71e1309 1314 static const char * const ram_split[] = {"5:3", "3:1", "1:1", "3:5"};
1da177e4
LT		 1315 unsigned int config;
1316 EL3WINDOW(3);
62afe595 1317 vp->available_media = ioread16(ioaddr + Wn3_Options);
1da177e4
LT		 1318 if ((vp->available_media & 0xff) == 0) /* Broken 3c916 */
1319 vp->available_media = 0x40;
62afe595 1320 config = ioread32(ioaddr + Wn3_Config);
1da177e4 1321 if (print_info) {
39738e16
AB		 1322 pr_debug(" Internal config register is %4.4x, transceivers %#x.\n",
1323 config, ioread16(ioaddr + Wn3_Options));
1324 pr_info(" %dK %s-wide RAM %s Rx:Tx split, %s%s interface.\n",
1da177e4
LT		 1325 8 << RAM_SIZE(config),
1326 RAM_WIDTH(config) ? "word" : "byte",
1327 ram_split[RAM_SPLIT(config)],
1328 AUTOSELECT(config) ? "autoselect/" : "",
1329 XCVR(config) > XCVR_ExtMII ? "<invalid transceiver>" :
1330 media_tbl[XCVR(config)].name);
1331 }
1332 vp->default_media = XCVR(config);
1333 if (vp->default_media == XCVR_NWAY)
1334 vp->has_nway = 1;
1335 vp->autoselect = AUTOSELECT(config);
1336 }
1337
1338 if (vp->media_override != 7) {
39738e16 1339 pr_info("%s: Media override to transceiver type %d (%s).\n",
1da177e4
LT		 1340 print_name, vp->media_override,
1341 media_tbl[vp->media_override].name);
1342 dev->if_port = vp->media_override;
1343 } else
1344 dev->if_port = vp->default_media;
1345
1346 if ((vp->available_media & 0x40) || (vci->drv_flags & HAS_NWAY) ||
1347 dev->if_port == XCVR_MII || dev->if_port == XCVR_NWAY) {
1348 int phy, phy_idx = 0;
1349 EL3WINDOW(4);
1350 mii_preamble_required++;
1351 if (vp->drv_flags & EXTRA_PREAMBLE)
1352 mii_preamble_required++;
1353 mdio_sync(ioaddr, 32);
106427e6 1354 mdio_read(dev, 24, MII_BMSR);
1da177e4
LT		 1355 for (phy = 0; phy < 32 && phy_idx < 1; phy++) {
1356 int mii_status, phyx;
1357
1358 /*
1359 * For the 3c905CX we look at index 24 first, because it bogusly
1360 * reports an external PHY at all indices
1361 */
1362 if (phy == 0)
1363 phyx = 24;
1364 else if (phy <= 24)
1365 phyx = phy - 1;
1366 else
1367 phyx = phy;
106427e6 1368 mii_status = mdio_read(dev, phyx, MII_BMSR);
1da177e4
LT		 1369 if (mii_status && mii_status != 0xffff) {
1370 vp->phys[phy_idx++] = phyx;
1371 if (print_info) {
39738e16
AB		 1372 pr_info(" MII transceiver found at address %d, status %4x.\n",
1373 phyx, mii_status);
1da177e4
LT		 1374 }
1375 if ((mii_status & 0x0040) == 0)
1376 mii_preamble_required++;
1377 }
1378 }
1379 mii_preamble_required--;
1380 if (phy_idx == 0) {
39738e16 1381 pr_warning(" ***WARNING*** No MII transceivers found!\n");
1da177e4
LT		 1382 vp->phys[0] = 24;
1383 } else {
106427e6 1384 vp->advertising = mdio_read(dev, vp->phys[0], MII_ADVERTISE);
1da177e4
LT		 1385 if (vp->full_duplex) {
1386 /* Only advertise the FD media types. */
1387 vp->advertising &= ~0x02A0;
1388 mdio_write(dev, vp->phys[0], 4, vp->advertising);
1389 }
1390 }
1391 vp->mii.phy_id = vp->phys[0];
1392 }
1393
1394 if (vp->capabilities & CapBusMaster) {
1395 vp->full_bus_master_tx = 1;
1396 if (print_info) {
39738e16 1397 pr_info(" Enabling bus-master transmits and %s receives.\n",
1da177e4
LT		 1398 (vp->info2 & 1) ? "early" : "whole-frame" );
1399 }
1400 vp->full_bus_master_rx = (vp->info2 & 1) ? 1 : 2;
1401 vp->bus_master = 0; /* AKPM: vortex only */
1402 }
1403
1404 /* The 3c59x-specific entries in the device structure. */
1da177e4 1405 if (vp->full_bus_master_tx) {
48b47a5e 1406 dev->netdev_ops = &boomrang_netdev_ops;
1da177e4 1407 /* Actually, it still should work with iommu. */
32fb5f06
JL		 1408 if (card_idx < MAX_UNITS &&
1409 ((hw_checksums[card_idx] == -1 && (vp->drv_flags & HAS_HWCKSM)) ||
1410 hw_checksums[card_idx] == 1)) {
d311b0d3 1411 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
1da177e4 1412 }
48b47a5e
SH		 1413 } else
1414 dev->netdev_ops = &vortex_netdev_ops;
1da177e4
LT		 1415
1416 if (print_info) {
39738e16 1417 pr_info("%s: scatter/gather %sabled. h/w checksums %sabled\n",
1da177e4
LT		 1418 print_name,
1419 (dev->features & NETIF_F_SG) ? "en":"dis",
1420 (dev->features & NETIF_F_IP_CSUM) ? "en":"dis");
1421 }
1422
1da177e4 1423 dev->ethtool_ops = &vortex_ethtool_ops;
1da177e4 1424 dev->watchdog_timeo = (watchdog * HZ) / 1000;
48b47a5e 1425
1da177e4
LT		 1426 if (pdev) {
1427 vp->pm_state_valid = 1;
1428 pci_save_state(VORTEX_PCI(vp));
1429 acpi_set_WOL(dev);
1430 }
1431 retval = register_netdev(dev);
1432 if (retval == 0)
1433 return 0;
1434
1435free_ring:
1436 pci_free_consistent(pdev,
1437 sizeof(struct boom_rx_desc) * RX_RING_SIZE
1438 + sizeof(struct boom_tx_desc) * TX_RING_SIZE,
1439 vp->rx_ring,
1440 vp->rx_ring_dma);
1441free_region:
1442 if (vp->must_free_region)
62afe595 1443 release_region(dev->base_addr, vci->io_size);
1da177e4 1444 free_netdev(dev);
39738e16 1445 pr_err(PFX "vortex_probe1 fails. Returns %d\n", retval);
1da177e4
LT		 1446out:
1447 return retval;
1448}
1449
1450static void
1451issue_and_wait(struct net_device *dev, int cmd)
1452{
62afe595
JL		 1453 struct vortex_private *vp = netdev_priv(dev);
1454 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 1455 int i;
1456
62afe595 1457 iowrite16(cmd, ioaddr + EL3_CMD);
1da177e4 1458 for (i = 0; i < 2000; i++) {
62afe595 1459 if (!(ioread16(ioaddr + EL3_STATUS) & CmdInProgress))
1da177e4
LT		 1460 return;
1461 }
1462
1463 /* OK, that didn't work. Do it the slow way. One second */
1464 for (i = 0; i < 100000; i++) {
62afe595 1465 if (!(ioread16(ioaddr + EL3_STATUS) & CmdInProgress)) {
1da177e4 1466 if (vortex_debug > 1)
39738e16 1467 pr_info("%s: command 0x%04x took %d usecs\n",
1da177e4
LT		 1468 dev->name, cmd, i * 10);
1469 return;
1470 }
1471 udelay(10);
1472 }
39738e16 1473 pr_err("%s: command 0x%04x did not complete! Status=0x%x\n",
62afe595 1474 dev->name, cmd, ioread16(ioaddr + EL3_STATUS));
1da177e4
LT		 1475}
1476
125d5ce8
SK		 1477static void
1478vortex_set_duplex(struct net_device *dev)
1479{
1480 struct vortex_private *vp = netdev_priv(dev);
1481 void __iomem *ioaddr = vp->ioaddr;
1482
39738e16 1483 pr_info("%s: setting %s-duplex.\n",
125d5ce8
SK		 1484 dev->name, (vp->full_duplex) ? "full" : "half");
1485
1486 EL3WINDOW(3);
1487 /* Set the full-duplex bit. */
1488 iowrite16(((vp->info1 & 0x8000) || vp->full_duplex ? 0x20 : 0) |
1489 (vp->large_frames ? 0x40 : 0) |
1490 ((vp->full_duplex && vp->flow_ctrl && vp->partner_flow_ctrl) ?
1491 0x100 : 0),
1492 ioaddr + Wn3_MAC_Ctrl);
125d5ce8
SK		 1493}
1494
1495static void vortex_check_media(struct net_device *dev, unsigned int init)
1496{
1497 struct vortex_private *vp = netdev_priv(dev);
1498 unsigned int ok_to_print = 0;
1499
1500 if (vortex_debug > 3)
1501 ok_to_print = 1;
1502
1503 if (mii_check_media(&vp->mii, ok_to_print, init)) {
1504 vp->full_duplex = vp->mii.full_duplex;
1505 vortex_set_duplex(dev);
1506 } else if (init) {
1507 vortex_set_duplex(dev);
1508 }
1509}
1510
c8303d10 1511static int
1da177e4
LT		 1512vortex_up(struct net_device *dev)
1513{
1da177e4 1514 struct vortex_private *vp = netdev_priv(dev);
62afe595 1515 void __iomem *ioaddr = vp->ioaddr;
1da177e4 1516 unsigned int config;
0280f9f9 1517 int i, mii_reg1, mii_reg5, err = 0;
1da177e4
LT		 1518
1519 if (VORTEX_PCI(vp)) {
1520 pci_set_power_state(VORTEX_PCI(vp), PCI_D0); /* Go active */
3c8fad18
DR		 1521 if (vp->pm_state_valid)
1522 pci_restore_state(VORTEX_PCI(vp));
c8303d10
MH		 1523 err = pci_enable_device(VORTEX_PCI(vp));
1524 if (err) {
39738e16 1525 pr_warning("%s: Could not enable device\n",
c8303d10
MH		 1526 dev->name);
1527 goto err_out;
1528 }
1da177e4
LT		 1529 }
1530
1531 /* Before initializing select the active media port. */
1532 EL3WINDOW(3);
62afe595 1533 config = ioread32(ioaddr + Wn3_Config);
1da177e4
LT		 1534
1535 if (vp->media_override != 7) {
39738e16 1536 pr_info("%s: Media override to transceiver %d (%s).\n",
1da177e4
LT		 1537 dev->name, vp->media_override,
1538 media_tbl[vp->media_override].name);
1539 dev->if_port = vp->media_override;
1540 } else if (vp->autoselect) {
1541 if (vp->has_nway) {
1542 if (vortex_debug > 1)
39738e16 1543 pr_info("%s: using NWAY device table, not %d\n",
1da177e4
LT		 1544 dev->name, dev->if_port);
1545 dev->if_port = XCVR_NWAY;
1546 } else {
1547 /* Find first available media type, starting with 100baseTx. */
1548 dev->if_port = XCVR_100baseTx;
1549 while (! (vp->available_media & media_tbl[dev->if_port].mask))
1550 dev->if_port = media_tbl[dev->if_port].next;
1551 if (vortex_debug > 1)
39738e16 1552 pr_info("%s: first available media type: %s\n",
1da177e4
LT		 1553 dev->name, media_tbl[dev->if_port].name);
1554 }
1555 } else {
1556 dev->if_port = vp->default_media;
1557 if (vortex_debug > 1)
39738e16 1558 pr_info("%s: using default media %s\n",
1da177e4
LT		 1559 dev->name, media_tbl[dev->if_port].name);
1560 }
1561
1562 init_timer(&vp->timer);
1563 vp->timer.expires = RUN_AT(media_tbl[dev->if_port].wait);
1564 vp->timer.data = (unsigned long)dev;
1565 vp->timer.function = vortex_timer; /* timer handler */
1566 add_timer(&vp->timer);
1567
1568 init_timer(&vp->rx_oom_timer);
1569 vp->rx_oom_timer.data = (unsigned long)dev;
1570 vp->rx_oom_timer.function = rx_oom_timer;
1571
1572 if (vortex_debug > 1)
39738e16 1573 pr_debug("%s: Initial media type %s.\n",
1da177e4
LT		 1574 dev->name, media_tbl[dev->if_port].name);
1575
125d5ce8 1576 vp->full_duplex = vp->mii.force_media;
1da177e4
LT		 1577 config = BFINS(config, dev->if_port, 20, 4);
1578 if (vortex_debug > 6)
39738e16 1579 pr_debug("vortex_up(): writing 0x%x to InternalConfig\n", config);
62afe595 1580 iowrite32(config, ioaddr + Wn3_Config);
1da177e4
LT		 1581
1582 if (dev->if_port == XCVR_MII || dev->if_port == XCVR_NWAY) {
1da177e4 1583 EL3WINDOW(4);
09ce3512
SK		 1584 mii_reg1 = mdio_read(dev, vp->phys[0], MII_BMSR);
1585 mii_reg5 = mdio_read(dev, vp->phys[0], MII_LPA);
1586 vp->partner_flow_ctrl = ((mii_reg5 & 0x0400) != 0);
373492d0 1587 vp->mii.full_duplex = vp->full_duplex;
09ce3512 1588
125d5ce8 1589 vortex_check_media(dev, 1);
1da177e4 1590 }
125d5ce8
SK		 1591 else
1592 vortex_set_duplex(dev);
1da177e4 1593
09ce3512
SK		 1594 issue_and_wait(dev, TxReset);
1595 /*
1596 * Don't reset the PHY - that upsets autonegotiation during DHCP operations.
1597 */
1598 issue_and_wait(dev, RxReset|0x04);
1599
1da177e4 1600
62afe595 1601 iowrite16(SetStatusEnb | 0x00, ioaddr + EL3_CMD);
1da177e4
LT		 1602
1603 if (vortex_debug > 1) {
1604 EL3WINDOW(4);
39738e16 1605 pr_debug("%s: vortex_up() irq %d media status %4.4x.\n",
62afe595 1606 dev->name, dev->irq, ioread16(ioaddr + Wn4_Media));
1da177e4
LT		 1607 }
1608
1609 /* Set the station address and mask in window 2 each time opened. */
1610 EL3WINDOW(2);
1611 for (i = 0; i < 6; i++)
62afe595 1612 iowrite8(dev->dev_addr[i], ioaddr + i);
1da177e4 1613 for (; i < 12; i+=2)
62afe595 1614 iowrite16(0, ioaddr + i);
1da177e4
LT		 1615
1616 if (vp->cb_fn_base) {
62afe595 1617 unsigned short n = ioread16(ioaddr + Wn2_ResetOptions) & ~0x4010;
1da177e4
LT		 1618 if (vp->drv_flags & INVERT_LED_PWR)
1619 n |= 0x10;
1620 if (vp->drv_flags & INVERT_MII_PWR)
1621 n |= 0x4000;
62afe595 1622 iowrite16(n, ioaddr + Wn2_ResetOptions);
1da177e4
LT		 1623 }
1624
1625 if (dev->if_port == XCVR_10base2)
1626 /* Start the thinnet transceiver. We should really wait 50ms...*/
62afe595 1627 iowrite16(StartCoax, ioaddr + EL3_CMD);
1da177e4
LT		 1628 if (dev->if_port != XCVR_NWAY) {
1629 EL3WINDOW(4);
62afe595 1630 iowrite16((ioread16(ioaddr + Wn4_Media) & ~(Media_10TP|Media_SQE)) |
1da177e4
LT		 1631 media_tbl[dev->if_port].media_bits, ioaddr + Wn4_Media);
1632 }
1633
1634 /* Switch to the stats window, and clear all stats by reading. */
62afe595 1635 iowrite16(StatsDisable, ioaddr + EL3_CMD);
1da177e4
LT		 1636 EL3WINDOW(6);
1637 for (i = 0; i < 10; i++)
62afe595
JL		 1638 ioread8(ioaddr + i);
1639 ioread16(ioaddr + 10);
1640 ioread16(ioaddr + 12);
1da177e4
LT		 1641 /* New: On the Vortex we must also clear the BadSSD counter. */
1642 EL3WINDOW(4);
62afe595 1643 ioread8(ioaddr + 12);
1da177e4 1644 /* ..and on the Boomerang we enable the extra statistics bits. */
62afe595 1645 iowrite16(0x0040, ioaddr + Wn4_NetDiag);
1da177e4
LT		 1646
1647 /* Switch to register set 7 for normal use. */
1648 EL3WINDOW(7);
1649
1650 if (vp->full_bus_master_rx) { /* Boomerang bus master. */
1651 vp->cur_rx = vp->dirty_rx = 0;
1652 /* Initialize the RxEarly register as recommended. */
62afe595
JL		 1653 iowrite16(SetRxThreshold + (1536>>2), ioaddr + EL3_CMD);
1654 iowrite32(0x0020, ioaddr + PktStatus);
1655 iowrite32(vp->rx_ring_dma, ioaddr + UpListPtr);
1da177e4
LT		 1656 }
1657 if (vp->full_bus_master_tx) { /* Boomerang bus master Tx. */
1658 vp->cur_tx = vp->dirty_tx = 0;
1659 if (vp->drv_flags & IS_BOOMERANG)
62afe595 1660 iowrite8(PKT_BUF_SZ>>8, ioaddr + TxFreeThreshold); /* Room for a packet. */
1da177e4
LT		 1661 /* Clear the Rx, Tx rings. */
1662 for (i = 0; i < RX_RING_SIZE; i++) /* AKPM: this is done in vortex_open, too */
1663 vp->rx_ring[i].status = 0;
1664 for (i = 0; i < TX_RING_SIZE; i++)
1665 vp->tx_skbuff[i] = NULL;
62afe595 1666 iowrite32(0, ioaddr + DownListPtr);
1da177e4
LT		 1667 }
1668 /* Set receiver mode: presumably accept b-case and phys addr only. */
1669 set_rx_mode(dev);
1670 /* enable 802.1q tagged frames */
1671 set_8021q_mode(dev, 1);
62afe595 1672 iowrite16(StatsEnable, ioaddr + EL3_CMD); /* Turn on statistics. */
1da177e4 1673
62afe595
JL		 1674 iowrite16(RxEnable, ioaddr + EL3_CMD); /* Enable the receiver. */
1675 iowrite16(TxEnable, ioaddr + EL3_CMD); /* Enable transmitter. */
1da177e4
LT		 1676 /* Allow status bits to be seen. */
1677 vp->status_enable = SetStatusEnb | HostError|IntReq|StatsFull|TxComplete|
1678 (vp->full_bus_master_tx ? DownComplete : TxAvailable) |
1679 (vp->full_bus_master_rx ? UpComplete : RxComplete) |
1680 (vp->bus_master ? DMADone : 0);
1681 vp->intr_enable = SetIntrEnb | IntLatch | TxAvailable |
1682 (vp->full_bus_master_rx ? 0 : RxComplete) |
1683 StatsFull | HostError | TxComplete | IntReq
1684 | (vp->bus_master ? DMADone : 0) | UpComplete | DownComplete;
62afe595 1685 iowrite16(vp->status_enable, ioaddr + EL3_CMD);
1da177e4 1686 /* Ack all pending events, and set active indicator mask. */
62afe595 1687 iowrite16(AckIntr | IntLatch | TxAvailable | RxEarly | IntReq,
1da177e4 1688 ioaddr + EL3_CMD);
62afe595 1689 iowrite16(vp->intr_enable, ioaddr + EL3_CMD);
1da177e4 1690 if (vp->cb_fn_base) /* The PCMCIA people are idiots. */
62afe595 1691 iowrite32(0x8000, vp->cb_fn_base + 4);
1da177e4 1692 netif_start_queue (dev);
c8303d10
MH		 1693err_out:
1694 return err;
1da177e4
LT		 1695}
1696
1697static int
1698vortex_open(struct net_device *dev)
1699{
1700 struct vortex_private *vp = netdev_priv(dev);
1701 int i;
1702 int retval;
1703
1704 /* Use the now-standard shared IRQ implementation. */
1705 if ((retval = request_irq(dev->irq, vp->full_bus_master_rx ?
1fb9df5d 1706 &boomerang_interrupt : &vortex_interrupt, IRQF_SHARED, dev->name, dev))) {
39738e16 1707 pr_err("%s: Could not reserve IRQ %d\n", dev->name, dev->irq);
c8303d10 1708 goto err;
1da177e4
LT		 1709 }
1710
1711 if (vp->full_bus_master_rx) { /* Boomerang bus master. */
1712 if (vortex_debug > 2)
39738e16 1713 pr_debug("%s: Filling in the Rx ring.\n", dev->name);
1da177e4
LT		 1714 for (i = 0; i < RX_RING_SIZE; i++) {
1715 struct sk_buff *skb;
1716 vp->rx_ring[i].next = cpu_to_le32(vp->rx_ring_dma + sizeof(struct boom_rx_desc) * (i+1));
1717 vp->rx_ring[i].status = 0; /* Clear complete bit. */
1718 vp->rx_ring[i].length = cpu_to_le32(PKT_BUF_SZ | LAST_FRAG);
9a5d3414
SH		 1719
1720 skb = __netdev_alloc_skb(dev, PKT_BUF_SZ + NET_IP_ALIGN,
1721 GFP_KERNEL);
1da177e4
LT		 1722 vp->rx_skbuff[i] = skb;
1723 if (skb == NULL)
1724 break; /* Bad news! */
9a5d3414
SH		 1725
1726 skb_reserve(skb, NET_IP_ALIGN); /* Align IP on 16 byte boundaries */
689be439 1727 vp->rx_ring[i].addr = cpu_to_le32(pci_map_single(VORTEX_PCI(vp), skb->data, PKT_BUF_SZ, PCI_DMA_FROMDEVICE));
1da177e4
LT		 1728 }
1729 if (i != RX_RING_SIZE) {
1730 int j;
39738e16 1731 pr_emerg("%s: no memory for rx ring\n", dev->name);
1da177e4
LT		 1732 for (j = 0; j < i; j++) {
1733 if (vp->rx_skbuff[j]) {
1734 dev_kfree_skb(vp->rx_skbuff[j]);
1735 vp->rx_skbuff[j] = NULL;
1736 }
1737 }
1738 retval = -ENOMEM;
c8303d10 1739 goto err_free_irq;
1da177e4
LT		 1740 }
1741 /* Wrap the ring. */
1742 vp->rx_ring[i-1].next = cpu_to_le32(vp->rx_ring_dma);
1743 }
1744
c8303d10
MH		 1745 retval = vortex_up(dev);
1746 if (!retval)
1747 goto out;
1da177e4 1748
c8303d10 1749err_free_irq:
1da177e4 1750 free_irq(dev->irq, dev);
c8303d10 1751err:
1da177e4 1752 if (vortex_debug > 1)
39738e16 1753 pr_err("%s: vortex_open() fails: returning %d\n", dev->name, retval);
c8303d10 1754out:
1da177e4
LT		 1755 return retval;
1756}
1757
1758static void
1759vortex_timer(unsigned long data)
1760{
1761 struct net_device *dev = (struct net_device *)data;
1762 struct vortex_private *vp = netdev_priv(dev);
62afe595 1763 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 1764 int next_tick = 60*HZ;
1765 int ok = 0;
125d5ce8 1766 int media_status, old_window;
1da177e4
LT		 1767
1768 if (vortex_debug > 2) {
39738e16 1769 pr_debug("%s: Media selection timer tick happened, %s.\n",
1da177e4 1770 dev->name, media_tbl[dev->if_port].name);
39738e16 1771 pr_debug("dev->watchdog_timeo=%d\n", dev->watchdog_timeo);
1da177e4
LT		 1772 }
1773
0a9da4bd 1774 disable_irq_lockdep(dev->irq);
62afe595 1775 old_window = ioread16(ioaddr + EL3_CMD) >> 13;
1da177e4 1776 EL3WINDOW(4);
62afe595 1777 media_status = ioread16(ioaddr + Wn4_Media);
1da177e4
LT		 1778 switch (dev->if_port) {
1779 case XCVR_10baseT: case XCVR_100baseTx: case XCVR_100baseFx:
1780 if (media_status & Media_LnkBeat) {
1781 netif_carrier_on(dev);
1782 ok = 1;
1783 if (vortex_debug > 1)
39738e16 1784 pr_debug("%s: Media %s has link beat, %x.\n",
1da177e4
LT		 1785 dev->name, media_tbl[dev->if_port].name, media_status);
1786 } else {
1787 netif_carrier_off(dev);
1788 if (vortex_debug > 1) {
39738e16 1789 pr_debug("%s: Media %s has no link beat, %x.\n",
1da177e4
LT		 1790 dev->name, media_tbl[dev->if_port].name, media_status);
1791 }
1792 }
1793 break;
1794 case XCVR_MII: case XCVR_NWAY:
1795 {
1da177e4 1796 ok = 1;
c5643cab
IM		 1797 /* Interrupts are already disabled */
1798 spin_lock(&vp->lock);
125d5ce8 1799 vortex_check_media(dev, 0);
c5643cab 1800 spin_unlock(&vp->lock);
1da177e4
LT		 1801 }
1802 break;
1803 default: /* Other media types handled by Tx timeouts. */
1804 if (vortex_debug > 1)
39738e16 1805 pr_debug("%s: Media %s has no indication, %x.\n",
1da177e4
LT		 1806 dev->name, media_tbl[dev->if_port].name, media_status);
1807 ok = 1;
1808 }
b4ff6450
SK		 1809
1810 if (!netif_carrier_ok(dev))
1811 next_tick = 5*HZ;
1812
e94d10eb
SK		 1813 if (vp->medialock)
1814 goto leave_media_alone;
1815
a880c4cd 1816 if (!ok) {
1da177e4
LT		 1817 unsigned int config;
1818
1819 do {
1820 dev->if_port = media_tbl[dev->if_port].next;
1821 } while ( ! (vp->available_media & media_tbl[dev->if_port].mask));
1822 if (dev->if_port == XCVR_Default) { /* Go back to default. */
1823 dev->if_port = vp->default_media;
1824 if (vortex_debug > 1)
39738e16 1825 pr_debug("%s: Media selection failing, using default %s port.\n",
1da177e4
LT		 1826 dev->name, media_tbl[dev->if_port].name);
1827 } else {
1828 if (vortex_debug > 1)
39738e16 1829 pr_debug("%s: Media selection failed, now trying %s port.\n",
1da177e4
LT		 1830 dev->name, media_tbl[dev->if_port].name);
1831 next_tick = media_tbl[dev->if_port].wait;
1832 }
62afe595 1833 iowrite16((media_status & ~(Media_10TP|Media_SQE)) |
1da177e4
LT		 1834 media_tbl[dev->if_port].media_bits, ioaddr + Wn4_Media);
1835
1836 EL3WINDOW(3);
62afe595 1837 config = ioread32(ioaddr + Wn3_Config);
1da177e4 1838 config = BFINS(config, dev->if_port, 20, 4);
62afe595 1839 iowrite32(config, ioaddr + Wn3_Config);
1da177e4 1840
62afe595 1841 iowrite16(dev->if_port == XCVR_10base2 ? StartCoax : StopCoax,
1da177e4
LT		 1842 ioaddr + EL3_CMD);
1843 if (vortex_debug > 1)
39738e16 1844 pr_debug("wrote 0x%08x to Wn3_Config\n", config);
1da177e4
LT		 1845 /* AKPM: FIXME: Should reset Rx & Tx here. P60 of 3c90xc.pdf */
1846 }
1da177e4
LT		 1847
1848leave_media_alone:
1849 if (vortex_debug > 2)
39738e16 1850 pr_debug("%s: Media selection timer finished, %s.\n",
1da177e4
LT		 1851 dev->name, media_tbl[dev->if_port].name);
1852
e94d10eb 1853 EL3WINDOW(old_window);
0a9da4bd 1854 enable_irq_lockdep(dev->irq);
1da177e4
LT		 1855 mod_timer(&vp->timer, RUN_AT(next_tick));
1856 if (vp->deferred)
62afe595 1857 iowrite16(FakeIntr, ioaddr + EL3_CMD);
1da177e4
LT		 1858 return;
1859}
1860
1861static void vortex_tx_timeout(struct net_device *dev)
1862{
1863 struct vortex_private *vp = netdev_priv(dev);
62afe595 1864 void __iomem *ioaddr = vp->ioaddr;
1da177e4 1865
39738e16 1866 pr_err("%s: transmit timed out, tx_status %2.2x status %4.4x.\n",
62afe595
JL		 1867 dev->name, ioread8(ioaddr + TxStatus),
1868 ioread16(ioaddr + EL3_STATUS));
1da177e4 1869 EL3WINDOW(4);
39738e16 1870 pr_err(" diagnostics: net %04x media %04x dma %08x fifo %04x\n",
62afe595
JL		 1871 ioread16(ioaddr + Wn4_NetDiag),
1872 ioread16(ioaddr + Wn4_Media),
1873 ioread32(ioaddr + PktStatus),
1874 ioread16(ioaddr + Wn4_FIFODiag));
1da177e4 1875 /* Slight code bloat to be user friendly. */
62afe595 1876 if ((ioread8(ioaddr + TxStatus) & 0x88) == 0x88)
39738e16 1877 pr_err("%s: Transmitter encountered 16 collisions --"
1da177e4 1878 " network cable problem?\n", dev->name);
62afe595 1879 if (ioread16(ioaddr + EL3_STATUS) & IntLatch) {
39738e16 1880 pr_err("%s: Interrupt posted but not delivered --"
1da177e4
LT		 1881 " IRQ blocked by another device?\n", dev->name);
1882 /* Bad idea here.. but we might as well handle a few events. */
1883 {
1884 /*
1885 * Block interrupts because vortex_interrupt does a bare spin_lock()
1886 */
1887 unsigned long flags;
1888 local_irq_save(flags);
1889 if (vp->full_bus_master_tx)
7d12e780 1890 boomerang_interrupt(dev->irq, dev);
1da177e4 1891 else
7d12e780 1892 vortex_interrupt(dev->irq, dev);
1da177e4
LT		 1893 local_irq_restore(flags);
1894 }
1895 }
1896
1897 if (vortex_debug > 0)
1898 dump_tx_ring(dev);
1899
1900 issue_and_wait(dev, TxReset);
1901
1daad055 1902 dev->stats.tx_errors++;
1da177e4 1903 if (vp->full_bus_master_tx) {
39738e16 1904 pr_debug("%s: Resetting the Tx ring pointer.\n", dev->name);
62afe595
JL		 1905 if (vp->cur_tx - vp->dirty_tx > 0 && ioread32(ioaddr + DownListPtr) == 0)
1906 iowrite32(vp->tx_ring_dma + (vp->dirty_tx % TX_RING_SIZE) * sizeof(struct boom_tx_desc),
1da177e4
LT		 1907 ioaddr + DownListPtr);
1908 if (vp->cur_tx - vp->dirty_tx < TX_RING_SIZE)
1909 netif_wake_queue (dev);
1910 if (vp->drv_flags & IS_BOOMERANG)
62afe595
JL		 1911 iowrite8(PKT_BUF_SZ>>8, ioaddr + TxFreeThreshold);
1912 iowrite16(DownUnstall, ioaddr + EL3_CMD);
1da177e4 1913 } else {
1daad055 1914 dev->stats.tx_dropped++;
1da177e4
LT		 1915 netif_wake_queue(dev);
1916 }
6aa20a22 1917
1da177e4 1918 /* Issue Tx Enable */
62afe595 1919 iowrite16(TxEnable, ioaddr + EL3_CMD);
1ae5dc34 1920 dev->trans_start = jiffies; /* prevent tx timeout */
6aa20a22 1921
1da177e4
LT		 1922 /* Switch to register set 7 for normal use. */
1923 EL3WINDOW(7);
1924}
1925
1926/*
1927 * Handle uncommon interrupt sources. This is a separate routine to minimize
1928 * the cache impact.
1929 */
1930static void
1931vortex_error(struct net_device *dev, int status)
1932{
1933 struct vortex_private *vp = netdev_priv(dev);
62afe595 1934 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 1935 int do_tx_reset = 0, reset_mask = 0;
1936 unsigned char tx_status = 0;
1937
1938 if (vortex_debug > 2) {
39738e16 1939 pr_err("%s: vortex_error(), status=0x%x\n", dev->name, status);
1da177e4
LT		 1940 }
1941
1942 if (status & TxComplete) { /* Really "TxError" for us. */
62afe595 1943 tx_status = ioread8(ioaddr + TxStatus);
1da177e4 1944 /* Presumably a tx-timeout. We must merely re-enable. */
8e95a202
JP		 1945 if (vortex_debug > 2 ||
1946 (tx_status != 0x88 && vortex_debug > 0)) {
39738e16 1947 pr_err("%s: Transmit error, Tx status register %2.2x.\n",
1da177e4
LT		 1948 dev->name, tx_status);
1949 if (tx_status == 0x82) {
39738e16 1950 pr_err("Probably a duplex mismatch. See "
1da177e4
LT		 1951 "Documentation/networking/vortex.txt\n");
1952 }
1953 dump_tx_ring(dev);
1954 }
1daad055
PZ		 1955 if (tx_status & 0x14) dev->stats.tx_fifo_errors++;
1956 if (tx_status & 0x38) dev->stats.tx_aborted_errors++;
0000754c 1957 if (tx_status & 0x08) vp->xstats.tx_max_collisions++;
62afe595 1958 iowrite8(0, ioaddr + TxStatus);
1da177e4
LT		 1959 if (tx_status & 0x30) { /* txJabber or txUnderrun */
1960 do_tx_reset = 1;
0000754c
AM		 1961 } else if ((tx_status & 0x08) && (vp->drv_flags & MAX_COLLISION_RESET)) { /* maxCollisions */
1962 do_tx_reset = 1;
1963 reset_mask = 0x0108; /* Reset interface logic, but not download logic */
1964 } else { /* Merely re-enable the transmitter. */
62afe595 1965 iowrite16(TxEnable, ioaddr + EL3_CMD);
1da177e4
LT		 1966 }
1967 }
1968
1969 if (status & RxEarly) { /* Rx early is unused. */
1970 vortex_rx(dev);
62afe595 1971 iowrite16(AckIntr | RxEarly, ioaddr + EL3_CMD);
1da177e4
LT		 1972 }
1973 if (status & StatsFull) { /* Empty statistics. */
1974 static int DoneDidThat;
1975 if (vortex_debug > 4)
39738e16 1976 pr_debug("%s: Updating stats.\n", dev->name);
1da177e4
LT		 1977 update_stats(ioaddr, dev);
1978 /* HACK: Disable statistics as an interrupt source. */
1979 /* This occurs when we have the wrong media type! */
1980 if (DoneDidThat == 0 &&
62afe595 1981 ioread16(ioaddr + EL3_STATUS) & StatsFull) {
39738e16 1982 pr_warning("%s: Updating statistics failed, disabling "
1da177e4
LT		 1983 "stats as an interrupt source.\n", dev->name);
1984 EL3WINDOW(5);
62afe595 1985 iowrite16(SetIntrEnb | (ioread16(ioaddr + 10) & ~StatsFull), ioaddr + EL3_CMD);
1da177e4
LT		 1986 vp->intr_enable &= ~StatsFull;
1987 EL3WINDOW(7);
1988 DoneDidThat++;
1989 }
1990 }
1991 if (status & IntReq) { /* Restore all interrupt sources. */
62afe595
JL		 1992 iowrite16(vp->status_enable, ioaddr + EL3_CMD);
1993 iowrite16(vp->intr_enable, ioaddr + EL3_CMD);
1da177e4
LT		 1994 }
1995 if (status & HostError) {
1996 u16 fifo_diag;
1997 EL3WINDOW(4);
62afe595 1998 fifo_diag = ioread16(ioaddr + Wn4_FIFODiag);
39738e16 1999 pr_err("%s: Host error, FIFO diagnostic register %4.4x.\n",
1da177e4
LT		 2000 dev->name, fifo_diag);
2001 /* Adapter failure requires Tx/Rx reset and reinit. */
2002 if (vp->full_bus_master_tx) {
62afe595 2003 int bus_status = ioread32(ioaddr + PktStatus);
1da177e4
LT		 2004 /* 0x80000000 PCI master abort. */
2005 /* 0x40000000 PCI target abort. */
2006 if (vortex_debug)
39738e16 2007 pr_err("%s: PCI bus error, bus status %8.8x\n", dev->name, bus_status);
1da177e4
LT		 2008
2009 /* In this case, blow the card away */
2010 /* Must not enter D3 or we can't legally issue the reset! */
2011 vortex_down(dev, 0);
2012 issue_and_wait(dev, TotalReset | 0xff);
2013 vortex_up(dev); /* AKPM: bug. vortex_up() assumes that the rx ring is full. It may not be. */
2014 } else if (fifo_diag & 0x0400)
2015 do_tx_reset = 1;
2016 if (fifo_diag & 0x3000) {
2017 /* Reset Rx fifo and upload logic */
2018 issue_and_wait(dev, RxReset|0x07);
2019 /* Set the Rx filter to the current state. */
2020 set_rx_mode(dev);
2021 /* enable 802.1q VLAN tagged frames */
2022 set_8021q_mode(dev, 1);
62afe595
JL		 2023 iowrite16(RxEnable, ioaddr + EL3_CMD); /* Re-enable the receiver. */
2024 iowrite16(AckIntr | HostError, ioaddr + EL3_CMD);
1da177e4
LT		 2025 }
2026 }
2027
2028 if (do_tx_reset) {
2029 issue_and_wait(dev, TxReset|reset_mask);
62afe595 2030 iowrite16(TxEnable, ioaddr + EL3_CMD);
1da177e4
LT		 2031 if (!vp->full_bus_master_tx)
2032 netif_wake_queue(dev);
2033 }
2034}
2035
27a1de95 2036static netdev_tx_t
1da177e4
LT		 2037vortex_start_xmit(struct sk_buff *skb, struct net_device *dev)
2038{
2039 struct vortex_private *vp = netdev_priv(dev);
62afe595 2040 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 2041
2042 /* Put out the doubleword header... */
62afe595 2043 iowrite32(skb->len, ioaddr + TX_FIFO);
1da177e4
LT		 2044 if (vp->bus_master) {
2045 /* Set the bus-master controller to transfer the packet. */
2046 int len = (skb->len + 3) & ~3;
a880c4cd 2047 iowrite32(vp->tx_skb_dma = pci_map_single(VORTEX_PCI(vp), skb->data, len, PCI_DMA_TODEVICE),
1da177e4 2048 ioaddr + Wn7_MasterAddr);
62afe595 2049 iowrite16(len, ioaddr + Wn7_MasterLen);
1da177e4 2050 vp->tx_skb = skb;
62afe595 2051 iowrite16(StartDMADown, ioaddr + EL3_CMD);
1da177e4
LT		 2052 /* netif_wake_queue() will be called at the DMADone interrupt. */
2053 } else {
2054 /* ... and the packet rounded to a doubleword. */
62afe595 2055 iowrite32_rep(ioaddr + TX_FIFO, skb->data, (skb->len + 3) >> 2);
1da177e4 2056 dev_kfree_skb (skb);
62afe595 2057 if (ioread16(ioaddr + TxFree) > 1536) {
1da177e4
LT		 2058 netif_start_queue (dev); /* AKPM: redundant? */
2059 } else {
2060 /* Interrupt us when the FIFO has room for max-sized packet. */
2061 netif_stop_queue(dev);
62afe595 2062 iowrite16(SetTxThreshold + (1536>>2), ioaddr + EL3_CMD);
1da177e4
LT		 2063 }
2064 }
2065
1da177e4
LT		 2066
2067 /* Clear the Tx status stack. */
2068 {
2069 int tx_status;
2070 int i = 32;
2071
62afe595 2072 while (--i > 0 && (tx_status = ioread8(ioaddr + TxStatus)) > 0) {
1da177e4
LT		 2073 if (tx_status & 0x3C) { /* A Tx-disabling error occurred. */
2074 if (vortex_debug > 2)
39738e16 2075 pr_debug("%s: Tx error, status %2.2x.\n",
1da177e4 2076 dev->name, tx_status);
1daad055
PZ		 2077 if (tx_status & 0x04) dev->stats.tx_fifo_errors++;
2078 if (tx_status & 0x38) dev->stats.tx_aborted_errors++;
1da177e4
LT		 2079 if (tx_status & 0x30) {
2080 issue_and_wait(dev, TxReset);
2081 }
62afe595 2082 iowrite16(TxEnable, ioaddr + EL3_CMD);
1da177e4 2083 }
62afe595 2084 iowrite8(0x00, ioaddr + TxStatus); /* Pop the status stack. */
1da177e4
LT		 2085 }
2086 }
6ed10654 2087 return NETDEV_TX_OK;
1da177e4
LT		 2088}
2089
27a1de95 2090static netdev_tx_t
1da177e4
LT		 2091boomerang_start_xmit(struct sk_buff *skb, struct net_device *dev)
2092{
2093 struct vortex_private *vp = netdev_priv(dev);
62afe595 2094 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 2095 /* Calculate the next Tx descriptor entry. */
2096 int entry = vp->cur_tx % TX_RING_SIZE;
2097 struct boom_tx_desc *prev_entry = &vp->tx_ring[(vp->cur_tx-1) % TX_RING_SIZE];
2098 unsigned long flags;
2099
2100 if (vortex_debug > 6) {
39738e16
AB		 2101 pr_debug("boomerang_start_xmit()\n");
2102 pr_debug("%s: Trying to send a packet, Tx index %d.\n",
0f667ff5 2103 dev->name, vp->cur_tx);
1da177e4
LT		 2104 }
2105
2106 if (vp->cur_tx - vp->dirty_tx >= TX_RING_SIZE) {
2107 if (vortex_debug > 0)
39738e16 2108 pr_warning("%s: BUG! Tx Ring full, refusing to send buffer.\n",
1da177e4
LT		 2109 dev->name);
2110 netif_stop_queue(dev);
5b548140 2111 return NETDEV_TX_BUSY;
1da177e4
LT		 2112 }
2113
2114 vp->tx_skbuff[entry] = skb;
2115
2116 vp->tx_ring[entry].next = 0;
2117#if DO_ZEROCOPY
84fa7933 2118 if (skb->ip_summed != CHECKSUM_PARTIAL)
1da177e4
LT		 2119 vp->tx_ring[entry].status = cpu_to_le32(skb->len | TxIntrUploaded);
2120 else
2121 vp->tx_ring[entry].status = cpu_to_le32(skb->len | TxIntrUploaded | AddTCPChksum | AddUDPChksum);
2122
2123 if (!skb_shinfo(skb)->nr_frags) {
2124 vp->tx_ring[entry].frag[0].addr = cpu_to_le32(pci_map_single(VORTEX_PCI(vp), skb->data,
2125 skb->len, PCI_DMA_TODEVICE));
2126 vp->tx_ring[entry].frag[0].length = cpu_to_le32(skb->len | LAST_FRAG);
2127 } else {
2128 int i;
2129
2130 vp->tx_ring[entry].frag[0].addr = cpu_to_le32(pci_map_single(VORTEX_PCI(vp), skb->data,
e743d313
ED		 2131 skb_headlen(skb), PCI_DMA_TODEVICE));
2132 vp->tx_ring[entry].frag[0].length = cpu_to_le32(skb_headlen(skb));
1da177e4
LT		 2133
2134 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
2135 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2136
2137 vp->tx_ring[entry].frag[i+1].addr =
2138 cpu_to_le32(pci_map_single(VORTEX_PCI(vp),
2139 (void*)page_address(frag->page) + frag->page_offset,
2140 frag->size, PCI_DMA_TODEVICE));
2141
2142 if (i == skb_shinfo(skb)->nr_frags-1)
2143 vp->tx_ring[entry].frag[i+1].length = cpu_to_le32(frag->size|LAST_FRAG);
2144 else
2145 vp->tx_ring[entry].frag[i+1].length = cpu_to_le32(frag->size);
2146 }
2147 }
2148#else
2149 vp->tx_ring[entry].addr = cpu_to_le32(pci_map_single(VORTEX_PCI(vp), skb->data, skb->len, PCI_DMA_TODEVICE));
2150 vp->tx_ring[entry].length = cpu_to_le32(skb->len | LAST_FRAG);
2151 vp->tx_ring[entry].status = cpu_to_le32(skb->len | TxIntrUploaded);
2152#endif
2153
2154 spin_lock_irqsave(&vp->lock, flags);
2155 /* Wait for the stall to complete. */
2156 issue_and_wait(dev, DownStall);
2157 prev_entry->next = cpu_to_le32(vp->tx_ring_dma + entry * sizeof(struct boom_tx_desc));
62afe595
JL		 2158 if (ioread32(ioaddr + DownListPtr) == 0) {
2159 iowrite32(vp->tx_ring_dma + entry * sizeof(struct boom_tx_desc), ioaddr + DownListPtr);
1da177e4
LT		 2160 vp->queued_packet++;
2161 }
2162
2163 vp->cur_tx++;
2164 if (vp->cur_tx - vp->dirty_tx > TX_RING_SIZE - 1) {
2165 netif_stop_queue (dev);
2166 } else { /* Clear previous interrupt enable. */
2167#if defined(tx_interrupt_mitigation)
2168 /* Dubious. If in boomeang_interrupt "faster" cyclone ifdef
2169 * were selected, this would corrupt DN_COMPLETE. No?
2170 */
2171 prev_entry->status &= cpu_to_le32(~TxIntrUploaded);
2172#endif
2173 }
62afe595 2174 iowrite16(DownUnstall, ioaddr + EL3_CMD);
1da177e4 2175 spin_unlock_irqrestore(&vp->lock, flags);
6ed10654 2176 return NETDEV_TX_OK;
1da177e4
LT		 2177}
2178
2179/* The interrupt handler does all of the Rx thread work and cleans up
2180 after the Tx thread. */
2181
2182/*
2183 * This is the ISR for the vortex series chips.
2184 * full_bus_master_tx == 0 && full_bus_master_rx == 0
2185 */
2186
2187static irqreturn_t
7d12e780 2188vortex_interrupt(int irq, void *dev_id)
1da177e4
LT		 2189{
2190 struct net_device *dev = dev_id;
2191 struct vortex_private *vp = netdev_priv(dev);
62afe595 2192 void __iomem *ioaddr;
1da177e4
LT		 2193 int status;
2194 int work_done = max_interrupt_work;
2195 int handled = 0;
2196
62afe595 2197 ioaddr = vp->ioaddr;
1da177e4
LT		 2198 spin_lock(&vp->lock);
2199
62afe595 2200 status = ioread16(ioaddr + EL3_STATUS);
1da177e4
LT		 2201
2202 if (vortex_debug > 6)
39738e16 2203 pr_debug("vortex_interrupt(). status=0x%4x\n", status);
1da177e4
LT		 2204
2205 if ((status & IntLatch) == 0)
2206 goto handler_exit; /* No interrupt: shared IRQs cause this */
2207 handled = 1;
2208
2209 if (status & IntReq) {
2210 status |= vp->deferred;
2211 vp->deferred = 0;
2212 }
2213
2214 if (status == 0xffff) /* h/w no longer present (hotplug)? */
2215 goto handler_exit;
2216
2217 if (vortex_debug > 4)
39738e16 2218 pr_debug("%s: interrupt, status %4.4x, latency %d ticks.\n",
62afe595 2219 dev->name, status, ioread8(ioaddr + Timer));
1da177e4
LT		 2220
2221 do {
2222 if (vortex_debug > 5)
39738e16 2223 pr_debug("%s: In interrupt loop, status %4.4x.\n",
1da177e4
LT		 2224 dev->name, status);
2225 if (status & RxComplete)
2226 vortex_rx(dev);
2227
2228 if (status & TxAvailable) {
2229 if (vortex_debug > 5)
39738e16 2230 pr_debug(" TX room bit was handled.\n");
1da177e4 2231 /* There's room in the FIFO for a full-sized packet. */
62afe595 2232 iowrite16(AckIntr | TxAvailable, ioaddr + EL3_CMD);
1da177e4
LT		 2233 netif_wake_queue (dev);
2234 }
2235
2236 if (status & DMADone) {
62afe595
JL		 2237 if (ioread16(ioaddr + Wn7_MasterStatus) & 0x1000) {
2238 iowrite16(0x1000, ioaddr + Wn7_MasterStatus); /* Ack the event. */
1da177e4
LT		 2239 pci_unmap_single(VORTEX_PCI(vp), vp->tx_skb_dma, (vp->tx_skb->len + 3) & ~3, PCI_DMA_TODEVICE);
2240 dev_kfree_skb_irq(vp->tx_skb); /* Release the transferred buffer */
62afe595 2241 if (ioread16(ioaddr + TxFree) > 1536) {
1da177e4
LT		 2242 /*
2243 * AKPM: FIXME: I don't think we need this. If the queue was stopped due to
2244 * insufficient FIFO room, the TxAvailable test will succeed and call
2245 * netif_wake_queue()
2246 */
2247 netif_wake_queue(dev);
2248 } else { /* Interrupt when FIFO has room for max-sized packet. */
62afe595 2249 iowrite16(SetTxThreshold + (1536>>2), ioaddr + EL3_CMD);
1da177e4
LT		 2250 netif_stop_queue(dev);
2251 }
2252 }
2253 }
2254 /* Check for all uncommon interrupts at once. */
2255 if (status & (HostError | RxEarly | StatsFull | TxComplete | IntReq)) {
2256 if (status == 0xffff)
2257 break;
2258 vortex_error(dev, status);
2259 }
2260
2261 if (--work_done < 0) {
39738e16
AB		 2262 pr_warning("%s: Too much work in interrupt, status %4.4x.\n",
2263 dev->name, status);
1da177e4
LT		 2264 /* Disable all pending interrupts. */
2265 do {
2266 vp->deferred |= status;
62afe595 2267 iowrite16(SetStatusEnb | (~vp->deferred & vp->status_enable),
1da177e4 2268 ioaddr + EL3_CMD);
62afe595
JL		 2269 iowrite16(AckIntr | (vp->deferred & 0x7ff), ioaddr + EL3_CMD);
2270 } while ((status = ioread16(ioaddr + EL3_CMD)) & IntLatch);
1da177e4
LT		 2271 /* The timer will reenable interrupts. */
2272 mod_timer(&vp->timer, jiffies + 1*HZ);
2273 break;
2274 }
2275 /* Acknowledge the IRQ. */
62afe595
JL		 2276 iowrite16(AckIntr | IntReq | IntLatch, ioaddr + EL3_CMD);
2277 } while ((status = ioread16(ioaddr + EL3_STATUS)) & (IntLatch | RxComplete));
1da177e4
LT		 2278
2279 if (vortex_debug > 4)
39738e16 2280 pr_debug("%s: exiting interrupt, status %4.4x.\n",
1da177e4
LT		 2281 dev->name, status);
2282handler_exit:
2283 spin_unlock(&vp->lock);
2284 return IRQ_RETVAL(handled);
2285}
2286
2287/*
2288 * This is the ISR for the boomerang series chips.
2289 * full_bus_master_tx == 1 && full_bus_master_rx == 1
2290 */
2291
2292static irqreturn_t
7d12e780 2293boomerang_interrupt(int irq, void *dev_id)
1da177e4
LT		 2294{
2295 struct net_device *dev = dev_id;
2296 struct vortex_private *vp = netdev_priv(dev);
62afe595 2297 void __iomem *ioaddr;
1da177e4
LT		 2298 int status;
2299 int work_done = max_interrupt_work;
2300
62afe595 2301 ioaddr = vp->ioaddr;
1da177e4
LT		 2302
2303 /*
2304 * It seems dopey to put the spinlock this early, but we could race against vortex_tx_timeout
2305 * and boomerang_start_xmit
2306 */
2307 spin_lock(&vp->lock);
2308
62afe595 2309 status = ioread16(ioaddr + EL3_STATUS);
1da177e4
LT		 2310
2311 if (vortex_debug > 6)
39738e16 2312 pr_debug("boomerang_interrupt. status=0x%4x\n", status);
1da177e4
LT		 2313
2314 if ((status & IntLatch) == 0)
2315 goto handler_exit; /* No interrupt: shared IRQs can cause this */
2316
2317 if (status == 0xffff) { /* h/w no longer present (hotplug)? */
2318 if (vortex_debug > 1)
39738e16 2319 pr_debug("boomerang_interrupt(1): status = 0xffff\n");
1da177e4
LT		 2320 goto handler_exit;
2321 }
2322
2323 if (status & IntReq) {
2324 status |= vp->deferred;
2325 vp->deferred = 0;
2326 }
2327
2328 if (vortex_debug > 4)
39738e16 2329 pr_debug("%s: interrupt, status %4.4x, latency %d ticks.\n",
62afe595 2330 dev->name, status, ioread8(ioaddr + Timer));
1da177e4
LT		 2331 do {
2332 if (vortex_debug > 5)
39738e16 2333 pr_debug("%s: In interrupt loop, status %4.4x.\n",
1da177e4
LT		 2334 dev->name, status);
2335 if (status & UpComplete) {
62afe595 2336 iowrite16(AckIntr | UpComplete, ioaddr + EL3_CMD);
1da177e4 2337 if (vortex_debug > 5)
39738e16 2338 pr_debug("boomerang_interrupt->boomerang_rx\n");
1da177e4
LT		 2339 boomerang_rx(dev);
2340 }
2341
2342 if (status & DownComplete) {
2343 unsigned int dirty_tx = vp->dirty_tx;
2344
62afe595 2345 iowrite16(AckIntr | DownComplete, ioaddr + EL3_CMD);
1da177e4
LT		 2346 while (vp->cur_tx - dirty_tx > 0) {
2347 int entry = dirty_tx % TX_RING_SIZE;
2348#if 1 /* AKPM: the latter is faster, but cyclone-only */
62afe595 2349 if (ioread32(ioaddr + DownListPtr) ==
1da177e4
LT		 2350 vp->tx_ring_dma + entry * sizeof(struct boom_tx_desc))
2351 break; /* It still hasn't been processed. */
2352#else
2353 if ((vp->tx_ring[entry].status & DN_COMPLETE) == 0)
2354 break; /* It still hasn't been processed. */
2355#endif
6aa20a22 2356
1da177e4
LT		 2357 if (vp->tx_skbuff[entry]) {
2358 struct sk_buff *skb = vp->tx_skbuff[entry];
6aa20a22 2359#if DO_ZEROCOPY
1da177e4
LT		 2360 int i;
2361 for (i=0; i<=skb_shinfo(skb)->nr_frags; i++)
2362 pci_unmap_single(VORTEX_PCI(vp),
2363 le32_to_cpu(vp->tx_ring[entry].frag[i].addr),
2364 le32_to_cpu(vp->tx_ring[entry].frag[i].length)&0xFFF,
2365 PCI_DMA_TODEVICE);
2366#else
2367 pci_unmap_single(VORTEX_PCI(vp),
2368 le32_to_cpu(vp->tx_ring[entry].addr), skb->len, PCI_DMA_TODEVICE);
2369#endif
2370 dev_kfree_skb_irq(skb);
2371 vp->tx_skbuff[entry] = NULL;
2372 } else {
39738e16 2373 pr_debug("boomerang_interrupt: no skb!\n");
1da177e4 2374 }
1daad055 2375 /* dev->stats.tx_packets++; Counted below. */
1da177e4
LT		 2376 dirty_tx++;
2377 }
2378 vp->dirty_tx = dirty_tx;
2379 if (vp->cur_tx - dirty_tx <= TX_RING_SIZE - 1) {
2380 if (vortex_debug > 6)
39738e16 2381 pr_debug("boomerang_interrupt: wake queue\n");
1da177e4
LT		 2382 netif_wake_queue (dev);
2383 }
2384 }
2385
2386 /* Check for all uncommon interrupts at once. */
2387 if (status & (HostError | RxEarly | StatsFull | TxComplete | IntReq))
2388 vortex_error(dev, status);
2389
2390 if (--work_done < 0) {
39738e16
AB		 2391 pr_warning("%s: Too much work in interrupt, status %4.4x.\n",
2392 dev->name, status);
1da177e4
LT		 2393 /* Disable all pending interrupts. */
2394 do {
2395 vp->deferred |= status;
62afe595 2396 iowrite16(SetStatusEnb | (~vp->deferred & vp->status_enable),
1da177e4 2397 ioaddr + EL3_CMD);
62afe595
JL		 2398 iowrite16(AckIntr | (vp->deferred & 0x7ff), ioaddr + EL3_CMD);
2399 } while ((status = ioread16(ioaddr + EL3_CMD)) & IntLatch);
1da177e4
LT		 2400 /* The timer will reenable interrupts. */
2401 mod_timer(&vp->timer, jiffies + 1*HZ);
2402 break;
2403 }
2404 /* Acknowledge the IRQ. */
62afe595 2405 iowrite16(AckIntr | IntReq | IntLatch, ioaddr + EL3_CMD);
1da177e4 2406 if (vp->cb_fn_base) /* The PCMCIA people are idiots. */
62afe595 2407 iowrite32(0x8000, vp->cb_fn_base + 4);
1da177e4 2408
62afe595 2409 } while ((status = ioread16(ioaddr + EL3_STATUS)) & IntLatch);
1da177e4
LT		 2410
2411 if (vortex_debug > 4)
39738e16 2412 pr_debug("%s: exiting interrupt, status %4.4x.\n",
1da177e4
LT		 2413 dev->name, status);
2414handler_exit:
2415 spin_unlock(&vp->lock);
2416 return IRQ_HANDLED;
2417}
2418
2419static int vortex_rx(struct net_device *dev)
2420{
2421 struct vortex_private *vp = netdev_priv(dev);
62afe595 2422 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 2423 int i;
2424 short rx_status;
2425
2426 if (vortex_debug > 5)
39738e16 2427 pr_debug("vortex_rx(): status %4.4x, rx_status %4.4x.\n",
62afe595
JL		 2428 ioread16(ioaddr+EL3_STATUS), ioread16(ioaddr+RxStatus));
2429 while ((rx_status = ioread16(ioaddr + RxStatus)) > 0) {
1da177e4 2430 if (rx_status & 0x4000) { /* Error, update stats. */
62afe595 2431 unsigned char rx_error = ioread8(ioaddr + RxErrors);
1da177e4 2432 if (vortex_debug > 2)
39738e16 2433 pr_debug(" Rx error: status %2.2x.\n", rx_error);
1daad055
PZ		 2434 dev->stats.rx_errors++;
2435 if (rx_error & 0x01) dev->stats.rx_over_errors++;
2436 if (rx_error & 0x02) dev->stats.rx_length_errors++;
2437 if (rx_error & 0x04) dev->stats.rx_frame_errors++;
2438 if (rx_error & 0x08) dev->stats.rx_crc_errors++;
2439 if (rx_error & 0x10) dev->stats.rx_length_errors++;
1da177e4
LT		 2440 } else {
2441 /* The packet length: up to 4.5K!. */
2442 int pkt_len = rx_status & 0x1fff;
2443 struct sk_buff *skb;
2444
2445 skb = dev_alloc_skb(pkt_len + 5);
2446 if (vortex_debug > 4)
39738e16 2447 pr_debug("Receiving packet size %d status %4.4x.\n",
1da177e4
LT		 2448 pkt_len, rx_status);
2449 if (skb != NULL) {
1da177e4
LT		 2450 skb_reserve(skb, 2); /* Align IP on 16 byte boundaries */
2451 /* 'skb_put()' points to the start of sk_buff data area. */
2452 if (vp->bus_master &&
62afe595 2453 ! (ioread16(ioaddr + Wn7_MasterStatus) & 0x8000)) {
1da177e4
LT		 2454 dma_addr_t dma = pci_map_single(VORTEX_PCI(vp), skb_put(skb, pkt_len),
2455 pkt_len, PCI_DMA_FROMDEVICE);
62afe595
JL		 2456 iowrite32(dma, ioaddr + Wn7_MasterAddr);
2457 iowrite16((skb->len + 3) & ~3, ioaddr + Wn7_MasterLen);
2458 iowrite16(StartDMAUp, ioaddr + EL3_CMD);
2459 while (ioread16(ioaddr + Wn7_MasterStatus) & 0x8000)
1da177e4
LT		 2460 ;
2461 pci_unmap_single(VORTEX_PCI(vp), dma, pkt_len, PCI_DMA_FROMDEVICE);
2462 } else {
62afe595
JL		 2463 ioread32_rep(ioaddr + RX_FIFO,
2464 skb_put(skb, pkt_len),
2465 (pkt_len + 3) >> 2);
1da177e4 2466 }
62afe595 2467 iowrite16(RxDiscard, ioaddr + EL3_CMD); /* Pop top Rx packet. */
1da177e4
LT		 2468 skb->protocol = eth_type_trans(skb, dev);
2469 netif_rx(skb);
1daad055 2470 dev->stats.rx_packets++;
1da177e4
LT		 2471 /* Wait a limited time to go to next packet. */
2472 for (i = 200; i >= 0; i--)
62afe595 2473 if ( ! (ioread16(ioaddr + EL3_STATUS) & CmdInProgress))
1da177e4
LT		 2474 break;
2475 continue;
2476 } else if (vortex_debug > 0)
39738e16
AB		 2477 pr_notice("%s: No memory to allocate a sk_buff of size %d.\n",
2478 dev->name, pkt_len);
1daad055 2479 dev->stats.rx_dropped++;
1da177e4 2480 }
1da177e4
LT		 2481 issue_and_wait(dev, RxDiscard);
2482 }
2483
2484 return 0;
2485}
2486
2487static int
2488boomerang_rx(struct net_device *dev)
2489{
2490 struct vortex_private *vp = netdev_priv(dev);
2491 int entry = vp->cur_rx % RX_RING_SIZE;
62afe595 2492 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 2493 int rx_status;
2494 int rx_work_limit = vp->dirty_rx + RX_RING_SIZE - vp->cur_rx;
2495
2496 if (vortex_debug > 5)
39738e16 2497 pr_debug("boomerang_rx(): status %4.4x\n", ioread16(ioaddr+EL3_STATUS));
1da177e4
LT		 2498
2499 while ((rx_status = le32_to_cpu(vp->rx_ring[entry].status)) & RxDComplete){
2500 if (--rx_work_limit < 0)
2501 break;
2502 if (rx_status & RxDError) { /* Error, update stats. */
2503 unsigned char rx_error = rx_status >> 16;
2504 if (vortex_debug > 2)
39738e16 2505 pr_debug(" Rx error: status %2.2x.\n", rx_error);
1daad055
PZ		 2506 dev->stats.rx_errors++;
2507 if (rx_error & 0x01) dev->stats.rx_over_errors++;
2508 if (rx_error & 0x02) dev->stats.rx_length_errors++;
2509 if (rx_error & 0x04) dev->stats.rx_frame_errors++;
2510 if (rx_error & 0x08) dev->stats.rx_crc_errors++;
2511 if (rx_error & 0x10) dev->stats.rx_length_errors++;
1da177e4
LT		 2512 } else {
2513 /* The packet length: up to 4.5K!. */
2514 int pkt_len = rx_status & 0x1fff;
2515 struct sk_buff *skb;
2516 dma_addr_t dma = le32_to_cpu(vp->rx_ring[entry].addr);
2517
2518 if (vortex_debug > 4)
39738e16 2519 pr_debug("Receiving packet size %d status %4.4x.\n",
1da177e4
LT		 2520 pkt_len, rx_status);
2521
2522 /* Check if the packet is long enough to just accept without
2523 copying to a properly sized skbuff. */
cc2d6596 2524 if (pkt_len < rx_copybreak && (skb = dev_alloc_skb(pkt_len + 2)) != NULL) {
1da177e4
LT		 2525 skb_reserve(skb, 2); /* Align IP on 16 byte boundaries */
2526 pci_dma_sync_single_for_cpu(VORTEX_PCI(vp), dma, PKT_BUF_SZ, PCI_DMA_FROMDEVICE);
2527 /* 'skb_put()' points to the start of sk_buff data area. */
2528 memcpy(skb_put(skb, pkt_len),
689be439 2529 vp->rx_skbuff[entry]->data,
1da177e4
LT		 2530 pkt_len);
2531 pci_dma_sync_single_for_device(VORTEX_PCI(vp), dma, PKT_BUF_SZ, PCI_DMA_FROMDEVICE);
2532 vp->rx_copy++;
2533 } else {
2534 /* Pass up the skbuff already on the Rx ring. */
2535 skb = vp->rx_skbuff[entry];
2536 vp->rx_skbuff[entry] = NULL;
2537 skb_put(skb, pkt_len);
2538 pci_unmap_single(VORTEX_PCI(vp), dma, PKT_BUF_SZ, PCI_DMA_FROMDEVICE);
2539 vp->rx_nocopy++;
2540 }
2541 skb->protocol = eth_type_trans(skb, dev);
2542 { /* Use hardware checksum info. */
2543 int csum_bits = rx_status & 0xee000000;
2544 if (csum_bits &&
2545 (csum_bits == (IPChksumValid | TCPChksumValid) ||
2546 csum_bits == (IPChksumValid | UDPChksumValid))) {
2547 skb->ip_summed = CHECKSUM_UNNECESSARY;
2548 vp->rx_csumhits++;
2549 }
2550 }
2551 netif_rx(skb);
1daad055 2552 dev->stats.rx_packets++;
1da177e4
LT		 2553 }
2554 entry = (++vp->cur_rx) % RX_RING_SIZE;
2555 }
2556 /* Refill the Rx ring buffers. */
2557 for (; vp->cur_rx - vp->dirty_rx > 0; vp->dirty_rx++) {
2558 struct sk_buff *skb;
2559 entry = vp->dirty_rx % RX_RING_SIZE;
2560 if (vp->rx_skbuff[entry] == NULL) {
89d71a66 2561 skb = netdev_alloc_skb_ip_align(dev, PKT_BUF_SZ);
1da177e4
LT		 2562 if (skb == NULL) {
2563 static unsigned long last_jif;
ff5688ae 2564 if (time_after(jiffies, last_jif + 10 * HZ)) {
39738e16 2565 pr_warning("%s: memory shortage\n", dev->name);
1da177e4
LT		 2566 last_jif = jiffies;
2567 }
2568 if ((vp->cur_rx - vp->dirty_rx) == RX_RING_SIZE)
2569 mod_timer(&vp->rx_oom_timer, RUN_AT(HZ * 1));
2570 break; /* Bad news! */
2571 }
9a5d3414 2572
689be439 2573 vp->rx_ring[entry].addr = cpu_to_le32(pci_map_single(VORTEX_PCI(vp), skb->data, PKT_BUF_SZ, PCI_DMA_FROMDEVICE));
1da177e4
LT		 2574 vp->rx_skbuff[entry] = skb;
2575 }
2576 vp->rx_ring[entry].status = 0; /* Clear complete bit. */
62afe595 2577 iowrite16(UpUnstall, ioaddr + EL3_CMD);
1da177e4
LT		 2578 }
2579 return 0;
2580}
2581
2582/*
2583 * If we've hit a total OOM refilling the Rx ring we poll once a second
2584 * for some memory. Otherwise there is no way to restart the rx process.
2585 */
2586static void
2587rx_oom_timer(unsigned long arg)
2588{
2589 struct net_device *dev = (struct net_device *)arg;
2590 struct vortex_private *vp = netdev_priv(dev);
2591
2592 spin_lock_irq(&vp->lock);
2593 if ((vp->cur_rx - vp->dirty_rx) == RX_RING_SIZE) /* This test is redundant, but makes me feel good */
2594 boomerang_rx(dev);
2595 if (vortex_debug > 1) {
39738e16 2596 pr_debug("%s: rx_oom_timer %s\n", dev->name,
1da177e4
LT		 2597 ((vp->cur_rx - vp->dirty_rx) != RX_RING_SIZE) ? "succeeded" : "retrying");
2598 }
2599 spin_unlock_irq(&vp->lock);
2600}
2601
2602static void
2603vortex_down(struct net_device *dev, int final_down)
2604{
2605 struct vortex_private *vp = netdev_priv(dev);
62afe595 2606 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 2607
2608 netif_stop_queue (dev);
2609
2610 del_timer_sync(&vp->rx_oom_timer);
2611 del_timer_sync(&vp->timer);
2612
1daad055 2613 /* Turn off statistics ASAP. We update dev->stats below. */
62afe595 2614 iowrite16(StatsDisable, ioaddr + EL3_CMD);
1da177e4
LT		 2615
2616 /* Disable the receiver and transmitter. */
62afe595
JL		 2617 iowrite16(RxDisable, ioaddr + EL3_CMD);
2618 iowrite16(TxDisable, ioaddr + EL3_CMD);
1da177e4
LT		 2619
2620 /* Disable receiving 802.1q tagged frames */
2621 set_8021q_mode(dev, 0);
2622
2623 if (dev->if_port == XCVR_10base2)
2624 /* Turn off thinnet power. Green! */
62afe595 2625 iowrite16(StopCoax, ioaddr + EL3_CMD);
1da177e4 2626
62afe595 2627 iowrite16(SetIntrEnb | 0x0000, ioaddr + EL3_CMD);
1da177e4
LT		 2628
2629 update_stats(ioaddr, dev);
2630 if (vp->full_bus_master_rx)
62afe595 2631 iowrite32(0, ioaddr + UpListPtr);
1da177e4 2632 if (vp->full_bus_master_tx)
62afe595 2633 iowrite32(0, ioaddr + DownListPtr);
1da177e4
LT		 2634
2635 if (final_down && VORTEX_PCI(vp)) {
3c8fad18 2636 vp->pm_state_valid = 1;
1da177e4
LT		 2637 pci_save_state(VORTEX_PCI(vp));
2638 acpi_set_WOL(dev);
2639 }
2640}
2641
2642static int
2643vortex_close(struct net_device *dev)
2644{
2645 struct vortex_private *vp = netdev_priv(dev);
62afe595 2646 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 2647 int i;
2648
2649 if (netif_device_present(dev))
2650 vortex_down(dev, 1);
2651
2652 if (vortex_debug > 1) {
39738e16 2653 pr_debug("%s: vortex_close() status %4.4x, Tx status %2.2x.\n",
62afe595 2654 dev->name, ioread16(ioaddr + EL3_STATUS), ioread8(ioaddr + TxStatus));
39738e16 2655 pr_debug("%s: vortex close stats: rx_nocopy %d rx_copy %d"
1da177e4
LT		 2656 " tx_queued %d Rx pre-checksummed %d.\n",
2657 dev->name, vp->rx_nocopy, vp->rx_copy, vp->queued_packet, vp->rx_csumhits);
2658 }
2659
2660#if DO_ZEROCOPY
32fb5f06
JL		 2661 if (vp->rx_csumhits &&
2662 (vp->drv_flags & HAS_HWCKSM) == 0 &&
2663 (vp->card_idx >= MAX_UNITS || hw_checksums[vp->card_idx] == -1)) {
39738e16 2664 pr_warning("%s supports hardware checksums, and we're not using them!\n", dev->name);
1da177e4
LT		 2665 }
2666#endif
6aa20a22 2667
1da177e4
LT		 2668 free_irq(dev->irq, dev);
2669
2670 if (vp->full_bus_master_rx) { /* Free Boomerang bus master Rx buffers. */
2671 for (i = 0; i < RX_RING_SIZE; i++)
2672 if (vp->rx_skbuff[i]) {
2673 pci_unmap_single( VORTEX_PCI(vp), le32_to_cpu(vp->rx_ring[i].addr),
2674 PKT_BUF_SZ, PCI_DMA_FROMDEVICE);
2675 dev_kfree_skb(vp->rx_skbuff[i]);
2676 vp->rx_skbuff[i] = NULL;
2677 }
2678 }
2679 if (vp->full_bus_master_tx) { /* Free Boomerang bus master Tx buffers. */
2680 for (i = 0; i < TX_RING_SIZE; i++) {
2681 if (vp->tx_skbuff[i]) {
2682 struct sk_buff *skb = vp->tx_skbuff[i];
2683#if DO_ZEROCOPY
2684 int k;
2685
2686 for (k=0; k<=skb_shinfo(skb)->nr_frags; k++)
2687 pci_unmap_single(VORTEX_PCI(vp),
2688 le32_to_cpu(vp->tx_ring[i].frag[k].addr),
2689 le32_to_cpu(vp->tx_ring[i].frag[k].length)&0xFFF,
2690 PCI_DMA_TODEVICE);
2691#else
2692 pci_unmap_single(VORTEX_PCI(vp), le32_to_cpu(vp->tx_ring[i].addr), skb->len, PCI_DMA_TODEVICE);
2693#endif
2694 dev_kfree_skb(skb);
2695 vp->tx_skbuff[i] = NULL;
2696 }
2697 }
2698 }
2699
2700 return 0;
2701}
2702
2703static void
2704dump_tx_ring(struct net_device *dev)
2705{
2706 if (vortex_debug > 0) {
2707 struct vortex_private *vp = netdev_priv(dev);
62afe595 2708 void __iomem *ioaddr = vp->ioaddr;
6aa20a22 2709
1da177e4
LT		 2710 if (vp->full_bus_master_tx) {
2711 int i;
62afe595 2712 int stalled = ioread32(ioaddr + PktStatus) & 0x04; /* Possible racy. But it's only debug stuff */
1da177e4 2713
39738e16 2714 pr_err(" Flags; bus-master %d, dirty %d(%d) current %d(%d)\n",
1da177e4
LT		 2715 vp->full_bus_master_tx,
2716 vp->dirty_tx, vp->dirty_tx % TX_RING_SIZE,
2717 vp->cur_tx, vp->cur_tx % TX_RING_SIZE);
39738e16 2718 pr_err(" Transmit list %8.8x vs. %p.\n",
62afe595 2719 ioread32(ioaddr + DownListPtr),
1da177e4
LT		 2720 &vp->tx_ring[vp->dirty_tx % TX_RING_SIZE]);
2721 issue_and_wait(dev, DownStall);
2722 for (i = 0; i < TX_RING_SIZE; i++) {
0cb13536
JD		 2723 unsigned int length;
2724
1da177e4 2725#if DO_ZEROCOPY
0cb13536 2726 length = le32_to_cpu(vp->tx_ring[i].frag[0].length);
1da177e4 2727#else
0cb13536 2728 length = le32_to_cpu(vp->tx_ring[i].length);
1da177e4 2729#endif
0cb13536
JD		 2730 pr_err(" %d: @%p length %8.8x status %8.8x\n",
2731 i, &vp->tx_ring[i], length,
1da177e4
LT		 2732 le32_to_cpu(vp->tx_ring[i].status));
2733 }
2734 if (!stalled)
62afe595 2735 iowrite16(DownUnstall, ioaddr + EL3_CMD);
1da177e4
LT		 2736 }
2737 }
2738}
2739
2740static struct net_device_stats *vortex_get_stats(struct net_device *dev)
2741{
2742 struct vortex_private *vp = netdev_priv(dev);
62afe595 2743 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 2744 unsigned long flags;
2745
2746 if (netif_device_present(dev)) { /* AKPM: Used to be netif_running */
2747 spin_lock_irqsave (&vp->lock, flags);
62afe595 2748 update_stats(ioaddr, dev);
1da177e4
LT		 2749 spin_unlock_irqrestore (&vp->lock, flags);
2750 }
1daad055 2751 return &dev->stats;
1da177e4
LT		 2752}
2753
2754/* Update statistics.
2755 Unlike with the EL3 we need not worry about interrupts changing
2756 the window setting from underneath us, but we must still guard
2757 against a race condition with a StatsUpdate interrupt updating the
2758 table. This is done by checking that the ASM (!) code generated uses
2759 atomic updates with '+='.
2760 */
62afe595 2761static void update_stats(void __iomem *ioaddr, struct net_device *dev)
1da177e4
LT		 2762{
2763 struct vortex_private *vp = netdev_priv(dev);
62afe595 2764 int old_window = ioread16(ioaddr + EL3_CMD);
1da177e4
LT		 2765
2766 if (old_window == 0xffff) /* Chip suspended or ejected. */
2767 return;
2768 /* Unlike the 3c5x9 we need not turn off stats updates while reading. */
2769 /* Switch to the stats window, and read everything. */
2770 EL3WINDOW(6);
1daad055
PZ		 2771 dev->stats.tx_carrier_errors += ioread8(ioaddr + 0);
2772 dev->stats.tx_heartbeat_errors += ioread8(ioaddr + 1);
2773 dev->stats.tx_window_errors += ioread8(ioaddr + 4);
2774 dev->stats.rx_fifo_errors += ioread8(ioaddr + 5);
2775 dev->stats.tx_packets += ioread8(ioaddr + 6);
2776 dev->stats.tx_packets += (ioread8(ioaddr + 9)&0x30) << 4;
62afe595 2777 /* Rx packets */ ioread8(ioaddr + 7); /* Must read to clear */
1da177e4
LT		 2778 /* Don't bother with register 9, an extension of registers 6&7.
2779 If we do use the 6&7 values the atomic update assumption above
2780 is invalid. */
1daad055
PZ		 2781 dev->stats.rx_bytes += ioread16(ioaddr + 10);
2782 dev->stats.tx_bytes += ioread16(ioaddr + 12);
1da177e4 2783 /* Extra stats for get_ethtool_stats() */
62afe595 2784 vp->xstats.tx_multiple_collisions += ioread8(ioaddr + 2);
8d1d0340 2785 vp->xstats.tx_single_collisions += ioread8(ioaddr + 3);
62afe595 2786 vp->xstats.tx_deferred += ioread8(ioaddr + 8);
1da177e4 2787 EL3WINDOW(4);
62afe595 2788 vp->xstats.rx_bad_ssd += ioread8(ioaddr + 12);
1da177e4 2789
1daad055 2790 dev->stats.collisions = vp->xstats.tx_multiple_collisions
8d1d0340
SK		 2791 + vp->xstats.tx_single_collisions
2792 + vp->xstats.tx_max_collisions;
2793
1da177e4 2794 {
62afe595 2795 u8 up = ioread8(ioaddr + 13);
1daad055
PZ		 2796 dev->stats.rx_bytes += (up & 0x0f) << 16;
2797 dev->stats.tx_bytes += (up & 0xf0) << 12;
1da177e4
LT		 2798 }
2799
2800 EL3WINDOW(old_window >> 13);
2801 return;
2802}
2803
2804static int vortex_nway_reset(struct net_device *dev)
2805{
2806 struct vortex_private *vp = netdev_priv(dev);
62afe595 2807 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 2808 unsigned long flags;
2809 int rc;
2810
2811 spin_lock_irqsave(&vp->lock, flags);
2812 EL3WINDOW(4);
2813 rc = mii_nway_restart(&vp->mii);
2814 spin_unlock_irqrestore(&vp->lock, flags);
2815 return rc;
2816}
2817
1da177e4
LT		 2818static int vortex_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2819{
2820 struct vortex_private *vp = netdev_priv(dev);
62afe595 2821 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 2822 unsigned long flags;
2823 int rc;
2824
2825 spin_lock_irqsave(&vp->lock, flags);
2826 EL3WINDOW(4);
2827 rc = mii_ethtool_gset(&vp->mii, cmd);
2828 spin_unlock_irqrestore(&vp->lock, flags);
2829 return rc;
2830}
2831
2832static int vortex_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2833{
2834 struct vortex_private *vp = netdev_priv(dev);
62afe595 2835 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 2836 unsigned long flags;
2837 int rc;
2838
2839 spin_lock_irqsave(&vp->lock, flags);
2840 EL3WINDOW(4);
2841 rc = mii_ethtool_sset(&vp->mii, cmd);
2842 spin_unlock_irqrestore(&vp->lock, flags);
2843 return rc;
2844}
2845
2846static u32 vortex_get_msglevel(struct net_device *dev)
2847{
2848 return vortex_debug;
2849}
2850
2851static void vortex_set_msglevel(struct net_device *dev, u32 dbg)
2852{
2853 vortex_debug = dbg;
2854}
2855
b9f2c044 2856static int vortex_get_sset_count(struct net_device *dev, int sset)
1da177e4 2857{
b9f2c044
JG		 2858 switch (sset) {
2859 case ETH_SS_STATS:
2860 return VORTEX_NUM_STATS;
2861 default:
2862 return -EOPNOTSUPP;
2863 }
1da177e4
LT		 2864}
2865
2866static void vortex_get_ethtool_stats(struct net_device *dev,
2867 struct ethtool_stats *stats, u64 *data)
2868{
2869 struct vortex_private *vp = netdev_priv(dev);
62afe595 2870 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 2871 unsigned long flags;
2872
2873 spin_lock_irqsave(&vp->lock, flags);
62afe595 2874 update_stats(ioaddr, dev);
1da177e4
LT		 2875 spin_unlock_irqrestore(&vp->lock, flags);
2876
2877 data[0] = vp->xstats.tx_deferred;
8d1d0340
SK		 2878 data[1] = vp->xstats.tx_max_collisions;
2879 data[2] = vp->xstats.tx_multiple_collisions;
2880 data[3] = vp->xstats.tx_single_collisions;
2881 data[4] = vp->xstats.rx_bad_ssd;
1da177e4
LT		 2882}
2883
2884
2885static void vortex_get_strings(struct net_device *dev, u32 stringset, u8 *data)
2886{
2887 switch (stringset) {
2888 case ETH_SS_STATS:
2889 memcpy(data, &ethtool_stats_keys, sizeof(ethtool_stats_keys));
2890 break;
2891 default:
2892 WARN_ON(1);
2893 break;
2894 }
2895}
2896
2897static void vortex_get_drvinfo(struct net_device *dev,
2898 struct ethtool_drvinfo *info)
2899{
2900 struct vortex_private *vp = netdev_priv(dev);
2901
2902 strcpy(info->driver, DRV_NAME);
1da177e4
LT		 2903 if (VORTEX_PCI(vp)) {
2904 strcpy(info->bus_info, pci_name(VORTEX_PCI(vp)));
2905 } else {
2906 if (VORTEX_EISA(vp))
86de79b6 2907 strcpy(info->bus_info, dev_name(vp->gendev));
1da177e4
LT		 2908 else
2909 sprintf(info->bus_info, "EISA 0x%lx %d",
2910 dev->base_addr, dev->irq);
2911 }
2912}
2913
7282d491 2914static const struct ethtool_ops vortex_ethtool_ops = {
1da177e4
LT		 2915 .get_drvinfo = vortex_get_drvinfo,
2916 .get_strings = vortex_get_strings,
2917 .get_msglevel = vortex_get_msglevel,
2918 .set_msglevel = vortex_set_msglevel,
2919 .get_ethtool_stats = vortex_get_ethtool_stats,
b9f2c044 2920 .get_sset_count = vortex_get_sset_count,
1da177e4
LT		 2921 .get_settings = vortex_get_settings,
2922 .set_settings = vortex_set_settings,
373a6887 2923 .get_link = ethtool_op_get_link,
1da177e4
LT		 2924 .nway_reset = vortex_nway_reset,
2925};
2926
2927#ifdef CONFIG_PCI
2928/*
2929 * Must power the device up to do MDIO operations
2930 */
2931static int vortex_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
2932{
2933 int err;
2934 struct vortex_private *vp = netdev_priv(dev);
62afe595 2935 void __iomem *ioaddr = vp->ioaddr;
1da177e4 2936 unsigned long flags;
cc2d6596 2937 pci_power_t state = 0;
1da177e4
LT		 2938
2939 if(VORTEX_PCI(vp))
2940 state = VORTEX_PCI(vp)->current_state;
2941
2942 /* The kernel core really should have pci_get_power_state() */
2943
2944 if(state != 0)
2945 pci_set_power_state(VORTEX_PCI(vp), PCI_D0);
2946 spin_lock_irqsave(&vp->lock, flags);
2947 EL3WINDOW(4);
2948 err = generic_mii_ioctl(&vp->mii, if_mii(rq), cmd, NULL);
2949 spin_unlock_irqrestore(&vp->lock, flags);
2950 if(state != 0)
2951 pci_set_power_state(VORTEX_PCI(vp), state);
2952
2953 return err;
2954}
2955#endif
2956
2957
2958/* Pre-Cyclone chips have no documented multicast filter, so the only
2959 multicast setting is to receive all multicast frames. At least
2960 the chip has a very clean way to set the mode, unlike many others. */
2961static void set_rx_mode(struct net_device *dev)
2962{
62afe595
JL		 2963 struct vortex_private *vp = netdev_priv(dev);
2964 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 2965 int new_mode;
2966
2967 if (dev->flags & IFF_PROMISC) {
d5b20697 2968 if (vortex_debug > 3)
39738e16 2969 pr_notice("%s: Setting promiscuous mode.\n", dev->name);
1da177e4 2970 new_mode = SetRxFilter|RxStation|RxMulticast|RxBroadcast|RxProm;
59ce25d9 2971 } else if (!netdev_mc_empty(dev) || dev->flags & IFF_ALLMULTI) {
1da177e4
LT		 2972 new_mode = SetRxFilter|RxStation|RxMulticast|RxBroadcast;
2973 } else
2974 new_mode = SetRxFilter | RxStation | RxBroadcast;
2975
62afe595 2976 iowrite16(new_mode, ioaddr + EL3_CMD);
1da177e4
LT		 2977}
2978
2979#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
2980/* Setup the card so that it can receive frames with an 802.1q VLAN tag.
2981 Note that this must be done after each RxReset due to some backwards
2982 compatibility logic in the Cyclone and Tornado ASICs */
2983
2984/* The Ethernet Type used for 802.1q tagged frames */
2985#define VLAN_ETHER_TYPE 0x8100
2986
2987static void set_8021q_mode(struct net_device *dev, int enable)
2988{
2989 struct vortex_private *vp = netdev_priv(dev);
62afe595
JL		 2990 void __iomem *ioaddr = vp->ioaddr;
2991 int old_window = ioread16(ioaddr + EL3_CMD);
1da177e4
LT		 2992 int mac_ctrl;
2993
2994 if ((vp->drv_flags&IS_CYCLONE) || (vp->drv_flags&IS_TORNADO)) {
2995 /* cyclone and tornado chipsets can recognize 802.1q
2996 * tagged frames and treat them correctly */
2997
2998 int max_pkt_size = dev->mtu+14; /* MTU+Ethernet header */
2999 if (enable)
3000 max_pkt_size += 4; /* 802.1Q VLAN tag */
3001
3002 EL3WINDOW(3);
62afe595 3003 iowrite16(max_pkt_size, ioaddr+Wn3_MaxPktSize);
1da177e4
LT		 3004
3005 /* set VlanEtherType to let the hardware checksumming
3006 treat tagged frames correctly */
3007 EL3WINDOW(7);
62afe595 3008 iowrite16(VLAN_ETHER_TYPE, ioaddr+Wn7_VlanEtherType);
1da177e4
LT		 3009 } else {
3010 /* on older cards we have to enable large frames */
3011
3012 vp->large_frames = dev->mtu > 1500 || enable;
3013
3014 EL3WINDOW(3);
62afe595 3015 mac_ctrl = ioread16(ioaddr+Wn3_MAC_Ctrl);
1da177e4
LT		 3016 if (vp->large_frames)
3017 mac_ctrl |= 0x40;
3018 else
3019 mac_ctrl &= ~0x40;
62afe595 3020 iowrite16(mac_ctrl, ioaddr+Wn3_MAC_Ctrl);
1da177e4
LT		 3021 }
3022
3023 EL3WINDOW(old_window);
3024}
3025#else
3026
3027static void set_8021q_mode(struct net_device *dev, int enable)
3028{
3029}
3030
3031
3032#endif
3033
3034/* MII transceiver control section.
3035 Read and write the MII registers using software-generated serial
3036 MDIO protocol. See the MII specifications or DP83840A data sheet
3037 for details. */
3038
3039/* The maximum data clock rate is 2.5 Mhz. The minimum timing is usually
3040 met by back-to-back PCI I/O cycles, but we insert a delay to avoid
3041 "overclocking" issues. */
62afe595 3042#define mdio_delay() ioread32(mdio_addr)
1da177e4
LT		 3043
3044#define MDIO_SHIFT_CLK 0x01
3045#define MDIO_DIR_WRITE 0x04
3046#define MDIO_DATA_WRITE0 (0x00 | MDIO_DIR_WRITE)
3047#define MDIO_DATA_WRITE1 (0x02 | MDIO_DIR_WRITE)
3048#define MDIO_DATA_READ 0x02
3049#define MDIO_ENB_IN 0x00
3050
3051/* Generate the preamble required for initial synchronization and
3052 a few older transceivers. */
62afe595 3053static void mdio_sync(void __iomem *ioaddr, int bits)
1da177e4 3054{
62afe595 3055 void __iomem *mdio_addr = ioaddr + Wn4_PhysicalMgmt;
1da177e4
LT		 3056
3057 /* Establish sync by sending at least 32 logic ones. */
3058 while (-- bits >= 0) {
62afe595 3059 iowrite16(MDIO_DATA_WRITE1, mdio_addr);
1da177e4 3060 mdio_delay();
62afe595 3061 iowrite16(MDIO_DATA_WRITE1 | MDIO_SHIFT_CLK, mdio_addr);
1da177e4
LT		 3062 mdio_delay();
3063 }
3064}
3065
3066static int mdio_read(struct net_device *dev, int phy_id, int location)
3067{
3068 int i;
62afe595
JL		 3069 struct vortex_private *vp = netdev_priv(dev);
3070 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 3071 int read_cmd = (0xf6 << 10) | (phy_id << 5) | location;
3072 unsigned int retval = 0;
62afe595 3073 void __iomem *mdio_addr = ioaddr + Wn4_PhysicalMgmt;
1da177e4
LT		 3074
3075 if (mii_preamble_required)
3076 mdio_sync(ioaddr, 32);
3077
3078 /* Shift the read command bits out. */
3079 for (i = 14; i >= 0; i--) {
3080 int dataval = (read_cmd&(1<<i)) ? MDIO_DATA_WRITE1 : MDIO_DATA_WRITE0;
62afe595 3081 iowrite16(dataval, mdio_addr);
1da177e4 3082 mdio_delay();
62afe595 3083 iowrite16(dataval | MDIO_SHIFT_CLK, mdio_addr);
1da177e4
LT		 3084 mdio_delay();
3085 }
3086 /* Read the two transition, 16 data, and wire-idle bits. */
3087 for (i = 19; i > 0; i--) {
62afe595 3088 iowrite16(MDIO_ENB_IN, mdio_addr);
1da177e4 3089 mdio_delay();
62afe595
JL		 3090 retval = (retval << 1) | ((ioread16(mdio_addr) & MDIO_DATA_READ) ? 1 : 0);
3091 iowrite16(MDIO_ENB_IN | MDIO_SHIFT_CLK, mdio_addr);
1da177e4
LT		 3092 mdio_delay();
3093 }
3094 return retval & 0x20000 ? 0xffff : retval>>1 & 0xffff;
3095}
3096
3097static void mdio_write(struct net_device *dev, int phy_id, int location, int value)
3098{
62afe595
JL		 3099 struct vortex_private *vp = netdev_priv(dev);
3100 void __iomem *ioaddr = vp->ioaddr;
1da177e4 3101 int write_cmd = 0x50020000 | (phy_id << 23) | (location << 18) | value;
62afe595 3102 void __iomem *mdio_addr = ioaddr + Wn4_PhysicalMgmt;
1da177e4
LT		 3103 int i;
3104
3105 if (mii_preamble_required)
3106 mdio_sync(ioaddr, 32);
3107
3108 /* Shift the command bits out. */
3109 for (i = 31; i >= 0; i--) {
3110 int dataval = (write_cmd&(1<<i)) ? MDIO_DATA_WRITE1 : MDIO_DATA_WRITE0;
62afe595 3111 iowrite16(dataval, mdio_addr);
1da177e4 3112 mdio_delay();
62afe595 3113 iowrite16(dataval | MDIO_SHIFT_CLK, mdio_addr);
1da177e4
LT		 3114 mdio_delay();
3115 }
3116 /* Leave the interface idle. */
3117 for (i = 1; i >= 0; i--) {
62afe595 3118 iowrite16(MDIO_ENB_IN, mdio_addr);
1da177e4 3119 mdio_delay();
62afe595 3120 iowrite16(MDIO_ENB_IN | MDIO_SHIFT_CLK, mdio_addr);
1da177e4
LT		 3121 mdio_delay();
3122 }
3123 return;
3124}
a880c4cd 3125
1da177e4
LT		 3126/* ACPI: Advanced Configuration and Power Interface. */
3127/* Set Wake-On-LAN mode and put the board into D3 (power-down) state. */
3128static void acpi_set_WOL(struct net_device *dev)
3129{
3130 struct vortex_private *vp = netdev_priv(dev);
62afe595 3131 void __iomem *ioaddr = vp->ioaddr;
1da177e4 3132
c17931c5
SK		 3133 device_set_wakeup_enable(vp->gendev, vp->enable_wol);
3134
1da177e4
LT		 3135 if (vp->enable_wol) {
3136 /* Power up on: 1==Downloaded Filter, 2==Magic Packets, 4==Link Status. */
3137 EL3WINDOW(7);
62afe595 3138 iowrite16(2, ioaddr + 0x0c);
1da177e4 3139 /* The RxFilter must accept the WOL frames. */
62afe595
JL		 3140 iowrite16(SetRxFilter|RxStation|RxMulticast|RxBroadcast, ioaddr + EL3_CMD);
3141 iowrite16(RxEnable, ioaddr + EL3_CMD);
1da177e4 3142
1a1769f3 3143 if (pci_enable_wake(VORTEX_PCI(vp), PCI_D3hot, 1)) {
39738e16 3144 pr_info("%s: WOL not supported.\n", pci_name(VORTEX_PCI(vp)));
1a1769f3
SK		 3145
3146 vp->enable_wol = 0;
3147 return;
3148 }
3c8fad18
DR		 3149
3150 /* Change the power state to D3; RxEnable doesn't take effect. */
3151 pci_set_power_state(VORTEX_PCI(vp), PCI_D3hot);
1da177e4 3152 }
1da177e4
LT		 3153}
3154
3155
a880c4cd 3156static void __devexit vortex_remove_one(struct pci_dev *pdev)
1da177e4
LT		 3157{
3158 struct net_device *dev = pci_get_drvdata(pdev);
3159 struct vortex_private *vp;
3160
3161 if (!dev) {
39738e16 3162 pr_err("vortex_remove_one called for Compaq device!\n");
1da177e4
LT		 3163 BUG();
3164 }
3165
3166 vp = netdev_priv(dev);
3167
62afe595
JL		 3168 if (vp->cb_fn_base)
3169 pci_iounmap(VORTEX_PCI(vp), vp->cb_fn_base);
3170
1da177e4
LT		 3171 unregister_netdev(dev);
3172
3173 if (VORTEX_PCI(vp)) {
3174 pci_set_power_state(VORTEX_PCI(vp), PCI_D0); /* Go active */
3175 if (vp->pm_state_valid)
3176 pci_restore_state(VORTEX_PCI(vp));
3177 pci_disable_device(VORTEX_PCI(vp));
3178 }
3179 /* Should really use issue_and_wait() here */
62afe595
JL		 3180 iowrite16(TotalReset | ((vp->drv_flags & EEPROM_RESET) ? 0x04 : 0x14),
3181 vp->ioaddr + EL3_CMD);
3182
3183 pci_iounmap(VORTEX_PCI(vp), vp->ioaddr);
1da177e4
LT		 3184
3185 pci_free_consistent(pdev,
3186 sizeof(struct boom_rx_desc) * RX_RING_SIZE
3187 + sizeof(struct boom_tx_desc) * TX_RING_SIZE,
3188 vp->rx_ring,
3189 vp->rx_ring_dma);
3190 if (vp->must_free_region)
3191 release_region(dev->base_addr, vp->io_size);
3192 free_netdev(dev);
3193}
3194
3195
3196static struct pci_driver vortex_driver = {
3197 .name = "3c59x",
3198 .probe = vortex_init_one,
3199 .remove = __devexit_p(vortex_remove_one),
3200 .id_table = vortex_pci_tbl,
7bfc4ab5 3201 .driver.pm = VORTEX_PM_OPS,
1da177e4
LT		 3202};
3203
3204
3205static int vortex_have_pci;
3206static int vortex_have_eisa;
3207
3208
a880c4cd 3209static int __init vortex_init(void)
1da177e4
LT		 3210{
3211 int pci_rc, eisa_rc;
3212
29917620 3213 pci_rc = pci_register_driver(&vortex_driver);
1da177e4
LT		 3214 eisa_rc = vortex_eisa_init();
3215
3216 if (pci_rc == 0)
3217 vortex_have_pci = 1;
3218 if (eisa_rc > 0)
3219 vortex_have_eisa = 1;
3220
3221 return (vortex_have_pci + vortex_have_eisa) ? 0 : -ENODEV;
3222}
3223
3224
a880c4cd 3225static void __exit vortex_eisa_cleanup(void)
1da177e4
LT		 3226{
3227 struct vortex_private *vp;
62afe595 3228 void __iomem *ioaddr;
1da177e4
LT		 3229
3230#ifdef CONFIG_EISA
3231 /* Take care of the EISA devices */
a880c4cd 3232 eisa_driver_unregister(&vortex_eisa_driver);
1da177e4 3233#endif
6aa20a22 3234
1da177e4 3235 if (compaq_net_device) {
454d7c9b 3236 vp = netdev_priv(compaq_net_device);
62afe595
JL		 3237 ioaddr = ioport_map(compaq_net_device->base_addr,
3238 VORTEX_TOTAL_SIZE);
1da177e4 3239
a880c4cd
SK		 3240 unregister_netdev(compaq_net_device);
3241 iowrite16(TotalReset, ioaddr + EL3_CMD);
62afe595
JL		 3242 release_region(compaq_net_device->base_addr,
3243 VORTEX_TOTAL_SIZE);
1da177e4 3244
a880c4cd 3245 free_netdev(compaq_net_device);
1da177e4
LT		 3246 }
3247}
3248
3249
a880c4cd 3250static void __exit vortex_cleanup(void)
1da177e4
LT		 3251{
3252 if (vortex_have_pci)
a880c4cd 3253 pci_unregister_driver(&vortex_driver);
1da177e4 3254 if (vortex_have_eisa)
a880c4cd 3255 vortex_eisa_cleanup();
1da177e4
LT		 3256}
3257
3258
3259module_init(vortex_init);
3260module_exit(vortex_cleanup);
Linux kernel - Deliverables
This page took 0.774978 seconds and 5 git commands to generate.