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Massive net driver const-ification.
[deliverable/linux.git] / drivers / net / 3c59x.c
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1da177e4
LT		 1/* EtherLinkXL.c: A 3Com EtherLink PCI III/XL ethernet driver for linux. */
2/*
3 Written 1996-1999 by Donald Becker.
4
5 This software may be used and distributed according to the terms
6 of the GNU General Public License, incorporated herein by reference.
7
8 This driver is for the 3Com "Vortex" and "Boomerang" series ethercards.
9 Members of the series include Fast EtherLink 3c590/3c592/3c595/3c597
10 and the EtherLink XL 3c900 and 3c905 cards.
11
12 Problem reports and questions should be directed to
13 vortex@scyld.com
14
15 The author may be reached as becker@scyld.com, or C/O
16 Scyld Computing Corporation
17 410 Severn Ave., Suite 210
18 Annapolis MD 21403
19
20 Linux Kernel Additions:
21
22 0.99H+lk0.9 - David S. Miller - softnet, PCI DMA updates
23 0.99H+lk1.0 - Jeff Garzik <jgarzik@pobox.com>
24 Remove compatibility defines for kernel versions < 2.2.x.
25 Update for new 2.3.x module interface
26 LK1.1.2 (March 19, 2000)
27 * New PCI interface (jgarzik)
28
29 LK1.1.3 25 April 2000, Andrew Morton <andrewm@uow.edu.au>
30 - Merged with 3c575_cb.c
31 - Don't set RxComplete in boomerang interrupt enable reg
32 - spinlock in vortex_timer to protect mdio functions
33 - disable local interrupts around call to vortex_interrupt in
34 vortex_tx_timeout() (So vortex_interrupt can use spin_lock())
35 - Select window 3 in vortex_timer()'s write to Wn3_MAC_Ctrl
36 - In vortex_start_xmit(), move the lock to _after_ we've altered
37 vp->cur_tx and vp->tx_full. This defeats the race between
38 vortex_start_xmit() and vortex_interrupt which was identified
39 by Bogdan Costescu.
40 - Merged back support for six new cards from various sources
41 - Set vortex_have_pci if pci_module_init returns zero (fixes cardbus
42 insertion oops)
43 - Tell it that 3c905C has NWAY for 100bT autoneg
44 - Fix handling of SetStatusEnd in 'Too much work..' code, as
45 per 2.3.99's 3c575_cb (Dave Hinds).
46 - Split ISR into two for vortex & boomerang
47 - Fix MOD_INC/DEC races
48 - Handle resource allocation failures.
49 - Fix 3CCFE575CT LED polarity
50 - Make tx_interrupt_mitigation the default
51
52 LK1.1.4 25 April 2000, Andrew Morton <andrewm@uow.edu.au>
53 - Add extra TxReset to vortex_up() to fix 575_cb hotplug initialisation probs.
54 - Put vortex_info_tbl into __devinitdata
55 - In the vortex_error StatsFull HACK, disable stats in vp->intr_enable as well
56 as in the hardware.
57 - Increased the loop counter in issue_and_wait from 2,000 to 4,000.
58
59 LK1.1.5 28 April 2000, andrewm
60 - Added powerpc defines (John Daniel <jdaniel@etresoft.com> said these work...)
61 - Some extra diagnostics
62 - In vortex_error(), reset the Tx on maxCollisions. Otherwise most
63 chips usually get a Tx timeout.
64 - Added extra_reset module parm
65 - Replaced some inline timer manip with mod_timer
66 (Franois romieu <Francois.Romieu@nic.fr>)
67 - In vortex_up(), don't make Wn3_config initialisation dependent upon has_nway
68 (this came across from 3c575_cb).
69
70 LK1.1.6 06 Jun 2000, andrewm
71 - Backed out the PPC defines.
72 - Use del_timer_sync(), mod_timer().
73 - Fix wrapped ulong comparison in boomerang_rx()
74 - Add IS_TORNADO, use it to suppress 3c905C checksum error msg
75 (Donald Becker, I Lee Hetherington <ilh@sls.lcs.mit.edu>)
76 - Replace union wn3_config with BFINS/BFEXT manipulation for
77 sparc64 (Pete Zaitcev, Peter Jones)
78 - In vortex_error, do_tx_reset and vortex_tx_timeout(Vortex):
79 do a netif_wake_queue() to better recover from errors. (Anders Pedersen,
80 Donald Becker)
81 - Print a warning on out-of-memory (rate limited to 1 per 10 secs)
82 - Added two more Cardbus 575 NICs: 5b57 and 6564 (Paul Wagland)
83
84 LK1.1.7 2 Jul 2000 andrewm
85 - Better handling of shared IRQs
86 - Reset the transmitter on a Tx reclaim error
87 - Fixed crash under OOM during vortex_open() (Mark Hemment)
88 - Fix Rx cessation problem during OOM (help from Mark Hemment)
89 - The spinlocks around the mdio access were blocking interrupts for 300uS.
90 Fix all this to use spin_lock_bh() within mdio_read/write
91 - Only write to TxFreeThreshold if it's a boomerang - other NICs don't
92 have one.
93 - Added 802.3x MAC-layer flow control support
94
95 LK1.1.8 13 Aug 2000 andrewm
96 - Ignore request_region() return value - already reserved if Cardbus.
97 - Merged some additional Cardbus flags from Don's 0.99Qk
98 - Some fixes for 3c556 (Fred Maciel)
99 - Fix for EISA initialisation (Jan Rekorajski)
100 - Renamed MII_XCVR_PWR and EEPROM_230 to align with 3c575_cb and D. Becker's drivers
101 - Fixed MII_XCVR_PWR for 3CCFE575CT
102 - Added INVERT_LED_PWR, used it.
103 - Backed out the extra_reset stuff
104
105 LK1.1.9 12 Sep 2000 andrewm
106 - Backed out the tx_reset_resume flags. It was a no-op.
107 - In vortex_error, don't reset the Tx on txReclaim errors
108 - In vortex_error, don't reset the Tx on maxCollisions errors.
109 Hence backed out all the DownListPtr logic here.
110 - In vortex_error, give Tornado cards a partial TxReset on
111 maxCollisions (David Hinds). Defined MAX_COLLISION_RESET for this.
112 - Redid some driver flags and device names based on pcmcia_cs-3.1.20.
113 - Fixed a bug where, if vp->tx_full is set when the interface
114 is downed, it remains set when the interface is upped. Bad
115 things happen.
116
117 LK1.1.10 17 Sep 2000 andrewm
118 - Added EEPROM_8BIT for 3c555 (Fred Maciel)
119 - Added experimental support for the 3c556B Laptop Hurricane (Louis Gerbarg)
120 - Add HAS_NWAY to "3c900 Cyclone 10Mbps TPO"
121
122 LK1.1.11 13 Nov 2000 andrewm
123 - Dump MOD_INC/DEC_USE_COUNT, use SET_MODULE_OWNER
124
125 LK1.1.12 1 Jan 2001 andrewm (2.4.0-pre1)
126 - Call pci_enable_device before we request our IRQ (Tobias Ringstrom)
127 - Add 3c590 PCI latency timer hack to vortex_probe1 (from 0.99Ra)
128 - Added extended issue_and_wait for the 3c905CX.
129 - Look for an MII on PHY index 24 first (3c905CX oddity).
130 - Add HAS_NWAY to 3cSOHO100-TX (Brett Frankenberger)
131 - Don't free skbs we don't own on oom path in vortex_open().
132
133 LK1.1.13 27 Jan 2001
134 - Added explicit `medialock' flag so we can truly
135 lock the media type down with `options'.
136 - "check ioremap return and some tidbits" (Arnaldo Carvalho de Melo <acme@conectiva.com.br>)
137 - Added and used EEPROM_NORESET for 3c556B PM resumes.
138 - Fixed leakage of vp->rx_ring.
139 - Break out separate HAS_HWCKSM device capability flag.
140 - Kill vp->tx_full (ANK)
141 - Merge zerocopy fragment handling (ANK?)
142
143 LK1.1.14 15 Feb 2001
144 - Enable WOL. Can be turned on with `enable_wol' module option.
145 - EISA and PCI initialisation fixes (jgarzik, Manfred Spraul)
146 - If a device's internalconfig register reports it has NWAY,
147 use it, even if autoselect is enabled.
148
149 LK1.1.15 6 June 2001 akpm
150 - Prevent double counting of received bytes (Lars Christensen)
151 - Add ethtool support (jgarzik)
152 - Add module parm descriptions (Andrzej M. Krzysztofowicz)
153 - Implemented alloc_etherdev() API
154 - Special-case the 'Tx error 82' message.
155
156 LK1.1.16 18 July 2001 akpm
157 - Make NETIF_F_SG dependent upon nr_free_highpages(), not on CONFIG_HIGHMEM
158 - Lessen verbosity of bootup messages
159 - Fix WOL - use new PM API functions.
160 - Use netif_running() instead of vp->open in suspend/resume.
161 - Don't reset the interface logic on open/close/rmmod. It upsets
162 autonegotiation, and hence DHCP (from 0.99T).
163 - Back out EEPROM_NORESET flag because of the above (we do it for all
164 NICs).
165 - Correct 3c982 identification string
166 - Rename wait_for_completion() to issue_and_wait() to avoid completion.h
167 clash.
168
169 LK1.1.17 18Dec01 akpm
170 - PCI ID 9805 is a Python-T, not a dual-port Cyclone. Apparently.
171 And it has NWAY.
172 - Mask our advertised modes (vp->advertising) with our capabilities
173 (MII reg5) when deciding which duplex mode to use.
174 - Add `global_options' as default for options[]. Ditto global_enable_wol,
175 global_full_duplex.
176
177 LK1.1.18 01Jul02 akpm
178 - Fix for undocumented transceiver power-up bit on some 3c566B's
179 (Donald Becker, Rahul Karnik)
180
181 - See http://www.zip.com.au/~akpm/linux/#3c59x-2.3 for more details.
182 - Also see Documentation/networking/vortex.txt
183
184 LK1.1.19 10Nov02 Marc Zyngier <maz@wild-wind.fr.eu.org>
185 - EISA sysfs integration.
186*/
187
188/*
189 * FIXME: This driver _could_ support MTU changing, but doesn't. See Don's hamachi.c implementation
190 * as well as other drivers
191 *
192 * NOTE: If you make 'vortex_debug' a constant (#define vortex_debug 0) the driver shrinks by 2k
193 * due to dead code elimination. There will be some performance benefits from this due to
194 * elimination of all the tests and reduced cache footprint.
195 */
196
197
198#define DRV_NAME "3c59x"
199#define DRV_VERSION "LK1.1.19"
200#define DRV_RELDATE "10 Nov 2002"
201
202
203
204/* A few values that may be tweaked. */
205/* Keep the ring sizes a power of two for efficiency. */
206#define TX_RING_SIZE 16
207#define RX_RING_SIZE 32
208#define PKT_BUF_SZ 1536 /* Size of each temporary Rx buffer.*/
209
210/* "Knobs" that adjust features and parameters. */
211/* Set the copy breakpoint for the copy-only-tiny-frames scheme.
212 Setting to > 1512 effectively disables this feature. */
213#ifndef __arm__
214static int rx_copybreak = 200;
215#else
216/* ARM systems perform better by disregarding the bus-master
217 transfer capability of these cards. -- rmk */
218static int rx_copybreak = 1513;
219#endif
220/* Allow setting MTU to a larger size, bypassing the normal ethernet setup. */
221static const int mtu = 1500;
222/* Maximum events (Rx packets, etc.) to handle at each interrupt. */
223static int max_interrupt_work = 32;
224/* Tx timeout interval (millisecs) */
225static int watchdog = 5000;
226
227/* Allow aggregation of Tx interrupts. Saves CPU load at the cost
228 * of possible Tx stalls if the system is blocking interrupts
229 * somewhere else. Undefine this to disable.
230 */
231#define tx_interrupt_mitigation 1
232
233/* Put out somewhat more debugging messages. (0: no msg, 1 minimal .. 6). */
234#define vortex_debug debug
235#ifdef VORTEX_DEBUG
236static int vortex_debug = VORTEX_DEBUG;
237#else
238static int vortex_debug = 1;
239#endif
240
241#include <linux/config.h>
242#include <linux/module.h>
243#include <linux/kernel.h>
244#include <linux/string.h>
245#include <linux/timer.h>
246#include <linux/errno.h>
247#include <linux/in.h>
248#include <linux/ioport.h>
249#include <linux/slab.h>
250#include <linux/interrupt.h>
251#include <linux/pci.h>
252#include <linux/mii.h>
253#include <linux/init.h>
254#include <linux/netdevice.h>
255#include <linux/etherdevice.h>
256#include <linux/skbuff.h>
257#include <linux/ethtool.h>
258#include <linux/highmem.h>
259#include <linux/eisa.h>
260#include <linux/bitops.h>
261#include <asm/irq.h> /* For NR_IRQS only. */
262#include <asm/io.h>
263#include <asm/uaccess.h>
264
265/* Kernel compatibility defines, some common to David Hinds' PCMCIA package.
266 This is only in the support-all-kernels source code. */
267
268#define RUN_AT(x) (jiffies + (x))
269
270#include <linux/delay.h>
271
272
273static char version[] __devinitdata =
274DRV_NAME ": Donald Becker and others. www.scyld.com/network/vortex.html\n";
275
276MODULE_AUTHOR("Donald Becker <becker@scyld.com>");
277MODULE_DESCRIPTION("3Com 3c59x/3c9xx ethernet driver "
278 DRV_VERSION " " DRV_RELDATE);
279MODULE_LICENSE("GPL");
280MODULE_VERSION(DRV_VERSION);
281
282
283/* Operational parameter that usually are not changed. */
284
285/* The Vortex size is twice that of the original EtherLinkIII series: the
286 runtime register window, window 1, is now always mapped in.
287 The Boomerang size is twice as large as the Vortex -- it has additional
288 bus master control registers. */
289#define VORTEX_TOTAL_SIZE 0x20
290#define BOOMERANG_TOTAL_SIZE 0x40
291
292/* Set iff a MII transceiver on any interface requires mdio preamble.
293 This only set with the original DP83840 on older 3c905 boards, so the extra
294 code size of a per-interface flag is not worthwhile. */
295static char mii_preamble_required;
296
297#define PFX DRV_NAME ": "
298
299
300
301/*
302 Theory of Operation
303
304I. Board Compatibility
305
306This device driver is designed for the 3Com FastEtherLink and FastEtherLink
307XL, 3Com's PCI to 10/100baseT adapters. It also works with the 10Mbs
308versions of the FastEtherLink cards. The supported product IDs are
309 3c590, 3c592, 3c595, 3c597, 3c900, 3c905
310
311The related ISA 3c515 is supported with a separate driver, 3c515.c, included
312with the kernel source or available from
313 cesdis.gsfc.nasa.gov:/pub/linux/drivers/3c515.html
314
315II. Board-specific settings
316
317PCI bus devices are configured by the system at boot time, so no jumpers
318need to be set on the board. The system BIOS should be set to assign the
319PCI INTA signal to an otherwise unused system IRQ line.
320
321The EEPROM settings for media type and forced-full-duplex are observed.
322The EEPROM media type should be left at the default "autoselect" unless using
32310base2 or AUI connections which cannot be reliably detected.
324
325III. Driver operation
326
327The 3c59x series use an interface that's very similar to the previous 3c5x9
328series. The primary interface is two programmed-I/O FIFOs, with an
329alternate single-contiguous-region bus-master transfer (see next).
330
331The 3c900 "Boomerang" series uses a full-bus-master interface with separate
332lists of transmit and receive descriptors, similar to the AMD LANCE/PCnet,
333DEC Tulip and Intel Speedo3. The first chip version retains a compatible
334programmed-I/O interface that has been removed in 'B' and subsequent board
335revisions.
336
337One extension that is advertised in a very large font is that the adapters
338are capable of being bus masters. On the Vortex chip this capability was
339only for a single contiguous region making it far less useful than the full
340bus master capability. There is a significant performance impact of taking
341an extra interrupt or polling for the completion of each transfer, as well
342as difficulty sharing the single transfer engine between the transmit and
343receive threads. Using DMA transfers is a win only with large blocks or
344with the flawed versions of the Intel Orion motherboard PCI controller.
345
346The Boomerang chip's full-bus-master interface is useful, and has the
347currently-unused advantages over other similar chips that queued transmit
348packets may be reordered and receive buffer groups are associated with a
349single frame.
350
351With full-bus-master support, this driver uses a "RX_COPYBREAK" scheme.
352Rather than a fixed intermediate receive buffer, this scheme allocates
353full-sized skbuffs as receive buffers. The value RX_COPYBREAK is used as
354the copying breakpoint: it is chosen to trade-off the memory wasted by
355passing the full-sized skbuff to the queue layer for all frames vs. the
356copying cost of copying a frame to a correctly-sized skbuff.
357
358IIIC. Synchronization
359The driver runs as two independent, single-threaded flows of control. One
360is the send-packet routine, which enforces single-threaded use by the
361dev->tbusy flag. The other thread is the interrupt handler, which is single
362threaded by the hardware and other software.
363
364IV. Notes
365
366Thanks to Cameron Spitzer and Terry Murphy of 3Com for providing development
3673c590, 3c595, and 3c900 boards.
368The name "Vortex" is the internal 3Com project name for the PCI ASIC, and
369the EISA version is called "Demon". According to Terry these names come
370from rides at the local amusement park.
371
372The new chips support both ethernet (1.5K) and FDDI (4.5K) packet sizes!
373This driver only supports ethernet packets because of the skbuff allocation
374limit of 4K.
375*/
376
377/* This table drives the PCI probe routines. It's mostly boilerplate in all
378 of the drivers, and will likely be provided by some future kernel.
379*/
380enum pci_flags_bit {
381 PCI_USES_IO=1, PCI_USES_MEM=2, PCI_USES_MASTER=4,
382 PCI_ADDR0=0x10<<0, PCI_ADDR1=0x10<<1, PCI_ADDR2=0x10<<2, PCI_ADDR3=0x10<<3,
383};
384
385enum { IS_VORTEX=1, IS_BOOMERANG=2, IS_CYCLONE=4, IS_TORNADO=8,
386 EEPROM_8BIT=0x10, /* AKPM: Uses 0x230 as the base bitmaps for EEPROM reads */
387 HAS_PWR_CTRL=0x20, HAS_MII=0x40, HAS_NWAY=0x80, HAS_CB_FNS=0x100,
388 INVERT_MII_PWR=0x200, INVERT_LED_PWR=0x400, MAX_COLLISION_RESET=0x800,
389 EEPROM_OFFSET=0x1000, HAS_HWCKSM=0x2000, WNO_XCVR_PWR=0x4000,
390 EXTRA_PREAMBLE=0x8000, EEPROM_RESET=0x10000, };
391
392enum vortex_chips {
393 CH_3C590 = 0,
394 CH_3C592,
395 CH_3C597,
396 CH_3C595_1,
397 CH_3C595_2,
398
399 CH_3C595_3,
400 CH_3C900_1,
401 CH_3C900_2,
402 CH_3C900_3,
403 CH_3C900_4,
404
405 CH_3C900_5,
406 CH_3C900B_FL,
407 CH_3C905_1,
408 CH_3C905_2,
409 CH_3C905B_1,
410
411 CH_3C905B_2,
412 CH_3C905B_FX,
413 CH_3C905C,
414 CH_3C9202,
415 CH_3C980,
416 CH_3C9805,
417
418 CH_3CSOHO100_TX,
419 CH_3C555,
420 CH_3C556,
421 CH_3C556B,
422 CH_3C575,
423
424 CH_3C575_1,
425 CH_3CCFE575,
426 CH_3CCFE575CT,
427 CH_3CCFE656,
428 CH_3CCFEM656,
429
430 CH_3CCFEM656_1,
431 CH_3C450,
432 CH_3C920,
433 CH_3C982A,
434 CH_3C982B,
435
436 CH_905BT4,
437 CH_920B_EMB_WNM,
438};
439
440
441/* note: this array directly indexed by above enums, and MUST
442 * be kept in sync with both the enums above, and the PCI device
443 * table below
444 */
445static struct vortex_chip_info {
446 const char *name;
447 int flags;
448 int drv_flags;
449 int io_size;
450} vortex_info_tbl[] __devinitdata = {
451 {"3c590 Vortex 10Mbps",
452 PCI_USES_IO|PCI_USES_MASTER, IS_VORTEX, 32, },
453 {"3c592 EISA 10Mbps Demon/Vortex", /* AKPM: from Don's 3c59x_cb.c 0.49H */
454 PCI_USES_IO|PCI_USES_MASTER, IS_VORTEX, 32, },
455 {"3c597 EISA Fast Demon/Vortex", /* AKPM: from Don's 3c59x_cb.c 0.49H */
456 PCI_USES_IO|PCI_USES_MASTER, IS_VORTEX, 32, },
457 {"3c595 Vortex 100baseTx",
458 PCI_USES_IO|PCI_USES_MASTER, IS_VORTEX, 32, },
459 {"3c595 Vortex 100baseT4",
460 PCI_USES_IO|PCI_USES_MASTER, IS_VORTEX, 32, },
461
462 {"3c595 Vortex 100base-MII",
463 PCI_USES_IO|PCI_USES_MASTER, IS_VORTEX, 32, },
464 {"3c900 Boomerang 10baseT",
465 PCI_USES_IO|PCI_USES_MASTER, IS_BOOMERANG|EEPROM_RESET, 64, },
466 {"3c900 Boomerang 10Mbps Combo",
467 PCI_USES_IO|PCI_USES_MASTER, IS_BOOMERANG|EEPROM_RESET, 64, },
468 {"3c900 Cyclone 10Mbps TPO", /* AKPM: from Don's 0.99M */
469 PCI_USES_IO|PCI_USES_MASTER, IS_CYCLONE|HAS_HWCKSM, 128, },
470 {"3c900 Cyclone 10Mbps Combo",
471 PCI_USES_IO|PCI_USES_MASTER, IS_CYCLONE|HAS_HWCKSM, 128, },
472
473 {"3c900 Cyclone 10Mbps TPC", /* AKPM: from Don's 0.99M */
474 PCI_USES_IO|PCI_USES_MASTER, IS_CYCLONE|HAS_HWCKSM, 128, },
475 {"3c900B-FL Cyclone 10base-FL",
476 PCI_USES_IO|PCI_USES_MASTER, IS_CYCLONE|HAS_HWCKSM, 128, },
477 {"3c905 Boomerang 100baseTx",
478 PCI_USES_IO|PCI_USES_MASTER, IS_BOOMERANG|HAS_MII|EEPROM_RESET, 64, },
479 {"3c905 Boomerang 100baseT4",
480 PCI_USES_IO|PCI_USES_MASTER, IS_BOOMERANG|HAS_MII|EEPROM_RESET, 64, },
481 {"3c905B Cyclone 100baseTx",
482 PCI_USES_IO|PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_HWCKSM|EXTRA_PREAMBLE, 128, },
483
484 {"3c905B Cyclone 10/100/BNC",
485 PCI_USES_IO|PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_HWCKSM, 128, },
486 {"3c905B-FX Cyclone 100baseFx",
487 PCI_USES_IO|PCI_USES_MASTER, IS_CYCLONE|HAS_HWCKSM, 128, },
488 {"3c905C Tornado",
489 PCI_USES_IO|PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|HAS_HWCKSM|EXTRA_PREAMBLE, 128, },
490 {"3c920B-EMB-WNM (ATI Radeon 9100 IGP)",
491 PCI_USES_IO|PCI_USES_MASTER, IS_TORNADO|HAS_MII|HAS_HWCKSM, 128, },
492 {"3c980 Cyclone",
493 PCI_USES_IO|PCI_USES_MASTER, IS_CYCLONE|HAS_HWCKSM, 128, },
494
495 {"3c980C Python-T",
496 PCI_USES_IO|PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_HWCKSM, 128, },
497 {"3cSOHO100-TX Hurricane",
498 PCI_USES_IO|PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_HWCKSM, 128, },
499 {"3c555 Laptop Hurricane",
500 PCI_USES_IO|PCI_USES_MASTER, IS_CYCLONE|EEPROM_8BIT|HAS_HWCKSM, 128, },
501 {"3c556 Laptop Tornado",
502 PCI_USES_IO|PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|EEPROM_8BIT|HAS_CB_FNS|INVERT_MII_PWR|
503 HAS_HWCKSM, 128, },
504 {"3c556B Laptop Hurricane",
505 PCI_USES_IO|PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|EEPROM_OFFSET|HAS_CB_FNS|INVERT_MII_PWR|
506 WNO_XCVR_PWR|HAS_HWCKSM, 128, },
507
508 {"3c575 [Megahertz] 10/100 LAN CardBus",
509 PCI_USES_IO|PCI_USES_MASTER, IS_BOOMERANG|HAS_MII|EEPROM_8BIT, 128, },
510 {"3c575 Boomerang CardBus",
511 PCI_USES_IO|PCI_USES_MASTER, IS_BOOMERANG|HAS_MII|EEPROM_8BIT, 128, },
512 {"3CCFE575BT Cyclone CardBus",
513 PCI_USES_IO|PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_CB_FNS|EEPROM_8BIT|
514 INVERT_LED_PWR|HAS_HWCKSM, 128, },
515 {"3CCFE575CT Tornado CardBus",
516 PCI_USES_IO|PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|HAS_CB_FNS|EEPROM_8BIT|INVERT_MII_PWR|
517 MAX_COLLISION_RESET|HAS_HWCKSM, 128, },
518 {"3CCFE656 Cyclone CardBus",
519 PCI_USES_IO|PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_CB_FNS|EEPROM_8BIT|INVERT_MII_PWR|
520 INVERT_LED_PWR|HAS_HWCKSM, 128, },
521
522 {"3CCFEM656B Cyclone+Winmodem CardBus",
523 PCI_USES_IO|PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_CB_FNS|EEPROM_8BIT|INVERT_MII_PWR|
524 INVERT_LED_PWR|HAS_HWCKSM, 128, },
525 {"3CXFEM656C Tornado+Winmodem CardBus", /* From pcmcia-cs-3.1.5 */
526 PCI_USES_IO|PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|HAS_CB_FNS|EEPROM_8BIT|INVERT_MII_PWR|
527 MAX_COLLISION_RESET|HAS_HWCKSM, 128, },
528 {"3c450 HomePNA Tornado", /* AKPM: from Don's 0.99Q */
529 PCI_USES_IO|PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|HAS_HWCKSM, 128, },
530 {"3c920 Tornado",
531 PCI_USES_IO|PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|HAS_HWCKSM, 128, },
532 {"3c982 Hydra Dual Port A",
533 PCI_USES_IO|PCI_USES_MASTER, IS_TORNADO|HAS_HWCKSM|HAS_NWAY, 128, },
534
535 {"3c982 Hydra Dual Port B",
536 PCI_USES_IO|PCI_USES_MASTER, IS_TORNADO|HAS_HWCKSM|HAS_NWAY, 128, },
537 {"3c905B-T4",
538 PCI_USES_IO|PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_HWCKSM|EXTRA_PREAMBLE, 128, },
539 {"3c920B-EMB-WNM Tornado",
540 PCI_USES_IO|PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|HAS_HWCKSM, 128, },
541
542 {NULL,}, /* NULL terminated list. */
543};
544
545
546static struct pci_device_id vortex_pci_tbl[] = {
547 { 0x10B7, 0x5900, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C590 },
548 { 0x10B7, 0x5920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C592 },
549 { 0x10B7, 0x5970, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C597 },
550 { 0x10B7, 0x5950, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C595_1 },
551 { 0x10B7, 0x5951, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C595_2 },
552
553 { 0x10B7, 0x5952, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C595_3 },
554 { 0x10B7, 0x9000, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C900_1 },
555 { 0x10B7, 0x9001, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C900_2 },
556 { 0x10B7, 0x9004, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C900_3 },
557 { 0x10B7, 0x9005, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C900_4 },
558
559 { 0x10B7, 0x9006, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C900_5 },
560 { 0x10B7, 0x900A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C900B_FL },
561 { 0x10B7, 0x9050, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905_1 },
562 { 0x10B7, 0x9051, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905_2 },
563 { 0x10B7, 0x9055, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905B_1 },
564
565 { 0x10B7, 0x9058, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905B_2 },
566 { 0x10B7, 0x905A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905B_FX },
567 { 0x10B7, 0x9200, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905C },
568 { 0x10B7, 0x9202, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C9202 },
569 { 0x10B7, 0x9800, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C980 },
570 { 0x10B7, 0x9805, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C9805 },
571
572 { 0x10B7, 0x7646, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3CSOHO100_TX },
573 { 0x10B7, 0x5055, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C555 },
574 { 0x10B7, 0x6055, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C556 },
575 { 0x10B7, 0x6056, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C556B },
576 { 0x10B7, 0x5b57, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C575 },
577
578 { 0x10B7, 0x5057, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C575_1 },
579 { 0x10B7, 0x5157, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3CCFE575 },
580 { 0x10B7, 0x5257, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3CCFE575CT },
581 { 0x10B7, 0x6560, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3CCFE656 },
582 { 0x10B7, 0x6562, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3CCFEM656 },
583
584 { 0x10B7, 0x6564, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3CCFEM656_1 },
585 { 0x10B7, 0x4500, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C450 },
586 { 0x10B7, 0x9201, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C920 },
587 { 0x10B7, 0x1201, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C982A },
588 { 0x10B7, 0x1202, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C982B },
589
590 { 0x10B7, 0x9056, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_905BT4 },
591 { 0x10B7, 0x9210, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_920B_EMB_WNM },
592
593 {0,} /* 0 terminated list. */
594};
595MODULE_DEVICE_TABLE(pci, vortex_pci_tbl);
596
597
598/* Operational definitions.
599 These are not used by other compilation units and thus are not
600 exported in a ".h" file.
601
602 First the windows. There are eight register windows, with the command
603 and status registers available in each.
604 */
62afe595 605#define EL3WINDOW(win_num) iowrite16(SelectWindow + (win_num), ioaddr + EL3_CMD)
1da177e4
LT		 606#define EL3_CMD 0x0e
607#define EL3_STATUS 0x0e
608
609/* The top five bits written to EL3_CMD are a command, the lower
610 11 bits are the parameter, if applicable.
611 Note that 11 parameters bits was fine for ethernet, but the new chip
612 can handle FDDI length frames (~4500 octets) and now parameters count
613 32-bit 'Dwords' rather than octets. */
614
615enum vortex_cmd {
616 TotalReset = 0<<11, SelectWindow = 1<<11, StartCoax = 2<<11,
617 RxDisable = 3<<11, RxEnable = 4<<11, RxReset = 5<<11,
618 UpStall = 6<<11, UpUnstall = (6<<11)+1,
619 DownStall = (6<<11)+2, DownUnstall = (6<<11)+3,
620 RxDiscard = 8<<11, TxEnable = 9<<11, TxDisable = 10<<11, TxReset = 11<<11,
621 FakeIntr = 12<<11, AckIntr = 13<<11, SetIntrEnb = 14<<11,
622 SetStatusEnb = 15<<11, SetRxFilter = 16<<11, SetRxThreshold = 17<<11,
623 SetTxThreshold = 18<<11, SetTxStart = 19<<11,
624 StartDMAUp = 20<<11, StartDMADown = (20<<11)+1, StatsEnable = 21<<11,
625 StatsDisable = 22<<11, StopCoax = 23<<11, SetFilterBit = 25<<11,};
626
627/* The SetRxFilter command accepts the following classes: */
628enum RxFilter {
629 RxStation = 1, RxMulticast = 2, RxBroadcast = 4, RxProm = 8 };
630
631/* Bits in the general status register. */
632enum vortex_status {
633 IntLatch = 0x0001, HostError = 0x0002, TxComplete = 0x0004,
634 TxAvailable = 0x0008, RxComplete = 0x0010, RxEarly = 0x0020,
635 IntReq = 0x0040, StatsFull = 0x0080,
636 DMADone = 1<<8, DownComplete = 1<<9, UpComplete = 1<<10,
637 DMAInProgress = 1<<11, /* DMA controller is still busy.*/
638 CmdInProgress = 1<<12, /* EL3_CMD is still busy.*/
639};
640
641/* Register window 1 offsets, the window used in normal operation.
642 On the Vortex this window is always mapped at offsets 0x10-0x1f. */
643enum Window1 {
644 TX_FIFO = 0x10, RX_FIFO = 0x10, RxErrors = 0x14,
645 RxStatus = 0x18, Timer=0x1A, TxStatus = 0x1B,
646 TxFree = 0x1C, /* Remaining free bytes in Tx buffer. */
647};
648enum Window0 {
649 Wn0EepromCmd = 10, /* Window 0: EEPROM command register. */
650 Wn0EepromData = 12, /* Window 0: EEPROM results register. */
651 IntrStatus=0x0E, /* Valid in all windows. */
652};
653enum Win0_EEPROM_bits {
654 EEPROM_Read = 0x80, EEPROM_WRITE = 0x40, EEPROM_ERASE = 0xC0,
655 EEPROM_EWENB = 0x30, /* Enable erasing/writing for 10 msec. */
656 EEPROM_EWDIS = 0x00, /* Disable EWENB before 10 msec timeout. */
657};
658/* EEPROM locations. */
659enum eeprom_offset {
660 PhysAddr01=0, PhysAddr23=1, PhysAddr45=2, ModelID=3,
661 EtherLink3ID=7, IFXcvrIO=8, IRQLine=9,
662 NodeAddr01=10, NodeAddr23=11, NodeAddr45=12,
663 DriverTune=13, Checksum=15};
664
665enum Window2 { /* Window 2. */
666 Wn2_ResetOptions=12,
667};
668enum Window3 { /* Window 3: MAC/config bits. */
669 Wn3_Config=0, Wn3_MaxPktSize=4, Wn3_MAC_Ctrl=6, Wn3_Options=8,
670};
671
672#define BFEXT(value, offset, bitcount) \
673 ((((unsigned long)(value)) >> (offset)) & ((1 << (bitcount)) - 1))
674
675#define BFINS(lhs, rhs, offset, bitcount) \
676 (((lhs) & ~((((1 << (bitcount)) - 1)) << (offset))) | \
677 (((rhs) & ((1 << (bitcount)) - 1)) << (offset)))
678
679#define RAM_SIZE(v) BFEXT(v, 0, 3)
680#define RAM_WIDTH(v) BFEXT(v, 3, 1)
681#define RAM_SPEED(v) BFEXT(v, 4, 2)
682#define ROM_SIZE(v) BFEXT(v, 6, 2)
683#define RAM_SPLIT(v) BFEXT(v, 16, 2)
684#define XCVR(v) BFEXT(v, 20, 4)
685#define AUTOSELECT(v) BFEXT(v, 24, 1)
686
687enum Window4 { /* Window 4: Xcvr/media bits. */
688 Wn4_FIFODiag = 4, Wn4_NetDiag = 6, Wn4_PhysicalMgmt=8, Wn4_Media = 10,
689};
690enum Win4_Media_bits {
691 Media_SQE = 0x0008, /* Enable SQE error counting for AUI. */
692 Media_10TP = 0x00C0, /* Enable link beat and jabber for 10baseT. */
693 Media_Lnk = 0x0080, /* Enable just link beat for 100TX/100FX. */
694 Media_LnkBeat = 0x0800,
695};
696enum Window7 { /* Window 7: Bus Master control. */
697 Wn7_MasterAddr = 0, Wn7_VlanEtherType=4, Wn7_MasterLen = 6,
698 Wn7_MasterStatus = 12,
699};
700/* Boomerang bus master control registers. */
701enum MasterCtrl {
702 PktStatus = 0x20, DownListPtr = 0x24, FragAddr = 0x28, FragLen = 0x2c,
703 TxFreeThreshold = 0x2f, UpPktStatus = 0x30, UpListPtr = 0x38,
704};
705
706/* The Rx and Tx descriptor lists.
707 Caution Alpha hackers: these types are 32 bits! Note also the 8 byte
708 alignment contraint on tx_ring[] and rx_ring[]. */
709#define LAST_FRAG 0x80000000 /* Last Addr/Len pair in descriptor. */
710#define DN_COMPLETE 0x00010000 /* This packet has been downloaded */
711struct boom_rx_desc {
712 u32 next; /* Last entry points to 0. */
713 s32 status;
714 u32 addr; /* Up to 63 addr/len pairs possible. */
715 s32 length; /* Set LAST_FRAG to indicate last pair. */
716};
717/* Values for the Rx status entry. */
718enum rx_desc_status {
719 RxDComplete=0x00008000, RxDError=0x4000,
720 /* See boomerang_rx() for actual error bits */
721 IPChksumErr=1<<25, TCPChksumErr=1<<26, UDPChksumErr=1<<27,
722 IPChksumValid=1<<29, TCPChksumValid=1<<30, UDPChksumValid=1<<31,
723};
724
725#ifdef MAX_SKB_FRAGS
726#define DO_ZEROCOPY 1
727#else
728#define DO_ZEROCOPY 0
729#endif
730
731struct boom_tx_desc {
732 u32 next; /* Last entry points to 0. */
733 s32 status; /* bits 0:12 length, others see below. */
734#if DO_ZEROCOPY
735 struct {
736 u32 addr;
737 s32 length;
738 } frag[1+MAX_SKB_FRAGS];
739#else
740 u32 addr;
741 s32 length;
742#endif
743};
744
745/* Values for the Tx status entry. */
746enum tx_desc_status {
747 CRCDisable=0x2000, TxDComplete=0x8000,
748 AddIPChksum=0x02000000, AddTCPChksum=0x04000000, AddUDPChksum=0x08000000,
749 TxIntrUploaded=0x80000000, /* IRQ when in FIFO, but maybe not sent. */
750};
751
752/* Chip features we care about in vp->capabilities, read from the EEPROM. */
753enum ChipCaps { CapBusMaster=0x20, CapPwrMgmt=0x2000 };
754
755struct vortex_extra_stats {
8d1d0340
SK		 756 unsigned long tx_deferred;
757 unsigned long tx_max_collisions;
758 unsigned long tx_multiple_collisions;
759 unsigned long tx_single_collisions;
760 unsigned long rx_bad_ssd;
1da177e4
LT		 761};
762
763struct vortex_private {
764 /* The Rx and Tx rings should be quad-word-aligned. */
765 struct boom_rx_desc* rx_ring;
766 struct boom_tx_desc* tx_ring;
767 dma_addr_t rx_ring_dma;
768 dma_addr_t tx_ring_dma;
769 /* The addresses of transmit- and receive-in-place skbuffs. */
770 struct sk_buff* rx_skbuff[RX_RING_SIZE];
771 struct sk_buff* tx_skbuff[TX_RING_SIZE];
772 unsigned int cur_rx, cur_tx; /* The next free ring entry */
773 unsigned int dirty_rx, dirty_tx; /* The ring entries to be free()ed. */
774 struct net_device_stats stats; /* Generic stats */
775 struct vortex_extra_stats xstats; /* NIC-specific extra stats */
776 struct sk_buff *tx_skb; /* Packet being eaten by bus master ctrl. */
777 dma_addr_t tx_skb_dma; /* Allocated DMA address for bus master ctrl DMA. */
778
779 /* PCI configuration space information. */
780 struct device *gendev;
62afe595
JL		 781 void __iomem *ioaddr; /* IO address space */
782 void __iomem *cb_fn_base; /* CardBus function status addr space. */
1da177e4
LT		 783
784 /* Some values here only for performance evaluation and path-coverage */
785 int rx_nocopy, rx_copy, queued_packet, rx_csumhits;
786 int card_idx;
787
788 /* The remainder are related to chip state, mostly media selection. */
789 struct timer_list timer; /* Media selection timer. */
790 struct timer_list rx_oom_timer; /* Rx skb allocation retry timer */
791 int options; /* User-settable misc. driver options. */
792 unsigned int media_override:4, /* Passed-in media type. */
793 default_media:4, /* Read from the EEPROM/Wn3_Config. */
794 full_duplex:1, force_fd:1, autoselect:1,
795 bus_master:1, /* Vortex can only do a fragment bus-m. */
796 full_bus_master_tx:1, full_bus_master_rx:2, /* Boomerang */
797 flow_ctrl:1, /* Use 802.3x flow control (PAUSE only) */
798 partner_flow_ctrl:1, /* Partner supports flow control */
799 has_nway:1,
800 enable_wol:1, /* Wake-on-LAN is enabled */
801 pm_state_valid:1, /* pci_dev->saved_config_space has sane contents */
802 open:1,
803 medialock:1,
804 must_free_region:1, /* Flag: if zero, Cardbus owns the I/O region */
805 large_frames:1; /* accept large frames */
806 int drv_flags;
807 u16 status_enable;
808 u16 intr_enable;
809 u16 available_media; /* From Wn3_Options. */
810 u16 capabilities, info1, info2; /* Various, from EEPROM. */
811 u16 advertising; /* NWay media advertisement */
812 unsigned char phys[2]; /* MII device addresses. */
813 u16 deferred; /* Resend these interrupts when we
814 * bale from the ISR */
815 u16 io_size; /* Size of PCI region (for release_region) */
816 spinlock_t lock; /* Serialise access to device & its vortex_private */
817 struct mii_if_info mii; /* MII lib hooks/info */
818};
819
820#ifdef CONFIG_PCI
821#define DEVICE_PCI(dev) (((dev)->bus == &pci_bus_type) ? to_pci_dev((dev)) : NULL)
822#else
823#define DEVICE_PCI(dev) NULL
824#endif
825
826#define VORTEX_PCI(vp) (((vp)->gendev) ? DEVICE_PCI((vp)->gendev) : NULL)
827
828#ifdef CONFIG_EISA
829#define DEVICE_EISA(dev) (((dev)->bus == &eisa_bus_type) ? to_eisa_device((dev)) : NULL)
830#else
831#define DEVICE_EISA(dev) NULL
832#endif
833
834#define VORTEX_EISA(vp) (((vp)->gendev) ? DEVICE_EISA((vp)->gendev) : NULL)
835
836/* The action to take with a media selection timer tick.
837 Note that we deviate from the 3Com order by checking 10base2 before AUI.
838 */
839enum xcvr_types {
840 XCVR_10baseT=0, XCVR_AUI, XCVR_10baseTOnly, XCVR_10base2, XCVR_100baseTx,
841 XCVR_100baseFx, XCVR_MII=6, XCVR_NWAY=8, XCVR_ExtMII=9, XCVR_Default=10,
842};
843
f71e1309 844static const struct media_table {
1da177e4
LT		 845 char *name;
846 unsigned int media_bits:16, /* Bits to set in Wn4_Media register. */
847 mask:8, /* The transceiver-present bit in Wn3_Config.*/
848 next:8; /* The media type to try next. */
849 int wait; /* Time before we check media status. */
850} media_tbl[] = {
851 { "10baseT", Media_10TP,0x08, XCVR_10base2, (14*HZ)/10},
852 { "10Mbs AUI", Media_SQE, 0x20, XCVR_Default, (1*HZ)/10},
853 { "undefined", 0, 0x80, XCVR_10baseT, 10000},
854 { "10base2", 0, 0x10, XCVR_AUI, (1*HZ)/10},
855 { "100baseTX", Media_Lnk, 0x02, XCVR_100baseFx, (14*HZ)/10},
856 { "100baseFX", Media_Lnk, 0x04, XCVR_MII, (14*HZ)/10},
857 { "MII", 0, 0x41, XCVR_10baseT, 3*HZ },
858 { "undefined", 0, 0x01, XCVR_10baseT, 10000},
859 { "Autonegotiate", 0, 0x41, XCVR_10baseT, 3*HZ},
860 { "MII-External", 0, 0x41, XCVR_10baseT, 3*HZ },
861 { "Default", 0, 0xFF, XCVR_10baseT, 10000},
862};
863
864static struct {
865 const char str[ETH_GSTRING_LEN];
866} ethtool_stats_keys[] = {
867 { "tx_deferred" },
8d1d0340 868 { "tx_max_collisions" },
1da177e4 869 { "tx_multiple_collisions" },
8d1d0340 870 { "tx_single_collisions" },
1da177e4
LT		 871 { "rx_bad_ssd" },
872};
873
874/* number of ETHTOOL_GSTATS u64's */
8d1d0340 875#define VORTEX_NUM_STATS 5
1da177e4 876
62afe595 877static int vortex_probe1(struct device *gendev, void __iomem *ioaddr, int irq,
1da177e4
LT		 878 int chip_idx, int card_idx);
879static void vortex_up(struct net_device *dev);
880static void vortex_down(struct net_device *dev, int final);
881static int vortex_open(struct net_device *dev);
62afe595 882static void mdio_sync(void __iomem *ioaddr, int bits);
1da177e4
LT		 883static int mdio_read(struct net_device *dev, int phy_id, int location);
884static void mdio_write(struct net_device *vp, int phy_id, int location, int value);
885static void vortex_timer(unsigned long arg);
886static void rx_oom_timer(unsigned long arg);
887static int vortex_start_xmit(struct sk_buff *skb, struct net_device *dev);
888static int boomerang_start_xmit(struct sk_buff *skb, struct net_device *dev);
889static int vortex_rx(struct net_device *dev);
890static int boomerang_rx(struct net_device *dev);
891static irqreturn_t vortex_interrupt(int irq, void *dev_id, struct pt_regs *regs);
892static irqreturn_t boomerang_interrupt(int irq, void *dev_id, struct pt_regs *regs);
893static int vortex_close(struct net_device *dev);
894static void dump_tx_ring(struct net_device *dev);
62afe595 895static void update_stats(void __iomem *ioaddr, struct net_device *dev);
1da177e4
LT		 896static struct net_device_stats *vortex_get_stats(struct net_device *dev);
897static void set_rx_mode(struct net_device *dev);
898#ifdef CONFIG_PCI
899static int vortex_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
900#endif
901static void vortex_tx_timeout(struct net_device *dev);
902static void acpi_set_WOL(struct net_device *dev);
903static struct ethtool_ops vortex_ethtool_ops;
904static void set_8021q_mode(struct net_device *dev, int enable);
905
906\f
907/* This driver uses 'options' to pass the media type, full-duplex flag, etc. */
908/* Option count limit only -- unlimited interfaces are supported. */
909#define MAX_UNITS 8
9954ab7f
JL		 910static int options[MAX_UNITS] = { [0 ... MAX_UNITS-1] = -1 };
911static int full_duplex[MAX_UNITS] = {[0 ... MAX_UNITS-1] = -1 };
912static int hw_checksums[MAX_UNITS] = {[0 ... MAX_UNITS-1] = -1 };
913static int flow_ctrl[MAX_UNITS] = {[0 ... MAX_UNITS-1] = -1 };
914static int enable_wol[MAX_UNITS] = {[0 ... MAX_UNITS-1] = -1 };
900fd17d 915static int use_mmio[MAX_UNITS] = {[0 ... MAX_UNITS-1] = -1 };
1da177e4
LT		 916static int global_options = -1;
917static int global_full_duplex = -1;
918static int global_enable_wol = -1;
900fd17d 919static int global_use_mmio = -1;
1da177e4
LT		 920
921/* #define dev_alloc_skb dev_alloc_skb_debug */
922
923/* Variables to work-around the Compaq PCI BIOS32 problem. */
924static int compaq_ioaddr, compaq_irq, compaq_device_id = 0x5900;
925static struct net_device *compaq_net_device;
926
927static int vortex_cards_found;
928
929module_param(debug, int, 0);
930module_param(global_options, int, 0);
931module_param_array(options, int, NULL, 0);
932module_param(global_full_duplex, int, 0);
933module_param_array(full_duplex, int, NULL, 0);
934module_param_array(hw_checksums, int, NULL, 0);
935module_param_array(flow_ctrl, int, NULL, 0);
936module_param(global_enable_wol, int, 0);
937module_param_array(enable_wol, int, NULL, 0);
938module_param(rx_copybreak, int, 0);
939module_param(max_interrupt_work, int, 0);
940module_param(compaq_ioaddr, int, 0);
941module_param(compaq_irq, int, 0);
942module_param(compaq_device_id, int, 0);
943module_param(watchdog, int, 0);
900fd17d
JL		 944module_param(global_use_mmio, int, 0);
945module_param_array(use_mmio, int, NULL, 0);
1da177e4
LT		 946MODULE_PARM_DESC(debug, "3c59x debug level (0-6)");
947MODULE_PARM_DESC(options, "3c59x: Bits 0-3: media type, bit 4: bus mastering, bit 9: full duplex");
948MODULE_PARM_DESC(global_options, "3c59x: same as options, but applies to all NICs if options is unset");
949MODULE_PARM_DESC(full_duplex, "3c59x full duplex setting(s) (1)");
46e5e4a8 950MODULE_PARM_DESC(global_full_duplex, "3c59x: same as full_duplex, but applies to all NICs if full_duplex is unset");
1da177e4
LT		 951MODULE_PARM_DESC(hw_checksums, "3c59x Hardware checksum checking by adapter(s) (0-1)");
952MODULE_PARM_DESC(flow_ctrl, "3c59x 802.3x flow control usage (PAUSE only) (0-1)");
953MODULE_PARM_DESC(enable_wol, "3c59x: Turn on Wake-on-LAN for adapter(s) (0-1)");
46e5e4a8 954MODULE_PARM_DESC(global_enable_wol, "3c59x: same as enable_wol, but applies to all NICs if enable_wol is unset");
1da177e4
LT		 955MODULE_PARM_DESC(rx_copybreak, "3c59x copy breakpoint for copy-only-tiny-frames");
956MODULE_PARM_DESC(max_interrupt_work, "3c59x maximum events handled per interrupt");
957MODULE_PARM_DESC(compaq_ioaddr, "3c59x PCI I/O base address (Compaq BIOS problem workaround)");
958MODULE_PARM_DESC(compaq_irq, "3c59x PCI IRQ number (Compaq BIOS problem workaround)");
959MODULE_PARM_DESC(compaq_device_id, "3c59x PCI device ID (Compaq BIOS problem workaround)");
960MODULE_PARM_DESC(watchdog, "3c59x transmit timeout in milliseconds");
900fd17d
JL		 961MODULE_PARM_DESC(global_use_mmio, "3c59x: same as use_mmio, but applies to all NICs if options is unset");
962MODULE_PARM_DESC(use_mmio, "3c59x: use memory-mapped PCI I/O resource (0-1)");
1da177e4
LT		 963
964#ifdef CONFIG_NET_POLL_CONTROLLER
965static void poll_vortex(struct net_device *dev)
966{
967 struct vortex_private *vp = netdev_priv(dev);
968 unsigned long flags;
969 local_save_flags(flags);
970 local_irq_disable();
971 (vp->full_bus_master_rx ? boomerang_interrupt:vortex_interrupt)(dev->irq,dev,NULL);
972 local_irq_restore(flags);
973}
974#endif
975
976#ifdef CONFIG_PM
977
978static int vortex_suspend (struct pci_dev *pdev, pm_message_t state)
979{
980 struct net_device *dev = pci_get_drvdata(pdev);
981
982 if (dev && dev->priv) {
983 if (netif_running(dev)) {
984 netif_device_detach(dev);
985 vortex_down(dev, 1);
986 }
5b039e68
RW		 987 pci_save_state(pdev);
988 pci_enable_wake(pdev, pci_choose_state(pdev, state), 0);
989 free_irq(dev->irq, dev);
990 pci_disable_device(pdev);
991 pci_set_power_state(pdev, pci_choose_state(pdev, state));
1da177e4
LT		 992 }
993 return 0;
994}
995
996static int vortex_resume (struct pci_dev *pdev)
997{
998 struct net_device *dev = pci_get_drvdata(pdev);
5b039e68 999 struct vortex_private *vp = netdev_priv(dev);
1da177e4 1000
5b039e68
RW		 1001 if (dev && vp) {
1002 pci_set_power_state(pdev, PCI_D0);
1003 pci_restore_state(pdev);
1004 pci_enable_device(pdev);
1005 pci_set_master(pdev);
1006 if (request_irq(dev->irq, vp->full_bus_master_rx ?
1007 &boomerang_interrupt : &vortex_interrupt, SA_SHIRQ, dev->name, dev)) {
1008 printk(KERN_WARNING "%s: Could not reserve IRQ %d\n", dev->name, dev->irq);
1009 pci_disable_device(pdev);
1010 return -EBUSY;
1011 }
1da177e4
LT		 1012 if (netif_running(dev)) {
1013 vortex_up(dev);
1014 netif_device_attach(dev);
1015 }
1016 }
1017 return 0;
1018}
1019
1020#endif /* CONFIG_PM */
1021
1022#ifdef CONFIG_EISA
1023static struct eisa_device_id vortex_eisa_ids[] = {
1024 { "TCM5920", CH_3C592 },
1025 { "TCM5970", CH_3C597 },
1026 { "" }
1027};
1028
1029static int vortex_eisa_probe (struct device *device);
1030static int vortex_eisa_remove (struct device *device);
1031
1032static struct eisa_driver vortex_eisa_driver = {
1033 .id_table = vortex_eisa_ids,
1034 .driver = {
1035 .name = "3c59x",
1036 .probe = vortex_eisa_probe,
1037 .remove = vortex_eisa_remove
1038 }
1039};
1040
1041static int vortex_eisa_probe (struct device *device)
1042{
62afe595 1043 void __iomem *ioaddr;
1da177e4
LT		 1044 struct eisa_device *edev;
1045
1046 edev = to_eisa_device (device);
1da177e4 1047
62afe595 1048 if (!request_region(edev->base_addr, VORTEX_TOTAL_SIZE, DRV_NAME))
1da177e4
LT		 1049 return -EBUSY;
1050
62afe595
JL		 1051 ioaddr = ioport_map(edev->base_addr, VORTEX_TOTAL_SIZE);
1052
1053 if (vortex_probe1(device, ioaddr, ioread16(ioaddr + 0xC88) >> 12,
1da177e4 1054 edev->id.driver_data, vortex_cards_found)) {
62afe595 1055 release_region (edev->base_addr, VORTEX_TOTAL_SIZE);
1da177e4
LT		 1056 return -ENODEV;
1057 }
1058
1059 vortex_cards_found++;
1060
1061 return 0;
1062}
1063
1064static int vortex_eisa_remove (struct device *device)
1065{
1066 struct eisa_device *edev;
1067 struct net_device *dev;
1068 struct vortex_private *vp;
62afe595 1069 void __iomem *ioaddr;
1da177e4
LT		 1070
1071 edev = to_eisa_device (device);
1072 dev = eisa_get_drvdata (edev);
1073
1074 if (!dev) {
1075 printk("vortex_eisa_remove called for Compaq device!\n");
1076 BUG();
1077 }
1078
1079 vp = netdev_priv(dev);
62afe595 1080 ioaddr = vp->ioaddr;
1da177e4
LT		 1081
1082 unregister_netdev (dev);
62afe595
JL		 1083 iowrite16 (TotalReset|0x14, ioaddr + EL3_CMD);
1084 release_region (dev->base_addr, VORTEX_TOTAL_SIZE);
1da177e4
LT		 1085
1086 free_netdev (dev);
1087 return 0;
1088}
1089#endif
1090
1091/* returns count found (>= 0), or negative on error */
1092static int __init vortex_eisa_init (void)
1093{
1094 int eisa_found = 0;
1095 int orig_cards_found = vortex_cards_found;
1096
1097#ifdef CONFIG_EISA
1098 if (eisa_driver_register (&vortex_eisa_driver) >= 0) {
1099 /* Because of the way EISA bus is probed, we cannot assume
1100 * any device have been found when we exit from
1101 * eisa_driver_register (the bus root driver may not be
1102 * initialized yet). So we blindly assume something was
1103 * found, and let the sysfs magic happend... */
1104
1105 eisa_found = 1;
1106 }
1107#endif
1108
1109 /* Special code to work-around the Compaq PCI BIOS32 problem. */
1110 if (compaq_ioaddr) {
62afe595
JL		 1111 vortex_probe1(NULL, ioport_map(compaq_ioaddr, VORTEX_TOTAL_SIZE),
1112 compaq_irq, compaq_device_id, vortex_cards_found++);
1da177e4
LT		 1113 }
1114
1115 return vortex_cards_found - orig_cards_found + eisa_found;
1116}
1117
1118/* returns count (>= 0), or negative on error */
1119static int __devinit vortex_init_one (struct pci_dev *pdev,
1120 const struct pci_device_id *ent)
1121{
900fd17d
JL		 1122 int rc, unit, pci_bar;
1123 struct vortex_chip_info *vci;
1124 void __iomem *ioaddr;
1da177e4
LT		 1125
1126 /* wake up and enable device */
1127 rc = pci_enable_device (pdev);
1128 if (rc < 0)
1129 goto out;
1130
900fd17d
JL		 1131 unit = vortex_cards_found;
1132
1133 if (global_use_mmio < 0 && (unit >= MAX_UNITS || use_mmio[unit] < 0)) {
1134 /* Determine the default if the user didn't override us */
1135 vci = &vortex_info_tbl[ent->driver_data];
1136 pci_bar = vci->drv_flags & (IS_CYCLONE | IS_TORNADO) ? 1 : 0;
1137 } else if (unit < MAX_UNITS && use_mmio[unit] >= 0)
1138 pci_bar = use_mmio[unit] ? 1 : 0;
1139 else
1140 pci_bar = global_use_mmio ? 1 : 0;
1141
1142 ioaddr = pci_iomap(pdev, pci_bar, 0);
1143 if (!ioaddr) /* If mapping fails, fall-back to BAR 0... */
1144 ioaddr = pci_iomap(pdev, 0, 0);
1145
1146 rc = vortex_probe1(&pdev->dev, ioaddr, pdev->irq,
1147 ent->driver_data, unit);
1da177e4
LT		 1148 if (rc < 0) {
1149 pci_disable_device (pdev);
1150 goto out;
1151 }
1152
1153 vortex_cards_found++;
1154
1155out:
1156 return rc;
1157}
1158
1159/*
1160 * Start up the PCI/EISA device which is described by *gendev.
1161 * Return 0 on success.
1162 *
1163 * NOTE: pdev can be NULL, for the case of a Compaq device
1164 */
1165static int __devinit vortex_probe1(struct device *gendev,
62afe595 1166 void __iomem *ioaddr, int irq,
1da177e4
LT		 1167 int chip_idx, int card_idx)
1168{
1169 struct vortex_private *vp;
1170 int option;
1171 unsigned int eeprom[0x40], checksum = 0; /* EEPROM contents */
1172 int i, step;
1173 struct net_device *dev;
1174 static int printed_version;
1175 int retval, print_info;
1176 struct vortex_chip_info * const vci = &vortex_info_tbl[chip_idx];
1177 char *print_name = "3c59x";
1178 struct pci_dev *pdev = NULL;
1179 struct eisa_device *edev = NULL;
1180
1181 if (!printed_version) {
1182 printk (version);
1183 printed_version = 1;
1184 }
1185
1186 if (gendev) {
1187 if ((pdev = DEVICE_PCI(gendev))) {
1188 print_name = pci_name(pdev);
1189 }
1190
1191 if ((edev = DEVICE_EISA(gendev))) {
1192 print_name = edev->dev.bus_id;
1193 }
1194 }
1195
1196 dev = alloc_etherdev(sizeof(*vp));
1197 retval = -ENOMEM;
1198 if (!dev) {
1199 printk (KERN_ERR PFX "unable to allocate etherdev, aborting\n");
1200 goto out;
1201 }
1202 SET_MODULE_OWNER(dev);
1203 SET_NETDEV_DEV(dev, gendev);
1204 vp = netdev_priv(dev);
1205
1206 option = global_options;
1207
1208 /* The lower four bits are the media type. */
1209 if (dev->mem_start) {
1210 /*
1211 * The 'options' param is passed in as the third arg to the
1212 * LILO 'ether=' argument for non-modular use
1213 */
1214 option = dev->mem_start;
1215 }
1216 else if (card_idx < MAX_UNITS) {
1217 if (options[card_idx] >= 0)
1218 option = options[card_idx];
1219 }
1220
1221 if (option > 0) {
1222 if (option & 0x8000)
1223 vortex_debug = 7;
1224 if (option & 0x4000)
1225 vortex_debug = 2;
1226 if (option & 0x0400)
1227 vp->enable_wol = 1;
1228 }
1229
1230 print_info = (vortex_debug > 1);
1231 if (print_info)
1232 printk (KERN_INFO "See Documentation/networking/vortex.txt\n");
1233
62afe595 1234 printk(KERN_INFO "%s: 3Com %s %s at %p. Vers " DRV_VERSION "\n",
1da177e4
LT		 1235 print_name,
1236 pdev ? "PCI" : "EISA",
1237 vci->name,
1238 ioaddr);
1239
62afe595 1240 dev->base_addr = (unsigned long)ioaddr;
1da177e4
LT		 1241 dev->irq = irq;
1242 dev->mtu = mtu;
62afe595 1243 vp->ioaddr = ioaddr;
1da177e4
LT		 1244 vp->large_frames = mtu > 1500;
1245 vp->drv_flags = vci->drv_flags;
1246 vp->has_nway = (vci->drv_flags & HAS_NWAY) ? 1 : 0;
1247 vp->io_size = vci->io_size;
1248 vp->card_idx = card_idx;
1249
1250 /* module list only for Compaq device */
1251 if (gendev == NULL) {
1252 compaq_net_device = dev;
1253 }
1254
1255 /* PCI-only startup logic */
1256 if (pdev) {
1257 /* EISA resources already marked, so only PCI needs to do this here */
1258 /* Ignore return value, because Cardbus drivers already allocate for us */
62afe595 1259 if (request_region(dev->base_addr, vci->io_size, print_name) != NULL)
1da177e4
LT		 1260 vp->must_free_region = 1;
1261
1262 /* enable bus-mastering if necessary */
1263 if (vci->flags & PCI_USES_MASTER)
1264 pci_set_master (pdev);
1265
1266 if (vci->drv_flags & IS_VORTEX) {
1267 u8 pci_latency;
1268 u8 new_latency = 248;
1269
1270 /* Check the PCI latency value. On the 3c590 series the latency timer
1271 must be set to the maximum value to avoid data corruption that occurs
1272 when the timer expires during a transfer. This bug exists the Vortex
1273 chip only. */
1274 pci_read_config_byte(pdev, PCI_LATENCY_TIMER, &pci_latency);
1275 if (pci_latency < new_latency) {
1276 printk(KERN_INFO "%s: Overriding PCI latency"
1277 " timer (CFLT) setting of %d, new value is %d.\n",
1278 print_name, pci_latency, new_latency);
1279 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, new_latency);
1280 }
1281 }
1282 }
1283
1284 spin_lock_init(&vp->lock);
1285 vp->gendev = gendev;
1286 vp->mii.dev = dev;
1287 vp->mii.mdio_read = mdio_read;
1288 vp->mii.mdio_write = mdio_write;
1289 vp->mii.phy_id_mask = 0x1f;
1290 vp->mii.reg_num_mask = 0x1f;
1291
1292 /* Makes sure rings are at least 16 byte aligned. */
1293 vp->rx_ring = pci_alloc_consistent(pdev, sizeof(struct boom_rx_desc) * RX_RING_SIZE
1294 + sizeof(struct boom_tx_desc) * TX_RING_SIZE,
1295 &vp->rx_ring_dma);
1296 retval = -ENOMEM;
1297 if (vp->rx_ring == 0)
1298 goto free_region;
1299
1300 vp->tx_ring = (struct boom_tx_desc *)(vp->rx_ring + RX_RING_SIZE);
1301 vp->tx_ring_dma = vp->rx_ring_dma + sizeof(struct boom_rx_desc) * RX_RING_SIZE;
1302
1303 /* if we are a PCI driver, we store info in pdev->driver_data
1304 * instead of a module list */
1305 if (pdev)
1306 pci_set_drvdata(pdev, dev);
1307 if (edev)
1308 eisa_set_drvdata (edev, dev);
1309
1310 vp->media_override = 7;
1311 if (option >= 0) {
1312 vp->media_override = ((option & 7) == 2) ? 0 : option & 15;
1313 if (vp->media_override != 7)
1314 vp->medialock = 1;
1315 vp->full_duplex = (option & 0x200) ? 1 : 0;
1316 vp->bus_master = (option & 16) ? 1 : 0;
1317 }
1318
1319 if (global_full_duplex > 0)
1320 vp->full_duplex = 1;
1321 if (global_enable_wol > 0)
1322 vp->enable_wol = 1;
1323
1324 if (card_idx < MAX_UNITS) {
1325 if (full_duplex[card_idx] > 0)
1326 vp->full_duplex = 1;
1327 if (flow_ctrl[card_idx] > 0)
1328 vp->flow_ctrl = 1;
1329 if (enable_wol[card_idx] > 0)
1330 vp->enable_wol = 1;
1331 }
1332
1333 vp->force_fd = vp->full_duplex;
1334 vp->options = option;
1335 /* Read the station address from the EEPROM. */
1336 EL3WINDOW(0);
1337 {
1338 int base;
1339
1340 if (vci->drv_flags & EEPROM_8BIT)
1341 base = 0x230;
1342 else if (vci->drv_flags & EEPROM_OFFSET)
1343 base = EEPROM_Read + 0x30;
1344 else
1345 base = EEPROM_Read;
1346
1347 for (i = 0; i < 0x40; i++) {
1348 int timer;
62afe595 1349 iowrite16(base + i, ioaddr + Wn0EepromCmd);
1da177e4
LT		 1350 /* Pause for at least 162 us. for the read to take place. */
1351 for (timer = 10; timer >= 0; timer--) {
1352 udelay(162);
62afe595 1353 if ((ioread16(ioaddr + Wn0EepromCmd) & 0x8000) == 0)
1da177e4
LT		 1354 break;
1355 }
62afe595 1356 eeprom[i] = ioread16(ioaddr + Wn0EepromData);
1da177e4
LT		 1357 }
1358 }
1359 for (i = 0; i < 0x18; i++)
1360 checksum ^= eeprom[i];
1361 checksum = (checksum ^ (checksum >> 8)) & 0xff;
1362 if (checksum != 0x00) { /* Grrr, needless incompatible change 3Com. */
1363 while (i < 0x21)
1364 checksum ^= eeprom[i++];
1365 checksum = (checksum ^ (checksum >> 8)) & 0xff;
1366 }
1367 if ((checksum != 0x00) && !(vci->drv_flags & IS_TORNADO))
1368 printk(" ***INVALID CHECKSUM %4.4x*** ", checksum);
1369 for (i = 0; i < 3; i++)
1370 ((u16 *)dev->dev_addr)[i] = htons(eeprom[i + 10]);
bb531fc0 1371 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
1da177e4
LT		 1372 if (print_info) {
1373 for (i = 0; i < 6; i++)
1374 printk("%c%2.2x", i ? ':' : ' ', dev->dev_addr[i]);
1375 }
1376 /* Unfortunately an all zero eeprom passes the checksum and this
1377 gets found in the wild in failure cases. Crypto is hard 8) */
1378 if (!is_valid_ether_addr(dev->dev_addr)) {
1379 retval = -EINVAL;
1380 printk(KERN_ERR "*** EEPROM MAC address is invalid.\n");
1381 goto free_ring; /* With every pack */
1382 }
1383 EL3WINDOW(2);
1384 for (i = 0; i < 6; i++)
62afe595 1385 iowrite8(dev->dev_addr[i], ioaddr + i);
1da177e4
LT		 1386
1387#ifdef __sparc__
1388 if (print_info)
1389 printk(", IRQ %s\n", __irq_itoa(dev->irq));
1390#else
1391 if (print_info)
1392 printk(", IRQ %d\n", dev->irq);
1393 /* Tell them about an invalid IRQ. */
1394 if (dev->irq <= 0 || dev->irq >= NR_IRQS)
1395 printk(KERN_WARNING " *** Warning: IRQ %d is unlikely to work! ***\n",
1396 dev->irq);
1397#endif
1398
1399 EL3WINDOW(4);
62afe595 1400 step = (ioread8(ioaddr + Wn4_NetDiag) & 0x1e) >> 1;
1da177e4
LT		 1401 if (print_info) {
1402 printk(KERN_INFO " product code %02x%02x rev %02x.%d date %02d-"
1403 "%02d-%02d\n", eeprom[6]&0xff, eeprom[6]>>8, eeprom[0x14],
1404 step, (eeprom[4]>>5) & 15, eeprom[4] & 31, eeprom[4]>>9);
1405 }
1406
1407
1408 if (pdev && vci->drv_flags & HAS_CB_FNS) {
1da177e4
LT		 1409 unsigned short n;
1410
62afe595
JL		 1411 vp->cb_fn_base = pci_iomap(pdev, 2, 0);
1412 if (!vp->cb_fn_base) {
1da177e4 1413 retval = -ENOMEM;
62afe595 1414 goto free_ring;
1da177e4 1415 }
62afe595 1416
1da177e4
LT		 1417 if (print_info) {
1418 printk(KERN_INFO "%s: CardBus functions mapped %8.8lx->%p\n",
62afe595
JL		 1419 print_name, pci_resource_start(pdev, 2),
1420 vp->cb_fn_base);
1da177e4
LT		 1421 }
1422 EL3WINDOW(2);
1423
62afe595 1424 n = ioread16(ioaddr + Wn2_ResetOptions) & ~0x4010;
1da177e4
LT		 1425 if (vp->drv_flags & INVERT_LED_PWR)
1426 n |= 0x10;
1427 if (vp->drv_flags & INVERT_MII_PWR)
1428 n |= 0x4000;
62afe595 1429 iowrite16(n, ioaddr + Wn2_ResetOptions);
1da177e4
LT		 1430 if (vp->drv_flags & WNO_XCVR_PWR) {
1431 EL3WINDOW(0);
62afe595 1432 iowrite16(0x0800, ioaddr);
1da177e4
LT		 1433 }
1434 }
1435
1436 /* Extract our information from the EEPROM data. */
1437 vp->info1 = eeprom[13];
1438 vp->info2 = eeprom[15];
1439 vp->capabilities = eeprom[16];
1440
1441 if (vp->info1 & 0x8000) {
1442 vp->full_duplex = 1;
1443 if (print_info)
1444 printk(KERN_INFO "Full duplex capable\n");
1445 }
1446
1447 {
f71e1309 1448 static const char * const ram_split[] = {"5:3", "3:1", "1:1", "3:5"};
1da177e4
LT		 1449 unsigned int config;
1450 EL3WINDOW(3);
62afe595 1451 vp->available_media = ioread16(ioaddr + Wn3_Options);
1da177e4
LT		 1452 if ((vp->available_media & 0xff) == 0) /* Broken 3c916 */
1453 vp->available_media = 0x40;
62afe595 1454 config = ioread32(ioaddr + Wn3_Config);
1da177e4
LT		 1455 if (print_info) {
1456 printk(KERN_DEBUG " Internal config register is %4.4x, "
62afe595 1457 "transceivers %#x.\n", config, ioread16(ioaddr + Wn3_Options));
1da177e4
LT		 1458 printk(KERN_INFO " %dK %s-wide RAM %s Rx:Tx split, %s%s interface.\n",
1459 8 << RAM_SIZE(config),
1460 RAM_WIDTH(config) ? "word" : "byte",
1461 ram_split[RAM_SPLIT(config)],
1462 AUTOSELECT(config) ? "autoselect/" : "",
1463 XCVR(config) > XCVR_ExtMII ? "<invalid transceiver>" :
1464 media_tbl[XCVR(config)].name);
1465 }
1466 vp->default_media = XCVR(config);
1467 if (vp->default_media == XCVR_NWAY)
1468 vp->has_nway = 1;
1469 vp->autoselect = AUTOSELECT(config);
1470 }
1471
1472 if (vp->media_override != 7) {
1473 printk(KERN_INFO "%s: Media override to transceiver type %d (%s).\n",
1474 print_name, vp->media_override,
1475 media_tbl[vp->media_override].name);
1476 dev->if_port = vp->media_override;
1477 } else
1478 dev->if_port = vp->default_media;
1479
1480 if ((vp->available_media & 0x40) || (vci->drv_flags & HAS_NWAY) ||
1481 dev->if_port == XCVR_MII || dev->if_port == XCVR_NWAY) {
1482 int phy, phy_idx = 0;
1483 EL3WINDOW(4);
1484 mii_preamble_required++;
1485 if (vp->drv_flags & EXTRA_PREAMBLE)
1486 mii_preamble_required++;
1487 mdio_sync(ioaddr, 32);
106427e6 1488 mdio_read(dev, 24, MII_BMSR);
1da177e4
LT		 1489 for (phy = 0; phy < 32 && phy_idx < 1; phy++) {
1490 int mii_status, phyx;
1491
1492 /*
1493 * For the 3c905CX we look at index 24 first, because it bogusly
1494 * reports an external PHY at all indices
1495 */
1496 if (phy == 0)
1497 phyx = 24;
1498 else if (phy <= 24)
1499 phyx = phy - 1;
1500 else
1501 phyx = phy;
106427e6 1502 mii_status = mdio_read(dev, phyx, MII_BMSR);
1da177e4
LT		 1503 if (mii_status && mii_status != 0xffff) {
1504 vp->phys[phy_idx++] = phyx;
1505 if (print_info) {
1506 printk(KERN_INFO " MII transceiver found at address %d,"
1507 " status %4x.\n", phyx, mii_status);
1508 }
1509 if ((mii_status & 0x0040) == 0)
1510 mii_preamble_required++;
1511 }
1512 }
1513 mii_preamble_required--;
1514 if (phy_idx == 0) {
1515 printk(KERN_WARNING" ***WARNING*** No MII transceivers found!\n");
1516 vp->phys[0] = 24;
1517 } else {
106427e6 1518 vp->advertising = mdio_read(dev, vp->phys[0], MII_ADVERTISE);
1da177e4
LT		 1519 if (vp->full_duplex) {
1520 /* Only advertise the FD media types. */
1521 vp->advertising &= ~0x02A0;
1522 mdio_write(dev, vp->phys[0], 4, vp->advertising);
1523 }
1524 }
1525 vp->mii.phy_id = vp->phys[0];
1526 }
1527
1528 if (vp->capabilities & CapBusMaster) {
1529 vp->full_bus_master_tx = 1;
1530 if (print_info) {
1531 printk(KERN_INFO " Enabling bus-master transmits and %s receives.\n",
1532 (vp->info2 & 1) ? "early" : "whole-frame" );
1533 }
1534 vp->full_bus_master_rx = (vp->info2 & 1) ? 1 : 2;
1535 vp->bus_master = 0; /* AKPM: vortex only */
1536 }
1537
1538 /* The 3c59x-specific entries in the device structure. */
1539 dev->open = vortex_open;
1540 if (vp->full_bus_master_tx) {
1541 dev->hard_start_xmit = boomerang_start_xmit;
1542 /* Actually, it still should work with iommu. */
32fb5f06
JL		 1543 if (card_idx < MAX_UNITS &&
1544 ((hw_checksums[card_idx] == -1 && (vp->drv_flags & HAS_HWCKSM)) ||
1545 hw_checksums[card_idx] == 1)) {
d311b0d3 1546 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
1da177e4
LT		 1547 }
1548 } else {
1549 dev->hard_start_xmit = vortex_start_xmit;
1550 }
1551
1552 if (print_info) {
1553 printk(KERN_INFO "%s: scatter/gather %sabled. h/w checksums %sabled\n",
1554 print_name,
1555 (dev->features & NETIF_F_SG) ? "en":"dis",
1556 (dev->features & NETIF_F_IP_CSUM) ? "en":"dis");
1557 }
1558
1559 dev->stop = vortex_close;
1560 dev->get_stats = vortex_get_stats;
1561#ifdef CONFIG_PCI
1562 dev->do_ioctl = vortex_ioctl;
1563#endif
1564 dev->ethtool_ops = &vortex_ethtool_ops;
1565 dev->set_multicast_list = set_rx_mode;
1566 dev->tx_timeout = vortex_tx_timeout;
1567 dev->watchdog_timeo = (watchdog * HZ) / 1000;
1568#ifdef CONFIG_NET_POLL_CONTROLLER
1569 dev->poll_controller = poll_vortex;
1570#endif
1571 if (pdev) {
1572 vp->pm_state_valid = 1;
1573 pci_save_state(VORTEX_PCI(vp));
1574 acpi_set_WOL(dev);
1575 }
1576 retval = register_netdev(dev);
1577 if (retval == 0)
1578 return 0;
1579
1580free_ring:
1581 pci_free_consistent(pdev,
1582 sizeof(struct boom_rx_desc) * RX_RING_SIZE
1583 + sizeof(struct boom_tx_desc) * TX_RING_SIZE,
1584 vp->rx_ring,
1585 vp->rx_ring_dma);
1586free_region:
1587 if (vp->must_free_region)
62afe595 1588 release_region(dev->base_addr, vci->io_size);
1da177e4
LT		 1589 free_netdev(dev);
1590 printk(KERN_ERR PFX "vortex_probe1 fails. Returns %d\n", retval);
1591out:
1592 return retval;
1593}
1594
1595static void
1596issue_and_wait(struct net_device *dev, int cmd)
1597{
62afe595
JL		 1598 struct vortex_private *vp = netdev_priv(dev);
1599 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 1600 int i;
1601
62afe595 1602 iowrite16(cmd, ioaddr + EL3_CMD);
1da177e4 1603 for (i = 0; i < 2000; i++) {
62afe595 1604 if (!(ioread16(ioaddr + EL3_STATUS) & CmdInProgress))
1da177e4
LT		 1605 return;
1606 }
1607
1608 /* OK, that didn't work. Do it the slow way. One second */
1609 for (i = 0; i < 100000; i++) {
62afe595 1610 if (!(ioread16(ioaddr + EL3_STATUS) & CmdInProgress)) {
1da177e4
LT		 1611 if (vortex_debug > 1)
1612 printk(KERN_INFO "%s: command 0x%04x took %d usecs\n",
1613 dev->name, cmd, i * 10);
1614 return;
1615 }
1616 udelay(10);
1617 }
1618 printk(KERN_ERR "%s: command 0x%04x did not complete! Status=0x%x\n",
62afe595 1619 dev->name, cmd, ioread16(ioaddr + EL3_STATUS));
1da177e4
LT		 1620}
1621
1622static void
1623vortex_up(struct net_device *dev)
1624{
1da177e4 1625 struct vortex_private *vp = netdev_priv(dev);
62afe595 1626 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 1627 unsigned int config;
1628 int i;
1629
1630 if (VORTEX_PCI(vp)) {
1631 pci_set_power_state(VORTEX_PCI(vp), PCI_D0); /* Go active */
3c8fad18
DR		 1632 if (vp->pm_state_valid)
1633 pci_restore_state(VORTEX_PCI(vp));
1da177e4
LT		 1634 pci_enable_device(VORTEX_PCI(vp));
1635 }
1636
1637 /* Before initializing select the active media port. */
1638 EL3WINDOW(3);
62afe595 1639 config = ioread32(ioaddr + Wn3_Config);
1da177e4
LT		 1640
1641 if (vp->media_override != 7) {
1642 printk(KERN_INFO "%s: Media override to transceiver %d (%s).\n",
1643 dev->name, vp->media_override,
1644 media_tbl[vp->media_override].name);
1645 dev->if_port = vp->media_override;
1646 } else if (vp->autoselect) {
1647 if (vp->has_nway) {
1648 if (vortex_debug > 1)
1649 printk(KERN_INFO "%s: using NWAY device table, not %d\n",
1650 dev->name, dev->if_port);
1651 dev->if_port = XCVR_NWAY;
1652 } else {
1653 /* Find first available media type, starting with 100baseTx. */
1654 dev->if_port = XCVR_100baseTx;
1655 while (! (vp->available_media & media_tbl[dev->if_port].mask))
1656 dev->if_port = media_tbl[dev->if_port].next;
1657 if (vortex_debug > 1)
1658 printk(KERN_INFO "%s: first available media type: %s\n",
1659 dev->name, media_tbl[dev->if_port].name);
1660 }
1661 } else {
1662 dev->if_port = vp->default_media;
1663 if (vortex_debug > 1)
1664 printk(KERN_INFO "%s: using default media %s\n",
1665 dev->name, media_tbl[dev->if_port].name);
1666 }
1667
1668 init_timer(&vp->timer);
1669 vp->timer.expires = RUN_AT(media_tbl[dev->if_port].wait);
1670 vp->timer.data = (unsigned long)dev;
1671 vp->timer.function = vortex_timer; /* timer handler */
1672 add_timer(&vp->timer);
1673
1674 init_timer(&vp->rx_oom_timer);
1675 vp->rx_oom_timer.data = (unsigned long)dev;
1676 vp->rx_oom_timer.function = rx_oom_timer;
1677
1678 if (vortex_debug > 1)
1679 printk(KERN_DEBUG "%s: Initial media type %s.\n",
1680 dev->name, media_tbl[dev->if_port].name);
1681
1682 vp->full_duplex = vp->force_fd;
1683 config = BFINS(config, dev->if_port, 20, 4);
1684 if (vortex_debug > 6)
1685 printk(KERN_DEBUG "vortex_up(): writing 0x%x to InternalConfig\n", config);
62afe595 1686 iowrite32(config, ioaddr + Wn3_Config);
1da177e4
LT		 1687
1688 if (dev->if_port == XCVR_MII || dev->if_port == XCVR_NWAY) {
1689 int mii_reg1, mii_reg5;
1690 EL3WINDOW(4);
1691 /* Read BMSR (reg1) only to clear old status. */
106427e6
NH		 1692 mii_reg1 = mdio_read(dev, vp->phys[0], MII_BMSR);
1693 mii_reg5 = mdio_read(dev, vp->phys[0], MII_LPA);
1da177e4
LT		 1694 if (mii_reg5 == 0xffff || mii_reg5 == 0x0000) {
1695 netif_carrier_off(dev); /* No MII device or no link partner report */
1696 } else {
1697 mii_reg5 &= vp->advertising;
1698 if ((mii_reg5 & 0x0100) != 0 /* 100baseTx-FD */
1699 || (mii_reg5 & 0x00C0) == 0x0040) /* 10T-FD, but not 100-HD */
1700 vp->full_duplex = 1;
1701 netif_carrier_on(dev);
1702 }
1703 vp->partner_flow_ctrl = ((mii_reg5 & 0x0400) != 0);
1704 if (vortex_debug > 1)
1705 printk(KERN_INFO "%s: MII #%d status %4.4x, link partner capability %4.4x,"
1706 " info1 %04x, setting %s-duplex.\n",
1707 dev->name, vp->phys[0],
1708 mii_reg1, mii_reg5,
1709 vp->info1, ((vp->info1 & 0x8000) || vp->full_duplex) ? "full" : "half");
1710 EL3WINDOW(3);
1711 }
1712
1713 /* Set the full-duplex bit. */
62afe595 1714 iowrite16( ((vp->info1 & 0x8000) || vp->full_duplex ? 0x20 : 0) |
1da177e4
LT		 1715 (vp->large_frames ? 0x40 : 0) |
1716 ((vp->full_duplex && vp->flow_ctrl && vp->partner_flow_ctrl) ? 0x100 : 0),
1717 ioaddr + Wn3_MAC_Ctrl);
1718
1719 if (vortex_debug > 1) {
1720 printk(KERN_DEBUG "%s: vortex_up() InternalConfig %8.8x.\n",
1721 dev->name, config);
1722 }
1723
1724 issue_and_wait(dev, TxReset);
1725 /*
1726 * Don't reset the PHY - that upsets autonegotiation during DHCP operations.
1727 */
1728 issue_and_wait(dev, RxReset|0x04);
1729
62afe595 1730 iowrite16(SetStatusEnb | 0x00, ioaddr + EL3_CMD);
1da177e4
LT		 1731
1732 if (vortex_debug > 1) {
1733 EL3WINDOW(4);
1734 printk(KERN_DEBUG "%s: vortex_up() irq %d media status %4.4x.\n",
62afe595 1735 dev->name, dev->irq, ioread16(ioaddr + Wn4_Media));
1da177e4
LT		 1736 }
1737
1738 /* Set the station address and mask in window 2 each time opened. */
1739 EL3WINDOW(2);
1740 for (i = 0; i < 6; i++)
62afe595 1741 iowrite8(dev->dev_addr[i], ioaddr + i);
1da177e4 1742 for (; i < 12; i+=2)
62afe595 1743 iowrite16(0, ioaddr + i);
1da177e4
LT		 1744
1745 if (vp->cb_fn_base) {
62afe595 1746 unsigned short n = ioread16(ioaddr + Wn2_ResetOptions) & ~0x4010;
1da177e4
LT		 1747 if (vp->drv_flags & INVERT_LED_PWR)
1748 n |= 0x10;
1749 if (vp->drv_flags & INVERT_MII_PWR)
1750 n |= 0x4000;
62afe595 1751 iowrite16(n, ioaddr + Wn2_ResetOptions);
1da177e4
LT		 1752 }
1753
1754 if (dev->if_port == XCVR_10base2)
1755 /* Start the thinnet transceiver. We should really wait 50ms...*/
62afe595 1756 iowrite16(StartCoax, ioaddr + EL3_CMD);
1da177e4
LT		 1757 if (dev->if_port != XCVR_NWAY) {
1758 EL3WINDOW(4);
62afe595 1759 iowrite16((ioread16(ioaddr + Wn4_Media) & ~(Media_10TP|Media_SQE)) |
1da177e4
LT		 1760 media_tbl[dev->if_port].media_bits, ioaddr + Wn4_Media);
1761 }
1762
1763 /* Switch to the stats window, and clear all stats by reading. */
62afe595 1764 iowrite16(StatsDisable, ioaddr + EL3_CMD);
1da177e4
LT		 1765 EL3WINDOW(6);
1766 for (i = 0; i < 10; i++)
62afe595
JL		 1767 ioread8(ioaddr + i);
1768 ioread16(ioaddr + 10);
1769 ioread16(ioaddr + 12);
1da177e4
LT		 1770 /* New: On the Vortex we must also clear the BadSSD counter. */
1771 EL3WINDOW(4);
62afe595 1772 ioread8(ioaddr + 12);
1da177e4 1773 /* ..and on the Boomerang we enable the extra statistics bits. */
62afe595 1774 iowrite16(0x0040, ioaddr + Wn4_NetDiag);
1da177e4
LT		 1775
1776 /* Switch to register set 7 for normal use. */
1777 EL3WINDOW(7);
1778
1779 if (vp->full_bus_master_rx) { /* Boomerang bus master. */
1780 vp->cur_rx = vp->dirty_rx = 0;
1781 /* Initialize the RxEarly register as recommended. */
62afe595
JL		 1782 iowrite16(SetRxThreshold + (1536>>2), ioaddr + EL3_CMD);
1783 iowrite32(0x0020, ioaddr + PktStatus);
1784 iowrite32(vp->rx_ring_dma, ioaddr + UpListPtr);
1da177e4
LT		 1785 }
1786 if (vp->full_bus_master_tx) { /* Boomerang bus master Tx. */
1787 vp->cur_tx = vp->dirty_tx = 0;
1788 if (vp->drv_flags & IS_BOOMERANG)
62afe595 1789 iowrite8(PKT_BUF_SZ>>8, ioaddr + TxFreeThreshold); /* Room for a packet. */
1da177e4
LT		 1790 /* Clear the Rx, Tx rings. */
1791 for (i = 0; i < RX_RING_SIZE; i++) /* AKPM: this is done in vortex_open, too */
1792 vp->rx_ring[i].status = 0;
1793 for (i = 0; i < TX_RING_SIZE; i++)
1794 vp->tx_skbuff[i] = NULL;
62afe595 1795 iowrite32(0, ioaddr + DownListPtr);
1da177e4
LT		 1796 }
1797 /* Set receiver mode: presumably accept b-case and phys addr only. */
1798 set_rx_mode(dev);
1799 /* enable 802.1q tagged frames */
1800 set_8021q_mode(dev, 1);
62afe595 1801 iowrite16(StatsEnable, ioaddr + EL3_CMD); /* Turn on statistics. */
1da177e4
LT		 1802
1803// issue_and_wait(dev, SetTxStart|0x07ff);
62afe595
JL		 1804 iowrite16(RxEnable, ioaddr + EL3_CMD); /* Enable the receiver. */
1805 iowrite16(TxEnable, ioaddr + EL3_CMD); /* Enable transmitter. */
1da177e4
LT		 1806 /* Allow status bits to be seen. */
1807 vp->status_enable = SetStatusEnb | HostError|IntReq|StatsFull|TxComplete|
1808 (vp->full_bus_master_tx ? DownComplete : TxAvailable) |
1809 (vp->full_bus_master_rx ? UpComplete : RxComplete) |
1810 (vp->bus_master ? DMADone : 0);
1811 vp->intr_enable = SetIntrEnb | IntLatch | TxAvailable |
1812 (vp->full_bus_master_rx ? 0 : RxComplete) |
1813 StatsFull | HostError | TxComplete | IntReq
1814 | (vp->bus_master ? DMADone : 0) | UpComplete | DownComplete;
62afe595 1815 iowrite16(vp->status_enable, ioaddr + EL3_CMD);
1da177e4 1816 /* Ack all pending events, and set active indicator mask. */
62afe595 1817 iowrite16(AckIntr | IntLatch | TxAvailable | RxEarly | IntReq,
1da177e4 1818 ioaddr + EL3_CMD);
62afe595 1819 iowrite16(vp->intr_enable, ioaddr + EL3_CMD);
1da177e4 1820 if (vp->cb_fn_base) /* The PCMCIA people are idiots. */
62afe595 1821 iowrite32(0x8000, vp->cb_fn_base + 4);
1da177e4
LT		 1822 netif_start_queue (dev);
1823}
1824
1825static int
1826vortex_open(struct net_device *dev)
1827{
1828 struct vortex_private *vp = netdev_priv(dev);
1829 int i;
1830 int retval;
1831
1832 /* Use the now-standard shared IRQ implementation. */
1833 if ((retval = request_irq(dev->irq, vp->full_bus_master_rx ?
1834 &boomerang_interrupt : &vortex_interrupt, SA_SHIRQ, dev->name, dev))) {
1835 printk(KERN_ERR "%s: Could not reserve IRQ %d\n", dev->name, dev->irq);
1836 goto out;
1837 }
1838
1839 if (vp->full_bus_master_rx) { /* Boomerang bus master. */
1840 if (vortex_debug > 2)
1841 printk(KERN_DEBUG "%s: Filling in the Rx ring.\n", dev->name);
1842 for (i = 0; i < RX_RING_SIZE; i++) {
1843 struct sk_buff *skb;
1844 vp->rx_ring[i].next = cpu_to_le32(vp->rx_ring_dma + sizeof(struct boom_rx_desc) * (i+1));
1845 vp->rx_ring[i].status = 0; /* Clear complete bit. */
1846 vp->rx_ring[i].length = cpu_to_le32(PKT_BUF_SZ | LAST_FRAG);
1847 skb = dev_alloc_skb(PKT_BUF_SZ);
1848 vp->rx_skbuff[i] = skb;
1849 if (skb == NULL)
1850 break; /* Bad news! */
1851 skb->dev = dev; /* Mark as being used by this device. */
1852 skb_reserve(skb, 2); /* Align IP on 16 byte boundaries */
689be439 1853 vp->rx_ring[i].addr = cpu_to_le32(pci_map_single(VORTEX_PCI(vp), skb->data, PKT_BUF_SZ, PCI_DMA_FROMDEVICE));
1da177e4
LT		 1854 }
1855 if (i != RX_RING_SIZE) {
1856 int j;
1857 printk(KERN_EMERG "%s: no memory for rx ring\n", dev->name);
1858 for (j = 0; j < i; j++) {
1859 if (vp->rx_skbuff[j]) {
1860 dev_kfree_skb(vp->rx_skbuff[j]);
1861 vp->rx_skbuff[j] = NULL;
1862 }
1863 }
1864 retval = -ENOMEM;
1865 goto out_free_irq;
1866 }
1867 /* Wrap the ring. */
1868 vp->rx_ring[i-1].next = cpu_to_le32(vp->rx_ring_dma);
1869 }
1870
1871 vortex_up(dev);
1872 return 0;
1873
1874out_free_irq:
1875 free_irq(dev->irq, dev);
1876out:
1877 if (vortex_debug > 1)
1878 printk(KERN_ERR "%s: vortex_open() fails: returning %d\n", dev->name, retval);
1879 return retval;
1880}
1881
1882static void
1883vortex_timer(unsigned long data)
1884{
1885 struct net_device *dev = (struct net_device *)data;
1886 struct vortex_private *vp = netdev_priv(dev);
62afe595 1887 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 1888 int next_tick = 60*HZ;
1889 int ok = 0;
1890 int media_status, mii_status, old_window;
1891
1892 if (vortex_debug > 2) {
1893 printk(KERN_DEBUG "%s: Media selection timer tick happened, %s.\n",
1894 dev->name, media_tbl[dev->if_port].name);
1895 printk(KERN_DEBUG "dev->watchdog_timeo=%d\n", dev->watchdog_timeo);
1896 }
1897
1898 if (vp->medialock)
1899 goto leave_media_alone;
1900 disable_irq(dev->irq);
62afe595 1901 old_window = ioread16(ioaddr + EL3_CMD) >> 13;
1da177e4 1902 EL3WINDOW(4);
62afe595 1903 media_status = ioread16(ioaddr + Wn4_Media);
1da177e4
LT		 1904 switch (dev->if_port) {
1905 case XCVR_10baseT: case XCVR_100baseTx: case XCVR_100baseFx:
1906 if (media_status & Media_LnkBeat) {
1907 netif_carrier_on(dev);
1908 ok = 1;
1909 if (vortex_debug > 1)
1910 printk(KERN_DEBUG "%s: Media %s has link beat, %x.\n",
1911 dev->name, media_tbl[dev->if_port].name, media_status);
1912 } else {
1913 netif_carrier_off(dev);
1914 if (vortex_debug > 1) {
1915 printk(KERN_DEBUG "%s: Media %s has no link beat, %x.\n",
1916 dev->name, media_tbl[dev->if_port].name, media_status);
1917 }
1918 }
1919 break;
1920 case XCVR_MII: case XCVR_NWAY:
1921 {
1922 spin_lock_bh(&vp->lock);
106427e6 1923 mii_status = mdio_read(dev, vp->phys[0], MII_BMSR);
d9e46de3
TC		 1924 if (!(mii_status & BMSR_LSTATUS)) {
1925 /* Re-read to get actual link status */
1926 mii_status = mdio_read(dev, vp->phys[0], MII_BMSR);
1927 }
1da177e4
LT		 1928 ok = 1;
1929 if (vortex_debug > 2)
1930 printk(KERN_DEBUG "%s: MII transceiver has status %4.4x.\n",
1931 dev->name, mii_status);
1932 if (mii_status & BMSR_LSTATUS) {
106427e6 1933 int mii_reg5 = mdio_read(dev, vp->phys[0], MII_LPA);
1da177e4
LT		 1934 if (! vp->force_fd && mii_reg5 != 0xffff) {
1935 int duplex;
1936
1937 mii_reg5 &= vp->advertising;
1938 duplex = (mii_reg5&0x0100) || (mii_reg5 & 0x01C0) == 0x0040;
1939 if (vp->full_duplex != duplex) {
1940 vp->full_duplex = duplex;
1941 printk(KERN_INFO "%s: Setting %s-duplex based on MII "
1942 "#%d link partner capability of %4.4x.\n",
1943 dev->name, vp->full_duplex ? "full" : "half",
1944 vp->phys[0], mii_reg5);
1945 /* Set the full-duplex bit. */
1946 EL3WINDOW(3);
62afe595 1947 iowrite16( (vp->full_duplex ? 0x20 : 0) |
1da177e4
LT		 1948 (vp->large_frames ? 0x40 : 0) |
1949 ((vp->full_duplex && vp->flow_ctrl && vp->partner_flow_ctrl) ? 0x100 : 0),
1950 ioaddr + Wn3_MAC_Ctrl);
1951 if (vortex_debug > 1)
1952 printk(KERN_DEBUG "Setting duplex in Wn3_MAC_Ctrl\n");
1953 /* AKPM: bug: should reset Tx and Rx after setting Duplex. Page 180 */
1954 }
1955 }
1956 netif_carrier_on(dev);
1957 } else {
1958 netif_carrier_off(dev);
1959 }
1960 spin_unlock_bh(&vp->lock);
1961 }
1962 break;
1963 default: /* Other media types handled by Tx timeouts. */
1964 if (vortex_debug > 1)
1965 printk(KERN_DEBUG "%s: Media %s has no indication, %x.\n",
1966 dev->name, media_tbl[dev->if_port].name, media_status);
1967 ok = 1;
1968 }
1969 if ( ! ok) {
1970 unsigned int config;
1971
1972 do {
1973 dev->if_port = media_tbl[dev->if_port].next;
1974 } while ( ! (vp->available_media & media_tbl[dev->if_port].mask));
1975 if (dev->if_port == XCVR_Default) { /* Go back to default. */
1976 dev->if_port = vp->default_media;
1977 if (vortex_debug > 1)
1978 printk(KERN_DEBUG "%s: Media selection failing, using default "
1979 "%s port.\n",
1980 dev->name, media_tbl[dev->if_port].name);
1981 } else {
1982 if (vortex_debug > 1)
1983 printk(KERN_DEBUG "%s: Media selection failed, now trying "
1984 "%s port.\n",
1985 dev->name, media_tbl[dev->if_port].name);
1986 next_tick = media_tbl[dev->if_port].wait;
1987 }
62afe595 1988 iowrite16((media_status & ~(Media_10TP|Media_SQE)) |
1da177e4
LT		 1989 media_tbl[dev->if_port].media_bits, ioaddr + Wn4_Media);
1990
1991 EL3WINDOW(3);
62afe595 1992 config = ioread32(ioaddr + Wn3_Config);
1da177e4 1993 config = BFINS(config, dev->if_port, 20, 4);
62afe595 1994 iowrite32(config, ioaddr + Wn3_Config);
1da177e4 1995
62afe595 1996 iowrite16(dev->if_port == XCVR_10base2 ? StartCoax : StopCoax,
1da177e4
LT		 1997 ioaddr + EL3_CMD);
1998 if (vortex_debug > 1)
1999 printk(KERN_DEBUG "wrote 0x%08x to Wn3_Config\n", config);
2000 /* AKPM: FIXME: Should reset Rx & Tx here. P60 of 3c90xc.pdf */
2001 }
2002 EL3WINDOW(old_window);
2003 enable_irq(dev->irq);
2004
2005leave_media_alone:
2006 if (vortex_debug > 2)
2007 printk(KERN_DEBUG "%s: Media selection timer finished, %s.\n",
2008 dev->name, media_tbl[dev->if_port].name);
2009
2010 mod_timer(&vp->timer, RUN_AT(next_tick));
2011 if (vp->deferred)
62afe595 2012 iowrite16(FakeIntr, ioaddr + EL3_CMD);
1da177e4
LT		 2013 return;
2014}
2015
2016static void vortex_tx_timeout(struct net_device *dev)
2017{
2018 struct vortex_private *vp = netdev_priv(dev);
62afe595 2019 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 2020
2021 printk(KERN_ERR "%s: transmit timed out, tx_status %2.2x status %4.4x.\n",
62afe595
JL		 2022 dev->name, ioread8(ioaddr + TxStatus),
2023 ioread16(ioaddr + EL3_STATUS));
1da177e4
LT		 2024 EL3WINDOW(4);
2025 printk(KERN_ERR " diagnostics: net %04x media %04x dma %08x fifo %04x\n",
62afe595
JL		 2026 ioread16(ioaddr + Wn4_NetDiag),
2027 ioread16(ioaddr + Wn4_Media),
2028 ioread32(ioaddr + PktStatus),
2029 ioread16(ioaddr + Wn4_FIFODiag));
1da177e4 2030 /* Slight code bloat to be user friendly. */
62afe595 2031 if ((ioread8(ioaddr + TxStatus) & 0x88) == 0x88)
1da177e4
LT		 2032 printk(KERN_ERR "%s: Transmitter encountered 16 collisions --"
2033 " network cable problem?\n", dev->name);
62afe595 2034 if (ioread16(ioaddr + EL3_STATUS) & IntLatch) {
1da177e4
LT		 2035 printk(KERN_ERR "%s: Interrupt posted but not delivered --"
2036 " IRQ blocked by another device?\n", dev->name);
2037 /* Bad idea here.. but we might as well handle a few events. */
2038 {
2039 /*
2040 * Block interrupts because vortex_interrupt does a bare spin_lock()
2041 */
2042 unsigned long flags;
2043 local_irq_save(flags);
2044 if (vp->full_bus_master_tx)
2045 boomerang_interrupt(dev->irq, dev, NULL);
2046 else
2047 vortex_interrupt(dev->irq, dev, NULL);
2048 local_irq_restore(flags);
2049 }
2050 }
2051
2052 if (vortex_debug > 0)
2053 dump_tx_ring(dev);
2054
2055 issue_and_wait(dev, TxReset);
2056
2057 vp->stats.tx_errors++;
2058 if (vp->full_bus_master_tx) {
2059 printk(KERN_DEBUG "%s: Resetting the Tx ring pointer.\n", dev->name);
62afe595
JL		 2060 if (vp->cur_tx - vp->dirty_tx > 0 && ioread32(ioaddr + DownListPtr) == 0)
2061 iowrite32(vp->tx_ring_dma + (vp->dirty_tx % TX_RING_SIZE) * sizeof(struct boom_tx_desc),
1da177e4
LT		 2062 ioaddr + DownListPtr);
2063 if (vp->cur_tx - vp->dirty_tx < TX_RING_SIZE)
2064 netif_wake_queue (dev);
2065 if (vp->drv_flags & IS_BOOMERANG)
62afe595
JL		 2066 iowrite8(PKT_BUF_SZ>>8, ioaddr + TxFreeThreshold);
2067 iowrite16(DownUnstall, ioaddr + EL3_CMD);
1da177e4
LT		 2068 } else {
2069 vp->stats.tx_dropped++;
2070 netif_wake_queue(dev);
2071 }
2072
2073 /* Issue Tx Enable */
62afe595 2074 iowrite16(TxEnable, ioaddr + EL3_CMD);
1da177e4
LT		 2075 dev->trans_start = jiffies;
2076
2077 /* Switch to register set 7 for normal use. */
2078 EL3WINDOW(7);
2079}
2080
2081/*
2082 * Handle uncommon interrupt sources. This is a separate routine to minimize
2083 * the cache impact.
2084 */
2085static void
2086vortex_error(struct net_device *dev, int status)
2087{
2088 struct vortex_private *vp = netdev_priv(dev);
62afe595 2089 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 2090 int do_tx_reset = 0, reset_mask = 0;
2091 unsigned char tx_status = 0;
2092
2093 if (vortex_debug > 2) {
2094 printk(KERN_ERR "%s: vortex_error(), status=0x%x\n", dev->name, status);
2095 }
2096
2097 if (status & TxComplete) { /* Really "TxError" for us. */
62afe595 2098 tx_status = ioread8(ioaddr + TxStatus);
1da177e4
LT		 2099 /* Presumably a tx-timeout. We must merely re-enable. */
2100 if (vortex_debug > 2
2101 || (tx_status != 0x88 && vortex_debug > 0)) {
2102 printk(KERN_ERR "%s: Transmit error, Tx status register %2.2x.\n",
2103 dev->name, tx_status);
2104 if (tx_status == 0x82) {
2105 printk(KERN_ERR "Probably a duplex mismatch. See "
2106 "Documentation/networking/vortex.txt\n");
2107 }
2108 dump_tx_ring(dev);
2109 }
2110 if (tx_status & 0x14) vp->stats.tx_fifo_errors++;
2111 if (tx_status & 0x38) vp->stats.tx_aborted_errors++;
62afe595 2112 iowrite8(0, ioaddr + TxStatus);
1da177e4
LT		 2113 if (tx_status & 0x30) { /* txJabber or txUnderrun */
2114 do_tx_reset = 1;
8d1d0340
SK		 2115 } else if (tx_status & 0x08) { /* maxCollisions */
2116 vp->xstats.tx_max_collisions++;
2117 if (vp->drv_flags & MAX_COLLISION_RESET) {
2118 do_tx_reset = 1;
2119 reset_mask = 0x0108; /* Reset interface logic, but not download logic */
2120 }
1da177e4 2121 } else { /* Merely re-enable the transmitter. */
62afe595 2122 iowrite16(TxEnable, ioaddr + EL3_CMD);
1da177e4
LT		 2123 }
2124 }
2125
2126 if (status & RxEarly) { /* Rx early is unused. */
2127 vortex_rx(dev);
62afe595 2128 iowrite16(AckIntr | RxEarly, ioaddr + EL3_CMD);
1da177e4
LT		 2129 }
2130 if (status & StatsFull) { /* Empty statistics. */
2131 static int DoneDidThat;
2132 if (vortex_debug > 4)
2133 printk(KERN_DEBUG "%s: Updating stats.\n", dev->name);
2134 update_stats(ioaddr, dev);
2135 /* HACK: Disable statistics as an interrupt source. */
2136 /* This occurs when we have the wrong media type! */
2137 if (DoneDidThat == 0 &&
62afe595 2138 ioread16(ioaddr + EL3_STATUS) & StatsFull) {
1da177e4
LT		 2139 printk(KERN_WARNING "%s: Updating statistics failed, disabling "
2140 "stats as an interrupt source.\n", dev->name);
2141 EL3WINDOW(5);
62afe595 2142 iowrite16(SetIntrEnb | (ioread16(ioaddr + 10) & ~StatsFull), ioaddr + EL3_CMD);
1da177e4
LT		 2143 vp->intr_enable &= ~StatsFull;
2144 EL3WINDOW(7);
2145 DoneDidThat++;
2146 }
2147 }
2148 if (status & IntReq) { /* Restore all interrupt sources. */
62afe595
JL		 2149 iowrite16(vp->status_enable, ioaddr + EL3_CMD);
2150 iowrite16(vp->intr_enable, ioaddr + EL3_CMD);
1da177e4
LT		 2151 }
2152 if (status & HostError) {
2153 u16 fifo_diag;
2154 EL3WINDOW(4);
62afe595 2155 fifo_diag = ioread16(ioaddr + Wn4_FIFODiag);
1da177e4
LT		 2156 printk(KERN_ERR "%s: Host error, FIFO diagnostic register %4.4x.\n",
2157 dev->name, fifo_diag);
2158 /* Adapter failure requires Tx/Rx reset and reinit. */
2159 if (vp->full_bus_master_tx) {
62afe595 2160 int bus_status = ioread32(ioaddr + PktStatus);
1da177e4
LT		 2161 /* 0x80000000 PCI master abort. */
2162 /* 0x40000000 PCI target abort. */
2163 if (vortex_debug)
2164 printk(KERN_ERR "%s: PCI bus error, bus status %8.8x\n", dev->name, bus_status);
2165
2166 /* In this case, blow the card away */
2167 /* Must not enter D3 or we can't legally issue the reset! */
2168 vortex_down(dev, 0);
2169 issue_and_wait(dev, TotalReset | 0xff);
2170 vortex_up(dev); /* AKPM: bug. vortex_up() assumes that the rx ring is full. It may not be. */
2171 } else if (fifo_diag & 0x0400)
2172 do_tx_reset = 1;
2173 if (fifo_diag & 0x3000) {
2174 /* Reset Rx fifo and upload logic */
2175 issue_and_wait(dev, RxReset|0x07);
2176 /* Set the Rx filter to the current state. */
2177 set_rx_mode(dev);
2178 /* enable 802.1q VLAN tagged frames */
2179 set_8021q_mode(dev, 1);
62afe595
JL		 2180 iowrite16(RxEnable, ioaddr + EL3_CMD); /* Re-enable the receiver. */
2181 iowrite16(AckIntr | HostError, ioaddr + EL3_CMD);
1da177e4
LT		 2182 }
2183 }
2184
2185 if (do_tx_reset) {
2186 issue_and_wait(dev, TxReset|reset_mask);
62afe595 2187 iowrite16(TxEnable, ioaddr + EL3_CMD);
1da177e4
LT		 2188 if (!vp->full_bus_master_tx)
2189 netif_wake_queue(dev);
2190 }
2191}
2192
2193static int
2194vortex_start_xmit(struct sk_buff *skb, struct net_device *dev)
2195{
2196 struct vortex_private *vp = netdev_priv(dev);
62afe595 2197 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 2198
2199 /* Put out the doubleword header... */
62afe595 2200 iowrite32(skb->len, ioaddr + TX_FIFO);
1da177e4
LT		 2201 if (vp->bus_master) {
2202 /* Set the bus-master controller to transfer the packet. */
2203 int len = (skb->len + 3) & ~3;
62afe595 2204 iowrite32( vp->tx_skb_dma = pci_map_single(VORTEX_PCI(vp), skb->data, len, PCI_DMA_TODEVICE),
1da177e4 2205 ioaddr + Wn7_MasterAddr);
62afe595 2206 iowrite16(len, ioaddr + Wn7_MasterLen);
1da177e4 2207 vp->tx_skb = skb;
62afe595 2208 iowrite16(StartDMADown, ioaddr + EL3_CMD);
1da177e4
LT		 2209 /* netif_wake_queue() will be called at the DMADone interrupt. */
2210 } else {
2211 /* ... and the packet rounded to a doubleword. */
62afe595 2212 iowrite32_rep(ioaddr + TX_FIFO, skb->data, (skb->len + 3) >> 2);
1da177e4 2213 dev_kfree_skb (skb);
62afe595 2214 if (ioread16(ioaddr + TxFree) > 1536) {
1da177e4
LT		 2215 netif_start_queue (dev); /* AKPM: redundant? */
2216 } else {
2217 /* Interrupt us when the FIFO has room for max-sized packet. */
2218 netif_stop_queue(dev);
62afe595 2219 iowrite16(SetTxThreshold + (1536>>2), ioaddr + EL3_CMD);
1da177e4
LT		 2220 }
2221 }
2222
2223 dev->trans_start = jiffies;
2224
2225 /* Clear the Tx status stack. */
2226 {
2227 int tx_status;
2228 int i = 32;
2229
62afe595 2230 while (--i > 0 && (tx_status = ioread8(ioaddr + TxStatus)) > 0) {
1da177e4
LT		 2231 if (tx_status & 0x3C) { /* A Tx-disabling error occurred. */
2232 if (vortex_debug > 2)
2233 printk(KERN_DEBUG "%s: Tx error, status %2.2x.\n",
2234 dev->name, tx_status);
2235 if (tx_status & 0x04) vp->stats.tx_fifo_errors++;
2236 if (tx_status & 0x38) vp->stats.tx_aborted_errors++;
2237 if (tx_status & 0x30) {
2238 issue_and_wait(dev, TxReset);
2239 }
62afe595 2240 iowrite16(TxEnable, ioaddr + EL3_CMD);
1da177e4 2241 }
62afe595 2242 iowrite8(0x00, ioaddr + TxStatus); /* Pop the status stack. */
1da177e4
LT		 2243 }
2244 }
2245 return 0;
2246}
2247
2248static int
2249boomerang_start_xmit(struct sk_buff *skb, struct net_device *dev)
2250{
2251 struct vortex_private *vp = netdev_priv(dev);
62afe595 2252 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 2253 /* Calculate the next Tx descriptor entry. */
2254 int entry = vp->cur_tx % TX_RING_SIZE;
2255 struct boom_tx_desc *prev_entry = &vp->tx_ring[(vp->cur_tx-1) % TX_RING_SIZE];
2256 unsigned long flags;
2257
2258 if (vortex_debug > 6) {
2259 printk(KERN_DEBUG "boomerang_start_xmit()\n");
0f667ff5
JL		 2260 printk(KERN_DEBUG "%s: Trying to send a packet, Tx index %d.\n",
2261 dev->name, vp->cur_tx);
1da177e4
LT		 2262 }
2263
2264 if (vp->cur_tx - vp->dirty_tx >= TX_RING_SIZE) {
2265 if (vortex_debug > 0)
2266 printk(KERN_WARNING "%s: BUG! Tx Ring full, refusing to send buffer.\n",
2267 dev->name);
2268 netif_stop_queue(dev);
2269 return 1;
2270 }
2271
2272 vp->tx_skbuff[entry] = skb;
2273
2274 vp->tx_ring[entry].next = 0;
2275#if DO_ZEROCOPY
2276 if (skb->ip_summed != CHECKSUM_HW)
2277 vp->tx_ring[entry].status = cpu_to_le32(skb->len | TxIntrUploaded);
2278 else
2279 vp->tx_ring[entry].status = cpu_to_le32(skb->len | TxIntrUploaded | AddTCPChksum | AddUDPChksum);
2280
2281 if (!skb_shinfo(skb)->nr_frags) {
2282 vp->tx_ring[entry].frag[0].addr = cpu_to_le32(pci_map_single(VORTEX_PCI(vp), skb->data,
2283 skb->len, PCI_DMA_TODEVICE));
2284 vp->tx_ring[entry].frag[0].length = cpu_to_le32(skb->len | LAST_FRAG);
2285 } else {
2286 int i;
2287
2288 vp->tx_ring[entry].frag[0].addr = cpu_to_le32(pci_map_single(VORTEX_PCI(vp), skb->data,
2289 skb->len-skb->data_len, PCI_DMA_TODEVICE));
2290 vp->tx_ring[entry].frag[0].length = cpu_to_le32(skb->len-skb->data_len);
2291
2292 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
2293 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2294
2295 vp->tx_ring[entry].frag[i+1].addr =
2296 cpu_to_le32(pci_map_single(VORTEX_PCI(vp),
2297 (void*)page_address(frag->page) + frag->page_offset,
2298 frag->size, PCI_DMA_TODEVICE));
2299
2300 if (i == skb_shinfo(skb)->nr_frags-1)
2301 vp->tx_ring[entry].frag[i+1].length = cpu_to_le32(frag->size|LAST_FRAG);
2302 else
2303 vp->tx_ring[entry].frag[i+1].length = cpu_to_le32(frag->size);
2304 }
2305 }
2306#else
2307 vp->tx_ring[entry].addr = cpu_to_le32(pci_map_single(VORTEX_PCI(vp), skb->data, skb->len, PCI_DMA_TODEVICE));
2308 vp->tx_ring[entry].length = cpu_to_le32(skb->len | LAST_FRAG);
2309 vp->tx_ring[entry].status = cpu_to_le32(skb->len | TxIntrUploaded);
2310#endif
2311
2312 spin_lock_irqsave(&vp->lock, flags);
2313 /* Wait for the stall to complete. */
2314 issue_and_wait(dev, DownStall);
2315 prev_entry->next = cpu_to_le32(vp->tx_ring_dma + entry * sizeof(struct boom_tx_desc));
62afe595
JL		 2316 if (ioread32(ioaddr + DownListPtr) == 0) {
2317 iowrite32(vp->tx_ring_dma + entry * sizeof(struct boom_tx_desc), ioaddr + DownListPtr);
1da177e4
LT		 2318 vp->queued_packet++;
2319 }
2320
2321 vp->cur_tx++;
2322 if (vp->cur_tx - vp->dirty_tx > TX_RING_SIZE - 1) {
2323 netif_stop_queue (dev);
2324 } else { /* Clear previous interrupt enable. */
2325#if defined(tx_interrupt_mitigation)
2326 /* Dubious. If in boomeang_interrupt "faster" cyclone ifdef
2327 * were selected, this would corrupt DN_COMPLETE. No?
2328 */
2329 prev_entry->status &= cpu_to_le32(~TxIntrUploaded);
2330#endif
2331 }
62afe595 2332 iowrite16(DownUnstall, ioaddr + EL3_CMD);
1da177e4
LT		 2333 spin_unlock_irqrestore(&vp->lock, flags);
2334 dev->trans_start = jiffies;
2335 return 0;
2336}
2337
2338/* The interrupt handler does all of the Rx thread work and cleans up
2339 after the Tx thread. */
2340
2341/*
2342 * This is the ISR for the vortex series chips.
2343 * full_bus_master_tx == 0 && full_bus_master_rx == 0
2344 */
2345
2346static irqreturn_t
2347vortex_interrupt(int irq, void *dev_id, struct pt_regs *regs)
2348{
2349 struct net_device *dev = dev_id;
2350 struct vortex_private *vp = netdev_priv(dev);
62afe595 2351 void __iomem *ioaddr;
1da177e4
LT		 2352 int status;
2353 int work_done = max_interrupt_work;
2354 int handled = 0;
2355
62afe595 2356 ioaddr = vp->ioaddr;
1da177e4
LT		 2357 spin_lock(&vp->lock);
2358
62afe595 2359 status = ioread16(ioaddr + EL3_STATUS);
1da177e4
LT		 2360
2361 if (vortex_debug > 6)
2362 printk("vortex_interrupt(). status=0x%4x\n", status);
2363
2364 if ((status & IntLatch) == 0)
2365 goto handler_exit; /* No interrupt: shared IRQs cause this */
2366 handled = 1;
2367
2368 if (status & IntReq) {
2369 status |= vp->deferred;
2370 vp->deferred = 0;
2371 }
2372
2373 if (status == 0xffff) /* h/w no longer present (hotplug)? */
2374 goto handler_exit;
2375
2376 if (vortex_debug > 4)
2377 printk(KERN_DEBUG "%s: interrupt, status %4.4x, latency %d ticks.\n",
62afe595 2378 dev->name, status, ioread8(ioaddr + Timer));
1da177e4
LT		 2379
2380 do {
2381 if (vortex_debug > 5)
2382 printk(KERN_DEBUG "%s: In interrupt loop, status %4.4x.\n",
2383 dev->name, status);
2384 if (status & RxComplete)
2385 vortex_rx(dev);
2386
2387 if (status & TxAvailable) {
2388 if (vortex_debug > 5)
2389 printk(KERN_DEBUG " TX room bit was handled.\n");
2390 /* There's room in the FIFO for a full-sized packet. */
62afe595 2391 iowrite16(AckIntr | TxAvailable, ioaddr + EL3_CMD);
1da177e4
LT		 2392 netif_wake_queue (dev);
2393 }
2394
2395 if (status & DMADone) {
62afe595
JL		 2396 if (ioread16(ioaddr + Wn7_MasterStatus) & 0x1000) {
2397 iowrite16(0x1000, ioaddr + Wn7_MasterStatus); /* Ack the event. */
1da177e4
LT		 2398 pci_unmap_single(VORTEX_PCI(vp), vp->tx_skb_dma, (vp->tx_skb->len + 3) & ~3, PCI_DMA_TODEVICE);
2399 dev_kfree_skb_irq(vp->tx_skb); /* Release the transferred buffer */
62afe595 2400 if (ioread16(ioaddr + TxFree) > 1536) {
1da177e4
LT		 2401 /*
2402 * AKPM: FIXME: I don't think we need this. If the queue was stopped due to
2403 * insufficient FIFO room, the TxAvailable test will succeed and call
2404 * netif_wake_queue()
2405 */
2406 netif_wake_queue(dev);
2407 } else { /* Interrupt when FIFO has room for max-sized packet. */
62afe595 2408 iowrite16(SetTxThreshold + (1536>>2), ioaddr + EL3_CMD);
1da177e4
LT		 2409 netif_stop_queue(dev);
2410 }
2411 }
2412 }
2413 /* Check for all uncommon interrupts at once. */
2414 if (status & (HostError | RxEarly | StatsFull | TxComplete | IntReq)) {
2415 if (status == 0xffff)
2416 break;
2417 vortex_error(dev, status);
2418 }
2419
2420 if (--work_done < 0) {
2421 printk(KERN_WARNING "%s: Too much work in interrupt, status "
2422 "%4.4x.\n", dev->name, status);
2423 /* Disable all pending interrupts. */
2424 do {
2425 vp->deferred |= status;
62afe595 2426 iowrite16(SetStatusEnb | (~vp->deferred & vp->status_enable),
1da177e4 2427 ioaddr + EL3_CMD);
62afe595
JL		 2428 iowrite16(AckIntr | (vp->deferred & 0x7ff), ioaddr + EL3_CMD);
2429 } while ((status = ioread16(ioaddr + EL3_CMD)) & IntLatch);
1da177e4
LT		 2430 /* The timer will reenable interrupts. */
2431 mod_timer(&vp->timer, jiffies + 1*HZ);
2432 break;
2433 }
2434 /* Acknowledge the IRQ. */
62afe595
JL		 2435 iowrite16(AckIntr | IntReq | IntLatch, ioaddr + EL3_CMD);
2436 } while ((status = ioread16(ioaddr + EL3_STATUS)) & (IntLatch | RxComplete));
1da177e4
LT		 2437
2438 if (vortex_debug > 4)
2439 printk(KERN_DEBUG "%s: exiting interrupt, status %4.4x.\n",
2440 dev->name, status);
2441handler_exit:
2442 spin_unlock(&vp->lock);
2443 return IRQ_RETVAL(handled);
2444}
2445
2446/*
2447 * This is the ISR for the boomerang series chips.
2448 * full_bus_master_tx == 1 && full_bus_master_rx == 1
2449 */
2450
2451static irqreturn_t
2452boomerang_interrupt(int irq, void *dev_id, struct pt_regs *regs)
2453{
2454 struct net_device *dev = dev_id;
2455 struct vortex_private *vp = netdev_priv(dev);
62afe595 2456 void __iomem *ioaddr;
1da177e4
LT		 2457 int status;
2458 int work_done = max_interrupt_work;
2459
62afe595 2460 ioaddr = vp->ioaddr;
1da177e4
LT		 2461
2462 /*
2463 * It seems dopey to put the spinlock this early, but we could race against vortex_tx_timeout
2464 * and boomerang_start_xmit
2465 */
2466 spin_lock(&vp->lock);
2467
62afe595 2468 status = ioread16(ioaddr + EL3_STATUS);
1da177e4
LT		 2469
2470 if (vortex_debug > 6)
2471 printk(KERN_DEBUG "boomerang_interrupt. status=0x%4x\n", status);
2472
2473 if ((status & IntLatch) == 0)
2474 goto handler_exit; /* No interrupt: shared IRQs can cause this */
2475
2476 if (status == 0xffff) { /* h/w no longer present (hotplug)? */
2477 if (vortex_debug > 1)
2478 printk(KERN_DEBUG "boomerang_interrupt(1): status = 0xffff\n");
2479 goto handler_exit;
2480 }
2481
2482 if (status & IntReq) {
2483 status |= vp->deferred;
2484 vp->deferred = 0;
2485 }
2486
2487 if (vortex_debug > 4)
2488 printk(KERN_DEBUG "%s: interrupt, status %4.4x, latency %d ticks.\n",
62afe595 2489 dev->name, status, ioread8(ioaddr + Timer));
1da177e4
LT		 2490 do {
2491 if (vortex_debug > 5)
2492 printk(KERN_DEBUG "%s: In interrupt loop, status %4.4x.\n",
2493 dev->name, status);
2494 if (status & UpComplete) {
62afe595 2495 iowrite16(AckIntr | UpComplete, ioaddr + EL3_CMD);
1da177e4
LT		 2496 if (vortex_debug > 5)
2497 printk(KERN_DEBUG "boomerang_interrupt->boomerang_rx\n");
2498 boomerang_rx(dev);
2499 }
2500
2501 if (status & DownComplete) {
2502 unsigned int dirty_tx = vp->dirty_tx;
2503
62afe595 2504 iowrite16(AckIntr | DownComplete, ioaddr + EL3_CMD);
1da177e4
LT		 2505 while (vp->cur_tx - dirty_tx > 0) {
2506 int entry = dirty_tx % TX_RING_SIZE;
2507#if 1 /* AKPM: the latter is faster, but cyclone-only */
62afe595 2508 if (ioread32(ioaddr + DownListPtr) ==
1da177e4
LT		 2509 vp->tx_ring_dma + entry * sizeof(struct boom_tx_desc))
2510 break; /* It still hasn't been processed. */
2511#else
2512 if ((vp->tx_ring[entry].status & DN_COMPLETE) == 0)
2513 break; /* It still hasn't been processed. */
2514#endif
2515
2516 if (vp->tx_skbuff[entry]) {
2517 struct sk_buff *skb = vp->tx_skbuff[entry];
2518#if DO_ZEROCOPY
2519 int i;
2520 for (i=0; i<=skb_shinfo(skb)->nr_frags; i++)
2521 pci_unmap_single(VORTEX_PCI(vp),
2522 le32_to_cpu(vp->tx_ring[entry].frag[i].addr),
2523 le32_to_cpu(vp->tx_ring[entry].frag[i].length)&0xFFF,
2524 PCI_DMA_TODEVICE);
2525#else
2526 pci_unmap_single(VORTEX_PCI(vp),
2527 le32_to_cpu(vp->tx_ring[entry].addr), skb->len, PCI_DMA_TODEVICE);
2528#endif
2529 dev_kfree_skb_irq(skb);
2530 vp->tx_skbuff[entry] = NULL;
2531 } else {
2532 printk(KERN_DEBUG "boomerang_interrupt: no skb!\n");
2533 }
2534 /* vp->stats.tx_packets++; Counted below. */
2535 dirty_tx++;
2536 }
2537 vp->dirty_tx = dirty_tx;
2538 if (vp->cur_tx - dirty_tx <= TX_RING_SIZE - 1) {
2539 if (vortex_debug > 6)
2540 printk(KERN_DEBUG "boomerang_interrupt: wake queue\n");
2541 netif_wake_queue (dev);
2542 }
2543 }
2544
2545 /* Check for all uncommon interrupts at once. */
2546 if (status & (HostError | RxEarly | StatsFull | TxComplete | IntReq))
2547 vortex_error(dev, status);
2548
2549 if (--work_done < 0) {
2550 printk(KERN_WARNING "%s: Too much work in interrupt, status "
2551 "%4.4x.\n", dev->name, status);
2552 /* Disable all pending interrupts. */
2553 do {
2554 vp->deferred |= status;
62afe595 2555 iowrite16(SetStatusEnb | (~vp->deferred & vp->status_enable),
1da177e4 2556 ioaddr + EL3_CMD);
62afe595
JL		 2557 iowrite16(AckIntr | (vp->deferred & 0x7ff), ioaddr + EL3_CMD);
2558 } while ((status = ioread16(ioaddr + EL3_CMD)) & IntLatch);
1da177e4
LT		 2559 /* The timer will reenable interrupts. */
2560 mod_timer(&vp->timer, jiffies + 1*HZ);
2561 break;
2562 }
2563 /* Acknowledge the IRQ. */
62afe595 2564 iowrite16(AckIntr | IntReq | IntLatch, ioaddr + EL3_CMD);
1da177e4 2565 if (vp->cb_fn_base) /* The PCMCIA people are idiots. */
62afe595 2566 iowrite32(0x8000, vp->cb_fn_base + 4);
1da177e4 2567
62afe595 2568 } while ((status = ioread16(ioaddr + EL3_STATUS)) & IntLatch);
1da177e4
LT		 2569
2570 if (vortex_debug > 4)
2571 printk(KERN_DEBUG "%s: exiting interrupt, status %4.4x.\n",
2572 dev->name, status);
2573handler_exit:
2574 spin_unlock(&vp->lock);
2575 return IRQ_HANDLED;
2576}
2577
2578static int vortex_rx(struct net_device *dev)
2579{
2580 struct vortex_private *vp = netdev_priv(dev);
62afe595 2581 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 2582 int i;
2583 short rx_status;
2584
2585 if (vortex_debug > 5)
2586 printk(KERN_DEBUG "vortex_rx(): status %4.4x, rx_status %4.4x.\n",
62afe595
JL		 2587 ioread16(ioaddr+EL3_STATUS), ioread16(ioaddr+RxStatus));
2588 while ((rx_status = ioread16(ioaddr + RxStatus)) > 0) {
1da177e4 2589 if (rx_status & 0x4000) { /* Error, update stats. */
62afe595 2590 unsigned char rx_error = ioread8(ioaddr + RxErrors);
1da177e4
LT		 2591 if (vortex_debug > 2)
2592 printk(KERN_DEBUG " Rx error: status %2.2x.\n", rx_error);
2593 vp->stats.rx_errors++;
2594 if (rx_error & 0x01) vp->stats.rx_over_errors++;
2595 if (rx_error & 0x02) vp->stats.rx_length_errors++;
2596 if (rx_error & 0x04) vp->stats.rx_frame_errors++;
2597 if (rx_error & 0x08) vp->stats.rx_crc_errors++;
2598 if (rx_error & 0x10) vp->stats.rx_length_errors++;
2599 } else {
2600 /* The packet length: up to 4.5K!. */
2601 int pkt_len = rx_status & 0x1fff;
2602 struct sk_buff *skb;
2603
2604 skb = dev_alloc_skb(pkt_len + 5);
2605 if (vortex_debug > 4)
2606 printk(KERN_DEBUG "Receiving packet size %d status %4.4x.\n",
2607 pkt_len, rx_status);
2608 if (skb != NULL) {
2609 skb->dev = dev;
2610 skb_reserve(skb, 2); /* Align IP on 16 byte boundaries */
2611 /* 'skb_put()' points to the start of sk_buff data area. */
2612 if (vp->bus_master &&
62afe595 2613 ! (ioread16(ioaddr + Wn7_MasterStatus) & 0x8000)) {
1da177e4
LT		 2614 dma_addr_t dma = pci_map_single(VORTEX_PCI(vp), skb_put(skb, pkt_len),
2615 pkt_len, PCI_DMA_FROMDEVICE);
62afe595
JL		 2616 iowrite32(dma, ioaddr + Wn7_MasterAddr);
2617 iowrite16((skb->len + 3) & ~3, ioaddr + Wn7_MasterLen);
2618 iowrite16(StartDMAUp, ioaddr + EL3_CMD);
2619 while (ioread16(ioaddr + Wn7_MasterStatus) & 0x8000)
1da177e4
LT		 2620 ;
2621 pci_unmap_single(VORTEX_PCI(vp), dma, pkt_len, PCI_DMA_FROMDEVICE);
2622 } else {
62afe595
JL		 2623 ioread32_rep(ioaddr + RX_FIFO,
2624 skb_put(skb, pkt_len),
2625 (pkt_len + 3) >> 2);
1da177e4 2626 }
62afe595 2627 iowrite16(RxDiscard, ioaddr + EL3_CMD); /* Pop top Rx packet. */
1da177e4
LT		 2628 skb->protocol = eth_type_trans(skb, dev);
2629 netif_rx(skb);
2630 dev->last_rx = jiffies;
2631 vp->stats.rx_packets++;
2632 /* Wait a limited time to go to next packet. */
2633 for (i = 200; i >= 0; i--)
62afe595 2634 if ( ! (ioread16(ioaddr + EL3_STATUS) & CmdInProgress))
1da177e4
LT		 2635 break;
2636 continue;
2637 } else if (vortex_debug > 0)
2638 printk(KERN_NOTICE "%s: No memory to allocate a sk_buff of "
2639 "size %d.\n", dev->name, pkt_len);
35b30674 2640 vp->stats.rx_dropped++;
1da177e4 2641 }
1da177e4
LT		 2642 issue_and_wait(dev, RxDiscard);
2643 }
2644
2645 return 0;
2646}
2647
2648static int
2649boomerang_rx(struct net_device *dev)
2650{
2651 struct vortex_private *vp = netdev_priv(dev);
2652 int entry = vp->cur_rx % RX_RING_SIZE;
62afe595 2653 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 2654 int rx_status;
2655 int rx_work_limit = vp->dirty_rx + RX_RING_SIZE - vp->cur_rx;
2656
2657 if (vortex_debug > 5)
62afe595 2658 printk(KERN_DEBUG "boomerang_rx(): status %4.4x\n", ioread16(ioaddr+EL3_STATUS));
1da177e4
LT		 2659
2660 while ((rx_status = le32_to_cpu(vp->rx_ring[entry].status)) & RxDComplete){
2661 if (--rx_work_limit < 0)
2662 break;
2663 if (rx_status & RxDError) { /* Error, update stats. */
2664 unsigned char rx_error = rx_status >> 16;
2665 if (vortex_debug > 2)
2666 printk(KERN_DEBUG " Rx error: status %2.2x.\n", rx_error);
2667 vp->stats.rx_errors++;
2668 if (rx_error & 0x01) vp->stats.rx_over_errors++;
2669 if (rx_error & 0x02) vp->stats.rx_length_errors++;
2670 if (rx_error & 0x04) vp->stats.rx_frame_errors++;
2671 if (rx_error & 0x08) vp->stats.rx_crc_errors++;
2672 if (rx_error & 0x10) vp->stats.rx_length_errors++;
2673 } else {
2674 /* The packet length: up to 4.5K!. */
2675 int pkt_len = rx_status & 0x1fff;
2676 struct sk_buff *skb;
2677 dma_addr_t dma = le32_to_cpu(vp->rx_ring[entry].addr);
2678
2679 if (vortex_debug > 4)
2680 printk(KERN_DEBUG "Receiving packet size %d status %4.4x.\n",
2681 pkt_len, rx_status);
2682
2683 /* Check if the packet is long enough to just accept without
2684 copying to a properly sized skbuff. */
2685 if (pkt_len < rx_copybreak && (skb = dev_alloc_skb(pkt_len + 2)) != 0) {
2686 skb->dev = dev;
2687 skb_reserve(skb, 2); /* Align IP on 16 byte boundaries */
2688 pci_dma_sync_single_for_cpu(VORTEX_PCI(vp), dma, PKT_BUF_SZ, PCI_DMA_FROMDEVICE);
2689 /* 'skb_put()' points to the start of sk_buff data area. */
2690 memcpy(skb_put(skb, pkt_len),
689be439 2691 vp->rx_skbuff[entry]->data,
1da177e4
LT		 2692 pkt_len);
2693 pci_dma_sync_single_for_device(VORTEX_PCI(vp), dma, PKT_BUF_SZ, PCI_DMA_FROMDEVICE);
2694 vp->rx_copy++;
2695 } else {
2696 /* Pass up the skbuff already on the Rx ring. */
2697 skb = vp->rx_skbuff[entry];
2698 vp->rx_skbuff[entry] = NULL;
2699 skb_put(skb, pkt_len);
2700 pci_unmap_single(VORTEX_PCI(vp), dma, PKT_BUF_SZ, PCI_DMA_FROMDEVICE);
2701 vp->rx_nocopy++;
2702 }
2703 skb->protocol = eth_type_trans(skb, dev);
2704 { /* Use hardware checksum info. */
2705 int csum_bits = rx_status & 0xee000000;
2706 if (csum_bits &&
2707 (csum_bits == (IPChksumValid | TCPChksumValid) ||
2708 csum_bits == (IPChksumValid | UDPChksumValid))) {
2709 skb->ip_summed = CHECKSUM_UNNECESSARY;
2710 vp->rx_csumhits++;
2711 }
2712 }
2713 netif_rx(skb);
2714 dev->last_rx = jiffies;
2715 vp->stats.rx_packets++;
2716 }
2717 entry = (++vp->cur_rx) % RX_RING_SIZE;
2718 }
2719 /* Refill the Rx ring buffers. */
2720 for (; vp->cur_rx - vp->dirty_rx > 0; vp->dirty_rx++) {
2721 struct sk_buff *skb;
2722 entry = vp->dirty_rx % RX_RING_SIZE;
2723 if (vp->rx_skbuff[entry] == NULL) {
2724 skb = dev_alloc_skb(PKT_BUF_SZ);
2725 if (skb == NULL) {
2726 static unsigned long last_jif;
2727 if ((jiffies - last_jif) > 10 * HZ) {
2728 printk(KERN_WARNING "%s: memory shortage\n", dev->name);
2729 last_jif = jiffies;
2730 }
2731 if ((vp->cur_rx - vp->dirty_rx) == RX_RING_SIZE)
2732 mod_timer(&vp->rx_oom_timer, RUN_AT(HZ * 1));
2733 break; /* Bad news! */
2734 }
2735 skb->dev = dev; /* Mark as being used by this device. */
2736 skb_reserve(skb, 2); /* Align IP on 16 byte boundaries */
689be439 2737 vp->rx_ring[entry].addr = cpu_to_le32(pci_map_single(VORTEX_PCI(vp), skb->data, PKT_BUF_SZ, PCI_DMA_FROMDEVICE));
1da177e4
LT		 2738 vp->rx_skbuff[entry] = skb;
2739 }
2740 vp->rx_ring[entry].status = 0; /* Clear complete bit. */
62afe595 2741 iowrite16(UpUnstall, ioaddr + EL3_CMD);
1da177e4
LT		 2742 }
2743 return 0;
2744}
2745
2746/*
2747 * If we've hit a total OOM refilling the Rx ring we poll once a second
2748 * for some memory. Otherwise there is no way to restart the rx process.
2749 */
2750static void
2751rx_oom_timer(unsigned long arg)
2752{
2753 struct net_device *dev = (struct net_device *)arg;
2754 struct vortex_private *vp = netdev_priv(dev);
2755
2756 spin_lock_irq(&vp->lock);
2757 if ((vp->cur_rx - vp->dirty_rx) == RX_RING_SIZE) /* This test is redundant, but makes me feel good */
2758 boomerang_rx(dev);
2759 if (vortex_debug > 1) {
2760 printk(KERN_DEBUG "%s: rx_oom_timer %s\n", dev->name,
2761 ((vp->cur_rx - vp->dirty_rx) != RX_RING_SIZE) ? "succeeded" : "retrying");
2762 }
2763 spin_unlock_irq(&vp->lock);
2764}
2765
2766static void
2767vortex_down(struct net_device *dev, int final_down)
2768{
2769 struct vortex_private *vp = netdev_priv(dev);
62afe595 2770 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 2771
2772 netif_stop_queue (dev);
2773
2774 del_timer_sync(&vp->rx_oom_timer);
2775 del_timer_sync(&vp->timer);
2776
2777 /* Turn off statistics ASAP. We update vp->stats below. */
62afe595 2778 iowrite16(StatsDisable, ioaddr + EL3_CMD);
1da177e4
LT		 2779
2780 /* Disable the receiver and transmitter. */
62afe595
JL		 2781 iowrite16(RxDisable, ioaddr + EL3_CMD);
2782 iowrite16(TxDisable, ioaddr + EL3_CMD);
1da177e4
LT		 2783
2784 /* Disable receiving 802.1q tagged frames */
2785 set_8021q_mode(dev, 0);
2786
2787 if (dev->if_port == XCVR_10base2)
2788 /* Turn off thinnet power. Green! */
62afe595 2789 iowrite16(StopCoax, ioaddr + EL3_CMD);
1da177e4 2790
62afe595 2791 iowrite16(SetIntrEnb | 0x0000, ioaddr + EL3_CMD);
1da177e4
LT		 2792
2793 update_stats(ioaddr, dev);
2794 if (vp->full_bus_master_rx)
62afe595 2795 iowrite32(0, ioaddr + UpListPtr);
1da177e4 2796 if (vp->full_bus_master_tx)
62afe595 2797 iowrite32(0, ioaddr + DownListPtr);
1da177e4
LT		 2798
2799 if (final_down && VORTEX_PCI(vp)) {
3c8fad18 2800 vp->pm_state_valid = 1;
1da177e4
LT		 2801 pci_save_state(VORTEX_PCI(vp));
2802 acpi_set_WOL(dev);
2803 }
2804}
2805
2806static int
2807vortex_close(struct net_device *dev)
2808{
2809 struct vortex_private *vp = netdev_priv(dev);
62afe595 2810 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 2811 int i;
2812
2813 if (netif_device_present(dev))
2814 vortex_down(dev, 1);
2815
2816 if (vortex_debug > 1) {
2817 printk(KERN_DEBUG"%s: vortex_close() status %4.4x, Tx status %2.2x.\n",
62afe595 2818 dev->name, ioread16(ioaddr + EL3_STATUS), ioread8(ioaddr + TxStatus));
1da177e4
LT		 2819 printk(KERN_DEBUG "%s: vortex close stats: rx_nocopy %d rx_copy %d"
2820 " tx_queued %d Rx pre-checksummed %d.\n",
2821 dev->name, vp->rx_nocopy, vp->rx_copy, vp->queued_packet, vp->rx_csumhits);
2822 }
2823
2824#if DO_ZEROCOPY
32fb5f06
JL		 2825 if (vp->rx_csumhits &&
2826 (vp->drv_flags & HAS_HWCKSM) == 0 &&
2827 (vp->card_idx >= MAX_UNITS || hw_checksums[vp->card_idx] == -1)) {
2828 printk(KERN_WARNING "%s supports hardware checksums, and we're "
2829 "not using them!\n", dev->name);
1da177e4
LT		 2830 }
2831#endif
2832
2833 free_irq(dev->irq, dev);
2834
2835 if (vp->full_bus_master_rx) { /* Free Boomerang bus master Rx buffers. */
2836 for (i = 0; i < RX_RING_SIZE; i++)
2837 if (vp->rx_skbuff[i]) {
2838 pci_unmap_single( VORTEX_PCI(vp), le32_to_cpu(vp->rx_ring[i].addr),
2839 PKT_BUF_SZ, PCI_DMA_FROMDEVICE);
2840 dev_kfree_skb(vp->rx_skbuff[i]);
2841 vp->rx_skbuff[i] = NULL;
2842 }
2843 }
2844 if (vp->full_bus_master_tx) { /* Free Boomerang bus master Tx buffers. */
2845 for (i = 0; i < TX_RING_SIZE; i++) {
2846 if (vp->tx_skbuff[i]) {
2847 struct sk_buff *skb = vp->tx_skbuff[i];
2848#if DO_ZEROCOPY
2849 int k;
2850
2851 for (k=0; k<=skb_shinfo(skb)->nr_frags; k++)
2852 pci_unmap_single(VORTEX_PCI(vp),
2853 le32_to_cpu(vp->tx_ring[i].frag[k].addr),
2854 le32_to_cpu(vp->tx_ring[i].frag[k].length)&0xFFF,
2855 PCI_DMA_TODEVICE);
2856#else
2857 pci_unmap_single(VORTEX_PCI(vp), le32_to_cpu(vp->tx_ring[i].addr), skb->len, PCI_DMA_TODEVICE);
2858#endif
2859 dev_kfree_skb(skb);
2860 vp->tx_skbuff[i] = NULL;
2861 }
2862 }
2863 }
2864
2865 return 0;
2866}
2867
2868static void
2869dump_tx_ring(struct net_device *dev)
2870{
2871 if (vortex_debug > 0) {
2872 struct vortex_private *vp = netdev_priv(dev);
62afe595 2873 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 2874
2875 if (vp->full_bus_master_tx) {
2876 int i;
62afe595 2877 int stalled = ioread32(ioaddr + PktStatus) & 0x04; /* Possible racy. But it's only debug stuff */
1da177e4
LT		 2878
2879 printk(KERN_ERR " Flags; bus-master %d, dirty %d(%d) current %d(%d)\n",
2880 vp->full_bus_master_tx,
2881 vp->dirty_tx, vp->dirty_tx % TX_RING_SIZE,
2882 vp->cur_tx, vp->cur_tx % TX_RING_SIZE);
2883 printk(KERN_ERR " Transmit list %8.8x vs. %p.\n",
62afe595 2884 ioread32(ioaddr + DownListPtr),
1da177e4
LT		 2885 &vp->tx_ring[vp->dirty_tx % TX_RING_SIZE]);
2886 issue_and_wait(dev, DownStall);
2887 for (i = 0; i < TX_RING_SIZE; i++) {
2888 printk(KERN_ERR " %d: @%p length %8.8x status %8.8x\n", i,
2889 &vp->tx_ring[i],
2890#if DO_ZEROCOPY
2891 le32_to_cpu(vp->tx_ring[i].frag[0].length),
2892#else
2893 le32_to_cpu(vp->tx_ring[i].length),
2894#endif
2895 le32_to_cpu(vp->tx_ring[i].status));
2896 }
2897 if (!stalled)
62afe595 2898 iowrite16(DownUnstall, ioaddr + EL3_CMD);
1da177e4
LT		 2899 }
2900 }
2901}
2902
2903static struct net_device_stats *vortex_get_stats(struct net_device *dev)
2904{
2905 struct vortex_private *vp = netdev_priv(dev);
62afe595 2906 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 2907 unsigned long flags;
2908
2909 if (netif_device_present(dev)) { /* AKPM: Used to be netif_running */
2910 spin_lock_irqsave (&vp->lock, flags);
62afe595 2911 update_stats(ioaddr, dev);
1da177e4
LT		 2912 spin_unlock_irqrestore (&vp->lock, flags);
2913 }
2914 return &vp->stats;
2915}
2916
2917/* Update statistics.
2918 Unlike with the EL3 we need not worry about interrupts changing
2919 the window setting from underneath us, but we must still guard
2920 against a race condition with a StatsUpdate interrupt updating the
2921 table. This is done by checking that the ASM (!) code generated uses
2922 atomic updates with '+='.
2923 */
62afe595 2924static void update_stats(void __iomem *ioaddr, struct net_device *dev)
1da177e4
LT		 2925{
2926 struct vortex_private *vp = netdev_priv(dev);
62afe595 2927 int old_window = ioread16(ioaddr + EL3_CMD);
1da177e4
LT		 2928
2929 if (old_window == 0xffff) /* Chip suspended or ejected. */
2930 return;
2931 /* Unlike the 3c5x9 we need not turn off stats updates while reading. */
2932 /* Switch to the stats window, and read everything. */
2933 EL3WINDOW(6);
62afe595
JL		 2934 vp->stats.tx_carrier_errors += ioread8(ioaddr + 0);
2935 vp->stats.tx_heartbeat_errors += ioread8(ioaddr + 1);
62afe595
JL		 2936 vp->stats.tx_window_errors += ioread8(ioaddr + 4);
2937 vp->stats.rx_fifo_errors += ioread8(ioaddr + 5);
2938 vp->stats.tx_packets += ioread8(ioaddr + 6);
2939 vp->stats.tx_packets += (ioread8(ioaddr + 9)&0x30) << 4;
2940 /* Rx packets */ ioread8(ioaddr + 7); /* Must read to clear */
1da177e4
LT		 2941 /* Don't bother with register 9, an extension of registers 6&7.
2942 If we do use the 6&7 values the atomic update assumption above
2943 is invalid. */
62afe595
JL		 2944 vp->stats.rx_bytes += ioread16(ioaddr + 10);
2945 vp->stats.tx_bytes += ioread16(ioaddr + 12);
1da177e4 2946 /* Extra stats for get_ethtool_stats() */
62afe595 2947 vp->xstats.tx_multiple_collisions += ioread8(ioaddr + 2);
8d1d0340 2948 vp->xstats.tx_single_collisions += ioread8(ioaddr + 3);
62afe595 2949 vp->xstats.tx_deferred += ioread8(ioaddr + 8);
1da177e4 2950 EL3WINDOW(4);
62afe595 2951 vp->xstats.rx_bad_ssd += ioread8(ioaddr + 12);
1da177e4 2952
8d1d0340
SK		 2953 vp->stats.collisions = vp->xstats.tx_multiple_collisions
2954 + vp->xstats.tx_single_collisions
2955 + vp->xstats.tx_max_collisions;
2956
1da177e4 2957 {
62afe595 2958 u8 up = ioread8(ioaddr + 13);
1da177e4
LT		 2959 vp->stats.rx_bytes += (up & 0x0f) << 16;
2960 vp->stats.tx_bytes += (up & 0xf0) << 12;
2961 }
2962
2963 EL3WINDOW(old_window >> 13);
2964 return;
2965}
2966
2967static int vortex_nway_reset(struct net_device *dev)
2968{
2969 struct vortex_private *vp = netdev_priv(dev);
62afe595 2970 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 2971 unsigned long flags;
2972 int rc;
2973
2974 spin_lock_irqsave(&vp->lock, flags);
2975 EL3WINDOW(4);
2976 rc = mii_nway_restart(&vp->mii);
2977 spin_unlock_irqrestore(&vp->lock, flags);
2978 return rc;
2979}
2980
2981static u32 vortex_get_link(struct net_device *dev)
2982{
2983 struct vortex_private *vp = netdev_priv(dev);
62afe595 2984 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 2985 unsigned long flags;
2986 int rc;
2987
2988 spin_lock_irqsave(&vp->lock, flags);
2989 EL3WINDOW(4);
2990 rc = mii_link_ok(&vp->mii);
2991 spin_unlock_irqrestore(&vp->lock, flags);
2992 return rc;
2993}
2994
2995static int vortex_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2996{
2997 struct vortex_private *vp = netdev_priv(dev);
62afe595 2998 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 2999 unsigned long flags;
3000 int rc;
3001
3002 spin_lock_irqsave(&vp->lock, flags);
3003 EL3WINDOW(4);
3004 rc = mii_ethtool_gset(&vp->mii, cmd);
3005 spin_unlock_irqrestore(&vp->lock, flags);
3006 return rc;
3007}
3008
3009static int vortex_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
3010{
3011 struct vortex_private *vp = netdev_priv(dev);
62afe595 3012 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 3013 unsigned long flags;
3014 int rc;
3015
3016 spin_lock_irqsave(&vp->lock, flags);
3017 EL3WINDOW(4);
3018 rc = mii_ethtool_sset(&vp->mii, cmd);
3019 spin_unlock_irqrestore(&vp->lock, flags);
3020 return rc;
3021}
3022
3023static u32 vortex_get_msglevel(struct net_device *dev)
3024{
3025 return vortex_debug;
3026}
3027
3028static void vortex_set_msglevel(struct net_device *dev, u32 dbg)
3029{
3030 vortex_debug = dbg;
3031}
3032
3033static int vortex_get_stats_count(struct net_device *dev)
3034{
3035 return VORTEX_NUM_STATS;
3036}
3037
3038static void vortex_get_ethtool_stats(struct net_device *dev,
3039 struct ethtool_stats *stats, u64 *data)
3040{
3041 struct vortex_private *vp = netdev_priv(dev);
62afe595 3042 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 3043 unsigned long flags;
3044
3045 spin_lock_irqsave(&vp->lock, flags);
62afe595 3046 update_stats(ioaddr, dev);
1da177e4
LT		 3047 spin_unlock_irqrestore(&vp->lock, flags);
3048
3049 data[0] = vp->xstats.tx_deferred;
8d1d0340
SK		 3050 data[1] = vp->xstats.tx_max_collisions;
3051 data[2] = vp->xstats.tx_multiple_collisions;
3052 data[3] = vp->xstats.tx_single_collisions;
3053 data[4] = vp->xstats.rx_bad_ssd;
1da177e4
LT		 3054}
3055
3056
3057static void vortex_get_strings(struct net_device *dev, u32 stringset, u8 *data)
3058{
3059 switch (stringset) {
3060 case ETH_SS_STATS:
3061 memcpy(data, &ethtool_stats_keys, sizeof(ethtool_stats_keys));
3062 break;
3063 default:
3064 WARN_ON(1);
3065 break;
3066 }
3067}
3068
3069static void vortex_get_drvinfo(struct net_device *dev,
3070 struct ethtool_drvinfo *info)
3071{
3072 struct vortex_private *vp = netdev_priv(dev);
3073
3074 strcpy(info->driver, DRV_NAME);
3075 strcpy(info->version, DRV_VERSION);
3076 if (VORTEX_PCI(vp)) {
3077 strcpy(info->bus_info, pci_name(VORTEX_PCI(vp)));
3078 } else {
3079 if (VORTEX_EISA(vp))
3080 sprintf(info->bus_info, vp->gendev->bus_id);
3081 else
3082 sprintf(info->bus_info, "EISA 0x%lx %d",
3083 dev->base_addr, dev->irq);
3084 }
3085}
3086
3087static struct ethtool_ops vortex_ethtool_ops = {
3088 .get_drvinfo = vortex_get_drvinfo,
3089 .get_strings = vortex_get_strings,
3090 .get_msglevel = vortex_get_msglevel,
3091 .set_msglevel = vortex_set_msglevel,
3092 .get_ethtool_stats = vortex_get_ethtool_stats,
3093 .get_stats_count = vortex_get_stats_count,
3094 .get_settings = vortex_get_settings,
3095 .set_settings = vortex_set_settings,
3096 .get_link = vortex_get_link,
3097 .nway_reset = vortex_nway_reset,
bb531fc0 3098 .get_perm_addr = ethtool_op_get_perm_addr,
1da177e4
LT		 3099};
3100
3101#ifdef CONFIG_PCI
3102/*
3103 * Must power the device up to do MDIO operations
3104 */
3105static int vortex_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
3106{
3107 int err;
3108 struct vortex_private *vp = netdev_priv(dev);
62afe595 3109 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 3110 unsigned long flags;
3111 int state = 0;
3112
3113 if(VORTEX_PCI(vp))
3114 state = VORTEX_PCI(vp)->current_state;
3115
3116 /* The kernel core really should have pci_get_power_state() */
3117
3118 if(state != 0)
3119 pci_set_power_state(VORTEX_PCI(vp), PCI_D0);
3120 spin_lock_irqsave(&vp->lock, flags);
3121 EL3WINDOW(4);
3122 err = generic_mii_ioctl(&vp->mii, if_mii(rq), cmd, NULL);
3123 spin_unlock_irqrestore(&vp->lock, flags);
3124 if(state != 0)
3125 pci_set_power_state(VORTEX_PCI(vp), state);
3126
3127 return err;
3128}
3129#endif
3130
3131
3132/* Pre-Cyclone chips have no documented multicast filter, so the only
3133 multicast setting is to receive all multicast frames. At least
3134 the chip has a very clean way to set the mode, unlike many others. */
3135static void set_rx_mode(struct net_device *dev)
3136{
62afe595
JL		 3137 struct vortex_private *vp = netdev_priv(dev);
3138 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 3139 int new_mode;
3140
3141 if (dev->flags & IFF_PROMISC) {
3142 if (vortex_debug > 0)
3143 printk(KERN_NOTICE "%s: Setting promiscuous mode.\n", dev->name);
3144 new_mode = SetRxFilter|RxStation|RxMulticast|RxBroadcast|RxProm;
3145 } else if ((dev->mc_list) || (dev->flags & IFF_ALLMULTI)) {
3146 new_mode = SetRxFilter|RxStation|RxMulticast|RxBroadcast;
3147 } else
3148 new_mode = SetRxFilter | RxStation | RxBroadcast;
3149
62afe595 3150 iowrite16(new_mode, ioaddr + EL3_CMD);
1da177e4
LT		 3151}
3152
3153#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
3154/* Setup the card so that it can receive frames with an 802.1q VLAN tag.
3155 Note that this must be done after each RxReset due to some backwards
3156 compatibility logic in the Cyclone and Tornado ASICs */
3157
3158/* The Ethernet Type used for 802.1q tagged frames */
3159#define VLAN_ETHER_TYPE 0x8100
3160
3161static void set_8021q_mode(struct net_device *dev, int enable)
3162{
3163 struct vortex_private *vp = netdev_priv(dev);
62afe595
JL		 3164 void __iomem *ioaddr = vp->ioaddr;
3165 int old_window = ioread16(ioaddr + EL3_CMD);
1da177e4
LT		 3166 int mac_ctrl;
3167
3168 if ((vp->drv_flags&IS_CYCLONE) || (vp->drv_flags&IS_TORNADO)) {
3169 /* cyclone and tornado chipsets can recognize 802.1q
3170 * tagged frames and treat them correctly */
3171
3172 int max_pkt_size = dev->mtu+14; /* MTU+Ethernet header */
3173 if (enable)
3174 max_pkt_size += 4; /* 802.1Q VLAN tag */
3175
3176 EL3WINDOW(3);
62afe595 3177 iowrite16(max_pkt_size, ioaddr+Wn3_MaxPktSize);
1da177e4
LT		 3178
3179 /* set VlanEtherType to let the hardware checksumming
3180 treat tagged frames correctly */
3181 EL3WINDOW(7);
62afe595 3182 iowrite16(VLAN_ETHER_TYPE, ioaddr+Wn7_VlanEtherType);
1da177e4
LT		 3183 } else {
3184 /* on older cards we have to enable large frames */
3185
3186 vp->large_frames = dev->mtu > 1500 || enable;
3187
3188 EL3WINDOW(3);
62afe595 3189 mac_ctrl = ioread16(ioaddr+Wn3_MAC_Ctrl);
1da177e4
LT		 3190 if (vp->large_frames)
3191 mac_ctrl |= 0x40;
3192 else
3193 mac_ctrl &= ~0x40;
62afe595 3194 iowrite16(mac_ctrl, ioaddr+Wn3_MAC_Ctrl);
1da177e4
LT		 3195 }
3196
3197 EL3WINDOW(old_window);
3198}
3199#else
3200
3201static void set_8021q_mode(struct net_device *dev, int enable)
3202{
3203}
3204
3205
3206#endif
3207
3208/* MII transceiver control section.
3209 Read and write the MII registers using software-generated serial
3210 MDIO protocol. See the MII specifications or DP83840A data sheet
3211 for details. */
3212
3213/* The maximum data clock rate is 2.5 Mhz. The minimum timing is usually
3214 met by back-to-back PCI I/O cycles, but we insert a delay to avoid
3215 "overclocking" issues. */
62afe595 3216#define mdio_delay() ioread32(mdio_addr)
1da177e4
LT		 3217
3218#define MDIO_SHIFT_CLK 0x01
3219#define MDIO_DIR_WRITE 0x04
3220#define MDIO_DATA_WRITE0 (0x00 | MDIO_DIR_WRITE)
3221#define MDIO_DATA_WRITE1 (0x02 | MDIO_DIR_WRITE)
3222#define MDIO_DATA_READ 0x02
3223#define MDIO_ENB_IN 0x00
3224
3225/* Generate the preamble required for initial synchronization and
3226 a few older transceivers. */
62afe595 3227static void mdio_sync(void __iomem *ioaddr, int bits)
1da177e4 3228{
62afe595 3229 void __iomem *mdio_addr = ioaddr + Wn4_PhysicalMgmt;
1da177e4
LT		 3230
3231 /* Establish sync by sending at least 32 logic ones. */
3232 while (-- bits >= 0) {
62afe595 3233 iowrite16(MDIO_DATA_WRITE1, mdio_addr);
1da177e4 3234 mdio_delay();
62afe595 3235 iowrite16(MDIO_DATA_WRITE1 | MDIO_SHIFT_CLK, mdio_addr);
1da177e4
LT		 3236 mdio_delay();
3237 }
3238}
3239
3240static int mdio_read(struct net_device *dev, int phy_id, int location)
3241{
3242 int i;
62afe595
JL		 3243 struct vortex_private *vp = netdev_priv(dev);
3244 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 3245 int read_cmd = (0xf6 << 10) | (phy_id << 5) | location;
3246 unsigned int retval = 0;
62afe595 3247 void __iomem *mdio_addr = ioaddr + Wn4_PhysicalMgmt;
1da177e4
LT		 3248
3249 if (mii_preamble_required)
3250 mdio_sync(ioaddr, 32);
3251
3252 /* Shift the read command bits out. */
3253 for (i = 14; i >= 0; i--) {
3254 int dataval = (read_cmd&(1<<i)) ? MDIO_DATA_WRITE1 : MDIO_DATA_WRITE0;
62afe595 3255 iowrite16(dataval, mdio_addr);
1da177e4 3256 mdio_delay();
62afe595 3257 iowrite16(dataval | MDIO_SHIFT_CLK, mdio_addr);
1da177e4
LT		 3258 mdio_delay();
3259 }
3260 /* Read the two transition, 16 data, and wire-idle bits. */
3261 for (i = 19; i > 0; i--) {
62afe595 3262 iowrite16(MDIO_ENB_IN, mdio_addr);
1da177e4 3263 mdio_delay();
62afe595
JL		 3264 retval = (retval << 1) | ((ioread16(mdio_addr) & MDIO_DATA_READ) ? 1 : 0);
3265 iowrite16(MDIO_ENB_IN | MDIO_SHIFT_CLK, mdio_addr);
1da177e4
LT		 3266 mdio_delay();
3267 }
3268 return retval & 0x20000 ? 0xffff : retval>>1 & 0xffff;
3269}
3270
3271static void mdio_write(struct net_device *dev, int phy_id, int location, int value)
3272{
62afe595
JL		 3273 struct vortex_private *vp = netdev_priv(dev);
3274 void __iomem *ioaddr = vp->ioaddr;
1da177e4 3275 int write_cmd = 0x50020000 | (phy_id << 23) | (location << 18) | value;
62afe595 3276 void __iomem *mdio_addr = ioaddr + Wn4_PhysicalMgmt;
1da177e4
LT		 3277 int i;
3278
3279 if (mii_preamble_required)
3280 mdio_sync(ioaddr, 32);
3281
3282 /* Shift the command bits out. */
3283 for (i = 31; i >= 0; i--) {
3284 int dataval = (write_cmd&(1<<i)) ? MDIO_DATA_WRITE1 : MDIO_DATA_WRITE0;
62afe595 3285 iowrite16(dataval, mdio_addr);
1da177e4 3286 mdio_delay();
62afe595 3287 iowrite16(dataval | MDIO_SHIFT_CLK, mdio_addr);
1da177e4
LT		 3288 mdio_delay();
3289 }
3290 /* Leave the interface idle. */
3291 for (i = 1; i >= 0; i--) {
62afe595 3292 iowrite16(MDIO_ENB_IN, mdio_addr);
1da177e4 3293 mdio_delay();
62afe595 3294 iowrite16(MDIO_ENB_IN | MDIO_SHIFT_CLK, mdio_addr);
1da177e4
LT		 3295 mdio_delay();
3296 }
3297 return;
3298}
3299\f
3300/* ACPI: Advanced Configuration and Power Interface. */
3301/* Set Wake-On-LAN mode and put the board into D3 (power-down) state. */
3302static void acpi_set_WOL(struct net_device *dev)
3303{
3304 struct vortex_private *vp = netdev_priv(dev);
62afe595 3305 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 3306
3307 if (vp->enable_wol) {
3308 /* Power up on: 1==Downloaded Filter, 2==Magic Packets, 4==Link Status. */
3309 EL3WINDOW(7);
62afe595 3310 iowrite16(2, ioaddr + 0x0c);
1da177e4 3311 /* The RxFilter must accept the WOL frames. */
62afe595
JL		 3312 iowrite16(SetRxFilter|RxStation|RxMulticast|RxBroadcast, ioaddr + EL3_CMD);
3313 iowrite16(RxEnable, ioaddr + EL3_CMD);
1da177e4
LT		 3314
3315 pci_enable_wake(VORTEX_PCI(vp), 0, 1);
3c8fad18
DR		 3316
3317 /* Change the power state to D3; RxEnable doesn't take effect. */
3318 pci_set_power_state(VORTEX_PCI(vp), PCI_D3hot);
1da177e4 3319 }
1da177e4
LT		 3320}
3321
3322
3323static void __devexit vortex_remove_one (struct pci_dev *pdev)
3324{
3325 struct net_device *dev = pci_get_drvdata(pdev);
3326 struct vortex_private *vp;
3327
3328 if (!dev) {
3329 printk("vortex_remove_one called for Compaq device!\n");
3330 BUG();
3331 }
3332
3333 vp = netdev_priv(dev);
3334
62afe595
JL		 3335 if (vp->cb_fn_base)
3336 pci_iounmap(VORTEX_PCI(vp), vp->cb_fn_base);
3337
1da177e4
LT		 3338 unregister_netdev(dev);
3339
3340 if (VORTEX_PCI(vp)) {
3341 pci_set_power_state(VORTEX_PCI(vp), PCI_D0); /* Go active */
3342 if (vp->pm_state_valid)
3343 pci_restore_state(VORTEX_PCI(vp));
3344 pci_disable_device(VORTEX_PCI(vp));
3345 }
3346 /* Should really use issue_and_wait() here */
62afe595
JL		 3347 iowrite16(TotalReset | ((vp->drv_flags & EEPROM_RESET) ? 0x04 : 0x14),
3348 vp->ioaddr + EL3_CMD);
3349
3350 pci_iounmap(VORTEX_PCI(vp), vp->ioaddr);
1da177e4
LT		 3351
3352 pci_free_consistent(pdev,
3353 sizeof(struct boom_rx_desc) * RX_RING_SIZE
3354 + sizeof(struct boom_tx_desc) * TX_RING_SIZE,
3355 vp->rx_ring,
3356 vp->rx_ring_dma);
3357 if (vp->must_free_region)
3358 release_region(dev->base_addr, vp->io_size);
3359 free_netdev(dev);
3360}
3361
3362
3363static struct pci_driver vortex_driver = {
3364 .name = "3c59x",
3365 .probe = vortex_init_one,
3366 .remove = __devexit_p(vortex_remove_one),
3367 .id_table = vortex_pci_tbl,
3368#ifdef CONFIG_PM
3369 .suspend = vortex_suspend,
3370 .resume = vortex_resume,
3371#endif
3372};
3373
3374
3375static int vortex_have_pci;
3376static int vortex_have_eisa;
3377
3378
3379static int __init vortex_init (void)
3380{
3381 int pci_rc, eisa_rc;
3382
3383 pci_rc = pci_module_init(&vortex_driver);
3384 eisa_rc = vortex_eisa_init();
3385
3386 if (pci_rc == 0)
3387 vortex_have_pci = 1;
3388 if (eisa_rc > 0)
3389 vortex_have_eisa = 1;
3390
3391 return (vortex_have_pci + vortex_have_eisa) ? 0 : -ENODEV;
3392}
3393
3394
3395static void __exit vortex_eisa_cleanup (void)
3396{
3397 struct vortex_private *vp;
62afe595 3398 void __iomem *ioaddr;
1da177e4
LT		 3399
3400#ifdef CONFIG_EISA
3401 /* Take care of the EISA devices */
3402 eisa_driver_unregister (&vortex_eisa_driver);
3403#endif
3404
3405 if (compaq_net_device) {
3406 vp = compaq_net_device->priv;
62afe595
JL		 3407 ioaddr = ioport_map(compaq_net_device->base_addr,
3408 VORTEX_TOTAL_SIZE);
1da177e4
LT		 3409
3410 unregister_netdev (compaq_net_device);
62afe595
JL		 3411 iowrite16 (TotalReset, ioaddr + EL3_CMD);
3412 release_region(compaq_net_device->base_addr,
3413 VORTEX_TOTAL_SIZE);
1da177e4
LT		 3414
3415 free_netdev (compaq_net_device);
3416 }
3417}
3418
3419
3420static void __exit vortex_cleanup (void)
3421{
3422 if (vortex_have_pci)
3423 pci_unregister_driver (&vortex_driver);
3424 if (vortex_have_eisa)
3425 vortex_eisa_cleanup ();
3426}
3427
3428
3429module_init(vortex_init);
3430module_exit(vortex_cleanup);
3431
3432\f
3433/*
3434 * Local variables:
3435 * c-indent-level: 4
3436 * c-basic-offset: 4
3437 * tab-width: 4
3438 * End:
3439 */
Linux kernel - Deliverables
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