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Merge git://git.kernel.org/pub/scm/linux/kernel/git/linville/wireless-next-2.6 into...
[deliverable/linux.git] / drivers / net / 8139cp.c
CommitLineData
1da177e4
LT		 1/* 8139cp.c: A Linux PCI Ethernet driver for the RealTek 8139C+ chips. */
2/*
3 Copyright 2001-2004 Jeff Garzik <jgarzik@pobox.com>
4
5 Copyright (C) 2001, 2002 David S. Miller (davem@redhat.com) [tg3.c]
6 Copyright (C) 2000, 2001 David S. Miller (davem@redhat.com) [sungem.c]
7 Copyright 2001 Manfred Spraul [natsemi.c]
8 Copyright 1999-2001 by Donald Becker. [natsemi.c]
9 Written 1997-2001 by Donald Becker. [8139too.c]
10 Copyright 1998-2001 by Jes Sorensen, <jes@trained-monkey.org>. [acenic.c]
11
12 This software may be used and distributed according to the terms of
13 the GNU General Public License (GPL), incorporated herein by reference.
14 Drivers based on or derived from this code fall under the GPL and must
15 retain the authorship, copyright and license notice. This file is not
16 a complete program and may only be used when the entire operating
17 system is licensed under the GPL.
18
19 See the file COPYING in this distribution for more information.
20
21 Contributors:
f3b197ac 22
1da177e4
LT		 23 Wake-on-LAN support - Felipe Damasio <felipewd@terra.com.br>
24 PCI suspend/resume - Felipe Damasio <felipewd@terra.com.br>
25 LinkChg interrupt - Felipe Damasio <felipewd@terra.com.br>
f3b197ac 26
1da177e4
LT		 27 TODO:
28 * Test Tx checksumming thoroughly
1da177e4
LT		 29
30 Low priority TODO:
31 * Complete reset on PciErr
32 * Consider Rx interrupt mitigation using TimerIntr
33 * Investigate using skb->priority with h/w VLAN priority
34 * Investigate using High Priority Tx Queue with skb->priority
35 * Adjust Rx FIFO threshold and Max Rx DMA burst on Rx FIFO error
36 * Adjust Tx FIFO threshold and Max Tx DMA burst on Tx FIFO error
37 * Implement Tx software interrupt mitigation via
38 Tx descriptor bit
39 * The real minimum of CP_MIN_MTU is 4 bytes. However,
40 for this to be supported, one must(?) turn on packet padding.
41 * Support external MII transceivers (patch available)
42
43 NOTES:
44 * TX checksumming is considered experimental. It is off by
45 default, use ethtool to turn it on.
46
47 */
48
b4f18b3f
JP		 49#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
50
1da177e4 51#define DRV_NAME "8139cp"
d5b20697 52#define DRV_VERSION "1.3"
1da177e4
LT		 53#define DRV_RELDATE "Mar 22, 2004"
54
55
1da177e4 56#include <linux/module.h>
e21ba282 57#include <linux/moduleparam.h>
1da177e4
LT		 58#include <linux/kernel.h>
59#include <linux/compiler.h>
60#include <linux/netdevice.h>
61#include <linux/etherdevice.h>
62#include <linux/init.h>
63#include <linux/pci.h>
8662d061 64#include <linux/dma-mapping.h>
1da177e4
LT		 65#include <linux/delay.h>
66#include <linux/ethtool.h>
5a0e3ad6 67#include <linux/gfp.h>
1da177e4
LT		 68#include <linux/mii.h>
69#include <linux/if_vlan.h>
70#include <linux/crc32.h>
71#include <linux/in.h>
72#include <linux/ip.h>
73#include <linux/tcp.h>
74#include <linux/udp.h>
75#include <linux/cache.h>
76#include <asm/io.h>
77#include <asm/irq.h>
78#include <asm/uaccess.h>
79
80/* VLAN tagging feature enable/disable */
81#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
82#define CP_VLAN_TAG_USED 1
83#define CP_VLAN_TX_TAG(tx_desc,vlan_tag_value) \
cf983019 84 do { (tx_desc)->opts2 = cpu_to_le32(vlan_tag_value); } while (0)
1da177e4
LT		 85#else
86#define CP_VLAN_TAG_USED 0
87#define CP_VLAN_TX_TAG(tx_desc,vlan_tag_value) \
88 do { (tx_desc)->opts2 = 0; } while (0)
89#endif
90
91/* These identify the driver base version and may not be removed. */
92static char version[] =
9cc40855 93DRV_NAME ": 10/100 PCI Ethernet driver v" DRV_VERSION " (" DRV_RELDATE ")\n";
1da177e4
LT		 94
95MODULE_AUTHOR("Jeff Garzik <jgarzik@pobox.com>");
96MODULE_DESCRIPTION("RealTek RTL-8139C+ series 10/100 PCI Ethernet driver");
a78d8927 97MODULE_VERSION(DRV_VERSION);
1da177e4
LT		 98MODULE_LICENSE("GPL");
99
100static int debug = -1;
e21ba282 101module_param(debug, int, 0);
1da177e4
LT		 102MODULE_PARM_DESC (debug, "8139cp: bitmapped message enable number");
103
104/* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
105 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
106static int multicast_filter_limit = 32;
e21ba282 107module_param(multicast_filter_limit, int, 0);
1da177e4
LT		 108MODULE_PARM_DESC (multicast_filter_limit, "8139cp: maximum number of filtered multicast addresses");
109
1da177e4
LT		 110#define CP_DEF_MSG_ENABLE (NETIF_MSG_DRV | \
111 NETIF_MSG_PROBE | \
112 NETIF_MSG_LINK)
113#define CP_NUM_STATS 14 /* struct cp_dma_stats, plus one */
114#define CP_STATS_SIZE 64 /* size in bytes of DMA stats block */
115#define CP_REGS_SIZE (0xff + 1)
116#define CP_REGS_VER 1 /* version 1 */
117#define CP_RX_RING_SIZE 64
118#define CP_TX_RING_SIZE 64
119#define CP_RING_BYTES \
120 ((sizeof(struct cp_desc) * CP_RX_RING_SIZE) + \
121 (sizeof(struct cp_desc) * CP_TX_RING_SIZE) + \
122 CP_STATS_SIZE)
123#define NEXT_TX(N) (((N) + 1) & (CP_TX_RING_SIZE - 1))
124#define NEXT_RX(N) (((N) + 1) & (CP_RX_RING_SIZE - 1))
125#define TX_BUFFS_AVAIL(CP) \
126 (((CP)->tx_tail <= (CP)->tx_head) ? \
127 (CP)->tx_tail + (CP_TX_RING_SIZE - 1) - (CP)->tx_head : \
128 (CP)->tx_tail - (CP)->tx_head - 1)
129
130#define PKT_BUF_SZ 1536 /* Size of each temporary Rx buffer.*/
1da177e4
LT		 131#define CP_INTERNAL_PHY 32
132
133/* The following settings are log_2(bytes)-4: 0 == 16 bytes .. 6==1024, 7==end of packet. */
134#define RX_FIFO_THRESH 5 /* Rx buffer level before first PCI xfer. */
135#define RX_DMA_BURST 4 /* Maximum PCI burst, '4' is 256 */
136#define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
137#define TX_EARLY_THRESH 256 /* Early Tx threshold, in bytes */
138
139/* Time in jiffies before concluding the transmitter is hung. */
140#define TX_TIMEOUT (6*HZ)
141
142/* hardware minimum and maximum for a single frame's data payload */
143#define CP_MIN_MTU 60 /* TODO: allow lower, but pad */
144#define CP_MAX_MTU 4096
145
146enum {
147 /* NIC register offsets */
148 MAC0 = 0x00, /* Ethernet hardware address. */
149 MAR0 = 0x08, /* Multicast filter. */
150 StatsAddr = 0x10, /* 64-bit start addr of 64-byte DMA stats blk */
151 TxRingAddr = 0x20, /* 64-bit start addr of Tx ring */
152 HiTxRingAddr = 0x28, /* 64-bit start addr of high priority Tx ring */
153 Cmd = 0x37, /* Command register */
154 IntrMask = 0x3C, /* Interrupt mask */
155 IntrStatus = 0x3E, /* Interrupt status */
156 TxConfig = 0x40, /* Tx configuration */
157 ChipVersion = 0x43, /* 8-bit chip version, inside TxConfig */
158 RxConfig = 0x44, /* Rx configuration */
159 RxMissed = 0x4C, /* 24 bits valid, write clears */
160 Cfg9346 = 0x50, /* EEPROM select/control; Cfg reg [un]lock */
161 Config1 = 0x52, /* Config1 */
162 Config3 = 0x59, /* Config3 */
163 Config4 = 0x5A, /* Config4 */
164 MultiIntr = 0x5C, /* Multiple interrupt select */
165 BasicModeCtrl = 0x62, /* MII BMCR */
166 BasicModeStatus = 0x64, /* MII BMSR */
167 NWayAdvert = 0x66, /* MII ADVERTISE */
168 NWayLPAR = 0x68, /* MII LPA */
169 NWayExpansion = 0x6A, /* MII Expansion */
170 Config5 = 0xD8, /* Config5 */
171 TxPoll = 0xD9, /* Tell chip to check Tx descriptors for work */
172 RxMaxSize = 0xDA, /* Max size of an Rx packet (8169 only) */
173 CpCmd = 0xE0, /* C+ Command register (C+ mode only) */
174 IntrMitigate = 0xE2, /* rx/tx interrupt mitigation control */
175 RxRingAddr = 0xE4, /* 64-bit start addr of Rx ring */
176 TxThresh = 0xEC, /* Early Tx threshold */
177 OldRxBufAddr = 0x30, /* DMA address of Rx ring buffer (C mode) */
178 OldTSD0 = 0x10, /* DMA address of first Tx desc (C mode) */
179
180 /* Tx and Rx status descriptors */
181 DescOwn = (1 << 31), /* Descriptor is owned by NIC */
182 RingEnd = (1 << 30), /* End of descriptor ring */
183 FirstFrag = (1 << 29), /* First segment of a packet */
184 LastFrag = (1 << 28), /* Final segment of a packet */
fcec3456
JG		 185 LargeSend = (1 << 27), /* TCP Large Send Offload (TSO) */
186 MSSShift = 16, /* MSS value position */
187 MSSMask = 0xfff, /* MSS value: 11 bits */
1da177e4
LT		 188 TxError = (1 << 23), /* Tx error summary */
189 RxError = (1 << 20), /* Rx error summary */
190 IPCS = (1 << 18), /* Calculate IP checksum */
191 UDPCS = (1 << 17), /* Calculate UDP/IP checksum */
192 TCPCS = (1 << 16), /* Calculate TCP/IP checksum */
193 TxVlanTag = (1 << 17), /* Add VLAN tag */
194 RxVlanTagged = (1 << 16), /* Rx VLAN tag available */
195 IPFail = (1 << 15), /* IP checksum failed */
196 UDPFail = (1 << 14), /* UDP/IP checksum failed */
197 TCPFail = (1 << 13), /* TCP/IP checksum failed */
198 NormalTxPoll = (1 << 6), /* One or more normal Tx packets to send */
199 PID1 = (1 << 17), /* 2 protocol id bits: 0==non-IP, */
200 PID0 = (1 << 16), /* 1==UDP/IP, 2==TCP/IP, 3==IP */
201 RxProtoTCP = 1,
202 RxProtoUDP = 2,
203 RxProtoIP = 3,
204 TxFIFOUnder = (1 << 25), /* Tx FIFO underrun */
205 TxOWC = (1 << 22), /* Tx Out-of-window collision */
206 TxLinkFail = (1 << 21), /* Link failed during Tx of packet */
207 TxMaxCol = (1 << 20), /* Tx aborted due to excessive collisions */
208 TxColCntShift = 16, /* Shift, to get 4-bit Tx collision cnt */
209 TxColCntMask = 0x01 | 0x02 | 0x04 | 0x08, /* 4-bit collision count */
210 RxErrFrame = (1 << 27), /* Rx frame alignment error */
211 RxMcast = (1 << 26), /* Rx multicast packet rcv'd */
212 RxErrCRC = (1 << 18), /* Rx CRC error */
213 RxErrRunt = (1 << 19), /* Rx error, packet < 64 bytes */
214 RxErrLong = (1 << 21), /* Rx error, packet > 4096 bytes */
215 RxErrFIFO = (1 << 22), /* Rx error, FIFO overflowed, pkt bad */
216
217 /* StatsAddr register */
218 DumpStats = (1 << 3), /* Begin stats dump */
219
220 /* RxConfig register */
221 RxCfgFIFOShift = 13, /* Shift, to get Rx FIFO thresh value */
222 RxCfgDMAShift = 8, /* Shift, to get Rx Max DMA value */
223 AcceptErr = 0x20, /* Accept packets with CRC errors */
224 AcceptRunt = 0x10, /* Accept runt (<64 bytes) packets */
225 AcceptBroadcast = 0x08, /* Accept broadcast packets */
226 AcceptMulticast = 0x04, /* Accept multicast packets */
227 AcceptMyPhys = 0x02, /* Accept pkts with our MAC as dest */
228 AcceptAllPhys = 0x01, /* Accept all pkts w/ physical dest */
229
230 /* IntrMask / IntrStatus registers */
231 PciErr = (1 << 15), /* System error on the PCI bus */
232 TimerIntr = (1 << 14), /* Asserted when TCTR reaches TimerInt value */
233 LenChg = (1 << 13), /* Cable length change */
234 SWInt = (1 << 8), /* Software-requested interrupt */
235 TxEmpty = (1 << 7), /* No Tx descriptors available */
236 RxFIFOOvr = (1 << 6), /* Rx FIFO Overflow */
237 LinkChg = (1 << 5), /* Packet underrun, or link change */
238 RxEmpty = (1 << 4), /* No Rx descriptors available */
239 TxErr = (1 << 3), /* Tx error */
240 TxOK = (1 << 2), /* Tx packet sent */
241 RxErr = (1 << 1), /* Rx error */
242 RxOK = (1 << 0), /* Rx packet received */
243 IntrResvd = (1 << 10), /* reserved, according to RealTek engineers,
244 but hardware likes to raise it */
245
246 IntrAll = PciErr | TimerIntr | LenChg | SWInt | TxEmpty |
247 RxFIFOOvr | LinkChg | RxEmpty | TxErr | TxOK |
248 RxErr | RxOK | IntrResvd,
249
250 /* C mode command register */
251 CmdReset = (1 << 4), /* Enable to reset; self-clearing */
252 RxOn = (1 << 3), /* Rx mode enable */
253 TxOn = (1 << 2), /* Tx mode enable */
254
255 /* C+ mode command register */
256 RxVlanOn = (1 << 6), /* Rx VLAN de-tagging enable */
257 RxChkSum = (1 << 5), /* Rx checksum offload enable */
258 PCIDAC = (1 << 4), /* PCI Dual Address Cycle (64-bit PCI) */
259 PCIMulRW = (1 << 3), /* Enable PCI read/write multiple */
260 CpRxOn = (1 << 1), /* Rx mode enable */
261 CpTxOn = (1 << 0), /* Tx mode enable */
262
263 /* Cfg9436 EEPROM control register */
264 Cfg9346_Lock = 0x00, /* Lock ConfigX/MII register access */
265 Cfg9346_Unlock = 0xC0, /* Unlock ConfigX/MII register access */
266
267 /* TxConfig register */
268 IFG = (1 << 25) | (1 << 24), /* standard IEEE interframe gap */
269 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
270
271 /* Early Tx Threshold register */
272 TxThreshMask = 0x3f, /* Mask bits 5-0 */
273 TxThreshMax = 2048, /* Max early Tx threshold */
274
275 /* Config1 register */
276 DriverLoaded = (1 << 5), /* Software marker, driver is loaded */
277 LWACT = (1 << 4), /* LWAKE active mode */
278 PMEnable = (1 << 0), /* Enable various PM features of chip */
279
280 /* Config3 register */
281 PARMEnable = (1 << 6), /* Enable auto-loading of PHY parms */
282 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */
283 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */
284
285 /* Config4 register */
286 LWPTN = (1 << 1), /* LWAKE Pattern */
287 LWPME = (1 << 4), /* LANWAKE vs PMEB */
288
289 /* Config5 register */
290 BWF = (1 << 6), /* Accept Broadcast wakeup frame */
291 MWF = (1 << 5), /* Accept Multicast wakeup frame */
292 UWF = (1 << 4), /* Accept Unicast wakeup frame */
293 LANWake = (1 << 1), /* Enable LANWake signal */
294 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */
295
296 cp_norx_intr_mask = PciErr | LinkChg | TxOK | TxErr | TxEmpty,
297 cp_rx_intr_mask = RxOK | RxErr | RxEmpty | RxFIFOOvr,
298 cp_intr_mask = cp_rx_intr_mask | cp_norx_intr_mask,
299};
300
301static const unsigned int cp_rx_config =
302 (RX_FIFO_THRESH << RxCfgFIFOShift) |
303 (RX_DMA_BURST << RxCfgDMAShift);
304
305struct cp_desc {
03233b90 306 __le32 opts1;
cf983019 307 __le32 opts2;
03233b90 308 __le64 addr;
1da177e4
LT		 309};
310
1da177e4 311struct cp_dma_stats {
03233b90
AV		 312 __le64 tx_ok;
313 __le64 rx_ok;
314 __le64 tx_err;
315 __le32 rx_err;
316 __le16 rx_fifo;
317 __le16 frame_align;
318 __le32 tx_ok_1col;
319 __le32 tx_ok_mcol;
320 __le64 rx_ok_phys;
321 __le64 rx_ok_bcast;
322 __le32 rx_ok_mcast;
323 __le16 tx_abort;
324 __le16 tx_underrun;
ba2d3587 325} __packed;
1da177e4
LT		 326
327struct cp_extra_stats {
328 unsigned long rx_frags;
329};
330
331struct cp_private {
332 void __iomem *regs;
333 struct net_device *dev;
334 spinlock_t lock;
335 u32 msg_enable;
336
bea3348e
SH		 337 struct napi_struct napi;
338
1da177e4
LT		 339 struct pci_dev *pdev;
340 u32 rx_config;
341 u16 cpcmd;
342
1da177e4 343 struct cp_extra_stats cp_stats;
1da177e4 344
d03d376d
FR		 345 unsigned rx_head ____cacheline_aligned;
346 unsigned rx_tail;
1da177e4 347 struct cp_desc *rx_ring;
0ba894d4 348 struct sk_buff *rx_skb[CP_RX_RING_SIZE];
1da177e4
LT		 349
350 unsigned tx_head ____cacheline_aligned;
351 unsigned tx_tail;
1da177e4 352 struct cp_desc *tx_ring;
48907e39 353 struct sk_buff *tx_skb[CP_TX_RING_SIZE];
d03d376d
FR		 354
355 unsigned rx_buf_sz;
356 unsigned wol_enabled : 1; /* Is Wake-on-LAN enabled? */
1da177e4
LT		 357
358#if CP_VLAN_TAG_USED
359 struct vlan_group *vlgrp;
360#endif
d03d376d 361 dma_addr_t ring_dma;
1da177e4
LT		 362
363 struct mii_if_info mii_if;
364};
365
366#define cpr8(reg) readb(cp->regs + (reg))
367#define cpr16(reg) readw(cp->regs + (reg))
368#define cpr32(reg) readl(cp->regs + (reg))
369#define cpw8(reg,val) writeb((val), cp->regs + (reg))
370#define cpw16(reg,val) writew((val), cp->regs + (reg))
371#define cpw32(reg,val) writel((val), cp->regs + (reg))
372#define cpw8_f(reg,val) do { \
373 writeb((val), cp->regs + (reg)); \
374 readb(cp->regs + (reg)); \
375 } while (0)
376#define cpw16_f(reg,val) do { \
377 writew((val), cp->regs + (reg)); \
378 readw(cp->regs + (reg)); \
379 } while (0)
380#define cpw32_f(reg,val) do { \
381 writel((val), cp->regs + (reg)); \
382 readl(cp->regs + (reg)); \
383 } while (0)
384
385
386static void __cp_set_rx_mode (struct net_device *dev);
387static void cp_tx (struct cp_private *cp);
388static void cp_clean_rings (struct cp_private *cp);
7502cd10
SK		 389#ifdef CONFIG_NET_POLL_CONTROLLER
390static void cp_poll_controller(struct net_device *dev);
391#endif
722fdb33
PC		 392static int cp_get_eeprom_len(struct net_device *dev);
393static int cp_get_eeprom(struct net_device *dev,
394 struct ethtool_eeprom *eeprom, u8 *data);
395static int cp_set_eeprom(struct net_device *dev,
396 struct ethtool_eeprom *eeprom, u8 *data);
1da177e4 397
a3aa1884 398static DEFINE_PCI_DEVICE_TABLE(cp_pci_tbl) = {
cccb20d3
FR		 399 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, PCI_DEVICE_ID_REALTEK_8139), },
400 { PCI_DEVICE(PCI_VENDOR_ID_TTTECH, PCI_DEVICE_ID_TTTECH_MC322), },
1da177e4
LT		 401 { },
402};
403MODULE_DEVICE_TABLE(pci, cp_pci_tbl);
404
405static struct {
406 const char str[ETH_GSTRING_LEN];
407} ethtool_stats_keys[] = {
408 { "tx_ok" },
409 { "rx_ok" },
410 { "tx_err" },
411 { "rx_err" },
412 { "rx_fifo" },
413 { "frame_align" },
414 { "tx_ok_1col" },
415 { "tx_ok_mcol" },
416 { "rx_ok_phys" },
417 { "rx_ok_bcast" },
418 { "rx_ok_mcast" },
419 { "tx_abort" },
420 { "tx_underrun" },
421 { "rx_frags" },
422};
423
424
425#if CP_VLAN_TAG_USED
426static void cp_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
427{
428 struct cp_private *cp = netdev_priv(dev);
429 unsigned long flags;
430
431 spin_lock_irqsave(&cp->lock, flags);
432 cp->vlgrp = grp;
7b332244
SH		 433 if (grp)
434 cp->cpcmd |= RxVlanOn;
435 else
436 cp->cpcmd &= ~RxVlanOn;
1da177e4 437
1da177e4 438 cpw16(CpCmd, cp->cpcmd);
1da177e4
LT		 439 spin_unlock_irqrestore(&cp->lock, flags);
440}
441#endif /* CP_VLAN_TAG_USED */
442
443static inline void cp_set_rxbufsize (struct cp_private *cp)
444{
445 unsigned int mtu = cp->dev->mtu;
f3b197ac 446
1da177e4
LT		 447 if (mtu > ETH_DATA_LEN)
448 /* MTU + ethernet header + FCS + optional VLAN tag */
449 cp->rx_buf_sz = mtu + ETH_HLEN + 8;
450 else
451 cp->rx_buf_sz = PKT_BUF_SZ;
452}
453
454static inline void cp_rx_skb (struct cp_private *cp, struct sk_buff *skb,
455 struct cp_desc *desc)
456{
457 skb->protocol = eth_type_trans (skb, cp->dev);
458
237225f7
PZ		 459 cp->dev->stats.rx_packets++;
460 cp->dev->stats.rx_bytes += skb->len;
1da177e4
LT		 461
462#if CP_VLAN_TAG_USED
cf983019 463 if (cp->vlgrp && (desc->opts2 & cpu_to_le32(RxVlanTagged))) {
1da177e4 464 vlan_hwaccel_receive_skb(skb, cp->vlgrp,
cf983019 465 swab16(le32_to_cpu(desc->opts2) & 0xffff));
1da177e4
LT		 466 } else
467#endif
468 netif_receive_skb(skb);
469}
470
471static void cp_rx_err_acct (struct cp_private *cp, unsigned rx_tail,
472 u32 status, u32 len)
473{
b4f18b3f
JP		 474 netif_dbg(cp, rx_err, cp->dev, "rx err, slot %d status 0x%x len %d\n",
475 rx_tail, status, len);
237225f7 476 cp->dev->stats.rx_errors++;
1da177e4 477 if (status & RxErrFrame)
237225f7 478 cp->dev->stats.rx_frame_errors++;
1da177e4 479 if (status & RxErrCRC)
237225f7 480 cp->dev->stats.rx_crc_errors++;
1da177e4 481 if ((status & RxErrRunt) || (status & RxErrLong))
237225f7 482 cp->dev->stats.rx_length_errors++;
1da177e4 483 if ((status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag))
237225f7 484 cp->dev->stats.rx_length_errors++;
1da177e4 485 if (status & RxErrFIFO)
237225f7 486 cp->dev->stats.rx_fifo_errors++;
1da177e4
LT		 487}
488
489static inline unsigned int cp_rx_csum_ok (u32 status)
490{
491 unsigned int protocol = (status >> 16) & 0x3;
f3b197ac 492
24b7ea9f
SW		 493 if (((protocol == RxProtoTCP) && !(status & TCPFail)) ||
494 ((protocol == RxProtoUDP) && !(status & UDPFail)))
1da177e4 495 return 1;
24b7ea9f
SW		 496 else
497 return 0;
1da177e4
LT		 498}
499
bea3348e 500static int cp_rx_poll(struct napi_struct *napi, int budget)
1da177e4 501{
bea3348e
SH		 502 struct cp_private *cp = container_of(napi, struct cp_private, napi);
503 struct net_device *dev = cp->dev;
504 unsigned int rx_tail = cp->rx_tail;
505 int rx;
1da177e4
LT		 506
507rx_status_loop:
508 rx = 0;
509 cpw16(IntrStatus, cp_rx_intr_mask);
510
511 while (1) {
512 u32 status, len;
513 dma_addr_t mapping;
514 struct sk_buff *skb, *new_skb;
515 struct cp_desc *desc;
839d1624 516 const unsigned buflen = cp->rx_buf_sz;
1da177e4 517
0ba894d4 518 skb = cp->rx_skb[rx_tail];
5d9428de 519 BUG_ON(!skb);
1da177e4
LT		 520
521 desc = &cp->rx_ring[rx_tail];
522 status = le32_to_cpu(desc->opts1);
523 if (status & DescOwn)
524 break;
525
526 len = (status & 0x1fff) - 4;
3598b57b 527 mapping = le64_to_cpu(desc->addr);
1da177e4
LT		 528
529 if ((status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag)) {
530 /* we don't support incoming fragmented frames.
531 * instead, we attempt to ensure that the
532 * pre-allocated RX skbs are properly sized such
533 * that RX fragments are never encountered
534 */
535 cp_rx_err_acct(cp, rx_tail, status, len);
237225f7 536 dev->stats.rx_dropped++;
1da177e4
LT		 537 cp->cp_stats.rx_frags++;
538 goto rx_next;
539 }
540
541 if (status & (RxError | RxErrFIFO)) {
542 cp_rx_err_acct(cp, rx_tail, status, len);
543 goto rx_next;
544 }
545
b4f18b3f
JP		 546 netif_dbg(cp, rx_status, dev, "rx slot %d status 0x%x len %d\n",
547 rx_tail, status, len);
1da177e4 548
89d71a66 549 new_skb = netdev_alloc_skb_ip_align(dev, buflen);
1da177e4 550 if (!new_skb) {
237225f7 551 dev->stats.rx_dropped++;
1da177e4
LT		 552 goto rx_next;
553 }
554
6cc92cdd 555 dma_unmap_single(&cp->pdev->dev, mapping,
1da177e4
LT		 556 buflen, PCI_DMA_FROMDEVICE);
557
558 /* Handle checksum offloading for incoming packets. */
559 if (cp_rx_csum_ok(status))
560 skb->ip_summed = CHECKSUM_UNNECESSARY;
561 else
bc8acf2c 562 skb_checksum_none_assert(skb);
1da177e4
LT		 563
564 skb_put(skb, len);
565
6cc92cdd 566 mapping = dma_map_single(&cp->pdev->dev, new_skb->data, buflen,
3598b57b 567 PCI_DMA_FROMDEVICE);
0ba894d4 568 cp->rx_skb[rx_tail] = new_skb;
1da177e4
LT		 569
570 cp_rx_skb(cp, skb, desc);
571 rx++;
572
573rx_next:
574 cp->rx_ring[rx_tail].opts2 = 0;
575 cp->rx_ring[rx_tail].addr = cpu_to_le64(mapping);
576 if (rx_tail == (CP_RX_RING_SIZE - 1))
577 desc->opts1 = cpu_to_le32(DescOwn | RingEnd |
578 cp->rx_buf_sz);
579 else
580 desc->opts1 = cpu_to_le32(DescOwn | cp->rx_buf_sz);
581 rx_tail = NEXT_RX(rx_tail);
582
bea3348e 583 if (rx >= budget)
1da177e4
LT		 584 break;
585 }
586
587 cp->rx_tail = rx_tail;
588
1da177e4
LT		 589 /* if we did not reach work limit, then we're done with
590 * this round of polling
591 */
bea3348e 592 if (rx < budget) {
d15e9c4d
FR		 593 unsigned long flags;
594
1da177e4
LT		 595 if (cpr16(IntrStatus) & cp_rx_intr_mask)
596 goto rx_status_loop;
597
bea3348e 598 spin_lock_irqsave(&cp->lock, flags);
288379f0 599 __napi_complete(napi);
349124a0 600 cpw16_f(IntrMask, cp_intr_mask);
bea3348e 601 spin_unlock_irqrestore(&cp->lock, flags);
1da177e4
LT		 602 }
603
bea3348e 604 return rx;
1da177e4
LT		 605}
606
7d12e780 607static irqreturn_t cp_interrupt (int irq, void *dev_instance)
1da177e4
LT		 608{
609 struct net_device *dev = dev_instance;
610 struct cp_private *cp;
611 u16 status;
612
613 if (unlikely(dev == NULL))
614 return IRQ_NONE;
615 cp = netdev_priv(dev);
616
617 status = cpr16(IntrStatus);
618 if (!status || (status == 0xFFFF))
619 return IRQ_NONE;
620
b4f18b3f
JP		 621 netif_dbg(cp, intr, dev, "intr, status %04x cmd %02x cpcmd %04x\n",
622 status, cpr8(Cmd), cpr16(CpCmd));
1da177e4
LT		 623
624 cpw16(IntrStatus, status & ~cp_rx_intr_mask);
625
626 spin_lock(&cp->lock);
627
628 /* close possible race's with dev_close */
629 if (unlikely(!netif_running(dev))) {
630 cpw16(IntrMask, 0);
631 spin_unlock(&cp->lock);
632 return IRQ_HANDLED;
633 }
634
635 if (status & (RxOK | RxErr | RxEmpty | RxFIFOOvr))
288379f0 636 if (napi_schedule_prep(&cp->napi)) {
1da177e4 637 cpw16_f(IntrMask, cp_norx_intr_mask);
288379f0 638 __napi_schedule(&cp->napi);
1da177e4
LT		 639 }
640
641 if (status & (TxOK | TxErr | TxEmpty | SWInt))
642 cp_tx(cp);
643 if (status & LinkChg)
2501f843 644 mii_check_media(&cp->mii_if, netif_msg_link(cp), false);
1da177e4
LT		 645
646 spin_unlock(&cp->lock);
647
648 if (status & PciErr) {
649 u16 pci_status;
650
651 pci_read_config_word(cp->pdev, PCI_STATUS, &pci_status);
652 pci_write_config_word(cp->pdev, PCI_STATUS, pci_status);
b4f18b3f
JP		 653 netdev_err(dev, "PCI bus error, status=%04x, PCI status=%04x\n",
654 status, pci_status);
1da177e4
LT		 655
656 /* TODO: reset hardware */
657 }
658
659 return IRQ_HANDLED;
660}
661
7502cd10
SK		 662#ifdef CONFIG_NET_POLL_CONTROLLER
663/*
664 * Polling receive - used by netconsole and other diagnostic tools
665 * to allow network i/o with interrupts disabled.
666 */
667static void cp_poll_controller(struct net_device *dev)
668{
669 disable_irq(dev->irq);
7d12e780 670 cp_interrupt(dev->irq, dev);
7502cd10
SK		 671 enable_irq(dev->irq);
672}
673#endif
674
1da177e4
LT		 675static void cp_tx (struct cp_private *cp)
676{
677 unsigned tx_head = cp->tx_head;
678 unsigned tx_tail = cp->tx_tail;
679
680 while (tx_tail != tx_head) {
3598b57b 681 struct cp_desc *txd = cp->tx_ring + tx_tail;
1da177e4
LT		 682 struct sk_buff *skb;
683 u32 status;
684
685 rmb();
3598b57b 686 status = le32_to_cpu(txd->opts1);
1da177e4
LT		 687 if (status & DescOwn)
688 break;
689
48907e39 690 skb = cp->tx_skb[tx_tail];
5d9428de 691 BUG_ON(!skb);
1da177e4 692
6cc92cdd 693 dma_unmap_single(&cp->pdev->dev, le64_to_cpu(txd->addr),
48907e39
FR		 694 le32_to_cpu(txd->opts1) & 0xffff,
695 PCI_DMA_TODEVICE);
1da177e4
LT		 696
697 if (status & LastFrag) {
698 if (status & (TxError | TxFIFOUnder)) {
b4f18b3f
JP		 699 netif_dbg(cp, tx_err, cp->dev,
700 "tx err, status 0x%x\n", status);
237225f7 701 cp->dev->stats.tx_errors++;
1da177e4 702 if (status & TxOWC)
237225f7 703 cp->dev->stats.tx_window_errors++;
1da177e4 704 if (status & TxMaxCol)
237225f7 705 cp->dev->stats.tx_aborted_errors++;
1da177e4 706 if (status & TxLinkFail)
237225f7 707 cp->dev->stats.tx_carrier_errors++;
1da177e4 708 if (status & TxFIFOUnder)
237225f7 709 cp->dev->stats.tx_fifo_errors++;
1da177e4 710 } else {
237225f7 711 cp->dev->stats.collisions +=
1da177e4 712 ((status >> TxColCntShift) & TxColCntMask);
237225f7
PZ		 713 cp->dev->stats.tx_packets++;
714 cp->dev->stats.tx_bytes += skb->len;
b4f18b3f
JP		 715 netif_dbg(cp, tx_done, cp->dev,
716 "tx done, slot %d\n", tx_tail);
1da177e4
LT		 717 }
718 dev_kfree_skb_irq(skb);
719 }
720
48907e39 721 cp->tx_skb[tx_tail] = NULL;
1da177e4
LT		 722
723 tx_tail = NEXT_TX(tx_tail);
724 }
725
726 cp->tx_tail = tx_tail;
727
728 if (TX_BUFFS_AVAIL(cp) > (MAX_SKB_FRAGS + 1))
729 netif_wake_queue(cp->dev);
730}
731
61357325
SH		 732static netdev_tx_t cp_start_xmit (struct sk_buff *skb,
733 struct net_device *dev)
1da177e4
LT		 734{
735 struct cp_private *cp = netdev_priv(dev);
736 unsigned entry;
fcec3456 737 u32 eor, flags;
553af567 738 unsigned long intr_flags;
1da177e4
LT		 739#if CP_VLAN_TAG_USED
740 u32 vlan_tag = 0;
741#endif
fcec3456 742 int mss = 0;
1da177e4 743
553af567 744 spin_lock_irqsave(&cp->lock, intr_flags);
1da177e4
LT		 745
746 /* This is a hard error, log it. */
747 if (TX_BUFFS_AVAIL(cp) <= (skb_shinfo(skb)->nr_frags + 1)) {
748 netif_stop_queue(dev);
553af567 749 spin_unlock_irqrestore(&cp->lock, intr_flags);
b4f18b3f 750 netdev_err(dev, "BUG! Tx Ring full when queue awake!\n");
5b548140 751 return NETDEV_TX_BUSY;
1da177e4
LT		 752 }
753
754#if CP_VLAN_TAG_USED
eab6d18d 755 if (vlan_tx_tag_present(skb))
cf983019 756 vlan_tag = TxVlanTag | swab16(vlan_tx_tag_get(skb));
1da177e4
LT		 757#endif
758
759 entry = cp->tx_head;
760 eor = (entry == (CP_TX_RING_SIZE - 1)) ? RingEnd : 0;
044a890c 761 mss = skb_shinfo(skb)->gso_size;
fcec3456 762
1da177e4
LT		 763 if (skb_shinfo(skb)->nr_frags == 0) {
764 struct cp_desc *txd = &cp->tx_ring[entry];
765 u32 len;
766 dma_addr_t mapping;
767
768 len = skb->len;
6cc92cdd 769 mapping = dma_map_single(&cp->pdev->dev, skb->data, len, PCI_DMA_TODEVICE);
1da177e4
LT		 770 CP_VLAN_TX_TAG(txd, vlan_tag);
771 txd->addr = cpu_to_le64(mapping);
772 wmb();
773
fcec3456
JG		 774 flags = eor | len | DescOwn | FirstFrag | LastFrag;
775
776 if (mss)
777 flags |= LargeSend | ((mss & MSSMask) << MSSShift);
84fa7933 778 else if (skb->ip_summed == CHECKSUM_PARTIAL) {
eddc9ec5 779 const struct iphdr *ip = ip_hdr(skb);
1da177e4 780 if (ip->protocol == IPPROTO_TCP)
fcec3456 781 flags |= IPCS | TCPCS;
1da177e4 782 else if (ip->protocol == IPPROTO_UDP)
fcec3456 783 flags |= IPCS | UDPCS;
1da177e4 784 else
5734418d 785 WARN_ON(1); /* we need a WARN() */
fcec3456
JG		 786 }
787
788 txd->opts1 = cpu_to_le32(flags);
1da177e4
LT		 789 wmb();
790
48907e39 791 cp->tx_skb[entry] = skb;
1da177e4
LT		 792 entry = NEXT_TX(entry);
793 } else {
794 struct cp_desc *txd;
795 u32 first_len, first_eor;
796 dma_addr_t first_mapping;
797 int frag, first_entry = entry;
eddc9ec5 798 const struct iphdr *ip = ip_hdr(skb);
1da177e4
LT		 799
800 /* We must give this initial chunk to the device last.
801 * Otherwise we could race with the device.
802 */
803 first_eor = eor;
804 first_len = skb_headlen(skb);
6cc92cdd 805 first_mapping = dma_map_single(&cp->pdev->dev, skb->data,
1da177e4 806 first_len, PCI_DMA_TODEVICE);
48907e39 807 cp->tx_skb[entry] = skb;
1da177e4
LT		 808 entry = NEXT_TX(entry);
809
810 for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) {
811 skb_frag_t *this_frag = &skb_shinfo(skb)->frags[frag];
812 u32 len;
813 u32 ctrl;
814 dma_addr_t mapping;
815
816 len = this_frag->size;
6cc92cdd 817 mapping = dma_map_single(&cp->pdev->dev,
1da177e4
LT		 818 ((void *) page_address(this_frag->page) +
819 this_frag->page_offset),
820 len, PCI_DMA_TODEVICE);
821 eor = (entry == (CP_TX_RING_SIZE - 1)) ? RingEnd : 0;
822
fcec3456
JG		 823 ctrl = eor | len | DescOwn;
824
825 if (mss)
826 ctrl |= LargeSend |
827 ((mss & MSSMask) << MSSShift);
84fa7933 828 else if (skb->ip_summed == CHECKSUM_PARTIAL) {
1da177e4 829 if (ip->protocol == IPPROTO_TCP)
fcec3456 830 ctrl |= IPCS | TCPCS;
1da177e4 831 else if (ip->protocol == IPPROTO_UDP)
fcec3456 832 ctrl |= IPCS | UDPCS;
1da177e4
LT		 833 else
834 BUG();
fcec3456 835 }
1da177e4
LT		 836
837 if (frag == skb_shinfo(skb)->nr_frags - 1)
838 ctrl |= LastFrag;
839
840 txd = &cp->tx_ring[entry];
841 CP_VLAN_TX_TAG(txd, vlan_tag);
842 txd->addr = cpu_to_le64(mapping);
843 wmb();
844
845 txd->opts1 = cpu_to_le32(ctrl);
846 wmb();
847
48907e39 848 cp->tx_skb[entry] = skb;
1da177e4
LT		 849 entry = NEXT_TX(entry);
850 }
851
852 txd = &cp->tx_ring[first_entry];
853 CP_VLAN_TX_TAG(txd, vlan_tag);
854 txd->addr = cpu_to_le64(first_mapping);
855 wmb();
856
84fa7933 857 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1da177e4
LT		 858 if (ip->protocol == IPPROTO_TCP)
859 txd->opts1 = cpu_to_le32(first_eor | first_len |
860 FirstFrag | DescOwn |
861 IPCS | TCPCS);
862 else if (ip->protocol == IPPROTO_UDP)
863 txd->opts1 = cpu_to_le32(first_eor | first_len |
864 FirstFrag | DescOwn |
865 IPCS | UDPCS);
866 else
867 BUG();
868 } else
869 txd->opts1 = cpu_to_le32(first_eor | first_len |
870 FirstFrag | DescOwn);
871 wmb();
872 }
873 cp->tx_head = entry;
b4f18b3f
JP		 874 netif_dbg(cp, tx_queued, cp->dev, "tx queued, slot %d, skblen %d\n",
875 entry, skb->len);
1da177e4
LT		 876 if (TX_BUFFS_AVAIL(cp) <= (MAX_SKB_FRAGS + 1))
877 netif_stop_queue(dev);
878
553af567 879 spin_unlock_irqrestore(&cp->lock, intr_flags);
1da177e4
LT		 880
881 cpw8(TxPoll, NormalTxPoll);
1da177e4 882
6ed10654 883 return NETDEV_TX_OK;
1da177e4
LT		 884}
885
886/* Set or clear the multicast filter for this adaptor.
887 This routine is not state sensitive and need not be SMP locked. */
888
889static void __cp_set_rx_mode (struct net_device *dev)
890{
891 struct cp_private *cp = netdev_priv(dev);
892 u32 mc_filter[2]; /* Multicast hash filter */
a56ed41d 893 int rx_mode;
1da177e4
LT		 894 u32 tmp;
895
896 /* Note: do not reorder, GCC is clever about common statements. */
897 if (dev->flags & IFF_PROMISC) {
898 /* Unconditionally log net taps. */
1da177e4
LT		 899 rx_mode =
900 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
901 AcceptAllPhys;
902 mc_filter[1] = mc_filter[0] = 0xffffffff;
a56ed41d 903 } else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
8e95a202 904 (dev->flags & IFF_ALLMULTI)) {
1da177e4
LT		 905 /* Too many to filter perfectly -- accept all multicasts. */
906 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
907 mc_filter[1] = mc_filter[0] = 0xffffffff;
908 } else {
22bedad3 909 struct netdev_hw_addr *ha;
1da177e4
LT		 910 rx_mode = AcceptBroadcast | AcceptMyPhys;
911 mc_filter[1] = mc_filter[0] = 0;
22bedad3
JP		 912 netdev_for_each_mc_addr(ha, dev) {
913 int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
1da177e4
LT		 914
915 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
916 rx_mode |= AcceptMulticast;
917 }
918 }
919
920 /* We can safely update without stopping the chip. */
921 tmp = cp_rx_config | rx_mode;
922 if (cp->rx_config != tmp) {
923 cpw32_f (RxConfig, tmp);
924 cp->rx_config = tmp;
925 }
926 cpw32_f (MAR0 + 0, mc_filter[0]);
927 cpw32_f (MAR0 + 4, mc_filter[1]);
928}
929
930static void cp_set_rx_mode (struct net_device *dev)
931{
932 unsigned long flags;
933 struct cp_private *cp = netdev_priv(dev);
934
935 spin_lock_irqsave (&cp->lock, flags);
936 __cp_set_rx_mode(dev);
937 spin_unlock_irqrestore (&cp->lock, flags);
938}
939
940static void __cp_get_stats(struct cp_private *cp)
941{
942 /* only lower 24 bits valid; write any value to clear */
237225f7 943 cp->dev->stats.rx_missed_errors += (cpr32 (RxMissed) & 0xffffff);
1da177e4
LT		 944 cpw32 (RxMissed, 0);
945}
946
947static struct net_device_stats *cp_get_stats(struct net_device *dev)
948{
949 struct cp_private *cp = netdev_priv(dev);
950 unsigned long flags;
951
952 /* The chip only need report frame silently dropped. */
953 spin_lock_irqsave(&cp->lock, flags);
954 if (netif_running(dev) && netif_device_present(dev))
955 __cp_get_stats(cp);
956 spin_unlock_irqrestore(&cp->lock, flags);
957
237225f7 958 return &dev->stats;
1da177e4
LT		 959}
960
961static void cp_stop_hw (struct cp_private *cp)
962{
963 cpw16(IntrStatus, ~(cpr16(IntrStatus)));
964 cpw16_f(IntrMask, 0);
965 cpw8(Cmd, 0);
966 cpw16_f(CpCmd, 0);
967 cpw16_f(IntrStatus, ~(cpr16(IntrStatus)));
968
969 cp->rx_tail = 0;
970 cp->tx_head = cp->tx_tail = 0;
971}
972
973static void cp_reset_hw (struct cp_private *cp)
974{
975 unsigned work = 1000;
976
977 cpw8(Cmd, CmdReset);
978
979 while (work--) {
980 if (!(cpr8(Cmd) & CmdReset))
981 return;
982
3173c890 983 schedule_timeout_uninterruptible(10);
1da177e4
LT		 984 }
985
b4f18b3f 986 netdev_err(cp->dev, "hardware reset timeout\n");
1da177e4
LT		 987}
988
989static inline void cp_start_hw (struct cp_private *cp)
990{
991 cpw16(CpCmd, cp->cpcmd);
992 cpw8(Cmd, RxOn | TxOn);
993}
994
995static void cp_init_hw (struct cp_private *cp)
996{
997 struct net_device *dev = cp->dev;
998 dma_addr_t ring_dma;
999
1000 cp_reset_hw(cp);
1001
1002 cpw8_f (Cfg9346, Cfg9346_Unlock);
1003
1004 /* Restore our idea of the MAC address. */
03233b90
AV		 1005 cpw32_f (MAC0 + 0, le32_to_cpu (*(__le32 *) (dev->dev_addr + 0)));
1006 cpw32_f (MAC0 + 4, le32_to_cpu (*(__le32 *) (dev->dev_addr + 4)));
1da177e4
LT		 1007
1008 cp_start_hw(cp);
1009 cpw8(TxThresh, 0x06); /* XXX convert magic num to a constant */
1010
1011 __cp_set_rx_mode(dev);
1012 cpw32_f (TxConfig, IFG | (TX_DMA_BURST << TxDMAShift));
1013
1014 cpw8(Config1, cpr8(Config1) | DriverLoaded | PMEnable);
1015 /* Disable Wake-on-LAN. Can be turned on with ETHTOOL_SWOL */
1016 cpw8(Config3, PARMEnable);
1017 cp->wol_enabled = 0;
1018
f3b197ac 1019 cpw8(Config5, cpr8(Config5) & PMEStatus);
1da177e4
LT		 1020
1021 cpw32_f(HiTxRingAddr, 0);
1022 cpw32_f(HiTxRingAddr + 4, 0);
1023
1024 ring_dma = cp->ring_dma;
1025 cpw32_f(RxRingAddr, ring_dma & 0xffffffff);
1026 cpw32_f(RxRingAddr + 4, (ring_dma >> 16) >> 16);
1027
1028 ring_dma += sizeof(struct cp_desc) * CP_RX_RING_SIZE;
1029 cpw32_f(TxRingAddr, ring_dma & 0xffffffff);
1030 cpw32_f(TxRingAddr + 4, (ring_dma >> 16) >> 16);
1031
1032 cpw16(MultiIntr, 0);
1033
1034 cpw16_f(IntrMask, cp_intr_mask);
1035
1036 cpw8_f(Cfg9346, Cfg9346_Lock);
1037}
1038
a52be1cb 1039static int cp_refill_rx(struct cp_private *cp)
1da177e4 1040{
a52be1cb 1041 struct net_device *dev = cp->dev;
1da177e4
LT		 1042 unsigned i;
1043
1044 for (i = 0; i < CP_RX_RING_SIZE; i++) {
1045 struct sk_buff *skb;
3598b57b 1046 dma_addr_t mapping;
1da177e4 1047
89d71a66 1048 skb = netdev_alloc_skb_ip_align(dev, cp->rx_buf_sz);
1da177e4
LT		 1049 if (!skb)
1050 goto err_out;
1051
6cc92cdd
JG		 1052 mapping = dma_map_single(&cp->pdev->dev, skb->data,
1053 cp->rx_buf_sz, PCI_DMA_FROMDEVICE);
0ba894d4 1054 cp->rx_skb[i] = skb;
1da177e4
LT		 1055
1056 cp->rx_ring[i].opts2 = 0;
3598b57b 1057 cp->rx_ring[i].addr = cpu_to_le64(mapping);
1da177e4
LT		 1058 if (i == (CP_RX_RING_SIZE - 1))
1059 cp->rx_ring[i].opts1 =
1060 cpu_to_le32(DescOwn | RingEnd | cp->rx_buf_sz);
1061 else
1062 cp->rx_ring[i].opts1 =
1063 cpu_to_le32(DescOwn | cp->rx_buf_sz);
1064 }
1065
1066 return 0;
1067
1068err_out:
1069 cp_clean_rings(cp);
1070 return -ENOMEM;
1071}
1072
576cfa93
FR		 1073static void cp_init_rings_index (struct cp_private *cp)
1074{
1075 cp->rx_tail = 0;
1076 cp->tx_head = cp->tx_tail = 0;
1077}
1078
1da177e4
LT		 1079static int cp_init_rings (struct cp_private *cp)
1080{
1081 memset(cp->tx_ring, 0, sizeof(struct cp_desc) * CP_TX_RING_SIZE);
1082 cp->tx_ring[CP_TX_RING_SIZE - 1].opts1 = cpu_to_le32(RingEnd);
1083
576cfa93 1084 cp_init_rings_index(cp);
1da177e4
LT		 1085
1086 return cp_refill_rx (cp);
1087}
1088
1089static int cp_alloc_rings (struct cp_private *cp)
1090{
1091 void *mem;
1092
6cc92cdd
JG		 1093 mem = dma_alloc_coherent(&cp->pdev->dev, CP_RING_BYTES,
1094 &cp->ring_dma, GFP_KERNEL);
1da177e4
LT		 1095 if (!mem)
1096 return -ENOMEM;
1097
1098 cp->rx_ring = mem;
1099 cp->tx_ring = &cp->rx_ring[CP_RX_RING_SIZE];
1100
1da177e4
LT		 1101 return cp_init_rings(cp);
1102}
1103
1104static void cp_clean_rings (struct cp_private *cp)
1105{
3598b57b 1106 struct cp_desc *desc;
1da177e4
LT		 1107 unsigned i;
1108
1da177e4 1109 for (i = 0; i < CP_RX_RING_SIZE; i++) {
0ba894d4 1110 if (cp->rx_skb[i]) {
3598b57b 1111 desc = cp->rx_ring + i;
6cc92cdd 1112 dma_unmap_single(&cp->pdev->dev,le64_to_cpu(desc->addr),
1da177e4 1113 cp->rx_buf_sz, PCI_DMA_FROMDEVICE);
0ba894d4 1114 dev_kfree_skb(cp->rx_skb[i]);
1da177e4
LT		 1115 }
1116 }
1117
1118 for (i = 0; i < CP_TX_RING_SIZE; i++) {
48907e39
FR		 1119 if (cp->tx_skb[i]) {
1120 struct sk_buff *skb = cp->tx_skb[i];
5734418d 1121
3598b57b 1122 desc = cp->tx_ring + i;
6cc92cdd 1123 dma_unmap_single(&cp->pdev->dev,le64_to_cpu(desc->addr),
48907e39
FR		 1124 le32_to_cpu(desc->opts1) & 0xffff,
1125 PCI_DMA_TODEVICE);
3598b57b 1126 if (le32_to_cpu(desc->opts1) & LastFrag)
5734418d 1127 dev_kfree_skb(skb);
237225f7 1128 cp->dev->stats.tx_dropped++;
1da177e4
LT		 1129 }
1130 }
1131
5734418d
FR		 1132 memset(cp->rx_ring, 0, sizeof(struct cp_desc) * CP_RX_RING_SIZE);
1133 memset(cp->tx_ring, 0, sizeof(struct cp_desc) * CP_TX_RING_SIZE);
1134
0ba894d4 1135 memset(cp->rx_skb, 0, sizeof(struct sk_buff *) * CP_RX_RING_SIZE);
48907e39 1136 memset(cp->tx_skb, 0, sizeof(struct sk_buff *) * CP_TX_RING_SIZE);
1da177e4
LT		 1137}
1138
1139static void cp_free_rings (struct cp_private *cp)
1140{
1141 cp_clean_rings(cp);
6cc92cdd
JG		 1142 dma_free_coherent(&cp->pdev->dev, CP_RING_BYTES, cp->rx_ring,
1143 cp->ring_dma);
1da177e4
LT		 1144 cp->rx_ring = NULL;
1145 cp->tx_ring = NULL;
1da177e4
LT		 1146}
1147
1148static int cp_open (struct net_device *dev)
1149{
1150 struct cp_private *cp = netdev_priv(dev);
1151 int rc;
1152
b4f18b3f 1153 netif_dbg(cp, ifup, dev, "enabling interface\n");
1da177e4
LT		 1154
1155 rc = cp_alloc_rings(cp);
1156 if (rc)
1157 return rc;
1158
bea3348e
SH		 1159 napi_enable(&cp->napi);
1160
1da177e4
LT		 1161 cp_init_hw(cp);
1162
1fb9df5d 1163 rc = request_irq(dev->irq, cp_interrupt, IRQF_SHARED, dev->name, dev);
1da177e4
LT		 1164 if (rc)
1165 goto err_out_hw;
1166
1167 netif_carrier_off(dev);
2501f843 1168 mii_check_media(&cp->mii_if, netif_msg_link(cp), true);
1da177e4
LT		 1169 netif_start_queue(dev);
1170
1171 return 0;
1172
1173err_out_hw:
bea3348e 1174 napi_disable(&cp->napi);
1da177e4
LT		 1175 cp_stop_hw(cp);
1176 cp_free_rings(cp);
1177 return rc;
1178}
1179
1180static int cp_close (struct net_device *dev)
1181{
1182 struct cp_private *cp = netdev_priv(dev);
1183 unsigned long flags;
1184
bea3348e
SH		 1185 napi_disable(&cp->napi);
1186
b4f18b3f 1187 netif_dbg(cp, ifdown, dev, "disabling interface\n");
1da177e4
LT		 1188
1189 spin_lock_irqsave(&cp->lock, flags);
1190
1191 netif_stop_queue(dev);
1192 netif_carrier_off(dev);
1193
1194 cp_stop_hw(cp);
1195
1196 spin_unlock_irqrestore(&cp->lock, flags);
1197
1da177e4
LT		 1198 free_irq(dev->irq, dev);
1199
1200 cp_free_rings(cp);
1201 return 0;
1202}
1203
9030c0d2
FR		 1204static void cp_tx_timeout(struct net_device *dev)
1205{
1206 struct cp_private *cp = netdev_priv(dev);
1207 unsigned long flags;
1208 int rc;
1209
b4f18b3f
JP		 1210 netdev_warn(dev, "Transmit timeout, status %2x %4x %4x %4x\n",
1211 cpr8(Cmd), cpr16(CpCmd),
1212 cpr16(IntrStatus), cpr16(IntrMask));
9030c0d2
FR		 1213
1214 spin_lock_irqsave(&cp->lock, flags);
1215
1216 cp_stop_hw(cp);
1217 cp_clean_rings(cp);
1218 rc = cp_init_rings(cp);
1219 cp_start_hw(cp);
1220
1221 netif_wake_queue(dev);
1222
1223 spin_unlock_irqrestore(&cp->lock, flags);
9030c0d2
FR		 1224}
1225
1da177e4
LT		 1226#ifdef BROKEN
1227static int cp_change_mtu(struct net_device *dev, int new_mtu)
1228{
1229 struct cp_private *cp = netdev_priv(dev);
1230 int rc;
1231 unsigned long flags;
1232
1233 /* check for invalid MTU, according to hardware limits */
1234 if (new_mtu < CP_MIN_MTU || new_mtu > CP_MAX_MTU)
1235 return -EINVAL;
1236
1237 /* if network interface not up, no need for complexity */
1238 if (!netif_running(dev)) {
1239 dev->mtu = new_mtu;
1240 cp_set_rxbufsize(cp); /* set new rx buf size */
1241 return 0;
1242 }
1243
1244 spin_lock_irqsave(&cp->lock, flags);
1245
1246 cp_stop_hw(cp); /* stop h/w and free rings */
1247 cp_clean_rings(cp);
1248
1249 dev->mtu = new_mtu;
1250 cp_set_rxbufsize(cp); /* set new rx buf size */
1251
1252 rc = cp_init_rings(cp); /* realloc and restart h/w */
1253 cp_start_hw(cp);
1254
1255 spin_unlock_irqrestore(&cp->lock, flags);
1256
1257 return rc;
1258}
1259#endif /* BROKEN */
1260
f71e1309 1261static const char mii_2_8139_map[8] = {
1da177e4
LT		 1262 BasicModeCtrl,
1263 BasicModeStatus,
1264 0,
1265 0,
1266 NWayAdvert,
1267 NWayLPAR,
1268 NWayExpansion,
1269 0
1270};
1271
1272static int mdio_read(struct net_device *dev, int phy_id, int location)
1273{
1274 struct cp_private *cp = netdev_priv(dev);
1275
1276 return location < 8 && mii_2_8139_map[location] ?
1277 readw(cp->regs + mii_2_8139_map[location]) : 0;
1278}
1279
1280
1281static void mdio_write(struct net_device *dev, int phy_id, int location,
1282 int value)
1283{
1284 struct cp_private *cp = netdev_priv(dev);
1285
1286 if (location == 0) {
1287 cpw8(Cfg9346, Cfg9346_Unlock);
1288 cpw16(BasicModeCtrl, value);
1289 cpw8(Cfg9346, Cfg9346_Lock);
1290 } else if (location < 8 && mii_2_8139_map[location])
1291 cpw16(mii_2_8139_map[location], value);
1292}
1293
1294/* Set the ethtool Wake-on-LAN settings */
1295static int netdev_set_wol (struct cp_private *cp,
1296 const struct ethtool_wolinfo *wol)
1297{
1298 u8 options;
1299
1300 options = cpr8 (Config3) & ~(LinkUp | MagicPacket);
1301 /* If WOL is being disabled, no need for complexity */
1302 if (wol->wolopts) {
1303 if (wol->wolopts & WAKE_PHY) options |= LinkUp;
1304 if (wol->wolopts & WAKE_MAGIC) options |= MagicPacket;
1305 }
1306
1307 cpw8 (Cfg9346, Cfg9346_Unlock);
1308 cpw8 (Config3, options);
1309 cpw8 (Cfg9346, Cfg9346_Lock);
1310
1311 options = 0; /* Paranoia setting */
1312 options = cpr8 (Config5) & ~(UWF | MWF | BWF);
1313 /* If WOL is being disabled, no need for complexity */
1314 if (wol->wolopts) {
1315 if (wol->wolopts & WAKE_UCAST) options |= UWF;
1316 if (wol->wolopts & WAKE_BCAST) options |= BWF;
1317 if (wol->wolopts & WAKE_MCAST) options |= MWF;
1318 }
1319
1320 cpw8 (Config5, options);
1321
1322 cp->wol_enabled = (wol->wolopts) ? 1 : 0;
1323
1324 return 0;
1325}
1326
1327/* Get the ethtool Wake-on-LAN settings */
1328static void netdev_get_wol (struct cp_private *cp,
1329 struct ethtool_wolinfo *wol)
1330{
1331 u8 options;
1332
1333 wol->wolopts = 0; /* Start from scratch */
1334 wol->supported = WAKE_PHY | WAKE_BCAST | WAKE_MAGIC |
1335 WAKE_MCAST | WAKE_UCAST;
1336 /* We don't need to go on if WOL is disabled */
1337 if (!cp->wol_enabled) return;
f3b197ac 1338
1da177e4
LT		 1339 options = cpr8 (Config3);
1340 if (options & LinkUp) wol->wolopts |= WAKE_PHY;
1341 if (options & MagicPacket) wol->wolopts |= WAKE_MAGIC;
1342
1343 options = 0; /* Paranoia setting */
1344 options = cpr8 (Config5);
1345 if (options & UWF) wol->wolopts |= WAKE_UCAST;
1346 if (options & BWF) wol->wolopts |= WAKE_BCAST;
1347 if (options & MWF) wol->wolopts |= WAKE_MCAST;
1348}
1349
1350static void cp_get_drvinfo (struct net_device *dev, struct ethtool_drvinfo *info)
1351{
1352 struct cp_private *cp = netdev_priv(dev);
1353
1354 strcpy (info->driver, DRV_NAME);
1355 strcpy (info->version, DRV_VERSION);
1356 strcpy (info->bus_info, pci_name(cp->pdev));
1357}
1358
1359static int cp_get_regs_len(struct net_device *dev)
1360{
1361 return CP_REGS_SIZE;
1362}
1363
b9f2c044 1364static int cp_get_sset_count (struct net_device *dev, int sset)
1da177e4 1365{
b9f2c044
JG		 1366 switch (sset) {
1367 case ETH_SS_STATS:
1368 return CP_NUM_STATS;
1369 default:
1370 return -EOPNOTSUPP;
1371 }
1da177e4
LT		 1372}
1373
1374static int cp_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1375{
1376 struct cp_private *cp = netdev_priv(dev);
1377 int rc;
1378 unsigned long flags;
1379
1380 spin_lock_irqsave(&cp->lock, flags);
1381 rc = mii_ethtool_gset(&cp->mii_if, cmd);
1382 spin_unlock_irqrestore(&cp->lock, flags);
1383
1384 return rc;
1385}
1386
1387static int cp_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1388{
1389 struct cp_private *cp = netdev_priv(dev);
1390 int rc;
1391 unsigned long flags;
1392
1393 spin_lock_irqsave(&cp->lock, flags);
1394 rc = mii_ethtool_sset(&cp->mii_if, cmd);
1395 spin_unlock_irqrestore(&cp->lock, flags);
1396
1397 return rc;
1398}
1399
1400static int cp_nway_reset(struct net_device *dev)
1401{
1402 struct cp_private *cp = netdev_priv(dev);
1403 return mii_nway_restart(&cp->mii_if);
1404}
1405
1406static u32 cp_get_msglevel(struct net_device *dev)
1407{
1408 struct cp_private *cp = netdev_priv(dev);
1409 return cp->msg_enable;
1410}
1411
1412static void cp_set_msglevel(struct net_device *dev, u32 value)
1413{
1414 struct cp_private *cp = netdev_priv(dev);
1415 cp->msg_enable = value;
1416}
1417
044a890c 1418static int cp_set_features(struct net_device *dev, u32 features)
1da177e4
LT		 1419{
1420 struct cp_private *cp = netdev_priv(dev);
044a890c 1421 unsigned long flags;
1da177e4 1422
044a890c
MM		 1423 if (!((dev->features ^ features) & NETIF_F_RXCSUM))
1424 return 0;
1da177e4 1425
044a890c 1426 spin_lock_irqsave(&cp->lock, flags);
1da177e4 1427
044a890c
MM		 1428 if (features & NETIF_F_RXCSUM)
1429 cp->cpcmd |= RxChkSum;
1da177e4 1430 else
044a890c 1431 cp->cpcmd &= ~RxChkSum;
1da177e4 1432
044a890c
MM		 1433 cpw16_f(CpCmd, cp->cpcmd);
1434 spin_unlock_irqrestore(&cp->lock, flags);
1da177e4
LT		 1435
1436 return 0;
1437}
1438
1439static void cp_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1440 void *p)
1441{
1442 struct cp_private *cp = netdev_priv(dev);
1443 unsigned long flags;
1444
1445 if (regs->len < CP_REGS_SIZE)
1446 return /* -EINVAL */;
1447
1448 regs->version = CP_REGS_VER;
1449
1450 spin_lock_irqsave(&cp->lock, flags);
1451 memcpy_fromio(p, cp->regs, CP_REGS_SIZE);
1452 spin_unlock_irqrestore(&cp->lock, flags);
1453}
1454
1455static void cp_get_wol (struct net_device *dev, struct ethtool_wolinfo *wol)
1456{
1457 struct cp_private *cp = netdev_priv(dev);
1458 unsigned long flags;
1459
1460 spin_lock_irqsave (&cp->lock, flags);
1461 netdev_get_wol (cp, wol);
1462 spin_unlock_irqrestore (&cp->lock, flags);
1463}
1464
1465static int cp_set_wol (struct net_device *dev, struct ethtool_wolinfo *wol)
1466{
1467 struct cp_private *cp = netdev_priv(dev);
1468 unsigned long flags;
1469 int rc;
1470
1471 spin_lock_irqsave (&cp->lock, flags);
1472 rc = netdev_set_wol (cp, wol);
1473 spin_unlock_irqrestore (&cp->lock, flags);
1474
1475 return rc;
1476}
1477
1478static void cp_get_strings (struct net_device *dev, u32 stringset, u8 *buf)
1479{
1480 switch (stringset) {
1481 case ETH_SS_STATS:
1482 memcpy(buf, &ethtool_stats_keys, sizeof(ethtool_stats_keys));
1483 break;
1484 default:
1485 BUG();
1486 break;
1487 }
1488}
1489
1490static void cp_get_ethtool_stats (struct net_device *dev,
1491 struct ethtool_stats *estats, u64 *tmp_stats)
1492{
1493 struct cp_private *cp = netdev_priv(dev);
8b512927
SH		 1494 struct cp_dma_stats *nic_stats;
1495 dma_addr_t dma;
1da177e4
LT		 1496 int i;
1497
6cc92cdd
JG		 1498 nic_stats = dma_alloc_coherent(&cp->pdev->dev, sizeof(*nic_stats),
1499 &dma, GFP_KERNEL);
8b512927
SH		 1500 if (!nic_stats)
1501 return;
97f568d8 1502
1da177e4 1503 /* begin NIC statistics dump */
8b512927 1504 cpw32(StatsAddr + 4, (u64)dma >> 32);
284901a9 1505 cpw32(StatsAddr, ((u64)dma & DMA_BIT_MASK(32)) | DumpStats);
1da177e4
LT		 1506 cpr32(StatsAddr);
1507
97f568d8 1508 for (i = 0; i < 1000; i++) {
1da177e4
LT		 1509 if ((cpr32(StatsAddr) & DumpStats) == 0)
1510 break;
97f568d8 1511 udelay(10);
1da177e4 1512 }
97f568d8
SH		 1513 cpw32(StatsAddr, 0);
1514 cpw32(StatsAddr + 4, 0);
8b512927 1515 cpr32(StatsAddr);
1da177e4
LT		 1516
1517 i = 0;
8b512927
SH		 1518 tmp_stats[i++] = le64_to_cpu(nic_stats->tx_ok);
1519 tmp_stats[i++] = le64_to_cpu(nic_stats->rx_ok);
1520 tmp_stats[i++] = le64_to_cpu(nic_stats->tx_err);
1521 tmp_stats[i++] = le32_to_cpu(nic_stats->rx_err);
1522 tmp_stats[i++] = le16_to_cpu(nic_stats->rx_fifo);
1523 tmp_stats[i++] = le16_to_cpu(nic_stats->frame_align);
1524 tmp_stats[i++] = le32_to_cpu(nic_stats->tx_ok_1col);
1525 tmp_stats[i++] = le32_to_cpu(nic_stats->tx_ok_mcol);
1526 tmp_stats[i++] = le64_to_cpu(nic_stats->rx_ok_phys);
1527 tmp_stats[i++] = le64_to_cpu(nic_stats->rx_ok_bcast);
1528 tmp_stats[i++] = le32_to_cpu(nic_stats->rx_ok_mcast);
1529 tmp_stats[i++] = le16_to_cpu(nic_stats->tx_abort);
1530 tmp_stats[i++] = le16_to_cpu(nic_stats->tx_underrun);
1da177e4 1531 tmp_stats[i++] = cp->cp_stats.rx_frags;
5d9428de 1532 BUG_ON(i != CP_NUM_STATS);
8b512927 1533
6cc92cdd 1534 dma_free_coherent(&cp->pdev->dev, sizeof(*nic_stats), nic_stats, dma);
1da177e4
LT		 1535}
1536
7282d491 1537static const struct ethtool_ops cp_ethtool_ops = {
1da177e4
LT		 1538 .get_drvinfo = cp_get_drvinfo,
1539 .get_regs_len = cp_get_regs_len,
b9f2c044 1540 .get_sset_count = cp_get_sset_count,
1da177e4
LT		 1541 .get_settings = cp_get_settings,
1542 .set_settings = cp_set_settings,
1543 .nway_reset = cp_nway_reset,
1544 .get_link = ethtool_op_get_link,
1545 .get_msglevel = cp_get_msglevel,
1546 .set_msglevel = cp_set_msglevel,
1da177e4
LT		 1547 .get_regs = cp_get_regs,
1548 .get_wol = cp_get_wol,
1549 .set_wol = cp_set_wol,
1550 .get_strings = cp_get_strings,
1551 .get_ethtool_stats = cp_get_ethtool_stats,
722fdb33
PC		 1552 .get_eeprom_len = cp_get_eeprom_len,
1553 .get_eeprom = cp_get_eeprom,
1554 .set_eeprom = cp_set_eeprom,
1da177e4
LT		 1555};
1556
1557static int cp_ioctl (struct net_device *dev, struct ifreq *rq, int cmd)
1558{
1559 struct cp_private *cp = netdev_priv(dev);
1560 int rc;
1561 unsigned long flags;
1562
1563 if (!netif_running(dev))
1564 return -EINVAL;
1565
1566 spin_lock_irqsave(&cp->lock, flags);
1567 rc = generic_mii_ioctl(&cp->mii_if, if_mii(rq), cmd, NULL);
1568 spin_unlock_irqrestore(&cp->lock, flags);
1569 return rc;
1570}
1571
c048aaf4
JP		 1572static int cp_set_mac_address(struct net_device *dev, void *p)
1573{
1574 struct cp_private *cp = netdev_priv(dev);
1575 struct sockaddr *addr = p;
1576
1577 if (!is_valid_ether_addr(addr->sa_data))
1578 return -EADDRNOTAVAIL;
1579
1580 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
1581
1582 spin_lock_irq(&cp->lock);
1583
1584 cpw8_f(Cfg9346, Cfg9346_Unlock);
1585 cpw32_f(MAC0 + 0, le32_to_cpu (*(__le32 *) (dev->dev_addr + 0)));
1586 cpw32_f(MAC0 + 4, le32_to_cpu (*(__le32 *) (dev->dev_addr + 4)));
1587 cpw8_f(Cfg9346, Cfg9346_Lock);
1588
1589 spin_unlock_irq(&cp->lock);
1590
1591 return 0;
1592}
1593
1da177e4
LT		 1594/* Serial EEPROM section. */
1595
1596/* EEPROM_Ctrl bits. */
1597#define EE_SHIFT_CLK 0x04 /* EEPROM shift clock. */
1598#define EE_CS 0x08 /* EEPROM chip select. */
1599#define EE_DATA_WRITE 0x02 /* EEPROM chip data in. */
1600#define EE_WRITE_0 0x00
1601#define EE_WRITE_1 0x02
1602#define EE_DATA_READ 0x01 /* EEPROM chip data out. */
1603#define EE_ENB (0x80 | EE_CS)
1604
1605/* Delay between EEPROM clock transitions.
1606 No extra delay is needed with 33Mhz PCI, but 66Mhz may change this.
1607 */
1608
1609#define eeprom_delay() readl(ee_addr)
1610
1611/* The EEPROM commands include the alway-set leading bit. */
722fdb33 1612#define EE_EXTEND_CMD (4)
1da177e4
LT		 1613#define EE_WRITE_CMD (5)
1614#define EE_READ_CMD (6)
1615#define EE_ERASE_CMD (7)
1616
722fdb33
PC		 1617#define EE_EWDS_ADDR (0)
1618#define EE_WRAL_ADDR (1)
1619#define EE_ERAL_ADDR (2)
1620#define EE_EWEN_ADDR (3)
1621
1622#define CP_EEPROM_MAGIC PCI_DEVICE_ID_REALTEK_8139
1da177e4 1623
722fdb33
PC		 1624static void eeprom_cmd_start(void __iomem *ee_addr)
1625{
1da177e4
LT		 1626 writeb (EE_ENB & ~EE_CS, ee_addr);
1627 writeb (EE_ENB, ee_addr);
1628 eeprom_delay ();
722fdb33 1629}
1da177e4 1630
722fdb33
PC		 1631static void eeprom_cmd(void __iomem *ee_addr, int cmd, int cmd_len)
1632{
1633 int i;
1634
1635 /* Shift the command bits out. */
1636 for (i = cmd_len - 1; i >= 0; i--) {
1637 int dataval = (cmd & (1 << i)) ? EE_DATA_WRITE : 0;
1da177e4
LT		 1638 writeb (EE_ENB | dataval, ee_addr);
1639 eeprom_delay ();
1640 writeb (EE_ENB | dataval | EE_SHIFT_CLK, ee_addr);
1641 eeprom_delay ();
1642 }
1643 writeb (EE_ENB, ee_addr);
1644 eeprom_delay ();
722fdb33
PC		 1645}
1646
1647static void eeprom_cmd_end(void __iomem *ee_addr)
1648{
1649 writeb (~EE_CS, ee_addr);
1650 eeprom_delay ();
1651}
1652
1653static void eeprom_extend_cmd(void __iomem *ee_addr, int extend_cmd,
1654 int addr_len)
1655{
1656 int cmd = (EE_EXTEND_CMD << addr_len) | (extend_cmd << (addr_len - 2));
1657
1658 eeprom_cmd_start(ee_addr);
1659 eeprom_cmd(ee_addr, cmd, 3 + addr_len);
1660 eeprom_cmd_end(ee_addr);
1661}
1662
1663static u16 read_eeprom (void __iomem *ioaddr, int location, int addr_len)
1664{
1665 int i;
1666 u16 retval = 0;
1667 void __iomem *ee_addr = ioaddr + Cfg9346;
1668 int read_cmd = location | (EE_READ_CMD << addr_len);
1669
1670 eeprom_cmd_start(ee_addr);
1671 eeprom_cmd(ee_addr, read_cmd, 3 + addr_len);
1da177e4
LT		 1672
1673 for (i = 16; i > 0; i--) {
1674 writeb (EE_ENB | EE_SHIFT_CLK, ee_addr);
1675 eeprom_delay ();
1676 retval =
1677 (retval << 1) | ((readb (ee_addr) & EE_DATA_READ) ? 1 :
1678 0);
1679 writeb (EE_ENB, ee_addr);
1680 eeprom_delay ();
1681 }
1682
722fdb33 1683 eeprom_cmd_end(ee_addr);
1da177e4
LT		 1684
1685 return retval;
1686}
1687
722fdb33
PC		 1688static void write_eeprom(void __iomem *ioaddr, int location, u16 val,
1689 int addr_len)
1690{
1691 int i;
1692 void __iomem *ee_addr = ioaddr + Cfg9346;
1693 int write_cmd = location | (EE_WRITE_CMD << addr_len);
1694
1695 eeprom_extend_cmd(ee_addr, EE_EWEN_ADDR, addr_len);
1696
1697 eeprom_cmd_start(ee_addr);
1698 eeprom_cmd(ee_addr, write_cmd, 3 + addr_len);
1699 eeprom_cmd(ee_addr, val, 16);
1700 eeprom_cmd_end(ee_addr);
1701
1702 eeprom_cmd_start(ee_addr);
1703 for (i = 0; i < 20000; i++)
1704 if (readb(ee_addr) & EE_DATA_READ)
1705 break;
1706 eeprom_cmd_end(ee_addr);
1707
1708 eeprom_extend_cmd(ee_addr, EE_EWDS_ADDR, addr_len);
1709}
1710
1711static int cp_get_eeprom_len(struct net_device *dev)
1712{
1713 struct cp_private *cp = netdev_priv(dev);
1714 int size;
1715
1716 spin_lock_irq(&cp->lock);
1717 size = read_eeprom(cp->regs, 0, 8) == 0x8129 ? 256 : 128;
1718 spin_unlock_irq(&cp->lock);
1719
1720 return size;
1721}
1722
1723static int cp_get_eeprom(struct net_device *dev,
1724 struct ethtool_eeprom *eeprom, u8 *data)
1725{
1726 struct cp_private *cp = netdev_priv(dev);
1727 unsigned int addr_len;
1728 u16 val;
1729 u32 offset = eeprom->offset >> 1;
1730 u32 len = eeprom->len;
1731 u32 i = 0;
1732
1733 eeprom->magic = CP_EEPROM_MAGIC;
1734
1735 spin_lock_irq(&cp->lock);
1736
1737 addr_len = read_eeprom(cp->regs, 0, 8) == 0x8129 ? 8 : 6;
1738
1739 if (eeprom->offset & 1) {
1740 val = read_eeprom(cp->regs, offset, addr_len);
1741 data[i++] = (u8)(val >> 8);
1742 offset++;
1743 }
1744
1745 while (i < len - 1) {
1746 val = read_eeprom(cp->regs, offset, addr_len);
1747 data[i++] = (u8)val;
1748 data[i++] = (u8)(val >> 8);
1749 offset++;
1750 }
1751
1752 if (i < len) {
1753 val = read_eeprom(cp->regs, offset, addr_len);
1754 data[i] = (u8)val;
1755 }
1756
1757 spin_unlock_irq(&cp->lock);
1758 return 0;
1759}
1760
1761static int cp_set_eeprom(struct net_device *dev,
1762 struct ethtool_eeprom *eeprom, u8 *data)
1763{
1764 struct cp_private *cp = netdev_priv(dev);
1765 unsigned int addr_len;
1766 u16 val;
1767 u32 offset = eeprom->offset >> 1;
1768 u32 len = eeprom->len;
1769 u32 i = 0;
1770
1771 if (eeprom->magic != CP_EEPROM_MAGIC)
1772 return -EINVAL;
1773
1774 spin_lock_irq(&cp->lock);
1775
1776 addr_len = read_eeprom(cp->regs, 0, 8) == 0x8129 ? 8 : 6;
1777
1778 if (eeprom->offset & 1) {
1779 val = read_eeprom(cp->regs, offset, addr_len) & 0xff;
1780 val |= (u16)data[i++] << 8;
1781 write_eeprom(cp->regs, offset, val, addr_len);
1782 offset++;
1783 }
1784
1785 while (i < len - 1) {
1786 val = (u16)data[i++];
1787 val |= (u16)data[i++] << 8;
1788 write_eeprom(cp->regs, offset, val, addr_len);
1789 offset++;
1790 }
1791
1792 if (i < len) {
1793 val = read_eeprom(cp->regs, offset, addr_len) & 0xff00;
1794 val |= (u16)data[i];
1795 write_eeprom(cp->regs, offset, val, addr_len);
1796 }
1797
1798 spin_unlock_irq(&cp->lock);
1799 return 0;
1800}
1801
1da177e4
LT		 1802/* Put the board into D3cold state and wait for WakeUp signal */
1803static void cp_set_d3_state (struct cp_private *cp)
1804{
1805 pci_enable_wake (cp->pdev, 0, 1); /* Enable PME# generation */
1806 pci_set_power_state (cp->pdev, PCI_D3hot);
1807}
1808
48dfcde4
SH		 1809static const struct net_device_ops cp_netdev_ops = {
1810 .ndo_open = cp_open,
1811 .ndo_stop = cp_close,
1812 .ndo_validate_addr = eth_validate_addr,
c048aaf4 1813 .ndo_set_mac_address = cp_set_mac_address,
48dfcde4
SH		 1814 .ndo_set_multicast_list = cp_set_rx_mode,
1815 .ndo_get_stats = cp_get_stats,
1816 .ndo_do_ioctl = cp_ioctl,
00829823 1817 .ndo_start_xmit = cp_start_xmit,
48dfcde4 1818 .ndo_tx_timeout = cp_tx_timeout,
044a890c 1819 .ndo_set_features = cp_set_features,
48dfcde4
SH		 1820#if CP_VLAN_TAG_USED
1821 .ndo_vlan_rx_register = cp_vlan_rx_register,
1822#endif
1823#ifdef BROKEN
1824 .ndo_change_mtu = cp_change_mtu,
1825#endif
fe96aaa1 1826
48dfcde4
SH		 1827#ifdef CONFIG_NET_POLL_CONTROLLER
1828 .ndo_poll_controller = cp_poll_controller,
1829#endif
1830};
1831
1da177e4
LT		 1832static int cp_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
1833{
1834 struct net_device *dev;
1835 struct cp_private *cp;
1836 int rc;
1837 void __iomem *regs;
2427ddd8 1838 resource_size_t pciaddr;
1da177e4 1839 unsigned int addr_len, i, pci_using_dac;
1da177e4
LT		 1840
1841#ifndef MODULE
1842 static int version_printed;
1843 if (version_printed++ == 0)
b93d5847 1844 pr_info("%s", version);
1da177e4
LT		 1845#endif
1846
1da177e4 1847 if (pdev->vendor == PCI_VENDOR_ID_REALTEK &&
44c10138 1848 pdev->device == PCI_DEVICE_ID_REALTEK_8139 && pdev->revision < 0x20) {
de4549ca 1849 dev_info(&pdev->dev,
b4f18b3f
JP		 1850 "This (id %04x:%04x rev %02x) is not an 8139C+ compatible chip, use 8139too\n",
1851 pdev->vendor, pdev->device, pdev->revision);
1da177e4
LT		 1852 return -ENODEV;
1853 }
1854
1855 dev = alloc_etherdev(sizeof(struct cp_private));
1856 if (!dev)
1857 return -ENOMEM;
1da177e4
LT		 1858 SET_NETDEV_DEV(dev, &pdev->dev);
1859
1860 cp = netdev_priv(dev);
1861 cp->pdev = pdev;
1862 cp->dev = dev;
1863 cp->msg_enable = (debug < 0 ? CP_DEF_MSG_ENABLE : debug);
1864 spin_lock_init (&cp->lock);
1865 cp->mii_if.dev = dev;
1866 cp->mii_if.mdio_read = mdio_read;
1867 cp->mii_if.mdio_write = mdio_write;
1868 cp->mii_if.phy_id = CP_INTERNAL_PHY;
1869 cp->mii_if.phy_id_mask = 0x1f;
1870 cp->mii_if.reg_num_mask = 0x1f;
1871 cp_set_rxbufsize(cp);
1872
1873 rc = pci_enable_device(pdev);
1874 if (rc)
1875 goto err_out_free;
1876
1877 rc = pci_set_mwi(pdev);
1878 if (rc)
1879 goto err_out_disable;
1880
1881 rc = pci_request_regions(pdev, DRV_NAME);
1882 if (rc)
1883 goto err_out_mwi;
1884
1885 pciaddr = pci_resource_start(pdev, 1);
1886 if (!pciaddr) {
1887 rc = -EIO;
9b91cf9d 1888 dev_err(&pdev->dev, "no MMIO resource\n");
1da177e4
LT		 1889 goto err_out_res;
1890 }
1891 if (pci_resource_len(pdev, 1) < CP_REGS_SIZE) {
1892 rc = -EIO;
9b91cf9d 1893 dev_err(&pdev->dev, "MMIO resource (%llx) too small\n",
2e8a538d 1894 (unsigned long long)pci_resource_len(pdev, 1));
1da177e4
LT		 1895 goto err_out_res;
1896 }
1897
1898 /* Configure DMA attributes. */
1899 if ((sizeof(dma_addr_t) > 4) &&
6a35528a
YH		 1900 !pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)) &&
1901 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
1da177e4
LT		 1902 pci_using_dac = 1;
1903 } else {
1904 pci_using_dac = 0;
1905
284901a9 1906 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
1da177e4 1907 if (rc) {
9b91cf9d 1908 dev_err(&pdev->dev,
b4f18b3f 1909 "No usable DMA configuration, aborting\n");
1da177e4
LT		 1910 goto err_out_res;
1911 }
284901a9 1912 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
1da177e4 1913 if (rc) {
9b91cf9d 1914 dev_err(&pdev->dev,
b4f18b3f 1915 "No usable consistent DMA configuration, aborting\n");
1da177e4
LT		 1916 goto err_out_res;
1917 }
1918 }
1919
1920 cp->cpcmd = (pci_using_dac ? PCIDAC : 0) |
1921 PCIMulRW | RxChkSum | CpRxOn | CpTxOn;
1922
044a890c
MM		 1923 dev->features |= NETIF_F_RXCSUM;
1924 dev->hw_features |= NETIF_F_RXCSUM;
1925
1da177e4
LT		 1926 regs = ioremap(pciaddr, CP_REGS_SIZE);
1927 if (!regs) {
1928 rc = -EIO;
4626dd46 1929 dev_err(&pdev->dev, "Cannot map PCI MMIO (%Lx@%Lx)\n",
b4f18b3f 1930 (unsigned long long)pci_resource_len(pdev, 1),
2e8a538d 1931 (unsigned long long)pciaddr);
1da177e4
LT		 1932 goto err_out_res;
1933 }
1934 dev->base_addr = (unsigned long) regs;
1935 cp->regs = regs;
1936
1937 cp_stop_hw(cp);
1938
1939 /* read MAC address from EEPROM */
1940 addr_len = read_eeprom (regs, 0, 8) == 0x8129 ? 8 : 6;
1941 for (i = 0; i < 3; i++)
03233b90
AV		 1942 ((__le16 *) (dev->dev_addr))[i] =
1943 cpu_to_le16(read_eeprom (regs, i + 7, addr_len));
bb0ce608 1944 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
1da177e4 1945
48dfcde4 1946 dev->netdev_ops = &cp_netdev_ops;
bea3348e 1947 netif_napi_add(dev, &cp->napi, cp_rx_poll, 16);
1da177e4 1948 dev->ethtool_ops = &cp_ethtool_ops;
1da177e4 1949 dev->watchdog_timeo = TX_TIMEOUT;
1da177e4
LT		 1950
1951#if CP_VLAN_TAG_USED
1952 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
1da177e4
LT		 1953#endif
1954
1955 if (pci_using_dac)
1956 dev->features |= NETIF_F_HIGHDMA;
1957
044a890c
MM		 1958 /* disabled by default until verified */
1959 dev->hw_features |= NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO;
fcec3456 1960
1da177e4
LT		 1961 dev->irq = pdev->irq;
1962
1963 rc = register_netdev(dev);
1964 if (rc)
1965 goto err_out_iomap;
1966
b4f18b3f
JP		 1967 netdev_info(dev, "RTL-8139C+ at 0x%lx, %pM, IRQ %d\n",
1968 dev->base_addr, dev->dev_addr, dev->irq);
1da177e4
LT		 1969
1970 pci_set_drvdata(pdev, dev);
1971
1972 /* enable busmastering and memory-write-invalidate */
1973 pci_set_master(pdev);
1974
2e8a538d
JG		 1975 if (cp->wol_enabled)
1976 cp_set_d3_state (cp);
1da177e4
LT		 1977
1978 return 0;
1979
1980err_out_iomap:
1981 iounmap(regs);
1982err_out_res:
1983 pci_release_regions(pdev);
1984err_out_mwi:
1985 pci_clear_mwi(pdev);
1986err_out_disable:
1987 pci_disable_device(pdev);
1988err_out_free:
1989 free_netdev(dev);
1990 return rc;
1991}
1992
1993static void cp_remove_one (struct pci_dev *pdev)
1994{
1995 struct net_device *dev = pci_get_drvdata(pdev);
1996 struct cp_private *cp = netdev_priv(dev);
1997
1da177e4
LT		 1998 unregister_netdev(dev);
1999 iounmap(cp->regs);
2e8a538d
JG		 2000 if (cp->wol_enabled)
2001 pci_set_power_state (pdev, PCI_D0);
1da177e4
LT		 2002 pci_release_regions(pdev);
2003 pci_clear_mwi(pdev);
2004 pci_disable_device(pdev);
2005 pci_set_drvdata(pdev, NULL);
2006 free_netdev(dev);
2007}
2008
2009#ifdef CONFIG_PM
05adc3b7 2010static int cp_suspend (struct pci_dev *pdev, pm_message_t state)
1da177e4 2011{
7668a494
FR		 2012 struct net_device *dev = pci_get_drvdata(pdev);
2013 struct cp_private *cp = netdev_priv(dev);
1da177e4
LT		 2014 unsigned long flags;
2015
7668a494
FR		 2016 if (!netif_running(dev))
2017 return 0;
1da177e4
LT		 2018
2019 netif_device_detach (dev);
2020 netif_stop_queue (dev);
2021
2022 spin_lock_irqsave (&cp->lock, flags);
2023
2024 /* Disable Rx and Tx */
2025 cpw16 (IntrMask, 0);
2026 cpw8 (Cmd, cpr8 (Cmd) & (~RxOn | ~TxOn));
2027
2028 spin_unlock_irqrestore (&cp->lock, flags);
2029
576cfa93
FR		 2030 pci_save_state(pdev);
2031 pci_enable_wake(pdev, pci_choose_state(pdev, state), cp->wol_enabled);
2032 pci_set_power_state(pdev, pci_choose_state(pdev, state));
1da177e4
LT		 2033
2034 return 0;
2035}
2036
2037static int cp_resume (struct pci_dev *pdev)
2038{
576cfa93
FR		 2039 struct net_device *dev = pci_get_drvdata (pdev);
2040 struct cp_private *cp = netdev_priv(dev);
a4cf0761 2041 unsigned long flags;
1da177e4 2042
576cfa93
FR		 2043 if (!netif_running(dev))
2044 return 0;
1da177e4
LT		 2045
2046 netif_device_attach (dev);
576cfa93
FR		 2047
2048 pci_set_power_state(pdev, PCI_D0);
2049 pci_restore_state(pdev);
2050 pci_enable_wake(pdev, PCI_D0, 0);
2051
2052 /* FIXME: sh*t may happen if the Rx ring buffer is depleted */
2053 cp_init_rings_index (cp);
1da177e4
LT		 2054 cp_init_hw (cp);
2055 netif_start_queue (dev);
a4cf0761
PO		 2056
2057 spin_lock_irqsave (&cp->lock, flags);
2058
2501f843 2059 mii_check_media(&cp->mii_if, netif_msg_link(cp), false);
a4cf0761
PO		 2060
2061 spin_unlock_irqrestore (&cp->lock, flags);
f3b197ac 2062
1da177e4
LT		 2063 return 0;
2064}
2065#endif /* CONFIG_PM */
2066
2067static struct pci_driver cp_driver = {
2068 .name = DRV_NAME,
2069 .id_table = cp_pci_tbl,
2070 .probe = cp_init_one,
2071 .remove = cp_remove_one,
2072#ifdef CONFIG_PM
2073 .resume = cp_resume,
2074 .suspend = cp_suspend,
2075#endif
2076};
2077
2078static int __init cp_init (void)
2079{
2080#ifdef MODULE
b93d5847 2081 pr_info("%s", version);
1da177e4 2082#endif
29917620 2083 return pci_register_driver(&cp_driver);
1da177e4
LT		 2084}
2085
2086static void __exit cp_exit (void)
2087{
2088 pci_unregister_driver (&cp_driver);
2089}
2090
2091module_init(cp_init);
2092module_exit(cp_exit);
Linux kernel - Deliverables
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