projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
Merge branch 'r8169-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/romieu...
[deliverable/linux.git] / drivers / net / 8139cp.c
CommitLineData
1da177e4
LT		 1/* 8139cp.c: A Linux PCI Ethernet driver for the RealTek 8139C+ chips. */
2/*
3 Copyright 2001-2004 Jeff Garzik <jgarzik@pobox.com>
4
5 Copyright (C) 2001, 2002 David S. Miller (davem@redhat.com) [tg3.c]
6 Copyright (C) 2000, 2001 David S. Miller (davem@redhat.com) [sungem.c]
7 Copyright 2001 Manfred Spraul [natsemi.c]
8 Copyright 1999-2001 by Donald Becker. [natsemi.c]
9 Written 1997-2001 by Donald Becker. [8139too.c]
10 Copyright 1998-2001 by Jes Sorensen, <jes@trained-monkey.org>. [acenic.c]
11
12 This software may be used and distributed according to the terms of
13 the GNU General Public License (GPL), incorporated herein by reference.
14 Drivers based on or derived from this code fall under the GPL and must
15 retain the authorship, copyright and license notice. This file is not
16 a complete program and may only be used when the entire operating
17 system is licensed under the GPL.
18
19 See the file COPYING in this distribution for more information.
20
21 Contributors:
f3b197ac 22
1da177e4
LT		 23 Wake-on-LAN support - Felipe Damasio <felipewd@terra.com.br>
24 PCI suspend/resume - Felipe Damasio <felipewd@terra.com.br>
25 LinkChg interrupt - Felipe Damasio <felipewd@terra.com.br>
f3b197ac 26
1da177e4
LT		 27 TODO:
28 * Test Tx checksumming thoroughly
1da177e4
LT		 29
30 Low priority TODO:
31 * Complete reset on PciErr
32 * Consider Rx interrupt mitigation using TimerIntr
33 * Investigate using skb->priority with h/w VLAN priority
34 * Investigate using High Priority Tx Queue with skb->priority
35 * Adjust Rx FIFO threshold and Max Rx DMA burst on Rx FIFO error
36 * Adjust Tx FIFO threshold and Max Tx DMA burst on Tx FIFO error
37 * Implement Tx software interrupt mitigation via
38 Tx descriptor bit
39 * The real minimum of CP_MIN_MTU is 4 bytes. However,
40 for this to be supported, one must(?) turn on packet padding.
41 * Support external MII transceivers (patch available)
42
43 NOTES:
44 * TX checksumming is considered experimental. It is off by
45 default, use ethtool to turn it on.
46
47 */
48
49#define DRV_NAME "8139cp"
d5b20697 50#define DRV_VERSION "1.3"
1da177e4
LT		 51#define DRV_RELDATE "Mar 22, 2004"
52
53
1da177e4 54#include <linux/module.h>
e21ba282 55#include <linux/moduleparam.h>
1da177e4
LT		 56#include <linux/kernel.h>
57#include <linux/compiler.h>
58#include <linux/netdevice.h>
59#include <linux/etherdevice.h>
60#include <linux/init.h>
61#include <linux/pci.h>
8662d061 62#include <linux/dma-mapping.h>
1da177e4
LT		 63#include <linux/delay.h>
64#include <linux/ethtool.h>
65#include <linux/mii.h>
66#include <linux/if_vlan.h>
67#include <linux/crc32.h>
68#include <linux/in.h>
69#include <linux/ip.h>
70#include <linux/tcp.h>
71#include <linux/udp.h>
72#include <linux/cache.h>
73#include <asm/io.h>
74#include <asm/irq.h>
75#include <asm/uaccess.h>
76
77/* VLAN tagging feature enable/disable */
78#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
79#define CP_VLAN_TAG_USED 1
80#define CP_VLAN_TX_TAG(tx_desc,vlan_tag_value) \
cf983019 81 do { (tx_desc)->opts2 = cpu_to_le32(vlan_tag_value); } while (0)
1da177e4
LT		 82#else
83#define CP_VLAN_TAG_USED 0
84#define CP_VLAN_TX_TAG(tx_desc,vlan_tag_value) \
85 do { (tx_desc)->opts2 = 0; } while (0)
86#endif
87
88/* These identify the driver base version and may not be removed. */
89static char version[] =
90KERN_INFO DRV_NAME ": 10/100 PCI Ethernet driver v" DRV_VERSION " (" DRV_RELDATE ")\n";
91
92MODULE_AUTHOR("Jeff Garzik <jgarzik@pobox.com>");
93MODULE_DESCRIPTION("RealTek RTL-8139C+ series 10/100 PCI Ethernet driver");
a78d8927 94MODULE_VERSION(DRV_VERSION);
1da177e4
LT		 95MODULE_LICENSE("GPL");
96
97static int debug = -1;
e21ba282 98module_param(debug, int, 0);
1da177e4
LT		 99MODULE_PARM_DESC (debug, "8139cp: bitmapped message enable number");
100
101/* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
102 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
103static int multicast_filter_limit = 32;
e21ba282 104module_param(multicast_filter_limit, int, 0);
1da177e4
LT		 105MODULE_PARM_DESC (multicast_filter_limit, "8139cp: maximum number of filtered multicast addresses");
106
107#define PFX DRV_NAME ": "
108
1da177e4
LT		 109#define CP_DEF_MSG_ENABLE (NETIF_MSG_DRV | \
110 NETIF_MSG_PROBE | \
111 NETIF_MSG_LINK)
112#define CP_NUM_STATS 14 /* struct cp_dma_stats, plus one */
113#define CP_STATS_SIZE 64 /* size in bytes of DMA stats block */
114#define CP_REGS_SIZE (0xff + 1)
115#define CP_REGS_VER 1 /* version 1 */
116#define CP_RX_RING_SIZE 64
117#define CP_TX_RING_SIZE 64
118#define CP_RING_BYTES \
119 ((sizeof(struct cp_desc) * CP_RX_RING_SIZE) + \
120 (sizeof(struct cp_desc) * CP_TX_RING_SIZE) + \
121 CP_STATS_SIZE)
122#define NEXT_TX(N) (((N) + 1) & (CP_TX_RING_SIZE - 1))
123#define NEXT_RX(N) (((N) + 1) & (CP_RX_RING_SIZE - 1))
124#define TX_BUFFS_AVAIL(CP) \
125 (((CP)->tx_tail <= (CP)->tx_head) ? \
126 (CP)->tx_tail + (CP_TX_RING_SIZE - 1) - (CP)->tx_head : \
127 (CP)->tx_tail - (CP)->tx_head - 1)
128
129#define PKT_BUF_SZ 1536 /* Size of each temporary Rx buffer.*/
130#define RX_OFFSET 2
131#define CP_INTERNAL_PHY 32
132
133/* The following settings are log_2(bytes)-4: 0 == 16 bytes .. 6==1024, 7==end of packet. */
134#define RX_FIFO_THRESH 5 /* Rx buffer level before first PCI xfer. */
135#define RX_DMA_BURST 4 /* Maximum PCI burst, '4' is 256 */
136#define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
137#define TX_EARLY_THRESH 256 /* Early Tx threshold, in bytes */
138
139/* Time in jiffies before concluding the transmitter is hung. */
140#define TX_TIMEOUT (6*HZ)
141
142/* hardware minimum and maximum for a single frame's data payload */
143#define CP_MIN_MTU 60 /* TODO: allow lower, but pad */
144#define CP_MAX_MTU 4096
145
146enum {
147 /* NIC register offsets */
148 MAC0 = 0x00, /* Ethernet hardware address. */
149 MAR0 = 0x08, /* Multicast filter. */
150 StatsAddr = 0x10, /* 64-bit start addr of 64-byte DMA stats blk */
151 TxRingAddr = 0x20, /* 64-bit start addr of Tx ring */
152 HiTxRingAddr = 0x28, /* 64-bit start addr of high priority Tx ring */
153 Cmd = 0x37, /* Command register */
154 IntrMask = 0x3C, /* Interrupt mask */
155 IntrStatus = 0x3E, /* Interrupt status */
156 TxConfig = 0x40, /* Tx configuration */
157 ChipVersion = 0x43, /* 8-bit chip version, inside TxConfig */
158 RxConfig = 0x44, /* Rx configuration */
159 RxMissed = 0x4C, /* 24 bits valid, write clears */
160 Cfg9346 = 0x50, /* EEPROM select/control; Cfg reg [un]lock */
161 Config1 = 0x52, /* Config1 */
162 Config3 = 0x59, /* Config3 */
163 Config4 = 0x5A, /* Config4 */
164 MultiIntr = 0x5C, /* Multiple interrupt select */
165 BasicModeCtrl = 0x62, /* MII BMCR */
166 BasicModeStatus = 0x64, /* MII BMSR */
167 NWayAdvert = 0x66, /* MII ADVERTISE */
168 NWayLPAR = 0x68, /* MII LPA */
169 NWayExpansion = 0x6A, /* MII Expansion */
170 Config5 = 0xD8, /* Config5 */
171 TxPoll = 0xD9, /* Tell chip to check Tx descriptors for work */
172 RxMaxSize = 0xDA, /* Max size of an Rx packet (8169 only) */
173 CpCmd = 0xE0, /* C+ Command register (C+ mode only) */
174 IntrMitigate = 0xE2, /* rx/tx interrupt mitigation control */
175 RxRingAddr = 0xE4, /* 64-bit start addr of Rx ring */
176 TxThresh = 0xEC, /* Early Tx threshold */
177 OldRxBufAddr = 0x30, /* DMA address of Rx ring buffer (C mode) */
178 OldTSD0 = 0x10, /* DMA address of first Tx desc (C mode) */
179
180 /* Tx and Rx status descriptors */
181 DescOwn = (1 << 31), /* Descriptor is owned by NIC */
182 RingEnd = (1 << 30), /* End of descriptor ring */
183 FirstFrag = (1 << 29), /* First segment of a packet */
184 LastFrag = (1 << 28), /* Final segment of a packet */
fcec3456
JG		 185 LargeSend = (1 << 27), /* TCP Large Send Offload (TSO) */
186 MSSShift = 16, /* MSS value position */
187 MSSMask = 0xfff, /* MSS value: 11 bits */
1da177e4
LT		 188 TxError = (1 << 23), /* Tx error summary */
189 RxError = (1 << 20), /* Rx error summary */
190 IPCS = (1 << 18), /* Calculate IP checksum */
191 UDPCS = (1 << 17), /* Calculate UDP/IP checksum */
192 TCPCS = (1 << 16), /* Calculate TCP/IP checksum */
193 TxVlanTag = (1 << 17), /* Add VLAN tag */
194 RxVlanTagged = (1 << 16), /* Rx VLAN tag available */
195 IPFail = (1 << 15), /* IP checksum failed */
196 UDPFail = (1 << 14), /* UDP/IP checksum failed */
197 TCPFail = (1 << 13), /* TCP/IP checksum failed */
198 NormalTxPoll = (1 << 6), /* One or more normal Tx packets to send */
199 PID1 = (1 << 17), /* 2 protocol id bits: 0==non-IP, */
200 PID0 = (1 << 16), /* 1==UDP/IP, 2==TCP/IP, 3==IP */
201 RxProtoTCP = 1,
202 RxProtoUDP = 2,
203 RxProtoIP = 3,
204 TxFIFOUnder = (1 << 25), /* Tx FIFO underrun */
205 TxOWC = (1 << 22), /* Tx Out-of-window collision */
206 TxLinkFail = (1 << 21), /* Link failed during Tx of packet */
207 TxMaxCol = (1 << 20), /* Tx aborted due to excessive collisions */
208 TxColCntShift = 16, /* Shift, to get 4-bit Tx collision cnt */
209 TxColCntMask = 0x01 | 0x02 | 0x04 | 0x08, /* 4-bit collision count */
210 RxErrFrame = (1 << 27), /* Rx frame alignment error */
211 RxMcast = (1 << 26), /* Rx multicast packet rcv'd */
212 RxErrCRC = (1 << 18), /* Rx CRC error */
213 RxErrRunt = (1 << 19), /* Rx error, packet < 64 bytes */
214 RxErrLong = (1 << 21), /* Rx error, packet > 4096 bytes */
215 RxErrFIFO = (1 << 22), /* Rx error, FIFO overflowed, pkt bad */
216
217 /* StatsAddr register */
218 DumpStats = (1 << 3), /* Begin stats dump */
219
220 /* RxConfig register */
221 RxCfgFIFOShift = 13, /* Shift, to get Rx FIFO thresh value */
222 RxCfgDMAShift = 8, /* Shift, to get Rx Max DMA value */
223 AcceptErr = 0x20, /* Accept packets with CRC errors */
224 AcceptRunt = 0x10, /* Accept runt (<64 bytes) packets */
225 AcceptBroadcast = 0x08, /* Accept broadcast packets */
226 AcceptMulticast = 0x04, /* Accept multicast packets */
227 AcceptMyPhys = 0x02, /* Accept pkts with our MAC as dest */
228 AcceptAllPhys = 0x01, /* Accept all pkts w/ physical dest */
229
230 /* IntrMask / IntrStatus registers */
231 PciErr = (1 << 15), /* System error on the PCI bus */
232 TimerIntr = (1 << 14), /* Asserted when TCTR reaches TimerInt value */
233 LenChg = (1 << 13), /* Cable length change */
234 SWInt = (1 << 8), /* Software-requested interrupt */
235 TxEmpty = (1 << 7), /* No Tx descriptors available */
236 RxFIFOOvr = (1 << 6), /* Rx FIFO Overflow */
237 LinkChg = (1 << 5), /* Packet underrun, or link change */
238 RxEmpty = (1 << 4), /* No Rx descriptors available */
239 TxErr = (1 << 3), /* Tx error */
240 TxOK = (1 << 2), /* Tx packet sent */
241 RxErr = (1 << 1), /* Rx error */
242 RxOK = (1 << 0), /* Rx packet received */
243 IntrResvd = (1 << 10), /* reserved, according to RealTek engineers,
244 but hardware likes to raise it */
245
246 IntrAll = PciErr | TimerIntr | LenChg | SWInt | TxEmpty |
247 RxFIFOOvr | LinkChg | RxEmpty | TxErr | TxOK |
248 RxErr | RxOK | IntrResvd,
249
250 /* C mode command register */
251 CmdReset = (1 << 4), /* Enable to reset; self-clearing */
252 RxOn = (1 << 3), /* Rx mode enable */
253 TxOn = (1 << 2), /* Tx mode enable */
254
255 /* C+ mode command register */
256 RxVlanOn = (1 << 6), /* Rx VLAN de-tagging enable */
257 RxChkSum = (1 << 5), /* Rx checksum offload enable */
258 PCIDAC = (1 << 4), /* PCI Dual Address Cycle (64-bit PCI) */
259 PCIMulRW = (1 << 3), /* Enable PCI read/write multiple */
260 CpRxOn = (1 << 1), /* Rx mode enable */
261 CpTxOn = (1 << 0), /* Tx mode enable */
262
263 /* Cfg9436 EEPROM control register */
264 Cfg9346_Lock = 0x00, /* Lock ConfigX/MII register access */
265 Cfg9346_Unlock = 0xC0, /* Unlock ConfigX/MII register access */
266
267 /* TxConfig register */
268 IFG = (1 << 25) | (1 << 24), /* standard IEEE interframe gap */
269 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
270
271 /* Early Tx Threshold register */
272 TxThreshMask = 0x3f, /* Mask bits 5-0 */
273 TxThreshMax = 2048, /* Max early Tx threshold */
274
275 /* Config1 register */
276 DriverLoaded = (1 << 5), /* Software marker, driver is loaded */
277 LWACT = (1 << 4), /* LWAKE active mode */
278 PMEnable = (1 << 0), /* Enable various PM features of chip */
279
280 /* Config3 register */
281 PARMEnable = (1 << 6), /* Enable auto-loading of PHY parms */
282 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */
283 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */
284
285 /* Config4 register */
286 LWPTN = (1 << 1), /* LWAKE Pattern */
287 LWPME = (1 << 4), /* LANWAKE vs PMEB */
288
289 /* Config5 register */
290 BWF = (1 << 6), /* Accept Broadcast wakeup frame */
291 MWF = (1 << 5), /* Accept Multicast wakeup frame */
292 UWF = (1 << 4), /* Accept Unicast wakeup frame */
293 LANWake = (1 << 1), /* Enable LANWake signal */
294 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */
295
296 cp_norx_intr_mask = PciErr | LinkChg | TxOK | TxErr | TxEmpty,
297 cp_rx_intr_mask = RxOK | RxErr | RxEmpty | RxFIFOOvr,
298 cp_intr_mask = cp_rx_intr_mask | cp_norx_intr_mask,
299};
300
301static const unsigned int cp_rx_config =
302 (RX_FIFO_THRESH << RxCfgFIFOShift) |
303 (RX_DMA_BURST << RxCfgDMAShift);
304
305struct cp_desc {
03233b90 306 __le32 opts1;
cf983019 307 __le32 opts2;
03233b90 308 __le64 addr;
1da177e4
LT		 309};
310
1da177e4 311struct cp_dma_stats {
03233b90
AV		 312 __le64 tx_ok;
313 __le64 rx_ok;
314 __le64 tx_err;
315 __le32 rx_err;
316 __le16 rx_fifo;
317 __le16 frame_align;
318 __le32 tx_ok_1col;
319 __le32 tx_ok_mcol;
320 __le64 rx_ok_phys;
321 __le64 rx_ok_bcast;
322 __le32 rx_ok_mcast;
323 __le16 tx_abort;
324 __le16 tx_underrun;
1da177e4
LT		 325} __attribute__((packed));
326
327struct cp_extra_stats {
328 unsigned long rx_frags;
329};
330
331struct cp_private {
332 void __iomem *regs;
333 struct net_device *dev;
334 spinlock_t lock;
335 u32 msg_enable;
336
bea3348e
SH		 337 struct napi_struct napi;
338
1da177e4
LT		 339 struct pci_dev *pdev;
340 u32 rx_config;
341 u16 cpcmd;
342
1da177e4 343 struct cp_extra_stats cp_stats;
1da177e4 344
d03d376d
FR		 345 unsigned rx_head ____cacheline_aligned;
346 unsigned rx_tail;
1da177e4 347 struct cp_desc *rx_ring;
0ba894d4 348 struct sk_buff *rx_skb[CP_RX_RING_SIZE];
1da177e4
LT		 349
350 unsigned tx_head ____cacheline_aligned;
351 unsigned tx_tail;
1da177e4 352 struct cp_desc *tx_ring;
48907e39 353 struct sk_buff *tx_skb[CP_TX_RING_SIZE];
d03d376d
FR		 354
355 unsigned rx_buf_sz;
356 unsigned wol_enabled : 1; /* Is Wake-on-LAN enabled? */
1da177e4
LT		 357
358#if CP_VLAN_TAG_USED
359 struct vlan_group *vlgrp;
360#endif
d03d376d 361 dma_addr_t ring_dma;
1da177e4
LT		 362
363 struct mii_if_info mii_if;
364};
365
366#define cpr8(reg) readb(cp->regs + (reg))
367#define cpr16(reg) readw(cp->regs + (reg))
368#define cpr32(reg) readl(cp->regs + (reg))
369#define cpw8(reg,val) writeb((val), cp->regs + (reg))
370#define cpw16(reg,val) writew((val), cp->regs + (reg))
371#define cpw32(reg,val) writel((val), cp->regs + (reg))
372#define cpw8_f(reg,val) do { \
373 writeb((val), cp->regs + (reg)); \
374 readb(cp->regs + (reg)); \
375 } while (0)
376#define cpw16_f(reg,val) do { \
377 writew((val), cp->regs + (reg)); \
378 readw(cp->regs + (reg)); \
379 } while (0)
380#define cpw32_f(reg,val) do { \
381 writel((val), cp->regs + (reg)); \
382 readl(cp->regs + (reg)); \
383 } while (0)
384
385
386static void __cp_set_rx_mode (struct net_device *dev);
387static void cp_tx (struct cp_private *cp);
388static void cp_clean_rings (struct cp_private *cp);
7502cd10
SK		 389#ifdef CONFIG_NET_POLL_CONTROLLER
390static void cp_poll_controller(struct net_device *dev);
391#endif
722fdb33
PC		 392static int cp_get_eeprom_len(struct net_device *dev);
393static int cp_get_eeprom(struct net_device *dev,
394 struct ethtool_eeprom *eeprom, u8 *data);
395static int cp_set_eeprom(struct net_device *dev,
396 struct ethtool_eeprom *eeprom, u8 *data);
1da177e4
LT		 397
398static struct pci_device_id cp_pci_tbl[] = {
cccb20d3
FR		 399 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, PCI_DEVICE_ID_REALTEK_8139), },
400 { PCI_DEVICE(PCI_VENDOR_ID_TTTECH, PCI_DEVICE_ID_TTTECH_MC322), },
1da177e4
LT		 401 { },
402};
403MODULE_DEVICE_TABLE(pci, cp_pci_tbl);
404
405static struct {
406 const char str[ETH_GSTRING_LEN];
407} ethtool_stats_keys[] = {
408 { "tx_ok" },
409 { "rx_ok" },
410 { "tx_err" },
411 { "rx_err" },
412 { "rx_fifo" },
413 { "frame_align" },
414 { "tx_ok_1col" },
415 { "tx_ok_mcol" },
416 { "rx_ok_phys" },
417 { "rx_ok_bcast" },
418 { "rx_ok_mcast" },
419 { "tx_abort" },
420 { "tx_underrun" },
421 { "rx_frags" },
422};
423
424
425#if CP_VLAN_TAG_USED
426static void cp_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
427{
428 struct cp_private *cp = netdev_priv(dev);
429 unsigned long flags;
430
431 spin_lock_irqsave(&cp->lock, flags);
432 cp->vlgrp = grp;
7b332244
SH		 433 if (grp)
434 cp->cpcmd |= RxVlanOn;
435 else
436 cp->cpcmd &= ~RxVlanOn;
1da177e4 437
1da177e4 438 cpw16(CpCmd, cp->cpcmd);
1da177e4
LT		 439 spin_unlock_irqrestore(&cp->lock, flags);
440}
441#endif /* CP_VLAN_TAG_USED */
442
443static inline void cp_set_rxbufsize (struct cp_private *cp)
444{
445 unsigned int mtu = cp->dev->mtu;
f3b197ac 446
1da177e4
LT		 447 if (mtu > ETH_DATA_LEN)
448 /* MTU + ethernet header + FCS + optional VLAN tag */
449 cp->rx_buf_sz = mtu + ETH_HLEN + 8;
450 else
451 cp->rx_buf_sz = PKT_BUF_SZ;
452}
453
454static inline void cp_rx_skb (struct cp_private *cp, struct sk_buff *skb,
455 struct cp_desc *desc)
456{
457 skb->protocol = eth_type_trans (skb, cp->dev);
458
237225f7
PZ		 459 cp->dev->stats.rx_packets++;
460 cp->dev->stats.rx_bytes += skb->len;
1da177e4
LT		 461 cp->dev->last_rx = jiffies;
462
463#if CP_VLAN_TAG_USED
cf983019 464 if (cp->vlgrp && (desc->opts2 & cpu_to_le32(RxVlanTagged))) {
1da177e4 465 vlan_hwaccel_receive_skb(skb, cp->vlgrp,
cf983019 466 swab16(le32_to_cpu(desc->opts2) & 0xffff));
1da177e4
LT		 467 } else
468#endif
469 netif_receive_skb(skb);
470}
471
472static void cp_rx_err_acct (struct cp_private *cp, unsigned rx_tail,
473 u32 status, u32 len)
474{
475 if (netif_msg_rx_err (cp))
476 printk (KERN_DEBUG
477 "%s: rx err, slot %d status 0x%x len %d\n",
478 cp->dev->name, rx_tail, status, len);
237225f7 479 cp->dev->stats.rx_errors++;
1da177e4 480 if (status & RxErrFrame)
237225f7 481 cp->dev->stats.rx_frame_errors++;
1da177e4 482 if (status & RxErrCRC)
237225f7 483 cp->dev->stats.rx_crc_errors++;
1da177e4 484 if ((status & RxErrRunt) || (status & RxErrLong))
237225f7 485 cp->dev->stats.rx_length_errors++;
1da177e4 486 if ((status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag))
237225f7 487 cp->dev->stats.rx_length_errors++;
1da177e4 488 if (status & RxErrFIFO)
237225f7 489 cp->dev->stats.rx_fifo_errors++;
1da177e4
LT		 490}
491
492static inline unsigned int cp_rx_csum_ok (u32 status)
493{
494 unsigned int protocol = (status >> 16) & 0x3;
f3b197ac 495
1da177e4
LT		 496 if (likely((protocol == RxProtoTCP) && (!(status & TCPFail))))
497 return 1;
498 else if ((protocol == RxProtoUDP) && (!(status & UDPFail)))
499 return 1;
500 else if ((protocol == RxProtoIP) && (!(status & IPFail)))
501 return 1;
502 return 0;
503}
504
bea3348e 505static int cp_rx_poll(struct napi_struct *napi, int budget)
1da177e4 506{
bea3348e
SH		 507 struct cp_private *cp = container_of(napi, struct cp_private, napi);
508 struct net_device *dev = cp->dev;
509 unsigned int rx_tail = cp->rx_tail;
510 int rx;
1da177e4
LT		 511
512rx_status_loop:
513 rx = 0;
514 cpw16(IntrStatus, cp_rx_intr_mask);
515
516 while (1) {
517 u32 status, len;
518 dma_addr_t mapping;
519 struct sk_buff *skb, *new_skb;
520 struct cp_desc *desc;
521 unsigned buflen;
522
0ba894d4 523 skb = cp->rx_skb[rx_tail];
5d9428de 524 BUG_ON(!skb);
1da177e4
LT		 525
526 desc = &cp->rx_ring[rx_tail];
527 status = le32_to_cpu(desc->opts1);
528 if (status & DescOwn)
529 break;
530
531 len = (status & 0x1fff) - 4;
3598b57b 532 mapping = le64_to_cpu(desc->addr);
1da177e4
LT		 533
534 if ((status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag)) {
535 /* we don't support incoming fragmented frames.
536 * instead, we attempt to ensure that the
537 * pre-allocated RX skbs are properly sized such
538 * that RX fragments are never encountered
539 */
540 cp_rx_err_acct(cp, rx_tail, status, len);
237225f7 541 dev->stats.rx_dropped++;
1da177e4
LT		 542 cp->cp_stats.rx_frags++;
543 goto rx_next;
544 }
545
546 if (status & (RxError | RxErrFIFO)) {
547 cp_rx_err_acct(cp, rx_tail, status, len);
548 goto rx_next;
549 }
550
551 if (netif_msg_rx_status(cp))
552 printk(KERN_DEBUG "%s: rx slot %d status 0x%x len %d\n",
c48e9399 553 dev->name, rx_tail, status, len);
1da177e4
LT		 554
555 buflen = cp->rx_buf_sz + RX_OFFSET;
556 new_skb = dev_alloc_skb (buflen);
557 if (!new_skb) {
237225f7 558 dev->stats.rx_dropped++;
1da177e4
LT		 559 goto rx_next;
560 }
561
562 skb_reserve(new_skb, RX_OFFSET);
1da177e4 563
6cc92cdd 564 dma_unmap_single(&cp->pdev->dev, mapping,
1da177e4
LT		 565 buflen, PCI_DMA_FROMDEVICE);
566
567 /* Handle checksum offloading for incoming packets. */
568 if (cp_rx_csum_ok(status))
569 skb->ip_summed = CHECKSUM_UNNECESSARY;
570 else
571 skb->ip_summed = CHECKSUM_NONE;
572
573 skb_put(skb, len);
574
6cc92cdd 575 mapping = dma_map_single(&cp->pdev->dev, new_skb->data, buflen,
3598b57b 576 PCI_DMA_FROMDEVICE);
0ba894d4 577 cp->rx_skb[rx_tail] = new_skb;
1da177e4
LT		 578
579 cp_rx_skb(cp, skb, desc);
580 rx++;
581
582rx_next:
583 cp->rx_ring[rx_tail].opts2 = 0;
584 cp->rx_ring[rx_tail].addr = cpu_to_le64(mapping);
585 if (rx_tail == (CP_RX_RING_SIZE - 1))
586 desc->opts1 = cpu_to_le32(DescOwn | RingEnd |
587 cp->rx_buf_sz);
588 else
589 desc->opts1 = cpu_to_le32(DescOwn | cp->rx_buf_sz);
590 rx_tail = NEXT_RX(rx_tail);
591
bea3348e 592 if (rx >= budget)
1da177e4
LT		 593 break;
594 }
595
596 cp->rx_tail = rx_tail;
597
1da177e4
LT		 598 /* if we did not reach work limit, then we're done with
599 * this round of polling
600 */
bea3348e 601 if (rx < budget) {
d15e9c4d
FR		 602 unsigned long flags;
603
1da177e4
LT		 604 if (cpr16(IntrStatus) & cp_rx_intr_mask)
605 goto rx_status_loop;
606
bea3348e 607 spin_lock_irqsave(&cp->lock, flags);
1da177e4 608 cpw16_f(IntrMask, cp_intr_mask);
bea3348e
SH		 609 __netif_rx_complete(dev, napi);
610 spin_unlock_irqrestore(&cp->lock, flags);
1da177e4
LT		 611 }
612
bea3348e 613 return rx;
1da177e4
LT		 614}
615
7d12e780 616static irqreturn_t cp_interrupt (int irq, void *dev_instance)
1da177e4
LT		 617{
618 struct net_device *dev = dev_instance;
619 struct cp_private *cp;
620 u16 status;
621
622 if (unlikely(dev == NULL))
623 return IRQ_NONE;
624 cp = netdev_priv(dev);
625
626 status = cpr16(IntrStatus);
627 if (!status || (status == 0xFFFF))
628 return IRQ_NONE;
629
630 if (netif_msg_intr(cp))
631 printk(KERN_DEBUG "%s: intr, status %04x cmd %02x cpcmd %04x\n",
632 dev->name, status, cpr8(Cmd), cpr16(CpCmd));
633
634 cpw16(IntrStatus, status & ~cp_rx_intr_mask);
635
636 spin_lock(&cp->lock);
637
638 /* close possible race's with dev_close */
639 if (unlikely(!netif_running(dev))) {
640 cpw16(IntrMask, 0);
641 spin_unlock(&cp->lock);
642 return IRQ_HANDLED;
643 }
644
645 if (status & (RxOK | RxErr | RxEmpty | RxFIFOOvr))
bea3348e 646 if (netif_rx_schedule_prep(dev, &cp->napi)) {
1da177e4 647 cpw16_f(IntrMask, cp_norx_intr_mask);
bea3348e 648 __netif_rx_schedule(dev, &cp->napi);
1da177e4
LT		 649 }
650
651 if (status & (TxOK | TxErr | TxEmpty | SWInt))
652 cp_tx(cp);
653 if (status & LinkChg)
2501f843 654 mii_check_media(&cp->mii_if, netif_msg_link(cp), false);
1da177e4
LT		 655
656 spin_unlock(&cp->lock);
657
658 if (status & PciErr) {
659 u16 pci_status;
660
661 pci_read_config_word(cp->pdev, PCI_STATUS, &pci_status);
662 pci_write_config_word(cp->pdev, PCI_STATUS, pci_status);
663 printk(KERN_ERR "%s: PCI bus error, status=%04x, PCI status=%04x\n",
664 dev->name, status, pci_status);
665
666 /* TODO: reset hardware */
667 }
668
669 return IRQ_HANDLED;
670}
671
7502cd10
SK		 672#ifdef CONFIG_NET_POLL_CONTROLLER
673/*
674 * Polling receive - used by netconsole and other diagnostic tools
675 * to allow network i/o with interrupts disabled.
676 */
677static void cp_poll_controller(struct net_device *dev)
678{
679 disable_irq(dev->irq);
7d12e780 680 cp_interrupt(dev->irq, dev);
7502cd10
SK		 681 enable_irq(dev->irq);
682}
683#endif
684
1da177e4
LT		 685static void cp_tx (struct cp_private *cp)
686{
687 unsigned tx_head = cp->tx_head;
688 unsigned tx_tail = cp->tx_tail;
689
690 while (tx_tail != tx_head) {
3598b57b 691 struct cp_desc *txd = cp->tx_ring + tx_tail;
1da177e4
LT		 692 struct sk_buff *skb;
693 u32 status;
694
695 rmb();
3598b57b 696 status = le32_to_cpu(txd->opts1);
1da177e4
LT		 697 if (status & DescOwn)
698 break;
699
48907e39 700 skb = cp->tx_skb[tx_tail];
5d9428de 701 BUG_ON(!skb);
1da177e4 702
6cc92cdd 703 dma_unmap_single(&cp->pdev->dev, le64_to_cpu(txd->addr),
48907e39
FR		 704 le32_to_cpu(txd->opts1) & 0xffff,
705 PCI_DMA_TODEVICE);
1da177e4
LT		 706
707 if (status & LastFrag) {
708 if (status & (TxError | TxFIFOUnder)) {
709 if (netif_msg_tx_err(cp))
710 printk(KERN_DEBUG "%s: tx err, status 0x%x\n",
711 cp->dev->name, status);
237225f7 712 cp->dev->stats.tx_errors++;
1da177e4 713 if (status & TxOWC)
237225f7 714 cp->dev->stats.tx_window_errors++;
1da177e4 715 if (status & TxMaxCol)
237225f7 716 cp->dev->stats.tx_aborted_errors++;
1da177e4 717 if (status & TxLinkFail)
237225f7 718 cp->dev->stats.tx_carrier_errors++;
1da177e4 719 if (status & TxFIFOUnder)
237225f7 720 cp->dev->stats.tx_fifo_errors++;
1da177e4 721 } else {
237225f7 722 cp->dev->stats.collisions +=
1da177e4 723 ((status >> TxColCntShift) & TxColCntMask);
237225f7
PZ		 724 cp->dev->stats.tx_packets++;
725 cp->dev->stats.tx_bytes += skb->len;
1da177e4
LT		 726 if (netif_msg_tx_done(cp))
727 printk(KERN_DEBUG "%s: tx done, slot %d\n", cp->dev->name, tx_tail);
728 }
729 dev_kfree_skb_irq(skb);
730 }
731
48907e39 732 cp->tx_skb[tx_tail] = NULL;
1da177e4
LT		 733
734 tx_tail = NEXT_TX(tx_tail);
735 }
736
737 cp->tx_tail = tx_tail;
738
739 if (TX_BUFFS_AVAIL(cp) > (MAX_SKB_FRAGS + 1))
740 netif_wake_queue(cp->dev);
741}
742
743static int cp_start_xmit (struct sk_buff *skb, struct net_device *dev)
744{
745 struct cp_private *cp = netdev_priv(dev);
746 unsigned entry;
fcec3456 747 u32 eor, flags;
553af567 748 unsigned long intr_flags;
1da177e4
LT		 749#if CP_VLAN_TAG_USED
750 u32 vlan_tag = 0;
751#endif
fcec3456 752 int mss = 0;
1da177e4 753
553af567 754 spin_lock_irqsave(&cp->lock, intr_flags);
1da177e4
LT		 755
756 /* This is a hard error, log it. */
757 if (TX_BUFFS_AVAIL(cp) <= (skb_shinfo(skb)->nr_frags + 1)) {
758 netif_stop_queue(dev);
553af567 759 spin_unlock_irqrestore(&cp->lock, intr_flags);
1da177e4
LT		 760 printk(KERN_ERR PFX "%s: BUG! Tx Ring full when queue awake!\n",
761 dev->name);
762 return 1;
763 }
764
765#if CP_VLAN_TAG_USED
766 if (cp->vlgrp && vlan_tx_tag_present(skb))
cf983019 767 vlan_tag = TxVlanTag | swab16(vlan_tx_tag_get(skb));
1da177e4
LT		 768#endif
769
770 entry = cp->tx_head;
771 eor = (entry == (CP_TX_RING_SIZE - 1)) ? RingEnd : 0;
fcec3456 772 if (dev->features & NETIF_F_TSO)
7967168c 773 mss = skb_shinfo(skb)->gso_size;
fcec3456 774
1da177e4
LT		 775 if (skb_shinfo(skb)->nr_frags == 0) {
776 struct cp_desc *txd = &cp->tx_ring[entry];
777 u32 len;
778 dma_addr_t mapping;
779
780 len = skb->len;
6cc92cdd 781 mapping = dma_map_single(&cp->pdev->dev, skb->data, len, PCI_DMA_TODEVICE);
1da177e4
LT		 782 CP_VLAN_TX_TAG(txd, vlan_tag);
783 txd->addr = cpu_to_le64(mapping);
784 wmb();
785
fcec3456
JG		 786 flags = eor | len | DescOwn | FirstFrag | LastFrag;
787
788 if (mss)
789 flags |= LargeSend | ((mss & MSSMask) << MSSShift);
84fa7933 790 else if (skb->ip_summed == CHECKSUM_PARTIAL) {
eddc9ec5 791 const struct iphdr *ip = ip_hdr(skb);
1da177e4 792 if (ip->protocol == IPPROTO_TCP)
fcec3456 793 flags |= IPCS | TCPCS;
1da177e4 794 else if (ip->protocol == IPPROTO_UDP)
fcec3456 795 flags |= IPCS | UDPCS;
1da177e4 796 else
5734418d 797 WARN_ON(1); /* we need a WARN() */
fcec3456
JG		 798 }
799
800 txd->opts1 = cpu_to_le32(flags);
1da177e4
LT		 801 wmb();
802
48907e39 803 cp->tx_skb[entry] = skb;
1da177e4
LT		 804 entry = NEXT_TX(entry);
805 } else {
806 struct cp_desc *txd;
807 u32 first_len, first_eor;
808 dma_addr_t first_mapping;
809 int frag, first_entry = entry;
eddc9ec5 810 const struct iphdr *ip = ip_hdr(skb);
1da177e4
LT		 811
812 /* We must give this initial chunk to the device last.
813 * Otherwise we could race with the device.
814 */
815 first_eor = eor;
816 first_len = skb_headlen(skb);
6cc92cdd 817 first_mapping = dma_map_single(&cp->pdev->dev, skb->data,
1da177e4 818 first_len, PCI_DMA_TODEVICE);
48907e39 819 cp->tx_skb[entry] = skb;
1da177e4
LT		 820 entry = NEXT_TX(entry);
821
822 for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) {
823 skb_frag_t *this_frag = &skb_shinfo(skb)->frags[frag];
824 u32 len;
825 u32 ctrl;
826 dma_addr_t mapping;
827
828 len = this_frag->size;
6cc92cdd 829 mapping = dma_map_single(&cp->pdev->dev,
1da177e4
LT		 830 ((void *) page_address(this_frag->page) +
831 this_frag->page_offset),
832 len, PCI_DMA_TODEVICE);
833 eor = (entry == (CP_TX_RING_SIZE - 1)) ? RingEnd : 0;
834
fcec3456
JG		 835 ctrl = eor | len | DescOwn;
836
837 if (mss)
838 ctrl |= LargeSend |
839 ((mss & MSSMask) << MSSShift);
84fa7933 840 else if (skb->ip_summed == CHECKSUM_PARTIAL) {
1da177e4 841 if (ip->protocol == IPPROTO_TCP)
fcec3456 842 ctrl |= IPCS | TCPCS;
1da177e4 843 else if (ip->protocol == IPPROTO_UDP)
fcec3456 844 ctrl |= IPCS | UDPCS;
1da177e4
LT		 845 else
846 BUG();
fcec3456 847 }
1da177e4
LT		 848
849 if (frag == skb_shinfo(skb)->nr_frags - 1)
850 ctrl |= LastFrag;
851
852 txd = &cp->tx_ring[entry];
853 CP_VLAN_TX_TAG(txd, vlan_tag);
854 txd->addr = cpu_to_le64(mapping);
855 wmb();
856
857 txd->opts1 = cpu_to_le32(ctrl);
858 wmb();
859
48907e39 860 cp->tx_skb[entry] = skb;
1da177e4
LT		 861 entry = NEXT_TX(entry);
862 }
863
864 txd = &cp->tx_ring[first_entry];
865 CP_VLAN_TX_TAG(txd, vlan_tag);
866 txd->addr = cpu_to_le64(first_mapping);
867 wmb();
868
84fa7933 869 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1da177e4
LT		 870 if (ip->protocol == IPPROTO_TCP)
871 txd->opts1 = cpu_to_le32(first_eor | first_len |
872 FirstFrag | DescOwn |
873 IPCS | TCPCS);
874 else if (ip->protocol == IPPROTO_UDP)
875 txd->opts1 = cpu_to_le32(first_eor | first_len |
876 FirstFrag | DescOwn |
877 IPCS | UDPCS);
878 else
879 BUG();
880 } else
881 txd->opts1 = cpu_to_le32(first_eor | first_len |
882 FirstFrag | DescOwn);
883 wmb();
884 }
885 cp->tx_head = entry;
886 if (netif_msg_tx_queued(cp))
887 printk(KERN_DEBUG "%s: tx queued, slot %d, skblen %d\n",
888 dev->name, entry, skb->len);
889 if (TX_BUFFS_AVAIL(cp) <= (MAX_SKB_FRAGS + 1))
890 netif_stop_queue(dev);
891
553af567 892 spin_unlock_irqrestore(&cp->lock, intr_flags);
1da177e4
LT		 893
894 cpw8(TxPoll, NormalTxPoll);
895 dev->trans_start = jiffies;
896
897 return 0;
898}
899
900/* Set or clear the multicast filter for this adaptor.
901 This routine is not state sensitive and need not be SMP locked. */
902
903static void __cp_set_rx_mode (struct net_device *dev)
904{
905 struct cp_private *cp = netdev_priv(dev);
906 u32 mc_filter[2]; /* Multicast hash filter */
907 int i, rx_mode;
908 u32 tmp;
909
910 /* Note: do not reorder, GCC is clever about common statements. */
911 if (dev->flags & IFF_PROMISC) {
912 /* Unconditionally log net taps. */
1da177e4
LT		 913 rx_mode =
914 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
915 AcceptAllPhys;
916 mc_filter[1] = mc_filter[0] = 0xffffffff;
917 } else if ((dev->mc_count > multicast_filter_limit)
918 || (dev->flags & IFF_ALLMULTI)) {
919 /* Too many to filter perfectly -- accept all multicasts. */
920 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
921 mc_filter[1] = mc_filter[0] = 0xffffffff;
922 } else {
923 struct dev_mc_list *mclist;
924 rx_mode = AcceptBroadcast | AcceptMyPhys;
925 mc_filter[1] = mc_filter[0] = 0;
926 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
927 i++, mclist = mclist->next) {
928 int bit_nr = ether_crc(ETH_ALEN, mclist->dmi_addr) >> 26;
929
930 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
931 rx_mode |= AcceptMulticast;
932 }
933 }
934
935 /* We can safely update without stopping the chip. */
936 tmp = cp_rx_config | rx_mode;
937 if (cp->rx_config != tmp) {
938 cpw32_f (RxConfig, tmp);
939 cp->rx_config = tmp;
940 }
941 cpw32_f (MAR0 + 0, mc_filter[0]);
942 cpw32_f (MAR0 + 4, mc_filter[1]);
943}
944
945static void cp_set_rx_mode (struct net_device *dev)
946{
947 unsigned long flags;
948 struct cp_private *cp = netdev_priv(dev);
949
950 spin_lock_irqsave (&cp->lock, flags);
951 __cp_set_rx_mode(dev);
952 spin_unlock_irqrestore (&cp->lock, flags);
953}
954
955static void __cp_get_stats(struct cp_private *cp)
956{
957 /* only lower 24 bits valid; write any value to clear */
237225f7 958 cp->dev->stats.rx_missed_errors += (cpr32 (RxMissed) & 0xffffff);
1da177e4
LT		 959 cpw32 (RxMissed, 0);
960}
961
962static struct net_device_stats *cp_get_stats(struct net_device *dev)
963{
964 struct cp_private *cp = netdev_priv(dev);
965 unsigned long flags;
966
967 /* The chip only need report frame silently dropped. */
968 spin_lock_irqsave(&cp->lock, flags);
969 if (netif_running(dev) && netif_device_present(dev))
970 __cp_get_stats(cp);
971 spin_unlock_irqrestore(&cp->lock, flags);
972
237225f7 973 return &dev->stats;
1da177e4
LT		 974}
975
976static void cp_stop_hw (struct cp_private *cp)
977{
978 cpw16(IntrStatus, ~(cpr16(IntrStatus)));
979 cpw16_f(IntrMask, 0);
980 cpw8(Cmd, 0);
981 cpw16_f(CpCmd, 0);
982 cpw16_f(IntrStatus, ~(cpr16(IntrStatus)));
983
984 cp->rx_tail = 0;
985 cp->tx_head = cp->tx_tail = 0;
986}
987
988static void cp_reset_hw (struct cp_private *cp)
989{
990 unsigned work = 1000;
991
992 cpw8(Cmd, CmdReset);
993
994 while (work--) {
995 if (!(cpr8(Cmd) & CmdReset))
996 return;
997
3173c890 998 schedule_timeout_uninterruptible(10);
1da177e4
LT		 999 }
1000
1001 printk(KERN_ERR "%s: hardware reset timeout\n", cp->dev->name);
1002}
1003
1004static inline void cp_start_hw (struct cp_private *cp)
1005{
1006 cpw16(CpCmd, cp->cpcmd);
1007 cpw8(Cmd, RxOn | TxOn);
1008}
1009
1010static void cp_init_hw (struct cp_private *cp)
1011{
1012 struct net_device *dev = cp->dev;
1013 dma_addr_t ring_dma;
1014
1015 cp_reset_hw(cp);
1016
1017 cpw8_f (Cfg9346, Cfg9346_Unlock);
1018
1019 /* Restore our idea of the MAC address. */
03233b90
AV		 1020 cpw32_f (MAC0 + 0, le32_to_cpu (*(__le32 *) (dev->dev_addr + 0)));
1021 cpw32_f (MAC0 + 4, le32_to_cpu (*(__le32 *) (dev->dev_addr + 4)));
1da177e4
LT		 1022
1023 cp_start_hw(cp);
1024 cpw8(TxThresh, 0x06); /* XXX convert magic num to a constant */
1025
1026 __cp_set_rx_mode(dev);
1027 cpw32_f (TxConfig, IFG | (TX_DMA_BURST << TxDMAShift));
1028
1029 cpw8(Config1, cpr8(Config1) | DriverLoaded | PMEnable);
1030 /* Disable Wake-on-LAN. Can be turned on with ETHTOOL_SWOL */
1031 cpw8(Config3, PARMEnable);
1032 cp->wol_enabled = 0;
1033
f3b197ac 1034 cpw8(Config5, cpr8(Config5) & PMEStatus);
1da177e4
LT		 1035
1036 cpw32_f(HiTxRingAddr, 0);
1037 cpw32_f(HiTxRingAddr + 4, 0);
1038
1039 ring_dma = cp->ring_dma;
1040 cpw32_f(RxRingAddr, ring_dma & 0xffffffff);
1041 cpw32_f(RxRingAddr + 4, (ring_dma >> 16) >> 16);
1042
1043 ring_dma += sizeof(struct cp_desc) * CP_RX_RING_SIZE;
1044 cpw32_f(TxRingAddr, ring_dma & 0xffffffff);
1045 cpw32_f(TxRingAddr + 4, (ring_dma >> 16) >> 16);
1046
1047 cpw16(MultiIntr, 0);
1048
1049 cpw16_f(IntrMask, cp_intr_mask);
1050
1051 cpw8_f(Cfg9346, Cfg9346_Lock);
1052}
1053
1054static int cp_refill_rx (struct cp_private *cp)
1055{
1056 unsigned i;
1057
1058 for (i = 0; i < CP_RX_RING_SIZE; i++) {
1059 struct sk_buff *skb;
3598b57b 1060 dma_addr_t mapping;
1da177e4
LT		 1061
1062 skb = dev_alloc_skb(cp->rx_buf_sz + RX_OFFSET);
1063 if (!skb)
1064 goto err_out;
1065
1da177e4
LT		 1066 skb_reserve(skb, RX_OFFSET);
1067
6cc92cdd
JG		 1068 mapping = dma_map_single(&cp->pdev->dev, skb->data,
1069 cp->rx_buf_sz, PCI_DMA_FROMDEVICE);
0ba894d4 1070 cp->rx_skb[i] = skb;
1da177e4
LT		 1071
1072 cp->rx_ring[i].opts2 = 0;
3598b57b 1073 cp->rx_ring[i].addr = cpu_to_le64(mapping);
1da177e4
LT		 1074 if (i == (CP_RX_RING_SIZE - 1))
1075 cp->rx_ring[i].opts1 =
1076 cpu_to_le32(DescOwn | RingEnd | cp->rx_buf_sz);
1077 else
1078 cp->rx_ring[i].opts1 =
1079 cpu_to_le32(DescOwn | cp->rx_buf_sz);
1080 }
1081
1082 return 0;
1083
1084err_out:
1085 cp_clean_rings(cp);
1086 return -ENOMEM;
1087}
1088
576cfa93
FR		 1089static void cp_init_rings_index (struct cp_private *cp)
1090{
1091 cp->rx_tail = 0;
1092 cp->tx_head = cp->tx_tail = 0;
1093}
1094
1da177e4
LT		 1095static int cp_init_rings (struct cp_private *cp)
1096{
1097 memset(cp->tx_ring, 0, sizeof(struct cp_desc) * CP_TX_RING_SIZE);
1098 cp->tx_ring[CP_TX_RING_SIZE - 1].opts1 = cpu_to_le32(RingEnd);
1099
576cfa93 1100 cp_init_rings_index(cp);
1da177e4
LT		 1101
1102 return cp_refill_rx (cp);
1103}
1104
1105static int cp_alloc_rings (struct cp_private *cp)
1106{
1107 void *mem;
1108
6cc92cdd
JG		 1109 mem = dma_alloc_coherent(&cp->pdev->dev, CP_RING_BYTES,
1110 &cp->ring_dma, GFP_KERNEL);
1da177e4
LT		 1111 if (!mem)
1112 return -ENOMEM;
1113
1114 cp->rx_ring = mem;
1115 cp->tx_ring = &cp->rx_ring[CP_RX_RING_SIZE];
1116
1da177e4
LT		 1117 return cp_init_rings(cp);
1118}
1119
1120static void cp_clean_rings (struct cp_private *cp)
1121{
3598b57b 1122 struct cp_desc *desc;
1da177e4
LT		 1123 unsigned i;
1124
1da177e4 1125 for (i = 0; i < CP_RX_RING_SIZE; i++) {
0ba894d4 1126 if (cp->rx_skb[i]) {
3598b57b 1127 desc = cp->rx_ring + i;
6cc92cdd 1128 dma_unmap_single(&cp->pdev->dev,le64_to_cpu(desc->addr),
1da177e4 1129 cp->rx_buf_sz, PCI_DMA_FROMDEVICE);
0ba894d4 1130 dev_kfree_skb(cp->rx_skb[i]);
1da177e4
LT		 1131 }
1132 }
1133
1134 for (i = 0; i < CP_TX_RING_SIZE; i++) {
48907e39
FR		 1135 if (cp->tx_skb[i]) {
1136 struct sk_buff *skb = cp->tx_skb[i];
5734418d 1137
3598b57b 1138 desc = cp->tx_ring + i;
6cc92cdd 1139 dma_unmap_single(&cp->pdev->dev,le64_to_cpu(desc->addr),
48907e39
FR		 1140 le32_to_cpu(desc->opts1) & 0xffff,
1141 PCI_DMA_TODEVICE);
3598b57b 1142 if (le32_to_cpu(desc->opts1) & LastFrag)
5734418d 1143 dev_kfree_skb(skb);
237225f7 1144 cp->dev->stats.tx_dropped++;
1da177e4
LT		 1145 }
1146 }
1147
5734418d
FR		 1148 memset(cp->rx_ring, 0, sizeof(struct cp_desc) * CP_RX_RING_SIZE);
1149 memset(cp->tx_ring, 0, sizeof(struct cp_desc) * CP_TX_RING_SIZE);
1150
0ba894d4 1151 memset(cp->rx_skb, 0, sizeof(struct sk_buff *) * CP_RX_RING_SIZE);
48907e39 1152 memset(cp->tx_skb, 0, sizeof(struct sk_buff *) * CP_TX_RING_SIZE);
1da177e4
LT		 1153}
1154
1155static void cp_free_rings (struct cp_private *cp)
1156{
1157 cp_clean_rings(cp);
6cc92cdd
JG		 1158 dma_free_coherent(&cp->pdev->dev, CP_RING_BYTES, cp->rx_ring,
1159 cp->ring_dma);
1da177e4
LT		 1160 cp->rx_ring = NULL;
1161 cp->tx_ring = NULL;
1da177e4
LT		 1162}
1163
1164static int cp_open (struct net_device *dev)
1165{
1166 struct cp_private *cp = netdev_priv(dev);
1167 int rc;
1168
1169 if (netif_msg_ifup(cp))
1170 printk(KERN_DEBUG "%s: enabling interface\n", dev->name);
1171
1172 rc = cp_alloc_rings(cp);
1173 if (rc)
1174 return rc;
1175
bea3348e
SH		 1176 napi_enable(&cp->napi);
1177
1da177e4
LT		 1178 cp_init_hw(cp);
1179
1fb9df5d 1180 rc = request_irq(dev->irq, cp_interrupt, IRQF_SHARED, dev->name, dev);
1da177e4
LT		 1181 if (rc)
1182 goto err_out_hw;
1183
1184 netif_carrier_off(dev);
2501f843 1185 mii_check_media(&cp->mii_if, netif_msg_link(cp), true);
1da177e4
LT		 1186 netif_start_queue(dev);
1187
1188 return 0;
1189
1190err_out_hw:
bea3348e 1191 napi_disable(&cp->napi);
1da177e4
LT		 1192 cp_stop_hw(cp);
1193 cp_free_rings(cp);
1194 return rc;
1195}
1196
1197static int cp_close (struct net_device *dev)
1198{
1199 struct cp_private *cp = netdev_priv(dev);
1200 unsigned long flags;
1201
bea3348e
SH		 1202 napi_disable(&cp->napi);
1203
1da177e4
LT		 1204 if (netif_msg_ifdown(cp))
1205 printk(KERN_DEBUG "%s: disabling interface\n", dev->name);
1206
1207 spin_lock_irqsave(&cp->lock, flags);
1208
1209 netif_stop_queue(dev);
1210 netif_carrier_off(dev);
1211
1212 cp_stop_hw(cp);
1213
1214 spin_unlock_irqrestore(&cp->lock, flags);
1215
1da177e4
LT		 1216 free_irq(dev->irq, dev);
1217
1218 cp_free_rings(cp);
1219 return 0;
1220}
1221
9030c0d2
FR		 1222static void cp_tx_timeout(struct net_device *dev)
1223{
1224 struct cp_private *cp = netdev_priv(dev);
1225 unsigned long flags;
1226 int rc;
1227
1228 printk(KERN_WARNING "%s: Transmit timeout, status %2x %4x %4x %4x\n",
1229 dev->name, cpr8(Cmd), cpr16(CpCmd),
1230 cpr16(IntrStatus), cpr16(IntrMask));
1231
1232 spin_lock_irqsave(&cp->lock, flags);
1233
1234 cp_stop_hw(cp);
1235 cp_clean_rings(cp);
1236 rc = cp_init_rings(cp);
1237 cp_start_hw(cp);
1238
1239 netif_wake_queue(dev);
1240
1241 spin_unlock_irqrestore(&cp->lock, flags);
1242
1243 return;
1244}
1245
1da177e4
LT		 1246#ifdef BROKEN
1247static int cp_change_mtu(struct net_device *dev, int new_mtu)
1248{
1249 struct cp_private *cp = netdev_priv(dev);
1250 int rc;
1251 unsigned long flags;
1252
1253 /* check for invalid MTU, according to hardware limits */
1254 if (new_mtu < CP_MIN_MTU || new_mtu > CP_MAX_MTU)
1255 return -EINVAL;
1256
1257 /* if network interface not up, no need for complexity */
1258 if (!netif_running(dev)) {
1259 dev->mtu = new_mtu;
1260 cp_set_rxbufsize(cp); /* set new rx buf size */
1261 return 0;
1262 }
1263
1264 spin_lock_irqsave(&cp->lock, flags);
1265
1266 cp_stop_hw(cp); /* stop h/w and free rings */
1267 cp_clean_rings(cp);
1268
1269 dev->mtu = new_mtu;
1270 cp_set_rxbufsize(cp); /* set new rx buf size */
1271
1272 rc = cp_init_rings(cp); /* realloc and restart h/w */
1273 cp_start_hw(cp);
1274
1275 spin_unlock_irqrestore(&cp->lock, flags);
1276
1277 return rc;
1278}
1279#endif /* BROKEN */
1280
f71e1309 1281static const char mii_2_8139_map[8] = {
1da177e4
LT		 1282 BasicModeCtrl,
1283 BasicModeStatus,
1284 0,
1285 0,
1286 NWayAdvert,
1287 NWayLPAR,
1288 NWayExpansion,
1289 0
1290};
1291
1292static int mdio_read(struct net_device *dev, int phy_id, int location)
1293{
1294 struct cp_private *cp = netdev_priv(dev);
1295
1296 return location < 8 && mii_2_8139_map[location] ?
1297 readw(cp->regs + mii_2_8139_map[location]) : 0;
1298}
1299
1300
1301static void mdio_write(struct net_device *dev, int phy_id, int location,
1302 int value)
1303{
1304 struct cp_private *cp = netdev_priv(dev);
1305
1306 if (location == 0) {
1307 cpw8(Cfg9346, Cfg9346_Unlock);
1308 cpw16(BasicModeCtrl, value);
1309 cpw8(Cfg9346, Cfg9346_Lock);
1310 } else if (location < 8 && mii_2_8139_map[location])
1311 cpw16(mii_2_8139_map[location], value);
1312}
1313
1314/* Set the ethtool Wake-on-LAN settings */
1315static int netdev_set_wol (struct cp_private *cp,
1316 const struct ethtool_wolinfo *wol)
1317{
1318 u8 options;
1319
1320 options = cpr8 (Config3) & ~(LinkUp | MagicPacket);
1321 /* If WOL is being disabled, no need for complexity */
1322 if (wol->wolopts) {
1323 if (wol->wolopts & WAKE_PHY) options |= LinkUp;
1324 if (wol->wolopts & WAKE_MAGIC) options |= MagicPacket;
1325 }
1326
1327 cpw8 (Cfg9346, Cfg9346_Unlock);
1328 cpw8 (Config3, options);
1329 cpw8 (Cfg9346, Cfg9346_Lock);
1330
1331 options = 0; /* Paranoia setting */
1332 options = cpr8 (Config5) & ~(UWF | MWF | BWF);
1333 /* If WOL is being disabled, no need for complexity */
1334 if (wol->wolopts) {
1335 if (wol->wolopts & WAKE_UCAST) options |= UWF;
1336 if (wol->wolopts & WAKE_BCAST) options |= BWF;
1337 if (wol->wolopts & WAKE_MCAST) options |= MWF;
1338 }
1339
1340 cpw8 (Config5, options);
1341
1342 cp->wol_enabled = (wol->wolopts) ? 1 : 0;
1343
1344 return 0;
1345}
1346
1347/* Get the ethtool Wake-on-LAN settings */
1348static void netdev_get_wol (struct cp_private *cp,
1349 struct ethtool_wolinfo *wol)
1350{
1351 u8 options;
1352
1353 wol->wolopts = 0; /* Start from scratch */
1354 wol->supported = WAKE_PHY | WAKE_BCAST | WAKE_MAGIC |
1355 WAKE_MCAST | WAKE_UCAST;
1356 /* We don't need to go on if WOL is disabled */
1357 if (!cp->wol_enabled) return;
f3b197ac 1358
1da177e4
LT		 1359 options = cpr8 (Config3);
1360 if (options & LinkUp) wol->wolopts |= WAKE_PHY;
1361 if (options & MagicPacket) wol->wolopts |= WAKE_MAGIC;
1362
1363 options = 0; /* Paranoia setting */
1364 options = cpr8 (Config5);
1365 if (options & UWF) wol->wolopts |= WAKE_UCAST;
1366 if (options & BWF) wol->wolopts |= WAKE_BCAST;
1367 if (options & MWF) wol->wolopts |= WAKE_MCAST;
1368}
1369
1370static void cp_get_drvinfo (struct net_device *dev, struct ethtool_drvinfo *info)
1371{
1372 struct cp_private *cp = netdev_priv(dev);
1373
1374 strcpy (info->driver, DRV_NAME);
1375 strcpy (info->version, DRV_VERSION);
1376 strcpy (info->bus_info, pci_name(cp->pdev));
1377}
1378
1379static int cp_get_regs_len(struct net_device *dev)
1380{
1381 return CP_REGS_SIZE;
1382}
1383
b9f2c044 1384static int cp_get_sset_count (struct net_device *dev, int sset)
1da177e4 1385{
b9f2c044
JG		 1386 switch (sset) {
1387 case ETH_SS_STATS:
1388 return CP_NUM_STATS;
1389 default:
1390 return -EOPNOTSUPP;
1391 }
1da177e4
LT		 1392}
1393
1394static int cp_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1395{
1396 struct cp_private *cp = netdev_priv(dev);
1397 int rc;
1398 unsigned long flags;
1399
1400 spin_lock_irqsave(&cp->lock, flags);
1401 rc = mii_ethtool_gset(&cp->mii_if, cmd);
1402 spin_unlock_irqrestore(&cp->lock, flags);
1403
1404 return rc;
1405}
1406
1407static int cp_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1408{
1409 struct cp_private *cp = netdev_priv(dev);
1410 int rc;
1411 unsigned long flags;
1412
1413 spin_lock_irqsave(&cp->lock, flags);
1414 rc = mii_ethtool_sset(&cp->mii_if, cmd);
1415 spin_unlock_irqrestore(&cp->lock, flags);
1416
1417 return rc;
1418}
1419
1420static int cp_nway_reset(struct net_device *dev)
1421{
1422 struct cp_private *cp = netdev_priv(dev);
1423 return mii_nway_restart(&cp->mii_if);
1424}
1425
1426static u32 cp_get_msglevel(struct net_device *dev)
1427{
1428 struct cp_private *cp = netdev_priv(dev);
1429 return cp->msg_enable;
1430}
1431
1432static void cp_set_msglevel(struct net_device *dev, u32 value)
1433{
1434 struct cp_private *cp = netdev_priv(dev);
1435 cp->msg_enable = value;
1436}
1437
1438static u32 cp_get_rx_csum(struct net_device *dev)
1439{
1440 struct cp_private *cp = netdev_priv(dev);
1441 return (cpr16(CpCmd) & RxChkSum) ? 1 : 0;
1442}
1443
1444static int cp_set_rx_csum(struct net_device *dev, u32 data)
1445{
1446 struct cp_private *cp = netdev_priv(dev);
1447 u16 cmd = cp->cpcmd, newcmd;
1448
1449 newcmd = cmd;
1450
1451 if (data)
1452 newcmd |= RxChkSum;
1453 else
1454 newcmd &= ~RxChkSum;
1455
1456 if (newcmd != cmd) {
1457 unsigned long flags;
1458
1459 spin_lock_irqsave(&cp->lock, flags);
1460 cp->cpcmd = newcmd;
1461 cpw16_f(CpCmd, newcmd);
1462 spin_unlock_irqrestore(&cp->lock, flags);
1463 }
1464
1465 return 0;
1466}
1467
1468static void cp_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1469 void *p)
1470{
1471 struct cp_private *cp = netdev_priv(dev);
1472 unsigned long flags;
1473
1474 if (regs->len < CP_REGS_SIZE)
1475 return /* -EINVAL */;
1476
1477 regs->version = CP_REGS_VER;
1478
1479 spin_lock_irqsave(&cp->lock, flags);
1480 memcpy_fromio(p, cp->regs, CP_REGS_SIZE);
1481 spin_unlock_irqrestore(&cp->lock, flags);
1482}
1483
1484static void cp_get_wol (struct net_device *dev, struct ethtool_wolinfo *wol)
1485{
1486 struct cp_private *cp = netdev_priv(dev);
1487 unsigned long flags;
1488
1489 spin_lock_irqsave (&cp->lock, flags);
1490 netdev_get_wol (cp, wol);
1491 spin_unlock_irqrestore (&cp->lock, flags);
1492}
1493
1494static int cp_set_wol (struct net_device *dev, struct ethtool_wolinfo *wol)
1495{
1496 struct cp_private *cp = netdev_priv(dev);
1497 unsigned long flags;
1498 int rc;
1499
1500 spin_lock_irqsave (&cp->lock, flags);
1501 rc = netdev_set_wol (cp, wol);
1502 spin_unlock_irqrestore (&cp->lock, flags);
1503
1504 return rc;
1505}
1506
1507static void cp_get_strings (struct net_device *dev, u32 stringset, u8 *buf)
1508{
1509 switch (stringset) {
1510 case ETH_SS_STATS:
1511 memcpy(buf, &ethtool_stats_keys, sizeof(ethtool_stats_keys));
1512 break;
1513 default:
1514 BUG();
1515 break;
1516 }
1517}
1518
1519static void cp_get_ethtool_stats (struct net_device *dev,
1520 struct ethtool_stats *estats, u64 *tmp_stats)
1521{
1522 struct cp_private *cp = netdev_priv(dev);
8b512927
SH		 1523 struct cp_dma_stats *nic_stats;
1524 dma_addr_t dma;
1da177e4
LT		 1525 int i;
1526
6cc92cdd
JG		 1527 nic_stats = dma_alloc_coherent(&cp->pdev->dev, sizeof(*nic_stats),
1528 &dma, GFP_KERNEL);
8b512927
SH		 1529 if (!nic_stats)
1530 return;
97f568d8 1531
1da177e4 1532 /* begin NIC statistics dump */
8b512927
SH		 1533 cpw32(StatsAddr + 4, (u64)dma >> 32);
1534 cpw32(StatsAddr, ((u64)dma & DMA_32BIT_MASK) | DumpStats);
1da177e4
LT		 1535 cpr32(StatsAddr);
1536
97f568d8 1537 for (i = 0; i < 1000; i++) {
1da177e4
LT		 1538 if ((cpr32(StatsAddr) & DumpStats) == 0)
1539 break;
97f568d8 1540 udelay(10);
1da177e4 1541 }
97f568d8
SH		 1542 cpw32(StatsAddr, 0);
1543 cpw32(StatsAddr + 4, 0);
8b512927 1544 cpr32(StatsAddr);
1da177e4
LT		 1545
1546 i = 0;
8b512927
SH		 1547 tmp_stats[i++] = le64_to_cpu(nic_stats->tx_ok);
1548 tmp_stats[i++] = le64_to_cpu(nic_stats->rx_ok);
1549 tmp_stats[i++] = le64_to_cpu(nic_stats->tx_err);
1550 tmp_stats[i++] = le32_to_cpu(nic_stats->rx_err);
1551 tmp_stats[i++] = le16_to_cpu(nic_stats->rx_fifo);
1552 tmp_stats[i++] = le16_to_cpu(nic_stats->frame_align);
1553 tmp_stats[i++] = le32_to_cpu(nic_stats->tx_ok_1col);
1554 tmp_stats[i++] = le32_to_cpu(nic_stats->tx_ok_mcol);
1555 tmp_stats[i++] = le64_to_cpu(nic_stats->rx_ok_phys);
1556 tmp_stats[i++] = le64_to_cpu(nic_stats->rx_ok_bcast);
1557 tmp_stats[i++] = le32_to_cpu(nic_stats->rx_ok_mcast);
1558 tmp_stats[i++] = le16_to_cpu(nic_stats->tx_abort);
1559 tmp_stats[i++] = le16_to_cpu(nic_stats->tx_underrun);
1da177e4 1560 tmp_stats[i++] = cp->cp_stats.rx_frags;
5d9428de 1561 BUG_ON(i != CP_NUM_STATS);
8b512927 1562
6cc92cdd 1563 dma_free_coherent(&cp->pdev->dev, sizeof(*nic_stats), nic_stats, dma);
1da177e4
LT		 1564}
1565
7282d491 1566static const struct ethtool_ops cp_ethtool_ops = {
1da177e4
LT		 1567 .get_drvinfo = cp_get_drvinfo,
1568 .get_regs_len = cp_get_regs_len,
b9f2c044 1569 .get_sset_count = cp_get_sset_count,
1da177e4
LT		 1570 .get_settings = cp_get_settings,
1571 .set_settings = cp_set_settings,
1572 .nway_reset = cp_nway_reset,
1573 .get_link = ethtool_op_get_link,
1574 .get_msglevel = cp_get_msglevel,
1575 .set_msglevel = cp_set_msglevel,
1576 .get_rx_csum = cp_get_rx_csum,
1577 .set_rx_csum = cp_set_rx_csum,
1da177e4 1578 .set_tx_csum = ethtool_op_set_tx_csum, /* local! */
1da177e4 1579 .set_sg = ethtool_op_set_sg,
fcec3456 1580 .set_tso = ethtool_op_set_tso,
1da177e4
LT		 1581 .get_regs = cp_get_regs,
1582 .get_wol = cp_get_wol,
1583 .set_wol = cp_set_wol,
1584 .get_strings = cp_get_strings,
1585 .get_ethtool_stats = cp_get_ethtool_stats,
722fdb33
PC		 1586 .get_eeprom_len = cp_get_eeprom_len,
1587 .get_eeprom = cp_get_eeprom,
1588 .set_eeprom = cp_set_eeprom,
1da177e4
LT		 1589};
1590
1591static int cp_ioctl (struct net_device *dev, struct ifreq *rq, int cmd)
1592{
1593 struct cp_private *cp = netdev_priv(dev);
1594 int rc;
1595 unsigned long flags;
1596
1597 if (!netif_running(dev))
1598 return -EINVAL;
1599
1600 spin_lock_irqsave(&cp->lock, flags);
1601 rc = generic_mii_ioctl(&cp->mii_if, if_mii(rq), cmd, NULL);
1602 spin_unlock_irqrestore(&cp->lock, flags);
1603 return rc;
1604}
1605
1606/* Serial EEPROM section. */
1607
1608/* EEPROM_Ctrl bits. */
1609#define EE_SHIFT_CLK 0x04 /* EEPROM shift clock. */
1610#define EE_CS 0x08 /* EEPROM chip select. */
1611#define EE_DATA_WRITE 0x02 /* EEPROM chip data in. */
1612#define EE_WRITE_0 0x00
1613#define EE_WRITE_1 0x02
1614#define EE_DATA_READ 0x01 /* EEPROM chip data out. */
1615#define EE_ENB (0x80 | EE_CS)
1616
1617/* Delay between EEPROM clock transitions.
1618 No extra delay is needed with 33Mhz PCI, but 66Mhz may change this.
1619 */
1620
1621#define eeprom_delay() readl(ee_addr)
1622
1623/* The EEPROM commands include the alway-set leading bit. */
722fdb33 1624#define EE_EXTEND_CMD (4)
1da177e4
LT		 1625#define EE_WRITE_CMD (5)
1626#define EE_READ_CMD (6)
1627#define EE_ERASE_CMD (7)
1628
722fdb33
PC		 1629#define EE_EWDS_ADDR (0)
1630#define EE_WRAL_ADDR (1)
1631#define EE_ERAL_ADDR (2)
1632#define EE_EWEN_ADDR (3)
1633
1634#define CP_EEPROM_MAGIC PCI_DEVICE_ID_REALTEK_8139
1da177e4 1635
722fdb33
PC		 1636static void eeprom_cmd_start(void __iomem *ee_addr)
1637{
1da177e4
LT		 1638 writeb (EE_ENB & ~EE_CS, ee_addr);
1639 writeb (EE_ENB, ee_addr);
1640 eeprom_delay ();
722fdb33 1641}
1da177e4 1642
722fdb33
PC		 1643static void eeprom_cmd(void __iomem *ee_addr, int cmd, int cmd_len)
1644{
1645 int i;
1646
1647 /* Shift the command bits out. */
1648 for (i = cmd_len - 1; i >= 0; i--) {
1649 int dataval = (cmd & (1 << i)) ? EE_DATA_WRITE : 0;
1da177e4
LT		 1650 writeb (EE_ENB | dataval, ee_addr);
1651 eeprom_delay ();
1652 writeb (EE_ENB | dataval | EE_SHIFT_CLK, ee_addr);
1653 eeprom_delay ();
1654 }
1655 writeb (EE_ENB, ee_addr);
1656 eeprom_delay ();
722fdb33
PC		 1657}
1658
1659static void eeprom_cmd_end(void __iomem *ee_addr)
1660{
1661 writeb (~EE_CS, ee_addr);
1662 eeprom_delay ();
1663}
1664
1665static void eeprom_extend_cmd(void __iomem *ee_addr, int extend_cmd,
1666 int addr_len)
1667{
1668 int cmd = (EE_EXTEND_CMD << addr_len) | (extend_cmd << (addr_len - 2));
1669
1670 eeprom_cmd_start(ee_addr);
1671 eeprom_cmd(ee_addr, cmd, 3 + addr_len);
1672 eeprom_cmd_end(ee_addr);
1673}
1674
1675static u16 read_eeprom (void __iomem *ioaddr, int location, int addr_len)
1676{
1677 int i;
1678 u16 retval = 0;
1679 void __iomem *ee_addr = ioaddr + Cfg9346;
1680 int read_cmd = location | (EE_READ_CMD << addr_len);
1681
1682 eeprom_cmd_start(ee_addr);
1683 eeprom_cmd(ee_addr, read_cmd, 3 + addr_len);
1da177e4
LT		 1684
1685 for (i = 16; i > 0; i--) {
1686 writeb (EE_ENB | EE_SHIFT_CLK, ee_addr);
1687 eeprom_delay ();
1688 retval =
1689 (retval << 1) | ((readb (ee_addr) & EE_DATA_READ) ? 1 :
1690 0);
1691 writeb (EE_ENB, ee_addr);
1692 eeprom_delay ();
1693 }
1694
722fdb33 1695 eeprom_cmd_end(ee_addr);
1da177e4
LT		 1696
1697 return retval;
1698}
1699
722fdb33
PC		 1700static void write_eeprom(void __iomem *ioaddr, int location, u16 val,
1701 int addr_len)
1702{
1703 int i;
1704 void __iomem *ee_addr = ioaddr + Cfg9346;
1705 int write_cmd = location | (EE_WRITE_CMD << addr_len);
1706
1707 eeprom_extend_cmd(ee_addr, EE_EWEN_ADDR, addr_len);
1708
1709 eeprom_cmd_start(ee_addr);
1710 eeprom_cmd(ee_addr, write_cmd, 3 + addr_len);
1711 eeprom_cmd(ee_addr, val, 16);
1712 eeprom_cmd_end(ee_addr);
1713
1714 eeprom_cmd_start(ee_addr);
1715 for (i = 0; i < 20000; i++)
1716 if (readb(ee_addr) & EE_DATA_READ)
1717 break;
1718 eeprom_cmd_end(ee_addr);
1719
1720 eeprom_extend_cmd(ee_addr, EE_EWDS_ADDR, addr_len);
1721}
1722
1723static int cp_get_eeprom_len(struct net_device *dev)
1724{
1725 struct cp_private *cp = netdev_priv(dev);
1726 int size;
1727
1728 spin_lock_irq(&cp->lock);
1729 size = read_eeprom(cp->regs, 0, 8) == 0x8129 ? 256 : 128;
1730 spin_unlock_irq(&cp->lock);
1731
1732 return size;
1733}
1734
1735static int cp_get_eeprom(struct net_device *dev,
1736 struct ethtool_eeprom *eeprom, u8 *data)
1737{
1738 struct cp_private *cp = netdev_priv(dev);
1739 unsigned int addr_len;
1740 u16 val;
1741 u32 offset = eeprom->offset >> 1;
1742 u32 len = eeprom->len;
1743 u32 i = 0;
1744
1745 eeprom->magic = CP_EEPROM_MAGIC;
1746
1747 spin_lock_irq(&cp->lock);
1748
1749 addr_len = read_eeprom(cp->regs, 0, 8) == 0x8129 ? 8 : 6;
1750
1751 if (eeprom->offset & 1) {
1752 val = read_eeprom(cp->regs, offset, addr_len);
1753 data[i++] = (u8)(val >> 8);
1754 offset++;
1755 }
1756
1757 while (i < len - 1) {
1758 val = read_eeprom(cp->regs, offset, addr_len);
1759 data[i++] = (u8)val;
1760 data[i++] = (u8)(val >> 8);
1761 offset++;
1762 }
1763
1764 if (i < len) {
1765 val = read_eeprom(cp->regs, offset, addr_len);
1766 data[i] = (u8)val;
1767 }
1768
1769 spin_unlock_irq(&cp->lock);
1770 return 0;
1771}
1772
1773static int cp_set_eeprom(struct net_device *dev,
1774 struct ethtool_eeprom *eeprom, u8 *data)
1775{
1776 struct cp_private *cp = netdev_priv(dev);
1777 unsigned int addr_len;
1778 u16 val;
1779 u32 offset = eeprom->offset >> 1;
1780 u32 len = eeprom->len;
1781 u32 i = 0;
1782
1783 if (eeprom->magic != CP_EEPROM_MAGIC)
1784 return -EINVAL;
1785
1786 spin_lock_irq(&cp->lock);
1787
1788 addr_len = read_eeprom(cp->regs, 0, 8) == 0x8129 ? 8 : 6;
1789
1790 if (eeprom->offset & 1) {
1791 val = read_eeprom(cp->regs, offset, addr_len) & 0xff;
1792 val |= (u16)data[i++] << 8;
1793 write_eeprom(cp->regs, offset, val, addr_len);
1794 offset++;
1795 }
1796
1797 while (i < len - 1) {
1798 val = (u16)data[i++];
1799 val |= (u16)data[i++] << 8;
1800 write_eeprom(cp->regs, offset, val, addr_len);
1801 offset++;
1802 }
1803
1804 if (i < len) {
1805 val = read_eeprom(cp->regs, offset, addr_len) & 0xff00;
1806 val |= (u16)data[i];
1807 write_eeprom(cp->regs, offset, val, addr_len);
1808 }
1809
1810 spin_unlock_irq(&cp->lock);
1811 return 0;
1812}
1813
1da177e4
LT		 1814/* Put the board into D3cold state and wait for WakeUp signal */
1815static void cp_set_d3_state (struct cp_private *cp)
1816{
1817 pci_enable_wake (cp->pdev, 0, 1); /* Enable PME# generation */
1818 pci_set_power_state (cp->pdev, PCI_D3hot);
1819}
1820
1821static int cp_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
1822{
1823 struct net_device *dev;
1824 struct cp_private *cp;
1825 int rc;
1826 void __iomem *regs;
2427ddd8 1827 resource_size_t pciaddr;
1da177e4 1828 unsigned int addr_len, i, pci_using_dac;
0795af57 1829 DECLARE_MAC_BUF(mac);
1da177e4
LT		 1830
1831#ifndef MODULE
1832 static int version_printed;
1833 if (version_printed++ == 0)
1834 printk("%s", version);
1835#endif
1836
1da177e4 1837 if (pdev->vendor == PCI_VENDOR_ID_REALTEK &&
44c10138 1838 pdev->device == PCI_DEVICE_ID_REALTEK_8139 && pdev->revision < 0x20) {
9b91cf9d 1839 dev_err(&pdev->dev,
2e8a538d 1840 "This (id %04x:%04x rev %02x) is not an 8139C+ compatible chip\n",
44c10138 1841 pdev->vendor, pdev->device, pdev->revision);
9b91cf9d 1842 dev_err(&pdev->dev, "Try the \"8139too\" driver instead.\n");
1da177e4
LT		 1843 return -ENODEV;
1844 }
1845
1846 dev = alloc_etherdev(sizeof(struct cp_private));
1847 if (!dev)
1848 return -ENOMEM;
1da177e4
LT		 1849 SET_NETDEV_DEV(dev, &pdev->dev);
1850
1851 cp = netdev_priv(dev);
1852 cp->pdev = pdev;
1853 cp->dev = dev;
1854 cp->msg_enable = (debug < 0 ? CP_DEF_MSG_ENABLE : debug);
1855 spin_lock_init (&cp->lock);
1856 cp->mii_if.dev = dev;
1857 cp->mii_if.mdio_read = mdio_read;
1858 cp->mii_if.mdio_write = mdio_write;
1859 cp->mii_if.phy_id = CP_INTERNAL_PHY;
1860 cp->mii_if.phy_id_mask = 0x1f;
1861 cp->mii_if.reg_num_mask = 0x1f;
1862 cp_set_rxbufsize(cp);
1863
1864 rc = pci_enable_device(pdev);
1865 if (rc)
1866 goto err_out_free;
1867
1868 rc = pci_set_mwi(pdev);
1869 if (rc)
1870 goto err_out_disable;
1871
1872 rc = pci_request_regions(pdev, DRV_NAME);
1873 if (rc)
1874 goto err_out_mwi;
1875
1876 pciaddr = pci_resource_start(pdev, 1);
1877 if (!pciaddr) {
1878 rc = -EIO;
9b91cf9d 1879 dev_err(&pdev->dev, "no MMIO resource\n");
1da177e4
LT		 1880 goto err_out_res;
1881 }
1882 if (pci_resource_len(pdev, 1) < CP_REGS_SIZE) {
1883 rc = -EIO;
9b91cf9d 1884 dev_err(&pdev->dev, "MMIO resource (%llx) too small\n",
2e8a538d 1885 (unsigned long long)pci_resource_len(pdev, 1));
1da177e4
LT		 1886 goto err_out_res;
1887 }
1888
1889 /* Configure DMA attributes. */
1890 if ((sizeof(dma_addr_t) > 4) &&
8662d061
TK		 1891 !pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK) &&
1892 !pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
1da177e4
LT		 1893 pci_using_dac = 1;
1894 } else {
1895 pci_using_dac = 0;
1896
8662d061 1897 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
1da177e4 1898 if (rc) {
9b91cf9d 1899 dev_err(&pdev->dev,
2e8a538d 1900 "No usable DMA configuration, aborting.\n");
1da177e4
LT		 1901 goto err_out_res;
1902 }
8662d061 1903 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
1da177e4 1904 if (rc) {
9b91cf9d 1905 dev_err(&pdev->dev,
2e8a538d
JG		 1906 "No usable consistent DMA configuration, "
1907 "aborting.\n");
1da177e4
LT		 1908 goto err_out_res;
1909 }
1910 }
1911
1912 cp->cpcmd = (pci_using_dac ? PCIDAC : 0) |
1913 PCIMulRW | RxChkSum | CpRxOn | CpTxOn;
1914
1915 regs = ioremap(pciaddr, CP_REGS_SIZE);
1916 if (!regs) {
1917 rc = -EIO;
4626dd46 1918 dev_err(&pdev->dev, "Cannot map PCI MMIO (%Lx@%Lx)\n",
2e8a538d
JG		 1919 (unsigned long long)pci_resource_len(pdev, 1),
1920 (unsigned long long)pciaddr);
1da177e4
LT		 1921 goto err_out_res;
1922 }
1923 dev->base_addr = (unsigned long) regs;
1924 cp->regs = regs;
1925
1926 cp_stop_hw(cp);
1927
1928 /* read MAC address from EEPROM */
1929 addr_len = read_eeprom (regs, 0, 8) == 0x8129 ? 8 : 6;
1930 for (i = 0; i < 3; i++)
03233b90
AV		 1931 ((__le16 *) (dev->dev_addr))[i] =
1932 cpu_to_le16(read_eeprom (regs, i + 7, addr_len));
bb0ce608 1933 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
1da177e4
LT		 1934
1935 dev->open = cp_open;
1936 dev->stop = cp_close;
1937 dev->set_multicast_list = cp_set_rx_mode;
1938 dev->hard_start_xmit = cp_start_xmit;
1939 dev->get_stats = cp_get_stats;
1940 dev->do_ioctl = cp_ioctl;
7502cd10
SK		 1941#ifdef CONFIG_NET_POLL_CONTROLLER
1942 dev->poll_controller = cp_poll_controller;
1943#endif
bea3348e 1944 netif_napi_add(dev, &cp->napi, cp_rx_poll, 16);
1da177e4
LT		 1945#ifdef BROKEN
1946 dev->change_mtu = cp_change_mtu;
1947#endif
1948 dev->ethtool_ops = &cp_ethtool_ops;
1da177e4
LT		 1949 dev->tx_timeout = cp_tx_timeout;
1950 dev->watchdog_timeo = TX_TIMEOUT;
1da177e4
LT		 1951
1952#if CP_VLAN_TAG_USED
1953 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
1954 dev->vlan_rx_register = cp_vlan_rx_register;
1da177e4
LT		 1955#endif
1956
1957 if (pci_using_dac)
1958 dev->features |= NETIF_F_HIGHDMA;
1959
fcec3456
JG		 1960#if 0 /* disabled by default until verified */
1961 dev->features |= NETIF_F_TSO;
1962#endif
1963
1da177e4
LT		 1964 dev->irq = pdev->irq;
1965
1966 rc = register_netdev(dev);
1967 if (rc)
1968 goto err_out_iomap;
1969
1970 printk (KERN_INFO "%s: RTL-8139C+ at 0x%lx, "
0795af57 1971 "%s, IRQ %d\n",
1da177e4
LT		 1972 dev->name,
1973 dev->base_addr,
0795af57 1974 print_mac(mac, dev->dev_addr),
1da177e4
LT		 1975 dev->irq);
1976
1977 pci_set_drvdata(pdev, dev);
1978
1979 /* enable busmastering and memory-write-invalidate */
1980 pci_set_master(pdev);
1981
2e8a538d
JG		 1982 if (cp->wol_enabled)
1983 cp_set_d3_state (cp);
1da177e4
LT		 1984
1985 return 0;
1986
1987err_out_iomap:
1988 iounmap(regs);
1989err_out_res:
1990 pci_release_regions(pdev);
1991err_out_mwi:
1992 pci_clear_mwi(pdev);
1993err_out_disable:
1994 pci_disable_device(pdev);
1995err_out_free:
1996 free_netdev(dev);
1997 return rc;
1998}
1999
2000static void cp_remove_one (struct pci_dev *pdev)
2001{
2002 struct net_device *dev = pci_get_drvdata(pdev);
2003 struct cp_private *cp = netdev_priv(dev);
2004
1da177e4
LT		 2005 unregister_netdev(dev);
2006 iounmap(cp->regs);
2e8a538d
JG		 2007 if (cp->wol_enabled)
2008 pci_set_power_state (pdev, PCI_D0);
1da177e4
LT		 2009 pci_release_regions(pdev);
2010 pci_clear_mwi(pdev);
2011 pci_disable_device(pdev);
2012 pci_set_drvdata(pdev, NULL);
2013 free_netdev(dev);
2014}
2015
2016#ifdef CONFIG_PM
05adc3b7 2017static int cp_suspend (struct pci_dev *pdev, pm_message_t state)
1da177e4 2018{
7668a494
FR		 2019 struct net_device *dev = pci_get_drvdata(pdev);
2020 struct cp_private *cp = netdev_priv(dev);
1da177e4
LT		 2021 unsigned long flags;
2022
7668a494
FR		 2023 if (!netif_running(dev))
2024 return 0;
1da177e4
LT		 2025
2026 netif_device_detach (dev);
2027 netif_stop_queue (dev);
2028
2029 spin_lock_irqsave (&cp->lock, flags);
2030
2031 /* Disable Rx and Tx */
2032 cpw16 (IntrMask, 0);
2033 cpw8 (Cmd, cpr8 (Cmd) & (~RxOn | ~TxOn));
2034
2035 spin_unlock_irqrestore (&cp->lock, flags);
2036
576cfa93
FR		 2037 pci_save_state(pdev);
2038 pci_enable_wake(pdev, pci_choose_state(pdev, state), cp->wol_enabled);
2039 pci_set_power_state(pdev, pci_choose_state(pdev, state));
1da177e4
LT		 2040
2041 return 0;
2042}
2043
2044static int cp_resume (struct pci_dev *pdev)
2045{
576cfa93
FR		 2046 struct net_device *dev = pci_get_drvdata (pdev);
2047 struct cp_private *cp = netdev_priv(dev);
a4cf0761 2048 unsigned long flags;
1da177e4 2049
576cfa93
FR		 2050 if (!netif_running(dev))
2051 return 0;
1da177e4
LT		 2052
2053 netif_device_attach (dev);
576cfa93
FR		 2054
2055 pci_set_power_state(pdev, PCI_D0);
2056 pci_restore_state(pdev);
2057 pci_enable_wake(pdev, PCI_D0, 0);
2058
2059 /* FIXME: sh*t may happen if the Rx ring buffer is depleted */
2060 cp_init_rings_index (cp);
1da177e4
LT		 2061 cp_init_hw (cp);
2062 netif_start_queue (dev);
a4cf0761
PO		 2063
2064 spin_lock_irqsave (&cp->lock, flags);
2065
2501f843 2066 mii_check_media(&cp->mii_if, netif_msg_link(cp), false);
a4cf0761
PO		 2067
2068 spin_unlock_irqrestore (&cp->lock, flags);
f3b197ac 2069
1da177e4
LT		 2070 return 0;
2071}
2072#endif /* CONFIG_PM */
2073
2074static struct pci_driver cp_driver = {
2075 .name = DRV_NAME,
2076 .id_table = cp_pci_tbl,
2077 .probe = cp_init_one,
2078 .remove = cp_remove_one,
2079#ifdef CONFIG_PM
2080 .resume = cp_resume,
2081 .suspend = cp_suspend,
2082#endif
2083};
2084
2085static int __init cp_init (void)
2086{
2087#ifdef MODULE
2088 printk("%s", version);
2089#endif
29917620 2090 return pci_register_driver(&cp_driver);
1da177e4
LT		 2091}
2092
2093static void __exit cp_exit (void)
2094{
2095 pci_unregister_driver (&cp_driver);
2096}
2097
2098module_init(cp_init);
2099module_exit(cp_exit);
Linux kernel - Deliverables
This page took 0.5413 seconds and 5 git commands to generate.