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x86: sparse_irq: fix typo in debug print out
[deliverable/linux.git] / drivers / net / 8139cp.c
CommitLineData
1da177e4
LT		 1/* 8139cp.c: A Linux PCI Ethernet driver for the RealTek 8139C+ chips. */
2/*
3 Copyright 2001-2004 Jeff Garzik <jgarzik@pobox.com>
4
5 Copyright (C) 2001, 2002 David S. Miller (davem@redhat.com) [tg3.c]
6 Copyright (C) 2000, 2001 David S. Miller (davem@redhat.com) [sungem.c]
7 Copyright 2001 Manfred Spraul [natsemi.c]
8 Copyright 1999-2001 by Donald Becker. [natsemi.c]
9 Written 1997-2001 by Donald Becker. [8139too.c]
10 Copyright 1998-2001 by Jes Sorensen, <jes@trained-monkey.org>. [acenic.c]
11
12 This software may be used and distributed according to the terms of
13 the GNU General Public License (GPL), incorporated herein by reference.
14 Drivers based on or derived from this code fall under the GPL and must
15 retain the authorship, copyright and license notice. This file is not
16 a complete program and may only be used when the entire operating
17 system is licensed under the GPL.
18
19 See the file COPYING in this distribution for more information.
20
21 Contributors:
f3b197ac 22
1da177e4
LT		 23 Wake-on-LAN support - Felipe Damasio <felipewd@terra.com.br>
24 PCI suspend/resume - Felipe Damasio <felipewd@terra.com.br>
25 LinkChg interrupt - Felipe Damasio <felipewd@terra.com.br>
f3b197ac 26
1da177e4
LT		 27 TODO:
28 * Test Tx checksumming thoroughly
1da177e4
LT		 29
30 Low priority TODO:
31 * Complete reset on PciErr
32 * Consider Rx interrupt mitigation using TimerIntr
33 * Investigate using skb->priority with h/w VLAN priority
34 * Investigate using High Priority Tx Queue with skb->priority
35 * Adjust Rx FIFO threshold and Max Rx DMA burst on Rx FIFO error
36 * Adjust Tx FIFO threshold and Max Tx DMA burst on Tx FIFO error
37 * Implement Tx software interrupt mitigation via
38 Tx descriptor bit
39 * The real minimum of CP_MIN_MTU is 4 bytes. However,
40 for this to be supported, one must(?) turn on packet padding.
41 * Support external MII transceivers (patch available)
42
43 NOTES:
44 * TX checksumming is considered experimental. It is off by
45 default, use ethtool to turn it on.
46
47 */
48
49#define DRV_NAME "8139cp"
d5b20697 50#define DRV_VERSION "1.3"
1da177e4
LT		 51#define DRV_RELDATE "Mar 22, 2004"
52
53
1da177e4 54#include <linux/module.h>
e21ba282 55#include <linux/moduleparam.h>
1da177e4
LT		 56#include <linux/kernel.h>
57#include <linux/compiler.h>
58#include <linux/netdevice.h>
59#include <linux/etherdevice.h>
60#include <linux/init.h>
61#include <linux/pci.h>
8662d061 62#include <linux/dma-mapping.h>
1da177e4
LT		 63#include <linux/delay.h>
64#include <linux/ethtool.h>
65#include <linux/mii.h>
66#include <linux/if_vlan.h>
67#include <linux/crc32.h>
68#include <linux/in.h>
69#include <linux/ip.h>
70#include <linux/tcp.h>
71#include <linux/udp.h>
72#include <linux/cache.h>
73#include <asm/io.h>
74#include <asm/irq.h>
75#include <asm/uaccess.h>
76
77/* VLAN tagging feature enable/disable */
78#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
79#define CP_VLAN_TAG_USED 1
80#define CP_VLAN_TX_TAG(tx_desc,vlan_tag_value) \
cf983019 81 do { (tx_desc)->opts2 = cpu_to_le32(vlan_tag_value); } while (0)
1da177e4
LT		 82#else
83#define CP_VLAN_TAG_USED 0
84#define CP_VLAN_TX_TAG(tx_desc,vlan_tag_value) \
85 do { (tx_desc)->opts2 = 0; } while (0)
86#endif
87
88/* These identify the driver base version and may not be removed. */
89static char version[] =
90KERN_INFO DRV_NAME ": 10/100 PCI Ethernet driver v" DRV_VERSION " (" DRV_RELDATE ")\n";
91
92MODULE_AUTHOR("Jeff Garzik <jgarzik@pobox.com>");
93MODULE_DESCRIPTION("RealTek RTL-8139C+ series 10/100 PCI Ethernet driver");
a78d8927 94MODULE_VERSION(DRV_VERSION);
1da177e4
LT		 95MODULE_LICENSE("GPL");
96
97static int debug = -1;
e21ba282 98module_param(debug, int, 0);
1da177e4
LT		 99MODULE_PARM_DESC (debug, "8139cp: bitmapped message enable number");
100
101/* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
102 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
103static int multicast_filter_limit = 32;
e21ba282 104module_param(multicast_filter_limit, int, 0);
1da177e4
LT		 105MODULE_PARM_DESC (multicast_filter_limit, "8139cp: maximum number of filtered multicast addresses");
106
107#define PFX DRV_NAME ": "
108
1da177e4
LT		 109#define CP_DEF_MSG_ENABLE (NETIF_MSG_DRV | \
110 NETIF_MSG_PROBE | \
111 NETIF_MSG_LINK)
112#define CP_NUM_STATS 14 /* struct cp_dma_stats, plus one */
113#define CP_STATS_SIZE 64 /* size in bytes of DMA stats block */
114#define CP_REGS_SIZE (0xff + 1)
115#define CP_REGS_VER 1 /* version 1 */
116#define CP_RX_RING_SIZE 64
117#define CP_TX_RING_SIZE 64
118#define CP_RING_BYTES \
119 ((sizeof(struct cp_desc) * CP_RX_RING_SIZE) + \
120 (sizeof(struct cp_desc) * CP_TX_RING_SIZE) + \
121 CP_STATS_SIZE)
122#define NEXT_TX(N) (((N) + 1) & (CP_TX_RING_SIZE - 1))
123#define NEXT_RX(N) (((N) + 1) & (CP_RX_RING_SIZE - 1))
124#define TX_BUFFS_AVAIL(CP) \
125 (((CP)->tx_tail <= (CP)->tx_head) ? \
126 (CP)->tx_tail + (CP_TX_RING_SIZE - 1) - (CP)->tx_head : \
127 (CP)->tx_tail - (CP)->tx_head - 1)
128
129#define PKT_BUF_SZ 1536 /* Size of each temporary Rx buffer.*/
1da177e4
LT		 130#define CP_INTERNAL_PHY 32
131
132/* The following settings are log_2(bytes)-4: 0 == 16 bytes .. 6==1024, 7==end of packet. */
133#define RX_FIFO_THRESH 5 /* Rx buffer level before first PCI xfer. */
134#define RX_DMA_BURST 4 /* Maximum PCI burst, '4' is 256 */
135#define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
136#define TX_EARLY_THRESH 256 /* Early Tx threshold, in bytes */
137
138/* Time in jiffies before concluding the transmitter is hung. */
139#define TX_TIMEOUT (6*HZ)
140
141/* hardware minimum and maximum for a single frame's data payload */
142#define CP_MIN_MTU 60 /* TODO: allow lower, but pad */
143#define CP_MAX_MTU 4096
144
145enum {
146 /* NIC register offsets */
147 MAC0 = 0x00, /* Ethernet hardware address. */
148 MAR0 = 0x08, /* Multicast filter. */
149 StatsAddr = 0x10, /* 64-bit start addr of 64-byte DMA stats blk */
150 TxRingAddr = 0x20, /* 64-bit start addr of Tx ring */
151 HiTxRingAddr = 0x28, /* 64-bit start addr of high priority Tx ring */
152 Cmd = 0x37, /* Command register */
153 IntrMask = 0x3C, /* Interrupt mask */
154 IntrStatus = 0x3E, /* Interrupt status */
155 TxConfig = 0x40, /* Tx configuration */
156 ChipVersion = 0x43, /* 8-bit chip version, inside TxConfig */
157 RxConfig = 0x44, /* Rx configuration */
158 RxMissed = 0x4C, /* 24 bits valid, write clears */
159 Cfg9346 = 0x50, /* EEPROM select/control; Cfg reg [un]lock */
160 Config1 = 0x52, /* Config1 */
161 Config3 = 0x59, /* Config3 */
162 Config4 = 0x5A, /* Config4 */
163 MultiIntr = 0x5C, /* Multiple interrupt select */
164 BasicModeCtrl = 0x62, /* MII BMCR */
165 BasicModeStatus = 0x64, /* MII BMSR */
166 NWayAdvert = 0x66, /* MII ADVERTISE */
167 NWayLPAR = 0x68, /* MII LPA */
168 NWayExpansion = 0x6A, /* MII Expansion */
169 Config5 = 0xD8, /* Config5 */
170 TxPoll = 0xD9, /* Tell chip to check Tx descriptors for work */
171 RxMaxSize = 0xDA, /* Max size of an Rx packet (8169 only) */
172 CpCmd = 0xE0, /* C+ Command register (C+ mode only) */
173 IntrMitigate = 0xE2, /* rx/tx interrupt mitigation control */
174 RxRingAddr = 0xE4, /* 64-bit start addr of Rx ring */
175 TxThresh = 0xEC, /* Early Tx threshold */
176 OldRxBufAddr = 0x30, /* DMA address of Rx ring buffer (C mode) */
177 OldTSD0 = 0x10, /* DMA address of first Tx desc (C mode) */
178
179 /* Tx and Rx status descriptors */
180 DescOwn = (1 << 31), /* Descriptor is owned by NIC */
181 RingEnd = (1 << 30), /* End of descriptor ring */
182 FirstFrag = (1 << 29), /* First segment of a packet */
183 LastFrag = (1 << 28), /* Final segment of a packet */
fcec3456
JG		 184 LargeSend = (1 << 27), /* TCP Large Send Offload (TSO) */
185 MSSShift = 16, /* MSS value position */
186 MSSMask = 0xfff, /* MSS value: 11 bits */
1da177e4
LT		 187 TxError = (1 << 23), /* Tx error summary */
188 RxError = (1 << 20), /* Rx error summary */
189 IPCS = (1 << 18), /* Calculate IP checksum */
190 UDPCS = (1 << 17), /* Calculate UDP/IP checksum */
191 TCPCS = (1 << 16), /* Calculate TCP/IP checksum */
192 TxVlanTag = (1 << 17), /* Add VLAN tag */
193 RxVlanTagged = (1 << 16), /* Rx VLAN tag available */
194 IPFail = (1 << 15), /* IP checksum failed */
195 UDPFail = (1 << 14), /* UDP/IP checksum failed */
196 TCPFail = (1 << 13), /* TCP/IP checksum failed */
197 NormalTxPoll = (1 << 6), /* One or more normal Tx packets to send */
198 PID1 = (1 << 17), /* 2 protocol id bits: 0==non-IP, */
199 PID0 = (1 << 16), /* 1==UDP/IP, 2==TCP/IP, 3==IP */
200 RxProtoTCP = 1,
201 RxProtoUDP = 2,
202 RxProtoIP = 3,
203 TxFIFOUnder = (1 << 25), /* Tx FIFO underrun */
204 TxOWC = (1 << 22), /* Tx Out-of-window collision */
205 TxLinkFail = (1 << 21), /* Link failed during Tx of packet */
206 TxMaxCol = (1 << 20), /* Tx aborted due to excessive collisions */
207 TxColCntShift = 16, /* Shift, to get 4-bit Tx collision cnt */
208 TxColCntMask = 0x01 | 0x02 | 0x04 | 0x08, /* 4-bit collision count */
209 RxErrFrame = (1 << 27), /* Rx frame alignment error */
210 RxMcast = (1 << 26), /* Rx multicast packet rcv'd */
211 RxErrCRC = (1 << 18), /* Rx CRC error */
212 RxErrRunt = (1 << 19), /* Rx error, packet < 64 bytes */
213 RxErrLong = (1 << 21), /* Rx error, packet > 4096 bytes */
214 RxErrFIFO = (1 << 22), /* Rx error, FIFO overflowed, pkt bad */
215
216 /* StatsAddr register */
217 DumpStats = (1 << 3), /* Begin stats dump */
218
219 /* RxConfig register */
220 RxCfgFIFOShift = 13, /* Shift, to get Rx FIFO thresh value */
221 RxCfgDMAShift = 8, /* Shift, to get Rx Max DMA value */
222 AcceptErr = 0x20, /* Accept packets with CRC errors */
223 AcceptRunt = 0x10, /* Accept runt (<64 bytes) packets */
224 AcceptBroadcast = 0x08, /* Accept broadcast packets */
225 AcceptMulticast = 0x04, /* Accept multicast packets */
226 AcceptMyPhys = 0x02, /* Accept pkts with our MAC as dest */
227 AcceptAllPhys = 0x01, /* Accept all pkts w/ physical dest */
228
229 /* IntrMask / IntrStatus registers */
230 PciErr = (1 << 15), /* System error on the PCI bus */
231 TimerIntr = (1 << 14), /* Asserted when TCTR reaches TimerInt value */
232 LenChg = (1 << 13), /* Cable length change */
233 SWInt = (1 << 8), /* Software-requested interrupt */
234 TxEmpty = (1 << 7), /* No Tx descriptors available */
235 RxFIFOOvr = (1 << 6), /* Rx FIFO Overflow */
236 LinkChg = (1 << 5), /* Packet underrun, or link change */
237 RxEmpty = (1 << 4), /* No Rx descriptors available */
238 TxErr = (1 << 3), /* Tx error */
239 TxOK = (1 << 2), /* Tx packet sent */
240 RxErr = (1 << 1), /* Rx error */
241 RxOK = (1 << 0), /* Rx packet received */
242 IntrResvd = (1 << 10), /* reserved, according to RealTek engineers,
243 but hardware likes to raise it */
244
245 IntrAll = PciErr | TimerIntr | LenChg | SWInt | TxEmpty |
246 RxFIFOOvr | LinkChg | RxEmpty | TxErr | TxOK |
247 RxErr | RxOK | IntrResvd,
248
249 /* C mode command register */
250 CmdReset = (1 << 4), /* Enable to reset; self-clearing */
251 RxOn = (1 << 3), /* Rx mode enable */
252 TxOn = (1 << 2), /* Tx mode enable */
253
254 /* C+ mode command register */
255 RxVlanOn = (1 << 6), /* Rx VLAN de-tagging enable */
256 RxChkSum = (1 << 5), /* Rx checksum offload enable */
257 PCIDAC = (1 << 4), /* PCI Dual Address Cycle (64-bit PCI) */
258 PCIMulRW = (1 << 3), /* Enable PCI read/write multiple */
259 CpRxOn = (1 << 1), /* Rx mode enable */
260 CpTxOn = (1 << 0), /* Tx mode enable */
261
262 /* Cfg9436 EEPROM control register */
263 Cfg9346_Lock = 0x00, /* Lock ConfigX/MII register access */
264 Cfg9346_Unlock = 0xC0, /* Unlock ConfigX/MII register access */
265
266 /* TxConfig register */
267 IFG = (1 << 25) | (1 << 24), /* standard IEEE interframe gap */
268 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
269
270 /* Early Tx Threshold register */
271 TxThreshMask = 0x3f, /* Mask bits 5-0 */
272 TxThreshMax = 2048, /* Max early Tx threshold */
273
274 /* Config1 register */
275 DriverLoaded = (1 << 5), /* Software marker, driver is loaded */
276 LWACT = (1 << 4), /* LWAKE active mode */
277 PMEnable = (1 << 0), /* Enable various PM features of chip */
278
279 /* Config3 register */
280 PARMEnable = (1 << 6), /* Enable auto-loading of PHY parms */
281 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */
282 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */
283
284 /* Config4 register */
285 LWPTN = (1 << 1), /* LWAKE Pattern */
286 LWPME = (1 << 4), /* LANWAKE vs PMEB */
287
288 /* Config5 register */
289 BWF = (1 << 6), /* Accept Broadcast wakeup frame */
290 MWF = (1 << 5), /* Accept Multicast wakeup frame */
291 UWF = (1 << 4), /* Accept Unicast wakeup frame */
292 LANWake = (1 << 1), /* Enable LANWake signal */
293 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */
294
295 cp_norx_intr_mask = PciErr | LinkChg | TxOK | TxErr | TxEmpty,
296 cp_rx_intr_mask = RxOK | RxErr | RxEmpty | RxFIFOOvr,
297 cp_intr_mask = cp_rx_intr_mask | cp_norx_intr_mask,
298};
299
300static const unsigned int cp_rx_config =
301 (RX_FIFO_THRESH << RxCfgFIFOShift) |
302 (RX_DMA_BURST << RxCfgDMAShift);
303
304struct cp_desc {
03233b90 305 __le32 opts1;
cf983019 306 __le32 opts2;
03233b90 307 __le64 addr;
1da177e4
LT		 308};
309
1da177e4 310struct cp_dma_stats {
03233b90
AV		 311 __le64 tx_ok;
312 __le64 rx_ok;
313 __le64 tx_err;
314 __le32 rx_err;
315 __le16 rx_fifo;
316 __le16 frame_align;
317 __le32 tx_ok_1col;
318 __le32 tx_ok_mcol;
319 __le64 rx_ok_phys;
320 __le64 rx_ok_bcast;
321 __le32 rx_ok_mcast;
322 __le16 tx_abort;
323 __le16 tx_underrun;
1da177e4
LT		 324} __attribute__((packed));
325
326struct cp_extra_stats {
327 unsigned long rx_frags;
328};
329
330struct cp_private {
331 void __iomem *regs;
332 struct net_device *dev;
333 spinlock_t lock;
334 u32 msg_enable;
335
bea3348e
SH		 336 struct napi_struct napi;
337
1da177e4
LT		 338 struct pci_dev *pdev;
339 u32 rx_config;
340 u16 cpcmd;
341
1da177e4 342 struct cp_extra_stats cp_stats;
1da177e4 343
d03d376d
FR		 344 unsigned rx_head ____cacheline_aligned;
345 unsigned rx_tail;
1da177e4 346 struct cp_desc *rx_ring;
0ba894d4 347 struct sk_buff *rx_skb[CP_RX_RING_SIZE];
1da177e4
LT		 348
349 unsigned tx_head ____cacheline_aligned;
350 unsigned tx_tail;
1da177e4 351 struct cp_desc *tx_ring;
48907e39 352 struct sk_buff *tx_skb[CP_TX_RING_SIZE];
d03d376d
FR		 353
354 unsigned rx_buf_sz;
355 unsigned wol_enabled : 1; /* Is Wake-on-LAN enabled? */
1da177e4
LT		 356
357#if CP_VLAN_TAG_USED
358 struct vlan_group *vlgrp;
359#endif
d03d376d 360 dma_addr_t ring_dma;
1da177e4
LT		 361
362 struct mii_if_info mii_if;
363};
364
365#define cpr8(reg) readb(cp->regs + (reg))
366#define cpr16(reg) readw(cp->regs + (reg))
367#define cpr32(reg) readl(cp->regs + (reg))
368#define cpw8(reg,val) writeb((val), cp->regs + (reg))
369#define cpw16(reg,val) writew((val), cp->regs + (reg))
370#define cpw32(reg,val) writel((val), cp->regs + (reg))
371#define cpw8_f(reg,val) do { \
372 writeb((val), cp->regs + (reg)); \
373 readb(cp->regs + (reg)); \
374 } while (0)
375#define cpw16_f(reg,val) do { \
376 writew((val), cp->regs + (reg)); \
377 readw(cp->regs + (reg)); \
378 } while (0)
379#define cpw32_f(reg,val) do { \
380 writel((val), cp->regs + (reg)); \
381 readl(cp->regs + (reg)); \
382 } while (0)
383
384
385static void __cp_set_rx_mode (struct net_device *dev);
386static void cp_tx (struct cp_private *cp);
387static void cp_clean_rings (struct cp_private *cp);
7502cd10
SK		 388#ifdef CONFIG_NET_POLL_CONTROLLER
389static void cp_poll_controller(struct net_device *dev);
390#endif
722fdb33
PC		 391static int cp_get_eeprom_len(struct net_device *dev);
392static int cp_get_eeprom(struct net_device *dev,
393 struct ethtool_eeprom *eeprom, u8 *data);
394static int cp_set_eeprom(struct net_device *dev,
395 struct ethtool_eeprom *eeprom, u8 *data);
1da177e4
LT		 396
397static struct pci_device_id cp_pci_tbl[] = {
cccb20d3
FR		 398 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, PCI_DEVICE_ID_REALTEK_8139), },
399 { PCI_DEVICE(PCI_VENDOR_ID_TTTECH, PCI_DEVICE_ID_TTTECH_MC322), },
1da177e4
LT		 400 { },
401};
402MODULE_DEVICE_TABLE(pci, cp_pci_tbl);
403
404static struct {
405 const char str[ETH_GSTRING_LEN];
406} ethtool_stats_keys[] = {
407 { "tx_ok" },
408 { "rx_ok" },
409 { "tx_err" },
410 { "rx_err" },
411 { "rx_fifo" },
412 { "frame_align" },
413 { "tx_ok_1col" },
414 { "tx_ok_mcol" },
415 { "rx_ok_phys" },
416 { "rx_ok_bcast" },
417 { "rx_ok_mcast" },
418 { "tx_abort" },
419 { "tx_underrun" },
420 { "rx_frags" },
421};
422
423
424#if CP_VLAN_TAG_USED
425static void cp_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
426{
427 struct cp_private *cp = netdev_priv(dev);
428 unsigned long flags;
429
430 spin_lock_irqsave(&cp->lock, flags);
431 cp->vlgrp = grp;
7b332244
SH		 432 if (grp)
433 cp->cpcmd |= RxVlanOn;
434 else
435 cp->cpcmd &= ~RxVlanOn;
1da177e4 436
1da177e4 437 cpw16(CpCmd, cp->cpcmd);
1da177e4
LT		 438 spin_unlock_irqrestore(&cp->lock, flags);
439}
440#endif /* CP_VLAN_TAG_USED */
441
442static inline void cp_set_rxbufsize (struct cp_private *cp)
443{
444 unsigned int mtu = cp->dev->mtu;
f3b197ac 445
1da177e4
LT		 446 if (mtu > ETH_DATA_LEN)
447 /* MTU + ethernet header + FCS + optional VLAN tag */
448 cp->rx_buf_sz = mtu + ETH_HLEN + 8;
449 else
450 cp->rx_buf_sz = PKT_BUF_SZ;
451}
452
453static inline void cp_rx_skb (struct cp_private *cp, struct sk_buff *skb,
454 struct cp_desc *desc)
455{
456 skb->protocol = eth_type_trans (skb, cp->dev);
457
237225f7
PZ		 458 cp->dev->stats.rx_packets++;
459 cp->dev->stats.rx_bytes += skb->len;
1da177e4
LT		 460 cp->dev->last_rx = jiffies;
461
462#if CP_VLAN_TAG_USED
cf983019 463 if (cp->vlgrp && (desc->opts2 & cpu_to_le32(RxVlanTagged))) {
1da177e4 464 vlan_hwaccel_receive_skb(skb, cp->vlgrp,
cf983019 465 swab16(le32_to_cpu(desc->opts2) & 0xffff));
1da177e4
LT		 466 } else
467#endif
468 netif_receive_skb(skb);
469}
470
471static void cp_rx_err_acct (struct cp_private *cp, unsigned rx_tail,
472 u32 status, u32 len)
473{
474 if (netif_msg_rx_err (cp))
475 printk (KERN_DEBUG
476 "%s: rx err, slot %d status 0x%x len %d\n",
477 cp->dev->name, rx_tail, status, len);
237225f7 478 cp->dev->stats.rx_errors++;
1da177e4 479 if (status & RxErrFrame)
237225f7 480 cp->dev->stats.rx_frame_errors++;
1da177e4 481 if (status & RxErrCRC)
237225f7 482 cp->dev->stats.rx_crc_errors++;
1da177e4 483 if ((status & RxErrRunt) || (status & RxErrLong))
237225f7 484 cp->dev->stats.rx_length_errors++;
1da177e4 485 if ((status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag))
237225f7 486 cp->dev->stats.rx_length_errors++;
1da177e4 487 if (status & RxErrFIFO)
237225f7 488 cp->dev->stats.rx_fifo_errors++;
1da177e4
LT		 489}
490
491static inline unsigned int cp_rx_csum_ok (u32 status)
492{
493 unsigned int protocol = (status >> 16) & 0x3;
f3b197ac 494
1da177e4
LT		 495 if (likely((protocol == RxProtoTCP) && (!(status & TCPFail))))
496 return 1;
497 else if ((protocol == RxProtoUDP) && (!(status & UDPFail)))
498 return 1;
499 else if ((protocol == RxProtoIP) && (!(status & IPFail)))
500 return 1;
501 return 0;
502}
503
bea3348e 504static int cp_rx_poll(struct napi_struct *napi, int budget)
1da177e4 505{
bea3348e
SH		 506 struct cp_private *cp = container_of(napi, struct cp_private, napi);
507 struct net_device *dev = cp->dev;
508 unsigned int rx_tail = cp->rx_tail;
509 int rx;
1da177e4
LT		 510
511rx_status_loop:
512 rx = 0;
513 cpw16(IntrStatus, cp_rx_intr_mask);
514
515 while (1) {
516 u32 status, len;
517 dma_addr_t mapping;
518 struct sk_buff *skb, *new_skb;
519 struct cp_desc *desc;
520 unsigned buflen;
521
0ba894d4 522 skb = cp->rx_skb[rx_tail];
5d9428de 523 BUG_ON(!skb);
1da177e4
LT		 524
525 desc = &cp->rx_ring[rx_tail];
526 status = le32_to_cpu(desc->opts1);
527 if (status & DescOwn)
528 break;
529
530 len = (status & 0x1fff) - 4;
3598b57b 531 mapping = le64_to_cpu(desc->addr);
1da177e4
LT		 532
533 if ((status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag)) {
534 /* we don't support incoming fragmented frames.
535 * instead, we attempt to ensure that the
536 * pre-allocated RX skbs are properly sized such
537 * that RX fragments are never encountered
538 */
539 cp_rx_err_acct(cp, rx_tail, status, len);
237225f7 540 dev->stats.rx_dropped++;
1da177e4
LT		 541 cp->cp_stats.rx_frags++;
542 goto rx_next;
543 }
544
545 if (status & (RxError | RxErrFIFO)) {
546 cp_rx_err_acct(cp, rx_tail, status, len);
547 goto rx_next;
548 }
549
550 if (netif_msg_rx_status(cp))
551 printk(KERN_DEBUG "%s: rx slot %d status 0x%x len %d\n",
c48e9399 552 dev->name, rx_tail, status, len);
1da177e4 553
a52be1cb
KL		 554 buflen = cp->rx_buf_sz + NET_IP_ALIGN;
555 new_skb = netdev_alloc_skb(dev, buflen);
1da177e4 556 if (!new_skb) {
237225f7 557 dev->stats.rx_dropped++;
1da177e4
LT		 558 goto rx_next;
559 }
560
a52be1cb 561 skb_reserve(new_skb, NET_IP_ALIGN);
1da177e4 562
6cc92cdd 563 dma_unmap_single(&cp->pdev->dev, mapping,
1da177e4
LT		 564 buflen, PCI_DMA_FROMDEVICE);
565
566 /* Handle checksum offloading for incoming packets. */
567 if (cp_rx_csum_ok(status))
568 skb->ip_summed = CHECKSUM_UNNECESSARY;
569 else
570 skb->ip_summed = CHECKSUM_NONE;
571
572 skb_put(skb, len);
573
6cc92cdd 574 mapping = dma_map_single(&cp->pdev->dev, new_skb->data, buflen,
3598b57b 575 PCI_DMA_FROMDEVICE);
0ba894d4 576 cp->rx_skb[rx_tail] = new_skb;
1da177e4
LT		 577
578 cp_rx_skb(cp, skb, desc);
579 rx++;
580
581rx_next:
582 cp->rx_ring[rx_tail].opts2 = 0;
583 cp->rx_ring[rx_tail].addr = cpu_to_le64(mapping);
584 if (rx_tail == (CP_RX_RING_SIZE - 1))
585 desc->opts1 = cpu_to_le32(DescOwn | RingEnd |
586 cp->rx_buf_sz);
587 else
588 desc->opts1 = cpu_to_le32(DescOwn | cp->rx_buf_sz);
589 rx_tail = NEXT_RX(rx_tail);
590
bea3348e 591 if (rx >= budget)
1da177e4
LT		 592 break;
593 }
594
595 cp->rx_tail = rx_tail;
596
1da177e4
LT		 597 /* if we did not reach work limit, then we're done with
598 * this round of polling
599 */
bea3348e 600 if (rx < budget) {
d15e9c4d
FR		 601 unsigned long flags;
602
1da177e4
LT		 603 if (cpr16(IntrStatus) & cp_rx_intr_mask)
604 goto rx_status_loop;
605
bea3348e 606 spin_lock_irqsave(&cp->lock, flags);
1da177e4 607 cpw16_f(IntrMask, cp_intr_mask);
bea3348e
SH		 608 __netif_rx_complete(dev, napi);
609 spin_unlock_irqrestore(&cp->lock, flags);
1da177e4
LT		 610 }
611
bea3348e 612 return rx;
1da177e4
LT		 613}
614
7d12e780 615static irqreturn_t cp_interrupt (int irq, void *dev_instance)
1da177e4
LT		 616{
617 struct net_device *dev = dev_instance;
618 struct cp_private *cp;
619 u16 status;
620
621 if (unlikely(dev == NULL))
622 return IRQ_NONE;
623 cp = netdev_priv(dev);
624
625 status = cpr16(IntrStatus);
626 if (!status || (status == 0xFFFF))
627 return IRQ_NONE;
628
629 if (netif_msg_intr(cp))
630 printk(KERN_DEBUG "%s: intr, status %04x cmd %02x cpcmd %04x\n",
631 dev->name, status, cpr8(Cmd), cpr16(CpCmd));
632
633 cpw16(IntrStatus, status & ~cp_rx_intr_mask);
634
635 spin_lock(&cp->lock);
636
637 /* close possible race's with dev_close */
638 if (unlikely(!netif_running(dev))) {
639 cpw16(IntrMask, 0);
640 spin_unlock(&cp->lock);
641 return IRQ_HANDLED;
642 }
643
644 if (status & (RxOK | RxErr | RxEmpty | RxFIFOOvr))
bea3348e 645 if (netif_rx_schedule_prep(dev, &cp->napi)) {
1da177e4 646 cpw16_f(IntrMask, cp_norx_intr_mask);
bea3348e 647 __netif_rx_schedule(dev, &cp->napi);
1da177e4
LT		 648 }
649
650 if (status & (TxOK | TxErr | TxEmpty | SWInt))
651 cp_tx(cp);
652 if (status & LinkChg)
2501f843 653 mii_check_media(&cp->mii_if, netif_msg_link(cp), false);
1da177e4
LT		 654
655 spin_unlock(&cp->lock);
656
657 if (status & PciErr) {
658 u16 pci_status;
659
660 pci_read_config_word(cp->pdev, PCI_STATUS, &pci_status);
661 pci_write_config_word(cp->pdev, PCI_STATUS, pci_status);
662 printk(KERN_ERR "%s: PCI bus error, status=%04x, PCI status=%04x\n",
663 dev->name, status, pci_status);
664
665 /* TODO: reset hardware */
666 }
667
668 return IRQ_HANDLED;
669}
670
7502cd10
SK		 671#ifdef CONFIG_NET_POLL_CONTROLLER
672/*
673 * Polling receive - used by netconsole and other diagnostic tools
674 * to allow network i/o with interrupts disabled.
675 */
676static void cp_poll_controller(struct net_device *dev)
677{
678 disable_irq(dev->irq);
7d12e780 679 cp_interrupt(dev->irq, dev);
7502cd10
SK		 680 enable_irq(dev->irq);
681}
682#endif
683
1da177e4
LT		 684static void cp_tx (struct cp_private *cp)
685{
686 unsigned tx_head = cp->tx_head;
687 unsigned tx_tail = cp->tx_tail;
688
689 while (tx_tail != tx_head) {
3598b57b 690 struct cp_desc *txd = cp->tx_ring + tx_tail;
1da177e4
LT		 691 struct sk_buff *skb;
692 u32 status;
693
694 rmb();
3598b57b 695 status = le32_to_cpu(txd->opts1);
1da177e4
LT		 696 if (status & DescOwn)
697 break;
698
48907e39 699 skb = cp->tx_skb[tx_tail];
5d9428de 700 BUG_ON(!skb);
1da177e4 701
6cc92cdd 702 dma_unmap_single(&cp->pdev->dev, le64_to_cpu(txd->addr),
48907e39
FR		 703 le32_to_cpu(txd->opts1) & 0xffff,
704 PCI_DMA_TODEVICE);
1da177e4
LT		 705
706 if (status & LastFrag) {
707 if (status & (TxError | TxFIFOUnder)) {
708 if (netif_msg_tx_err(cp))
709 printk(KERN_DEBUG "%s: tx err, status 0x%x\n",
710 cp->dev->name, status);
237225f7 711 cp->dev->stats.tx_errors++;
1da177e4 712 if (status & TxOWC)
237225f7 713 cp->dev->stats.tx_window_errors++;
1da177e4 714 if (status & TxMaxCol)
237225f7 715 cp->dev->stats.tx_aborted_errors++;
1da177e4 716 if (status & TxLinkFail)
237225f7 717 cp->dev->stats.tx_carrier_errors++;
1da177e4 718 if (status & TxFIFOUnder)
237225f7 719 cp->dev->stats.tx_fifo_errors++;
1da177e4 720 } else {
237225f7 721 cp->dev->stats.collisions +=
1da177e4 722 ((status >> TxColCntShift) & TxColCntMask);
237225f7
PZ		 723 cp->dev->stats.tx_packets++;
724 cp->dev->stats.tx_bytes += skb->len;
1da177e4
LT		 725 if (netif_msg_tx_done(cp))
726 printk(KERN_DEBUG "%s: tx done, slot %d\n", cp->dev->name, tx_tail);
727 }
728 dev_kfree_skb_irq(skb);
729 }
730
48907e39 731 cp->tx_skb[tx_tail] = NULL;
1da177e4
LT		 732
733 tx_tail = NEXT_TX(tx_tail);
734 }
735
736 cp->tx_tail = tx_tail;
737
738 if (TX_BUFFS_AVAIL(cp) > (MAX_SKB_FRAGS + 1))
739 netif_wake_queue(cp->dev);
740}
741
742static int cp_start_xmit (struct sk_buff *skb, struct net_device *dev)
743{
744 struct cp_private *cp = netdev_priv(dev);
745 unsigned entry;
fcec3456 746 u32 eor, flags;
553af567 747 unsigned long intr_flags;
1da177e4
LT		 748#if CP_VLAN_TAG_USED
749 u32 vlan_tag = 0;
750#endif
fcec3456 751 int mss = 0;
1da177e4 752
553af567 753 spin_lock_irqsave(&cp->lock, intr_flags);
1da177e4
LT		 754
755 /* This is a hard error, log it. */
756 if (TX_BUFFS_AVAIL(cp) <= (skb_shinfo(skb)->nr_frags + 1)) {
757 netif_stop_queue(dev);
553af567 758 spin_unlock_irqrestore(&cp->lock, intr_flags);
1da177e4
LT		 759 printk(KERN_ERR PFX "%s: BUG! Tx Ring full when queue awake!\n",
760 dev->name);
761 return 1;
762 }
763
764#if CP_VLAN_TAG_USED
765 if (cp->vlgrp && vlan_tx_tag_present(skb))
cf983019 766 vlan_tag = TxVlanTag | swab16(vlan_tx_tag_get(skb));
1da177e4
LT		 767#endif
768
769 entry = cp->tx_head;
770 eor = (entry == (CP_TX_RING_SIZE - 1)) ? RingEnd : 0;
fcec3456 771 if (dev->features & NETIF_F_TSO)
7967168c 772 mss = skb_shinfo(skb)->gso_size;
fcec3456 773
1da177e4
LT		 774 if (skb_shinfo(skb)->nr_frags == 0) {
775 struct cp_desc *txd = &cp->tx_ring[entry];
776 u32 len;
777 dma_addr_t mapping;
778
779 len = skb->len;
6cc92cdd 780 mapping = dma_map_single(&cp->pdev->dev, skb->data, len, PCI_DMA_TODEVICE);
1da177e4
LT		 781 CP_VLAN_TX_TAG(txd, vlan_tag);
782 txd->addr = cpu_to_le64(mapping);
783 wmb();
784
fcec3456
JG		 785 flags = eor | len | DescOwn | FirstFrag | LastFrag;
786
787 if (mss)
788 flags |= LargeSend | ((mss & MSSMask) << MSSShift);
84fa7933 789 else if (skb->ip_summed == CHECKSUM_PARTIAL) {
eddc9ec5 790 const struct iphdr *ip = ip_hdr(skb);
1da177e4 791 if (ip->protocol == IPPROTO_TCP)
fcec3456 792 flags |= IPCS | TCPCS;
1da177e4 793 else if (ip->protocol == IPPROTO_UDP)
fcec3456 794 flags |= IPCS | UDPCS;
1da177e4 795 else
5734418d 796 WARN_ON(1); /* we need a WARN() */
fcec3456
JG		 797 }
798
799 txd->opts1 = cpu_to_le32(flags);
1da177e4
LT		 800 wmb();
801
48907e39 802 cp->tx_skb[entry] = skb;
1da177e4
LT		 803 entry = NEXT_TX(entry);
804 } else {
805 struct cp_desc *txd;
806 u32 first_len, first_eor;
807 dma_addr_t first_mapping;
808 int frag, first_entry = entry;
eddc9ec5 809 const struct iphdr *ip = ip_hdr(skb);
1da177e4
LT		 810
811 /* We must give this initial chunk to the device last.
812 * Otherwise we could race with the device.
813 */
814 first_eor = eor;
815 first_len = skb_headlen(skb);
6cc92cdd 816 first_mapping = dma_map_single(&cp->pdev->dev, skb->data,
1da177e4 817 first_len, PCI_DMA_TODEVICE);
48907e39 818 cp->tx_skb[entry] = skb;
1da177e4
LT		 819 entry = NEXT_TX(entry);
820
821 for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) {
822 skb_frag_t *this_frag = &skb_shinfo(skb)->frags[frag];
823 u32 len;
824 u32 ctrl;
825 dma_addr_t mapping;
826
827 len = this_frag->size;
6cc92cdd 828 mapping = dma_map_single(&cp->pdev->dev,
1da177e4
LT		 829 ((void *) page_address(this_frag->page) +
830 this_frag->page_offset),
831 len, PCI_DMA_TODEVICE);
832 eor = (entry == (CP_TX_RING_SIZE - 1)) ? RingEnd : 0;
833
fcec3456
JG		 834 ctrl = eor | len | DescOwn;
835
836 if (mss)
837 ctrl |= LargeSend |
838 ((mss & MSSMask) << MSSShift);
84fa7933 839 else if (skb->ip_summed == CHECKSUM_PARTIAL) {
1da177e4 840 if (ip->protocol == IPPROTO_TCP)
fcec3456 841 ctrl |= IPCS | TCPCS;
1da177e4 842 else if (ip->protocol == IPPROTO_UDP)
fcec3456 843 ctrl |= IPCS | UDPCS;
1da177e4
LT		 844 else
845 BUG();
fcec3456 846 }
1da177e4
LT		 847
848 if (frag == skb_shinfo(skb)->nr_frags - 1)
849 ctrl |= LastFrag;
850
851 txd = &cp->tx_ring[entry];
852 CP_VLAN_TX_TAG(txd, vlan_tag);
853 txd->addr = cpu_to_le64(mapping);
854 wmb();
855
856 txd->opts1 = cpu_to_le32(ctrl);
857 wmb();
858
48907e39 859 cp->tx_skb[entry] = skb;
1da177e4
LT		 860 entry = NEXT_TX(entry);
861 }
862
863 txd = &cp->tx_ring[first_entry];
864 CP_VLAN_TX_TAG(txd, vlan_tag);
865 txd->addr = cpu_to_le64(first_mapping);
866 wmb();
867
84fa7933 868 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1da177e4
LT		 869 if (ip->protocol == IPPROTO_TCP)
870 txd->opts1 = cpu_to_le32(first_eor | first_len |
871 FirstFrag | DescOwn |
872 IPCS | TCPCS);
873 else if (ip->protocol == IPPROTO_UDP)
874 txd->opts1 = cpu_to_le32(first_eor | first_len |
875 FirstFrag | DescOwn |
876 IPCS | UDPCS);
877 else
878 BUG();
879 } else
880 txd->opts1 = cpu_to_le32(first_eor | first_len |
881 FirstFrag | DescOwn);
882 wmb();
883 }
884 cp->tx_head = entry;
885 if (netif_msg_tx_queued(cp))
886 printk(KERN_DEBUG "%s: tx queued, slot %d, skblen %d\n",
887 dev->name, entry, skb->len);
888 if (TX_BUFFS_AVAIL(cp) <= (MAX_SKB_FRAGS + 1))
889 netif_stop_queue(dev);
890
553af567 891 spin_unlock_irqrestore(&cp->lock, intr_flags);
1da177e4
LT		 892
893 cpw8(TxPoll, NormalTxPoll);
894 dev->trans_start = jiffies;
895
896 return 0;
897}
898
899/* Set or clear the multicast filter for this adaptor.
900 This routine is not state sensitive and need not be SMP locked. */
901
902static void __cp_set_rx_mode (struct net_device *dev)
903{
904 struct cp_private *cp = netdev_priv(dev);
905 u32 mc_filter[2]; /* Multicast hash filter */
906 int i, rx_mode;
907 u32 tmp;
908
909 /* Note: do not reorder, GCC is clever about common statements. */
910 if (dev->flags & IFF_PROMISC) {
911 /* Unconditionally log net taps. */
1da177e4
LT		 912 rx_mode =
913 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
914 AcceptAllPhys;
915 mc_filter[1] = mc_filter[0] = 0xffffffff;
916 } else if ((dev->mc_count > multicast_filter_limit)
917 || (dev->flags & IFF_ALLMULTI)) {
918 /* Too many to filter perfectly -- accept all multicasts. */
919 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
920 mc_filter[1] = mc_filter[0] = 0xffffffff;
921 } else {
922 struct dev_mc_list *mclist;
923 rx_mode = AcceptBroadcast | AcceptMyPhys;
924 mc_filter[1] = mc_filter[0] = 0;
925 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
926 i++, mclist = mclist->next) {
927 int bit_nr = ether_crc(ETH_ALEN, mclist->dmi_addr) >> 26;
928
929 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
930 rx_mode |= AcceptMulticast;
931 }
932 }
933
934 /* We can safely update without stopping the chip. */
935 tmp = cp_rx_config | rx_mode;
936 if (cp->rx_config != tmp) {
937 cpw32_f (RxConfig, tmp);
938 cp->rx_config = tmp;
939 }
940 cpw32_f (MAR0 + 0, mc_filter[0]);
941 cpw32_f (MAR0 + 4, mc_filter[1]);
942}
943
944static void cp_set_rx_mode (struct net_device *dev)
945{
946 unsigned long flags;
947 struct cp_private *cp = netdev_priv(dev);
948
949 spin_lock_irqsave (&cp->lock, flags);
950 __cp_set_rx_mode(dev);
951 spin_unlock_irqrestore (&cp->lock, flags);
952}
953
954static void __cp_get_stats(struct cp_private *cp)
955{
956 /* only lower 24 bits valid; write any value to clear */
237225f7 957 cp->dev->stats.rx_missed_errors += (cpr32 (RxMissed) & 0xffffff);
1da177e4
LT		 958 cpw32 (RxMissed, 0);
959}
960
961static struct net_device_stats *cp_get_stats(struct net_device *dev)
962{
963 struct cp_private *cp = netdev_priv(dev);
964 unsigned long flags;
965
966 /* The chip only need report frame silently dropped. */
967 spin_lock_irqsave(&cp->lock, flags);
968 if (netif_running(dev) && netif_device_present(dev))
969 __cp_get_stats(cp);
970 spin_unlock_irqrestore(&cp->lock, flags);
971
237225f7 972 return &dev->stats;
1da177e4
LT		 973}
974
975static void cp_stop_hw (struct cp_private *cp)
976{
977 cpw16(IntrStatus, ~(cpr16(IntrStatus)));
978 cpw16_f(IntrMask, 0);
979 cpw8(Cmd, 0);
980 cpw16_f(CpCmd, 0);
981 cpw16_f(IntrStatus, ~(cpr16(IntrStatus)));
982
983 cp->rx_tail = 0;
984 cp->tx_head = cp->tx_tail = 0;
985}
986
987static void cp_reset_hw (struct cp_private *cp)
988{
989 unsigned work = 1000;
990
991 cpw8(Cmd, CmdReset);
992
993 while (work--) {
994 if (!(cpr8(Cmd) & CmdReset))
995 return;
996
3173c890 997 schedule_timeout_uninterruptible(10);
1da177e4
LT		 998 }
999
1000 printk(KERN_ERR "%s: hardware reset timeout\n", cp->dev->name);
1001}
1002
1003static inline void cp_start_hw (struct cp_private *cp)
1004{
1005 cpw16(CpCmd, cp->cpcmd);
1006 cpw8(Cmd, RxOn | TxOn);
1007}
1008
1009static void cp_init_hw (struct cp_private *cp)
1010{
1011 struct net_device *dev = cp->dev;
1012 dma_addr_t ring_dma;
1013
1014 cp_reset_hw(cp);
1015
1016 cpw8_f (Cfg9346, Cfg9346_Unlock);
1017
1018 /* Restore our idea of the MAC address. */
03233b90
AV		 1019 cpw32_f (MAC0 + 0, le32_to_cpu (*(__le32 *) (dev->dev_addr + 0)));
1020 cpw32_f (MAC0 + 4, le32_to_cpu (*(__le32 *) (dev->dev_addr + 4)));
1da177e4
LT		 1021
1022 cp_start_hw(cp);
1023 cpw8(TxThresh, 0x06); /* XXX convert magic num to a constant */
1024
1025 __cp_set_rx_mode(dev);
1026 cpw32_f (TxConfig, IFG | (TX_DMA_BURST << TxDMAShift));
1027
1028 cpw8(Config1, cpr8(Config1) | DriverLoaded | PMEnable);
1029 /* Disable Wake-on-LAN. Can be turned on with ETHTOOL_SWOL */
1030 cpw8(Config3, PARMEnable);
1031 cp->wol_enabled = 0;
1032
f3b197ac 1033 cpw8(Config5, cpr8(Config5) & PMEStatus);
1da177e4
LT		 1034
1035 cpw32_f(HiTxRingAddr, 0);
1036 cpw32_f(HiTxRingAddr + 4, 0);
1037
1038 ring_dma = cp->ring_dma;
1039 cpw32_f(RxRingAddr, ring_dma & 0xffffffff);
1040 cpw32_f(RxRingAddr + 4, (ring_dma >> 16) >> 16);
1041
1042 ring_dma += sizeof(struct cp_desc) * CP_RX_RING_SIZE;
1043 cpw32_f(TxRingAddr, ring_dma & 0xffffffff);
1044 cpw32_f(TxRingAddr + 4, (ring_dma >> 16) >> 16);
1045
1046 cpw16(MultiIntr, 0);
1047
1048 cpw16_f(IntrMask, cp_intr_mask);
1049
1050 cpw8_f(Cfg9346, Cfg9346_Lock);
1051}
1052
a52be1cb 1053static int cp_refill_rx(struct cp_private *cp)
1da177e4 1054{
a52be1cb 1055 struct net_device *dev = cp->dev;
1da177e4
LT		 1056 unsigned i;
1057
1058 for (i = 0; i < CP_RX_RING_SIZE; i++) {
1059 struct sk_buff *skb;
3598b57b 1060 dma_addr_t mapping;
1da177e4 1061
a52be1cb 1062 skb = netdev_alloc_skb(dev, cp->rx_buf_sz + NET_IP_ALIGN);
1da177e4
LT		 1063 if (!skb)
1064 goto err_out;
1065
a52be1cb 1066 skb_reserve(skb, NET_IP_ALIGN);
1da177e4 1067
6cc92cdd
JG		 1068 mapping = dma_map_single(&cp->pdev->dev, skb->data,
1069 cp->rx_buf_sz, PCI_DMA_FROMDEVICE);
0ba894d4 1070 cp->rx_skb[i] = skb;
1da177e4
LT		 1071
1072 cp->rx_ring[i].opts2 = 0;
3598b57b 1073 cp->rx_ring[i].addr = cpu_to_le64(mapping);
1da177e4
LT		 1074 if (i == (CP_RX_RING_SIZE - 1))
1075 cp->rx_ring[i].opts1 =
1076 cpu_to_le32(DescOwn | RingEnd | cp->rx_buf_sz);
1077 else
1078 cp->rx_ring[i].opts1 =
1079 cpu_to_le32(DescOwn | cp->rx_buf_sz);
1080 }
1081
1082 return 0;
1083
1084err_out:
1085 cp_clean_rings(cp);
1086 return -ENOMEM;
1087}
1088
576cfa93
FR		 1089static void cp_init_rings_index (struct cp_private *cp)
1090{
1091 cp->rx_tail = 0;
1092 cp->tx_head = cp->tx_tail = 0;
1093}
1094
1da177e4
LT		 1095static int cp_init_rings (struct cp_private *cp)
1096{
1097 memset(cp->tx_ring, 0, sizeof(struct cp_desc) * CP_TX_RING_SIZE);
1098 cp->tx_ring[CP_TX_RING_SIZE - 1].opts1 = cpu_to_le32(RingEnd);
1099
576cfa93 1100 cp_init_rings_index(cp);
1da177e4
LT		 1101
1102 return cp_refill_rx (cp);
1103}
1104
1105static int cp_alloc_rings (struct cp_private *cp)
1106{
1107 void *mem;
1108
6cc92cdd
JG		 1109 mem = dma_alloc_coherent(&cp->pdev->dev, CP_RING_BYTES,
1110 &cp->ring_dma, GFP_KERNEL);
1da177e4
LT		 1111 if (!mem)
1112 return -ENOMEM;
1113
1114 cp->rx_ring = mem;
1115 cp->tx_ring = &cp->rx_ring[CP_RX_RING_SIZE];
1116
1da177e4
LT		 1117 return cp_init_rings(cp);
1118}
1119
1120static void cp_clean_rings (struct cp_private *cp)
1121{
3598b57b 1122 struct cp_desc *desc;
1da177e4
LT		 1123 unsigned i;
1124
1da177e4 1125 for (i = 0; i < CP_RX_RING_SIZE; i++) {
0ba894d4 1126 if (cp->rx_skb[i]) {
3598b57b 1127 desc = cp->rx_ring + i;
6cc92cdd 1128 dma_unmap_single(&cp->pdev->dev,le64_to_cpu(desc->addr),
1da177e4 1129 cp->rx_buf_sz, PCI_DMA_FROMDEVICE);
0ba894d4 1130 dev_kfree_skb(cp->rx_skb[i]);
1da177e4
LT		 1131 }
1132 }
1133
1134 for (i = 0; i < CP_TX_RING_SIZE; i++) {
48907e39
FR		 1135 if (cp->tx_skb[i]) {
1136 struct sk_buff *skb = cp->tx_skb[i];
5734418d 1137
3598b57b 1138 desc = cp->tx_ring + i;
6cc92cdd 1139 dma_unmap_single(&cp->pdev->dev,le64_to_cpu(desc->addr),
48907e39
FR		 1140 le32_to_cpu(desc->opts1) & 0xffff,
1141 PCI_DMA_TODEVICE);
3598b57b 1142 if (le32_to_cpu(desc->opts1) & LastFrag)
5734418d 1143 dev_kfree_skb(skb);
237225f7 1144 cp->dev->stats.tx_dropped++;
1da177e4
LT		 1145 }
1146 }
1147
5734418d
FR		 1148 memset(cp->rx_ring, 0, sizeof(struct cp_desc) * CP_RX_RING_SIZE);
1149 memset(cp->tx_ring, 0, sizeof(struct cp_desc) * CP_TX_RING_SIZE);
1150
0ba894d4 1151 memset(cp->rx_skb, 0, sizeof(struct sk_buff *) * CP_RX_RING_SIZE);
48907e39 1152 memset(cp->tx_skb, 0, sizeof(struct sk_buff *) * CP_TX_RING_SIZE);
1da177e4
LT		 1153}
1154
1155static void cp_free_rings (struct cp_private *cp)
1156{
1157 cp_clean_rings(cp);
6cc92cdd
JG		 1158 dma_free_coherent(&cp->pdev->dev, CP_RING_BYTES, cp->rx_ring,
1159 cp->ring_dma);
1da177e4
LT		 1160 cp->rx_ring = NULL;
1161 cp->tx_ring = NULL;
1da177e4
LT		 1162}
1163
1164static int cp_open (struct net_device *dev)
1165{
1166 struct cp_private *cp = netdev_priv(dev);
1167 int rc;
1168
1169 if (netif_msg_ifup(cp))
1170 printk(KERN_DEBUG "%s: enabling interface\n", dev->name);
1171
1172 rc = cp_alloc_rings(cp);
1173 if (rc)
1174 return rc;
1175
bea3348e
SH		 1176 napi_enable(&cp->napi);
1177
1da177e4
LT		 1178 cp_init_hw(cp);
1179
1fb9df5d 1180 rc = request_irq(dev->irq, cp_interrupt, IRQF_SHARED, dev->name, dev);
1da177e4
LT		 1181 if (rc)
1182 goto err_out_hw;
1183
1184 netif_carrier_off(dev);
2501f843 1185 mii_check_media(&cp->mii_if, netif_msg_link(cp), true);
1da177e4
LT		 1186 netif_start_queue(dev);
1187
1188 return 0;
1189
1190err_out_hw:
bea3348e 1191 napi_disable(&cp->napi);
1da177e4
LT		 1192 cp_stop_hw(cp);
1193 cp_free_rings(cp);
1194 return rc;
1195}
1196
1197static int cp_close (struct net_device *dev)
1198{
1199 struct cp_private *cp = netdev_priv(dev);
1200 unsigned long flags;
1201
bea3348e
SH		 1202 napi_disable(&cp->napi);
1203
1da177e4
LT		 1204 if (netif_msg_ifdown(cp))
1205 printk(KERN_DEBUG "%s: disabling interface\n", dev->name);
1206
1207 spin_lock_irqsave(&cp->lock, flags);
1208
1209 netif_stop_queue(dev);
1210 netif_carrier_off(dev);
1211
1212 cp_stop_hw(cp);
1213
1214 spin_unlock_irqrestore(&cp->lock, flags);
1215
1da177e4
LT		 1216 free_irq(dev->irq, dev);
1217
1218 cp_free_rings(cp);
1219 return 0;
1220}
1221
9030c0d2
FR		 1222static void cp_tx_timeout(struct net_device *dev)
1223{
1224 struct cp_private *cp = netdev_priv(dev);
1225 unsigned long flags;
1226 int rc;
1227
1228 printk(KERN_WARNING "%s: Transmit timeout, status %2x %4x %4x %4x\n",
1229 dev->name, cpr8(Cmd), cpr16(CpCmd),
1230 cpr16(IntrStatus), cpr16(IntrMask));
1231
1232 spin_lock_irqsave(&cp->lock, flags);
1233
1234 cp_stop_hw(cp);
1235 cp_clean_rings(cp);
1236 rc = cp_init_rings(cp);
1237 cp_start_hw(cp);
1238
1239 netif_wake_queue(dev);
1240
1241 spin_unlock_irqrestore(&cp->lock, flags);
1242
1243 return;
1244}
1245
1da177e4
LT		 1246#ifdef BROKEN
1247static int cp_change_mtu(struct net_device *dev, int new_mtu)
1248{
1249 struct cp_private *cp = netdev_priv(dev);
1250 int rc;
1251 unsigned long flags;
1252
1253 /* check for invalid MTU, according to hardware limits */
1254 if (new_mtu < CP_MIN_MTU || new_mtu > CP_MAX_MTU)
1255 return -EINVAL;
1256
1257 /* if network interface not up, no need for complexity */
1258 if (!netif_running(dev)) {
1259 dev->mtu = new_mtu;
1260 cp_set_rxbufsize(cp); /* set new rx buf size */
1261 return 0;
1262 }
1263
1264 spin_lock_irqsave(&cp->lock, flags);
1265
1266 cp_stop_hw(cp); /* stop h/w and free rings */
1267 cp_clean_rings(cp);
1268
1269 dev->mtu = new_mtu;
1270 cp_set_rxbufsize(cp); /* set new rx buf size */
1271
1272 rc = cp_init_rings(cp); /* realloc and restart h/w */
1273 cp_start_hw(cp);
1274
1275 spin_unlock_irqrestore(&cp->lock, flags);
1276
1277 return rc;
1278}
1279#endif /* BROKEN */
1280
f71e1309 1281static const char mii_2_8139_map[8] = {
1da177e4
LT		 1282 BasicModeCtrl,
1283 BasicModeStatus,
1284 0,
1285 0,
1286 NWayAdvert,
1287 NWayLPAR,
1288 NWayExpansion,
1289 0
1290};
1291
1292static int mdio_read(struct net_device *dev, int phy_id, int location)
1293{
1294 struct cp_private *cp = netdev_priv(dev);
1295
1296 return location < 8 && mii_2_8139_map[location] ?
1297 readw(cp->regs + mii_2_8139_map[location]) : 0;
1298}
1299
1300
1301static void mdio_write(struct net_device *dev, int phy_id, int location,
1302 int value)
1303{
1304 struct cp_private *cp = netdev_priv(dev);
1305
1306 if (location == 0) {
1307 cpw8(Cfg9346, Cfg9346_Unlock);
1308 cpw16(BasicModeCtrl, value);
1309 cpw8(Cfg9346, Cfg9346_Lock);
1310 } else if (location < 8 && mii_2_8139_map[location])
1311 cpw16(mii_2_8139_map[location], value);
1312}
1313
1314/* Set the ethtool Wake-on-LAN settings */
1315static int netdev_set_wol (struct cp_private *cp,
1316 const struct ethtool_wolinfo *wol)
1317{
1318 u8 options;
1319
1320 options = cpr8 (Config3) & ~(LinkUp | MagicPacket);
1321 /* If WOL is being disabled, no need for complexity */
1322 if (wol->wolopts) {
1323 if (wol->wolopts & WAKE_PHY) options |= LinkUp;
1324 if (wol->wolopts & WAKE_MAGIC) options |= MagicPacket;
1325 }
1326
1327 cpw8 (Cfg9346, Cfg9346_Unlock);
1328 cpw8 (Config3, options);
1329 cpw8 (Cfg9346, Cfg9346_Lock);
1330
1331 options = 0; /* Paranoia setting */
1332 options = cpr8 (Config5) & ~(UWF | MWF | BWF);
1333 /* If WOL is being disabled, no need for complexity */
1334 if (wol->wolopts) {
1335 if (wol->wolopts & WAKE_UCAST) options |= UWF;
1336 if (wol->wolopts & WAKE_BCAST) options |= BWF;
1337 if (wol->wolopts & WAKE_MCAST) options |= MWF;
1338 }
1339
1340 cpw8 (Config5, options);
1341
1342 cp->wol_enabled = (wol->wolopts) ? 1 : 0;
1343
1344 return 0;
1345}
1346
1347/* Get the ethtool Wake-on-LAN settings */
1348static void netdev_get_wol (struct cp_private *cp,
1349 struct ethtool_wolinfo *wol)
1350{
1351 u8 options;
1352
1353 wol->wolopts = 0; /* Start from scratch */
1354 wol->supported = WAKE_PHY | WAKE_BCAST | WAKE_MAGIC |
1355 WAKE_MCAST | WAKE_UCAST;
1356 /* We don't need to go on if WOL is disabled */
1357 if (!cp->wol_enabled) return;
f3b197ac 1358
1da177e4
LT		 1359 options = cpr8 (Config3);
1360 if (options & LinkUp) wol->wolopts |= WAKE_PHY;
1361 if (options & MagicPacket) wol->wolopts |= WAKE_MAGIC;
1362
1363 options = 0; /* Paranoia setting */
1364 options = cpr8 (Config5);
1365 if (options & UWF) wol->wolopts |= WAKE_UCAST;
1366 if (options & BWF) wol->wolopts |= WAKE_BCAST;
1367 if (options & MWF) wol->wolopts |= WAKE_MCAST;
1368}
1369
1370static void cp_get_drvinfo (struct net_device *dev, struct ethtool_drvinfo *info)
1371{
1372 struct cp_private *cp = netdev_priv(dev);
1373
1374 strcpy (info->driver, DRV_NAME);
1375 strcpy (info->version, DRV_VERSION);
1376 strcpy (info->bus_info, pci_name(cp->pdev));
1377}
1378
1379static int cp_get_regs_len(struct net_device *dev)
1380{
1381 return CP_REGS_SIZE;
1382}
1383
b9f2c044 1384static int cp_get_sset_count (struct net_device *dev, int sset)
1da177e4 1385{
b9f2c044
JG		 1386 switch (sset) {
1387 case ETH_SS_STATS:
1388 return CP_NUM_STATS;
1389 default:
1390 return -EOPNOTSUPP;
1391 }
1da177e4
LT		 1392}
1393
1394static int cp_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1395{
1396 struct cp_private *cp = netdev_priv(dev);
1397 int rc;
1398 unsigned long flags;
1399
1400 spin_lock_irqsave(&cp->lock, flags);
1401 rc = mii_ethtool_gset(&cp->mii_if, cmd);
1402 spin_unlock_irqrestore(&cp->lock, flags);
1403
1404 return rc;
1405}
1406
1407static int cp_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1408{
1409 struct cp_private *cp = netdev_priv(dev);
1410 int rc;
1411 unsigned long flags;
1412
1413 spin_lock_irqsave(&cp->lock, flags);
1414 rc = mii_ethtool_sset(&cp->mii_if, cmd);
1415 spin_unlock_irqrestore(&cp->lock, flags);
1416
1417 return rc;
1418}
1419
1420static int cp_nway_reset(struct net_device *dev)
1421{
1422 struct cp_private *cp = netdev_priv(dev);
1423 return mii_nway_restart(&cp->mii_if);
1424}
1425
1426static u32 cp_get_msglevel(struct net_device *dev)
1427{
1428 struct cp_private *cp = netdev_priv(dev);
1429 return cp->msg_enable;
1430}
1431
1432static void cp_set_msglevel(struct net_device *dev, u32 value)
1433{
1434 struct cp_private *cp = netdev_priv(dev);
1435 cp->msg_enable = value;
1436}
1437
1438static u32 cp_get_rx_csum(struct net_device *dev)
1439{
1440 struct cp_private *cp = netdev_priv(dev);
1441 return (cpr16(CpCmd) & RxChkSum) ? 1 : 0;
1442}
1443
1444static int cp_set_rx_csum(struct net_device *dev, u32 data)
1445{
1446 struct cp_private *cp = netdev_priv(dev);
1447 u16 cmd = cp->cpcmd, newcmd;
1448
1449 newcmd = cmd;
1450
1451 if (data)
1452 newcmd |= RxChkSum;
1453 else
1454 newcmd &= ~RxChkSum;
1455
1456 if (newcmd != cmd) {
1457 unsigned long flags;
1458
1459 spin_lock_irqsave(&cp->lock, flags);
1460 cp->cpcmd = newcmd;
1461 cpw16_f(CpCmd, newcmd);
1462 spin_unlock_irqrestore(&cp->lock, flags);
1463 }
1464
1465 return 0;
1466}
1467
1468static void cp_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1469 void *p)
1470{
1471 struct cp_private *cp = netdev_priv(dev);
1472 unsigned long flags;
1473
1474 if (regs->len < CP_REGS_SIZE)
1475 return /* -EINVAL */;
1476
1477 regs->version = CP_REGS_VER;
1478
1479 spin_lock_irqsave(&cp->lock, flags);
1480 memcpy_fromio(p, cp->regs, CP_REGS_SIZE);
1481 spin_unlock_irqrestore(&cp->lock, flags);
1482}
1483
1484static void cp_get_wol (struct net_device *dev, struct ethtool_wolinfo *wol)
1485{
1486 struct cp_private *cp = netdev_priv(dev);
1487 unsigned long flags;
1488
1489 spin_lock_irqsave (&cp->lock, flags);
1490 netdev_get_wol (cp, wol);
1491 spin_unlock_irqrestore (&cp->lock, flags);
1492}
1493
1494static int cp_set_wol (struct net_device *dev, struct ethtool_wolinfo *wol)
1495{
1496 struct cp_private *cp = netdev_priv(dev);
1497 unsigned long flags;
1498 int rc;
1499
1500 spin_lock_irqsave (&cp->lock, flags);
1501 rc = netdev_set_wol (cp, wol);
1502 spin_unlock_irqrestore (&cp->lock, flags);
1503
1504 return rc;
1505}
1506
1507static void cp_get_strings (struct net_device *dev, u32 stringset, u8 *buf)
1508{
1509 switch (stringset) {
1510 case ETH_SS_STATS:
1511 memcpy(buf, &ethtool_stats_keys, sizeof(ethtool_stats_keys));
1512 break;
1513 default:
1514 BUG();
1515 break;
1516 }
1517}
1518
1519static void cp_get_ethtool_stats (struct net_device *dev,
1520 struct ethtool_stats *estats, u64 *tmp_stats)
1521{
1522 struct cp_private *cp = netdev_priv(dev);
8b512927
SH		 1523 struct cp_dma_stats *nic_stats;
1524 dma_addr_t dma;
1da177e4
LT		 1525 int i;
1526
6cc92cdd
JG		 1527 nic_stats = dma_alloc_coherent(&cp->pdev->dev, sizeof(*nic_stats),
1528 &dma, GFP_KERNEL);
8b512927
SH		 1529 if (!nic_stats)
1530 return;
97f568d8 1531
1da177e4 1532 /* begin NIC statistics dump */
8b512927
SH		 1533 cpw32(StatsAddr + 4, (u64)dma >> 32);
1534 cpw32(StatsAddr, ((u64)dma & DMA_32BIT_MASK) | DumpStats);
1da177e4
LT		 1535 cpr32(StatsAddr);
1536
97f568d8 1537 for (i = 0; i < 1000; i++) {
1da177e4
LT		 1538 if ((cpr32(StatsAddr) & DumpStats) == 0)
1539 break;
97f568d8 1540 udelay(10);
1da177e4 1541 }
97f568d8
SH		 1542 cpw32(StatsAddr, 0);
1543 cpw32(StatsAddr + 4, 0);
8b512927 1544 cpr32(StatsAddr);
1da177e4
LT		 1545
1546 i = 0;
8b512927
SH		 1547 tmp_stats[i++] = le64_to_cpu(nic_stats->tx_ok);
1548 tmp_stats[i++] = le64_to_cpu(nic_stats->rx_ok);
1549 tmp_stats[i++] = le64_to_cpu(nic_stats->tx_err);
1550 tmp_stats[i++] = le32_to_cpu(nic_stats->rx_err);
1551 tmp_stats[i++] = le16_to_cpu(nic_stats->rx_fifo);
1552 tmp_stats[i++] = le16_to_cpu(nic_stats->frame_align);
1553 tmp_stats[i++] = le32_to_cpu(nic_stats->tx_ok_1col);
1554 tmp_stats[i++] = le32_to_cpu(nic_stats->tx_ok_mcol);
1555 tmp_stats[i++] = le64_to_cpu(nic_stats->rx_ok_phys);
1556 tmp_stats[i++] = le64_to_cpu(nic_stats->rx_ok_bcast);
1557 tmp_stats[i++] = le32_to_cpu(nic_stats->rx_ok_mcast);
1558 tmp_stats[i++] = le16_to_cpu(nic_stats->tx_abort);
1559 tmp_stats[i++] = le16_to_cpu(nic_stats->tx_underrun);
1da177e4 1560 tmp_stats[i++] = cp->cp_stats.rx_frags;
5d9428de 1561 BUG_ON(i != CP_NUM_STATS);
8b512927 1562
6cc92cdd 1563 dma_free_coherent(&cp->pdev->dev, sizeof(*nic_stats), nic_stats, dma);
1da177e4
LT		 1564}
1565
7282d491 1566static const struct ethtool_ops cp_ethtool_ops = {
1da177e4
LT		 1567 .get_drvinfo = cp_get_drvinfo,
1568 .get_regs_len = cp_get_regs_len,
b9f2c044 1569 .get_sset_count = cp_get_sset_count,
1da177e4
LT		 1570 .get_settings = cp_get_settings,
1571 .set_settings = cp_set_settings,
1572 .nway_reset = cp_nway_reset,
1573 .get_link = ethtool_op_get_link,
1574 .get_msglevel = cp_get_msglevel,
1575 .set_msglevel = cp_set_msglevel,
1576 .get_rx_csum = cp_get_rx_csum,
1577 .set_rx_csum = cp_set_rx_csum,
1da177e4 1578 .set_tx_csum = ethtool_op_set_tx_csum, /* local! */
1da177e4 1579 .set_sg = ethtool_op_set_sg,
fcec3456 1580 .set_tso = ethtool_op_set_tso,
1da177e4
LT		 1581 .get_regs = cp_get_regs,
1582 .get_wol = cp_get_wol,
1583 .set_wol = cp_set_wol,
1584 .get_strings = cp_get_strings,
1585 .get_ethtool_stats = cp_get_ethtool_stats,
722fdb33
PC		 1586 .get_eeprom_len = cp_get_eeprom_len,
1587 .get_eeprom = cp_get_eeprom,
1588 .set_eeprom = cp_set_eeprom,
1da177e4
LT		 1589};
1590
1591static int cp_ioctl (struct net_device *dev, struct ifreq *rq, int cmd)
1592{
1593 struct cp_private *cp = netdev_priv(dev);
1594 int rc;
1595 unsigned long flags;
1596
1597 if (!netif_running(dev))
1598 return -EINVAL;
1599
1600 spin_lock_irqsave(&cp->lock, flags);
1601 rc = generic_mii_ioctl(&cp->mii_if, if_mii(rq), cmd, NULL);
1602 spin_unlock_irqrestore(&cp->lock, flags);
1603 return rc;
1604}
1605
1606/* Serial EEPROM section. */
1607
1608/* EEPROM_Ctrl bits. */
1609#define EE_SHIFT_CLK 0x04 /* EEPROM shift clock. */
1610#define EE_CS 0x08 /* EEPROM chip select. */
1611#define EE_DATA_WRITE 0x02 /* EEPROM chip data in. */
1612#define EE_WRITE_0 0x00
1613#define EE_WRITE_1 0x02
1614#define EE_DATA_READ 0x01 /* EEPROM chip data out. */
1615#define EE_ENB (0x80 | EE_CS)
1616
1617/* Delay between EEPROM clock transitions.
1618 No extra delay is needed with 33Mhz PCI, but 66Mhz may change this.
1619 */
1620
1621#define eeprom_delay() readl(ee_addr)
1622
1623/* The EEPROM commands include the alway-set leading bit. */
722fdb33 1624#define EE_EXTEND_CMD (4)
1da177e4
LT		 1625#define EE_WRITE_CMD (5)
1626#define EE_READ_CMD (6)
1627#define EE_ERASE_CMD (7)
1628
722fdb33
PC		 1629#define EE_EWDS_ADDR (0)
1630#define EE_WRAL_ADDR (1)
1631#define EE_ERAL_ADDR (2)
1632#define EE_EWEN_ADDR (3)
1633
1634#define CP_EEPROM_MAGIC PCI_DEVICE_ID_REALTEK_8139
1da177e4 1635
722fdb33
PC		 1636static void eeprom_cmd_start(void __iomem *ee_addr)
1637{
1da177e4
LT		 1638 writeb (EE_ENB & ~EE_CS, ee_addr);
1639 writeb (EE_ENB, ee_addr);
1640 eeprom_delay ();
722fdb33 1641}
1da177e4 1642
722fdb33
PC		 1643static void eeprom_cmd(void __iomem *ee_addr, int cmd, int cmd_len)
1644{
1645 int i;
1646
1647 /* Shift the command bits out. */
1648 for (i = cmd_len - 1; i >= 0; i--) {
1649 int dataval = (cmd & (1 << i)) ? EE_DATA_WRITE : 0;
1da177e4
LT		 1650 writeb (EE_ENB | dataval, ee_addr);
1651 eeprom_delay ();
1652 writeb (EE_ENB | dataval | EE_SHIFT_CLK, ee_addr);
1653 eeprom_delay ();
1654 }
1655 writeb (EE_ENB, ee_addr);
1656 eeprom_delay ();
722fdb33
PC		 1657}
1658
1659static void eeprom_cmd_end(void __iomem *ee_addr)
1660{
1661 writeb (~EE_CS, ee_addr);
1662 eeprom_delay ();
1663}
1664
1665static void eeprom_extend_cmd(void __iomem *ee_addr, int extend_cmd,
1666 int addr_len)
1667{
1668 int cmd = (EE_EXTEND_CMD << addr_len) | (extend_cmd << (addr_len - 2));
1669
1670 eeprom_cmd_start(ee_addr);
1671 eeprom_cmd(ee_addr, cmd, 3 + addr_len);
1672 eeprom_cmd_end(ee_addr);
1673}
1674
1675static u16 read_eeprom (void __iomem *ioaddr, int location, int addr_len)
1676{
1677 int i;
1678 u16 retval = 0;
1679 void __iomem *ee_addr = ioaddr + Cfg9346;
1680 int read_cmd = location | (EE_READ_CMD << addr_len);
1681
1682 eeprom_cmd_start(ee_addr);
1683 eeprom_cmd(ee_addr, read_cmd, 3 + addr_len);
1da177e4
LT		 1684
1685 for (i = 16; i > 0; i--) {
1686 writeb (EE_ENB | EE_SHIFT_CLK, ee_addr);
1687 eeprom_delay ();
1688 retval =
1689 (retval << 1) | ((readb (ee_addr) & EE_DATA_READ) ? 1 :
1690 0);
1691 writeb (EE_ENB, ee_addr);
1692 eeprom_delay ();
1693 }
1694
722fdb33 1695 eeprom_cmd_end(ee_addr);
1da177e4
LT		 1696
1697 return retval;
1698}
1699
722fdb33
PC		 1700static void write_eeprom(void __iomem *ioaddr, int location, u16 val,
1701 int addr_len)
1702{
1703 int i;
1704 void __iomem *ee_addr = ioaddr + Cfg9346;
1705 int write_cmd = location | (EE_WRITE_CMD << addr_len);
1706
1707 eeprom_extend_cmd(ee_addr, EE_EWEN_ADDR, addr_len);
1708
1709 eeprom_cmd_start(ee_addr);
1710 eeprom_cmd(ee_addr, write_cmd, 3 + addr_len);
1711 eeprom_cmd(ee_addr, val, 16);
1712 eeprom_cmd_end(ee_addr);
1713
1714 eeprom_cmd_start(ee_addr);
1715 for (i = 0; i < 20000; i++)
1716 if (readb(ee_addr) & EE_DATA_READ)
1717 break;
1718 eeprom_cmd_end(ee_addr);
1719
1720 eeprom_extend_cmd(ee_addr, EE_EWDS_ADDR, addr_len);
1721}
1722
1723static int cp_get_eeprom_len(struct net_device *dev)
1724{
1725 struct cp_private *cp = netdev_priv(dev);
1726 int size;
1727
1728 spin_lock_irq(&cp->lock);
1729 size = read_eeprom(cp->regs, 0, 8) == 0x8129 ? 256 : 128;
1730 spin_unlock_irq(&cp->lock);
1731
1732 return size;
1733}
1734
1735static int cp_get_eeprom(struct net_device *dev,
1736 struct ethtool_eeprom *eeprom, u8 *data)
1737{
1738 struct cp_private *cp = netdev_priv(dev);
1739 unsigned int addr_len;
1740 u16 val;
1741 u32 offset = eeprom->offset >> 1;
1742 u32 len = eeprom->len;
1743 u32 i = 0;
1744
1745 eeprom->magic = CP_EEPROM_MAGIC;
1746
1747 spin_lock_irq(&cp->lock);
1748
1749 addr_len = read_eeprom(cp->regs, 0, 8) == 0x8129 ? 8 : 6;
1750
1751 if (eeprom->offset & 1) {
1752 val = read_eeprom(cp->regs, offset, addr_len);
1753 data[i++] = (u8)(val >> 8);
1754 offset++;
1755 }
1756
1757 while (i < len - 1) {
1758 val = read_eeprom(cp->regs, offset, addr_len);
1759 data[i++] = (u8)val;
1760 data[i++] = (u8)(val >> 8);
1761 offset++;
1762 }
1763
1764 if (i < len) {
1765 val = read_eeprom(cp->regs, offset, addr_len);
1766 data[i] = (u8)val;
1767 }
1768
1769 spin_unlock_irq(&cp->lock);
1770 return 0;
1771}
1772
1773static int cp_set_eeprom(struct net_device *dev,
1774 struct ethtool_eeprom *eeprom, u8 *data)
1775{
1776 struct cp_private *cp = netdev_priv(dev);
1777 unsigned int addr_len;
1778 u16 val;
1779 u32 offset = eeprom->offset >> 1;
1780 u32 len = eeprom->len;
1781 u32 i = 0;
1782
1783 if (eeprom->magic != CP_EEPROM_MAGIC)
1784 return -EINVAL;
1785
1786 spin_lock_irq(&cp->lock);
1787
1788 addr_len = read_eeprom(cp->regs, 0, 8) == 0x8129 ? 8 : 6;
1789
1790 if (eeprom->offset & 1) {
1791 val = read_eeprom(cp->regs, offset, addr_len) & 0xff;
1792 val |= (u16)data[i++] << 8;
1793 write_eeprom(cp->regs, offset, val, addr_len);
1794 offset++;
1795 }
1796
1797 while (i < len - 1) {
1798 val = (u16)data[i++];
1799 val |= (u16)data[i++] << 8;
1800 write_eeprom(cp->regs, offset, val, addr_len);
1801 offset++;
1802 }
1803
1804 if (i < len) {
1805 val = read_eeprom(cp->regs, offset, addr_len) & 0xff00;
1806 val |= (u16)data[i];
1807 write_eeprom(cp->regs, offset, val, addr_len);
1808 }
1809
1810 spin_unlock_irq(&cp->lock);
1811 return 0;
1812}
1813
1da177e4
LT		 1814/* Put the board into D3cold state and wait for WakeUp signal */
1815static void cp_set_d3_state (struct cp_private *cp)
1816{
1817 pci_enable_wake (cp->pdev, 0, 1); /* Enable PME# generation */
1818 pci_set_power_state (cp->pdev, PCI_D3hot);
1819}
1820
1821static int cp_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
1822{
1823 struct net_device *dev;
1824 struct cp_private *cp;
1825 int rc;
1826 void __iomem *regs;
2427ddd8 1827 resource_size_t pciaddr;
1da177e4 1828 unsigned int addr_len, i, pci_using_dac;
0795af57 1829 DECLARE_MAC_BUF(mac);
1da177e4
LT		 1830
1831#ifndef MODULE
1832 static int version_printed;
1833 if (version_printed++ == 0)
1834 printk("%s", version);
1835#endif
1836
1da177e4 1837 if (pdev->vendor == PCI_VENDOR_ID_REALTEK &&
44c10138 1838 pdev->device == PCI_DEVICE_ID_REALTEK_8139 && pdev->revision < 0x20) {
9b91cf9d 1839 dev_err(&pdev->dev,
2e8a538d 1840 "This (id %04x:%04x rev %02x) is not an 8139C+ compatible chip\n",
44c10138 1841 pdev->vendor, pdev->device, pdev->revision);
9b91cf9d 1842 dev_err(&pdev->dev, "Try the \"8139too\" driver instead.\n");
1da177e4
LT		 1843 return -ENODEV;
1844 }
1845
1846 dev = alloc_etherdev(sizeof(struct cp_private));
1847 if (!dev)
1848 return -ENOMEM;
1da177e4
LT		 1849 SET_NETDEV_DEV(dev, &pdev->dev);
1850
1851 cp = netdev_priv(dev);
1852 cp->pdev = pdev;
1853 cp->dev = dev;
1854 cp->msg_enable = (debug < 0 ? CP_DEF_MSG_ENABLE : debug);
1855 spin_lock_init (&cp->lock);
1856 cp->mii_if.dev = dev;
1857 cp->mii_if.mdio_read = mdio_read;
1858 cp->mii_if.mdio_write = mdio_write;
1859 cp->mii_if.phy_id = CP_INTERNAL_PHY;
1860 cp->mii_if.phy_id_mask = 0x1f;
1861 cp->mii_if.reg_num_mask = 0x1f;
1862 cp_set_rxbufsize(cp);
1863
1864 rc = pci_enable_device(pdev);
1865 if (rc)
1866 goto err_out_free;
1867
1868 rc = pci_set_mwi(pdev);
1869 if (rc)
1870 goto err_out_disable;
1871
1872 rc = pci_request_regions(pdev, DRV_NAME);
1873 if (rc)
1874 goto err_out_mwi;
1875
1876 pciaddr = pci_resource_start(pdev, 1);
1877 if (!pciaddr) {
1878 rc = -EIO;
9b91cf9d 1879 dev_err(&pdev->dev, "no MMIO resource\n");
1da177e4
LT		 1880 goto err_out_res;
1881 }
1882 if (pci_resource_len(pdev, 1) < CP_REGS_SIZE) {
1883 rc = -EIO;
9b91cf9d 1884 dev_err(&pdev->dev, "MMIO resource (%llx) too small\n",
2e8a538d 1885 (unsigned long long)pci_resource_len(pdev, 1));
1da177e4
LT		 1886 goto err_out_res;
1887 }
1888
1889 /* Configure DMA attributes. */
1890 if ((sizeof(dma_addr_t) > 4) &&
8662d061
TK		 1891 !pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK) &&
1892 !pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
1da177e4
LT		 1893 pci_using_dac = 1;
1894 } else {
1895 pci_using_dac = 0;
1896
8662d061 1897 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
1da177e4 1898 if (rc) {
9b91cf9d 1899 dev_err(&pdev->dev,
2e8a538d 1900 "No usable DMA configuration, aborting.\n");
1da177e4
LT		 1901 goto err_out_res;
1902 }
8662d061 1903 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
1da177e4 1904 if (rc) {
9b91cf9d 1905 dev_err(&pdev->dev,
2e8a538d
JG		 1906 "No usable consistent DMA configuration, "
1907 "aborting.\n");
1da177e4
LT		 1908 goto err_out_res;
1909 }
1910 }
1911
1912 cp->cpcmd = (pci_using_dac ? PCIDAC : 0) |
1913 PCIMulRW | RxChkSum | CpRxOn | CpTxOn;
1914
1915 regs = ioremap(pciaddr, CP_REGS_SIZE);
1916 if (!regs) {
1917 rc = -EIO;
4626dd46 1918 dev_err(&pdev->dev, "Cannot map PCI MMIO (%Lx@%Lx)\n",
2e8a538d
JG		 1919 (unsigned long long)pci_resource_len(pdev, 1),
1920 (unsigned long long)pciaddr);
1da177e4
LT		 1921 goto err_out_res;
1922 }
1923 dev->base_addr = (unsigned long) regs;
1924 cp->regs = regs;
1925
1926 cp_stop_hw(cp);
1927
1928 /* read MAC address from EEPROM */
1929 addr_len = read_eeprom (regs, 0, 8) == 0x8129 ? 8 : 6;
1930 for (i = 0; i < 3; i++)
03233b90
AV		 1931 ((__le16 *) (dev->dev_addr))[i] =
1932 cpu_to_le16(read_eeprom (regs, i + 7, addr_len));
bb0ce608 1933 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
1da177e4
LT		 1934
1935 dev->open = cp_open;
1936 dev->stop = cp_close;
1937 dev->set_multicast_list = cp_set_rx_mode;
1938 dev->hard_start_xmit = cp_start_xmit;
1939 dev->get_stats = cp_get_stats;
1940 dev->do_ioctl = cp_ioctl;
7502cd10
SK		 1941#ifdef CONFIG_NET_POLL_CONTROLLER
1942 dev->poll_controller = cp_poll_controller;
1943#endif
bea3348e 1944 netif_napi_add(dev, &cp->napi, cp_rx_poll, 16);
1da177e4
LT		 1945#ifdef BROKEN
1946 dev->change_mtu = cp_change_mtu;
1947#endif
1948 dev->ethtool_ops = &cp_ethtool_ops;
1da177e4
LT		 1949 dev->tx_timeout = cp_tx_timeout;
1950 dev->watchdog_timeo = TX_TIMEOUT;
1da177e4
LT		 1951
1952#if CP_VLAN_TAG_USED
1953 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
1954 dev->vlan_rx_register = cp_vlan_rx_register;
1da177e4
LT		 1955#endif
1956
1957 if (pci_using_dac)
1958 dev->features |= NETIF_F_HIGHDMA;
1959
fcec3456
JG		 1960#if 0 /* disabled by default until verified */
1961 dev->features |= NETIF_F_TSO;
1962#endif
1963
1da177e4
LT		 1964 dev->irq = pdev->irq;
1965
1966 rc = register_netdev(dev);
1967 if (rc)
1968 goto err_out_iomap;
1969
1970 printk (KERN_INFO "%s: RTL-8139C+ at 0x%lx, "
0795af57 1971 "%s, IRQ %d\n",
1da177e4
LT		 1972 dev->name,
1973 dev->base_addr,
0795af57 1974 print_mac(mac, dev->dev_addr),
1da177e4
LT		 1975 dev->irq);
1976
1977 pci_set_drvdata(pdev, dev);
1978
1979 /* enable busmastering and memory-write-invalidate */
1980 pci_set_master(pdev);
1981
2e8a538d
JG		 1982 if (cp->wol_enabled)
1983 cp_set_d3_state (cp);
1da177e4
LT		 1984
1985 return 0;
1986
1987err_out_iomap:
1988 iounmap(regs);
1989err_out_res:
1990 pci_release_regions(pdev);
1991err_out_mwi:
1992 pci_clear_mwi(pdev);
1993err_out_disable:
1994 pci_disable_device(pdev);
1995err_out_free:
1996 free_netdev(dev);
1997 return rc;
1998}
1999
2000static void cp_remove_one (struct pci_dev *pdev)
2001{
2002 struct net_device *dev = pci_get_drvdata(pdev);
2003 struct cp_private *cp = netdev_priv(dev);
2004
1da177e4
LT		 2005 unregister_netdev(dev);
2006 iounmap(cp->regs);
2e8a538d
JG		 2007 if (cp->wol_enabled)
2008 pci_set_power_state (pdev, PCI_D0);
1da177e4
LT		 2009 pci_release_regions(pdev);
2010 pci_clear_mwi(pdev);
2011 pci_disable_device(pdev);
2012 pci_set_drvdata(pdev, NULL);
2013 free_netdev(dev);
2014}
2015
2016#ifdef CONFIG_PM
05adc3b7 2017static int cp_suspend (struct pci_dev *pdev, pm_message_t state)
1da177e4 2018{
7668a494
FR		 2019 struct net_device *dev = pci_get_drvdata(pdev);
2020 struct cp_private *cp = netdev_priv(dev);
1da177e4
LT		 2021 unsigned long flags;
2022
7668a494
FR		 2023 if (!netif_running(dev))
2024 return 0;
1da177e4
LT		 2025
2026 netif_device_detach (dev);
2027 netif_stop_queue (dev);
2028
2029 spin_lock_irqsave (&cp->lock, flags);
2030
2031 /* Disable Rx and Tx */
2032 cpw16 (IntrMask, 0);
2033 cpw8 (Cmd, cpr8 (Cmd) & (~RxOn | ~TxOn));
2034
2035 spin_unlock_irqrestore (&cp->lock, flags);
2036
576cfa93
FR		 2037 pci_save_state(pdev);
2038 pci_enable_wake(pdev, pci_choose_state(pdev, state), cp->wol_enabled);
2039 pci_set_power_state(pdev, pci_choose_state(pdev, state));
1da177e4
LT		 2040
2041 return 0;
2042}
2043
2044static int cp_resume (struct pci_dev *pdev)
2045{
576cfa93
FR		 2046 struct net_device *dev = pci_get_drvdata (pdev);
2047 struct cp_private *cp = netdev_priv(dev);
a4cf0761 2048 unsigned long flags;
1da177e4 2049
576cfa93
FR		 2050 if (!netif_running(dev))
2051 return 0;
1da177e4
LT		 2052
2053 netif_device_attach (dev);
576cfa93
FR		 2054
2055 pci_set_power_state(pdev, PCI_D0);
2056 pci_restore_state(pdev);
2057 pci_enable_wake(pdev, PCI_D0, 0);
2058
2059 /* FIXME: sh*t may happen if the Rx ring buffer is depleted */
2060 cp_init_rings_index (cp);
1da177e4
LT		 2061 cp_init_hw (cp);
2062 netif_start_queue (dev);
a4cf0761
PO		 2063
2064 spin_lock_irqsave (&cp->lock, flags);
2065
2501f843 2066 mii_check_media(&cp->mii_if, netif_msg_link(cp), false);
a4cf0761
PO		 2067
2068 spin_unlock_irqrestore (&cp->lock, flags);
f3b197ac 2069
1da177e4
LT		 2070 return 0;
2071}
2072#endif /* CONFIG_PM */
2073
2074static struct pci_driver cp_driver = {
2075 .name = DRV_NAME,
2076 .id_table = cp_pci_tbl,
2077 .probe = cp_init_one,
2078 .remove = cp_remove_one,
2079#ifdef CONFIG_PM
2080 .resume = cp_resume,
2081 .suspend = cp_suspend,
2082#endif
2083};
2084
2085static int __init cp_init (void)
2086{
2087#ifdef MODULE
2088 printk("%s", version);
2089#endif
29917620 2090 return pci_register_driver(&cp_driver);
1da177e4
LT		 2091}
2092
2093static void __exit cp_exit (void)
2094{
2095 pci_unregister_driver (&cp_driver);
2096}
2097
2098module_init(cp_init);
2099module_exit(cp_exit);
Linux kernel - Deliverables
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