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signals: consolidate checks for whether or not to ignore a signal
[deliverable/linux.git] / drivers / net / acenic.c
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1da177e4
LT		 1/*
2 * acenic.c: Linux driver for the Alteon AceNIC Gigabit Ethernet card
3 * and other Tigon based cards.
4 *
5 * Copyright 1998-2002 by Jes Sorensen, <jes@trained-monkey.org>.
6 *
7 * Thanks to Alteon and 3Com for providing hardware and documentation
8 * enabling me to write this driver.
9 *
10 * A mailing list for discussing the use of this driver has been
11 * setup, please subscribe to the lists if you have any questions
12 * about the driver. Send mail to linux-acenic-help@sunsite.auc.dk to
13 * see how to subscribe.
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License as published by
17 * the Free Software Foundation; either version 2 of the License, or
18 * (at your option) any later version.
19 *
20 * Additional credits:
21 * Pete Wyckoff <wyckoff@ca.sandia.gov>: Initial Linux/Alpha and trace
22 * dump support. The trace dump support has not been
23 * integrated yet however.
24 * Troy Benjegerdes: Big Endian (PPC) patches.
25 * Nate Stahl: Better out of memory handling and stats support.
26 * Aman Singla: Nasty race between interrupt handler and tx code dealing
27 * with 'testing the tx_ret_csm and setting tx_full'
28 * David S. Miller <davem@redhat.com>: conversion to new PCI dma mapping
29 * infrastructure and Sparc support
30 * Pierrick Pinasseau (CERN): For lending me an Ultra 5 to test the
31 * driver under Linux/Sparc64
32 * Matt Domsch <Matt_Domsch@dell.com>: Detect Alteon 1000baseT cards
33 * ETHTOOL_GDRVINFO support
34 * Chip Salzenberg <chip@valinux.com>: Fix race condition between tx
35 * handler and close() cleanup.
36 * Ken Aaker <kdaaker@rchland.vnet.ibm.com>: Correct check for whether
37 * memory mapped IO is enabled to
38 * make the driver work on RS/6000.
39 * Takayoshi Kouchi <kouchi@hpc.bs1.fc.nec.co.jp>: Identifying problem
40 * where the driver would disable
41 * bus master mode if it had to disable
42 * write and invalidate.
43 * Stephen Hack <stephen_hack@hp.com>: Fixed ace_set_mac_addr for little
44 * endian systems.
45 * Val Henson <vhenson@esscom.com>: Reset Jumbo skb producer and
46 * rx producer index when
47 * flushing the Jumbo ring.
48 * Hans Grobler <grobh@sun.ac.za>: Memory leak fixes in the
49 * driver init path.
50 * Grant Grundler <grundler@cup.hp.com>: PCI write posting fixes.
51 */
52
1da177e4
LT		 53#include <linux/module.h>
54#include <linux/moduleparam.h>
55#include <linux/version.h>
56#include <linux/types.h>
57#include <linux/errno.h>
58#include <linux/ioport.h>
59#include <linux/pci.h>
1e7f0bd8 60#include <linux/dma-mapping.h>
1da177e4
LT		 61#include <linux/kernel.h>
62#include <linux/netdevice.h>
63#include <linux/etherdevice.h>
64#include <linux/skbuff.h>
65#include <linux/init.h>
66#include <linux/delay.h>
67#include <linux/mm.h>
68#include <linux/highmem.h>
69#include <linux/sockios.h>
70
71#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
72#include <linux/if_vlan.h>
73#endif
74
75#ifdef SIOCETHTOOL
76#include <linux/ethtool.h>
77#endif
78
79#include <net/sock.h>
80#include <net/ip.h>
81
82#include <asm/system.h>
83#include <asm/io.h>
84#include <asm/irq.h>
85#include <asm/byteorder.h>
86#include <asm/uaccess.h>
87
88
89#define DRV_NAME "acenic"
90
91#undef INDEX_DEBUG
92
93#ifdef CONFIG_ACENIC_OMIT_TIGON_I
94#define ACE_IS_TIGON_I(ap) 0
95#define ACE_TX_RING_ENTRIES(ap) MAX_TX_RING_ENTRIES
96#else
97#define ACE_IS_TIGON_I(ap) (ap->version == 1)
98#define ACE_TX_RING_ENTRIES(ap) ap->tx_ring_entries
99#endif
100
101#ifndef PCI_VENDOR_ID_ALTEON
6aa20a22 102#define PCI_VENDOR_ID_ALTEON 0x12ae
1da177e4
LT		 103#endif
104#ifndef PCI_DEVICE_ID_ALTEON_ACENIC_FIBRE
105#define PCI_DEVICE_ID_ALTEON_ACENIC_FIBRE 0x0001
106#define PCI_DEVICE_ID_ALTEON_ACENIC_COPPER 0x0002
107#endif
108#ifndef PCI_DEVICE_ID_3COM_3C985
109#define PCI_DEVICE_ID_3COM_3C985 0x0001
110#endif
111#ifndef PCI_VENDOR_ID_NETGEAR
112#define PCI_VENDOR_ID_NETGEAR 0x1385
113#define PCI_DEVICE_ID_NETGEAR_GA620 0x620a
114#endif
115#ifndef PCI_DEVICE_ID_NETGEAR_GA620T
116#define PCI_DEVICE_ID_NETGEAR_GA620T 0x630a
117#endif
118
119
120/*
121 * Farallon used the DEC vendor ID by mistake and they seem not
122 * to care - stinky!
123 */
124#ifndef PCI_DEVICE_ID_FARALLON_PN9000SX
125#define PCI_DEVICE_ID_FARALLON_PN9000SX 0x1a
126#endif
127#ifndef PCI_DEVICE_ID_FARALLON_PN9100T
128#define PCI_DEVICE_ID_FARALLON_PN9100T 0xfa
129#endif
130#ifndef PCI_VENDOR_ID_SGI
131#define PCI_VENDOR_ID_SGI 0x10a9
132#endif
133#ifndef PCI_DEVICE_ID_SGI_ACENIC
134#define PCI_DEVICE_ID_SGI_ACENIC 0x0009
135#endif
136
137static struct pci_device_id acenic_pci_tbl[] = {
138 { PCI_VENDOR_ID_ALTEON, PCI_DEVICE_ID_ALTEON_ACENIC_FIBRE,
139 PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_NETWORK_ETHERNET << 8, 0xffff00, },
140 { PCI_VENDOR_ID_ALTEON, PCI_DEVICE_ID_ALTEON_ACENIC_COPPER,
141 PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_NETWORK_ETHERNET << 8, 0xffff00, },
142 { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3C985,
143 PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_NETWORK_ETHERNET << 8, 0xffff00, },
144 { PCI_VENDOR_ID_NETGEAR, PCI_DEVICE_ID_NETGEAR_GA620,
145 PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_NETWORK_ETHERNET << 8, 0xffff00, },
146 { PCI_VENDOR_ID_NETGEAR, PCI_DEVICE_ID_NETGEAR_GA620T,
147 PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_NETWORK_ETHERNET << 8, 0xffff00, },
148 /*
149 * Farallon used the DEC vendor ID on their cards incorrectly,
150 * then later Alteon's ID.
151 */
152 { PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_FARALLON_PN9000SX,
153 PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_NETWORK_ETHERNET << 8, 0xffff00, },
154 { PCI_VENDOR_ID_ALTEON, PCI_DEVICE_ID_FARALLON_PN9100T,
155 PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_NETWORK_ETHERNET << 8, 0xffff00, },
156 { PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_ACENIC,
157 PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_NETWORK_ETHERNET << 8, 0xffff00, },
158 { }
159};
160MODULE_DEVICE_TABLE(pci, acenic_pci_tbl);
161
1da177e4 162#define ace_sync_irq(irq) synchronize_irq(irq)
1da177e4
LT		 163
164#ifndef offset_in_page
165#define offset_in_page(ptr) ((unsigned long)(ptr) & ~PAGE_MASK)
166#endif
167
168#define ACE_MAX_MOD_PARMS 8
169#define BOARD_IDX_STATIC 0
170#define BOARD_IDX_OVERFLOW -1
171
172#if (defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)) && \
173 defined(NETIF_F_HW_VLAN_RX)
174#define ACENIC_DO_VLAN 1
175#define ACE_RCB_VLAN_FLAG RCB_FLG_VLAN_ASSIST
176#else
177#define ACENIC_DO_VLAN 0
178#define ACE_RCB_VLAN_FLAG 0
179#endif
180
181#include "acenic.h"
182
183/*
184 * These must be defined before the firmware is included.
185 */
186#define MAX_TEXT_LEN 96*1024
187#define MAX_RODATA_LEN 8*1024
188#define MAX_DATA_LEN 2*1024
189
190#include "acenic_firmware.h"
191
192#ifndef tigon2FwReleaseLocal
193#define tigon2FwReleaseLocal 0
194#endif
195
196/*
197 * This driver currently supports Tigon I and Tigon II based cards
198 * including the Alteon AceNIC, the 3Com 3C985[B] and NetGear
199 * GA620. The driver should also work on the SGI, DEC and Farallon
200 * versions of the card, however I have not been able to test that
201 * myself.
202 *
203 * This card is really neat, it supports receive hardware checksumming
204 * and jumbo frames (up to 9000 bytes) and does a lot of work in the
205 * firmware. Also the programming interface is quite neat, except for
206 * the parts dealing with the i2c eeprom on the card ;-)
207 *
208 * Using jumbo frames:
209 *
210 * To enable jumbo frames, simply specify an mtu between 1500 and 9000
211 * bytes to ifconfig. Jumbo frames can be enabled or disabled at any time
212 * by running `ifconfig eth<X> mtu <MTU>' with <X> being the Ethernet
213 * interface number and <MTU> being the MTU value.
214 *
215 * Module parameters:
216 *
217 * When compiled as a loadable module, the driver allows for a number
218 * of module parameters to be specified. The driver supports the
219 * following module parameters:
220 *
221 * trace=<val> - Firmware trace level. This requires special traced
222 * firmware to replace the firmware supplied with
223 * the driver - for debugging purposes only.
224 *
225 * link=<val> - Link state. Normally you want to use the default link
226 * parameters set by the driver. This can be used to
227 * override these in case your switch doesn't negotiate
228 * the link properly. Valid values are:
229 * 0x0001 - Force half duplex link.
230 * 0x0002 - Do not negotiate line speed with the other end.
231 * 0x0010 - 10Mbit/sec link.
232 * 0x0020 - 100Mbit/sec link.
233 * 0x0040 - 1000Mbit/sec link.
234 * 0x0100 - Do not negotiate flow control.
235 * 0x0200 - Enable RX flow control Y
236 * 0x0400 - Enable TX flow control Y (Tigon II NICs only).
237 * Default value is 0x0270, ie. enable link+flow
238 * control negotiation. Negotiating the highest
239 * possible link speed with RX flow control enabled.
240 *
241 * When disabling link speed negotiation, only one link
242 * speed is allowed to be specified!
243 *
244 * tx_coal_tick=<val> - number of coalescing clock ticks (us) allowed
245 * to wait for more packets to arive before
246 * interrupting the host, from the time the first
247 * packet arrives.
248 *
249 * rx_coal_tick=<val> - number of coalescing clock ticks (us) allowed
250 * to wait for more packets to arive in the transmit ring,
251 * before interrupting the host, after transmitting the
252 * first packet in the ring.
253 *
254 * max_tx_desc=<val> - maximum number of transmit descriptors
255 * (packets) transmitted before interrupting the host.
256 *
257 * max_rx_desc=<val> - maximum number of receive descriptors
258 * (packets) received before interrupting the host.
259 *
260 * tx_ratio=<val> - 7 bit value (0 - 63) specifying the split in 64th
261 * increments of the NIC's on board memory to be used for
262 * transmit and receive buffers. For the 1MB NIC app. 800KB
263 * is available, on the 1/2MB NIC app. 300KB is available.
264 * 68KB will always be available as a minimum for both
265 * directions. The default value is a 50/50 split.
266 * dis_pci_mem_inval=<val> - disable PCI memory write and invalidate
267 * operations, default (1) is to always disable this as
268 * that is what Alteon does on NT. I have not been able
269 * to measure any real performance differences with
270 * this on my systems. Set <val>=0 if you want to
271 * enable these operations.
272 *
273 * If you use more than one NIC, specify the parameters for the
274 * individual NICs with a comma, ie. trace=0,0x00001fff,0 you want to
275 * run tracing on NIC #2 but not on NIC #1 and #3.
276 *
277 * TODO:
278 *
279 * - Proper multicast support.
280 * - NIC dump support.
281 * - More tuning parameters.
282 *
283 * The mini ring is not used under Linux and I am not sure it makes sense
284 * to actually use it.
285 *
286 * New interrupt handler strategy:
287 *
288 * The old interrupt handler worked using the traditional method of
289 * replacing an skbuff with a new one when a packet arrives. However
290 * the rx rings do not need to contain a static number of buffer
291 * descriptors, thus it makes sense to move the memory allocation out
292 * of the main interrupt handler and do it in a bottom half handler
293 * and only allocate new buffers when the number of buffers in the
294 * ring is below a certain threshold. In order to avoid starving the
295 * NIC under heavy load it is however necessary to force allocation
296 * when hitting a minimum threshold. The strategy for alloction is as
297 * follows:
298 *
299 * RX_LOW_BUF_THRES - allocate buffers in the bottom half
300 * RX_PANIC_LOW_THRES - we are very low on buffers, allocate
301 * the buffers in the interrupt handler
302 * RX_RING_THRES - maximum number of buffers in the rx ring
303 * RX_MINI_THRES - maximum number of buffers in the mini ring
304 * RX_JUMBO_THRES - maximum number of buffers in the jumbo ring
305 *
306 * One advantagous side effect of this allocation approach is that the
307 * entire rx processing can be done without holding any spin lock
308 * since the rx rings and registers are totally independent of the tx
309 * ring and its registers. This of course includes the kmalloc's of
310 * new skb's. Thus start_xmit can run in parallel with rx processing
311 * and the memory allocation on SMP systems.
312 *
313 * Note that running the skb reallocation in a bottom half opens up
314 * another can of races which needs to be handled properly. In
315 * particular it can happen that the interrupt handler tries to run
316 * the reallocation while the bottom half is either running on another
317 * CPU or was interrupted on the same CPU. To get around this the
318 * driver uses bitops to prevent the reallocation routines from being
319 * reentered.
320 *
321 * TX handling can also be done without holding any spin lock, wheee
322 * this is fun! since tx_ret_csm is only written to by the interrupt
323 * handler. The case to be aware of is when shutting down the device
324 * and cleaning up where it is necessary to make sure that
325 * start_xmit() is not running while this is happening. Well DaveM
326 * informs me that this case is already protected against ... bye bye
327 * Mr. Spin Lock, it was nice to know you.
328 *
329 * TX interrupts are now partly disabled so the NIC will only generate
330 * TX interrupts for the number of coal ticks, not for the number of
331 * TX packets in the queue. This should reduce the number of TX only,
332 * ie. when no RX processing is done, interrupts seen.
333 */
334
335/*
336 * Threshold values for RX buffer allocation - the low water marks for
337 * when to start refilling the rings are set to 75% of the ring
338 * sizes. It seems to make sense to refill the rings entirely from the
339 * intrrupt handler once it gets below the panic threshold, that way
340 * we don't risk that the refilling is moved to another CPU when the
341 * one running the interrupt handler just got the slab code hot in its
342 * cache.
343 */
344#define RX_RING_SIZE 72
345#define RX_MINI_SIZE 64
346#define RX_JUMBO_SIZE 48
347
348#define RX_PANIC_STD_THRES 16
349#define RX_PANIC_STD_REFILL (3*RX_PANIC_STD_THRES)/2
350#define RX_LOW_STD_THRES (3*RX_RING_SIZE)/4
351#define RX_PANIC_MINI_THRES 12
352#define RX_PANIC_MINI_REFILL (3*RX_PANIC_MINI_THRES)/2
353#define RX_LOW_MINI_THRES (3*RX_MINI_SIZE)/4
354#define RX_PANIC_JUMBO_THRES 6
355#define RX_PANIC_JUMBO_REFILL (3*RX_PANIC_JUMBO_THRES)/2
356#define RX_LOW_JUMBO_THRES (3*RX_JUMBO_SIZE)/4
357
358
359/*
360 * Size of the mini ring entries, basically these just should be big
361 * enough to take TCP ACKs
362 */
363#define ACE_MINI_SIZE 100
364
365#define ACE_MINI_BUFSIZE ACE_MINI_SIZE
366#define ACE_STD_BUFSIZE (ACE_STD_MTU + ETH_HLEN + 4)
367#define ACE_JUMBO_BUFSIZE (ACE_JUMBO_MTU + ETH_HLEN + 4)
368
369/*
370 * There seems to be a magic difference in the effect between 995 and 996
371 * but little difference between 900 and 995 ... no idea why.
372 *
373 * There is now a default set of tuning parameters which is set, depending
374 * on whether or not the user enables Jumbo frames. It's assumed that if
375 * Jumbo frames are enabled, the user wants optimal tuning for that case.
376 */
377#define DEF_TX_COAL 400 /* 996 */
378#define DEF_TX_MAX_DESC 60 /* was 40 */
379#define DEF_RX_COAL 120 /* 1000 */
380#define DEF_RX_MAX_DESC 25
381#define DEF_TX_RATIO 21 /* 24 */
382
383#define DEF_JUMBO_TX_COAL 20
384#define DEF_JUMBO_TX_MAX_DESC 60
385#define DEF_JUMBO_RX_COAL 30
386#define DEF_JUMBO_RX_MAX_DESC 6
387#define DEF_JUMBO_TX_RATIO 21
388
389#if tigon2FwReleaseLocal < 20001118
390/*
391 * Standard firmware and early modifications duplicate
392 * IRQ load without this flag (coal timer is never reset).
393 * Note that with this flag tx_coal should be less than
394 * time to xmit full tx ring.
395 * 400usec is not so bad for tx ring size of 128.
396 */
397#define TX_COAL_INTS_ONLY 1 /* worth it */
398#else
399/*
400 * With modified firmware, this is not necessary, but still useful.
401 */
402#define TX_COAL_INTS_ONLY 1
403#endif
404
405#define DEF_TRACE 0
406#define DEF_STAT (2 * TICKS_PER_SEC)
407
408
ddfce6bb 409static int link_state[ACE_MAX_MOD_PARMS];
1da177e4
LT		 410static int trace[ACE_MAX_MOD_PARMS];
411static int tx_coal_tick[ACE_MAX_MOD_PARMS];
412static int rx_coal_tick[ACE_MAX_MOD_PARMS];
413static int max_tx_desc[ACE_MAX_MOD_PARMS];
414static int max_rx_desc[ACE_MAX_MOD_PARMS];
415static int tx_ratio[ACE_MAX_MOD_PARMS];
416static int dis_pci_mem_inval[ACE_MAX_MOD_PARMS] = {1, 1, 1, 1, 1, 1, 1, 1};
417
418MODULE_AUTHOR("Jes Sorensen <jes@trained-monkey.org>");
419MODULE_LICENSE("GPL");
420MODULE_DESCRIPTION("AceNIC/3C985/GA620 Gigabit Ethernet driver");
421
ddfce6bb 422module_param_array_named(link, link_state, int, NULL, 0);
1da177e4
LT		 423module_param_array(trace, int, NULL, 0);
424module_param_array(tx_coal_tick, int, NULL, 0);
425module_param_array(max_tx_desc, int, NULL, 0);
426module_param_array(rx_coal_tick, int, NULL, 0);
427module_param_array(max_rx_desc, int, NULL, 0);
428module_param_array(tx_ratio, int, NULL, 0);
429MODULE_PARM_DESC(link, "AceNIC/3C985/NetGear link state");
430MODULE_PARM_DESC(trace, "AceNIC/3C985/NetGear firmware trace level");
431MODULE_PARM_DESC(tx_coal_tick, "AceNIC/3C985/GA620 max clock ticks to wait from first tx descriptor arrives");
432MODULE_PARM_DESC(max_tx_desc, "AceNIC/3C985/GA620 max number of transmit descriptors to wait");
433MODULE_PARM_DESC(rx_coal_tick, "AceNIC/3C985/GA620 max clock ticks to wait from first rx descriptor arrives");
434MODULE_PARM_DESC(max_rx_desc, "AceNIC/3C985/GA620 max number of receive descriptors to wait");
435MODULE_PARM_DESC(tx_ratio, "AceNIC/3C985/GA620 ratio of NIC memory used for TX/RX descriptors (range 0-63)");
436
437
6aa20a22 438static char version[] __devinitdata =
1da177e4
LT		 439 "acenic.c: v0.92 08/05/2002 Jes Sorensen, linux-acenic@SunSITE.dk\n"
440 " http://home.cern.ch/~jes/gige/acenic.html\n";
441
442static int ace_get_settings(struct net_device *, struct ethtool_cmd *);
443static int ace_set_settings(struct net_device *, struct ethtool_cmd *);
444static void ace_get_drvinfo(struct net_device *, struct ethtool_drvinfo *);
445
7282d491 446static const struct ethtool_ops ace_ethtool_ops = {
1da177e4
LT		 447 .get_settings = ace_get_settings,
448 .set_settings = ace_set_settings,
449 .get_drvinfo = ace_get_drvinfo,
450};
451
452static void ace_watchdog(struct net_device *dev);
453
454static int __devinit acenic_probe_one(struct pci_dev *pdev,
455 const struct pci_device_id *id)
456{
457 struct net_device *dev;
458 struct ace_private *ap;
459 static int boards_found;
460
461 dev = alloc_etherdev(sizeof(struct ace_private));
462 if (dev == NULL) {
463 printk(KERN_ERR "acenic: Unable to allocate "
464 "net_device structure!\n");
465 return -ENOMEM;
466 }
467
1da177e4
LT		 468 SET_NETDEV_DEV(dev, &pdev->dev);
469
470 ap = dev->priv;
471 ap->pdev = pdev;
472 ap->name = pci_name(pdev);
473
474 dev->features |= NETIF_F_SG | NETIF_F_IP_CSUM;
475#if ACENIC_DO_VLAN
476 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
477 dev->vlan_rx_register = ace_vlan_rx_register;
1da177e4 478#endif
25805dcf
SH		 479
480 dev->tx_timeout = &ace_watchdog;
481 dev->watchdog_timeo = 5*HZ;
1da177e4
LT		 482
483 dev->open = &ace_open;
484 dev->stop = &ace_close;
485 dev->hard_start_xmit = &ace_start_xmit;
486 dev->get_stats = &ace_get_stats;
487 dev->set_multicast_list = &ace_set_multicast_list;
488 SET_ETHTOOL_OPS(dev, &ace_ethtool_ops);
489 dev->set_mac_address = &ace_set_mac_addr;
490 dev->change_mtu = &ace_change_mtu;
491
492 /* we only display this string ONCE */
493 if (!boards_found)
494 printk(version);
495
496 if (pci_enable_device(pdev))
497 goto fail_free_netdev;
498
499 /*
500 * Enable master mode before we start playing with the
501 * pci_command word since pci_set_master() will modify
502 * it.
503 */
504 pci_set_master(pdev);
505
506 pci_read_config_word(pdev, PCI_COMMAND, &ap->pci_command);
507
6aa20a22 508 /* OpenFirmware on Mac's does not set this - DOH.. */
1da177e4
LT		 509 if (!(ap->pci_command & PCI_COMMAND_MEMORY)) {
510 printk(KERN_INFO "%s: Enabling PCI Memory Mapped "
511 "access - was not enabled by BIOS/Firmware\n",
512 ap->name);
513 ap->pci_command = ap->pci_command | PCI_COMMAND_MEMORY;
514 pci_write_config_word(ap->pdev, PCI_COMMAND,
515 ap->pci_command);
516 wmb();
517 }
518
519 pci_read_config_byte(pdev, PCI_LATENCY_TIMER, &ap->pci_latency);
520 if (ap->pci_latency <= 0x40) {
521 ap->pci_latency = 0x40;
522 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, ap->pci_latency);
523 }
524
525 /*
526 * Remap the regs into kernel space - this is abuse of
527 * dev->base_addr since it was means for I/O port
528 * addresses but who gives a damn.
529 */
530 dev->base_addr = pci_resource_start(pdev, 0);
531 ap->regs = ioremap(dev->base_addr, 0x4000);
532 if (!ap->regs) {
533 printk(KERN_ERR "%s: Unable to map I/O register, "
534 "AceNIC %i will be disabled.\n",
535 ap->name, boards_found);
536 goto fail_free_netdev;
537 }
538
539 switch(pdev->vendor) {
540 case PCI_VENDOR_ID_ALTEON:
541 if (pdev->device == PCI_DEVICE_ID_FARALLON_PN9100T) {
542 printk(KERN_INFO "%s: Farallon PN9100-T ",
543 ap->name);
544 } else {
545 printk(KERN_INFO "%s: Alteon AceNIC ",
546 ap->name);
547 }
548 break;
549 case PCI_VENDOR_ID_3COM:
550 printk(KERN_INFO "%s: 3Com 3C985 ", ap->name);
551 break;
552 case PCI_VENDOR_ID_NETGEAR:
553 printk(KERN_INFO "%s: NetGear GA620 ", ap->name);
554 break;
555 case PCI_VENDOR_ID_DEC:
556 if (pdev->device == PCI_DEVICE_ID_FARALLON_PN9000SX) {
557 printk(KERN_INFO "%s: Farallon PN9000-SX ",
558 ap->name);
559 break;
560 }
561 case PCI_VENDOR_ID_SGI:
562 printk(KERN_INFO "%s: SGI AceNIC ", ap->name);
563 break;
564 default:
565 printk(KERN_INFO "%s: Unknown AceNIC ", ap->name);
566 break;
567 }
568
569 printk("Gigabit Ethernet at 0x%08lx, ", dev->base_addr);
c6387a48 570 printk("irq %d\n", pdev->irq);
1da177e4
LT		 571
572#ifdef CONFIG_ACENIC_OMIT_TIGON_I
573 if ((readl(&ap->regs->HostCtrl) >> 28) == 4) {
574 printk(KERN_ERR "%s: Driver compiled without Tigon I"
575 " support - NIC disabled\n", dev->name);
576 goto fail_uninit;
577 }
578#endif
579
580 if (ace_allocate_descriptors(dev))
581 goto fail_free_netdev;
582
583#ifdef MODULE
584 if (boards_found >= ACE_MAX_MOD_PARMS)
585 ap->board_idx = BOARD_IDX_OVERFLOW;
586 else
587 ap->board_idx = boards_found;
588#else
589 ap->board_idx = BOARD_IDX_STATIC;
590#endif
591
592 if (ace_init(dev))
593 goto fail_free_netdev;
594
595 if (register_netdev(dev)) {
596 printk(KERN_ERR "acenic: device registration failed\n");
597 goto fail_uninit;
598 }
599 ap->name = dev->name;
600
601 if (ap->pci_using_dac)
602 dev->features |= NETIF_F_HIGHDMA;
603
604 pci_set_drvdata(pdev, dev);
605
606 boards_found++;
607 return 0;
608
609 fail_uninit:
610 ace_init_cleanup(dev);
611 fail_free_netdev:
612 free_netdev(dev);
613 return -ENODEV;
614}
615
616static void __devexit acenic_remove_one(struct pci_dev *pdev)
617{
618 struct net_device *dev = pci_get_drvdata(pdev);
619 struct ace_private *ap = netdev_priv(dev);
620 struct ace_regs __iomem *regs = ap->regs;
621 short i;
622
623 unregister_netdev(dev);
624
625 writel(readl(&regs->CpuCtrl) | CPU_HALT, &regs->CpuCtrl);
626 if (ap->version >= 2)
627 writel(readl(&regs->CpuBCtrl) | CPU_HALT, &regs->CpuBCtrl);
6aa20a22 628
1da177e4
LT		 629 /*
630 * This clears any pending interrupts
631 */
632 writel(1, &regs->Mb0Lo);
633 readl(&regs->CpuCtrl); /* flush */
634
635 /*
636 * Make sure no other CPUs are processing interrupts
637 * on the card before the buffers are being released.
638 * Otherwise one might experience some `interesting'
639 * effects.
640 *
641 * Then release the RX buffers - jumbo buffers were
642 * already released in ace_close().
643 */
644 ace_sync_irq(dev->irq);
645
646 for (i = 0; i < RX_STD_RING_ENTRIES; i++) {
647 struct sk_buff *skb = ap->skb->rx_std_skbuff[i].skb;
648
649 if (skb) {
650 struct ring_info *ringp;
651 dma_addr_t mapping;
652
653 ringp = &ap->skb->rx_std_skbuff[i];
654 mapping = pci_unmap_addr(ringp, mapping);
655 pci_unmap_page(ap->pdev, mapping,
656 ACE_STD_BUFSIZE,
657 PCI_DMA_FROMDEVICE);
658
659 ap->rx_std_ring[i].size = 0;
660 ap->skb->rx_std_skbuff[i].skb = NULL;
661 dev_kfree_skb(skb);
662 }
663 }
664
665 if (ap->version >= 2) {
666 for (i = 0; i < RX_MINI_RING_ENTRIES; i++) {
667 struct sk_buff *skb = ap->skb->rx_mini_skbuff[i].skb;
668
669 if (skb) {
670 struct ring_info *ringp;
671 dma_addr_t mapping;
672
673 ringp = &ap->skb->rx_mini_skbuff[i];
674 mapping = pci_unmap_addr(ringp,mapping);
675 pci_unmap_page(ap->pdev, mapping,
676 ACE_MINI_BUFSIZE,
677 PCI_DMA_FROMDEVICE);
678
679 ap->rx_mini_ring[i].size = 0;
680 ap->skb->rx_mini_skbuff[i].skb = NULL;
681 dev_kfree_skb(skb);
682 }
683 }
684 }
685
686 for (i = 0; i < RX_JUMBO_RING_ENTRIES; i++) {
687 struct sk_buff *skb = ap->skb->rx_jumbo_skbuff[i].skb;
688 if (skb) {
689 struct ring_info *ringp;
690 dma_addr_t mapping;
691
692 ringp = &ap->skb->rx_jumbo_skbuff[i];
693 mapping = pci_unmap_addr(ringp, mapping);
694 pci_unmap_page(ap->pdev, mapping,
695 ACE_JUMBO_BUFSIZE,
696 PCI_DMA_FROMDEVICE);
697
698 ap->rx_jumbo_ring[i].size = 0;
699 ap->skb->rx_jumbo_skbuff[i].skb = NULL;
700 dev_kfree_skb(skb);
701 }
702 }
703
704 ace_init_cleanup(dev);
705 free_netdev(dev);
706}
707
708static struct pci_driver acenic_pci_driver = {
709 .name = "acenic",
710 .id_table = acenic_pci_tbl,
711 .probe = acenic_probe_one,
712 .remove = __devexit_p(acenic_remove_one),
713};
714
715static int __init acenic_init(void)
716{
29917620 717 return pci_register_driver(&acenic_pci_driver);
1da177e4
LT		 718}
719
720static void __exit acenic_exit(void)
721{
722 pci_unregister_driver(&acenic_pci_driver);
723}
724
725module_init(acenic_init);
726module_exit(acenic_exit);
727
728static void ace_free_descriptors(struct net_device *dev)
729{
730 struct ace_private *ap = netdev_priv(dev);
731 int size;
732
733 if (ap->rx_std_ring != NULL) {
734 size = (sizeof(struct rx_desc) *
735 (RX_STD_RING_ENTRIES +
736 RX_JUMBO_RING_ENTRIES +
737 RX_MINI_RING_ENTRIES +
738 RX_RETURN_RING_ENTRIES));
739 pci_free_consistent(ap->pdev, size, ap->rx_std_ring,
740 ap->rx_ring_base_dma);
741 ap->rx_std_ring = NULL;
742 ap->rx_jumbo_ring = NULL;
743 ap->rx_mini_ring = NULL;
744 ap->rx_return_ring = NULL;
745 }
746 if (ap->evt_ring != NULL) {
747 size = (sizeof(struct event) * EVT_RING_ENTRIES);
748 pci_free_consistent(ap->pdev, size, ap->evt_ring,
749 ap->evt_ring_dma);
750 ap->evt_ring = NULL;
751 }
752 if (ap->tx_ring != NULL && !ACE_IS_TIGON_I(ap)) {
753 size = (sizeof(struct tx_desc) * MAX_TX_RING_ENTRIES);
754 pci_free_consistent(ap->pdev, size, ap->tx_ring,
755 ap->tx_ring_dma);
756 }
757 ap->tx_ring = NULL;
758
759 if (ap->evt_prd != NULL) {
760 pci_free_consistent(ap->pdev, sizeof(u32),
761 (void *)ap->evt_prd, ap->evt_prd_dma);
762 ap->evt_prd = NULL;
763 }
764 if (ap->rx_ret_prd != NULL) {
765 pci_free_consistent(ap->pdev, sizeof(u32),
766 (void *)ap->rx_ret_prd,
767 ap->rx_ret_prd_dma);
768 ap->rx_ret_prd = NULL;
769 }
770 if (ap->tx_csm != NULL) {
771 pci_free_consistent(ap->pdev, sizeof(u32),
772 (void *)ap->tx_csm, ap->tx_csm_dma);
773 ap->tx_csm = NULL;
774 }
775}
776
777
778static int ace_allocate_descriptors(struct net_device *dev)
779{
780 struct ace_private *ap = netdev_priv(dev);
781 int size;
782
783 size = (sizeof(struct rx_desc) *
784 (RX_STD_RING_ENTRIES +
785 RX_JUMBO_RING_ENTRIES +
786 RX_MINI_RING_ENTRIES +
787 RX_RETURN_RING_ENTRIES));
788
789 ap->rx_std_ring = pci_alloc_consistent(ap->pdev, size,
790 &ap->rx_ring_base_dma);
791 if (ap->rx_std_ring == NULL)
792 goto fail;
793
794 ap->rx_jumbo_ring = ap->rx_std_ring + RX_STD_RING_ENTRIES;
795 ap->rx_mini_ring = ap->rx_jumbo_ring + RX_JUMBO_RING_ENTRIES;
796 ap->rx_return_ring = ap->rx_mini_ring + RX_MINI_RING_ENTRIES;
797
798 size = (sizeof(struct event) * EVT_RING_ENTRIES);
799
800 ap->evt_ring = pci_alloc_consistent(ap->pdev, size, &ap->evt_ring_dma);
801
802 if (ap->evt_ring == NULL)
803 goto fail;
804
805 /*
806 * Only allocate a host TX ring for the Tigon II, the Tigon I
807 * has to use PCI registers for this ;-(
808 */
809 if (!ACE_IS_TIGON_I(ap)) {
810 size = (sizeof(struct tx_desc) * MAX_TX_RING_ENTRIES);
811
812 ap->tx_ring = pci_alloc_consistent(ap->pdev, size,
813 &ap->tx_ring_dma);
814
815 if (ap->tx_ring == NULL)
816 goto fail;
817 }
818
819 ap->evt_prd = pci_alloc_consistent(ap->pdev, sizeof(u32),
820 &ap->evt_prd_dma);
821 if (ap->evt_prd == NULL)
822 goto fail;
823
824 ap->rx_ret_prd = pci_alloc_consistent(ap->pdev, sizeof(u32),
825 &ap->rx_ret_prd_dma);
826 if (ap->rx_ret_prd == NULL)
827 goto fail;
828
829 ap->tx_csm = pci_alloc_consistent(ap->pdev, sizeof(u32),
830 &ap->tx_csm_dma);
831 if (ap->tx_csm == NULL)
832 goto fail;
833
834 return 0;
835
836fail:
837 /* Clean up. */
838 ace_init_cleanup(dev);
839 return 1;
840}
841
842
843/*
844 * Generic cleanup handling data allocated during init. Used when the
845 * module is unloaded or if an error occurs during initialization
846 */
847static void ace_init_cleanup(struct net_device *dev)
848{
849 struct ace_private *ap;
850
851 ap = netdev_priv(dev);
852
853 ace_free_descriptors(dev);
854
855 if (ap->info)
856 pci_free_consistent(ap->pdev, sizeof(struct ace_info),
857 ap->info, ap->info_dma);
b4558ea9
JJ		 858 kfree(ap->skb);
859 kfree(ap->trace_buf);
1da177e4
LT		 860
861 if (dev->irq)
862 free_irq(dev->irq, dev);
863
864 iounmap(ap->regs);
865}
866
867
868/*
869 * Commands are considered to be slow.
870 */
871static inline void ace_issue_cmd(struct ace_regs __iomem *regs, struct cmd *cmd)
872{
873 u32 idx;
874
875 idx = readl(&regs->CmdPrd);
876
877 writel(*(u32 *)(cmd), &regs->CmdRng[idx]);
878 idx = (idx + 1) % CMD_RING_ENTRIES;
879
880 writel(idx, &regs->CmdPrd);
881}
882
883
884static int __devinit ace_init(struct net_device *dev)
885{
886 struct ace_private *ap;
887 struct ace_regs __iomem *regs;
888 struct ace_info *info = NULL;
889 struct pci_dev *pdev;
890 unsigned long myjif;
891 u64 tmp_ptr;
892 u32 tig_ver, mac1, mac2, tmp, pci_state;
893 int board_idx, ecode = 0;
894 short i;
895 unsigned char cache_size;
0795af57 896 DECLARE_MAC_BUF(mac);
1da177e4
LT		 897
898 ap = netdev_priv(dev);
899 regs = ap->regs;
900
901 board_idx = ap->board_idx;
902
903 /*
904 * aman@sgi.com - its useful to do a NIC reset here to
905 * address the `Firmware not running' problem subsequent
906 * to any crashes involving the NIC
907 */
908 writel(HW_RESET | (HW_RESET << 24), &regs->HostCtrl);
909 readl(&regs->HostCtrl); /* PCI write posting */
910 udelay(5);
911
912 /*
913 * Don't access any other registers before this point!
914 */
915#ifdef __BIG_ENDIAN
916 /*
917 * This will most likely need BYTE_SWAP once we switch
918 * to using __raw_writel()
919 */
920 writel((WORD_SWAP | CLR_INT | ((WORD_SWAP | CLR_INT) << 24)),
921 &regs->HostCtrl);
922#else
923 writel((CLR_INT | WORD_SWAP | ((CLR_INT | WORD_SWAP) << 24)),
924 &regs->HostCtrl);
925#endif
926 readl(&regs->HostCtrl); /* PCI write posting */
927
928 /*
929 * Stop the NIC CPU and clear pending interrupts
930 */
931 writel(readl(&regs->CpuCtrl) | CPU_HALT, &regs->CpuCtrl);
932 readl(&regs->CpuCtrl); /* PCI write posting */
933 writel(0, &regs->Mb0Lo);
934
935 tig_ver = readl(&regs->HostCtrl) >> 28;
936
937 switch(tig_ver){
938#ifndef CONFIG_ACENIC_OMIT_TIGON_I
939 case 4:
940 case 5:
941 printk(KERN_INFO " Tigon I (Rev. %i), Firmware: %i.%i.%i, ",
942 tig_ver, tigonFwReleaseMajor, tigonFwReleaseMinor,
943 tigonFwReleaseFix);
944 writel(0, &regs->LocalCtrl);
945 ap->version = 1;
946 ap->tx_ring_entries = TIGON_I_TX_RING_ENTRIES;
947 break;
948#endif
949 case 6:
950 printk(KERN_INFO " Tigon II (Rev. %i), Firmware: %i.%i.%i, ",
951 tig_ver, tigon2FwReleaseMajor, tigon2FwReleaseMinor,
952 tigon2FwReleaseFix);
953 writel(readl(&regs->CpuBCtrl) | CPU_HALT, &regs->CpuBCtrl);
954 readl(&regs->CpuBCtrl); /* PCI write posting */
955 /*
956 * The SRAM bank size does _not_ indicate the amount
957 * of memory on the card, it controls the _bank_ size!
958 * Ie. a 1MB AceNIC will have two banks of 512KB.
959 */
960 writel(SRAM_BANK_512K, &regs->LocalCtrl);
961 writel(SYNC_SRAM_TIMING, &regs->MiscCfg);
962 ap->version = 2;
963 ap->tx_ring_entries = MAX_TX_RING_ENTRIES;
964 break;
965 default:
966 printk(KERN_WARNING " Unsupported Tigon version detected "
967 "(%i)\n", tig_ver);
968 ecode = -ENODEV;
969 goto init_error;
970 }
971
972 /*
973 * ModeStat _must_ be set after the SRAM settings as this change
974 * seems to corrupt the ModeStat and possible other registers.
975 * The SRAM settings survive resets and setting it to the same
976 * value a second time works as well. This is what caused the
977 * `Firmware not running' problem on the Tigon II.
978 */
979#ifdef __BIG_ENDIAN
980 writel(ACE_BYTE_SWAP_DMA | ACE_WARN | ACE_FATAL | ACE_BYTE_SWAP_BD |
981 ACE_WORD_SWAP_BD | ACE_NO_JUMBO_FRAG, &regs->ModeStat);
982#else
983 writel(ACE_BYTE_SWAP_DMA | ACE_WARN | ACE_FATAL |
984 ACE_WORD_SWAP_BD | ACE_NO_JUMBO_FRAG, &regs->ModeStat);
985#endif
986 readl(&regs->ModeStat); /* PCI write posting */
987
988 mac1 = 0;
989 for(i = 0; i < 4; i++) {
ddfce6bb 990 int t;
6f9d4722 991
1da177e4 992 mac1 = mac1 << 8;
ddfce6bb
SH		 993 t = read_eeprom_byte(dev, 0x8c+i);
994 if (t < 0) {
1da177e4
LT		 995 ecode = -EIO;
996 goto init_error;
997 } else
ddfce6bb 998 mac1 |= (t & 0xff);
1da177e4
LT		 999 }
1000 mac2 = 0;
1001 for(i = 4; i < 8; i++) {
ddfce6bb 1002 int t;
6f9d4722 1003
1da177e4 1004 mac2 = mac2 << 8;
ddfce6bb
SH		 1005 t = read_eeprom_byte(dev, 0x8c+i);
1006 if (t < 0) {
1da177e4
LT		 1007 ecode = -EIO;
1008 goto init_error;
1009 } else
ddfce6bb 1010 mac2 |= (t & 0xff);
1da177e4
LT		 1011 }
1012
1013 writel(mac1, &regs->MacAddrHi);
1014 writel(mac2, &regs->MacAddrLo);
1015
1da177e4
LT		 1016 dev->dev_addr[0] = (mac1 >> 8) & 0xff;
1017 dev->dev_addr[1] = mac1 & 0xff;
1018 dev->dev_addr[2] = (mac2 >> 24) & 0xff;
1019 dev->dev_addr[3] = (mac2 >> 16) & 0xff;
1020 dev->dev_addr[4] = (mac2 >> 8) & 0xff;
1021 dev->dev_addr[5] = mac2 & 0xff;
1022
0795af57
JP		 1023 printk("MAC: %s\n", print_mac(mac, dev->dev_addr));
1024
1da177e4
LT		 1025 /*
1026 * Looks like this is necessary to deal with on all architectures,
1027 * even this %$#%$# N440BX Intel based thing doesn't get it right.
1028 * Ie. having two NICs in the machine, one will have the cache
1029 * line set at boot time, the other will not.
1030 */
1031 pdev = ap->pdev;
1032 pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &cache_size);
1033 cache_size <<= 2;
1034 if (cache_size != SMP_CACHE_BYTES) {
1035 printk(KERN_INFO " PCI cache line size set incorrectly "
1036 "(%i bytes) by BIOS/FW, ", cache_size);
1037 if (cache_size > SMP_CACHE_BYTES)
1038 printk("expecting %i\n", SMP_CACHE_BYTES);
1039 else {
1040 printk("correcting to %i\n", SMP_CACHE_BYTES);
1041 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE,
1042 SMP_CACHE_BYTES >> 2);
1043 }
1044 }
1045
1046 pci_state = readl(&regs->PciState);
1047 printk(KERN_INFO " PCI bus width: %i bits, speed: %iMHz, "
1048 "latency: %i clks\n",
1049 (pci_state & PCI_32BIT) ? 32 : 64,
6aa20a22 1050 (pci_state & PCI_66MHZ) ? 66 : 33,
1da177e4
LT		 1051 ap->pci_latency);
1052
1053 /*
1054 * Set the max DMA transfer size. Seems that for most systems
1055 * the performance is better when no MAX parameter is
1056 * set. However for systems enabling PCI write and invalidate,
1057 * DMA writes must be set to the L1 cache line size to get
1058 * optimal performance.
1059 *
1060 * The default is now to turn the PCI write and invalidate off
1061 * - that is what Alteon does for NT.
1062 */
1063 tmp = READ_CMD_MEM | WRITE_CMD_MEM;
1064 if (ap->version >= 2) {
1065 tmp |= (MEM_READ_MULTIPLE | (pci_state & PCI_66MHZ));
1066 /*
1067 * Tuning parameters only supported for 8 cards
1068 */
1069 if (board_idx == BOARD_IDX_OVERFLOW ||
1070 dis_pci_mem_inval[board_idx]) {
1071 if (ap->pci_command & PCI_COMMAND_INVALIDATE) {
1072 ap->pci_command &= ~PCI_COMMAND_INVALIDATE;
1073 pci_write_config_word(pdev, PCI_COMMAND,
1074 ap->pci_command);
1075 printk(KERN_INFO " Disabling PCI memory "
1076 "write and invalidate\n");
1077 }
1078 } else if (ap->pci_command & PCI_COMMAND_INVALIDATE) {
1079 printk(KERN_INFO " PCI memory write & invalidate "
1080 "enabled by BIOS, enabling counter measures\n");
1081
1082 switch(SMP_CACHE_BYTES) {
1083 case 16:
1084 tmp |= DMA_WRITE_MAX_16;
1085 break;
1086 case 32:
1087 tmp |= DMA_WRITE_MAX_32;
1088 break;
1089 case 64:
1090 tmp |= DMA_WRITE_MAX_64;
1091 break;
1092 case 128:
1093 tmp |= DMA_WRITE_MAX_128;
1094 break;
1095 default:
1096 printk(KERN_INFO " Cache line size %i not "
1097 "supported, PCI write and invalidate "
1098 "disabled\n", SMP_CACHE_BYTES);
1099 ap->pci_command &= ~PCI_COMMAND_INVALIDATE;
1100 pci_write_config_word(pdev, PCI_COMMAND,
1101 ap->pci_command);
1102 }
1103 }
1104 }
1105
1106#ifdef __sparc__
1107 /*
1108 * On this platform, we know what the best dma settings
1109 * are. We use 64-byte maximum bursts, because if we
1110 * burst larger than the cache line size (or even cross
1111 * a 64byte boundary in a single burst) the UltraSparc
1112 * PCI controller will disconnect at 64-byte multiples.
1113 *
1114 * Read-multiple will be properly enabled above, and when
1115 * set will give the PCI controller proper hints about
1116 * prefetching.
1117 */
1118 tmp &= ~DMA_READ_WRITE_MASK;
1119 tmp |= DMA_READ_MAX_64;
1120 tmp |= DMA_WRITE_MAX_64;
1121#endif
1122#ifdef __alpha__
1123 tmp &= ~DMA_READ_WRITE_MASK;
1124 tmp |= DMA_READ_MAX_128;
1125 /*
1126 * All the docs say MUST NOT. Well, I did.
1127 * Nothing terrible happens, if we load wrong size.
1128 * Bit w&i still works better!
1129 */
1130 tmp |= DMA_WRITE_MAX_128;
1131#endif
1132 writel(tmp, &regs->PciState);
1133
1134#if 0
1135 /*
1136 * The Host PCI bus controller driver has to set FBB.
1137 * If all devices on that PCI bus support FBB, then the controller
1138 * can enable FBB support in the Host PCI Bus controller (or on
1139 * the PCI-PCI bridge if that applies).
1140 * -ggg
1141 */
1142 /*
1143 * I have received reports from people having problems when this
1144 * bit is enabled.
1145 */
1146 if (!(ap->pci_command & PCI_COMMAND_FAST_BACK)) {
1147 printk(KERN_INFO " Enabling PCI Fast Back to Back\n");
1148 ap->pci_command |= PCI_COMMAND_FAST_BACK;
1149 pci_write_config_word(pdev, PCI_COMMAND, ap->pci_command);
1150 }
1151#endif
6aa20a22 1152
1da177e4
LT		 1153 /*
1154 * Configure DMA attributes.
1155 */
1e7f0bd8 1156 if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
1da177e4 1157 ap->pci_using_dac = 1;
1e7f0bd8 1158 } else if (!pci_set_dma_mask(pdev, DMA_32BIT_MASK)) {
1da177e4
LT		 1159 ap->pci_using_dac = 0;
1160 } else {
1161 ecode = -ENODEV;
1162 goto init_error;
1163 }
1164
1165 /*
1166 * Initialize the generic info block and the command+event rings
1167 * and the control blocks for the transmit and receive rings
1168 * as they need to be setup once and for all.
1169 */
1170 if (!(info = pci_alloc_consistent(ap->pdev, sizeof(struct ace_info),
1171 &ap->info_dma))) {
1172 ecode = -EAGAIN;
1173 goto init_error;
1174 }
1175 ap->info = info;
1176
1177 /*
1178 * Get the memory for the skb rings.
1179 */
1180 if (!(ap->skb = kmalloc(sizeof(struct ace_skb), GFP_KERNEL))) {
1181 ecode = -EAGAIN;
1182 goto init_error;
1183 }
1184
1fb9df5d 1185 ecode = request_irq(pdev->irq, ace_interrupt, IRQF_SHARED,
1da177e4
LT		 1186 DRV_NAME, dev);
1187 if (ecode) {
1188 printk(KERN_WARNING "%s: Requested IRQ %d is busy\n",
1189 DRV_NAME, pdev->irq);
1190 goto init_error;
1191 } else
1192 dev->irq = pdev->irq;
1193
1194#ifdef INDEX_DEBUG
1195 spin_lock_init(&ap->debug_lock);
1196 ap->last_tx = ACE_TX_RING_ENTRIES(ap) - 1;
1197 ap->last_std_rx = 0;
1198 ap->last_mini_rx = 0;
1199#endif
1200
1201 memset(ap->info, 0, sizeof(struct ace_info));
1202 memset(ap->skb, 0, sizeof(struct ace_skb));
1203
1204 ace_load_firmware(dev);
1205 ap->fw_running = 0;
1206
1207 tmp_ptr = ap->info_dma;
1208 writel(tmp_ptr >> 32, &regs->InfoPtrHi);
1209 writel(tmp_ptr & 0xffffffff, &regs->InfoPtrLo);
1210
1211 memset(ap->evt_ring, 0, EVT_RING_ENTRIES * sizeof(struct event));
1212
1213 set_aceaddr(&info->evt_ctrl.rngptr, ap->evt_ring_dma);
1214 info->evt_ctrl.flags = 0;
1215
1216 *(ap->evt_prd) = 0;
1217 wmb();
1218 set_aceaddr(&info->evt_prd_ptr, ap->evt_prd_dma);
1219 writel(0, &regs->EvtCsm);
1220
1221 set_aceaddr(&info->cmd_ctrl.rngptr, 0x100);
1222 info->cmd_ctrl.flags = 0;
1223 info->cmd_ctrl.max_len = 0;
1224
1225 for (i = 0; i < CMD_RING_ENTRIES; i++)
1226 writel(0, &regs->CmdRng[i]);
1227
1228 writel(0, &regs->CmdPrd);
1229 writel(0, &regs->CmdCsm);
1230
1231 tmp_ptr = ap->info_dma;
1232 tmp_ptr += (unsigned long) &(((struct ace_info *)0)->s.stats);
1233 set_aceaddr(&info->stats2_ptr, (dma_addr_t) tmp_ptr);
1234
1235 set_aceaddr(&info->rx_std_ctrl.rngptr, ap->rx_ring_base_dma);
1236 info->rx_std_ctrl.max_len = ACE_STD_BUFSIZE;
1237 info->rx_std_ctrl.flags =
1238 RCB_FLG_TCP_UDP_SUM | RCB_FLG_NO_PSEUDO_HDR | ACE_RCB_VLAN_FLAG;
1239
1240 memset(ap->rx_std_ring, 0,
1241 RX_STD_RING_ENTRIES * sizeof(struct rx_desc));
1242
1243 for (i = 0; i < RX_STD_RING_ENTRIES; i++)
1244 ap->rx_std_ring[i].flags = BD_FLG_TCP_UDP_SUM;
1245
1246 ap->rx_std_skbprd = 0;
1247 atomic_set(&ap->cur_rx_bufs, 0);
1248
1249 set_aceaddr(&info->rx_jumbo_ctrl.rngptr,
1250 (ap->rx_ring_base_dma +
1251 (sizeof(struct rx_desc) * RX_STD_RING_ENTRIES)));
1252 info->rx_jumbo_ctrl.max_len = 0;
1253 info->rx_jumbo_ctrl.flags =
1254 RCB_FLG_TCP_UDP_SUM | RCB_FLG_NO_PSEUDO_HDR | ACE_RCB_VLAN_FLAG;
1255
1256 memset(ap->rx_jumbo_ring, 0,
1257 RX_JUMBO_RING_ENTRIES * sizeof(struct rx_desc));
1258
1259 for (i = 0; i < RX_JUMBO_RING_ENTRIES; i++)
1260 ap->rx_jumbo_ring[i].flags = BD_FLG_TCP_UDP_SUM | BD_FLG_JUMBO;
1261
1262 ap->rx_jumbo_skbprd = 0;
1263 atomic_set(&ap->cur_jumbo_bufs, 0);
1264
1265 memset(ap->rx_mini_ring, 0,
1266 RX_MINI_RING_ENTRIES * sizeof(struct rx_desc));
1267
1268 if (ap->version >= 2) {
1269 set_aceaddr(&info->rx_mini_ctrl.rngptr,
1270 (ap->rx_ring_base_dma +
1271 (sizeof(struct rx_desc) *
1272 (RX_STD_RING_ENTRIES +
1273 RX_JUMBO_RING_ENTRIES))));
1274 info->rx_mini_ctrl.max_len = ACE_MINI_SIZE;
6aa20a22 1275 info->rx_mini_ctrl.flags =
1da177e4
LT		 1276 RCB_FLG_TCP_UDP_SUM|RCB_FLG_NO_PSEUDO_HDR|ACE_RCB_VLAN_FLAG;
1277
1278 for (i = 0; i < RX_MINI_RING_ENTRIES; i++)
1279 ap->rx_mini_ring[i].flags =
1280 BD_FLG_TCP_UDP_SUM | BD_FLG_MINI;
1281 } else {
1282 set_aceaddr(&info->rx_mini_ctrl.rngptr, 0);
1283 info->rx_mini_ctrl.flags = RCB_FLG_RNG_DISABLE;
1284 info->rx_mini_ctrl.max_len = 0;
1285 }
1286
1287 ap->rx_mini_skbprd = 0;
1288 atomic_set(&ap->cur_mini_bufs, 0);
1289
1290 set_aceaddr(&info->rx_return_ctrl.rngptr,
1291 (ap->rx_ring_base_dma +
1292 (sizeof(struct rx_desc) *
1293 (RX_STD_RING_ENTRIES +
1294 RX_JUMBO_RING_ENTRIES +
1295 RX_MINI_RING_ENTRIES))));
1296 info->rx_return_ctrl.flags = 0;
1297 info->rx_return_ctrl.max_len = RX_RETURN_RING_ENTRIES;
1298
1299 memset(ap->rx_return_ring, 0,
1300 RX_RETURN_RING_ENTRIES * sizeof(struct rx_desc));
1301
1302 set_aceaddr(&info->rx_ret_prd_ptr, ap->rx_ret_prd_dma);
1303 *(ap->rx_ret_prd) = 0;
1304
1305 writel(TX_RING_BASE, &regs->WinBase);
1306
1307 if (ACE_IS_TIGON_I(ap)) {
ddfce6bb 1308 ap->tx_ring = (__force struct tx_desc *) regs->Window;
6aa20a22 1309 for (i = 0; i < (TIGON_I_TX_RING_ENTRIES
1da177e4 1310 * sizeof(struct tx_desc)) / sizeof(u32); i++)
ddfce6bb 1311 writel(0, (__force void __iomem *)ap->tx_ring + i * 4);
1da177e4
LT		 1312
1313 set_aceaddr(&info->tx_ctrl.rngptr, TX_RING_BASE);
1314 } else {
1315 memset(ap->tx_ring, 0,
1316 MAX_TX_RING_ENTRIES * sizeof(struct tx_desc));
1317
1318 set_aceaddr(&info->tx_ctrl.rngptr, ap->tx_ring_dma);
1319 }
1320
1321 info->tx_ctrl.max_len = ACE_TX_RING_ENTRIES(ap);
1322 tmp = RCB_FLG_TCP_UDP_SUM | RCB_FLG_NO_PSEUDO_HDR | ACE_RCB_VLAN_FLAG;
1323
1324 /*
1325 * The Tigon I does not like having the TX ring in host memory ;-(
1326 */
1327 if (!ACE_IS_TIGON_I(ap))
1328 tmp |= RCB_FLG_TX_HOST_RING;
1329#if TX_COAL_INTS_ONLY
1330 tmp |= RCB_FLG_COAL_INT_ONLY;
1331#endif
1332 info->tx_ctrl.flags = tmp;
1333
1334 set_aceaddr(&info->tx_csm_ptr, ap->tx_csm_dma);
1335
1336 /*
1337 * Potential item for tuning parameter
1338 */
1339#if 0 /* NO */
1340 writel(DMA_THRESH_16W, &regs->DmaReadCfg);
1341 writel(DMA_THRESH_16W, &regs->DmaWriteCfg);
1342#else
1343 writel(DMA_THRESH_8W, &regs->DmaReadCfg);
1344 writel(DMA_THRESH_8W, &regs->DmaWriteCfg);
1345#endif
1346
1347 writel(0, &regs->MaskInt);
1348 writel(1, &regs->IfIdx);
1349#if 0
1350 /*
1351 * McKinley boxes do not like us fiddling with AssistState
1352 * this early
1353 */
1354 writel(1, &regs->AssistState);
1355#endif
1356
1357 writel(DEF_STAT, &regs->TuneStatTicks);
1358 writel(DEF_TRACE, &regs->TuneTrace);
1359
1360 ace_set_rxtx_parms(dev, 0);
1361
1362 if (board_idx == BOARD_IDX_OVERFLOW) {
1363 printk(KERN_WARNING "%s: more than %i NICs detected, "
1364 "ignoring module parameters!\n",
1365 ap->name, ACE_MAX_MOD_PARMS);
1366 } else if (board_idx >= 0) {
1367 if (tx_coal_tick[board_idx])
1368 writel(tx_coal_tick[board_idx],
1369 &regs->TuneTxCoalTicks);
1370 if (max_tx_desc[board_idx])
1371 writel(max_tx_desc[board_idx], &regs->TuneMaxTxDesc);
1372
1373 if (rx_coal_tick[board_idx])
1374 writel(rx_coal_tick[board_idx],
1375 &regs->TuneRxCoalTicks);
1376 if (max_rx_desc[board_idx])
1377 writel(max_rx_desc[board_idx], &regs->TuneMaxRxDesc);
1378
1379 if (trace[board_idx])
1380 writel(trace[board_idx], &regs->TuneTrace);
1381
1382 if ((tx_ratio[board_idx] > 0) && (tx_ratio[board_idx] < 64))
1383 writel(tx_ratio[board_idx], &regs->TxBufRat);
1384 }
1385
1386 /*
1387 * Default link parameters
1388 */
1389 tmp = LNK_ENABLE | LNK_FULL_DUPLEX | LNK_1000MB | LNK_100MB |
1390 LNK_10MB | LNK_RX_FLOW_CTL_Y | LNK_NEG_FCTL | LNK_NEGOTIATE;
1391 if(ap->version >= 2)
1392 tmp |= LNK_TX_FLOW_CTL_Y;
1393
1394 /*
1395 * Override link default parameters
1396 */
ddfce6bb
SH		 1397 if ((board_idx >= 0) && link_state[board_idx]) {
1398 int option = link_state[board_idx];
1da177e4
LT		 1399
1400 tmp = LNK_ENABLE;
1401
1402 if (option & 0x01) {
1403 printk(KERN_INFO "%s: Setting half duplex link\n",
1404 ap->name);
1405 tmp &= ~LNK_FULL_DUPLEX;
1406 }
1407 if (option & 0x02)
1408 tmp &= ~LNK_NEGOTIATE;
1409 if (option & 0x10)
1410 tmp |= LNK_10MB;
1411 if (option & 0x20)
1412 tmp |= LNK_100MB;
1413 if (option & 0x40)
1414 tmp |= LNK_1000MB;
1415 if ((option & 0x70) == 0) {
1416 printk(KERN_WARNING "%s: No media speed specified, "
1417 "forcing auto negotiation\n", ap->name);
1418 tmp |= LNK_NEGOTIATE | LNK_1000MB |
1419 LNK_100MB | LNK_10MB;
1420 }
1421 if ((option & 0x100) == 0)
1422 tmp |= LNK_NEG_FCTL;
1423 else
1424 printk(KERN_INFO "%s: Disabling flow control "
1425 "negotiation\n", ap->name);
1426 if (option & 0x200)
1427 tmp |= LNK_RX_FLOW_CTL_Y;
1428 if ((option & 0x400) && (ap->version >= 2)) {
1429 printk(KERN_INFO "%s: Enabling TX flow control\n",
1430 ap->name);
1431 tmp |= LNK_TX_FLOW_CTL_Y;
1432 }
1433 }
1434
1435 ap->link = tmp;
1436 writel(tmp, &regs->TuneLink);
1437 if (ap->version >= 2)
1438 writel(tmp, &regs->TuneFastLink);
1439
1440 if (ACE_IS_TIGON_I(ap))
1441 writel(tigonFwStartAddr, &regs->Pc);
1442 if (ap->version == 2)
1443 writel(tigon2FwStartAddr, &regs->Pc);
1444
1445 writel(0, &regs->Mb0Lo);
1446
1447 /*
1448 * Set tx_csm before we start receiving interrupts, otherwise
1449 * the interrupt handler might think it is supposed to process
1450 * tx ints before we are up and running, which may cause a null
1451 * pointer access in the int handler.
1452 */
1453 ap->cur_rx = 0;
1454 ap->tx_prd = *(ap->tx_csm) = ap->tx_ret_csm = 0;
1455
1456 wmb();
1457 ace_set_txprd(regs, ap, 0);
1458 writel(0, &regs->RxRetCsm);
1459
1460 /*
1461 * Zero the stats before starting the interface
1462 */
1463 memset(&ap->stats, 0, sizeof(ap->stats));
1464
1465 /*
1466 * Enable DMA engine now.
1467 * If we do this sooner, Mckinley box pukes.
1468 * I assume it's because Tigon II DMA engine wants to check
1469 * *something* even before the CPU is started.
1470 */
1471 writel(1, &regs->AssistState); /* enable DMA */
1472
1473 /*
1474 * Start the NIC CPU
1475 */
1476 writel(readl(&regs->CpuCtrl) & ~(CPU_HALT|CPU_TRACE), &regs->CpuCtrl);
1477 readl(&regs->CpuCtrl);
1478
1479 /*
1480 * Wait for the firmware to spin up - max 3 seconds.
1481 */
1482 myjif = jiffies + 3 * HZ;
1483 while (time_before(jiffies, myjif) && !ap->fw_running)
1484 cpu_relax();
1485
1486 if (!ap->fw_running) {
1487 printk(KERN_ERR "%s: Firmware NOT running!\n", ap->name);
1488
1489 ace_dump_trace(ap);
1490 writel(readl(&regs->CpuCtrl) | CPU_HALT, &regs->CpuCtrl);
1491 readl(&regs->CpuCtrl);
1492
1493 /* aman@sgi.com - account for badly behaving firmware/NIC:
1494 * - have observed that the NIC may continue to generate
1495 * interrupts for some reason; attempt to stop it - halt
1496 * second CPU for Tigon II cards, and also clear Mb0
1497 * - if we're a module, we'll fail to load if this was
1498 * the only GbE card in the system => if the kernel does
1499 * see an interrupt from the NIC, code to handle it is
1500 * gone and OOps! - so free_irq also
1501 */
1502 if (ap->version >= 2)
1503 writel(readl(&regs->CpuBCtrl) | CPU_HALT,
1504 &regs->CpuBCtrl);
1505 writel(0, &regs->Mb0Lo);
1506 readl(&regs->Mb0Lo);
1507
1508 ecode = -EBUSY;
1509 goto init_error;
1510 }
1511
1512 /*
1513 * We load the ring here as there seem to be no way to tell the
1514 * firmware to wipe the ring without re-initializing it.
1515 */
1516 if (!test_and_set_bit(0, &ap->std_refill_busy))
1517 ace_load_std_rx_ring(ap, RX_RING_SIZE);
1518 else
1519 printk(KERN_ERR "%s: Someone is busy refilling the RX ring\n",
1520 ap->name);
1521 if (ap->version >= 2) {
1522 if (!test_and_set_bit(0, &ap->mini_refill_busy))
1523 ace_load_mini_rx_ring(ap, RX_MINI_SIZE);
1524 else
1525 printk(KERN_ERR "%s: Someone is busy refilling "
1526 "the RX mini ring\n", ap->name);
1527 }
1528 return 0;
1529
1530 init_error:
1531 ace_init_cleanup(dev);
1532 return ecode;
1533}
1534
1535
1536static void ace_set_rxtx_parms(struct net_device *dev, int jumbo)
1537{
1538 struct ace_private *ap = netdev_priv(dev);
1539 struct ace_regs __iomem *regs = ap->regs;
1540 int board_idx = ap->board_idx;
1541
1542 if (board_idx >= 0) {
1543 if (!jumbo) {
1544 if (!tx_coal_tick[board_idx])
1545 writel(DEF_TX_COAL, &regs->TuneTxCoalTicks);
1546 if (!max_tx_desc[board_idx])
1547 writel(DEF_TX_MAX_DESC, &regs->TuneMaxTxDesc);
1548 if (!rx_coal_tick[board_idx])
1549 writel(DEF_RX_COAL, &regs->TuneRxCoalTicks);
1550 if (!max_rx_desc[board_idx])
1551 writel(DEF_RX_MAX_DESC, &regs->TuneMaxRxDesc);
1552 if (!tx_ratio[board_idx])
1553 writel(DEF_TX_RATIO, &regs->TxBufRat);
1554 } else {
1555 if (!tx_coal_tick[board_idx])
1556 writel(DEF_JUMBO_TX_COAL,
1557 &regs->TuneTxCoalTicks);
1558 if (!max_tx_desc[board_idx])
1559 writel(DEF_JUMBO_TX_MAX_DESC,
1560 &regs->TuneMaxTxDesc);
1561 if (!rx_coal_tick[board_idx])
1562 writel(DEF_JUMBO_RX_COAL,
1563 &regs->TuneRxCoalTicks);
1564 if (!max_rx_desc[board_idx])
1565 writel(DEF_JUMBO_RX_MAX_DESC,
1566 &regs->TuneMaxRxDesc);
1567 if (!tx_ratio[board_idx])
1568 writel(DEF_JUMBO_TX_RATIO, &regs->TxBufRat);
1569 }
1570 }
1571}
1572
1573
1574static void ace_watchdog(struct net_device *data)
1575{
1576 struct net_device *dev = data;
1577 struct ace_private *ap = netdev_priv(dev);
1578 struct ace_regs __iomem *regs = ap->regs;
1579
1580 /*
1581 * We haven't received a stats update event for more than 2.5
1582 * seconds and there is data in the transmit queue, thus we
1583 * asume the card is stuck.
1584 */
1585 if (*ap->tx_csm != ap->tx_ret_csm) {
1586 printk(KERN_WARNING "%s: Transmitter is stuck, %08x\n",
1587 dev->name, (unsigned int)readl(&regs->HostCtrl));
1588 /* This can happen due to ieee flow control. */
1589 } else {
1590 printk(KERN_DEBUG "%s: BUG... transmitter died. Kicking it.\n",
1591 dev->name);
1592#if 0
1593 netif_wake_queue(dev);
1594#endif
1595 }
1596}
1597
1598
1599static void ace_tasklet(unsigned long dev)
1600{
1601 struct ace_private *ap = netdev_priv((struct net_device *)dev);
1602 int cur_size;
1603
1604 cur_size = atomic_read(&ap->cur_rx_bufs);
1605 if ((cur_size < RX_LOW_STD_THRES) &&
1606 !test_and_set_bit(0, &ap->std_refill_busy)) {
1607#ifdef DEBUG
1608 printk("refilling buffers (current %i)\n", cur_size);
1609#endif
1610 ace_load_std_rx_ring(ap, RX_RING_SIZE - cur_size);
1611 }
1612
1613 if (ap->version >= 2) {
1614 cur_size = atomic_read(&ap->cur_mini_bufs);
1615 if ((cur_size < RX_LOW_MINI_THRES) &&
1616 !test_and_set_bit(0, &ap->mini_refill_busy)) {
1617#ifdef DEBUG
1618 printk("refilling mini buffers (current %i)\n",
1619 cur_size);
1620#endif
1621 ace_load_mini_rx_ring(ap, RX_MINI_SIZE - cur_size);
1622 }
1623 }
1624
1625 cur_size = atomic_read(&ap->cur_jumbo_bufs);
1626 if (ap->jumbo && (cur_size < RX_LOW_JUMBO_THRES) &&
1627 !test_and_set_bit(0, &ap->jumbo_refill_busy)) {
1628#ifdef DEBUG
1629 printk("refilling jumbo buffers (current %i)\n", cur_size);
1630#endif
1631 ace_load_jumbo_rx_ring(ap, RX_JUMBO_SIZE - cur_size);
1632 }
1633 ap->tasklet_pending = 0;
1634}
1635
1636
1637/*
1638 * Copy the contents of the NIC's trace buffer to kernel memory.
1639 */
1640static void ace_dump_trace(struct ace_private *ap)
1641{
1642#if 0
1643 if (!ap->trace_buf)
1644 if (!(ap->trace_buf = kmalloc(ACE_TRACE_SIZE, GFP_KERNEL)))
1645 return;
1646#endif
1647}
1648
1649
1650/*
1651 * Load the standard rx ring.
1652 *
1653 * Loading rings is safe without holding the spin lock since this is
1654 * done only before the device is enabled, thus no interrupts are
1655 * generated and by the interrupt handler/tasklet handler.
1656 */
1657static void ace_load_std_rx_ring(struct ace_private *ap, int nr_bufs)
1658{
1659 struct ace_regs __iomem *regs = ap->regs;
1660 short i, idx;
6aa20a22 1661
1da177e4
LT		 1662
1663 prefetchw(&ap->cur_rx_bufs);
1664
1665 idx = ap->rx_std_skbprd;
1666
1667 for (i = 0; i < nr_bufs; i++) {
1668 struct sk_buff *skb;
1669 struct rx_desc *rd;
1670 dma_addr_t mapping;
1671
1672 skb = alloc_skb(ACE_STD_BUFSIZE + NET_IP_ALIGN, GFP_ATOMIC);
1673 if (!skb)
1674 break;
1675
1676 skb_reserve(skb, NET_IP_ALIGN);
1677 mapping = pci_map_page(ap->pdev, virt_to_page(skb->data),
1678 offset_in_page(skb->data),
1679 ACE_STD_BUFSIZE,
1680 PCI_DMA_FROMDEVICE);
1681 ap->skb->rx_std_skbuff[idx].skb = skb;
1682 pci_unmap_addr_set(&ap->skb->rx_std_skbuff[idx],
1683 mapping, mapping);
1684
1685 rd = &ap->rx_std_ring[idx];
1686 set_aceaddr(&rd->addr, mapping);
1687 rd->size = ACE_STD_BUFSIZE;
1688 rd->idx = idx;
1689 idx = (idx + 1) % RX_STD_RING_ENTRIES;
1690 }
1691
1692 if (!i)
1693 goto error_out;
1694
1695 atomic_add(i, &ap->cur_rx_bufs);
1696 ap->rx_std_skbprd = idx;
1697
1698 if (ACE_IS_TIGON_I(ap)) {
1699 struct cmd cmd;
1700 cmd.evt = C_SET_RX_PRD_IDX;
1701 cmd.code = 0;
1702 cmd.idx = ap->rx_std_skbprd;
1703 ace_issue_cmd(regs, &cmd);
1704 } else {
1705 writel(idx, &regs->RxStdPrd);
1706 wmb();
1707 }
1708
1709 out:
1710 clear_bit(0, &ap->std_refill_busy);
1711 return;
1712
1713 error_out:
1714 printk(KERN_INFO "Out of memory when allocating "
1715 "standard receive buffers\n");
1716 goto out;
1717}
1718
1719
1720static void ace_load_mini_rx_ring(struct ace_private *ap, int nr_bufs)
1721{
1722 struct ace_regs __iomem *regs = ap->regs;
1723 short i, idx;
1724
1725 prefetchw(&ap->cur_mini_bufs);
1726
1727 idx = ap->rx_mini_skbprd;
1728 for (i = 0; i < nr_bufs; i++) {
1729 struct sk_buff *skb;
1730 struct rx_desc *rd;
1731 dma_addr_t mapping;
1732
1733 skb = alloc_skb(ACE_MINI_BUFSIZE + NET_IP_ALIGN, GFP_ATOMIC);
1734 if (!skb)
1735 break;
1736
1737 skb_reserve(skb, NET_IP_ALIGN);
1738 mapping = pci_map_page(ap->pdev, virt_to_page(skb->data),
1739 offset_in_page(skb->data),
1740 ACE_MINI_BUFSIZE,
1741 PCI_DMA_FROMDEVICE);
1742 ap->skb->rx_mini_skbuff[idx].skb = skb;
1743 pci_unmap_addr_set(&ap->skb->rx_mini_skbuff[idx],
1744 mapping, mapping);
1745
1746 rd = &ap->rx_mini_ring[idx];
1747 set_aceaddr(&rd->addr, mapping);
1748 rd->size = ACE_MINI_BUFSIZE;
1749 rd->idx = idx;
1750 idx = (idx + 1) % RX_MINI_RING_ENTRIES;
1751 }
1752
1753 if (!i)
1754 goto error_out;
1755
1756 atomic_add(i, &ap->cur_mini_bufs);
1757
1758 ap->rx_mini_skbprd = idx;
1759
1760 writel(idx, &regs->RxMiniPrd);
1761 wmb();
1762
1763 out:
1764 clear_bit(0, &ap->mini_refill_busy);
1765 return;
1766 error_out:
1767 printk(KERN_INFO "Out of memory when allocating "
1768 "mini receive buffers\n");
1769 goto out;
1770}
1771
1772
1773/*
1774 * Load the jumbo rx ring, this may happen at any time if the MTU
1775 * is changed to a value > 1500.
1776 */
1777static void ace_load_jumbo_rx_ring(struct ace_private *ap, int nr_bufs)
1778{
1779 struct ace_regs __iomem *regs = ap->regs;
1780 short i, idx;
1781
1782 idx = ap->rx_jumbo_skbprd;
1783
1784 for (i = 0; i < nr_bufs; i++) {
1785 struct sk_buff *skb;
1786 struct rx_desc *rd;
1787 dma_addr_t mapping;
1788
1789 skb = alloc_skb(ACE_JUMBO_BUFSIZE + NET_IP_ALIGN, GFP_ATOMIC);
1790 if (!skb)
1791 break;
1792
1793 skb_reserve(skb, NET_IP_ALIGN);
1794 mapping = pci_map_page(ap->pdev, virt_to_page(skb->data),
1795 offset_in_page(skb->data),
1796 ACE_JUMBO_BUFSIZE,
1797 PCI_DMA_FROMDEVICE);
1798 ap->skb->rx_jumbo_skbuff[idx].skb = skb;
1799 pci_unmap_addr_set(&ap->skb->rx_jumbo_skbuff[idx],
1800 mapping, mapping);
1801
1802 rd = &ap->rx_jumbo_ring[idx];
1803 set_aceaddr(&rd->addr, mapping);
1804 rd->size = ACE_JUMBO_BUFSIZE;
1805 rd->idx = idx;
1806 idx = (idx + 1) % RX_JUMBO_RING_ENTRIES;
1807 }
1808
1809 if (!i)
1810 goto error_out;
1811
1812 atomic_add(i, &ap->cur_jumbo_bufs);
1813 ap->rx_jumbo_skbprd = idx;
1814
1815 if (ACE_IS_TIGON_I(ap)) {
1816 struct cmd cmd;
1817 cmd.evt = C_SET_RX_JUMBO_PRD_IDX;
1818 cmd.code = 0;
1819 cmd.idx = ap->rx_jumbo_skbprd;
1820 ace_issue_cmd(regs, &cmd);
1821 } else {
1822 writel(idx, &regs->RxJumboPrd);
1823 wmb();
1824 }
1825
1826 out:
1827 clear_bit(0, &ap->jumbo_refill_busy);
1828 return;
1829 error_out:
1830 if (net_ratelimit())
1831 printk(KERN_INFO "Out of memory when allocating "
1832 "jumbo receive buffers\n");
1833 goto out;
1834}
1835
1836
1837/*
1838 * All events are considered to be slow (RX/TX ints do not generate
1839 * events) and are handled here, outside the main interrupt handler,
1840 * to reduce the size of the handler.
1841 */
1842static u32 ace_handle_event(struct net_device *dev, u32 evtcsm, u32 evtprd)
1843{
1844 struct ace_private *ap;
1845
1846 ap = netdev_priv(dev);
1847
1848 while (evtcsm != evtprd) {
1849 switch (ap->evt_ring[evtcsm].evt) {
1850 case E_FW_RUNNING:
1851 printk(KERN_INFO "%s: Firmware up and running\n",
1852 ap->name);
1853 ap->fw_running = 1;
1854 wmb();
1855 break;
1856 case E_STATS_UPDATED:
1857 break;
1858 case E_LNK_STATE:
1859 {
1860 u16 code = ap->evt_ring[evtcsm].code;
1861 switch (code) {
1862 case E_C_LINK_UP:
1863 {
1864 u32 state = readl(&ap->regs->GigLnkState);
1865 printk(KERN_WARNING "%s: Optical link UP "
1866 "(%s Duplex, Flow Control: %s%s)\n",
1867 ap->name,
1868 state & LNK_FULL_DUPLEX ? "Full":"Half",
1869 state & LNK_TX_FLOW_CTL_Y ? "TX " : "",
1870 state & LNK_RX_FLOW_CTL_Y ? "RX" : "");
1871 break;
1872 }
1873 case E_C_LINK_DOWN:
1874 printk(KERN_WARNING "%s: Optical link DOWN\n",
1875 ap->name);
1876 break;
1877 case E_C_LINK_10_100:
1878 printk(KERN_WARNING "%s: 10/100BaseT link "
1879 "UP\n", ap->name);
1880 break;
1881 default:
1882 printk(KERN_ERR "%s: Unknown optical link "
1883 "state %02x\n", ap->name, code);
1884 }
1885 break;
1886 }
1887 case E_ERROR:
1888 switch(ap->evt_ring[evtcsm].code) {
1889 case E_C_ERR_INVAL_CMD:
1890 printk(KERN_ERR "%s: invalid command error\n",
1891 ap->name);
1892 break;
1893 case E_C_ERR_UNIMP_CMD:
1894 printk(KERN_ERR "%s: unimplemented command "
1895 "error\n", ap->name);
1896 break;
1897 case E_C_ERR_BAD_CFG:
1898 printk(KERN_ERR "%s: bad config error\n",
1899 ap->name);
1900 break;
1901 default:
1902 printk(KERN_ERR "%s: unknown error %02x\n",
1903 ap->name, ap->evt_ring[evtcsm].code);
1904 }
1905 break;
1906 case E_RESET_JUMBO_RNG:
1907 {
1908 int i;
1909 for (i = 0; i < RX_JUMBO_RING_ENTRIES; i++) {
1910 if (ap->skb->rx_jumbo_skbuff[i].skb) {
1911 ap->rx_jumbo_ring[i].size = 0;
1912 set_aceaddr(&ap->rx_jumbo_ring[i].addr, 0);
1913 dev_kfree_skb(ap->skb->rx_jumbo_skbuff[i].skb);
1914 ap->skb->rx_jumbo_skbuff[i].skb = NULL;
1915 }
1916 }
1917
1918 if (ACE_IS_TIGON_I(ap)) {
1919 struct cmd cmd;
1920 cmd.evt = C_SET_RX_JUMBO_PRD_IDX;
1921 cmd.code = 0;
1922 cmd.idx = 0;
1923 ace_issue_cmd(ap->regs, &cmd);
1924 } else {
1925 writel(0, &((ap->regs)->RxJumboPrd));
1926 wmb();
1927 }
1928
1929 ap->jumbo = 0;
1930 ap->rx_jumbo_skbprd = 0;
1931 printk(KERN_INFO "%s: Jumbo ring flushed\n",
1932 ap->name);
1933 clear_bit(0, &ap->jumbo_refill_busy);
1934 break;
1935 }
1936 default:
1937 printk(KERN_ERR "%s: Unhandled event 0x%02x\n",
1938 ap->name, ap->evt_ring[evtcsm].evt);
1939 }
1940 evtcsm = (evtcsm + 1) % EVT_RING_ENTRIES;
1941 }
1942
1943 return evtcsm;
1944}
1945
1946
1947static void ace_rx_int(struct net_device *dev, u32 rxretprd, u32 rxretcsm)
1948{
1949 struct ace_private *ap = netdev_priv(dev);
1950 u32 idx;
1951 int mini_count = 0, std_count = 0;
1952
1953 idx = rxretcsm;
1954
1955 prefetchw(&ap->cur_rx_bufs);
1956 prefetchw(&ap->cur_mini_bufs);
6aa20a22 1957
1da177e4
LT		 1958 while (idx != rxretprd) {
1959 struct ring_info *rip;
1960 struct sk_buff *skb;
1961 struct rx_desc *rxdesc, *retdesc;
1962 u32 skbidx;
1963 int bd_flags, desc_type, mapsize;
1964 u16 csum;
1965
1966
1967 /* make sure the rx descriptor isn't read before rxretprd */
6aa20a22 1968 if (idx == rxretcsm)
1da177e4
LT		 1969 rmb();
1970
1971 retdesc = &ap->rx_return_ring[idx];
1972 skbidx = retdesc->idx;
1973 bd_flags = retdesc->flags;
1974 desc_type = bd_flags & (BD_FLG_JUMBO | BD_FLG_MINI);
1975
1976 switch(desc_type) {
1977 /*
1978 * Normal frames do not have any flags set
1979 *
1980 * Mini and normal frames arrive frequently,
1981 * so use a local counter to avoid doing
1982 * atomic operations for each packet arriving.
1983 */
1984 case 0:
1985 rip = &ap->skb->rx_std_skbuff[skbidx];
1986 mapsize = ACE_STD_BUFSIZE;
1987 rxdesc = &ap->rx_std_ring[skbidx];
1988 std_count++;
1989 break;
1990 case BD_FLG_JUMBO:
1991 rip = &ap->skb->rx_jumbo_skbuff[skbidx];
1992 mapsize = ACE_JUMBO_BUFSIZE;
1993 rxdesc = &ap->rx_jumbo_ring[skbidx];
1994 atomic_dec(&ap->cur_jumbo_bufs);
1995 break;
1996 case BD_FLG_MINI:
1997 rip = &ap->skb->rx_mini_skbuff[skbidx];
1998 mapsize = ACE_MINI_BUFSIZE;
1999 rxdesc = &ap->rx_mini_ring[skbidx];
6aa20a22 2000 mini_count++;
1da177e4
LT		 2001 break;
2002 default:
2003 printk(KERN_INFO "%s: unknown frame type (0x%02x) "
2004 "returned by NIC\n", dev->name,
2005 retdesc->flags);
2006 goto error;
2007 }
2008
2009 skb = rip->skb;
2010 rip->skb = NULL;
2011 pci_unmap_page(ap->pdev,
2012 pci_unmap_addr(rip, mapping),
2013 mapsize,
2014 PCI_DMA_FROMDEVICE);
2015 skb_put(skb, retdesc->size);
2016
2017 /*
2018 * Fly baby, fly!
2019 */
2020 csum = retdesc->tcp_udp_csum;
2021
1da177e4
LT		 2022 skb->protocol = eth_type_trans(skb, dev);
2023
2024 /*
2025 * Instead of forcing the poor tigon mips cpu to calculate
2026 * pseudo hdr checksum, we do this ourselves.
2027 */
2028 if (bd_flags & BD_FLG_TCP_UDP_SUM) {
2029 skb->csum = htons(csum);
84fa7933 2030 skb->ip_summed = CHECKSUM_COMPLETE;
1da177e4
LT		 2031 } else {
2032 skb->ip_summed = CHECKSUM_NONE;
2033 }
2034
2035 /* send it up */
2036#if ACENIC_DO_VLAN
2037 if (ap->vlgrp && (bd_flags & BD_FLG_VLAN_TAG)) {
2038 vlan_hwaccel_rx(skb, ap->vlgrp, retdesc->vlan);
2039 } else
2040#endif
2041 netif_rx(skb);
2042
2043 dev->last_rx = jiffies;
2044 ap->stats.rx_packets++;
2045 ap->stats.rx_bytes += retdesc->size;
2046
2047 idx = (idx + 1) % RX_RETURN_RING_ENTRIES;
2048 }
2049
2050 atomic_sub(std_count, &ap->cur_rx_bufs);
2051 if (!ACE_IS_TIGON_I(ap))
2052 atomic_sub(mini_count, &ap->cur_mini_bufs);
2053
2054 out:
2055 /*
2056 * According to the documentation RxRetCsm is obsolete with
2057 * the 12.3.x Firmware - my Tigon I NICs seem to disagree!
2058 */
2059 if (ACE_IS_TIGON_I(ap)) {
2060 writel(idx, &ap->regs->RxRetCsm);
2061 }
2062 ap->cur_rx = idx;
2063
2064 return;
2065 error:
2066 idx = rxretprd;
2067 goto out;
2068}
2069
2070
2071static inline void ace_tx_int(struct net_device *dev,
2072 u32 txcsm, u32 idx)
2073{
2074 struct ace_private *ap = netdev_priv(dev);
2075
2076 do {
2077 struct sk_buff *skb;
2078 dma_addr_t mapping;
2079 struct tx_ring_info *info;
2080
2081 info = ap->skb->tx_skbuff + idx;
2082 skb = info->skb;
2083 mapping = pci_unmap_addr(info, mapping);
2084
2085 if (mapping) {
2086 pci_unmap_page(ap->pdev, mapping,
2087 pci_unmap_len(info, maplen),
2088 PCI_DMA_TODEVICE);
2089 pci_unmap_addr_set(info, mapping, 0);
2090 }
2091
2092 if (skb) {
2093 ap->stats.tx_packets++;
2094 ap->stats.tx_bytes += skb->len;
2095 dev_kfree_skb_irq(skb);
2096 info->skb = NULL;
2097 }
2098
2099 idx = (idx + 1) % ACE_TX_RING_ENTRIES(ap);
2100 } while (idx != txcsm);
2101
2102 if (netif_queue_stopped(dev))
2103 netif_wake_queue(dev);
2104
2105 wmb();
2106 ap->tx_ret_csm = txcsm;
2107
2108 /* So... tx_ret_csm is advanced _after_ check for device wakeup.
2109 *
2110 * We could try to make it before. In this case we would get
2111 * the following race condition: hard_start_xmit on other cpu
2112 * enters after we advanced tx_ret_csm and fills space,
2113 * which we have just freed, so that we make illegal device wakeup.
2114 * There is no good way to workaround this (at entry
2115 * to ace_start_xmit detects this condition and prevents
2116 * ring corruption, but it is not a good workaround.)
2117 *
2118 * When tx_ret_csm is advanced after, we wake up device _only_
2119 * if we really have some space in ring (though the core doing
2120 * hard_start_xmit can see full ring for some period and has to
2121 * synchronize.) Superb.
2122 * BUT! We get another subtle race condition. hard_start_xmit
2123 * may think that ring is full between wakeup and advancing
2124 * tx_ret_csm and will stop device instantly! It is not so bad.
2125 * We are guaranteed that there is something in ring, so that
2126 * the next irq will resume transmission. To speedup this we could
2127 * mark descriptor, which closes ring with BD_FLG_COAL_NOW
2128 * (see ace_start_xmit).
2129 *
2130 * Well, this dilemma exists in all lock-free devices.
2131 * We, following scheme used in drivers by Donald Becker,
2132 * select the least dangerous.
2133 * --ANK
2134 */
2135}
2136
2137
7d12e780 2138static irqreturn_t ace_interrupt(int irq, void *dev_id)
1da177e4
LT		 2139{
2140 struct net_device *dev = (struct net_device *)dev_id;
2141 struct ace_private *ap = netdev_priv(dev);
2142 struct ace_regs __iomem *regs = ap->regs;
2143 u32 idx;
2144 u32 txcsm, rxretcsm, rxretprd;
2145 u32 evtcsm, evtprd;
2146
2147 /*
2148 * In case of PCI shared interrupts or spurious interrupts,
2149 * we want to make sure it is actually our interrupt before
2150 * spending any time in here.
2151 */
2152 if (!(readl(&regs->HostCtrl) & IN_INT))
2153 return IRQ_NONE;
2154
2155 /*
2156 * ACK intr now. Otherwise we will lose updates to rx_ret_prd,
2157 * which happened _after_ rxretprd = *ap->rx_ret_prd; but before
2158 * writel(0, &regs->Mb0Lo).
2159 *
2160 * "IRQ avoidance" recommended in docs applies to IRQs served
2161 * threads and it is wrong even for that case.
2162 */
2163 writel(0, &regs->Mb0Lo);
2164 readl(&regs->Mb0Lo);
2165
2166 /*
2167 * There is no conflict between transmit handling in
2168 * start_xmit and receive processing, thus there is no reason
2169 * to take a spin lock for RX handling. Wait until we start
2170 * working on the other stuff - hey we don't need a spin lock
2171 * anymore.
2172 */
2173 rxretprd = *ap->rx_ret_prd;
2174 rxretcsm = ap->cur_rx;
2175
2176 if (rxretprd != rxretcsm)
2177 ace_rx_int(dev, rxretprd, rxretcsm);
2178
2179 txcsm = *ap->tx_csm;
2180 idx = ap->tx_ret_csm;
2181
2182 if (txcsm != idx) {
2183 /*
2184 * If each skb takes only one descriptor this check degenerates
2185 * to identity, because new space has just been opened.
2186 * But if skbs are fragmented we must check that this index
2187 * update releases enough of space, otherwise we just
2188 * wait for device to make more work.
2189 */
2190 if (!tx_ring_full(ap, txcsm, ap->tx_prd))
2191 ace_tx_int(dev, txcsm, idx);
2192 }
2193
2194 evtcsm = readl(&regs->EvtCsm);
2195 evtprd = *ap->evt_prd;
2196
2197 if (evtcsm != evtprd) {
2198 evtcsm = ace_handle_event(dev, evtcsm, evtprd);
2199 writel(evtcsm, &regs->EvtCsm);
2200 }
2201
2202 /*
2203 * This has to go last in the interrupt handler and run with
2204 * the spin lock released ... what lock?
2205 */
2206 if (netif_running(dev)) {
2207 int cur_size;
2208 int run_tasklet = 0;
2209
2210 cur_size = atomic_read(&ap->cur_rx_bufs);
2211 if (cur_size < RX_LOW_STD_THRES) {
2212 if ((cur_size < RX_PANIC_STD_THRES) &&
2213 !test_and_set_bit(0, &ap->std_refill_busy)) {
2214#ifdef DEBUG
2215 printk("low on std buffers %i\n", cur_size);
2216#endif
2217 ace_load_std_rx_ring(ap,
2218 RX_RING_SIZE - cur_size);
2219 } else
2220 run_tasklet = 1;
2221 }
2222
2223 if (!ACE_IS_TIGON_I(ap)) {
2224 cur_size = atomic_read(&ap->cur_mini_bufs);
2225 if (cur_size < RX_LOW_MINI_THRES) {
2226 if ((cur_size < RX_PANIC_MINI_THRES) &&
2227 !test_and_set_bit(0,
2228 &ap->mini_refill_busy)) {
2229#ifdef DEBUG
2230 printk("low on mini buffers %i\n",
2231 cur_size);
2232#endif
2233 ace_load_mini_rx_ring(ap, RX_MINI_SIZE - cur_size);
2234 } else
2235 run_tasklet = 1;
2236 }
2237 }
2238
2239 if (ap->jumbo) {
2240 cur_size = atomic_read(&ap->cur_jumbo_bufs);
2241 if (cur_size < RX_LOW_JUMBO_THRES) {
2242 if ((cur_size < RX_PANIC_JUMBO_THRES) &&
2243 !test_and_set_bit(0,
2244 &ap->jumbo_refill_busy)){
2245#ifdef DEBUG
2246 printk("low on jumbo buffers %i\n",
2247 cur_size);
2248#endif
2249 ace_load_jumbo_rx_ring(ap, RX_JUMBO_SIZE - cur_size);
2250 } else
2251 run_tasklet = 1;
2252 }
2253 }
2254 if (run_tasklet && !ap->tasklet_pending) {
2255 ap->tasklet_pending = 1;
2256 tasklet_schedule(&ap->ace_tasklet);
2257 }
2258 }
2259
2260 return IRQ_HANDLED;
2261}
2262
2263
2264#if ACENIC_DO_VLAN
2265static void ace_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
2266{
2267 struct ace_private *ap = netdev_priv(dev);
2268 unsigned long flags;
2269
2270 local_irq_save(flags);
2271 ace_mask_irq(dev);
2272
2273 ap->vlgrp = grp;
2274
2275 ace_unmask_irq(dev);
2276 local_irq_restore(flags);
2277}
1da177e4
LT		 2278#endif /* ACENIC_DO_VLAN */
2279
2280
2281static int ace_open(struct net_device *dev)
2282{
2283 struct ace_private *ap = netdev_priv(dev);
2284 struct ace_regs __iomem *regs = ap->regs;
2285 struct cmd cmd;
2286
2287 if (!(ap->fw_running)) {
2288 printk(KERN_WARNING "%s: Firmware not running!\n", dev->name);
2289 return -EBUSY;
2290 }
2291
2292 writel(dev->mtu + ETH_HLEN + 4, &regs->IfMtu);
2293
2294 cmd.evt = C_CLEAR_STATS;
2295 cmd.code = 0;
2296 cmd.idx = 0;
2297 ace_issue_cmd(regs, &cmd);
2298
2299 cmd.evt = C_HOST_STATE;
2300 cmd.code = C_C_STACK_UP;
2301 cmd.idx = 0;
2302 ace_issue_cmd(regs, &cmd);
2303
2304 if (ap->jumbo &&
2305 !test_and_set_bit(0, &ap->jumbo_refill_busy))
2306 ace_load_jumbo_rx_ring(ap, RX_JUMBO_SIZE);
2307
2308 if (dev->flags & IFF_PROMISC) {
2309 cmd.evt = C_SET_PROMISC_MODE;
2310 cmd.code = C_C_PROMISC_ENABLE;
2311 cmd.idx = 0;
2312 ace_issue_cmd(regs, &cmd);
2313
2314 ap->promisc = 1;
2315 }else
2316 ap->promisc = 0;
2317 ap->mcast_all = 0;
2318
2319#if 0
2320 cmd.evt = C_LNK_NEGOTIATION;
2321 cmd.code = 0;
2322 cmd.idx = 0;
2323 ace_issue_cmd(regs, &cmd);
2324#endif
2325
2326 netif_start_queue(dev);
2327
2328 /*
2329 * Setup the bottom half rx ring refill handler
2330 */
2331 tasklet_init(&ap->ace_tasklet, ace_tasklet, (unsigned long)dev);
2332 return 0;
2333}
2334
2335
2336static int ace_close(struct net_device *dev)
2337{
2338 struct ace_private *ap = netdev_priv(dev);
2339 struct ace_regs __iomem *regs = ap->regs;
2340 struct cmd cmd;
2341 unsigned long flags;
2342 short i;
2343
2344 /*
2345 * Without (or before) releasing irq and stopping hardware, this
2346 * is an absolute non-sense, by the way. It will be reset instantly
2347 * by the first irq.
2348 */
2349 netif_stop_queue(dev);
2350
6aa20a22 2351
1da177e4
LT		 2352 if (ap->promisc) {
2353 cmd.evt = C_SET_PROMISC_MODE;
2354 cmd.code = C_C_PROMISC_DISABLE;
2355 cmd.idx = 0;
2356 ace_issue_cmd(regs, &cmd);
2357 ap->promisc = 0;
2358 }
2359
2360 cmd.evt = C_HOST_STATE;
2361 cmd.code = C_C_STACK_DOWN;
2362 cmd.idx = 0;
2363 ace_issue_cmd(regs, &cmd);
2364
2365 tasklet_kill(&ap->ace_tasklet);
2366
2367 /*
2368 * Make sure one CPU is not processing packets while
2369 * buffers are being released by another.
2370 */
2371
2372 local_irq_save(flags);
2373 ace_mask_irq(dev);
2374
2375 for (i = 0; i < ACE_TX_RING_ENTRIES(ap); i++) {
2376 struct sk_buff *skb;
2377 dma_addr_t mapping;
2378 struct tx_ring_info *info;
2379
2380 info = ap->skb->tx_skbuff + i;
2381 skb = info->skb;
2382 mapping = pci_unmap_addr(info, mapping);
2383
2384 if (mapping) {
2385 if (ACE_IS_TIGON_I(ap)) {
ddfce6bb
SH		 2386 /* NB: TIGON_1 is special, tx_ring is in io space */
2387 struct tx_desc __iomem *tx;
2388 tx = (__force struct tx_desc __iomem *) &ap->tx_ring[i];
1da177e4
LT		 2389 writel(0, &tx->addr.addrhi);
2390 writel(0, &tx->addr.addrlo);
2391 writel(0, &tx->flagsize);
2392 } else
2393 memset(ap->tx_ring + i, 0,
2394 sizeof(struct tx_desc));
2395 pci_unmap_page(ap->pdev, mapping,
2396 pci_unmap_len(info, maplen),
2397 PCI_DMA_TODEVICE);
2398 pci_unmap_addr_set(info, mapping, 0);
2399 }
2400 if (skb) {
2401 dev_kfree_skb(skb);
2402 info->skb = NULL;
2403 }
2404 }
2405
2406 if (ap->jumbo) {
2407 cmd.evt = C_RESET_JUMBO_RNG;
2408 cmd.code = 0;
2409 cmd.idx = 0;
2410 ace_issue_cmd(regs, &cmd);
2411 }
2412
2413 ace_unmask_irq(dev);
2414 local_irq_restore(flags);
2415
2416 return 0;
2417}
2418
2419
2420static inline dma_addr_t
2421ace_map_tx_skb(struct ace_private *ap, struct sk_buff *skb,
2422 struct sk_buff *tail, u32 idx)
2423{
2424 dma_addr_t mapping;
2425 struct tx_ring_info *info;
2426
2427 mapping = pci_map_page(ap->pdev, virt_to_page(skb->data),
2428 offset_in_page(skb->data),
2429 skb->len, PCI_DMA_TODEVICE);
2430
2431 info = ap->skb->tx_skbuff + idx;
2432 info->skb = tail;
2433 pci_unmap_addr_set(info, mapping, mapping);
2434 pci_unmap_len_set(info, maplen, skb->len);
2435 return mapping;
2436}
2437
2438
2439static inline void
2440ace_load_tx_bd(struct ace_private *ap, struct tx_desc *desc, u64 addr,
2441 u32 flagsize, u32 vlan_tag)
2442{
2443#if !USE_TX_COAL_NOW
2444 flagsize &= ~BD_FLG_COAL_NOW;
2445#endif
2446
2447 if (ACE_IS_TIGON_I(ap)) {
ddfce6bb 2448 struct tx_desc __iomem *io = (__force struct tx_desc __iomem *) desc;
1da177e4
LT		 2449 writel(addr >> 32, &io->addr.addrhi);
2450 writel(addr & 0xffffffff, &io->addr.addrlo);
2451 writel(flagsize, &io->flagsize);
2452#if ACENIC_DO_VLAN
2453 writel(vlan_tag, &io->vlanres);
2454#endif
2455 } else {
2456 desc->addr.addrhi = addr >> 32;
2457 desc->addr.addrlo = addr;
2458 desc->flagsize = flagsize;
2459#if ACENIC_DO_VLAN
2460 desc->vlanres = vlan_tag;
2461#endif
2462 }
2463}
2464
2465
2466static int ace_start_xmit(struct sk_buff *skb, struct net_device *dev)
2467{
2468 struct ace_private *ap = netdev_priv(dev);
2469 struct ace_regs __iomem *regs = ap->regs;
2470 struct tx_desc *desc;
2471 u32 idx, flagsize;
2472 unsigned long maxjiff = jiffies + 3*HZ;
2473
2474restart:
2475 idx = ap->tx_prd;
2476
2477 if (tx_ring_full(ap, ap->tx_ret_csm, idx))
2478 goto overflow;
2479
2480 if (!skb_shinfo(skb)->nr_frags) {
2481 dma_addr_t mapping;
2482 u32 vlan_tag = 0;
2483
2484 mapping = ace_map_tx_skb(ap, skb, skb, idx);
2485 flagsize = (skb->len << 16) | (BD_FLG_END);
84fa7933 2486 if (skb->ip_summed == CHECKSUM_PARTIAL)
1da177e4
LT		 2487 flagsize |= BD_FLG_TCP_UDP_SUM;
2488#if ACENIC_DO_VLAN
2489 if (vlan_tx_tag_present(skb)) {
2490 flagsize |= BD_FLG_VLAN_TAG;
2491 vlan_tag = vlan_tx_tag_get(skb);
2492 }
2493#endif
2494 desc = ap->tx_ring + idx;
2495 idx = (idx + 1) % ACE_TX_RING_ENTRIES(ap);
2496
2497 /* Look at ace_tx_int for explanations. */
2498 if (tx_ring_full(ap, ap->tx_ret_csm, idx))
2499 flagsize |= BD_FLG_COAL_NOW;
2500
2501 ace_load_tx_bd(ap, desc, mapping, flagsize, vlan_tag);
2502 } else {
2503 dma_addr_t mapping;
2504 u32 vlan_tag = 0;
2505 int i, len = 0;
2506
2507 mapping = ace_map_tx_skb(ap, skb, NULL, idx);
2508 flagsize = (skb_headlen(skb) << 16);
84fa7933 2509 if (skb->ip_summed == CHECKSUM_PARTIAL)
1da177e4
LT		 2510 flagsize |= BD_FLG_TCP_UDP_SUM;
2511#if ACENIC_DO_VLAN
2512 if (vlan_tx_tag_present(skb)) {
2513 flagsize |= BD_FLG_VLAN_TAG;
2514 vlan_tag = vlan_tx_tag_get(skb);
2515 }
2516#endif
2517
2518 ace_load_tx_bd(ap, ap->tx_ring + idx, mapping, flagsize, vlan_tag);
2519
2520 idx = (idx + 1) % ACE_TX_RING_ENTRIES(ap);
2521
2522 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
2523 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2524 struct tx_ring_info *info;
2525
2526 len += frag->size;
2527 info = ap->skb->tx_skbuff + idx;
2528 desc = ap->tx_ring + idx;
2529
2530 mapping = pci_map_page(ap->pdev, frag->page,
2531 frag->page_offset, frag->size,
2532 PCI_DMA_TODEVICE);
2533
2534 flagsize = (frag->size << 16);
84fa7933 2535 if (skb->ip_summed == CHECKSUM_PARTIAL)
1da177e4
LT		 2536 flagsize |= BD_FLG_TCP_UDP_SUM;
2537 idx = (idx + 1) % ACE_TX_RING_ENTRIES(ap);
2538
2539 if (i == skb_shinfo(skb)->nr_frags - 1) {
2540 flagsize |= BD_FLG_END;
2541 if (tx_ring_full(ap, ap->tx_ret_csm, idx))
2542 flagsize |= BD_FLG_COAL_NOW;
2543
2544 /*
2545 * Only the last fragment frees
2546 * the skb!
2547 */
2548 info->skb = skb;
2549 } else {
2550 info->skb = NULL;
2551 }
2552 pci_unmap_addr_set(info, mapping, mapping);
2553 pci_unmap_len_set(info, maplen, frag->size);
2554 ace_load_tx_bd(ap, desc, mapping, flagsize, vlan_tag);
2555 }
2556 }
2557
2558 wmb();
2559 ap->tx_prd = idx;
2560 ace_set_txprd(regs, ap, idx);
2561
2562 if (flagsize & BD_FLG_COAL_NOW) {
2563 netif_stop_queue(dev);
2564
2565 /*
2566 * A TX-descriptor producer (an IRQ) might have gotten
2567 * inbetween, making the ring free again. Since xmit is
2568 * serialized, this is the only situation we have to
2569 * re-test.
2570 */
2571 if (!tx_ring_full(ap, ap->tx_ret_csm, idx))
2572 netif_wake_queue(dev);
2573 }
2574
2575 dev->trans_start = jiffies;
2576 return NETDEV_TX_OK;
2577
2578overflow:
2579 /*
2580 * This race condition is unavoidable with lock-free drivers.
2581 * We wake up the queue _before_ tx_prd is advanced, so that we can
2582 * enter hard_start_xmit too early, while tx ring still looks closed.
2583 * This happens ~1-4 times per 100000 packets, so that we can allow
2584 * to loop syncing to other CPU. Probably, we need an additional
2585 * wmb() in ace_tx_intr as well.
2586 *
2587 * Note that this race is relieved by reserving one more entry
2588 * in tx ring than it is necessary (see original non-SG driver).
2589 * However, with SG we need to reserve 2*MAX_SKB_FRAGS+1, which
2590 * is already overkill.
2591 *
2592 * Alternative is to return with 1 not throttling queue. In this
2593 * case loop becomes longer, no more useful effects.
2594 */
2595 if (time_before(jiffies, maxjiff)) {
2596 barrier();
2597 cpu_relax();
2598 goto restart;
2599 }
6aa20a22 2600
1da177e4
LT		 2601 /* The ring is stuck full. */
2602 printk(KERN_WARNING "%s: Transmit ring stuck full\n", dev->name);
2603 return NETDEV_TX_BUSY;
2604}
2605
2606
2607static int ace_change_mtu(struct net_device *dev, int new_mtu)
2608{
2609 struct ace_private *ap = netdev_priv(dev);
2610 struct ace_regs __iomem *regs = ap->regs;
2611
2612 if (new_mtu > ACE_JUMBO_MTU)
2613 return -EINVAL;
2614
2615 writel(new_mtu + ETH_HLEN + 4, &regs->IfMtu);
2616 dev->mtu = new_mtu;
2617
2618 if (new_mtu > ACE_STD_MTU) {
2619 if (!(ap->jumbo)) {
2620 printk(KERN_INFO "%s: Enabling Jumbo frame "
2621 "support\n", dev->name);
2622 ap->jumbo = 1;
2623 if (!test_and_set_bit(0, &ap->jumbo_refill_busy))
2624 ace_load_jumbo_rx_ring(ap, RX_JUMBO_SIZE);
2625 ace_set_rxtx_parms(dev, 1);
2626 }
2627 } else {
2628 while (test_and_set_bit(0, &ap->jumbo_refill_busy));
2629 ace_sync_irq(dev->irq);
2630 ace_set_rxtx_parms(dev, 0);
2631 if (ap->jumbo) {
2632 struct cmd cmd;
2633
2634 cmd.evt = C_RESET_JUMBO_RNG;
2635 cmd.code = 0;
2636 cmd.idx = 0;
2637 ace_issue_cmd(regs, &cmd);
2638 }
2639 }
2640
2641 return 0;
2642}
2643
2644static int ace_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
2645{
2646 struct ace_private *ap = netdev_priv(dev);
2647 struct ace_regs __iomem *regs = ap->regs;
2648 u32 link;
2649
2650 memset(ecmd, 0, sizeof(struct ethtool_cmd));
2651 ecmd->supported =
2652 (SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full |
2653 SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full |
2654 SUPPORTED_1000baseT_Half | SUPPORTED_1000baseT_Full |
2655 SUPPORTED_Autoneg | SUPPORTED_FIBRE);
2656
2657 ecmd->port = PORT_FIBRE;
2658 ecmd->transceiver = XCVR_INTERNAL;
2659
2660 link = readl(&regs->GigLnkState);
2661 if (link & LNK_1000MB)
2662 ecmd->speed = SPEED_1000;
2663 else {
2664 link = readl(&regs->FastLnkState);
2665 if (link & LNK_100MB)
2666 ecmd->speed = SPEED_100;
2667 else if (link & LNK_10MB)
2668 ecmd->speed = SPEED_10;
2669 else
2670 ecmd->speed = 0;
2671 }
2672 if (link & LNK_FULL_DUPLEX)
2673 ecmd->duplex = DUPLEX_FULL;
2674 else
2675 ecmd->duplex = DUPLEX_HALF;
2676
2677 if (link & LNK_NEGOTIATE)
2678 ecmd->autoneg = AUTONEG_ENABLE;
2679 else
2680 ecmd->autoneg = AUTONEG_DISABLE;
2681
2682#if 0
2683 /*
2684 * Current struct ethtool_cmd is insufficient
2685 */
2686 ecmd->trace = readl(&regs->TuneTrace);
2687
2688 ecmd->txcoal = readl(&regs->TuneTxCoalTicks);
2689 ecmd->rxcoal = readl(&regs->TuneRxCoalTicks);
2690#endif
2691 ecmd->maxtxpkt = readl(&regs->TuneMaxTxDesc);
2692 ecmd->maxrxpkt = readl(&regs->TuneMaxRxDesc);
2693
2694 return 0;
2695}
2696
2697static int ace_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
2698{
2699 struct ace_private *ap = netdev_priv(dev);
2700 struct ace_regs __iomem *regs = ap->regs;
2701 u32 link, speed;
2702
2703 link = readl(&regs->GigLnkState);
2704 if (link & LNK_1000MB)
2705 speed = SPEED_1000;
2706 else {
2707 link = readl(&regs->FastLnkState);
2708 if (link & LNK_100MB)
2709 speed = SPEED_100;
2710 else if (link & LNK_10MB)
2711 speed = SPEED_10;
2712 else
2713 speed = SPEED_100;
2714 }
2715
2716 link = LNK_ENABLE | LNK_1000MB | LNK_100MB | LNK_10MB |
2717 LNK_RX_FLOW_CTL_Y | LNK_NEG_FCTL;
2718 if (!ACE_IS_TIGON_I(ap))
2719 link |= LNK_TX_FLOW_CTL_Y;
2720 if (ecmd->autoneg == AUTONEG_ENABLE)
2721 link |= LNK_NEGOTIATE;
2722 if (ecmd->speed != speed) {
2723 link &= ~(LNK_1000MB | LNK_100MB | LNK_10MB);
2724 switch (speed) {
2725 case SPEED_1000:
2726 link |= LNK_1000MB;
2727 break;
2728 case SPEED_100:
2729 link |= LNK_100MB;
2730 break;
2731 case SPEED_10:
2732 link |= LNK_10MB;
2733 break;
2734 }
2735 }
2736
2737 if (ecmd->duplex == DUPLEX_FULL)
2738 link |= LNK_FULL_DUPLEX;
2739
2740 if (link != ap->link) {
2741 struct cmd cmd;
2742 printk(KERN_INFO "%s: Renegotiating link state\n",
2743 dev->name);
2744
2745 ap->link = link;
2746 writel(link, &regs->TuneLink);
2747 if (!ACE_IS_TIGON_I(ap))
2748 writel(link, &regs->TuneFastLink);
2749 wmb();
2750
2751 cmd.evt = C_LNK_NEGOTIATION;
2752 cmd.code = 0;
2753 cmd.idx = 0;
2754 ace_issue_cmd(regs, &cmd);
2755 }
2756 return 0;
2757}
2758
6aa20a22 2759static void ace_get_drvinfo(struct net_device *dev,
1da177e4
LT		 2760 struct ethtool_drvinfo *info)
2761{
2762 struct ace_private *ap = netdev_priv(dev);
2763
2764 strlcpy(info->driver, "acenic", sizeof(info->driver));
6aa20a22 2765 snprintf(info->version, sizeof(info->version), "%i.%i.%i",
1da177e4
LT		 2766 tigonFwReleaseMajor, tigonFwReleaseMinor,
2767 tigonFwReleaseFix);
2768
2769 if (ap->pdev)
6aa20a22 2770 strlcpy(info->bus_info, pci_name(ap->pdev),
1da177e4
LT		 2771 sizeof(info->bus_info));
2772
2773}
2774
2775/*
2776 * Set the hardware MAC address.
2777 */
2778static int ace_set_mac_addr(struct net_device *dev, void *p)
2779{
2780 struct ace_private *ap = netdev_priv(dev);
2781 struct ace_regs __iomem *regs = ap->regs;
2782 struct sockaddr *addr=p;
2783 u8 *da;
2784 struct cmd cmd;
2785
2786 if(netif_running(dev))
2787 return -EBUSY;
2788
2789 memcpy(dev->dev_addr, addr->sa_data,dev->addr_len);
2790
2791 da = (u8 *)dev->dev_addr;
2792
2793 writel(da[0] << 8 | da[1], &regs->MacAddrHi);
2794 writel((da[2] << 24) | (da[3] << 16) | (da[4] << 8) | da[5],
2795 &regs->MacAddrLo);
2796
2797 cmd.evt = C_SET_MAC_ADDR;
2798 cmd.code = 0;
2799 cmd.idx = 0;
2800 ace_issue_cmd(regs, &cmd);
2801
2802 return 0;
2803}
2804
2805
2806static void ace_set_multicast_list(struct net_device *dev)
2807{
2808 struct ace_private *ap = netdev_priv(dev);
2809 struct ace_regs __iomem *regs = ap->regs;
2810 struct cmd cmd;
2811
2812 if ((dev->flags & IFF_ALLMULTI) && !(ap->mcast_all)) {
2813 cmd.evt = C_SET_MULTICAST_MODE;
2814 cmd.code = C_C_MCAST_ENABLE;
2815 cmd.idx = 0;
2816 ace_issue_cmd(regs, &cmd);
2817 ap->mcast_all = 1;
2818 } else if (ap->mcast_all) {
2819 cmd.evt = C_SET_MULTICAST_MODE;
2820 cmd.code = C_C_MCAST_DISABLE;
2821 cmd.idx = 0;
2822 ace_issue_cmd(regs, &cmd);
2823 ap->mcast_all = 0;
2824 }
2825
2826 if ((dev->flags & IFF_PROMISC) && !(ap->promisc)) {
2827 cmd.evt = C_SET_PROMISC_MODE;
2828 cmd.code = C_C_PROMISC_ENABLE;
2829 cmd.idx = 0;
2830 ace_issue_cmd(regs, &cmd);
2831 ap->promisc = 1;
2832 }else if (!(dev->flags & IFF_PROMISC) && (ap->promisc)) {
2833 cmd.evt = C_SET_PROMISC_MODE;
2834 cmd.code = C_C_PROMISC_DISABLE;
2835 cmd.idx = 0;
2836 ace_issue_cmd(regs, &cmd);
2837 ap->promisc = 0;
2838 }
2839
2840 /*
2841 * For the time being multicast relies on the upper layers
2842 * filtering it properly. The Firmware does not allow one to
2843 * set the entire multicast list at a time and keeping track of
2844 * it here is going to be messy.
2845 */
2846 if ((dev->mc_count) && !(ap->mcast_all)) {
2847 cmd.evt = C_SET_MULTICAST_MODE;
2848 cmd.code = C_C_MCAST_ENABLE;
2849 cmd.idx = 0;
2850 ace_issue_cmd(regs, &cmd);
2851 }else if (!ap->mcast_all) {
2852 cmd.evt = C_SET_MULTICAST_MODE;
2853 cmd.code = C_C_MCAST_DISABLE;
2854 cmd.idx = 0;
2855 ace_issue_cmd(regs, &cmd);
2856 }
2857}
2858
2859
2860static struct net_device_stats *ace_get_stats(struct net_device *dev)
2861{
2862 struct ace_private *ap = netdev_priv(dev);
2863 struct ace_mac_stats __iomem *mac_stats =
2864 (struct ace_mac_stats __iomem *)ap->regs->Stats;
2865
2866 ap->stats.rx_missed_errors = readl(&mac_stats->drop_space);
2867 ap->stats.multicast = readl(&mac_stats->kept_mc);
2868 ap->stats.collisions = readl(&mac_stats->coll);
2869
2870 return &ap->stats;
2871}
2872
2873
2874static void __devinit ace_copy(struct ace_regs __iomem *regs, void *src,
2875 u32 dest, int size)
2876{
2877 void __iomem *tdest;
2878 u32 *wsrc;
2879 short tsize, i;
2880
2881 if (size <= 0)
2882 return;
2883
2884 while (size > 0) {
2885 tsize = min_t(u32, ((~dest & (ACE_WINDOW_SIZE - 1)) + 1),
2886 min_t(u32, size, ACE_WINDOW_SIZE));
6aa20a22 2887 tdest = (void __iomem *) &regs->Window +
1da177e4
LT		 2888 (dest & (ACE_WINDOW_SIZE - 1));
2889 writel(dest & ~(ACE_WINDOW_SIZE - 1), &regs->WinBase);
2890 /*
2891 * This requires byte swapping on big endian, however
2892 * writel does that for us
2893 */
2894 wsrc = src;
2895 for (i = 0; i < (tsize / 4); i++) {
2896 writel(wsrc[i], tdest + i*4);
2897 }
2898 dest += tsize;
2899 src += tsize;
2900 size -= tsize;
2901 }
2902
2903 return;
2904}
2905
2906
2907static void __devinit ace_clear(struct ace_regs __iomem *regs, u32 dest, int size)
2908{
2909 void __iomem *tdest;
2910 short tsize = 0, i;
2911
2912 if (size <= 0)
2913 return;
2914
2915 while (size > 0) {
2916 tsize = min_t(u32, ((~dest & (ACE_WINDOW_SIZE - 1)) + 1),
2917 min_t(u32, size, ACE_WINDOW_SIZE));
6aa20a22 2918 tdest = (void __iomem *) &regs->Window +
1da177e4
LT		 2919 (dest & (ACE_WINDOW_SIZE - 1));
2920 writel(dest & ~(ACE_WINDOW_SIZE - 1), &regs->WinBase);
2921
2922 for (i = 0; i < (tsize / 4); i++) {
2923 writel(0, tdest + i*4);
2924 }
2925
2926 dest += tsize;
2927 size -= tsize;
2928 }
2929
2930 return;
2931}
2932
2933
2934/*
2935 * Download the firmware into the SRAM on the NIC
2936 *
2937 * This operation requires the NIC to be halted and is performed with
2938 * interrupts disabled and with the spinlock hold.
2939 */
ddfce6bb 2940static int __devinit ace_load_firmware(struct net_device *dev)
1da177e4
LT		 2941{
2942 struct ace_private *ap = netdev_priv(dev);
2943 struct ace_regs __iomem *regs = ap->regs;
2944
2945 if (!(readl(&regs->CpuCtrl) & CPU_HALTED)) {
2946 printk(KERN_ERR "%s: trying to download firmware while the "
2947 "CPU is running!\n", ap->name);
2948 return -EFAULT;
2949 }
2950
2951 /*
2952 * Do not try to clear more than 512KB or we end up seeing
2953 * funny things on NICs with only 512KB SRAM
2954 */
2955 ace_clear(regs, 0x2000, 0x80000-0x2000);
2956 if (ACE_IS_TIGON_I(ap)) {
2957 ace_copy(regs, tigonFwText, tigonFwTextAddr, tigonFwTextLen);
2958 ace_copy(regs, tigonFwData, tigonFwDataAddr, tigonFwDataLen);
2959 ace_copy(regs, tigonFwRodata, tigonFwRodataAddr,
2960 tigonFwRodataLen);
2961 ace_clear(regs, tigonFwBssAddr, tigonFwBssLen);
2962 ace_clear(regs, tigonFwSbssAddr, tigonFwSbssLen);
2963 }else if (ap->version == 2) {
2964 ace_clear(regs, tigon2FwBssAddr, tigon2FwBssLen);
2965 ace_clear(regs, tigon2FwSbssAddr, tigon2FwSbssLen);
2966 ace_copy(regs, tigon2FwText, tigon2FwTextAddr,tigon2FwTextLen);
2967 ace_copy(regs, tigon2FwRodata, tigon2FwRodataAddr,
2968 tigon2FwRodataLen);
2969 ace_copy(regs, tigon2FwData, tigon2FwDataAddr,tigon2FwDataLen);
2970 }
2971
2972 return 0;
2973}
2974
2975
2976/*
2977 * The eeprom on the AceNIC is an Atmel i2c EEPROM.
2978 *
2979 * Accessing the EEPROM is `interesting' to say the least - don't read
2980 * this code right after dinner.
2981 *
2982 * This is all about black magic and bit-banging the device .... I
2983 * wonder in what hospital they have put the guy who designed the i2c
2984 * specs.
2985 *
2986 * Oh yes, this is only the beginning!
2987 *
2988 * Thanks to Stevarino Webinski for helping tracking down the bugs in the
2989 * code i2c readout code by beta testing all my hacks.
2990 */
2991static void __devinit eeprom_start(struct ace_regs __iomem *regs)
2992{
2993 u32 local;
2994
2995 readl(&regs->LocalCtrl);
2996 udelay(ACE_SHORT_DELAY);
2997 local = readl(&regs->LocalCtrl);
2998 local |= EEPROM_DATA_OUT | EEPROM_WRITE_ENABLE;
2999 writel(local, &regs->LocalCtrl);
3000 readl(&regs->LocalCtrl);
3001 mb();
3002 udelay(ACE_SHORT_DELAY);
3003 local |= EEPROM_CLK_OUT;
3004 writel(local, &regs->LocalCtrl);
3005 readl(&regs->LocalCtrl);
3006 mb();
3007 udelay(ACE_SHORT_DELAY);
3008 local &= ~EEPROM_DATA_OUT;
3009 writel(local, &regs->LocalCtrl);
3010 readl(&regs->LocalCtrl);
3011 mb();
3012 udelay(ACE_SHORT_DELAY);
3013 local &= ~EEPROM_CLK_OUT;
3014 writel(local, &regs->LocalCtrl);
3015 readl(&regs->LocalCtrl);
3016 mb();
3017}
3018
3019
3020static void __devinit eeprom_prep(struct ace_regs __iomem *regs, u8 magic)
3021{
3022 short i;
3023 u32 local;
3024
3025 udelay(ACE_SHORT_DELAY);
3026 local = readl(&regs->LocalCtrl);
3027 local &= ~EEPROM_DATA_OUT;
3028 local |= EEPROM_WRITE_ENABLE;
3029 writel(local, &regs->LocalCtrl);
3030 readl(&regs->LocalCtrl);
3031 mb();
3032
3033 for (i = 0; i < 8; i++, magic <<= 1) {
3034 udelay(ACE_SHORT_DELAY);
6aa20a22 3035 if (magic & 0x80)
1da177e4
LT		 3036 local |= EEPROM_DATA_OUT;
3037 else
3038 local &= ~EEPROM_DATA_OUT;
3039 writel(local, &regs->LocalCtrl);
3040 readl(&regs->LocalCtrl);
3041 mb();
3042
3043 udelay(ACE_SHORT_DELAY);
3044 local |= EEPROM_CLK_OUT;
3045 writel(local, &regs->LocalCtrl);
3046 readl(&regs->LocalCtrl);
3047 mb();
3048 udelay(ACE_SHORT_DELAY);
3049 local &= ~(EEPROM_CLK_OUT | EEPROM_DATA_OUT);
3050 writel(local, &regs->LocalCtrl);
3051 readl(&regs->LocalCtrl);
3052 mb();
3053 }
3054}
3055
3056
3057static int __devinit eeprom_check_ack(struct ace_regs __iomem *regs)
3058{
3059 int state;
3060 u32 local;
3061
3062 local = readl(&regs->LocalCtrl);
3063 local &= ~EEPROM_WRITE_ENABLE;
3064 writel(local, &regs->LocalCtrl);
3065 readl(&regs->LocalCtrl);
3066 mb();
3067 udelay(ACE_LONG_DELAY);
3068 local |= EEPROM_CLK_OUT;
3069 writel(local, &regs->LocalCtrl);
3070 readl(&regs->LocalCtrl);
3071 mb();
3072 udelay(ACE_SHORT_DELAY);
3073 /* sample data in middle of high clk */
3074 state = (readl(&regs->LocalCtrl) & EEPROM_DATA_IN) != 0;
3075 udelay(ACE_SHORT_DELAY);
3076 mb();
3077 writel(readl(&regs->LocalCtrl) & ~EEPROM_CLK_OUT, &regs->LocalCtrl);
3078 readl(&regs->LocalCtrl);
3079 mb();
3080
3081 return state;
3082}
3083
3084
3085static void __devinit eeprom_stop(struct ace_regs __iomem *regs)
3086{
3087 u32 local;
3088
3089 udelay(ACE_SHORT_DELAY);
3090 local = readl(&regs->LocalCtrl);
3091 local |= EEPROM_WRITE_ENABLE;
3092 writel(local, &regs->LocalCtrl);
3093 readl(&regs->LocalCtrl);
3094 mb();
3095 udelay(ACE_SHORT_DELAY);
3096 local &= ~EEPROM_DATA_OUT;
3097 writel(local, &regs->LocalCtrl);
3098 readl(&regs->LocalCtrl);
3099 mb();
3100 udelay(ACE_SHORT_DELAY);
3101 local |= EEPROM_CLK_OUT;
3102 writel(local, &regs->LocalCtrl);
3103 readl(&regs->LocalCtrl);
3104 mb();
3105 udelay(ACE_SHORT_DELAY);
3106 local |= EEPROM_DATA_OUT;
3107 writel(local, &regs->LocalCtrl);
3108 readl(&regs->LocalCtrl);
3109 mb();
3110 udelay(ACE_LONG_DELAY);
3111 local &= ~EEPROM_CLK_OUT;
3112 writel(local, &regs->LocalCtrl);
3113 mb();
3114}
3115
3116
3117/*
3118 * Read a whole byte from the EEPROM.
3119 */
3120static int __devinit read_eeprom_byte(struct net_device *dev,
3121 unsigned long offset)
3122{
3123 struct ace_private *ap = netdev_priv(dev);
3124 struct ace_regs __iomem *regs = ap->regs;
3125 unsigned long flags;
3126 u32 local;
3127 int result = 0;
3128 short i;
3129
1da177e4
LT		 3130 /*
3131 * Don't take interrupts on this CPU will bit banging
3132 * the %#%#@$ I2C device
3133 */
3134 local_irq_save(flags);
3135
3136 eeprom_start(regs);
3137
3138 eeprom_prep(regs, EEPROM_WRITE_SELECT);
3139 if (eeprom_check_ack(regs)) {
3140 local_irq_restore(flags);
3141 printk(KERN_ERR "%s: Unable to sync eeprom\n", ap->name);
3142 result = -EIO;
3143 goto eeprom_read_error;
3144 }
3145
3146 eeprom_prep(regs, (offset >> 8) & 0xff);
3147 if (eeprom_check_ack(regs)) {
3148 local_irq_restore(flags);
3149 printk(KERN_ERR "%s: Unable to set address byte 0\n",
3150 ap->name);
3151 result = -EIO;
3152 goto eeprom_read_error;
3153 }
3154
3155 eeprom_prep(regs, offset & 0xff);
3156 if (eeprom_check_ack(regs)) {
3157 local_irq_restore(flags);
3158 printk(KERN_ERR "%s: Unable to set address byte 1\n",
3159 ap->name);
3160 result = -EIO;
3161 goto eeprom_read_error;
3162 }
3163
3164 eeprom_start(regs);
3165 eeprom_prep(regs, EEPROM_READ_SELECT);
3166 if (eeprom_check_ack(regs)) {
3167 local_irq_restore(flags);
3168 printk(KERN_ERR "%s: Unable to set READ_SELECT\n",
3169 ap->name);
3170 result = -EIO;
3171 goto eeprom_read_error;
3172 }
3173
3174 for (i = 0; i < 8; i++) {
3175 local = readl(&regs->LocalCtrl);
3176 local &= ~EEPROM_WRITE_ENABLE;
3177 writel(local, &regs->LocalCtrl);
3178 readl(&regs->LocalCtrl);
3179 udelay(ACE_LONG_DELAY);
3180 mb();
3181 local |= EEPROM_CLK_OUT;
3182 writel(local, &regs->LocalCtrl);
3183 readl(&regs->LocalCtrl);
3184 mb();
3185 udelay(ACE_SHORT_DELAY);
3186 /* sample data mid high clk */
3187 result = (result << 1) |
3188 ((readl(&regs->LocalCtrl) & EEPROM_DATA_IN) != 0);
3189 udelay(ACE_SHORT_DELAY);
3190 mb();
3191 local = readl(&regs->LocalCtrl);
3192 local &= ~EEPROM_CLK_OUT;
3193 writel(local, &regs->LocalCtrl);
3194 readl(&regs->LocalCtrl);
3195 udelay(ACE_SHORT_DELAY);
3196 mb();
3197 if (i == 7) {
3198 local |= EEPROM_WRITE_ENABLE;
3199 writel(local, &regs->LocalCtrl);
3200 readl(&regs->LocalCtrl);
3201 mb();
3202 udelay(ACE_SHORT_DELAY);
3203 }
3204 }
3205
3206 local |= EEPROM_DATA_OUT;
3207 writel(local, &regs->LocalCtrl);
3208 readl(&regs->LocalCtrl);
3209 mb();
3210 udelay(ACE_SHORT_DELAY);
3211 writel(readl(&regs->LocalCtrl) | EEPROM_CLK_OUT, &regs->LocalCtrl);
3212 readl(&regs->LocalCtrl);
3213 udelay(ACE_LONG_DELAY);
3214 writel(readl(&regs->LocalCtrl) & ~EEPROM_CLK_OUT, &regs->LocalCtrl);
3215 readl(&regs->LocalCtrl);
3216 mb();
3217 udelay(ACE_SHORT_DELAY);
3218 eeprom_stop(regs);
3219
3220 local_irq_restore(flags);
3221 out:
3222 return result;
3223
3224 eeprom_read_error:
3225 printk(KERN_ERR "%s: Unable to read eeprom byte 0x%02lx\n",
3226 ap->name, offset);
3227 goto out;
3228}
3229
3230
3231/*
3232 * Local variables:
3233 * compile-command: "gcc -D__SMP__ -D__KERNEL__ -DMODULE -I../../include -Wall -Wstrict-prototypes -O2 -fomit-frame-pointer -pipe -fno-strength-reduce -DMODVERSIONS -include ../../include/linux/modversions.h -c -o acenic.o acenic.c"
3234 * End:
3235 */
Linux kernel - Deliverables
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