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Merge branch 'splice' of git://brick.kernel.dk/data/git/linux-2.6-block
[deliverable/linux.git] / drivers / net / acenic.c
CommitLineData
1da177e4
LT		 1/*
2 * acenic.c: Linux driver for the Alteon AceNIC Gigabit Ethernet card
3 * and other Tigon based cards.
4 *
5 * Copyright 1998-2002 by Jes Sorensen, <jes@trained-monkey.org>.
6 *
7 * Thanks to Alteon and 3Com for providing hardware and documentation
8 * enabling me to write this driver.
9 *
10 * A mailing list for discussing the use of this driver has been
11 * setup, please subscribe to the lists if you have any questions
12 * about the driver. Send mail to linux-acenic-help@sunsite.auc.dk to
13 * see how to subscribe.
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License as published by
17 * the Free Software Foundation; either version 2 of the License, or
18 * (at your option) any later version.
19 *
20 * Additional credits:
21 * Pete Wyckoff <wyckoff@ca.sandia.gov>: Initial Linux/Alpha and trace
22 * dump support. The trace dump support has not been
23 * integrated yet however.
24 * Troy Benjegerdes: Big Endian (PPC) patches.
25 * Nate Stahl: Better out of memory handling and stats support.
26 * Aman Singla: Nasty race between interrupt handler and tx code dealing
27 * with 'testing the tx_ret_csm and setting tx_full'
28 * David S. Miller <davem@redhat.com>: conversion to new PCI dma mapping
29 * infrastructure and Sparc support
30 * Pierrick Pinasseau (CERN): For lending me an Ultra 5 to test the
31 * driver under Linux/Sparc64
32 * Matt Domsch <Matt_Domsch@dell.com>: Detect Alteon 1000baseT cards
33 * ETHTOOL_GDRVINFO support
34 * Chip Salzenberg <chip@valinux.com>: Fix race condition between tx
35 * handler and close() cleanup.
36 * Ken Aaker <kdaaker@rchland.vnet.ibm.com>: Correct check for whether
37 * memory mapped IO is enabled to
38 * make the driver work on RS/6000.
39 * Takayoshi Kouchi <kouchi@hpc.bs1.fc.nec.co.jp>: Identifying problem
40 * where the driver would disable
41 * bus master mode if it had to disable
42 * write and invalidate.
43 * Stephen Hack <stephen_hack@hp.com>: Fixed ace_set_mac_addr for little
44 * endian systems.
45 * Val Henson <vhenson@esscom.com>: Reset Jumbo skb producer and
46 * rx producer index when
47 * flushing the Jumbo ring.
48 * Hans Grobler <grobh@sun.ac.za>: Memory leak fixes in the
49 * driver init path.
50 * Grant Grundler <grundler@cup.hp.com>: PCI write posting fixes.
51 */
52
53#include <linux/config.h>
54#include <linux/module.h>
55#include <linux/moduleparam.h>
56#include <linux/version.h>
57#include <linux/types.h>
58#include <linux/errno.h>
59#include <linux/ioport.h>
60#include <linux/pci.h>
1e7f0bd8 61#include <linux/dma-mapping.h>
1da177e4
LT		 62#include <linux/kernel.h>
63#include <linux/netdevice.h>
64#include <linux/etherdevice.h>
65#include <linux/skbuff.h>
66#include <linux/init.h>
67#include <linux/delay.h>
68#include <linux/mm.h>
69#include <linux/highmem.h>
70#include <linux/sockios.h>
71
72#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
73#include <linux/if_vlan.h>
74#endif
75
76#ifdef SIOCETHTOOL
77#include <linux/ethtool.h>
78#endif
79
80#include <net/sock.h>
81#include <net/ip.h>
82
83#include <asm/system.h>
84#include <asm/io.h>
85#include <asm/irq.h>
86#include <asm/byteorder.h>
87#include <asm/uaccess.h>
88
89
90#define DRV_NAME "acenic"
91
92#undef INDEX_DEBUG
93
94#ifdef CONFIG_ACENIC_OMIT_TIGON_I
95#define ACE_IS_TIGON_I(ap) 0
96#define ACE_TX_RING_ENTRIES(ap) MAX_TX_RING_ENTRIES
97#else
98#define ACE_IS_TIGON_I(ap) (ap->version == 1)
99#define ACE_TX_RING_ENTRIES(ap) ap->tx_ring_entries
100#endif
101
102#ifndef PCI_VENDOR_ID_ALTEON
103#define PCI_VENDOR_ID_ALTEON 0x12ae
104#endif
105#ifndef PCI_DEVICE_ID_ALTEON_ACENIC_FIBRE
106#define PCI_DEVICE_ID_ALTEON_ACENIC_FIBRE 0x0001
107#define PCI_DEVICE_ID_ALTEON_ACENIC_COPPER 0x0002
108#endif
109#ifndef PCI_DEVICE_ID_3COM_3C985
110#define PCI_DEVICE_ID_3COM_3C985 0x0001
111#endif
112#ifndef PCI_VENDOR_ID_NETGEAR
113#define PCI_VENDOR_ID_NETGEAR 0x1385
114#define PCI_DEVICE_ID_NETGEAR_GA620 0x620a
115#endif
116#ifndef PCI_DEVICE_ID_NETGEAR_GA620T
117#define PCI_DEVICE_ID_NETGEAR_GA620T 0x630a
118#endif
119
120
121/*
122 * Farallon used the DEC vendor ID by mistake and they seem not
123 * to care - stinky!
124 */
125#ifndef PCI_DEVICE_ID_FARALLON_PN9000SX
126#define PCI_DEVICE_ID_FARALLON_PN9000SX 0x1a
127#endif
128#ifndef PCI_DEVICE_ID_FARALLON_PN9100T
129#define PCI_DEVICE_ID_FARALLON_PN9100T 0xfa
130#endif
131#ifndef PCI_VENDOR_ID_SGI
132#define PCI_VENDOR_ID_SGI 0x10a9
133#endif
134#ifndef PCI_DEVICE_ID_SGI_ACENIC
135#define PCI_DEVICE_ID_SGI_ACENIC 0x0009
136#endif
137
138static struct pci_device_id acenic_pci_tbl[] = {
139 { PCI_VENDOR_ID_ALTEON, PCI_DEVICE_ID_ALTEON_ACENIC_FIBRE,
140 PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_NETWORK_ETHERNET << 8, 0xffff00, },
141 { PCI_VENDOR_ID_ALTEON, PCI_DEVICE_ID_ALTEON_ACENIC_COPPER,
142 PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_NETWORK_ETHERNET << 8, 0xffff00, },
143 { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3C985,
144 PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_NETWORK_ETHERNET << 8, 0xffff00, },
145 { PCI_VENDOR_ID_NETGEAR, PCI_DEVICE_ID_NETGEAR_GA620,
146 PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_NETWORK_ETHERNET << 8, 0xffff00, },
147 { PCI_VENDOR_ID_NETGEAR, PCI_DEVICE_ID_NETGEAR_GA620T,
148 PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_NETWORK_ETHERNET << 8, 0xffff00, },
149 /*
150 * Farallon used the DEC vendor ID on their cards incorrectly,
151 * then later Alteon's ID.
152 */
153 { PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_FARALLON_PN9000SX,
154 PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_NETWORK_ETHERNET << 8, 0xffff00, },
155 { PCI_VENDOR_ID_ALTEON, PCI_DEVICE_ID_FARALLON_PN9100T,
156 PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_NETWORK_ETHERNET << 8, 0xffff00, },
157 { PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_ACENIC,
158 PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_NETWORK_ETHERNET << 8, 0xffff00, },
159 { }
160};
161MODULE_DEVICE_TABLE(pci, acenic_pci_tbl);
162
163#ifndef SET_NETDEV_DEV
164#define SET_NETDEV_DEV(net, pdev) do{} while(0)
165#endif
166
167#if LINUX_VERSION_CODE >= 0x2051c
168#define ace_sync_irq(irq) synchronize_irq(irq)
169#else
170#define ace_sync_irq(irq) synchronize_irq()
171#endif
172
173#ifndef offset_in_page
174#define offset_in_page(ptr) ((unsigned long)(ptr) & ~PAGE_MASK)
175#endif
176
177#define ACE_MAX_MOD_PARMS 8
178#define BOARD_IDX_STATIC 0
179#define BOARD_IDX_OVERFLOW -1
180
181#if (defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)) && \
182 defined(NETIF_F_HW_VLAN_RX)
183#define ACENIC_DO_VLAN 1
184#define ACE_RCB_VLAN_FLAG RCB_FLG_VLAN_ASSIST
185#else
186#define ACENIC_DO_VLAN 0
187#define ACE_RCB_VLAN_FLAG 0
188#endif
189
190#include "acenic.h"
191
192/*
193 * These must be defined before the firmware is included.
194 */
195#define MAX_TEXT_LEN 96*1024
196#define MAX_RODATA_LEN 8*1024
197#define MAX_DATA_LEN 2*1024
198
199#include "acenic_firmware.h"
200
201#ifndef tigon2FwReleaseLocal
202#define tigon2FwReleaseLocal 0
203#endif
204
205/*
206 * This driver currently supports Tigon I and Tigon II based cards
207 * including the Alteon AceNIC, the 3Com 3C985[B] and NetGear
208 * GA620. The driver should also work on the SGI, DEC and Farallon
209 * versions of the card, however I have not been able to test that
210 * myself.
211 *
212 * This card is really neat, it supports receive hardware checksumming
213 * and jumbo frames (up to 9000 bytes) and does a lot of work in the
214 * firmware. Also the programming interface is quite neat, except for
215 * the parts dealing with the i2c eeprom on the card ;-)
216 *
217 * Using jumbo frames:
218 *
219 * To enable jumbo frames, simply specify an mtu between 1500 and 9000
220 * bytes to ifconfig. Jumbo frames can be enabled or disabled at any time
221 * by running `ifconfig eth<X> mtu <MTU>' with <X> being the Ethernet
222 * interface number and <MTU> being the MTU value.
223 *
224 * Module parameters:
225 *
226 * When compiled as a loadable module, the driver allows for a number
227 * of module parameters to be specified. The driver supports the
228 * following module parameters:
229 *
230 * trace=<val> - Firmware trace level. This requires special traced
231 * firmware to replace the firmware supplied with
232 * the driver - for debugging purposes only.
233 *
234 * link=<val> - Link state. Normally you want to use the default link
235 * parameters set by the driver. This can be used to
236 * override these in case your switch doesn't negotiate
237 * the link properly. Valid values are:
238 * 0x0001 - Force half duplex link.
239 * 0x0002 - Do not negotiate line speed with the other end.
240 * 0x0010 - 10Mbit/sec link.
241 * 0x0020 - 100Mbit/sec link.
242 * 0x0040 - 1000Mbit/sec link.
243 * 0x0100 - Do not negotiate flow control.
244 * 0x0200 - Enable RX flow control Y
245 * 0x0400 - Enable TX flow control Y (Tigon II NICs only).
246 * Default value is 0x0270, ie. enable link+flow
247 * control negotiation. Negotiating the highest
248 * possible link speed with RX flow control enabled.
249 *
250 * When disabling link speed negotiation, only one link
251 * speed is allowed to be specified!
252 *
253 * tx_coal_tick=<val> - number of coalescing clock ticks (us) allowed
254 * to wait for more packets to arive before
255 * interrupting the host, from the time the first
256 * packet arrives.
257 *
258 * rx_coal_tick=<val> - number of coalescing clock ticks (us) allowed
259 * to wait for more packets to arive in the transmit ring,
260 * before interrupting the host, after transmitting the
261 * first packet in the ring.
262 *
263 * max_tx_desc=<val> - maximum number of transmit descriptors
264 * (packets) transmitted before interrupting the host.
265 *
266 * max_rx_desc=<val> - maximum number of receive descriptors
267 * (packets) received before interrupting the host.
268 *
269 * tx_ratio=<val> - 7 bit value (0 - 63) specifying the split in 64th
270 * increments of the NIC's on board memory to be used for
271 * transmit and receive buffers. For the 1MB NIC app. 800KB
272 * is available, on the 1/2MB NIC app. 300KB is available.
273 * 68KB will always be available as a minimum for both
274 * directions. The default value is a 50/50 split.
275 * dis_pci_mem_inval=<val> - disable PCI memory write and invalidate
276 * operations, default (1) is to always disable this as
277 * that is what Alteon does on NT. I have not been able
278 * to measure any real performance differences with
279 * this on my systems. Set <val>=0 if you want to
280 * enable these operations.
281 *
282 * If you use more than one NIC, specify the parameters for the
283 * individual NICs with a comma, ie. trace=0,0x00001fff,0 you want to
284 * run tracing on NIC #2 but not on NIC #1 and #3.
285 *
286 * TODO:
287 *
288 * - Proper multicast support.
289 * - NIC dump support.
290 * - More tuning parameters.
291 *
292 * The mini ring is not used under Linux and I am not sure it makes sense
293 * to actually use it.
294 *
295 * New interrupt handler strategy:
296 *
297 * The old interrupt handler worked using the traditional method of
298 * replacing an skbuff with a new one when a packet arrives. However
299 * the rx rings do not need to contain a static number of buffer
300 * descriptors, thus it makes sense to move the memory allocation out
301 * of the main interrupt handler and do it in a bottom half handler
302 * and only allocate new buffers when the number of buffers in the
303 * ring is below a certain threshold. In order to avoid starving the
304 * NIC under heavy load it is however necessary to force allocation
305 * when hitting a minimum threshold. The strategy for alloction is as
306 * follows:
307 *
308 * RX_LOW_BUF_THRES - allocate buffers in the bottom half
309 * RX_PANIC_LOW_THRES - we are very low on buffers, allocate
310 * the buffers in the interrupt handler
311 * RX_RING_THRES - maximum number of buffers in the rx ring
312 * RX_MINI_THRES - maximum number of buffers in the mini ring
313 * RX_JUMBO_THRES - maximum number of buffers in the jumbo ring
314 *
315 * One advantagous side effect of this allocation approach is that the
316 * entire rx processing can be done without holding any spin lock
317 * since the rx rings and registers are totally independent of the tx
318 * ring and its registers. This of course includes the kmalloc's of
319 * new skb's. Thus start_xmit can run in parallel with rx processing
320 * and the memory allocation on SMP systems.
321 *
322 * Note that running the skb reallocation in a bottom half opens up
323 * another can of races which needs to be handled properly. In
324 * particular it can happen that the interrupt handler tries to run
325 * the reallocation while the bottom half is either running on another
326 * CPU or was interrupted on the same CPU. To get around this the
327 * driver uses bitops to prevent the reallocation routines from being
328 * reentered.
329 *
330 * TX handling can also be done without holding any spin lock, wheee
331 * this is fun! since tx_ret_csm is only written to by the interrupt
332 * handler. The case to be aware of is when shutting down the device
333 * and cleaning up where it is necessary to make sure that
334 * start_xmit() is not running while this is happening. Well DaveM
335 * informs me that this case is already protected against ... bye bye
336 * Mr. Spin Lock, it was nice to know you.
337 *
338 * TX interrupts are now partly disabled so the NIC will only generate
339 * TX interrupts for the number of coal ticks, not for the number of
340 * TX packets in the queue. This should reduce the number of TX only,
341 * ie. when no RX processing is done, interrupts seen.
342 */
343
344/*
345 * Threshold values for RX buffer allocation - the low water marks for
346 * when to start refilling the rings are set to 75% of the ring
347 * sizes. It seems to make sense to refill the rings entirely from the
348 * intrrupt handler once it gets below the panic threshold, that way
349 * we don't risk that the refilling is moved to another CPU when the
350 * one running the interrupt handler just got the slab code hot in its
351 * cache.
352 */
353#define RX_RING_SIZE 72
354#define RX_MINI_SIZE 64
355#define RX_JUMBO_SIZE 48
356
357#define RX_PANIC_STD_THRES 16
358#define RX_PANIC_STD_REFILL (3*RX_PANIC_STD_THRES)/2
359#define RX_LOW_STD_THRES (3*RX_RING_SIZE)/4
360#define RX_PANIC_MINI_THRES 12
361#define RX_PANIC_MINI_REFILL (3*RX_PANIC_MINI_THRES)/2
362#define RX_LOW_MINI_THRES (3*RX_MINI_SIZE)/4
363#define RX_PANIC_JUMBO_THRES 6
364#define RX_PANIC_JUMBO_REFILL (3*RX_PANIC_JUMBO_THRES)/2
365#define RX_LOW_JUMBO_THRES (3*RX_JUMBO_SIZE)/4
366
367
368/*
369 * Size of the mini ring entries, basically these just should be big
370 * enough to take TCP ACKs
371 */
372#define ACE_MINI_SIZE 100
373
374#define ACE_MINI_BUFSIZE ACE_MINI_SIZE
375#define ACE_STD_BUFSIZE (ACE_STD_MTU + ETH_HLEN + 4)
376#define ACE_JUMBO_BUFSIZE (ACE_JUMBO_MTU + ETH_HLEN + 4)
377
378/*
379 * There seems to be a magic difference in the effect between 995 and 996
380 * but little difference between 900 and 995 ... no idea why.
381 *
382 * There is now a default set of tuning parameters which is set, depending
383 * on whether or not the user enables Jumbo frames. It's assumed that if
384 * Jumbo frames are enabled, the user wants optimal tuning for that case.
385 */
386#define DEF_TX_COAL 400 /* 996 */
387#define DEF_TX_MAX_DESC 60 /* was 40 */
388#define DEF_RX_COAL 120 /* 1000 */
389#define DEF_RX_MAX_DESC 25
390#define DEF_TX_RATIO 21 /* 24 */
391
392#define DEF_JUMBO_TX_COAL 20
393#define DEF_JUMBO_TX_MAX_DESC 60
394#define DEF_JUMBO_RX_COAL 30
395#define DEF_JUMBO_RX_MAX_DESC 6
396#define DEF_JUMBO_TX_RATIO 21
397
398#if tigon2FwReleaseLocal < 20001118
399/*
400 * Standard firmware and early modifications duplicate
401 * IRQ load without this flag (coal timer is never reset).
402 * Note that with this flag tx_coal should be less than
403 * time to xmit full tx ring.
404 * 400usec is not so bad for tx ring size of 128.
405 */
406#define TX_COAL_INTS_ONLY 1 /* worth it */
407#else
408/*
409 * With modified firmware, this is not necessary, but still useful.
410 */
411#define TX_COAL_INTS_ONLY 1
412#endif
413
414#define DEF_TRACE 0
415#define DEF_STAT (2 * TICKS_PER_SEC)
416
417
418static int link[ACE_MAX_MOD_PARMS];
419static int trace[ACE_MAX_MOD_PARMS];
420static int tx_coal_tick[ACE_MAX_MOD_PARMS];
421static int rx_coal_tick[ACE_MAX_MOD_PARMS];
422static int max_tx_desc[ACE_MAX_MOD_PARMS];
423static int max_rx_desc[ACE_MAX_MOD_PARMS];
424static int tx_ratio[ACE_MAX_MOD_PARMS];
425static int dis_pci_mem_inval[ACE_MAX_MOD_PARMS] = {1, 1, 1, 1, 1, 1, 1, 1};
426
427MODULE_AUTHOR("Jes Sorensen <jes@trained-monkey.org>");
428MODULE_LICENSE("GPL");
429MODULE_DESCRIPTION("AceNIC/3C985/GA620 Gigabit Ethernet driver");
430
431module_param_array(link, int, NULL, 0);
432module_param_array(trace, int, NULL, 0);
433module_param_array(tx_coal_tick, int, NULL, 0);
434module_param_array(max_tx_desc, int, NULL, 0);
435module_param_array(rx_coal_tick, int, NULL, 0);
436module_param_array(max_rx_desc, int, NULL, 0);
437module_param_array(tx_ratio, int, NULL, 0);
438MODULE_PARM_DESC(link, "AceNIC/3C985/NetGear link state");
439MODULE_PARM_DESC(trace, "AceNIC/3C985/NetGear firmware trace level");
440MODULE_PARM_DESC(tx_coal_tick, "AceNIC/3C985/GA620 max clock ticks to wait from first tx descriptor arrives");
441MODULE_PARM_DESC(max_tx_desc, "AceNIC/3C985/GA620 max number of transmit descriptors to wait");
442MODULE_PARM_DESC(rx_coal_tick, "AceNIC/3C985/GA620 max clock ticks to wait from first rx descriptor arrives");
443MODULE_PARM_DESC(max_rx_desc, "AceNIC/3C985/GA620 max number of receive descriptors to wait");
444MODULE_PARM_DESC(tx_ratio, "AceNIC/3C985/GA620 ratio of NIC memory used for TX/RX descriptors (range 0-63)");
445
446
447static char version[] __devinitdata =
448 "acenic.c: v0.92 08/05/2002 Jes Sorensen, linux-acenic@SunSITE.dk\n"
449 " http://home.cern.ch/~jes/gige/acenic.html\n";
450
451static int ace_get_settings(struct net_device *, struct ethtool_cmd *);
452static int ace_set_settings(struct net_device *, struct ethtool_cmd *);
453static void ace_get_drvinfo(struct net_device *, struct ethtool_drvinfo *);
454
455static struct ethtool_ops ace_ethtool_ops = {
456 .get_settings = ace_get_settings,
457 .set_settings = ace_set_settings,
458 .get_drvinfo = ace_get_drvinfo,
459};
460
461static void ace_watchdog(struct net_device *dev);
462
463static int __devinit acenic_probe_one(struct pci_dev *pdev,
464 const struct pci_device_id *id)
465{
466 struct net_device *dev;
467 struct ace_private *ap;
468 static int boards_found;
469
470 dev = alloc_etherdev(sizeof(struct ace_private));
471 if (dev == NULL) {
472 printk(KERN_ERR "acenic: Unable to allocate "
473 "net_device structure!\n");
474 return -ENOMEM;
475 }
476
477 SET_MODULE_OWNER(dev);
478 SET_NETDEV_DEV(dev, &pdev->dev);
479
480 ap = dev->priv;
481 ap->pdev = pdev;
482 ap->name = pci_name(pdev);
483
484 dev->features |= NETIF_F_SG | NETIF_F_IP_CSUM;
485#if ACENIC_DO_VLAN
486 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
487 dev->vlan_rx_register = ace_vlan_rx_register;
488 dev->vlan_rx_kill_vid = ace_vlan_rx_kill_vid;
489#endif
490 if (1) {
491 dev->tx_timeout = &ace_watchdog;
492 dev->watchdog_timeo = 5*HZ;
493 }
494
495 dev->open = &ace_open;
496 dev->stop = &ace_close;
497 dev->hard_start_xmit = &ace_start_xmit;
498 dev->get_stats = &ace_get_stats;
499 dev->set_multicast_list = &ace_set_multicast_list;
500 SET_ETHTOOL_OPS(dev, &ace_ethtool_ops);
501 dev->set_mac_address = &ace_set_mac_addr;
502 dev->change_mtu = &ace_change_mtu;
503
504 /* we only display this string ONCE */
505 if (!boards_found)
506 printk(version);
507
508 if (pci_enable_device(pdev))
509 goto fail_free_netdev;
510
511 /*
512 * Enable master mode before we start playing with the
513 * pci_command word since pci_set_master() will modify
514 * it.
515 */
516 pci_set_master(pdev);
517
518 pci_read_config_word(pdev, PCI_COMMAND, &ap->pci_command);
519
520 /* OpenFirmware on Mac's does not set this - DOH.. */
521 if (!(ap->pci_command & PCI_COMMAND_MEMORY)) {
522 printk(KERN_INFO "%s: Enabling PCI Memory Mapped "
523 "access - was not enabled by BIOS/Firmware\n",
524 ap->name);
525 ap->pci_command = ap->pci_command | PCI_COMMAND_MEMORY;
526 pci_write_config_word(ap->pdev, PCI_COMMAND,
527 ap->pci_command);
528 wmb();
529 }
530
531 pci_read_config_byte(pdev, PCI_LATENCY_TIMER, &ap->pci_latency);
532 if (ap->pci_latency <= 0x40) {
533 ap->pci_latency = 0x40;
534 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, ap->pci_latency);
535 }
536
537 /*
538 * Remap the regs into kernel space - this is abuse of
539 * dev->base_addr since it was means for I/O port
540 * addresses but who gives a damn.
541 */
542 dev->base_addr = pci_resource_start(pdev, 0);
543 ap->regs = ioremap(dev->base_addr, 0x4000);
544 if (!ap->regs) {
545 printk(KERN_ERR "%s: Unable to map I/O register, "
546 "AceNIC %i will be disabled.\n",
547 ap->name, boards_found);
548 goto fail_free_netdev;
549 }
550
551 switch(pdev->vendor) {
552 case PCI_VENDOR_ID_ALTEON:
553 if (pdev->device == PCI_DEVICE_ID_FARALLON_PN9100T) {
554 printk(KERN_INFO "%s: Farallon PN9100-T ",
555 ap->name);
556 } else {
557 printk(KERN_INFO "%s: Alteon AceNIC ",
558 ap->name);
559 }
560 break;
561 case PCI_VENDOR_ID_3COM:
562 printk(KERN_INFO "%s: 3Com 3C985 ", ap->name);
563 break;
564 case PCI_VENDOR_ID_NETGEAR:
565 printk(KERN_INFO "%s: NetGear GA620 ", ap->name);
566 break;
567 case PCI_VENDOR_ID_DEC:
568 if (pdev->device == PCI_DEVICE_ID_FARALLON_PN9000SX) {
569 printk(KERN_INFO "%s: Farallon PN9000-SX ",
570 ap->name);
571 break;
572 }
573 case PCI_VENDOR_ID_SGI:
574 printk(KERN_INFO "%s: SGI AceNIC ", ap->name);
575 break;
576 default:
577 printk(KERN_INFO "%s: Unknown AceNIC ", ap->name);
578 break;
579 }
580
581 printk("Gigabit Ethernet at 0x%08lx, ", dev->base_addr);
582#ifdef __sparc__
583 printk("irq %s\n", __irq_itoa(pdev->irq));
584#else
585 printk("irq %i\n", pdev->irq);
586#endif
587
588#ifdef CONFIG_ACENIC_OMIT_TIGON_I
589 if ((readl(&ap->regs->HostCtrl) >> 28) == 4) {
590 printk(KERN_ERR "%s: Driver compiled without Tigon I"
591 " support - NIC disabled\n", dev->name);
592 goto fail_uninit;
593 }
594#endif
595
596 if (ace_allocate_descriptors(dev))
597 goto fail_free_netdev;
598
599#ifdef MODULE
600 if (boards_found >= ACE_MAX_MOD_PARMS)
601 ap->board_idx = BOARD_IDX_OVERFLOW;
602 else
603 ap->board_idx = boards_found;
604#else
605 ap->board_idx = BOARD_IDX_STATIC;
606#endif
607
608 if (ace_init(dev))
609 goto fail_free_netdev;
610
611 if (register_netdev(dev)) {
612 printk(KERN_ERR "acenic: device registration failed\n");
613 goto fail_uninit;
614 }
615 ap->name = dev->name;
616
617 if (ap->pci_using_dac)
618 dev->features |= NETIF_F_HIGHDMA;
619
620 pci_set_drvdata(pdev, dev);
621
622 boards_found++;
623 return 0;
624
625 fail_uninit:
626 ace_init_cleanup(dev);
627 fail_free_netdev:
628 free_netdev(dev);
629 return -ENODEV;
630}
631
632static void __devexit acenic_remove_one(struct pci_dev *pdev)
633{
634 struct net_device *dev = pci_get_drvdata(pdev);
635 struct ace_private *ap = netdev_priv(dev);
636 struct ace_regs __iomem *regs = ap->regs;
637 short i;
638
639 unregister_netdev(dev);
640
641 writel(readl(&regs->CpuCtrl) | CPU_HALT, &regs->CpuCtrl);
642 if (ap->version >= 2)
643 writel(readl(&regs->CpuBCtrl) | CPU_HALT, &regs->CpuBCtrl);
644
645 /*
646 * This clears any pending interrupts
647 */
648 writel(1, &regs->Mb0Lo);
649 readl(&regs->CpuCtrl); /* flush */
650
651 /*
652 * Make sure no other CPUs are processing interrupts
653 * on the card before the buffers are being released.
654 * Otherwise one might experience some `interesting'
655 * effects.
656 *
657 * Then release the RX buffers - jumbo buffers were
658 * already released in ace_close().
659 */
660 ace_sync_irq(dev->irq);
661
662 for (i = 0; i < RX_STD_RING_ENTRIES; i++) {
663 struct sk_buff *skb = ap->skb->rx_std_skbuff[i].skb;
664
665 if (skb) {
666 struct ring_info *ringp;
667 dma_addr_t mapping;
668
669 ringp = &ap->skb->rx_std_skbuff[i];
670 mapping = pci_unmap_addr(ringp, mapping);
671 pci_unmap_page(ap->pdev, mapping,
672 ACE_STD_BUFSIZE,
673 PCI_DMA_FROMDEVICE);
674
675 ap->rx_std_ring[i].size = 0;
676 ap->skb->rx_std_skbuff[i].skb = NULL;
677 dev_kfree_skb(skb);
678 }
679 }
680
681 if (ap->version >= 2) {
682 for (i = 0; i < RX_MINI_RING_ENTRIES; i++) {
683 struct sk_buff *skb = ap->skb->rx_mini_skbuff[i].skb;
684
685 if (skb) {
686 struct ring_info *ringp;
687 dma_addr_t mapping;
688
689 ringp = &ap->skb->rx_mini_skbuff[i];
690 mapping = pci_unmap_addr(ringp,mapping);
691 pci_unmap_page(ap->pdev, mapping,
692 ACE_MINI_BUFSIZE,
693 PCI_DMA_FROMDEVICE);
694
695 ap->rx_mini_ring[i].size = 0;
696 ap->skb->rx_mini_skbuff[i].skb = NULL;
697 dev_kfree_skb(skb);
698 }
699 }
700 }
701
702 for (i = 0; i < RX_JUMBO_RING_ENTRIES; i++) {
703 struct sk_buff *skb = ap->skb->rx_jumbo_skbuff[i].skb;
704 if (skb) {
705 struct ring_info *ringp;
706 dma_addr_t mapping;
707
708 ringp = &ap->skb->rx_jumbo_skbuff[i];
709 mapping = pci_unmap_addr(ringp, mapping);
710 pci_unmap_page(ap->pdev, mapping,
711 ACE_JUMBO_BUFSIZE,
712 PCI_DMA_FROMDEVICE);
713
714 ap->rx_jumbo_ring[i].size = 0;
715 ap->skb->rx_jumbo_skbuff[i].skb = NULL;
716 dev_kfree_skb(skb);
717 }
718 }
719
720 ace_init_cleanup(dev);
721 free_netdev(dev);
722}
723
724static struct pci_driver acenic_pci_driver = {
725 .name = "acenic",
726 .id_table = acenic_pci_tbl,
727 .probe = acenic_probe_one,
728 .remove = __devexit_p(acenic_remove_one),
729};
730
731static int __init acenic_init(void)
732{
733 return pci_module_init(&acenic_pci_driver);
734}
735
736static void __exit acenic_exit(void)
737{
738 pci_unregister_driver(&acenic_pci_driver);
739}
740
741module_init(acenic_init);
742module_exit(acenic_exit);
743
744static void ace_free_descriptors(struct net_device *dev)
745{
746 struct ace_private *ap = netdev_priv(dev);
747 int size;
748
749 if (ap->rx_std_ring != NULL) {
750 size = (sizeof(struct rx_desc) *
751 (RX_STD_RING_ENTRIES +
752 RX_JUMBO_RING_ENTRIES +
753 RX_MINI_RING_ENTRIES +
754 RX_RETURN_RING_ENTRIES));
755 pci_free_consistent(ap->pdev, size, ap->rx_std_ring,
756 ap->rx_ring_base_dma);
757 ap->rx_std_ring = NULL;
758 ap->rx_jumbo_ring = NULL;
759 ap->rx_mini_ring = NULL;
760 ap->rx_return_ring = NULL;
761 }
762 if (ap->evt_ring != NULL) {
763 size = (sizeof(struct event) * EVT_RING_ENTRIES);
764 pci_free_consistent(ap->pdev, size, ap->evt_ring,
765 ap->evt_ring_dma);
766 ap->evt_ring = NULL;
767 }
768 if (ap->tx_ring != NULL && !ACE_IS_TIGON_I(ap)) {
769 size = (sizeof(struct tx_desc) * MAX_TX_RING_ENTRIES);
770 pci_free_consistent(ap->pdev, size, ap->tx_ring,
771 ap->tx_ring_dma);
772 }
773 ap->tx_ring = NULL;
774
775 if (ap->evt_prd != NULL) {
776 pci_free_consistent(ap->pdev, sizeof(u32),
777 (void *)ap->evt_prd, ap->evt_prd_dma);
778 ap->evt_prd = NULL;
779 }
780 if (ap->rx_ret_prd != NULL) {
781 pci_free_consistent(ap->pdev, sizeof(u32),
782 (void *)ap->rx_ret_prd,
783 ap->rx_ret_prd_dma);
784 ap->rx_ret_prd = NULL;
785 }
786 if (ap->tx_csm != NULL) {
787 pci_free_consistent(ap->pdev, sizeof(u32),
788 (void *)ap->tx_csm, ap->tx_csm_dma);
789 ap->tx_csm = NULL;
790 }
791}
792
793
794static int ace_allocate_descriptors(struct net_device *dev)
795{
796 struct ace_private *ap = netdev_priv(dev);
797 int size;
798
799 size = (sizeof(struct rx_desc) *
800 (RX_STD_RING_ENTRIES +
801 RX_JUMBO_RING_ENTRIES +
802 RX_MINI_RING_ENTRIES +
803 RX_RETURN_RING_ENTRIES));
804
805 ap->rx_std_ring = pci_alloc_consistent(ap->pdev, size,
806 &ap->rx_ring_base_dma);
807 if (ap->rx_std_ring == NULL)
808 goto fail;
809
810 ap->rx_jumbo_ring = ap->rx_std_ring + RX_STD_RING_ENTRIES;
811 ap->rx_mini_ring = ap->rx_jumbo_ring + RX_JUMBO_RING_ENTRIES;
812 ap->rx_return_ring = ap->rx_mini_ring + RX_MINI_RING_ENTRIES;
813
814 size = (sizeof(struct event) * EVT_RING_ENTRIES);
815
816 ap->evt_ring = pci_alloc_consistent(ap->pdev, size, &ap->evt_ring_dma);
817
818 if (ap->evt_ring == NULL)
819 goto fail;
820
821 /*
822 * Only allocate a host TX ring for the Tigon II, the Tigon I
823 * has to use PCI registers for this ;-(
824 */
825 if (!ACE_IS_TIGON_I(ap)) {
826 size = (sizeof(struct tx_desc) * MAX_TX_RING_ENTRIES);
827
828 ap->tx_ring = pci_alloc_consistent(ap->pdev, size,
829 &ap->tx_ring_dma);
830
831 if (ap->tx_ring == NULL)
832 goto fail;
833 }
834
835 ap->evt_prd = pci_alloc_consistent(ap->pdev, sizeof(u32),
836 &ap->evt_prd_dma);
837 if (ap->evt_prd == NULL)
838 goto fail;
839
840 ap->rx_ret_prd = pci_alloc_consistent(ap->pdev, sizeof(u32),
841 &ap->rx_ret_prd_dma);
842 if (ap->rx_ret_prd == NULL)
843 goto fail;
844
845 ap->tx_csm = pci_alloc_consistent(ap->pdev, sizeof(u32),
846 &ap->tx_csm_dma);
847 if (ap->tx_csm == NULL)
848 goto fail;
849
850 return 0;
851
852fail:
853 /* Clean up. */
854 ace_init_cleanup(dev);
855 return 1;
856}
857
858
859/*
860 * Generic cleanup handling data allocated during init. Used when the
861 * module is unloaded or if an error occurs during initialization
862 */
863static void ace_init_cleanup(struct net_device *dev)
864{
865 struct ace_private *ap;
866
867 ap = netdev_priv(dev);
868
869 ace_free_descriptors(dev);
870
871 if (ap->info)
872 pci_free_consistent(ap->pdev, sizeof(struct ace_info),
873 ap->info, ap->info_dma);
b4558ea9
JJ		 874 kfree(ap->skb);
875 kfree(ap->trace_buf);
1da177e4
LT		 876
877 if (dev->irq)
878 free_irq(dev->irq, dev);
879
880 iounmap(ap->regs);
881}
882
883
884/*
885 * Commands are considered to be slow.
886 */
887static inline void ace_issue_cmd(struct ace_regs __iomem *regs, struct cmd *cmd)
888{
889 u32 idx;
890
891 idx = readl(&regs->CmdPrd);
892
893 writel(*(u32 *)(cmd), &regs->CmdRng[idx]);
894 idx = (idx + 1) % CMD_RING_ENTRIES;
895
896 writel(idx, &regs->CmdPrd);
897}
898
899
900static int __devinit ace_init(struct net_device *dev)
901{
902 struct ace_private *ap;
903 struct ace_regs __iomem *regs;
904 struct ace_info *info = NULL;
905 struct pci_dev *pdev;
906 unsigned long myjif;
907 u64 tmp_ptr;
908 u32 tig_ver, mac1, mac2, tmp, pci_state;
909 int board_idx, ecode = 0;
910 short i;
911 unsigned char cache_size;
912
913 ap = netdev_priv(dev);
914 regs = ap->regs;
915
916 board_idx = ap->board_idx;
917
918 /*
919 * aman@sgi.com - its useful to do a NIC reset here to
920 * address the `Firmware not running' problem subsequent
921 * to any crashes involving the NIC
922 */
923 writel(HW_RESET | (HW_RESET << 24), &regs->HostCtrl);
924 readl(&regs->HostCtrl); /* PCI write posting */
925 udelay(5);
926
927 /*
928 * Don't access any other registers before this point!
929 */
930#ifdef __BIG_ENDIAN
931 /*
932 * This will most likely need BYTE_SWAP once we switch
933 * to using __raw_writel()
934 */
935 writel((WORD_SWAP | CLR_INT | ((WORD_SWAP | CLR_INT) << 24)),
936 &regs->HostCtrl);
937#else
938 writel((CLR_INT | WORD_SWAP | ((CLR_INT | WORD_SWAP) << 24)),
939 &regs->HostCtrl);
940#endif
941 readl(&regs->HostCtrl); /* PCI write posting */
942
943 /*
944 * Stop the NIC CPU and clear pending interrupts
945 */
946 writel(readl(&regs->CpuCtrl) | CPU_HALT, &regs->CpuCtrl);
947 readl(&regs->CpuCtrl); /* PCI write posting */
948 writel(0, &regs->Mb0Lo);
949
950 tig_ver = readl(&regs->HostCtrl) >> 28;
951
952 switch(tig_ver){
953#ifndef CONFIG_ACENIC_OMIT_TIGON_I
954 case 4:
955 case 5:
956 printk(KERN_INFO " Tigon I (Rev. %i), Firmware: %i.%i.%i, ",
957 tig_ver, tigonFwReleaseMajor, tigonFwReleaseMinor,
958 tigonFwReleaseFix);
959 writel(0, &regs->LocalCtrl);
960 ap->version = 1;
961 ap->tx_ring_entries = TIGON_I_TX_RING_ENTRIES;
962 break;
963#endif
964 case 6:
965 printk(KERN_INFO " Tigon II (Rev. %i), Firmware: %i.%i.%i, ",
966 tig_ver, tigon2FwReleaseMajor, tigon2FwReleaseMinor,
967 tigon2FwReleaseFix);
968 writel(readl(&regs->CpuBCtrl) | CPU_HALT, &regs->CpuBCtrl);
969 readl(&regs->CpuBCtrl); /* PCI write posting */
970 /*
971 * The SRAM bank size does _not_ indicate the amount
972 * of memory on the card, it controls the _bank_ size!
973 * Ie. a 1MB AceNIC will have two banks of 512KB.
974 */
975 writel(SRAM_BANK_512K, &regs->LocalCtrl);
976 writel(SYNC_SRAM_TIMING, &regs->MiscCfg);
977 ap->version = 2;
978 ap->tx_ring_entries = MAX_TX_RING_ENTRIES;
979 break;
980 default:
981 printk(KERN_WARNING " Unsupported Tigon version detected "
982 "(%i)\n", tig_ver);
983 ecode = -ENODEV;
984 goto init_error;
985 }
986
987 /*
988 * ModeStat _must_ be set after the SRAM settings as this change
989 * seems to corrupt the ModeStat and possible other registers.
990 * The SRAM settings survive resets and setting it to the same
991 * value a second time works as well. This is what caused the
992 * `Firmware not running' problem on the Tigon II.
993 */
994#ifdef __BIG_ENDIAN
995 writel(ACE_BYTE_SWAP_DMA | ACE_WARN | ACE_FATAL | ACE_BYTE_SWAP_BD |
996 ACE_WORD_SWAP_BD | ACE_NO_JUMBO_FRAG, &regs->ModeStat);
997#else
998 writel(ACE_BYTE_SWAP_DMA | ACE_WARN | ACE_FATAL |
999 ACE_WORD_SWAP_BD | ACE_NO_JUMBO_FRAG, &regs->ModeStat);
1000#endif
1001 readl(&regs->ModeStat); /* PCI write posting */
1002
1003 mac1 = 0;
1004 for(i = 0; i < 4; i++) {
6f9d4722
ES		 1005 int tmp;
1006
1da177e4
LT		 1007 mac1 = mac1 << 8;
1008 tmp = read_eeprom_byte(dev, 0x8c+i);
1009 if (tmp < 0) {
1010 ecode = -EIO;
1011 goto init_error;
1012 } else
1013 mac1 |= (tmp & 0xff);
1014 }
1015 mac2 = 0;
1016 for(i = 4; i < 8; i++) {
6f9d4722
ES		 1017 int tmp;
1018
1da177e4
LT		 1019 mac2 = mac2 << 8;
1020 tmp = read_eeprom_byte(dev, 0x8c+i);
1021 if (tmp < 0) {
1022 ecode = -EIO;
1023 goto init_error;
1024 } else
1025 mac2 |= (tmp & 0xff);
1026 }
1027
1028 writel(mac1, &regs->MacAddrHi);
1029 writel(mac2, &regs->MacAddrLo);
1030
1031 printk("MAC: %02x:%02x:%02x:%02x:%02x:%02x\n",
1032 (mac1 >> 8) & 0xff, mac1 & 0xff, (mac2 >> 24) &0xff,
1033 (mac2 >> 16) & 0xff, (mac2 >> 8) & 0xff, mac2 & 0xff);
1034
1035 dev->dev_addr[0] = (mac1 >> 8) & 0xff;
1036 dev->dev_addr[1] = mac1 & 0xff;
1037 dev->dev_addr[2] = (mac2 >> 24) & 0xff;
1038 dev->dev_addr[3] = (mac2 >> 16) & 0xff;
1039 dev->dev_addr[4] = (mac2 >> 8) & 0xff;
1040 dev->dev_addr[5] = mac2 & 0xff;
1041
1042 /*
1043 * Looks like this is necessary to deal with on all architectures,
1044 * even this %$#%$# N440BX Intel based thing doesn't get it right.
1045 * Ie. having two NICs in the machine, one will have the cache
1046 * line set at boot time, the other will not.
1047 */
1048 pdev = ap->pdev;
1049 pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &cache_size);
1050 cache_size <<= 2;
1051 if (cache_size != SMP_CACHE_BYTES) {
1052 printk(KERN_INFO " PCI cache line size set incorrectly "
1053 "(%i bytes) by BIOS/FW, ", cache_size);
1054 if (cache_size > SMP_CACHE_BYTES)
1055 printk("expecting %i\n", SMP_CACHE_BYTES);
1056 else {
1057 printk("correcting to %i\n", SMP_CACHE_BYTES);
1058 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE,
1059 SMP_CACHE_BYTES >> 2);
1060 }
1061 }
1062
1063 pci_state = readl(&regs->PciState);
1064 printk(KERN_INFO " PCI bus width: %i bits, speed: %iMHz, "
1065 "latency: %i clks\n",
1066 (pci_state & PCI_32BIT) ? 32 : 64,
1067 (pci_state & PCI_66MHZ) ? 66 : 33,
1068 ap->pci_latency);
1069
1070 /*
1071 * Set the max DMA transfer size. Seems that for most systems
1072 * the performance is better when no MAX parameter is
1073 * set. However for systems enabling PCI write and invalidate,
1074 * DMA writes must be set to the L1 cache line size to get
1075 * optimal performance.
1076 *
1077 * The default is now to turn the PCI write and invalidate off
1078 * - that is what Alteon does for NT.
1079 */
1080 tmp = READ_CMD_MEM | WRITE_CMD_MEM;
1081 if (ap->version >= 2) {
1082 tmp |= (MEM_READ_MULTIPLE | (pci_state & PCI_66MHZ));
1083 /*
1084 * Tuning parameters only supported for 8 cards
1085 */
1086 if (board_idx == BOARD_IDX_OVERFLOW ||
1087 dis_pci_mem_inval[board_idx]) {
1088 if (ap->pci_command & PCI_COMMAND_INVALIDATE) {
1089 ap->pci_command &= ~PCI_COMMAND_INVALIDATE;
1090 pci_write_config_word(pdev, PCI_COMMAND,
1091 ap->pci_command);
1092 printk(KERN_INFO " Disabling PCI memory "
1093 "write and invalidate\n");
1094 }
1095 } else if (ap->pci_command & PCI_COMMAND_INVALIDATE) {
1096 printk(KERN_INFO " PCI memory write & invalidate "
1097 "enabled by BIOS, enabling counter measures\n");
1098
1099 switch(SMP_CACHE_BYTES) {
1100 case 16:
1101 tmp |= DMA_WRITE_MAX_16;
1102 break;
1103 case 32:
1104 tmp |= DMA_WRITE_MAX_32;
1105 break;
1106 case 64:
1107 tmp |= DMA_WRITE_MAX_64;
1108 break;
1109 case 128:
1110 tmp |= DMA_WRITE_MAX_128;
1111 break;
1112 default:
1113 printk(KERN_INFO " Cache line size %i not "
1114 "supported, PCI write and invalidate "
1115 "disabled\n", SMP_CACHE_BYTES);
1116 ap->pci_command &= ~PCI_COMMAND_INVALIDATE;
1117 pci_write_config_word(pdev, PCI_COMMAND,
1118 ap->pci_command);
1119 }
1120 }
1121 }
1122
1123#ifdef __sparc__
1124 /*
1125 * On this platform, we know what the best dma settings
1126 * are. We use 64-byte maximum bursts, because if we
1127 * burst larger than the cache line size (or even cross
1128 * a 64byte boundary in a single burst) the UltraSparc
1129 * PCI controller will disconnect at 64-byte multiples.
1130 *
1131 * Read-multiple will be properly enabled above, and when
1132 * set will give the PCI controller proper hints about
1133 * prefetching.
1134 */
1135 tmp &= ~DMA_READ_WRITE_MASK;
1136 tmp |= DMA_READ_MAX_64;
1137 tmp |= DMA_WRITE_MAX_64;
1138#endif
1139#ifdef __alpha__
1140 tmp &= ~DMA_READ_WRITE_MASK;
1141 tmp |= DMA_READ_MAX_128;
1142 /*
1143 * All the docs say MUST NOT. Well, I did.
1144 * Nothing terrible happens, if we load wrong size.
1145 * Bit w&i still works better!
1146 */
1147 tmp |= DMA_WRITE_MAX_128;
1148#endif
1149 writel(tmp, &regs->PciState);
1150
1151#if 0
1152 /*
1153 * The Host PCI bus controller driver has to set FBB.
1154 * If all devices on that PCI bus support FBB, then the controller
1155 * can enable FBB support in the Host PCI Bus controller (or on
1156 * the PCI-PCI bridge if that applies).
1157 * -ggg
1158 */
1159 /*
1160 * I have received reports from people having problems when this
1161 * bit is enabled.
1162 */
1163 if (!(ap->pci_command & PCI_COMMAND_FAST_BACK)) {
1164 printk(KERN_INFO " Enabling PCI Fast Back to Back\n");
1165 ap->pci_command |= PCI_COMMAND_FAST_BACK;
1166 pci_write_config_word(pdev, PCI_COMMAND, ap->pci_command);
1167 }
1168#endif
1169
1170 /*
1171 * Configure DMA attributes.
1172 */
1e7f0bd8 1173 if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
1da177e4 1174 ap->pci_using_dac = 1;
1e7f0bd8 1175 } else if (!pci_set_dma_mask(pdev, DMA_32BIT_MASK)) {
1da177e4
LT		 1176 ap->pci_using_dac = 0;
1177 } else {
1178 ecode = -ENODEV;
1179 goto init_error;
1180 }
1181
1182 /*
1183 * Initialize the generic info block and the command+event rings
1184 * and the control blocks for the transmit and receive rings
1185 * as they need to be setup once and for all.
1186 */
1187 if (!(info = pci_alloc_consistent(ap->pdev, sizeof(struct ace_info),
1188 &ap->info_dma))) {
1189 ecode = -EAGAIN;
1190 goto init_error;
1191 }
1192 ap->info = info;
1193
1194 /*
1195 * Get the memory for the skb rings.
1196 */
1197 if (!(ap->skb = kmalloc(sizeof(struct ace_skb), GFP_KERNEL))) {
1198 ecode = -EAGAIN;
1199 goto init_error;
1200 }
1201
1202 ecode = request_irq(pdev->irq, ace_interrupt, SA_SHIRQ,
1203 DRV_NAME, dev);
1204 if (ecode) {
1205 printk(KERN_WARNING "%s: Requested IRQ %d is busy\n",
1206 DRV_NAME, pdev->irq);
1207 goto init_error;
1208 } else
1209 dev->irq = pdev->irq;
1210
1211#ifdef INDEX_DEBUG
1212 spin_lock_init(&ap->debug_lock);
1213 ap->last_tx = ACE_TX_RING_ENTRIES(ap) - 1;
1214 ap->last_std_rx = 0;
1215 ap->last_mini_rx = 0;
1216#endif
1217
1218 memset(ap->info, 0, sizeof(struct ace_info));
1219 memset(ap->skb, 0, sizeof(struct ace_skb));
1220
1221 ace_load_firmware(dev);
1222 ap->fw_running = 0;
1223
1224 tmp_ptr = ap->info_dma;
1225 writel(tmp_ptr >> 32, &regs->InfoPtrHi);
1226 writel(tmp_ptr & 0xffffffff, &regs->InfoPtrLo);
1227
1228 memset(ap->evt_ring, 0, EVT_RING_ENTRIES * sizeof(struct event));
1229
1230 set_aceaddr(&info->evt_ctrl.rngptr, ap->evt_ring_dma);
1231 info->evt_ctrl.flags = 0;
1232
1233 *(ap->evt_prd) = 0;
1234 wmb();
1235 set_aceaddr(&info->evt_prd_ptr, ap->evt_prd_dma);
1236 writel(0, &regs->EvtCsm);
1237
1238 set_aceaddr(&info->cmd_ctrl.rngptr, 0x100);
1239 info->cmd_ctrl.flags = 0;
1240 info->cmd_ctrl.max_len = 0;
1241
1242 for (i = 0; i < CMD_RING_ENTRIES; i++)
1243 writel(0, &regs->CmdRng[i]);
1244
1245 writel(0, &regs->CmdPrd);
1246 writel(0, &regs->CmdCsm);
1247
1248 tmp_ptr = ap->info_dma;
1249 tmp_ptr += (unsigned long) &(((struct ace_info *)0)->s.stats);
1250 set_aceaddr(&info->stats2_ptr, (dma_addr_t) tmp_ptr);
1251
1252 set_aceaddr(&info->rx_std_ctrl.rngptr, ap->rx_ring_base_dma);
1253 info->rx_std_ctrl.max_len = ACE_STD_BUFSIZE;
1254 info->rx_std_ctrl.flags =
1255 RCB_FLG_TCP_UDP_SUM | RCB_FLG_NO_PSEUDO_HDR | ACE_RCB_VLAN_FLAG;
1256
1257 memset(ap->rx_std_ring, 0,
1258 RX_STD_RING_ENTRIES * sizeof(struct rx_desc));
1259
1260 for (i = 0; i < RX_STD_RING_ENTRIES; i++)
1261 ap->rx_std_ring[i].flags = BD_FLG_TCP_UDP_SUM;
1262
1263 ap->rx_std_skbprd = 0;
1264 atomic_set(&ap->cur_rx_bufs, 0);
1265
1266 set_aceaddr(&info->rx_jumbo_ctrl.rngptr,
1267 (ap->rx_ring_base_dma +
1268 (sizeof(struct rx_desc) * RX_STD_RING_ENTRIES)));
1269 info->rx_jumbo_ctrl.max_len = 0;
1270 info->rx_jumbo_ctrl.flags =
1271 RCB_FLG_TCP_UDP_SUM | RCB_FLG_NO_PSEUDO_HDR | ACE_RCB_VLAN_FLAG;
1272
1273 memset(ap->rx_jumbo_ring, 0,
1274 RX_JUMBO_RING_ENTRIES * sizeof(struct rx_desc));
1275
1276 for (i = 0; i < RX_JUMBO_RING_ENTRIES; i++)
1277 ap->rx_jumbo_ring[i].flags = BD_FLG_TCP_UDP_SUM | BD_FLG_JUMBO;
1278
1279 ap->rx_jumbo_skbprd = 0;
1280 atomic_set(&ap->cur_jumbo_bufs, 0);
1281
1282 memset(ap->rx_mini_ring, 0,
1283 RX_MINI_RING_ENTRIES * sizeof(struct rx_desc));
1284
1285 if (ap->version >= 2) {
1286 set_aceaddr(&info->rx_mini_ctrl.rngptr,
1287 (ap->rx_ring_base_dma +
1288 (sizeof(struct rx_desc) *
1289 (RX_STD_RING_ENTRIES +
1290 RX_JUMBO_RING_ENTRIES))));
1291 info->rx_mini_ctrl.max_len = ACE_MINI_SIZE;
1292 info->rx_mini_ctrl.flags =
1293 RCB_FLG_TCP_UDP_SUM|RCB_FLG_NO_PSEUDO_HDR|ACE_RCB_VLAN_FLAG;
1294
1295 for (i = 0; i < RX_MINI_RING_ENTRIES; i++)
1296 ap->rx_mini_ring[i].flags =
1297 BD_FLG_TCP_UDP_SUM | BD_FLG_MINI;
1298 } else {
1299 set_aceaddr(&info->rx_mini_ctrl.rngptr, 0);
1300 info->rx_mini_ctrl.flags = RCB_FLG_RNG_DISABLE;
1301 info->rx_mini_ctrl.max_len = 0;
1302 }
1303
1304 ap->rx_mini_skbprd = 0;
1305 atomic_set(&ap->cur_mini_bufs, 0);
1306
1307 set_aceaddr(&info->rx_return_ctrl.rngptr,
1308 (ap->rx_ring_base_dma +
1309 (sizeof(struct rx_desc) *
1310 (RX_STD_RING_ENTRIES +
1311 RX_JUMBO_RING_ENTRIES +
1312 RX_MINI_RING_ENTRIES))));
1313 info->rx_return_ctrl.flags = 0;
1314 info->rx_return_ctrl.max_len = RX_RETURN_RING_ENTRIES;
1315
1316 memset(ap->rx_return_ring, 0,
1317 RX_RETURN_RING_ENTRIES * sizeof(struct rx_desc));
1318
1319 set_aceaddr(&info->rx_ret_prd_ptr, ap->rx_ret_prd_dma);
1320 *(ap->rx_ret_prd) = 0;
1321
1322 writel(TX_RING_BASE, &regs->WinBase);
1323
1324 if (ACE_IS_TIGON_I(ap)) {
1325 ap->tx_ring = (struct tx_desc *) regs->Window;
1326 for (i = 0; i < (TIGON_I_TX_RING_ENTRIES
1327 * sizeof(struct tx_desc)) / sizeof(u32); i++)
1328 writel(0, (void __iomem *)ap->tx_ring + i * 4);
1329
1330 set_aceaddr(&info->tx_ctrl.rngptr, TX_RING_BASE);
1331 } else {
1332 memset(ap->tx_ring, 0,
1333 MAX_TX_RING_ENTRIES * sizeof(struct tx_desc));
1334
1335 set_aceaddr(&info->tx_ctrl.rngptr, ap->tx_ring_dma);
1336 }
1337
1338 info->tx_ctrl.max_len = ACE_TX_RING_ENTRIES(ap);
1339 tmp = RCB_FLG_TCP_UDP_SUM | RCB_FLG_NO_PSEUDO_HDR | ACE_RCB_VLAN_FLAG;
1340
1341 /*
1342 * The Tigon I does not like having the TX ring in host memory ;-(
1343 */
1344 if (!ACE_IS_TIGON_I(ap))
1345 tmp |= RCB_FLG_TX_HOST_RING;
1346#if TX_COAL_INTS_ONLY
1347 tmp |= RCB_FLG_COAL_INT_ONLY;
1348#endif
1349 info->tx_ctrl.flags = tmp;
1350
1351 set_aceaddr(&info->tx_csm_ptr, ap->tx_csm_dma);
1352
1353 /*
1354 * Potential item for tuning parameter
1355 */
1356#if 0 /* NO */
1357 writel(DMA_THRESH_16W, &regs->DmaReadCfg);
1358 writel(DMA_THRESH_16W, &regs->DmaWriteCfg);
1359#else
1360 writel(DMA_THRESH_8W, &regs->DmaReadCfg);
1361 writel(DMA_THRESH_8W, &regs->DmaWriteCfg);
1362#endif
1363
1364 writel(0, &regs->MaskInt);
1365 writel(1, &regs->IfIdx);
1366#if 0
1367 /*
1368 * McKinley boxes do not like us fiddling with AssistState
1369 * this early
1370 */
1371 writel(1, &regs->AssistState);
1372#endif
1373
1374 writel(DEF_STAT, &regs->TuneStatTicks);
1375 writel(DEF_TRACE, &regs->TuneTrace);
1376
1377 ace_set_rxtx_parms(dev, 0);
1378
1379 if (board_idx == BOARD_IDX_OVERFLOW) {
1380 printk(KERN_WARNING "%s: more than %i NICs detected, "
1381 "ignoring module parameters!\n",
1382 ap->name, ACE_MAX_MOD_PARMS);
1383 } else if (board_idx >= 0) {
1384 if (tx_coal_tick[board_idx])
1385 writel(tx_coal_tick[board_idx],
1386 &regs->TuneTxCoalTicks);
1387 if (max_tx_desc[board_idx])
1388 writel(max_tx_desc[board_idx], &regs->TuneMaxTxDesc);
1389
1390 if (rx_coal_tick[board_idx])
1391 writel(rx_coal_tick[board_idx],
1392 &regs->TuneRxCoalTicks);
1393 if (max_rx_desc[board_idx])
1394 writel(max_rx_desc[board_idx], &regs->TuneMaxRxDesc);
1395
1396 if (trace[board_idx])
1397 writel(trace[board_idx], &regs->TuneTrace);
1398
1399 if ((tx_ratio[board_idx] > 0) && (tx_ratio[board_idx] < 64))
1400 writel(tx_ratio[board_idx], &regs->TxBufRat);
1401 }
1402
1403 /*
1404 * Default link parameters
1405 */
1406 tmp = LNK_ENABLE | LNK_FULL_DUPLEX | LNK_1000MB | LNK_100MB |
1407 LNK_10MB | LNK_RX_FLOW_CTL_Y | LNK_NEG_FCTL | LNK_NEGOTIATE;
1408 if(ap->version >= 2)
1409 tmp |= LNK_TX_FLOW_CTL_Y;
1410
1411 /*
1412 * Override link default parameters
1413 */
1414 if ((board_idx >= 0) && link[board_idx]) {
1415 int option = link[board_idx];
1416
1417 tmp = LNK_ENABLE;
1418
1419 if (option & 0x01) {
1420 printk(KERN_INFO "%s: Setting half duplex link\n",
1421 ap->name);
1422 tmp &= ~LNK_FULL_DUPLEX;
1423 }
1424 if (option & 0x02)
1425 tmp &= ~LNK_NEGOTIATE;
1426 if (option & 0x10)
1427 tmp |= LNK_10MB;
1428 if (option & 0x20)
1429 tmp |= LNK_100MB;
1430 if (option & 0x40)
1431 tmp |= LNK_1000MB;
1432 if ((option & 0x70) == 0) {
1433 printk(KERN_WARNING "%s: No media speed specified, "
1434 "forcing auto negotiation\n", ap->name);
1435 tmp |= LNK_NEGOTIATE | LNK_1000MB |
1436 LNK_100MB | LNK_10MB;
1437 }
1438 if ((option & 0x100) == 0)
1439 tmp |= LNK_NEG_FCTL;
1440 else
1441 printk(KERN_INFO "%s: Disabling flow control "
1442 "negotiation\n", ap->name);
1443 if (option & 0x200)
1444 tmp |= LNK_RX_FLOW_CTL_Y;
1445 if ((option & 0x400) && (ap->version >= 2)) {
1446 printk(KERN_INFO "%s: Enabling TX flow control\n",
1447 ap->name);
1448 tmp |= LNK_TX_FLOW_CTL_Y;
1449 }
1450 }
1451
1452 ap->link = tmp;
1453 writel(tmp, &regs->TuneLink);
1454 if (ap->version >= 2)
1455 writel(tmp, &regs->TuneFastLink);
1456
1457 if (ACE_IS_TIGON_I(ap))
1458 writel(tigonFwStartAddr, &regs->Pc);
1459 if (ap->version == 2)
1460 writel(tigon2FwStartAddr, &regs->Pc);
1461
1462 writel(0, &regs->Mb0Lo);
1463
1464 /*
1465 * Set tx_csm before we start receiving interrupts, otherwise
1466 * the interrupt handler might think it is supposed to process
1467 * tx ints before we are up and running, which may cause a null
1468 * pointer access in the int handler.
1469 */
1470 ap->cur_rx = 0;
1471 ap->tx_prd = *(ap->tx_csm) = ap->tx_ret_csm = 0;
1472
1473 wmb();
1474 ace_set_txprd(regs, ap, 0);
1475 writel(0, &regs->RxRetCsm);
1476
1477 /*
1478 * Zero the stats before starting the interface
1479 */
1480 memset(&ap->stats, 0, sizeof(ap->stats));
1481
1482 /*
1483 * Enable DMA engine now.
1484 * If we do this sooner, Mckinley box pukes.
1485 * I assume it's because Tigon II DMA engine wants to check
1486 * *something* even before the CPU is started.
1487 */
1488 writel(1, &regs->AssistState); /* enable DMA */
1489
1490 /*
1491 * Start the NIC CPU
1492 */
1493 writel(readl(&regs->CpuCtrl) & ~(CPU_HALT|CPU_TRACE), &regs->CpuCtrl);
1494 readl(&regs->CpuCtrl);
1495
1496 /*
1497 * Wait for the firmware to spin up - max 3 seconds.
1498 */
1499 myjif = jiffies + 3 * HZ;
1500 while (time_before(jiffies, myjif) && !ap->fw_running)
1501 cpu_relax();
1502
1503 if (!ap->fw_running) {
1504 printk(KERN_ERR "%s: Firmware NOT running!\n", ap->name);
1505
1506 ace_dump_trace(ap);
1507 writel(readl(&regs->CpuCtrl) | CPU_HALT, &regs->CpuCtrl);
1508 readl(&regs->CpuCtrl);
1509
1510 /* aman@sgi.com - account for badly behaving firmware/NIC:
1511 * - have observed that the NIC may continue to generate
1512 * interrupts for some reason; attempt to stop it - halt
1513 * second CPU for Tigon II cards, and also clear Mb0
1514 * - if we're a module, we'll fail to load if this was
1515 * the only GbE card in the system => if the kernel does
1516 * see an interrupt from the NIC, code to handle it is
1517 * gone and OOps! - so free_irq also
1518 */
1519 if (ap->version >= 2)
1520 writel(readl(&regs->CpuBCtrl) | CPU_HALT,
1521 &regs->CpuBCtrl);
1522 writel(0, &regs->Mb0Lo);
1523 readl(&regs->Mb0Lo);
1524
1525 ecode = -EBUSY;
1526 goto init_error;
1527 }
1528
1529 /*
1530 * We load the ring here as there seem to be no way to tell the
1531 * firmware to wipe the ring without re-initializing it.
1532 */
1533 if (!test_and_set_bit(0, &ap->std_refill_busy))
1534 ace_load_std_rx_ring(ap, RX_RING_SIZE);
1535 else
1536 printk(KERN_ERR "%s: Someone is busy refilling the RX ring\n",
1537 ap->name);
1538 if (ap->version >= 2) {
1539 if (!test_and_set_bit(0, &ap->mini_refill_busy))
1540 ace_load_mini_rx_ring(ap, RX_MINI_SIZE);
1541 else
1542 printk(KERN_ERR "%s: Someone is busy refilling "
1543 "the RX mini ring\n", ap->name);
1544 }
1545 return 0;
1546
1547 init_error:
1548 ace_init_cleanup(dev);
1549 return ecode;
1550}
1551
1552
1553static void ace_set_rxtx_parms(struct net_device *dev, int jumbo)
1554{
1555 struct ace_private *ap = netdev_priv(dev);
1556 struct ace_regs __iomem *regs = ap->regs;
1557 int board_idx = ap->board_idx;
1558
1559 if (board_idx >= 0) {
1560 if (!jumbo) {
1561 if (!tx_coal_tick[board_idx])
1562 writel(DEF_TX_COAL, &regs->TuneTxCoalTicks);
1563 if (!max_tx_desc[board_idx])
1564 writel(DEF_TX_MAX_DESC, &regs->TuneMaxTxDesc);
1565 if (!rx_coal_tick[board_idx])
1566 writel(DEF_RX_COAL, &regs->TuneRxCoalTicks);
1567 if (!max_rx_desc[board_idx])
1568 writel(DEF_RX_MAX_DESC, &regs->TuneMaxRxDesc);
1569 if (!tx_ratio[board_idx])
1570 writel(DEF_TX_RATIO, &regs->TxBufRat);
1571 } else {
1572 if (!tx_coal_tick[board_idx])
1573 writel(DEF_JUMBO_TX_COAL,
1574 &regs->TuneTxCoalTicks);
1575 if (!max_tx_desc[board_idx])
1576 writel(DEF_JUMBO_TX_MAX_DESC,
1577 &regs->TuneMaxTxDesc);
1578 if (!rx_coal_tick[board_idx])
1579 writel(DEF_JUMBO_RX_COAL,
1580 &regs->TuneRxCoalTicks);
1581 if (!max_rx_desc[board_idx])
1582 writel(DEF_JUMBO_RX_MAX_DESC,
1583 &regs->TuneMaxRxDesc);
1584 if (!tx_ratio[board_idx])
1585 writel(DEF_JUMBO_TX_RATIO, &regs->TxBufRat);
1586 }
1587 }
1588}
1589
1590
1591static void ace_watchdog(struct net_device *data)
1592{
1593 struct net_device *dev = data;
1594 struct ace_private *ap = netdev_priv(dev);
1595 struct ace_regs __iomem *regs = ap->regs;
1596
1597 /*
1598 * We haven't received a stats update event for more than 2.5
1599 * seconds and there is data in the transmit queue, thus we
1600 * asume the card is stuck.
1601 */
1602 if (*ap->tx_csm != ap->tx_ret_csm) {
1603 printk(KERN_WARNING "%s: Transmitter is stuck, %08x\n",
1604 dev->name, (unsigned int)readl(&regs->HostCtrl));
1605 /* This can happen due to ieee flow control. */
1606 } else {
1607 printk(KERN_DEBUG "%s: BUG... transmitter died. Kicking it.\n",
1608 dev->name);
1609#if 0
1610 netif_wake_queue(dev);
1611#endif
1612 }
1613}
1614
1615
1616static void ace_tasklet(unsigned long dev)
1617{
1618 struct ace_private *ap = netdev_priv((struct net_device *)dev);
1619 int cur_size;
1620
1621 cur_size = atomic_read(&ap->cur_rx_bufs);
1622 if ((cur_size < RX_LOW_STD_THRES) &&
1623 !test_and_set_bit(0, &ap->std_refill_busy)) {
1624#ifdef DEBUG
1625 printk("refilling buffers (current %i)\n", cur_size);
1626#endif
1627 ace_load_std_rx_ring(ap, RX_RING_SIZE - cur_size);
1628 }
1629
1630 if (ap->version >= 2) {
1631 cur_size = atomic_read(&ap->cur_mini_bufs);
1632 if ((cur_size < RX_LOW_MINI_THRES) &&
1633 !test_and_set_bit(0, &ap->mini_refill_busy)) {
1634#ifdef DEBUG
1635 printk("refilling mini buffers (current %i)\n",
1636 cur_size);
1637#endif
1638 ace_load_mini_rx_ring(ap, RX_MINI_SIZE - cur_size);
1639 }
1640 }
1641
1642 cur_size = atomic_read(&ap->cur_jumbo_bufs);
1643 if (ap->jumbo && (cur_size < RX_LOW_JUMBO_THRES) &&
1644 !test_and_set_bit(0, &ap->jumbo_refill_busy)) {
1645#ifdef DEBUG
1646 printk("refilling jumbo buffers (current %i)\n", cur_size);
1647#endif
1648 ace_load_jumbo_rx_ring(ap, RX_JUMBO_SIZE - cur_size);
1649 }
1650 ap->tasklet_pending = 0;
1651}
1652
1653
1654/*
1655 * Copy the contents of the NIC's trace buffer to kernel memory.
1656 */
1657static void ace_dump_trace(struct ace_private *ap)
1658{
1659#if 0
1660 if (!ap->trace_buf)
1661 if (!(ap->trace_buf = kmalloc(ACE_TRACE_SIZE, GFP_KERNEL)))
1662 return;
1663#endif
1664}
1665
1666
1667/*
1668 * Load the standard rx ring.
1669 *
1670 * Loading rings is safe without holding the spin lock since this is
1671 * done only before the device is enabled, thus no interrupts are
1672 * generated and by the interrupt handler/tasklet handler.
1673 */
1674static void ace_load_std_rx_ring(struct ace_private *ap, int nr_bufs)
1675{
1676 struct ace_regs __iomem *regs = ap->regs;
1677 short i, idx;
1678
1679
1680 prefetchw(&ap->cur_rx_bufs);
1681
1682 idx = ap->rx_std_skbprd;
1683
1684 for (i = 0; i < nr_bufs; i++) {
1685 struct sk_buff *skb;
1686 struct rx_desc *rd;
1687 dma_addr_t mapping;
1688
1689 skb = alloc_skb(ACE_STD_BUFSIZE + NET_IP_ALIGN, GFP_ATOMIC);
1690 if (!skb)
1691 break;
1692
1693 skb_reserve(skb, NET_IP_ALIGN);
1694 mapping = pci_map_page(ap->pdev, virt_to_page(skb->data),
1695 offset_in_page(skb->data),
1696 ACE_STD_BUFSIZE,
1697 PCI_DMA_FROMDEVICE);
1698 ap->skb->rx_std_skbuff[idx].skb = skb;
1699 pci_unmap_addr_set(&ap->skb->rx_std_skbuff[idx],
1700 mapping, mapping);
1701
1702 rd = &ap->rx_std_ring[idx];
1703 set_aceaddr(&rd->addr, mapping);
1704 rd->size = ACE_STD_BUFSIZE;
1705 rd->idx = idx;
1706 idx = (idx + 1) % RX_STD_RING_ENTRIES;
1707 }
1708
1709 if (!i)
1710 goto error_out;
1711
1712 atomic_add(i, &ap->cur_rx_bufs);
1713 ap->rx_std_skbprd = idx;
1714
1715 if (ACE_IS_TIGON_I(ap)) {
1716 struct cmd cmd;
1717 cmd.evt = C_SET_RX_PRD_IDX;
1718 cmd.code = 0;
1719 cmd.idx = ap->rx_std_skbprd;
1720 ace_issue_cmd(regs, &cmd);
1721 } else {
1722 writel(idx, &regs->RxStdPrd);
1723 wmb();
1724 }
1725
1726 out:
1727 clear_bit(0, &ap->std_refill_busy);
1728 return;
1729
1730 error_out:
1731 printk(KERN_INFO "Out of memory when allocating "
1732 "standard receive buffers\n");
1733 goto out;
1734}
1735
1736
1737static void ace_load_mini_rx_ring(struct ace_private *ap, int nr_bufs)
1738{
1739 struct ace_regs __iomem *regs = ap->regs;
1740 short i, idx;
1741
1742 prefetchw(&ap->cur_mini_bufs);
1743
1744 idx = ap->rx_mini_skbprd;
1745 for (i = 0; i < nr_bufs; i++) {
1746 struct sk_buff *skb;
1747 struct rx_desc *rd;
1748 dma_addr_t mapping;
1749
1750 skb = alloc_skb(ACE_MINI_BUFSIZE + NET_IP_ALIGN, GFP_ATOMIC);
1751 if (!skb)
1752 break;
1753
1754 skb_reserve(skb, NET_IP_ALIGN);
1755 mapping = pci_map_page(ap->pdev, virt_to_page(skb->data),
1756 offset_in_page(skb->data),
1757 ACE_MINI_BUFSIZE,
1758 PCI_DMA_FROMDEVICE);
1759 ap->skb->rx_mini_skbuff[idx].skb = skb;
1760 pci_unmap_addr_set(&ap->skb->rx_mini_skbuff[idx],
1761 mapping, mapping);
1762
1763 rd = &ap->rx_mini_ring[idx];
1764 set_aceaddr(&rd->addr, mapping);
1765 rd->size = ACE_MINI_BUFSIZE;
1766 rd->idx = idx;
1767 idx = (idx + 1) % RX_MINI_RING_ENTRIES;
1768 }
1769
1770 if (!i)
1771 goto error_out;
1772
1773 atomic_add(i, &ap->cur_mini_bufs);
1774
1775 ap->rx_mini_skbprd = idx;
1776
1777 writel(idx, &regs->RxMiniPrd);
1778 wmb();
1779
1780 out:
1781 clear_bit(0, &ap->mini_refill_busy);
1782 return;
1783 error_out:
1784 printk(KERN_INFO "Out of memory when allocating "
1785 "mini receive buffers\n");
1786 goto out;
1787}
1788
1789
1790/*
1791 * Load the jumbo rx ring, this may happen at any time if the MTU
1792 * is changed to a value > 1500.
1793 */
1794static void ace_load_jumbo_rx_ring(struct ace_private *ap, int nr_bufs)
1795{
1796 struct ace_regs __iomem *regs = ap->regs;
1797 short i, idx;
1798
1799 idx = ap->rx_jumbo_skbprd;
1800
1801 for (i = 0; i < nr_bufs; i++) {
1802 struct sk_buff *skb;
1803 struct rx_desc *rd;
1804 dma_addr_t mapping;
1805
1806 skb = alloc_skb(ACE_JUMBO_BUFSIZE + NET_IP_ALIGN, GFP_ATOMIC);
1807 if (!skb)
1808 break;
1809
1810 skb_reserve(skb, NET_IP_ALIGN);
1811 mapping = pci_map_page(ap->pdev, virt_to_page(skb->data),
1812 offset_in_page(skb->data),
1813 ACE_JUMBO_BUFSIZE,
1814 PCI_DMA_FROMDEVICE);
1815 ap->skb->rx_jumbo_skbuff[idx].skb = skb;
1816 pci_unmap_addr_set(&ap->skb->rx_jumbo_skbuff[idx],
1817 mapping, mapping);
1818
1819 rd = &ap->rx_jumbo_ring[idx];
1820 set_aceaddr(&rd->addr, mapping);
1821 rd->size = ACE_JUMBO_BUFSIZE;
1822 rd->idx = idx;
1823 idx = (idx + 1) % RX_JUMBO_RING_ENTRIES;
1824 }
1825
1826 if (!i)
1827 goto error_out;
1828
1829 atomic_add(i, &ap->cur_jumbo_bufs);
1830 ap->rx_jumbo_skbprd = idx;
1831
1832 if (ACE_IS_TIGON_I(ap)) {
1833 struct cmd cmd;
1834 cmd.evt = C_SET_RX_JUMBO_PRD_IDX;
1835 cmd.code = 0;
1836 cmd.idx = ap->rx_jumbo_skbprd;
1837 ace_issue_cmd(regs, &cmd);
1838 } else {
1839 writel(idx, &regs->RxJumboPrd);
1840 wmb();
1841 }
1842
1843 out:
1844 clear_bit(0, &ap->jumbo_refill_busy);
1845 return;
1846 error_out:
1847 if (net_ratelimit())
1848 printk(KERN_INFO "Out of memory when allocating "
1849 "jumbo receive buffers\n");
1850 goto out;
1851}
1852
1853
1854/*
1855 * All events are considered to be slow (RX/TX ints do not generate
1856 * events) and are handled here, outside the main interrupt handler,
1857 * to reduce the size of the handler.
1858 */
1859static u32 ace_handle_event(struct net_device *dev, u32 evtcsm, u32 evtprd)
1860{
1861 struct ace_private *ap;
1862
1863 ap = netdev_priv(dev);
1864
1865 while (evtcsm != evtprd) {
1866 switch (ap->evt_ring[evtcsm].evt) {
1867 case E_FW_RUNNING:
1868 printk(KERN_INFO "%s: Firmware up and running\n",
1869 ap->name);
1870 ap->fw_running = 1;
1871 wmb();
1872 break;
1873 case E_STATS_UPDATED:
1874 break;
1875 case E_LNK_STATE:
1876 {
1877 u16 code = ap->evt_ring[evtcsm].code;
1878 switch (code) {
1879 case E_C_LINK_UP:
1880 {
1881 u32 state = readl(&ap->regs->GigLnkState);
1882 printk(KERN_WARNING "%s: Optical link UP "
1883 "(%s Duplex, Flow Control: %s%s)\n",
1884 ap->name,
1885 state & LNK_FULL_DUPLEX ? "Full":"Half",
1886 state & LNK_TX_FLOW_CTL_Y ? "TX " : "",
1887 state & LNK_RX_FLOW_CTL_Y ? "RX" : "");
1888 break;
1889 }
1890 case E_C_LINK_DOWN:
1891 printk(KERN_WARNING "%s: Optical link DOWN\n",
1892 ap->name);
1893 break;
1894 case E_C_LINK_10_100:
1895 printk(KERN_WARNING "%s: 10/100BaseT link "
1896 "UP\n", ap->name);
1897 break;
1898 default:
1899 printk(KERN_ERR "%s: Unknown optical link "
1900 "state %02x\n", ap->name, code);
1901 }
1902 break;
1903 }
1904 case E_ERROR:
1905 switch(ap->evt_ring[evtcsm].code) {
1906 case E_C_ERR_INVAL_CMD:
1907 printk(KERN_ERR "%s: invalid command error\n",
1908 ap->name);
1909 break;
1910 case E_C_ERR_UNIMP_CMD:
1911 printk(KERN_ERR "%s: unimplemented command "
1912 "error\n", ap->name);
1913 break;
1914 case E_C_ERR_BAD_CFG:
1915 printk(KERN_ERR "%s: bad config error\n",
1916 ap->name);
1917 break;
1918 default:
1919 printk(KERN_ERR "%s: unknown error %02x\n",
1920 ap->name, ap->evt_ring[evtcsm].code);
1921 }
1922 break;
1923 case E_RESET_JUMBO_RNG:
1924 {
1925 int i;
1926 for (i = 0; i < RX_JUMBO_RING_ENTRIES; i++) {
1927 if (ap->skb->rx_jumbo_skbuff[i].skb) {
1928 ap->rx_jumbo_ring[i].size = 0;
1929 set_aceaddr(&ap->rx_jumbo_ring[i].addr, 0);
1930 dev_kfree_skb(ap->skb->rx_jumbo_skbuff[i].skb);
1931 ap->skb->rx_jumbo_skbuff[i].skb = NULL;
1932 }
1933 }
1934
1935 if (ACE_IS_TIGON_I(ap)) {
1936 struct cmd cmd;
1937 cmd.evt = C_SET_RX_JUMBO_PRD_IDX;
1938 cmd.code = 0;
1939 cmd.idx = 0;
1940 ace_issue_cmd(ap->regs, &cmd);
1941 } else {
1942 writel(0, &((ap->regs)->RxJumboPrd));
1943 wmb();
1944 }
1945
1946 ap->jumbo = 0;
1947 ap->rx_jumbo_skbprd = 0;
1948 printk(KERN_INFO "%s: Jumbo ring flushed\n",
1949 ap->name);
1950 clear_bit(0, &ap->jumbo_refill_busy);
1951 break;
1952 }
1953 default:
1954 printk(KERN_ERR "%s: Unhandled event 0x%02x\n",
1955 ap->name, ap->evt_ring[evtcsm].evt);
1956 }
1957 evtcsm = (evtcsm + 1) % EVT_RING_ENTRIES;
1958 }
1959
1960 return evtcsm;
1961}
1962
1963
1964static void ace_rx_int(struct net_device *dev, u32 rxretprd, u32 rxretcsm)
1965{
1966 struct ace_private *ap = netdev_priv(dev);
1967 u32 idx;
1968 int mini_count = 0, std_count = 0;
1969
1970 idx = rxretcsm;
1971
1972 prefetchw(&ap->cur_rx_bufs);
1973 prefetchw(&ap->cur_mini_bufs);
1974
1975 while (idx != rxretprd) {
1976 struct ring_info *rip;
1977 struct sk_buff *skb;
1978 struct rx_desc *rxdesc, *retdesc;
1979 u32 skbidx;
1980 int bd_flags, desc_type, mapsize;
1981 u16 csum;
1982
1983
1984 /* make sure the rx descriptor isn't read before rxretprd */
1985 if (idx == rxretcsm)
1986 rmb();
1987
1988 retdesc = &ap->rx_return_ring[idx];
1989 skbidx = retdesc->idx;
1990 bd_flags = retdesc->flags;
1991 desc_type = bd_flags & (BD_FLG_JUMBO | BD_FLG_MINI);
1992
1993 switch(desc_type) {
1994 /*
1995 * Normal frames do not have any flags set
1996 *
1997 * Mini and normal frames arrive frequently,
1998 * so use a local counter to avoid doing
1999 * atomic operations for each packet arriving.
2000 */
2001 case 0:
2002 rip = &ap->skb->rx_std_skbuff[skbidx];
2003 mapsize = ACE_STD_BUFSIZE;
2004 rxdesc = &ap->rx_std_ring[skbidx];
2005 std_count++;
2006 break;
2007 case BD_FLG_JUMBO:
2008 rip = &ap->skb->rx_jumbo_skbuff[skbidx];
2009 mapsize = ACE_JUMBO_BUFSIZE;
2010 rxdesc = &ap->rx_jumbo_ring[skbidx];
2011 atomic_dec(&ap->cur_jumbo_bufs);
2012 break;
2013 case BD_FLG_MINI:
2014 rip = &ap->skb->rx_mini_skbuff[skbidx];
2015 mapsize = ACE_MINI_BUFSIZE;
2016 rxdesc = &ap->rx_mini_ring[skbidx];
2017 mini_count++;
2018 break;
2019 default:
2020 printk(KERN_INFO "%s: unknown frame type (0x%02x) "
2021 "returned by NIC\n", dev->name,
2022 retdesc->flags);
2023 goto error;
2024 }
2025
2026 skb = rip->skb;
2027 rip->skb = NULL;
2028 pci_unmap_page(ap->pdev,
2029 pci_unmap_addr(rip, mapping),
2030 mapsize,
2031 PCI_DMA_FROMDEVICE);
2032 skb_put(skb, retdesc->size);
2033
2034 /*
2035 * Fly baby, fly!
2036 */
2037 csum = retdesc->tcp_udp_csum;
2038
2039 skb->dev = dev;
2040 skb->protocol = eth_type_trans(skb, dev);
2041
2042 /*
2043 * Instead of forcing the poor tigon mips cpu to calculate
2044 * pseudo hdr checksum, we do this ourselves.
2045 */
2046 if (bd_flags & BD_FLG_TCP_UDP_SUM) {
2047 skb->csum = htons(csum);
2048 skb->ip_summed = CHECKSUM_HW;
2049 } else {
2050 skb->ip_summed = CHECKSUM_NONE;
2051 }
2052
2053 /* send it up */
2054#if ACENIC_DO_VLAN
2055 if (ap->vlgrp && (bd_flags & BD_FLG_VLAN_TAG)) {
2056 vlan_hwaccel_rx(skb, ap->vlgrp, retdesc->vlan);
2057 } else
2058#endif
2059 netif_rx(skb);
2060
2061 dev->last_rx = jiffies;
2062 ap->stats.rx_packets++;
2063 ap->stats.rx_bytes += retdesc->size;
2064
2065 idx = (idx + 1) % RX_RETURN_RING_ENTRIES;
2066 }
2067
2068 atomic_sub(std_count, &ap->cur_rx_bufs);
2069 if (!ACE_IS_TIGON_I(ap))
2070 atomic_sub(mini_count, &ap->cur_mini_bufs);
2071
2072 out:
2073 /*
2074 * According to the documentation RxRetCsm is obsolete with
2075 * the 12.3.x Firmware - my Tigon I NICs seem to disagree!
2076 */
2077 if (ACE_IS_TIGON_I(ap)) {
2078 writel(idx, &ap->regs->RxRetCsm);
2079 }
2080 ap->cur_rx = idx;
2081
2082 return;
2083 error:
2084 idx = rxretprd;
2085 goto out;
2086}
2087
2088
2089static inline void ace_tx_int(struct net_device *dev,
2090 u32 txcsm, u32 idx)
2091{
2092 struct ace_private *ap = netdev_priv(dev);
2093
2094 do {
2095 struct sk_buff *skb;
2096 dma_addr_t mapping;
2097 struct tx_ring_info *info;
2098
2099 info = ap->skb->tx_skbuff + idx;
2100 skb = info->skb;
2101 mapping = pci_unmap_addr(info, mapping);
2102
2103 if (mapping) {
2104 pci_unmap_page(ap->pdev, mapping,
2105 pci_unmap_len(info, maplen),
2106 PCI_DMA_TODEVICE);
2107 pci_unmap_addr_set(info, mapping, 0);
2108 }
2109
2110 if (skb) {
2111 ap->stats.tx_packets++;
2112 ap->stats.tx_bytes += skb->len;
2113 dev_kfree_skb_irq(skb);
2114 info->skb = NULL;
2115 }
2116
2117 idx = (idx + 1) % ACE_TX_RING_ENTRIES(ap);
2118 } while (idx != txcsm);
2119
2120 if (netif_queue_stopped(dev))
2121 netif_wake_queue(dev);
2122
2123 wmb();
2124 ap->tx_ret_csm = txcsm;
2125
2126 /* So... tx_ret_csm is advanced _after_ check for device wakeup.
2127 *
2128 * We could try to make it before. In this case we would get
2129 * the following race condition: hard_start_xmit on other cpu
2130 * enters after we advanced tx_ret_csm and fills space,
2131 * which we have just freed, so that we make illegal device wakeup.
2132 * There is no good way to workaround this (at entry
2133 * to ace_start_xmit detects this condition and prevents
2134 * ring corruption, but it is not a good workaround.)
2135 *
2136 * When tx_ret_csm is advanced after, we wake up device _only_
2137 * if we really have some space in ring (though the core doing
2138 * hard_start_xmit can see full ring for some period and has to
2139 * synchronize.) Superb.
2140 * BUT! We get another subtle race condition. hard_start_xmit
2141 * may think that ring is full between wakeup and advancing
2142 * tx_ret_csm and will stop device instantly! It is not so bad.
2143 * We are guaranteed that there is something in ring, so that
2144 * the next irq will resume transmission. To speedup this we could
2145 * mark descriptor, which closes ring with BD_FLG_COAL_NOW
2146 * (see ace_start_xmit).
2147 *
2148 * Well, this dilemma exists in all lock-free devices.
2149 * We, following scheme used in drivers by Donald Becker,
2150 * select the least dangerous.
2151 * --ANK
2152 */
2153}
2154
2155
2156static irqreturn_t ace_interrupt(int irq, void *dev_id, struct pt_regs *ptregs)
2157{
2158 struct net_device *dev = (struct net_device *)dev_id;
2159 struct ace_private *ap = netdev_priv(dev);
2160 struct ace_regs __iomem *regs = ap->regs;
2161 u32 idx;
2162 u32 txcsm, rxretcsm, rxretprd;
2163 u32 evtcsm, evtprd;
2164
2165 /*
2166 * In case of PCI shared interrupts or spurious interrupts,
2167 * we want to make sure it is actually our interrupt before
2168 * spending any time in here.
2169 */
2170 if (!(readl(&regs->HostCtrl) & IN_INT))
2171 return IRQ_NONE;
2172
2173 /*
2174 * ACK intr now. Otherwise we will lose updates to rx_ret_prd,
2175 * which happened _after_ rxretprd = *ap->rx_ret_prd; but before
2176 * writel(0, &regs->Mb0Lo).
2177 *
2178 * "IRQ avoidance" recommended in docs applies to IRQs served
2179 * threads and it is wrong even for that case.
2180 */
2181 writel(0, &regs->Mb0Lo);
2182 readl(&regs->Mb0Lo);
2183
2184 /*
2185 * There is no conflict between transmit handling in
2186 * start_xmit and receive processing, thus there is no reason
2187 * to take a spin lock for RX handling. Wait until we start
2188 * working on the other stuff - hey we don't need a spin lock
2189 * anymore.
2190 */
2191 rxretprd = *ap->rx_ret_prd;
2192 rxretcsm = ap->cur_rx;
2193
2194 if (rxretprd != rxretcsm)
2195 ace_rx_int(dev, rxretprd, rxretcsm);
2196
2197 txcsm = *ap->tx_csm;
2198 idx = ap->tx_ret_csm;
2199
2200 if (txcsm != idx) {
2201 /*
2202 * If each skb takes only one descriptor this check degenerates
2203 * to identity, because new space has just been opened.
2204 * But if skbs are fragmented we must check that this index
2205 * update releases enough of space, otherwise we just
2206 * wait for device to make more work.
2207 */
2208 if (!tx_ring_full(ap, txcsm, ap->tx_prd))
2209 ace_tx_int(dev, txcsm, idx);
2210 }
2211
2212 evtcsm = readl(&regs->EvtCsm);
2213 evtprd = *ap->evt_prd;
2214
2215 if (evtcsm != evtprd) {
2216 evtcsm = ace_handle_event(dev, evtcsm, evtprd);
2217 writel(evtcsm, &regs->EvtCsm);
2218 }
2219
2220 /*
2221 * This has to go last in the interrupt handler and run with
2222 * the spin lock released ... what lock?
2223 */
2224 if (netif_running(dev)) {
2225 int cur_size;
2226 int run_tasklet = 0;
2227
2228 cur_size = atomic_read(&ap->cur_rx_bufs);
2229 if (cur_size < RX_LOW_STD_THRES) {
2230 if ((cur_size < RX_PANIC_STD_THRES) &&
2231 !test_and_set_bit(0, &ap->std_refill_busy)) {
2232#ifdef DEBUG
2233 printk("low on std buffers %i\n", cur_size);
2234#endif
2235 ace_load_std_rx_ring(ap,
2236 RX_RING_SIZE - cur_size);
2237 } else
2238 run_tasklet = 1;
2239 }
2240
2241 if (!ACE_IS_TIGON_I(ap)) {
2242 cur_size = atomic_read(&ap->cur_mini_bufs);
2243 if (cur_size < RX_LOW_MINI_THRES) {
2244 if ((cur_size < RX_PANIC_MINI_THRES) &&
2245 !test_and_set_bit(0,
2246 &ap->mini_refill_busy)) {
2247#ifdef DEBUG
2248 printk("low on mini buffers %i\n",
2249 cur_size);
2250#endif
2251 ace_load_mini_rx_ring(ap, RX_MINI_SIZE - cur_size);
2252 } else
2253 run_tasklet = 1;
2254 }
2255 }
2256
2257 if (ap->jumbo) {
2258 cur_size = atomic_read(&ap->cur_jumbo_bufs);
2259 if (cur_size < RX_LOW_JUMBO_THRES) {
2260 if ((cur_size < RX_PANIC_JUMBO_THRES) &&
2261 !test_and_set_bit(0,
2262 &ap->jumbo_refill_busy)){
2263#ifdef DEBUG
2264 printk("low on jumbo buffers %i\n",
2265 cur_size);
2266#endif
2267 ace_load_jumbo_rx_ring(ap, RX_JUMBO_SIZE - cur_size);
2268 } else
2269 run_tasklet = 1;
2270 }
2271 }
2272 if (run_tasklet && !ap->tasklet_pending) {
2273 ap->tasklet_pending = 1;
2274 tasklet_schedule(&ap->ace_tasklet);
2275 }
2276 }
2277
2278 return IRQ_HANDLED;
2279}
2280
2281
2282#if ACENIC_DO_VLAN
2283static void ace_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
2284{
2285 struct ace_private *ap = netdev_priv(dev);
2286 unsigned long flags;
2287
2288 local_irq_save(flags);
2289 ace_mask_irq(dev);
2290
2291 ap->vlgrp = grp;
2292
2293 ace_unmask_irq(dev);
2294 local_irq_restore(flags);
2295}
2296
2297
2298static void ace_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid)
2299{
2300 struct ace_private *ap = netdev_priv(dev);
2301 unsigned long flags;
2302
2303 local_irq_save(flags);
2304 ace_mask_irq(dev);
2305
2306 if (ap->vlgrp)
2307 ap->vlgrp->vlan_devices[vid] = NULL;
2308
2309 ace_unmask_irq(dev);
2310 local_irq_restore(flags);
2311}
2312#endif /* ACENIC_DO_VLAN */
2313
2314
2315static int ace_open(struct net_device *dev)
2316{
2317 struct ace_private *ap = netdev_priv(dev);
2318 struct ace_regs __iomem *regs = ap->regs;
2319 struct cmd cmd;
2320
2321 if (!(ap->fw_running)) {
2322 printk(KERN_WARNING "%s: Firmware not running!\n", dev->name);
2323 return -EBUSY;
2324 }
2325
2326 writel(dev->mtu + ETH_HLEN + 4, &regs->IfMtu);
2327
2328 cmd.evt = C_CLEAR_STATS;
2329 cmd.code = 0;
2330 cmd.idx = 0;
2331 ace_issue_cmd(regs, &cmd);
2332
2333 cmd.evt = C_HOST_STATE;
2334 cmd.code = C_C_STACK_UP;
2335 cmd.idx = 0;
2336 ace_issue_cmd(regs, &cmd);
2337
2338 if (ap->jumbo &&
2339 !test_and_set_bit(0, &ap->jumbo_refill_busy))
2340 ace_load_jumbo_rx_ring(ap, RX_JUMBO_SIZE);
2341
2342 if (dev->flags & IFF_PROMISC) {
2343 cmd.evt = C_SET_PROMISC_MODE;
2344 cmd.code = C_C_PROMISC_ENABLE;
2345 cmd.idx = 0;
2346 ace_issue_cmd(regs, &cmd);
2347
2348 ap->promisc = 1;
2349 }else
2350 ap->promisc = 0;
2351 ap->mcast_all = 0;
2352
2353#if 0
2354 cmd.evt = C_LNK_NEGOTIATION;
2355 cmd.code = 0;
2356 cmd.idx = 0;
2357 ace_issue_cmd(regs, &cmd);
2358#endif
2359
2360 netif_start_queue(dev);
2361
2362 /*
2363 * Setup the bottom half rx ring refill handler
2364 */
2365 tasklet_init(&ap->ace_tasklet, ace_tasklet, (unsigned long)dev);
2366 return 0;
2367}
2368
2369
2370static int ace_close(struct net_device *dev)
2371{
2372 struct ace_private *ap = netdev_priv(dev);
2373 struct ace_regs __iomem *regs = ap->regs;
2374 struct cmd cmd;
2375 unsigned long flags;
2376 short i;
2377
2378 /*
2379 * Without (or before) releasing irq and stopping hardware, this
2380 * is an absolute non-sense, by the way. It will be reset instantly
2381 * by the first irq.
2382 */
2383 netif_stop_queue(dev);
2384
2385
2386 if (ap->promisc) {
2387 cmd.evt = C_SET_PROMISC_MODE;
2388 cmd.code = C_C_PROMISC_DISABLE;
2389 cmd.idx = 0;
2390 ace_issue_cmd(regs, &cmd);
2391 ap->promisc = 0;
2392 }
2393
2394 cmd.evt = C_HOST_STATE;
2395 cmd.code = C_C_STACK_DOWN;
2396 cmd.idx = 0;
2397 ace_issue_cmd(regs, &cmd);
2398
2399 tasklet_kill(&ap->ace_tasklet);
2400
2401 /*
2402 * Make sure one CPU is not processing packets while
2403 * buffers are being released by another.
2404 */
2405
2406 local_irq_save(flags);
2407 ace_mask_irq(dev);
2408
2409 for (i = 0; i < ACE_TX_RING_ENTRIES(ap); i++) {
2410 struct sk_buff *skb;
2411 dma_addr_t mapping;
2412 struct tx_ring_info *info;
2413
2414 info = ap->skb->tx_skbuff + i;
2415 skb = info->skb;
2416 mapping = pci_unmap_addr(info, mapping);
2417
2418 if (mapping) {
2419 if (ACE_IS_TIGON_I(ap)) {
2420 struct tx_desc __iomem *tx
2421 = (struct tx_desc __iomem *) &ap->tx_ring[i];
2422 writel(0, &tx->addr.addrhi);
2423 writel(0, &tx->addr.addrlo);
2424 writel(0, &tx->flagsize);
2425 } else
2426 memset(ap->tx_ring + i, 0,
2427 sizeof(struct tx_desc));
2428 pci_unmap_page(ap->pdev, mapping,
2429 pci_unmap_len(info, maplen),
2430 PCI_DMA_TODEVICE);
2431 pci_unmap_addr_set(info, mapping, 0);
2432 }
2433 if (skb) {
2434 dev_kfree_skb(skb);
2435 info->skb = NULL;
2436 }
2437 }
2438
2439 if (ap->jumbo) {
2440 cmd.evt = C_RESET_JUMBO_RNG;
2441 cmd.code = 0;
2442 cmd.idx = 0;
2443 ace_issue_cmd(regs, &cmd);
2444 }
2445
2446 ace_unmask_irq(dev);
2447 local_irq_restore(flags);
2448
2449 return 0;
2450}
2451
2452
2453static inline dma_addr_t
2454ace_map_tx_skb(struct ace_private *ap, struct sk_buff *skb,
2455 struct sk_buff *tail, u32 idx)
2456{
2457 dma_addr_t mapping;
2458 struct tx_ring_info *info;
2459
2460 mapping = pci_map_page(ap->pdev, virt_to_page(skb->data),
2461 offset_in_page(skb->data),
2462 skb->len, PCI_DMA_TODEVICE);
2463
2464 info = ap->skb->tx_skbuff + idx;
2465 info->skb = tail;
2466 pci_unmap_addr_set(info, mapping, mapping);
2467 pci_unmap_len_set(info, maplen, skb->len);
2468 return mapping;
2469}
2470
2471
2472static inline void
2473ace_load_tx_bd(struct ace_private *ap, struct tx_desc *desc, u64 addr,
2474 u32 flagsize, u32 vlan_tag)
2475{
2476#if !USE_TX_COAL_NOW
2477 flagsize &= ~BD_FLG_COAL_NOW;
2478#endif
2479
2480 if (ACE_IS_TIGON_I(ap)) {
2481 struct tx_desc __iomem *io = (struct tx_desc __iomem *) desc;
2482 writel(addr >> 32, &io->addr.addrhi);
2483 writel(addr & 0xffffffff, &io->addr.addrlo);
2484 writel(flagsize, &io->flagsize);
2485#if ACENIC_DO_VLAN
2486 writel(vlan_tag, &io->vlanres);
2487#endif
2488 } else {
2489 desc->addr.addrhi = addr >> 32;
2490 desc->addr.addrlo = addr;
2491 desc->flagsize = flagsize;
2492#if ACENIC_DO_VLAN
2493 desc->vlanres = vlan_tag;
2494#endif
2495 }
2496}
2497
2498
2499static int ace_start_xmit(struct sk_buff *skb, struct net_device *dev)
2500{
2501 struct ace_private *ap = netdev_priv(dev);
2502 struct ace_regs __iomem *regs = ap->regs;
2503 struct tx_desc *desc;
2504 u32 idx, flagsize;
2505 unsigned long maxjiff = jiffies + 3*HZ;
2506
2507restart:
2508 idx = ap->tx_prd;
2509
2510 if (tx_ring_full(ap, ap->tx_ret_csm, idx))
2511 goto overflow;
2512
2513 if (!skb_shinfo(skb)->nr_frags) {
2514 dma_addr_t mapping;
2515 u32 vlan_tag = 0;
2516
2517 mapping = ace_map_tx_skb(ap, skb, skb, idx);
2518 flagsize = (skb->len << 16) | (BD_FLG_END);
2519 if (skb->ip_summed == CHECKSUM_HW)
2520 flagsize |= BD_FLG_TCP_UDP_SUM;
2521#if ACENIC_DO_VLAN
2522 if (vlan_tx_tag_present(skb)) {
2523 flagsize |= BD_FLG_VLAN_TAG;
2524 vlan_tag = vlan_tx_tag_get(skb);
2525 }
2526#endif
2527 desc = ap->tx_ring + idx;
2528 idx = (idx + 1) % ACE_TX_RING_ENTRIES(ap);
2529
2530 /* Look at ace_tx_int for explanations. */
2531 if (tx_ring_full(ap, ap->tx_ret_csm, idx))
2532 flagsize |= BD_FLG_COAL_NOW;
2533
2534 ace_load_tx_bd(ap, desc, mapping, flagsize, vlan_tag);
2535 } else {
2536 dma_addr_t mapping;
2537 u32 vlan_tag = 0;
2538 int i, len = 0;
2539
2540 mapping = ace_map_tx_skb(ap, skb, NULL, idx);
2541 flagsize = (skb_headlen(skb) << 16);
2542 if (skb->ip_summed == CHECKSUM_HW)
2543 flagsize |= BD_FLG_TCP_UDP_SUM;
2544#if ACENIC_DO_VLAN
2545 if (vlan_tx_tag_present(skb)) {
2546 flagsize |= BD_FLG_VLAN_TAG;
2547 vlan_tag = vlan_tx_tag_get(skb);
2548 }
2549#endif
2550
2551 ace_load_tx_bd(ap, ap->tx_ring + idx, mapping, flagsize, vlan_tag);
2552
2553 idx = (idx + 1) % ACE_TX_RING_ENTRIES(ap);
2554
2555 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
2556 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2557 struct tx_ring_info *info;
2558
2559 len += frag->size;
2560 info = ap->skb->tx_skbuff + idx;
2561 desc = ap->tx_ring + idx;
2562
2563 mapping = pci_map_page(ap->pdev, frag->page,
2564 frag->page_offset, frag->size,
2565 PCI_DMA_TODEVICE);
2566
2567 flagsize = (frag->size << 16);
2568 if (skb->ip_summed == CHECKSUM_HW)
2569 flagsize |= BD_FLG_TCP_UDP_SUM;
2570 idx = (idx + 1) % ACE_TX_RING_ENTRIES(ap);
2571
2572 if (i == skb_shinfo(skb)->nr_frags - 1) {
2573 flagsize |= BD_FLG_END;
2574 if (tx_ring_full(ap, ap->tx_ret_csm, idx))
2575 flagsize |= BD_FLG_COAL_NOW;
2576
2577 /*
2578 * Only the last fragment frees
2579 * the skb!
2580 */
2581 info->skb = skb;
2582 } else {
2583 info->skb = NULL;
2584 }
2585 pci_unmap_addr_set(info, mapping, mapping);
2586 pci_unmap_len_set(info, maplen, frag->size);
2587 ace_load_tx_bd(ap, desc, mapping, flagsize, vlan_tag);
2588 }
2589 }
2590
2591 wmb();
2592 ap->tx_prd = idx;
2593 ace_set_txprd(regs, ap, idx);
2594
2595 if (flagsize & BD_FLG_COAL_NOW) {
2596 netif_stop_queue(dev);
2597
2598 /*
2599 * A TX-descriptor producer (an IRQ) might have gotten
2600 * inbetween, making the ring free again. Since xmit is
2601 * serialized, this is the only situation we have to
2602 * re-test.
2603 */
2604 if (!tx_ring_full(ap, ap->tx_ret_csm, idx))
2605 netif_wake_queue(dev);
2606 }
2607
2608 dev->trans_start = jiffies;
2609 return NETDEV_TX_OK;
2610
2611overflow:
2612 /*
2613 * This race condition is unavoidable with lock-free drivers.
2614 * We wake up the queue _before_ tx_prd is advanced, so that we can
2615 * enter hard_start_xmit too early, while tx ring still looks closed.
2616 * This happens ~1-4 times per 100000 packets, so that we can allow
2617 * to loop syncing to other CPU. Probably, we need an additional
2618 * wmb() in ace_tx_intr as well.
2619 *
2620 * Note that this race is relieved by reserving one more entry
2621 * in tx ring than it is necessary (see original non-SG driver).
2622 * However, with SG we need to reserve 2*MAX_SKB_FRAGS+1, which
2623 * is already overkill.
2624 *
2625 * Alternative is to return with 1 not throttling queue. In this
2626 * case loop becomes longer, no more useful effects.
2627 */
2628 if (time_before(jiffies, maxjiff)) {
2629 barrier();
2630 cpu_relax();
2631 goto restart;
2632 }
2633
2634 /* The ring is stuck full. */
2635 printk(KERN_WARNING "%s: Transmit ring stuck full\n", dev->name);
2636 return NETDEV_TX_BUSY;
2637}
2638
2639
2640static int ace_change_mtu(struct net_device *dev, int new_mtu)
2641{
2642 struct ace_private *ap = netdev_priv(dev);
2643 struct ace_regs __iomem *regs = ap->regs;
2644
2645 if (new_mtu > ACE_JUMBO_MTU)
2646 return -EINVAL;
2647
2648 writel(new_mtu + ETH_HLEN + 4, &regs->IfMtu);
2649 dev->mtu = new_mtu;
2650
2651 if (new_mtu > ACE_STD_MTU) {
2652 if (!(ap->jumbo)) {
2653 printk(KERN_INFO "%s: Enabling Jumbo frame "
2654 "support\n", dev->name);
2655 ap->jumbo = 1;
2656 if (!test_and_set_bit(0, &ap->jumbo_refill_busy))
2657 ace_load_jumbo_rx_ring(ap, RX_JUMBO_SIZE);
2658 ace_set_rxtx_parms(dev, 1);
2659 }
2660 } else {
2661 while (test_and_set_bit(0, &ap->jumbo_refill_busy));
2662 ace_sync_irq(dev->irq);
2663 ace_set_rxtx_parms(dev, 0);
2664 if (ap->jumbo) {
2665 struct cmd cmd;
2666
2667 cmd.evt = C_RESET_JUMBO_RNG;
2668 cmd.code = 0;
2669 cmd.idx = 0;
2670 ace_issue_cmd(regs, &cmd);
2671 }
2672 }
2673
2674 return 0;
2675}
2676
2677static int ace_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
2678{
2679 struct ace_private *ap = netdev_priv(dev);
2680 struct ace_regs __iomem *regs = ap->regs;
2681 u32 link;
2682
2683 memset(ecmd, 0, sizeof(struct ethtool_cmd));
2684 ecmd->supported =
2685 (SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full |
2686 SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full |
2687 SUPPORTED_1000baseT_Half | SUPPORTED_1000baseT_Full |
2688 SUPPORTED_Autoneg | SUPPORTED_FIBRE);
2689
2690 ecmd->port = PORT_FIBRE;
2691 ecmd->transceiver = XCVR_INTERNAL;
2692
2693 link = readl(&regs->GigLnkState);
2694 if (link & LNK_1000MB)
2695 ecmd->speed = SPEED_1000;
2696 else {
2697 link = readl(&regs->FastLnkState);
2698 if (link & LNK_100MB)
2699 ecmd->speed = SPEED_100;
2700 else if (link & LNK_10MB)
2701 ecmd->speed = SPEED_10;
2702 else
2703 ecmd->speed = 0;
2704 }
2705 if (link & LNK_FULL_DUPLEX)
2706 ecmd->duplex = DUPLEX_FULL;
2707 else
2708 ecmd->duplex = DUPLEX_HALF;
2709
2710 if (link & LNK_NEGOTIATE)
2711 ecmd->autoneg = AUTONEG_ENABLE;
2712 else
2713 ecmd->autoneg = AUTONEG_DISABLE;
2714
2715#if 0
2716 /*
2717 * Current struct ethtool_cmd is insufficient
2718 */
2719 ecmd->trace = readl(&regs->TuneTrace);
2720
2721 ecmd->txcoal = readl(&regs->TuneTxCoalTicks);
2722 ecmd->rxcoal = readl(&regs->TuneRxCoalTicks);
2723#endif
2724 ecmd->maxtxpkt = readl(&regs->TuneMaxTxDesc);
2725 ecmd->maxrxpkt = readl(&regs->TuneMaxRxDesc);
2726
2727 return 0;
2728}
2729
2730static int ace_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
2731{
2732 struct ace_private *ap = netdev_priv(dev);
2733 struct ace_regs __iomem *regs = ap->regs;
2734 u32 link, speed;
2735
2736 link = readl(&regs->GigLnkState);
2737 if (link & LNK_1000MB)
2738 speed = SPEED_1000;
2739 else {
2740 link = readl(&regs->FastLnkState);
2741 if (link & LNK_100MB)
2742 speed = SPEED_100;
2743 else if (link & LNK_10MB)
2744 speed = SPEED_10;
2745 else
2746 speed = SPEED_100;
2747 }
2748
2749 link = LNK_ENABLE | LNK_1000MB | LNK_100MB | LNK_10MB |
2750 LNK_RX_FLOW_CTL_Y | LNK_NEG_FCTL;
2751 if (!ACE_IS_TIGON_I(ap))
2752 link |= LNK_TX_FLOW_CTL_Y;
2753 if (ecmd->autoneg == AUTONEG_ENABLE)
2754 link |= LNK_NEGOTIATE;
2755 if (ecmd->speed != speed) {
2756 link &= ~(LNK_1000MB | LNK_100MB | LNK_10MB);
2757 switch (speed) {
2758 case SPEED_1000:
2759 link |= LNK_1000MB;
2760 break;
2761 case SPEED_100:
2762 link |= LNK_100MB;
2763 break;
2764 case SPEED_10:
2765 link |= LNK_10MB;
2766 break;
2767 }
2768 }
2769
2770 if (ecmd->duplex == DUPLEX_FULL)
2771 link |= LNK_FULL_DUPLEX;
2772
2773 if (link != ap->link) {
2774 struct cmd cmd;
2775 printk(KERN_INFO "%s: Renegotiating link state\n",
2776 dev->name);
2777
2778 ap->link = link;
2779 writel(link, &regs->TuneLink);
2780 if (!ACE_IS_TIGON_I(ap))
2781 writel(link, &regs->TuneFastLink);
2782 wmb();
2783
2784 cmd.evt = C_LNK_NEGOTIATION;
2785 cmd.code = 0;
2786 cmd.idx = 0;
2787 ace_issue_cmd(regs, &cmd);
2788 }
2789 return 0;
2790}
2791
2792static void ace_get_drvinfo(struct net_device *dev,
2793 struct ethtool_drvinfo *info)
2794{
2795 struct ace_private *ap = netdev_priv(dev);
2796
2797 strlcpy(info->driver, "acenic", sizeof(info->driver));
2798 snprintf(info->version, sizeof(info->version), "%i.%i.%i",
2799 tigonFwReleaseMajor, tigonFwReleaseMinor,
2800 tigonFwReleaseFix);
2801
2802 if (ap->pdev)
2803 strlcpy(info->bus_info, pci_name(ap->pdev),
2804 sizeof(info->bus_info));
2805
2806}
2807
2808/*
2809 * Set the hardware MAC address.
2810 */
2811static int ace_set_mac_addr(struct net_device *dev, void *p)
2812{
2813 struct ace_private *ap = netdev_priv(dev);
2814 struct ace_regs __iomem *regs = ap->regs;
2815 struct sockaddr *addr=p;
2816 u8 *da;
2817 struct cmd cmd;
2818
2819 if(netif_running(dev))
2820 return -EBUSY;
2821
2822 memcpy(dev->dev_addr, addr->sa_data,dev->addr_len);
2823
2824 da = (u8 *)dev->dev_addr;
2825
2826 writel(da[0] << 8 | da[1], &regs->MacAddrHi);
2827 writel((da[2] << 24) | (da[3] << 16) | (da[4] << 8) | da[5],
2828 &regs->MacAddrLo);
2829
2830 cmd.evt = C_SET_MAC_ADDR;
2831 cmd.code = 0;
2832 cmd.idx = 0;
2833 ace_issue_cmd(regs, &cmd);
2834
2835 return 0;
2836}
2837
2838
2839static void ace_set_multicast_list(struct net_device *dev)
2840{
2841 struct ace_private *ap = netdev_priv(dev);
2842 struct ace_regs __iomem *regs = ap->regs;
2843 struct cmd cmd;
2844
2845 if ((dev->flags & IFF_ALLMULTI) && !(ap->mcast_all)) {
2846 cmd.evt = C_SET_MULTICAST_MODE;
2847 cmd.code = C_C_MCAST_ENABLE;
2848 cmd.idx = 0;
2849 ace_issue_cmd(regs, &cmd);
2850 ap->mcast_all = 1;
2851 } else if (ap->mcast_all) {
2852 cmd.evt = C_SET_MULTICAST_MODE;
2853 cmd.code = C_C_MCAST_DISABLE;
2854 cmd.idx = 0;
2855 ace_issue_cmd(regs, &cmd);
2856 ap->mcast_all = 0;
2857 }
2858
2859 if ((dev->flags & IFF_PROMISC) && !(ap->promisc)) {
2860 cmd.evt = C_SET_PROMISC_MODE;
2861 cmd.code = C_C_PROMISC_ENABLE;
2862 cmd.idx = 0;
2863 ace_issue_cmd(regs, &cmd);
2864 ap->promisc = 1;
2865 }else if (!(dev->flags & IFF_PROMISC) && (ap->promisc)) {
2866 cmd.evt = C_SET_PROMISC_MODE;
2867 cmd.code = C_C_PROMISC_DISABLE;
2868 cmd.idx = 0;
2869 ace_issue_cmd(regs, &cmd);
2870 ap->promisc = 0;
2871 }
2872
2873 /*
2874 * For the time being multicast relies on the upper layers
2875 * filtering it properly. The Firmware does not allow one to
2876 * set the entire multicast list at a time and keeping track of
2877 * it here is going to be messy.
2878 */
2879 if ((dev->mc_count) && !(ap->mcast_all)) {
2880 cmd.evt = C_SET_MULTICAST_MODE;
2881 cmd.code = C_C_MCAST_ENABLE;
2882 cmd.idx = 0;
2883 ace_issue_cmd(regs, &cmd);
2884 }else if (!ap->mcast_all) {
2885 cmd.evt = C_SET_MULTICAST_MODE;
2886 cmd.code = C_C_MCAST_DISABLE;
2887 cmd.idx = 0;
2888 ace_issue_cmd(regs, &cmd);
2889 }
2890}
2891
2892
2893static struct net_device_stats *ace_get_stats(struct net_device *dev)
2894{
2895 struct ace_private *ap = netdev_priv(dev);
2896 struct ace_mac_stats __iomem *mac_stats =
2897 (struct ace_mac_stats __iomem *)ap->regs->Stats;
2898
2899 ap->stats.rx_missed_errors = readl(&mac_stats->drop_space);
2900 ap->stats.multicast = readl(&mac_stats->kept_mc);
2901 ap->stats.collisions = readl(&mac_stats->coll);
2902
2903 return &ap->stats;
2904}
2905
2906
2907static void __devinit ace_copy(struct ace_regs __iomem *regs, void *src,
2908 u32 dest, int size)
2909{
2910 void __iomem *tdest;
2911 u32 *wsrc;
2912 short tsize, i;
2913
2914 if (size <= 0)
2915 return;
2916
2917 while (size > 0) {
2918 tsize = min_t(u32, ((~dest & (ACE_WINDOW_SIZE - 1)) + 1),
2919 min_t(u32, size, ACE_WINDOW_SIZE));
2920 tdest = (void __iomem *) &regs->Window +
2921 (dest & (ACE_WINDOW_SIZE - 1));
2922 writel(dest & ~(ACE_WINDOW_SIZE - 1), &regs->WinBase);
2923 /*
2924 * This requires byte swapping on big endian, however
2925 * writel does that for us
2926 */
2927 wsrc = src;
2928 for (i = 0; i < (tsize / 4); i++) {
2929 writel(wsrc[i], tdest + i*4);
2930 }
2931 dest += tsize;
2932 src += tsize;
2933 size -= tsize;
2934 }
2935
2936 return;
2937}
2938
2939
2940static void __devinit ace_clear(struct ace_regs __iomem *regs, u32 dest, int size)
2941{
2942 void __iomem *tdest;
2943 short tsize = 0, i;
2944
2945 if (size <= 0)
2946 return;
2947
2948 while (size > 0) {
2949 tsize = min_t(u32, ((~dest & (ACE_WINDOW_SIZE - 1)) + 1),
2950 min_t(u32, size, ACE_WINDOW_SIZE));
2951 tdest = (void __iomem *) &regs->Window +
2952 (dest & (ACE_WINDOW_SIZE - 1));
2953 writel(dest & ~(ACE_WINDOW_SIZE - 1), &regs->WinBase);
2954
2955 for (i = 0; i < (tsize / 4); i++) {
2956 writel(0, tdest + i*4);
2957 }
2958
2959 dest += tsize;
2960 size -= tsize;
2961 }
2962
2963 return;
2964}
2965
2966
2967/*
2968 * Download the firmware into the SRAM on the NIC
2969 *
2970 * This operation requires the NIC to be halted and is performed with
2971 * interrupts disabled and with the spinlock hold.
2972 */
2973int __devinit ace_load_firmware(struct net_device *dev)
2974{
2975 struct ace_private *ap = netdev_priv(dev);
2976 struct ace_regs __iomem *regs = ap->regs;
2977
2978 if (!(readl(&regs->CpuCtrl) & CPU_HALTED)) {
2979 printk(KERN_ERR "%s: trying to download firmware while the "
2980 "CPU is running!\n", ap->name);
2981 return -EFAULT;
2982 }
2983
2984 /*
2985 * Do not try to clear more than 512KB or we end up seeing
2986 * funny things on NICs with only 512KB SRAM
2987 */
2988 ace_clear(regs, 0x2000, 0x80000-0x2000);
2989 if (ACE_IS_TIGON_I(ap)) {
2990 ace_copy(regs, tigonFwText, tigonFwTextAddr, tigonFwTextLen);
2991 ace_copy(regs, tigonFwData, tigonFwDataAddr, tigonFwDataLen);
2992 ace_copy(regs, tigonFwRodata, tigonFwRodataAddr,
2993 tigonFwRodataLen);
2994 ace_clear(regs, tigonFwBssAddr, tigonFwBssLen);
2995 ace_clear(regs, tigonFwSbssAddr, tigonFwSbssLen);
2996 }else if (ap->version == 2) {
2997 ace_clear(regs, tigon2FwBssAddr, tigon2FwBssLen);
2998 ace_clear(regs, tigon2FwSbssAddr, tigon2FwSbssLen);
2999 ace_copy(regs, tigon2FwText, tigon2FwTextAddr,tigon2FwTextLen);
3000 ace_copy(regs, tigon2FwRodata, tigon2FwRodataAddr,
3001 tigon2FwRodataLen);
3002 ace_copy(regs, tigon2FwData, tigon2FwDataAddr,tigon2FwDataLen);
3003 }
3004
3005 return 0;
3006}
3007
3008
3009/*
3010 * The eeprom on the AceNIC is an Atmel i2c EEPROM.
3011 *
3012 * Accessing the EEPROM is `interesting' to say the least - don't read
3013 * this code right after dinner.
3014 *
3015 * This is all about black magic and bit-banging the device .... I
3016 * wonder in what hospital they have put the guy who designed the i2c
3017 * specs.
3018 *
3019 * Oh yes, this is only the beginning!
3020 *
3021 * Thanks to Stevarino Webinski for helping tracking down the bugs in the
3022 * code i2c readout code by beta testing all my hacks.
3023 */
3024static void __devinit eeprom_start(struct ace_regs __iomem *regs)
3025{
3026 u32 local;
3027
3028 readl(&regs->LocalCtrl);
3029 udelay(ACE_SHORT_DELAY);
3030 local = readl(&regs->LocalCtrl);
3031 local |= EEPROM_DATA_OUT | EEPROM_WRITE_ENABLE;
3032 writel(local, &regs->LocalCtrl);
3033 readl(&regs->LocalCtrl);
3034 mb();
3035 udelay(ACE_SHORT_DELAY);
3036 local |= EEPROM_CLK_OUT;
3037 writel(local, &regs->LocalCtrl);
3038 readl(&regs->LocalCtrl);
3039 mb();
3040 udelay(ACE_SHORT_DELAY);
3041 local &= ~EEPROM_DATA_OUT;
3042 writel(local, &regs->LocalCtrl);
3043 readl(&regs->LocalCtrl);
3044 mb();
3045 udelay(ACE_SHORT_DELAY);
3046 local &= ~EEPROM_CLK_OUT;
3047 writel(local, &regs->LocalCtrl);
3048 readl(&regs->LocalCtrl);
3049 mb();
3050}
3051
3052
3053static void __devinit eeprom_prep(struct ace_regs __iomem *regs, u8 magic)
3054{
3055 short i;
3056 u32 local;
3057
3058 udelay(ACE_SHORT_DELAY);
3059 local = readl(&regs->LocalCtrl);
3060 local &= ~EEPROM_DATA_OUT;
3061 local |= EEPROM_WRITE_ENABLE;
3062 writel(local, &regs->LocalCtrl);
3063 readl(&regs->LocalCtrl);
3064 mb();
3065
3066 for (i = 0; i < 8; i++, magic <<= 1) {
3067 udelay(ACE_SHORT_DELAY);
3068 if (magic & 0x80)
3069 local |= EEPROM_DATA_OUT;
3070 else
3071 local &= ~EEPROM_DATA_OUT;
3072 writel(local, &regs->LocalCtrl);
3073 readl(&regs->LocalCtrl);
3074 mb();
3075
3076 udelay(ACE_SHORT_DELAY);
3077 local |= EEPROM_CLK_OUT;
3078 writel(local, &regs->LocalCtrl);
3079 readl(&regs->LocalCtrl);
3080 mb();
3081 udelay(ACE_SHORT_DELAY);
3082 local &= ~(EEPROM_CLK_OUT | EEPROM_DATA_OUT);
3083 writel(local, &regs->LocalCtrl);
3084 readl(&regs->LocalCtrl);
3085 mb();
3086 }
3087}
3088
3089
3090static int __devinit eeprom_check_ack(struct ace_regs __iomem *regs)
3091{
3092 int state;
3093 u32 local;
3094
3095 local = readl(&regs->LocalCtrl);
3096 local &= ~EEPROM_WRITE_ENABLE;
3097 writel(local, &regs->LocalCtrl);
3098 readl(&regs->LocalCtrl);
3099 mb();
3100 udelay(ACE_LONG_DELAY);
3101 local |= EEPROM_CLK_OUT;
3102 writel(local, &regs->LocalCtrl);
3103 readl(&regs->LocalCtrl);
3104 mb();
3105 udelay(ACE_SHORT_DELAY);
3106 /* sample data in middle of high clk */
3107 state = (readl(&regs->LocalCtrl) & EEPROM_DATA_IN) != 0;
3108 udelay(ACE_SHORT_DELAY);
3109 mb();
3110 writel(readl(&regs->LocalCtrl) & ~EEPROM_CLK_OUT, &regs->LocalCtrl);
3111 readl(&regs->LocalCtrl);
3112 mb();
3113
3114 return state;
3115}
3116
3117
3118static void __devinit eeprom_stop(struct ace_regs __iomem *regs)
3119{
3120 u32 local;
3121
3122 udelay(ACE_SHORT_DELAY);
3123 local = readl(&regs->LocalCtrl);
3124 local |= EEPROM_WRITE_ENABLE;
3125 writel(local, &regs->LocalCtrl);
3126 readl(&regs->LocalCtrl);
3127 mb();
3128 udelay(ACE_SHORT_DELAY);
3129 local &= ~EEPROM_DATA_OUT;
3130 writel(local, &regs->LocalCtrl);
3131 readl(&regs->LocalCtrl);
3132 mb();
3133 udelay(ACE_SHORT_DELAY);
3134 local |= EEPROM_CLK_OUT;
3135 writel(local, &regs->LocalCtrl);
3136 readl(&regs->LocalCtrl);
3137 mb();
3138 udelay(ACE_SHORT_DELAY);
3139 local |= EEPROM_DATA_OUT;
3140 writel(local, &regs->LocalCtrl);
3141 readl(&regs->LocalCtrl);
3142 mb();
3143 udelay(ACE_LONG_DELAY);
3144 local &= ~EEPROM_CLK_OUT;
3145 writel(local, &regs->LocalCtrl);
3146 mb();
3147}
3148
3149
3150/*
3151 * Read a whole byte from the EEPROM.
3152 */
3153static int __devinit read_eeprom_byte(struct net_device *dev,
3154 unsigned long offset)
3155{
3156 struct ace_private *ap = netdev_priv(dev);
3157 struct ace_regs __iomem *regs = ap->regs;
3158 unsigned long flags;
3159 u32 local;
3160 int result = 0;
3161 short i;
3162
3163 if (!dev) {
3164 printk(KERN_ERR "No device!\n");
3165 result = -ENODEV;
3166 goto out;
3167 }
3168
3169 /*
3170 * Don't take interrupts on this CPU will bit banging
3171 * the %#%#@$ I2C device
3172 */
3173 local_irq_save(flags);
3174
3175 eeprom_start(regs);
3176
3177 eeprom_prep(regs, EEPROM_WRITE_SELECT);
3178 if (eeprom_check_ack(regs)) {
3179 local_irq_restore(flags);
3180 printk(KERN_ERR "%s: Unable to sync eeprom\n", ap->name);
3181 result = -EIO;
3182 goto eeprom_read_error;
3183 }
3184
3185 eeprom_prep(regs, (offset >> 8) & 0xff);
3186 if (eeprom_check_ack(regs)) {
3187 local_irq_restore(flags);
3188 printk(KERN_ERR "%s: Unable to set address byte 0\n",
3189 ap->name);
3190 result = -EIO;
3191 goto eeprom_read_error;
3192 }
3193
3194 eeprom_prep(regs, offset & 0xff);
3195 if (eeprom_check_ack(regs)) {
3196 local_irq_restore(flags);
3197 printk(KERN_ERR "%s: Unable to set address byte 1\n",
3198 ap->name);
3199 result = -EIO;
3200 goto eeprom_read_error;
3201 }
3202
3203 eeprom_start(regs);
3204 eeprom_prep(regs, EEPROM_READ_SELECT);
3205 if (eeprom_check_ack(regs)) {
3206 local_irq_restore(flags);
3207 printk(KERN_ERR "%s: Unable to set READ_SELECT\n",
3208 ap->name);
3209 result = -EIO;
3210 goto eeprom_read_error;
3211 }
3212
3213 for (i = 0; i < 8; i++) {
3214 local = readl(&regs->LocalCtrl);
3215 local &= ~EEPROM_WRITE_ENABLE;
3216 writel(local, &regs->LocalCtrl);
3217 readl(&regs->LocalCtrl);
3218 udelay(ACE_LONG_DELAY);
3219 mb();
3220 local |= EEPROM_CLK_OUT;
3221 writel(local, &regs->LocalCtrl);
3222 readl(&regs->LocalCtrl);
3223 mb();
3224 udelay(ACE_SHORT_DELAY);
3225 /* sample data mid high clk */
3226 result = (result << 1) |
3227 ((readl(&regs->LocalCtrl) & EEPROM_DATA_IN) != 0);
3228 udelay(ACE_SHORT_DELAY);
3229 mb();
3230 local = readl(&regs->LocalCtrl);
3231 local &= ~EEPROM_CLK_OUT;
3232 writel(local, &regs->LocalCtrl);
3233 readl(&regs->LocalCtrl);
3234 udelay(ACE_SHORT_DELAY);
3235 mb();
3236 if (i == 7) {
3237 local |= EEPROM_WRITE_ENABLE;
3238 writel(local, &regs->LocalCtrl);
3239 readl(&regs->LocalCtrl);
3240 mb();
3241 udelay(ACE_SHORT_DELAY);
3242 }
3243 }
3244
3245 local |= EEPROM_DATA_OUT;
3246 writel(local, &regs->LocalCtrl);
3247 readl(&regs->LocalCtrl);
3248 mb();
3249 udelay(ACE_SHORT_DELAY);
3250 writel(readl(&regs->LocalCtrl) | EEPROM_CLK_OUT, &regs->LocalCtrl);
3251 readl(&regs->LocalCtrl);
3252 udelay(ACE_LONG_DELAY);
3253 writel(readl(&regs->LocalCtrl) & ~EEPROM_CLK_OUT, &regs->LocalCtrl);
3254 readl(&regs->LocalCtrl);
3255 mb();
3256 udelay(ACE_SHORT_DELAY);
3257 eeprom_stop(regs);
3258
3259 local_irq_restore(flags);
3260 out:
3261 return result;
3262
3263 eeprom_read_error:
3264 printk(KERN_ERR "%s: Unable to read eeprom byte 0x%02lx\n",
3265 ap->name, offset);
3266 goto out;
3267}
3268
3269
3270/*
3271 * Local variables:
3272 * compile-command: "gcc -D__SMP__ -D__KERNEL__ -DMODULE -I../../include -Wall -Wstrict-prototypes -O2 -fomit-frame-pointer -pipe -fno-strength-reduce -DMODVERSIONS -include ../../include/linux/modversions.h -c -o acenic.o acenic.c"
3273 * End:
3274 */
Linux kernel - Deliverables
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