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signals: consolidate checks for whether or not to ignore a signal
[deliverable/linux.git] / drivers / net / amd8111e.c
CommitLineData
1da177e4 1
6aa20a22
JG		 2/* Advanced Micro Devices Inc. AMD8111E Linux Network Driver
3 * Copyright (C) 2004 Advanced Micro Devices
4 *
1da177e4 5 *
1da177e4
LT		 6 * Copyright 2001,2002 Jeff Garzik <jgarzik@mandrakesoft.com> [ 8139cp.c,tg3.c ]
7 * Copyright (C) 2001, 2002 David S. Miller (davem@redhat.com)[ tg3.c]
8 * Copyright 1996-1999 Thomas Bogendoerfer [ pcnet32.c ]
9 * Derived from the lance driver written 1993,1994,1995 by Donald Becker.
10 * Copyright 1993 United States Government as represented by the
11 * Director, National Security Agency.[ pcnet32.c ]
12 * Carsten Langgaard, carstenl@mips.com [ pcnet32.c ]
13 * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
14 *
6aa20a22 15 *
1da177e4
LT		 16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License as published by
18 * the Free Software Foundation; either version 2 of the License, or
19 * (at your option) any later version.
20 *
21 * This program is distributed in the hope that it will be useful,
22 * but WITHOUT ANY WARRANTY; without even the implied warranty of
23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24 * GNU General Public License for more details.
25 *
26 * You should have received a copy of the GNU General Public License
27 * along with this program; if not, write to the Free Software
6aa20a22 28 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
1da177e4 29 * USA
6aa20a22 30
1da177e4
LT		 31Module Name:
32
33 amd8111e.c
34
35Abstract:
6aa20a22
JG		 36
37 AMD8111 based 10/100 Ethernet Controller Driver.
1da177e4
LT		 38
39Environment:
40
41 Kernel Mode
42
43Revision History:
44 3.0.0
45 Initial Revision.
46 3.0.1
47 1. Dynamic interrupt coalescing.
48 2. Removed prev_stats.
49 3. MII support.
50 4. Dynamic IPG support
51 3.0.2 05/29/2003
52 1. Bug fix: Fixed failure to send jumbo packets larger than 4k.
53 2. Bug fix: Fixed VLAN support failure.
54 3. Bug fix: Fixed receive interrupt coalescing bug.
55 4. Dynamic IPG support is disabled by default.
56 3.0.3 06/05/2003
57 1. Bug fix: Fixed failure to close the interface if SMP is enabled.
58 3.0.4 12/09/2003
59 1. Added set_mac_address routine for bonding driver support.
60 2. Tested the driver for bonding support
6aa20a22 61 3. Bug fix: Fixed mismach in actual receive buffer lenth and lenth
1da177e4 62 indicated to the h/w.
6aa20a22 63 4. Modified amd8111e_rx() routine to receive all the received packets
1da177e4
LT		 64 in the first interrupt.
65 5. Bug fix: Corrected rx_errors reported in get_stats() function.
66 3.0.5 03/22/2004
6aa20a22 67 1. Added NAPI support
1da177e4
LT		 68
69*/
70
71
1da177e4
LT		 72#include <linux/module.h>
73#include <linux/kernel.h>
74#include <linux/types.h>
75#include <linux/compiler.h>
76#include <linux/slab.h>
77#include <linux/delay.h>
78#include <linux/init.h>
79#include <linux/ioport.h>
80#include <linux/pci.h>
81#include <linux/netdevice.h>
82#include <linux/etherdevice.h>
83#include <linux/skbuff.h>
84#include <linux/ethtool.h>
85#include <linux/mii.h>
86#include <linux/if_vlan.h>
6aa20a22 87#include <linux/ctype.h>
1da177e4 88#include <linux/crc32.h>
cac8c81a 89#include <linux/dma-mapping.h>
1da177e4
LT		 90
91#include <asm/system.h>
92#include <asm/io.h>
93#include <asm/byteorder.h>
94#include <asm/uaccess.h>
95
96#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
97#define AMD8111E_VLAN_TAG_USED 1
98#else
99#define AMD8111E_VLAN_TAG_USED 0
100#endif
101
102#include "amd8111e.h"
103#define MODULE_NAME "amd8111e"
d5b20697 104#define MODULE_VERS "3.0.6"
1da177e4 105MODULE_AUTHOR("Advanced Micro Devices, Inc.");
d5b20697 106MODULE_DESCRIPTION ("AMD8111 based 10/100 Ethernet Controller. Driver Version 3.0.6");
1da177e4
LT		 107MODULE_LICENSE("GPL");
108MODULE_DEVICE_TABLE(pci, amd8111e_pci_tbl);
109module_param_array(speed_duplex, int, NULL, 0);
110MODULE_PARM_DESC(speed_duplex, "Set device speed and duplex modes, 0: Auto Negotitate, 1: 10Mbps Half Duplex, 2: 10Mbps Full Duplex, 3: 100Mbps Half Duplex, 4: 100Mbps Full Duplex");
111module_param_array(coalesce, bool, NULL, 0);
112MODULE_PARM_DESC(coalesce, "Enable or Disable interrupt coalescing, 1: Enable, 0: Disable");
113module_param_array(dynamic_ipg, bool, NULL, 0);
114MODULE_PARM_DESC(dynamic_ipg, "Enable or Disable dynamic IPG, 1: Enable, 0: Disable");
115
116static struct pci_device_id amd8111e_pci_tbl[] = {
6aa20a22 117
1da177e4
LT		 118 { PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD8111E_7462,
119 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
120 { 0, }
121
122};
6aa20a22 123/*
1da177e4
LT		 124This function will read the PHY registers.
125*/
126static int amd8111e_read_phy(struct amd8111e_priv* lp, int phy_id, int reg, u32* val)
127{
128 void __iomem *mmio = lp->mmio;
129 unsigned int reg_val;
130 unsigned int repeat= REPEAT_CNT;
131
132 reg_val = readl(mmio + PHY_ACCESS);
133 while (reg_val & PHY_CMD_ACTIVE)
134 reg_val = readl( mmio + PHY_ACCESS );
135
136 writel( PHY_RD_CMD | ((phy_id & 0x1f) << 21) |
137 ((reg & 0x1f) << 16), mmio +PHY_ACCESS);
138 do{
139 reg_val = readl(mmio + PHY_ACCESS);
140 udelay(30); /* It takes 30 us to read/write data */
141 } while (--repeat && (reg_val & PHY_CMD_ACTIVE));
142 if(reg_val & PHY_RD_ERR)
143 goto err_phy_read;
6aa20a22 144
1da177e4
LT		 145 *val = reg_val & 0xffff;
146 return 0;
6aa20a22 147err_phy_read:
1da177e4
LT		 148 *val = 0;
149 return -EINVAL;
6aa20a22 150
1da177e4
LT		 151}
152
6aa20a22
JG		 153/*
154This function will write into PHY registers.
1da177e4
LT		 155*/
156static int amd8111e_write_phy(struct amd8111e_priv* lp,int phy_id, int reg, u32 val)
157{
632155e6 158 unsigned int repeat = REPEAT_CNT;
1da177e4
LT		 159 void __iomem *mmio = lp->mmio;
160 unsigned int reg_val;
161
162 reg_val = readl(mmio + PHY_ACCESS);
163 while (reg_val & PHY_CMD_ACTIVE)
164 reg_val = readl( mmio + PHY_ACCESS );
165
166 writel( PHY_WR_CMD | ((phy_id & 0x1f) << 21) |
167 ((reg & 0x1f) << 16)|val, mmio + PHY_ACCESS);
168
169 do{
170 reg_val = readl(mmio + PHY_ACCESS);
171 udelay(30); /* It takes 30 us to read/write the data */
172 } while (--repeat && (reg_val & PHY_CMD_ACTIVE));
6aa20a22 173
1da177e4
LT		 174 if(reg_val & PHY_RD_ERR)
175 goto err_phy_write;
6aa20a22 176
1da177e4
LT		 177 return 0;
178
6aa20a22 179err_phy_write:
1da177e4 180 return -EINVAL;
6aa20a22 181
1da177e4 182}
6aa20a22 183/*
1da177e4 184This is the mii register read function provided to the mii interface.
6aa20a22 185*/
1da177e4
LT		 186static int amd8111e_mdio_read(struct net_device * dev, int phy_id, int reg_num)
187{
188 struct amd8111e_priv* lp = netdev_priv(dev);
189 unsigned int reg_val;
190
191 amd8111e_read_phy(lp,phy_id,reg_num,&reg_val);
192 return reg_val;
6aa20a22 193
1da177e4
LT		 194}
195
6aa20a22 196/*
1da177e4 197This is the mii register write function provided to the mii interface.
6aa20a22 198*/
1da177e4
LT		 199static void amd8111e_mdio_write(struct net_device * dev, int phy_id, int reg_num, int val)
200{
201 struct amd8111e_priv* lp = netdev_priv(dev);
202
203 amd8111e_write_phy(lp, phy_id, reg_num, val);
204}
205
206/*
207This function will set PHY speed. During initialization sets the original speed to 100 full.
208*/
209static void amd8111e_set_ext_phy(struct net_device *dev)
210{
211 struct amd8111e_priv *lp = netdev_priv(dev);
212 u32 bmcr,advert,tmp;
6aa20a22 213
1da177e4
LT		 214 /* Determine mii register values to set the speed */
215 advert = amd8111e_mdio_read(dev, lp->ext_phy_addr, MII_ADVERTISE);
216 tmp = advert & ~(ADVERTISE_ALL | ADVERTISE_100BASE4);
217 switch (lp->ext_phy_option){
218
219 default:
220 case SPEED_AUTONEG: /* advertise all values */
221 tmp |= ( ADVERTISE_10HALF|ADVERTISE_10FULL|
222 ADVERTISE_100HALF|ADVERTISE_100FULL) ;
223 break;
224 case SPEED10_HALF:
225 tmp |= ADVERTISE_10HALF;
226 break;
227 case SPEED10_FULL:
228 tmp |= ADVERTISE_10FULL;
229 break;
6aa20a22 230 case SPEED100_HALF:
1da177e4
LT		 231 tmp |= ADVERTISE_100HALF;
232 break;
233 case SPEED100_FULL:
234 tmp |= ADVERTISE_100FULL;
235 break;
236 }
237
238 if(advert != tmp)
239 amd8111e_mdio_write(dev, lp->ext_phy_addr, MII_ADVERTISE, tmp);
240 /* Restart auto negotiation */
241 bmcr = amd8111e_mdio_read(dev, lp->ext_phy_addr, MII_BMCR);
242 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
243 amd8111e_mdio_write(dev, lp->ext_phy_addr, MII_BMCR, bmcr);
244
245}
246
6aa20a22
JG		 247/*
248This function will unmap skb->data space and will free
1da177e4
LT		 249all transmit and receive skbuffs.
250*/
251static int amd8111e_free_skbs(struct net_device *dev)
252{
253 struct amd8111e_priv *lp = netdev_priv(dev);
254 struct sk_buff* rx_skbuff;
255 int i;
256
257 /* Freeing transmit skbs */
258 for(i = 0; i < NUM_TX_BUFFERS; i++){
259 if(lp->tx_skbuff[i]){
260 pci_unmap_single(lp->pci_dev,lp->tx_dma_addr[i], lp->tx_skbuff[i]->len,PCI_DMA_TODEVICE);
261 dev_kfree_skb (lp->tx_skbuff[i]);
262 lp->tx_skbuff[i] = NULL;
263 lp->tx_dma_addr[i] = 0;
264 }
265 }
266 /* Freeing previously allocated receive buffers */
267 for (i = 0; i < NUM_RX_BUFFERS; i++){
268 rx_skbuff = lp->rx_skbuff[i];
269 if(rx_skbuff != NULL){
270 pci_unmap_single(lp->pci_dev,lp->rx_dma_addr[i],
271 lp->rx_buff_len - 2,PCI_DMA_FROMDEVICE);
272 dev_kfree_skb(lp->rx_skbuff[i]);
273 lp->rx_skbuff[i] = NULL;
274 lp->rx_dma_addr[i] = 0;
275 }
276 }
6aa20a22 277
1da177e4
LT		 278 return 0;
279}
280
281/*
282This will set the receive buffer length corresponding to the mtu size of networkinterface.
283*/
284static inline void amd8111e_set_rx_buff_len(struct net_device* dev)
285{
286 struct amd8111e_priv* lp = netdev_priv(dev);
287 unsigned int mtu = dev->mtu;
6aa20a22 288
1da177e4
LT		 289 if (mtu > ETH_DATA_LEN){
290 /* MTU + ethernet header + FCS
291 + optional VLAN tag + skb reserve space 2 */
292
293 lp->rx_buff_len = mtu + ETH_HLEN + 10;
294 lp->options |= OPTION_JUMBO_ENABLE;
295 } else{
296 lp->rx_buff_len = PKT_BUFF_SZ;
297 lp->options &= ~OPTION_JUMBO_ENABLE;
298 }
299}
300
6aa20a22 301/*
1da177e4
LT		 302This function will free all the previously allocated buffers, determine new receive buffer length and will allocate new receive buffers. This function also allocates and initializes both the transmitter and receive hardware descriptors.
303 */
304static int amd8111e_init_ring(struct net_device *dev)
305{
306 struct amd8111e_priv *lp = netdev_priv(dev);
307 int i;
308
309 lp->rx_idx = lp->tx_idx = 0;
310 lp->tx_complete_idx = 0;
311 lp->tx_ring_idx = 0;
6aa20a22 312
1da177e4
LT		 313
314 if(lp->opened)
315 /* Free previously allocated transmit and receive skbs */
6aa20a22 316 amd8111e_free_skbs(dev);
1da177e4
LT		 317
318 else{
319 /* allocate the tx and rx descriptors */
6aa20a22 320 if((lp->tx_ring = pci_alloc_consistent(lp->pci_dev,
1da177e4
LT		 321 sizeof(struct amd8111e_tx_dr)*NUM_TX_RING_DR,
322 &lp->tx_ring_dma_addr)) == NULL)
6aa20a22 323
1da177e4 324 goto err_no_mem;
6aa20a22
JG		 325
326 if((lp->rx_ring = pci_alloc_consistent(lp->pci_dev,
1da177e4
LT		 327 sizeof(struct amd8111e_rx_dr)*NUM_RX_RING_DR,
328 &lp->rx_ring_dma_addr)) == NULL)
6aa20a22 329
1da177e4
LT		 330 goto err_free_tx_ring;
331
332 }
333 /* Set new receive buff size */
334 amd8111e_set_rx_buff_len(dev);
335
336 /* Allocating receive skbs */
337 for (i = 0; i < NUM_RX_BUFFERS; i++) {
338
339 if (!(lp->rx_skbuff[i] = dev_alloc_skb(lp->rx_buff_len))) {
340 /* Release previos allocated skbs */
341 for(--i; i >= 0 ;i--)
342 dev_kfree_skb(lp->rx_skbuff[i]);
343 goto err_free_rx_ring;
344 }
345 skb_reserve(lp->rx_skbuff[i],2);
346 }
347 /* Initilaizing receive descriptors */
348 for (i = 0; i < NUM_RX_BUFFERS; i++) {
6aa20a22 349 lp->rx_dma_addr[i] = pci_map_single(lp->pci_dev,
1da177e4
LT		 350 lp->rx_skbuff[i]->data,lp->rx_buff_len-2, PCI_DMA_FROMDEVICE);
351
352 lp->rx_ring[i].buff_phy_addr = cpu_to_le32(lp->rx_dma_addr[i]);
353 lp->rx_ring[i].buff_count = cpu_to_le16(lp->rx_buff_len-2);
354 wmb();
355 lp->rx_ring[i].rx_flags = cpu_to_le16(OWN_BIT);
356 }
357
358 /* Initializing transmit descriptors */
359 for (i = 0; i < NUM_TX_RING_DR; i++) {
360 lp->tx_ring[i].buff_phy_addr = 0;
361 lp->tx_ring[i].tx_flags = 0;
362 lp->tx_ring[i].buff_count = 0;
363 }
364
365 return 0;
366
367err_free_rx_ring:
6aa20a22
JG		 368
369 pci_free_consistent(lp->pci_dev,
1da177e4
LT		 370 sizeof(struct amd8111e_rx_dr)*NUM_RX_RING_DR,lp->rx_ring,
371 lp->rx_ring_dma_addr);
372
373err_free_tx_ring:
6aa20a22 374
1da177e4 375 pci_free_consistent(lp->pci_dev,
6aa20a22 376 sizeof(struct amd8111e_tx_dr)*NUM_TX_RING_DR,lp->tx_ring,
1da177e4
LT		 377 lp->tx_ring_dma_addr);
378
379err_no_mem:
380 return -ENOMEM;
381}
382/* This function will set the interrupt coalescing according to the input arguments */
383static int amd8111e_set_coalesce(struct net_device * dev, enum coal_mode cmod)
384{
385 unsigned int timeout;
386 unsigned int event_count;
387
388 struct amd8111e_priv *lp = netdev_priv(dev);
389 void __iomem *mmio = lp->mmio;
390 struct amd8111e_coalesce_conf * coal_conf = &lp->coal_conf;
391
392
393 switch(cmod)
394 {
395 case RX_INTR_COAL :
396 timeout = coal_conf->rx_timeout;
397 event_count = coal_conf->rx_event_count;
6aa20a22
JG		 398 if( timeout > MAX_TIMEOUT ||
399 event_count > MAX_EVENT_COUNT )
1da177e4
LT		 400 return -EINVAL;
401
6aa20a22 402 timeout = timeout * DELAY_TIMER_CONV;
1da177e4
LT		 403 writel(VAL0|STINTEN, mmio+INTEN0);
404 writel((u32)DLY_INT_A_R0|( event_count<< 16 )|timeout,
405 mmio+DLY_INT_A);
406 break;
407
408 case TX_INTR_COAL :
409 timeout = coal_conf->tx_timeout;
410 event_count = coal_conf->tx_event_count;
6aa20a22
JG		 411 if( timeout > MAX_TIMEOUT ||
412 event_count > MAX_EVENT_COUNT )
1da177e4
LT		 413 return -EINVAL;
414
6aa20a22
JG		 415
416 timeout = timeout * DELAY_TIMER_CONV;
1da177e4
LT		 417 writel(VAL0|STINTEN,mmio+INTEN0);
418 writel((u32)DLY_INT_B_T0|( event_count<< 16 )|timeout,
419 mmio+DLY_INT_B);
420 break;
421
422 case DISABLE_COAL:
423 writel(0,mmio+STVAL);
424 writel(STINTEN, mmio+INTEN0);
425 writel(0, mmio +DLY_INT_B);
426 writel(0, mmio+DLY_INT_A);
427 break;
6aa20a22 428 case ENABLE_COAL:
1da177e4
LT		 429 /* Start the timer */
430 writel((u32)SOFT_TIMER_FREQ, mmio+STVAL); /* 0.5 sec */
431 writel(VAL0|STINTEN, mmio+INTEN0);
432 break;
433 default:
434 break;
435
436 }
437 return 0;
438
439}
440
6aa20a22
JG		 441/*
442This function initializes the device registers and starts the device.
1da177e4
LT		 443*/
444static int amd8111e_restart(struct net_device *dev)
445{
446 struct amd8111e_priv *lp = netdev_priv(dev);
447 void __iomem *mmio = lp->mmio;
448 int i,reg_val;
449
450 /* stop the chip */
451 writel(RUN, mmio + CMD0);
452
453 if(amd8111e_init_ring(dev))
454 return -ENOMEM;
455
456 /* enable the port manager and set auto negotiation always */
457 writel((u32) VAL1|EN_PMGR, mmio + CMD3 );
6aa20a22
JG		 458 writel((u32)XPHYANE|XPHYRST , mmio + CTRL2);
459
1da177e4
LT		 460 amd8111e_set_ext_phy(dev);
461
462 /* set control registers */
463 reg_val = readl(mmio + CTRL1);
464 reg_val &= ~XMTSP_MASK;
465 writel( reg_val| XMTSP_128 | CACHE_ALIGN, mmio + CTRL1 );
466
467 /* enable interrupt */
6aa20a22 468 writel( APINT5EN | APINT4EN | APINT3EN | APINT2EN | APINT1EN |
1da177e4
LT		 469 APINT0EN | MIIPDTINTEN | MCCIINTEN | MCCINTEN | MREINTEN |
470 SPNDINTEN | MPINTEN | SINTEN | STINTEN, mmio + INTEN0);
471
472 writel(VAL3 | LCINTEN | VAL1 | TINTEN0 | VAL0 | RINTEN0, mmio + INTEN0);
473
474 /* initialize tx and rx ring base addresses */
475 writel((u32)lp->tx_ring_dma_addr,mmio + XMT_RING_BASE_ADDR0);
476 writel((u32)lp->rx_ring_dma_addr,mmio+ RCV_RING_BASE_ADDR0);
477
478 writew((u32)NUM_TX_RING_DR, mmio + XMT_RING_LEN0);
479 writew((u16)NUM_RX_RING_DR, mmio + RCV_RING_LEN0);
6aa20a22 480
1da177e4
LT		 481 /* set default IPG to 96 */
482 writew((u32)DEFAULT_IPG,mmio+IPG);
6aa20a22 483 writew((u32)(DEFAULT_IPG-IFS1_DELTA), mmio + IFS1);
1da177e4
LT		 484
485 if(lp->options & OPTION_JUMBO_ENABLE){
486 writel((u32)VAL2|JUMBO, mmio + CMD3);
487 /* Reset REX_UFLO */
488 writel( REX_UFLO, mmio + CMD2);
489 /* Should not set REX_UFLO for jumbo frames */
490 writel( VAL0 | APAD_XMT|REX_RTRY , mmio + CMD2);
491 }else{
492 writel( VAL0 | APAD_XMT | REX_RTRY|REX_UFLO, mmio + CMD2);
493 writel((u32)JUMBO, mmio + CMD3);
494 }
495
496#if AMD8111E_VLAN_TAG_USED
497 writel((u32) VAL2|VSIZE|VL_TAG_DEL, mmio + CMD3);
498#endif
499 writel( VAL0 | APAD_XMT | REX_RTRY, mmio + CMD2 );
6aa20a22 500
1da177e4
LT		 501 /* Setting the MAC address to the device */
502 for(i = 0; i < ETH_ADDR_LEN; i++)
6aa20a22 503 writeb( dev->dev_addr[i], mmio + PADR + i );
1da177e4
LT		 504
505 /* Enable interrupt coalesce */
506 if(lp->options & OPTION_INTR_COAL_ENABLE){
507 printk(KERN_INFO "%s: Interrupt Coalescing Enabled.\n",
508 dev->name);
509 amd8111e_set_coalesce(dev,ENABLE_COAL);
510 }
6aa20a22 511
1da177e4
LT		 512 /* set RUN bit to start the chip */
513 writel(VAL2 | RDMD0, mmio + CMD0);
514 writel(VAL0 | INTREN | RUN, mmio + CMD0);
6aa20a22 515
1da177e4
LT		 516 /* To avoid PCI posting bug */
517 readl(mmio+CMD0);
518 return 0;
519}
6aa20a22
JG		 520/*
521This function clears necessary the device registers.
522*/
1da177e4
LT		 523static void amd8111e_init_hw_default( struct amd8111e_priv* lp)
524{
525 unsigned int reg_val;
526 unsigned int logic_filter[2] ={0,};
527 void __iomem *mmio = lp->mmio;
528
529
530 /* stop the chip */
531 writel(RUN, mmio + CMD0);
532
533 /* AUTOPOLL0 Register *//*TBD default value is 8100 in FPS */
534 writew( 0x8100 | lp->ext_phy_addr, mmio + AUTOPOLL0);
535
536 /* Clear RCV_RING_BASE_ADDR */
537 writel(0, mmio + RCV_RING_BASE_ADDR0);
538
539 /* Clear XMT_RING_BASE_ADDR */
540 writel(0, mmio + XMT_RING_BASE_ADDR0);
541 writel(0, mmio + XMT_RING_BASE_ADDR1);
542 writel(0, mmio + XMT_RING_BASE_ADDR2);
543 writel(0, mmio + XMT_RING_BASE_ADDR3);
544
545 /* Clear CMD0 */
546 writel(CMD0_CLEAR,mmio + CMD0);
6aa20a22 547
1da177e4
LT		 548 /* Clear CMD2 */
549 writel(CMD2_CLEAR, mmio +CMD2);
550
551 /* Clear CMD7 */
552 writel(CMD7_CLEAR , mmio + CMD7);
553
554 /* Clear DLY_INT_A and DLY_INT_B */
555 writel(0x0, mmio + DLY_INT_A);
556 writel(0x0, mmio + DLY_INT_B);
557
558 /* Clear FLOW_CONTROL */
559 writel(0x0, mmio + FLOW_CONTROL);
560
561 /* Clear INT0 write 1 to clear register */
562 reg_val = readl(mmio + INT0);
563 writel(reg_val, mmio + INT0);
564
565 /* Clear STVAL */
566 writel(0x0, mmio + STVAL);
567
568 /* Clear INTEN0 */
569 writel( INTEN0_CLEAR, mmio + INTEN0);
570
571 /* Clear LADRF */
572 writel(0x0 , mmio + LADRF);
573
574 /* Set SRAM_SIZE & SRAM_BOUNDARY registers */
575 writel( 0x80010,mmio + SRAM_SIZE);
576
577 /* Clear RCV_RING0_LEN */
578 writel(0x0, mmio + RCV_RING_LEN0);
579
580 /* Clear XMT_RING0/1/2/3_LEN */
581 writel(0x0, mmio + XMT_RING_LEN0);
582 writel(0x0, mmio + XMT_RING_LEN1);
583 writel(0x0, mmio + XMT_RING_LEN2);
584 writel(0x0, mmio + XMT_RING_LEN3);
585
586 /* Clear XMT_RING_LIMIT */
587 writel(0x0, mmio + XMT_RING_LIMIT);
588
589 /* Clear MIB */
590 writew(MIB_CLEAR, mmio + MIB_ADDR);
591
592 /* Clear LARF */
593 amd8111e_writeq(*(u64*)logic_filter,mmio+LADRF);
594
595 /* SRAM_SIZE register */
596 reg_val = readl(mmio + SRAM_SIZE);
6aa20a22 597
1da177e4
LT		 598 if(lp->options & OPTION_JUMBO_ENABLE)
599 writel( VAL2|JUMBO, mmio + CMD3);
600#if AMD8111E_VLAN_TAG_USED
601 writel(VAL2|VSIZE|VL_TAG_DEL, mmio + CMD3 );
602#endif
603 /* Set default value to CTRL1 Register */
604 writel(CTRL1_DEFAULT, mmio + CTRL1);
605
606 /* To avoid PCI posting bug */
607 readl(mmio + CMD2);
608
609}
610
6aa20a22
JG		 611/*
612This function disables the interrupt and clears all the pending
1da177e4
LT		 613interrupts in INT0
614 */
615static void amd8111e_disable_interrupt(struct amd8111e_priv* lp)
6aa20a22 616{
1da177e4
LT		 617 u32 intr0;
618
619 /* Disable interrupt */
620 writel(INTREN, lp->mmio + CMD0);
6aa20a22 621
1da177e4
LT		 622 /* Clear INT0 */
623 intr0 = readl(lp->mmio + INT0);
624 writel(intr0, lp->mmio + INT0);
6aa20a22 625
1da177e4
LT		 626 /* To avoid PCI posting bug */
627 readl(lp->mmio + INT0);
628
629}
630
631/*
6aa20a22 632This function stops the chip.
1da177e4
LT		 633*/
634static void amd8111e_stop_chip(struct amd8111e_priv* lp)
635{
636 writel(RUN, lp->mmio + CMD0);
6aa20a22 637
1da177e4
LT		 638 /* To avoid PCI posting bug */
639 readl(lp->mmio + CMD0);
640}
641
6aa20a22 642/*
1da177e4
LT		 643This function frees the transmiter and receiver descriptor rings.
644*/
645static void amd8111e_free_ring(struct amd8111e_priv* lp)
6aa20a22 646{
1da177e4
LT		 647
648 /* Free transmit and receive skbs */
649 amd8111e_free_skbs(lp->amd8111e_net_dev);
650
651 /* Free transmit and receive descriptor rings */
652 if(lp->rx_ring){
6aa20a22 653 pci_free_consistent(lp->pci_dev,
1da177e4
LT		 654 sizeof(struct amd8111e_rx_dr)*NUM_RX_RING_DR,
655 lp->rx_ring, lp->rx_ring_dma_addr);
656 lp->rx_ring = NULL;
657 }
6aa20a22 658
1da177e4 659 if(lp->tx_ring){
6aa20a22 660 pci_free_consistent(lp->pci_dev,
1da177e4
LT		 661 sizeof(struct amd8111e_tx_dr)*NUM_TX_RING_DR,
662 lp->tx_ring, lp->tx_ring_dma_addr);
663
664 lp->tx_ring = NULL;
665 }
666
667}
6aa20a22
JG		 668#if AMD8111E_VLAN_TAG_USED
669/*
1da177e4 670This is the receive indication function for packets with vlan tag.
6aa20a22 671*/
1da177e4
LT		 672static int amd8111e_vlan_rx(struct amd8111e_priv *lp, struct sk_buff *skb, u16 vlan_tag)
673{
674#ifdef CONFIG_AMD8111E_NAPI
675 return vlan_hwaccel_receive_skb(skb, lp->vlgrp,vlan_tag);
676#else
677 return vlan_hwaccel_rx(skb, lp->vlgrp, vlan_tag);
678#endif /* CONFIG_AMD8111E_NAPI */
679}
680#endif
681
682/*
6aa20a22 683This function will free all the transmit skbs that are actually transmitted by the device. It will check the ownership of the skb before freeing the skb.
1da177e4
LT		 684*/
685static int amd8111e_tx(struct net_device *dev)
686{
687 struct amd8111e_priv* lp = netdev_priv(dev);
688 int tx_index = lp->tx_complete_idx & TX_RING_DR_MOD_MASK;
689 int status;
690 /* Complete all the transmit packet */
691 while (lp->tx_complete_idx != lp->tx_idx){
692 tx_index = lp->tx_complete_idx & TX_RING_DR_MOD_MASK;
693 status = le16_to_cpu(lp->tx_ring[tx_index].tx_flags);
694
695 if(status & OWN_BIT)
696 break; /* It still hasn't been Txed */
697
698 lp->tx_ring[tx_index].buff_phy_addr = 0;
699
700 /* We must free the original skb */
701 if (lp->tx_skbuff[tx_index]) {
702 pci_unmap_single(lp->pci_dev, lp->tx_dma_addr[tx_index],
703 lp->tx_skbuff[tx_index]->len,
704 PCI_DMA_TODEVICE);
705 dev_kfree_skb_irq (lp->tx_skbuff[tx_index]);
706 lp->tx_skbuff[tx_index] = NULL;
707 lp->tx_dma_addr[tx_index] = 0;
708 }
709 lp->tx_complete_idx++;
710 /*COAL update tx coalescing parameters */
711 lp->coal_conf.tx_packets++;
05d2fec9
AV		 712 lp->coal_conf.tx_bytes +=
713 le16_to_cpu(lp->tx_ring[tx_index].buff_count);
1da177e4
LT		 714
715 if (netif_queue_stopped(dev) &&
716 lp->tx_complete_idx > lp->tx_idx - NUM_TX_BUFFERS +2){
717 /* The ring is no longer full, clear tbusy. */
718 /* lp->tx_full = 0; */
719 netif_wake_queue (dev);
720 }
721 }
722 return 0;
723}
724
725#ifdef CONFIG_AMD8111E_NAPI
726/* This function handles the driver receive operation in polling mode */
bea3348e 727static int amd8111e_rx_poll(struct napi_struct *napi, int budget)
1da177e4 728{
bea3348e
SH		 729 struct amd8111e_priv *lp = container_of(napi, struct amd8111e_priv, napi);
730 struct net_device *dev = lp->amd8111e_net_dev;
1da177e4
LT		 731 int rx_index = lp->rx_idx & RX_RING_DR_MOD_MASK;
732 void __iomem *mmio = lp->mmio;
733 struct sk_buff *skb,*new_skb;
734 int min_pkt_len, status;
735 unsigned int intr0;
736 int num_rx_pkt = 0;
737 /*int max_rx_pkt = NUM_RX_BUFFERS;*/
738 short pkt_len;
6aa20a22 739#if AMD8111E_VLAN_TAG_USED
1da177e4
LT		 740 short vtag;
741#endif
bea3348e 742 int rx_pkt_limit = budget;
dfa1b73f 743 unsigned long flags;
6aa20a22
JG		 744
745 do{
1da177e4
LT		 746 /* process receive packets until we use the quota*/
747 /* If we own the next entry, it's a new packet. Send it up. */
748 while(1) {
749 status = le16_to_cpu(lp->rx_ring[rx_index].rx_flags);
750 if (status & OWN_BIT)
751 break;
752
6aa20a22 753 /*
1da177e4
LT		 754 * There is a tricky error noted by John Murphy,
755 * <murf@perftech.com> to Russ Nelson: Even with
6aa20a22
JG		 756 * full-sized * buffers it's possible for a
757 * jabber packet to use two buffers, with only
1da177e4
LT		 758 * the last correctly noting the error.
759 */
760
761 if(status & ERR_BIT) {
762 /* reseting flags */
763 lp->rx_ring[rx_index].rx_flags &= RESET_RX_FLAGS;
764 goto err_next_pkt;
765 }
766 /* check for STP and ENP */
767 if(!((status & STP_BIT) && (status & ENP_BIT))){
768 /* reseting flags */
769 lp->rx_ring[rx_index].rx_flags &= RESET_RX_FLAGS;
770 goto err_next_pkt;
771 }
772 pkt_len = le16_to_cpu(lp->rx_ring[rx_index].msg_count) - 4;
773
6aa20a22 774#if AMD8111E_VLAN_TAG_USED
1da177e4 775 vtag = status & TT_MASK;
6aa20a22 776 /*MAC will strip vlan tag*/
1da177e4
LT		 777 if(lp->vlgrp != NULL && vtag !=0)
778 min_pkt_len =MIN_PKT_LEN - 4;
779 else
780#endif
781 min_pkt_len =MIN_PKT_LEN;
782
783 if (pkt_len < min_pkt_len) {
784 lp->rx_ring[rx_index].rx_flags &= RESET_RX_FLAGS;
785 lp->drv_rx_errors++;
786 goto err_next_pkt;
787 }
788 if(--rx_pkt_limit < 0)
789 goto rx_not_empty;
790 if(!(new_skb = dev_alloc_skb(lp->rx_buff_len))){
6aa20a22 791 /* if allocation fail,
1da177e4
LT		 792 ignore that pkt and go to next one */
793 lp->rx_ring[rx_index].rx_flags &= RESET_RX_FLAGS;
794 lp->drv_rx_errors++;
795 goto err_next_pkt;
796 }
6aa20a22 797
1da177e4
LT		 798 skb_reserve(new_skb, 2);
799 skb = lp->rx_skbuff[rx_index];
800 pci_unmap_single(lp->pci_dev,lp->rx_dma_addr[rx_index],
801 lp->rx_buff_len-2, PCI_DMA_FROMDEVICE);
802 skb_put(skb, pkt_len);
1da177e4 803 lp->rx_skbuff[rx_index] = new_skb;
1da177e4
LT		 804 lp->rx_dma_addr[rx_index] = pci_map_single(lp->pci_dev,
805 new_skb->data,
806 lp->rx_buff_len-2,
807 PCI_DMA_FROMDEVICE);
6aa20a22 808
1da177e4
LT		 809 skb->protocol = eth_type_trans(skb, dev);
810
6aa20a22 811#if AMD8111E_VLAN_TAG_USED
1da177e4
LT		 812 if(lp->vlgrp != NULL && (vtag == TT_VLAN_TAGGED)){
813 amd8111e_vlan_rx(lp, skb,
814 le16_to_cpu(lp->rx_ring[rx_index].tag_ctrl_info));
815 } else
816#endif
817 netif_receive_skb(skb);
818 /*COAL update rx coalescing parameters*/
819 lp->coal_conf.rx_packets++;
6aa20a22 820 lp->coal_conf.rx_bytes += pkt_len;
1da177e4
LT		 821 num_rx_pkt++;
822 dev->last_rx = jiffies;
6aa20a22
JG		 823
824 err_next_pkt:
1da177e4
LT		 825 lp->rx_ring[rx_index].buff_phy_addr
826 = cpu_to_le32(lp->rx_dma_addr[rx_index]);
6aa20a22 827 lp->rx_ring[rx_index].buff_count =
1da177e4
LT		 828 cpu_to_le16(lp->rx_buff_len-2);
829 wmb();
830 lp->rx_ring[rx_index].rx_flags |= cpu_to_le16(OWN_BIT);
831 rx_index = (++lp->rx_idx) & RX_RING_DR_MOD_MASK;
832 }
6aa20a22 833 /* Check the interrupt status register for more packets in the
1da177e4
LT		 834 mean time. Process them since we have not used up our quota.*/
835
836 intr0 = readl(mmio + INT0);
837 /*Ack receive packets */
838 writel(intr0 & RINT0,mmio + INT0);
839
840 } while(intr0 & RINT0);
841
842 /* Receive descriptor is empty now */
dfa1b73f 843 spin_lock_irqsave(&lp->lock, flags);
bea3348e 844 __netif_rx_complete(dev, napi);
1da177e4
LT		 845 writel(VAL0|RINTEN0, mmio + INTEN0);
846 writel(VAL2 | RDMD0, mmio + CMD0);
dfa1b73f 847 spin_unlock_irqrestore(&lp->lock, flags);
dfa1b73f 848
1da177e4 849rx_not_empty:
bea3348e 850 return num_rx_pkt;
1da177e4
LT		 851}
852
853#else
6aa20a22 854/*
1da177e4
LT		 855This function will check the ownership of receive buffers and descriptors. It will indicate to kernel up to half the number of maximum receive buffers in the descriptor ring, in a single receive interrupt. It will also replenish the descriptors with new skbs.
856*/
857static int amd8111e_rx(struct net_device *dev)
858{
859 struct amd8111e_priv *lp = netdev_priv(dev);
860 struct sk_buff *skb,*new_skb;
861 int rx_index = lp->rx_idx & RX_RING_DR_MOD_MASK;
862 int min_pkt_len, status;
863 int num_rx_pkt = 0;
864 int max_rx_pkt = NUM_RX_BUFFERS;
865 short pkt_len;
6aa20a22 866#if AMD8111E_VLAN_TAG_USED
1da177e4
LT		 867 short vtag;
868#endif
6aa20a22 869
1da177e4
LT		 870 /* If we own the next entry, it's a new packet. Send it up. */
871 while(++num_rx_pkt <= max_rx_pkt){
872 status = le16_to_cpu(lp->rx_ring[rx_index].rx_flags);
873 if(status & OWN_BIT)
874 return 0;
6aa20a22
JG		 875
876 /* check if err summary bit is set */
1da177e4 877 if(status & ERR_BIT){
6aa20a22 878 /*
1da177e4
LT		 879 * There is a tricky error noted by John Murphy,
880 * <murf@perftech.com> to Russ Nelson: Even with full-sized
881 * buffers it's possible for a jabber packet to use two
882 * buffers, with only the last correctly noting the error. */
883 /* reseting flags */
884 lp->rx_ring[rx_index].rx_flags &= RESET_RX_FLAGS;
885 goto err_next_pkt;
886 }
887 /* check for STP and ENP */
888 if(!((status & STP_BIT) && (status & ENP_BIT))){
889 /* reseting flags */
890 lp->rx_ring[rx_index].rx_flags &= RESET_RX_FLAGS;
891 goto err_next_pkt;
892 }
893 pkt_len = le16_to_cpu(lp->rx_ring[rx_index].msg_count) - 4;
894
6aa20a22 895#if AMD8111E_VLAN_TAG_USED
1da177e4 896 vtag = status & TT_MASK;
6aa20a22 897 /*MAC will strip vlan tag*/
1da177e4
LT		 898 if(lp->vlgrp != NULL && vtag !=0)
899 min_pkt_len =MIN_PKT_LEN - 4;
900 else
901#endif
902 min_pkt_len =MIN_PKT_LEN;
903
904 if (pkt_len < min_pkt_len) {
905 lp->rx_ring[rx_index].rx_flags &= RESET_RX_FLAGS;
906 lp->drv_rx_errors++;
907 goto err_next_pkt;
908 }
909 if(!(new_skb = dev_alloc_skb(lp->rx_buff_len))){
6aa20a22 910 /* if allocation fail,
1da177e4
LT		 911 ignore that pkt and go to next one */
912 lp->rx_ring[rx_index].rx_flags &= RESET_RX_FLAGS;
913 lp->drv_rx_errors++;
914 goto err_next_pkt;
915 }
6aa20a22 916
1da177e4
LT		 917 skb_reserve(new_skb, 2);
918 skb = lp->rx_skbuff[rx_index];
919 pci_unmap_single(lp->pci_dev,lp->rx_dma_addr[rx_index],
920 lp->rx_buff_len-2, PCI_DMA_FROMDEVICE);
921 skb_put(skb, pkt_len);
1da177e4 922 lp->rx_skbuff[rx_index] = new_skb;
1da177e4
LT		 923 lp->rx_dma_addr[rx_index] = pci_map_single(lp->pci_dev,
924 new_skb->data, lp->rx_buff_len-2,PCI_DMA_FROMDEVICE);
6aa20a22 925
1da177e4
LT		 926 skb->protocol = eth_type_trans(skb, dev);
927
6aa20a22 928#if AMD8111E_VLAN_TAG_USED
1da177e4
LT		 929 if(lp->vlgrp != NULL && (vtag == TT_VLAN_TAGGED)){
930 amd8111e_vlan_rx(lp, skb,
931 le16_to_cpu(lp->rx_ring[rx_index].tag_ctrl_info));
932 } else
933#endif
6aa20a22 934
1da177e4
LT		 935 netif_rx (skb);
936 /*COAL update rx coalescing parameters*/
937 lp->coal_conf.rx_packets++;
6aa20a22 938 lp->coal_conf.rx_bytes += pkt_len;
1da177e4
LT		 939
940 dev->last_rx = jiffies;
6aa20a22 941
1da177e4
LT		 942err_next_pkt:
943 lp->rx_ring[rx_index].buff_phy_addr
944 = cpu_to_le32(lp->rx_dma_addr[rx_index]);
6aa20a22 945 lp->rx_ring[rx_index].buff_count =
1da177e4
LT		 946 cpu_to_le16(lp->rx_buff_len-2);
947 wmb();
948 lp->rx_ring[rx_index].rx_flags |= cpu_to_le16(OWN_BIT);
949 rx_index = (++lp->rx_idx) & RX_RING_DR_MOD_MASK;
950 }
951
952 return 0;
953}
954#endif /* CONFIG_AMD8111E_NAPI */
6aa20a22 955/*
1da177e4
LT		 956This function will indicate the link status to the kernel.
957*/
958static int amd8111e_link_change(struct net_device* dev)
6aa20a22 959{
1da177e4
LT		 960 struct amd8111e_priv *lp = netdev_priv(dev);
961 int status0,speed;
962
963 /* read the link change */
964 status0 = readl(lp->mmio + STAT0);
6aa20a22 965
1da177e4
LT		 966 if(status0 & LINK_STATS){
967 if(status0 & AUTONEG_COMPLETE)
968 lp->link_config.autoneg = AUTONEG_ENABLE;
6aa20a22 969 else
1da177e4
LT		 970 lp->link_config.autoneg = AUTONEG_DISABLE;
971
972 if(status0 & FULL_DPLX)
973 lp->link_config.duplex = DUPLEX_FULL;
6aa20a22 974 else
1da177e4
LT		 975 lp->link_config.duplex = DUPLEX_HALF;
976 speed = (status0 & SPEED_MASK) >> 7;
977 if(speed == PHY_SPEED_10)
978 lp->link_config.speed = SPEED_10;
979 else if(speed == PHY_SPEED_100)
980 lp->link_config.speed = SPEED_100;
981
982 printk(KERN_INFO "%s: Link is Up. Speed is %s Mbps %s Duplex\n", dev->name,
6aa20a22
JG		 983 (lp->link_config.speed == SPEED_100) ? "100": "10",
984 (lp->link_config.duplex == DUPLEX_FULL)? "Full": "Half");
1da177e4
LT		 985 netif_carrier_on(dev);
986 }
6aa20a22 987 else{
1da177e4
LT		 988 lp->link_config.speed = SPEED_INVALID;
989 lp->link_config.duplex = DUPLEX_INVALID;
990 lp->link_config.autoneg = AUTONEG_INVALID;
991 printk(KERN_INFO "%s: Link is Down.\n",dev->name);
992 netif_carrier_off(dev);
993 }
6aa20a22 994
1da177e4
LT		 995 return 0;
996}
997/*
6aa20a22 998This function reads the mib counters.
1da177e4
LT		 999*/
1000static int amd8111e_read_mib(void __iomem *mmio, u8 MIB_COUNTER)
1001{
1002 unsigned int status;
1003 unsigned int data;
1004 unsigned int repeat = REPEAT_CNT;
1005
1006 writew( MIB_RD_CMD | MIB_COUNTER, mmio + MIB_ADDR);
1007 do {
1008 status = readw(mmio + MIB_ADDR);
1009 udelay(2); /* controller takes MAX 2 us to get mib data */
1010 }
1011 while (--repeat && (status & MIB_CMD_ACTIVE));
1012
1013 data = readl(mmio + MIB_DATA);
1014 return data;
1015}
1016
1017/*
1018This function reads the mib registers and returns the hardware statistics. It updates previous internal driver statistics with new values.
6aa20a22 1019*/
1da177e4
LT		 1020static struct net_device_stats *amd8111e_get_stats(struct net_device * dev)
1021{
1022 struct amd8111e_priv *lp = netdev_priv(dev);
1023 void __iomem *mmio = lp->mmio;
1024 unsigned long flags;
1025 /* struct net_device_stats *prev_stats = &lp->prev_stats; */
1026 struct net_device_stats* new_stats = &lp->stats;
6aa20a22 1027
1da177e4 1028 if(!lp->opened)
6aa20a22 1029 return &lp->stats;
1da177e4
LT		 1030 spin_lock_irqsave (&lp->lock, flags);
1031
1032 /* stats.rx_packets */
1033 new_stats->rx_packets = amd8111e_read_mib(mmio, rcv_broadcast_pkts)+
1034 amd8111e_read_mib(mmio, rcv_multicast_pkts)+
1035 amd8111e_read_mib(mmio, rcv_unicast_pkts);
1036
1037 /* stats.tx_packets */
1038 new_stats->tx_packets = amd8111e_read_mib(mmio, xmt_packets);
1039
1040 /*stats.rx_bytes */
1041 new_stats->rx_bytes = amd8111e_read_mib(mmio, rcv_octets);
1042
1043 /* stats.tx_bytes */
1044 new_stats->tx_bytes = amd8111e_read_mib(mmio, xmt_octets);
1045
1046 /* stats.rx_errors */
1047 /* hw errors + errors driver reported */
1048 new_stats->rx_errors = amd8111e_read_mib(mmio, rcv_undersize_pkts)+
1049 amd8111e_read_mib(mmio, rcv_fragments)+
1050 amd8111e_read_mib(mmio, rcv_jabbers)+
1051 amd8111e_read_mib(mmio, rcv_alignment_errors)+
1052 amd8111e_read_mib(mmio, rcv_fcs_errors)+
1053 amd8111e_read_mib(mmio, rcv_miss_pkts)+
1054 lp->drv_rx_errors;
1055
1056 /* stats.tx_errors */
1057 new_stats->tx_errors = amd8111e_read_mib(mmio, xmt_underrun_pkts);
1058
1059 /* stats.rx_dropped*/
1060 new_stats->rx_dropped = amd8111e_read_mib(mmio, rcv_miss_pkts);
1061
1062 /* stats.tx_dropped*/
1063 new_stats->tx_dropped = amd8111e_read_mib(mmio, xmt_underrun_pkts);
1064
1065 /* stats.multicast*/
1066 new_stats->multicast = amd8111e_read_mib(mmio, rcv_multicast_pkts);
1067
1068 /* stats.collisions*/
1069 new_stats->collisions = amd8111e_read_mib(mmio, xmt_collisions);
1070
1071 /* stats.rx_length_errors*/
6aa20a22 1072 new_stats->rx_length_errors =
1da177e4
LT		 1073 amd8111e_read_mib(mmio, rcv_undersize_pkts)+
1074 amd8111e_read_mib(mmio, rcv_oversize_pkts);
1075
1076 /* stats.rx_over_errors*/
1077 new_stats->rx_over_errors = amd8111e_read_mib(mmio, rcv_miss_pkts);
1078
1079 /* stats.rx_crc_errors*/
1080 new_stats->rx_crc_errors = amd8111e_read_mib(mmio, rcv_fcs_errors);
1081
1082 /* stats.rx_frame_errors*/
1083 new_stats->rx_frame_errors =
1084 amd8111e_read_mib(mmio, rcv_alignment_errors);
1085
1086 /* stats.rx_fifo_errors */
1087 new_stats->rx_fifo_errors = amd8111e_read_mib(mmio, rcv_miss_pkts);
1088
1089 /* stats.rx_missed_errors */
1090 new_stats->rx_missed_errors = amd8111e_read_mib(mmio, rcv_miss_pkts);
1091
1092 /* stats.tx_aborted_errors*/
6aa20a22 1093 new_stats->tx_aborted_errors =
1da177e4
LT		 1094 amd8111e_read_mib(mmio, xmt_excessive_collision);
1095
1096 /* stats.tx_carrier_errors*/
6aa20a22 1097 new_stats->tx_carrier_errors =
1da177e4
LT		 1098 amd8111e_read_mib(mmio, xmt_loss_carrier);
1099
1100 /* stats.tx_fifo_errors*/
1101 new_stats->tx_fifo_errors = amd8111e_read_mib(mmio, xmt_underrun_pkts);
1102
1103 /* stats.tx_window_errors*/
1104 new_stats->tx_window_errors =
1105 amd8111e_read_mib(mmio, xmt_late_collision);
1106
1107 /* Reset the mibs for collecting new statistics */
1108 /* writew(MIB_CLEAR, mmio + MIB_ADDR);*/
6aa20a22 1109
1da177e4
LT		 1110 spin_unlock_irqrestore (&lp->lock, flags);
1111
1112 return new_stats;
1113}
3a4fa0a2 1114/* This function recalculate the interrupt coalescing mode on every interrupt
1da177e4
LT		 1115according to the datarate and the packet rate.
1116*/
1117static int amd8111e_calc_coalesce(struct net_device *dev)
1118{
1119 struct amd8111e_priv *lp = netdev_priv(dev);
1120 struct amd8111e_coalesce_conf * coal_conf = &lp->coal_conf;
1121 int tx_pkt_rate;
1122 int rx_pkt_rate;
1123 int tx_data_rate;
1124 int rx_data_rate;
1125 int rx_pkt_size;
1126 int tx_pkt_size;
1127
1128 tx_pkt_rate = coal_conf->tx_packets - coal_conf->tx_prev_packets;
1129 coal_conf->tx_prev_packets = coal_conf->tx_packets;
6aa20a22 1130
1da177e4
LT		 1131 tx_data_rate = coal_conf->tx_bytes - coal_conf->tx_prev_bytes;
1132 coal_conf->tx_prev_bytes = coal_conf->tx_bytes;
6aa20a22 1133
1da177e4
LT		 1134 rx_pkt_rate = coal_conf->rx_packets - coal_conf->rx_prev_packets;
1135 coal_conf->rx_prev_packets = coal_conf->rx_packets;
6aa20a22 1136
1da177e4
LT		 1137 rx_data_rate = coal_conf->rx_bytes - coal_conf->rx_prev_bytes;
1138 coal_conf->rx_prev_bytes = coal_conf->rx_bytes;
6aa20a22 1139
1da177e4
LT		 1140 if(rx_pkt_rate < 800){
1141 if(coal_conf->rx_coal_type != NO_COALESCE){
6aa20a22 1142
1da177e4
LT		 1143 coal_conf->rx_timeout = 0x0;
1144 coal_conf->rx_event_count = 0;
1145 amd8111e_set_coalesce(dev,RX_INTR_COAL);
1146 coal_conf->rx_coal_type = NO_COALESCE;
1147 }
1148 }
1149 else{
6aa20a22 1150
1da177e4
LT		 1151 rx_pkt_size = rx_data_rate/rx_pkt_rate;
1152 if (rx_pkt_size < 128){
1153 if(coal_conf->rx_coal_type != NO_COALESCE){
6aa20a22 1154
1da177e4
LT		 1155 coal_conf->rx_timeout = 0;
1156 coal_conf->rx_event_count = 0;
1157 amd8111e_set_coalesce(dev,RX_INTR_COAL);
1158 coal_conf->rx_coal_type = NO_COALESCE;
1159 }
1160
1161 }
1162 else if ( (rx_pkt_size >= 128) && (rx_pkt_size < 512) ){
6aa20a22 1163
1da177e4
LT		 1164 if(coal_conf->rx_coal_type != LOW_COALESCE){
1165 coal_conf->rx_timeout = 1;
1166 coal_conf->rx_event_count = 4;
1167 amd8111e_set_coalesce(dev,RX_INTR_COAL);
1168 coal_conf->rx_coal_type = LOW_COALESCE;
1169 }
1170 }
1171 else if ((rx_pkt_size >= 512) && (rx_pkt_size < 1024)){
6aa20a22 1172
1da177e4
LT		 1173 if(coal_conf->rx_coal_type != MEDIUM_COALESCE){
1174 coal_conf->rx_timeout = 1;
1175 coal_conf->rx_event_count = 4;
1176 amd8111e_set_coalesce(dev,RX_INTR_COAL);
1177 coal_conf->rx_coal_type = MEDIUM_COALESCE;
6aa20a22
JG		 1178 }
1179
1da177e4
LT		 1180 }
1181 else if(rx_pkt_size >= 1024){
1182 if(coal_conf->rx_coal_type != HIGH_COALESCE){
1183 coal_conf->rx_timeout = 2;
1184 coal_conf->rx_event_count = 3;
1185 amd8111e_set_coalesce(dev,RX_INTR_COAL);
1186 coal_conf->rx_coal_type = HIGH_COALESCE;
6aa20a22 1187 }
1da177e4
LT		 1188 }
1189 }
1190 /* NOW FOR TX INTR COALESC */
1191 if(tx_pkt_rate < 800){
1192 if(coal_conf->tx_coal_type != NO_COALESCE){
6aa20a22 1193
1da177e4
LT		 1194 coal_conf->tx_timeout = 0x0;
1195 coal_conf->tx_event_count = 0;
1196 amd8111e_set_coalesce(dev,TX_INTR_COAL);
1197 coal_conf->tx_coal_type = NO_COALESCE;
1198 }
1199 }
1200 else{
6aa20a22 1201
1da177e4
LT		 1202 tx_pkt_size = tx_data_rate/tx_pkt_rate;
1203 if (tx_pkt_size < 128){
6aa20a22 1204
1da177e4 1205 if(coal_conf->tx_coal_type != NO_COALESCE){
6aa20a22 1206
1da177e4
LT		 1207 coal_conf->tx_timeout = 0;
1208 coal_conf->tx_event_count = 0;
1209 amd8111e_set_coalesce(dev,TX_INTR_COAL);
1210 coal_conf->tx_coal_type = NO_COALESCE;
1211 }
1212
1213 }
1214 else if ( (tx_pkt_size >= 128) && (tx_pkt_size < 512) ){
6aa20a22 1215
1da177e4
LT		 1216 if(coal_conf->tx_coal_type != LOW_COALESCE){
1217 coal_conf->tx_timeout = 1;
1218 coal_conf->tx_event_count = 2;
1219 amd8111e_set_coalesce(dev,TX_INTR_COAL);
1220 coal_conf->tx_coal_type = LOW_COALESCE;
1221
1222 }
1223 }
1224 else if ((tx_pkt_size >= 512) && (tx_pkt_size < 1024)){
6aa20a22 1225
1da177e4
LT		 1226 if(coal_conf->tx_coal_type != MEDIUM_COALESCE){
1227 coal_conf->tx_timeout = 2;
1228 coal_conf->tx_event_count = 5;
1229 amd8111e_set_coalesce(dev,TX_INTR_COAL);
1230 coal_conf->tx_coal_type = MEDIUM_COALESCE;
6aa20a22
JG		 1231 }
1232
1da177e4
LT		 1233 }
1234 else if(tx_pkt_size >= 1024){
1235 if (tx_pkt_size >= 1024){
1236 if(coal_conf->tx_coal_type != HIGH_COALESCE){
1237 coal_conf->tx_timeout = 4;
1238 coal_conf->tx_event_count = 8;
1239 amd8111e_set_coalesce(dev,TX_INTR_COAL);
1240 coal_conf->tx_coal_type = HIGH_COALESCE;
6aa20a22 1241 }
1da177e4
LT		 1242 }
1243 }
1244 }
1245 return 0;
1246
1247}
1248/*
1249This is device interrupt function. It handles transmit, receive,link change and hardware timer interrupts.
1250*/
7d12e780 1251static irqreturn_t amd8111e_interrupt(int irq, void *dev_id)
1da177e4
LT		 1252{
1253
1254 struct net_device * dev = (struct net_device *) dev_id;
1255 struct amd8111e_priv *lp = netdev_priv(dev);
1256 void __iomem *mmio = lp->mmio;
dfa1b73f 1257 unsigned int intr0, intren0;
1da177e4
LT		 1258 unsigned int handled = 1;
1259
dfa1b73f 1260 if(unlikely(dev == NULL))
1da177e4
LT		 1261 return IRQ_NONE;
1262
dfa1b73f
LT		 1263 spin_lock(&lp->lock);
1264
1da177e4
LT		 1265 /* disabling interrupt */
1266 writel(INTREN, mmio + CMD0);
1267
1268 /* Read interrupt status */
1269 intr0 = readl(mmio + INT0);
dfa1b73f 1270 intren0 = readl(mmio + INTEN0);
1da177e4
LT		 1271
1272 /* Process all the INT event until INTR bit is clear. */
1273
1274 if (!(intr0 & INTR)){
1275 handled = 0;
1276 goto err_no_interrupt;
1277 }
6aa20a22 1278
1da177e4
LT		 1279 /* Current driver processes 4 interrupts : RINT,TINT,LCINT,STINT */
1280 writel(intr0, mmio + INT0);
1281
1282 /* Check if Receive Interrupt has occurred. */
44456d37 1283#ifdef CONFIG_AMD8111E_NAPI
1da177e4 1284 if(intr0 & RINT0){
bea3348e 1285 if(netif_rx_schedule_prep(dev, &lp->napi)){
1da177e4
LT		 1286 /* Disable receive interupts */
1287 writel(RINTEN0, mmio + INTEN0);
1288 /* Schedule a polling routine */
bea3348e 1289 __netif_rx_schedule(dev, &lp->napi);
1da177e4 1290 }
dfa1b73f 1291 else if (intren0 & RINTEN0) {
1da177e4
LT		 1292 printk("************Driver bug! \
1293 interrupt while in poll\n");
dfa1b73f
LT		 1294 /* Fix by disable receive interrupts */
1295 writel(RINTEN0, mmio + INTEN0);
1da177e4
LT		 1296 }
1297 }
1298#else
1299 if(intr0 & RINT0){
1300 amd8111e_rx(dev);
1301 writel(VAL2 | RDMD0, mmio + CMD0);
1302 }
1303#endif /* CONFIG_AMD8111E_NAPI */
1304 /* Check if Transmit Interrupt has occurred. */
1305 if(intr0 & TINT0)
1306 amd8111e_tx(dev);
6aa20a22 1307
1da177e4
LT		 1308 /* Check if Link Change Interrupt has occurred. */
1309 if (intr0 & LCINT)
1310 amd8111e_link_change(dev);
1311
1312 /* Check if Hardware Timer Interrupt has occurred. */
1313 if (intr0 & STINT)
1314 amd8111e_calc_coalesce(dev);
1315
1316err_no_interrupt:
1317 writel( VAL0 | INTREN,mmio + CMD0);
6aa20a22 1318
dfa1b73f 1319 spin_unlock(&lp->lock);
6aa20a22 1320
1da177e4
LT		 1321 return IRQ_RETVAL(handled);
1322}
1323
1324#ifdef CONFIG_NET_POLL_CONTROLLER
1325static void amd8111e_poll(struct net_device *dev)
6aa20a22 1326{
1da177e4 1327 unsigned long flags;
b7e36bfa 1328 local_irq_save(flags);
7d12e780 1329 amd8111e_interrupt(0, dev);
6aa20a22
JG		 1330 local_irq_restore(flags);
1331}
1da177e4
LT		 1332#endif
1333
1334
1335/*
1336This function closes the network interface and updates the statistics so that most recent statistics will be available after the interface is down.
1337*/
1338static int amd8111e_close(struct net_device * dev)
1339{
1340 struct amd8111e_priv *lp = netdev_priv(dev);
1341 netif_stop_queue(dev);
6aa20a22 1342
3defd0ee 1343#ifdef CONFIG_AMD8111E_NAPI
bea3348e 1344 napi_disable(&lp->napi);
3defd0ee 1345#endif
bea3348e 1346
1da177e4 1347 spin_lock_irq(&lp->lock);
6aa20a22 1348
1da177e4
LT		 1349 amd8111e_disable_interrupt(lp);
1350 amd8111e_stop_chip(lp);
1351 amd8111e_free_ring(lp);
6aa20a22 1352
1da177e4
LT		 1353 netif_carrier_off(lp->amd8111e_net_dev);
1354
1355 /* Delete ipg timer */
6aa20a22 1356 if(lp->options & OPTION_DYN_IPG_ENABLE)
1da177e4
LT		 1357 del_timer_sync(&lp->ipg_data.ipg_timer);
1358
1359 spin_unlock_irq(&lp->lock);
1360 free_irq(dev->irq, dev);
6aa20a22 1361
1da177e4
LT		 1362 /* Update the statistics before closing */
1363 amd8111e_get_stats(dev);
1364 lp->opened = 0;
1365 return 0;
1366}
6aa20a22 1367/* This function opens new interface.It requests irq for the device, initializes the device,buffers and descriptors, and starts the device.
1da177e4
LT		 1368*/
1369static int amd8111e_open(struct net_device * dev )
1370{
1371 struct amd8111e_priv *lp = netdev_priv(dev);
1372
1fb9df5d 1373 if(dev->irq ==0 || request_irq(dev->irq, amd8111e_interrupt, IRQF_SHARED,
6aa20a22 1374 dev->name, dev))
1da177e4
LT		 1375 return -EAGAIN;
1376
3defd0ee 1377#ifdef CONFIG_AMD8111E_NAPI
bea3348e 1378 napi_enable(&lp->napi);
3defd0ee 1379#endif
bea3348e 1380
1da177e4
LT		 1381 spin_lock_irq(&lp->lock);
1382
1383 amd8111e_init_hw_default(lp);
1384
1385 if(amd8111e_restart(dev)){
1386 spin_unlock_irq(&lp->lock);
3defd0ee 1387#ifdef CONFIG_AMD8111E_NAPI
bea3348e 1388 napi_disable(&lp->napi);
3defd0ee 1389#endif
1da177e4
LT		 1390 if (dev->irq)
1391 free_irq(dev->irq, dev);
1392 return -ENOMEM;
1393 }
1394 /* Start ipg timer */
6aa20a22 1395 if(lp->options & OPTION_DYN_IPG_ENABLE){
1da177e4
LT		 1396 add_timer(&lp->ipg_data.ipg_timer);
1397 printk(KERN_INFO "%s: Dynamic IPG Enabled.\n",dev->name);
1398 }
1399
1400 lp->opened = 1;
1401
1402 spin_unlock_irq(&lp->lock);
1403
1404 netif_start_queue(dev);
1405
6aa20a22 1406 return 0;
1da177e4 1407}
6aa20a22 1408/*
1da177e4
LT		 1409This function checks if there is any transmit descriptors available to queue more packet.
1410*/
1411static int amd8111e_tx_queue_avail(struct amd8111e_priv* lp )
6aa20a22 1412{
1da177e4 1413 int tx_index = lp->tx_idx & TX_BUFF_MOD_MASK;
ee41a82f 1414 if (lp->tx_skbuff[tx_index])
1da177e4
LT		 1415 return -1;
1416 else
1417 return 0;
6aa20a22 1418
1da177e4 1419}
6aa20a22 1420/*
1da177e4
LT		 1421This function will queue the transmit packets to the descriptors and will trigger the send operation. It also initializes the transmit descriptors with buffer physical address, byte count, ownership to hardware etc.
1422*/
1423
1424static int amd8111e_start_xmit(struct sk_buff *skb, struct net_device * dev)
1425{
1426 struct amd8111e_priv *lp = netdev_priv(dev);
1427 int tx_index;
1428 unsigned long flags;
1429
1430 spin_lock_irqsave(&lp->lock, flags);
1431
1432 tx_index = lp->tx_idx & TX_RING_DR_MOD_MASK;
1433
1434 lp->tx_ring[tx_index].buff_count = cpu_to_le16(skb->len);
1435
1436 lp->tx_skbuff[tx_index] = skb;
1437 lp->tx_ring[tx_index].tx_flags = 0;
1438
1439#if AMD8111E_VLAN_TAG_USED
1440 if((lp->vlgrp != NULL) && vlan_tx_tag_present(skb)){
6aa20a22
JG		 1441 lp->tx_ring[tx_index].tag_ctrl_cmd |=
1442 cpu_to_le16(TCC_VLAN_INSERT);
1443 lp->tx_ring[tx_index].tag_ctrl_info =
1da177e4
LT		 1444 cpu_to_le16(vlan_tx_tag_get(skb));
1445
1446 }
1447#endif
1448 lp->tx_dma_addr[tx_index] =
1449 pci_map_single(lp->pci_dev, skb->data, skb->len, PCI_DMA_TODEVICE);
1450 lp->tx_ring[tx_index].buff_phy_addr =
ee41a82f 1451 cpu_to_le32(lp->tx_dma_addr[tx_index]);
1da177e4
LT		 1452
1453 /* Set FCS and LTINT bits */
1454 wmb();
1455 lp->tx_ring[tx_index].tx_flags |=
1456 cpu_to_le16(OWN_BIT | STP_BIT | ENP_BIT|ADD_FCS_BIT|LTINT_BIT);
1457
1458 lp->tx_idx++;
1459
1460 /* Trigger an immediate send poll. */
1461 writel( VAL1 | TDMD0, lp->mmio + CMD0);
1462 writel( VAL2 | RDMD0,lp->mmio + CMD0);
1463
1464 dev->trans_start = jiffies;
1465
1466 if(amd8111e_tx_queue_avail(lp) < 0){
1467 netif_stop_queue(dev);
1468 }
1469 spin_unlock_irqrestore(&lp->lock, flags);
1470 return 0;
1471}
1472/*
1473This function returns all the memory mapped registers of the device.
1474*/
1475static void amd8111e_read_regs(struct amd8111e_priv *lp, u32 *buf)
1476{
1477 void __iomem *mmio = lp->mmio;
1478 /* Read only necessary registers */
1479 buf[0] = readl(mmio + XMT_RING_BASE_ADDR0);
1480 buf[1] = readl(mmio + XMT_RING_LEN0);
1481 buf[2] = readl(mmio + RCV_RING_BASE_ADDR0);
1482 buf[3] = readl(mmio + RCV_RING_LEN0);
1483 buf[4] = readl(mmio + CMD0);
1484 buf[5] = readl(mmio + CMD2);
1485 buf[6] = readl(mmio + CMD3);
1486 buf[7] = readl(mmio + CMD7);
1487 buf[8] = readl(mmio + INT0);
1488 buf[9] = readl(mmio + INTEN0);
1489 buf[10] = readl(mmio + LADRF);
1490 buf[11] = readl(mmio + LADRF+4);
1491 buf[12] = readl(mmio + STAT0);
1492}
1493
6aa20a22 1494
1da177e4 1495/*
6aa20a22 1496This function sets promiscuos mode, all-multi mode or the multicast address
1da177e4
LT		 1497list to the device.
1498*/
1499static void amd8111e_set_multicast_list(struct net_device *dev)
1500{
1501 struct dev_mc_list* mc_ptr;
1502 struct amd8111e_priv *lp = netdev_priv(dev);
1503 u32 mc_filter[2] ;
1504 int i,bit_num;
1505 if(dev->flags & IFF_PROMISC){
1da177e4
LT		 1506 writel( VAL2 | PROM, lp->mmio + CMD2);
1507 return;
1508 }
1509 else
1510 writel( PROM, lp->mmio + CMD2);
1511 if(dev->flags & IFF_ALLMULTI || dev->mc_count > MAX_FILTER_SIZE){
1512 /* get all multicast packet */
1513 mc_filter[1] = mc_filter[0] = 0xffffffff;
1514 lp->mc_list = dev->mc_list;
1515 lp->options |= OPTION_MULTICAST_ENABLE;
1516 amd8111e_writeq(*(u64*)mc_filter,lp->mmio + LADRF);
1517 return;
1518 }
1519 if( dev->mc_count == 0 ){
1520 /* get only own packets */
1521 mc_filter[1] = mc_filter[0] = 0;
1522 lp->mc_list = NULL;
1523 lp->options &= ~OPTION_MULTICAST_ENABLE;
1524 amd8111e_writeq(*(u64*)mc_filter,lp->mmio + LADRF);
1525 /* disable promiscous mode */
1526 writel(PROM, lp->mmio + CMD2);
1527 return;
1528 }
1529 /* load all the multicast addresses in the logic filter */
1530 lp->options |= OPTION_MULTICAST_ENABLE;
1531 lp->mc_list = dev->mc_list;
1532 mc_filter[1] = mc_filter[0] = 0;
1533 for (i = 0, mc_ptr = dev->mc_list; mc_ptr && i < dev->mc_count;
1534 i++, mc_ptr = mc_ptr->next) {
6b4bdde6 1535 bit_num = (ether_crc_le(ETH_ALEN, mc_ptr->dmi_addr) >> 26) & 0x3f;
1da177e4 1536 mc_filter[bit_num >> 5] |= 1 << (bit_num & 31);
6aa20a22 1537 }
1da177e4
LT		 1538 amd8111e_writeq(*(u64*)mc_filter,lp->mmio+ LADRF);
1539
1540 /* To eliminate PCI posting bug */
1541 readl(lp->mmio + CMD2);
1542
1543}
1544
1545static void amd8111e_get_drvinfo(struct net_device* dev, struct ethtool_drvinfo *info)
1546{
1547 struct amd8111e_priv *lp = netdev_priv(dev);
1548 struct pci_dev *pci_dev = lp->pci_dev;
1549 strcpy (info->driver, MODULE_NAME);
1550 strcpy (info->version, MODULE_VERS);
1551 sprintf(info->fw_version,"%u",chip_version);
1552 strcpy (info->bus_info, pci_name(pci_dev));
1553}
1554
1555static int amd8111e_get_regs_len(struct net_device *dev)
1556{
1557 return AMD8111E_REG_DUMP_LEN;
1558}
1559
1560static void amd8111e_get_regs(struct net_device *dev, struct ethtool_regs *regs, void *buf)
1561{
1562 struct amd8111e_priv *lp = netdev_priv(dev);
1563 regs->version = 0;
1564 amd8111e_read_regs(lp, buf);
1565}
1566
1567static int amd8111e_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
1568{
1569 struct amd8111e_priv *lp = netdev_priv(dev);
1570 spin_lock_irq(&lp->lock);
1571 mii_ethtool_gset(&lp->mii_if, ecmd);
1572 spin_unlock_irq(&lp->lock);
1573 return 0;
1574}
1575
1576static int amd8111e_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
1577{
1578 struct amd8111e_priv *lp = netdev_priv(dev);
1579 int res;
1580 spin_lock_irq(&lp->lock);
1581 res = mii_ethtool_sset(&lp->mii_if, ecmd);
1582 spin_unlock_irq(&lp->lock);
1583 return res;
1584}
1585
1586static int amd8111e_nway_reset(struct net_device *dev)
1587{
1588 struct amd8111e_priv *lp = netdev_priv(dev);
1589 return mii_nway_restart(&lp->mii_if);
1590}
1591
1592static u32 amd8111e_get_link(struct net_device *dev)
1593{
1594 struct amd8111e_priv *lp = netdev_priv(dev);
1595 return mii_link_ok(&lp->mii_if);
1596}
1597
1598static void amd8111e_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol_info)
1599{
1600 struct amd8111e_priv *lp = netdev_priv(dev);
1601 wol_info->supported = WAKE_MAGIC|WAKE_PHY;
1602 if (lp->options & OPTION_WOL_ENABLE)
1603 wol_info->wolopts = WAKE_MAGIC;
1604}
1605
1606static int amd8111e_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol_info)
1607{
1608 struct amd8111e_priv *lp = netdev_priv(dev);
1609 if (wol_info->wolopts & ~(WAKE_MAGIC|WAKE_PHY))
1610 return -EINVAL;
1611 spin_lock_irq(&lp->lock);
1612 if (wol_info->wolopts & WAKE_MAGIC)
6aa20a22 1613 lp->options |=
1da177e4
LT		 1614 (OPTION_WOL_ENABLE | OPTION_WAKE_MAGIC_ENABLE);
1615 else if(wol_info->wolopts & WAKE_PHY)
6aa20a22 1616 lp->options |=
1da177e4
LT		 1617 (OPTION_WOL_ENABLE | OPTION_WAKE_PHY_ENABLE);
1618 else
6aa20a22 1619 lp->options &= ~OPTION_WOL_ENABLE;
1da177e4
LT		 1620 spin_unlock_irq(&lp->lock);
1621 return 0;
1622}
1623
7282d491 1624static const struct ethtool_ops ops = {
1da177e4
LT		 1625 .get_drvinfo = amd8111e_get_drvinfo,
1626 .get_regs_len = amd8111e_get_regs_len,
1627 .get_regs = amd8111e_get_regs,
1628 .get_settings = amd8111e_get_settings,
1629 .set_settings = amd8111e_set_settings,
1630 .nway_reset = amd8111e_nway_reset,
1631 .get_link = amd8111e_get_link,
1632 .get_wol = amd8111e_get_wol,
1633 .set_wol = amd8111e_set_wol,
1634};
1635
1636/*
6aa20a22 1637This function handles all the ethtool ioctls. It gives driver info, gets/sets driver speed, gets memory mapped register values, forces auto negotiation, sets/gets WOL options for ethtool application.
1da177e4 1638*/
6aa20a22 1639
1da177e4
LT		 1640static int amd8111e_ioctl(struct net_device * dev , struct ifreq *ifr, int cmd)
1641{
1642 struct mii_ioctl_data *data = if_mii(ifr);
1643 struct amd8111e_priv *lp = netdev_priv(dev);
1644 int err;
1645 u32 mii_regval;
1646
1647 if (!capable(CAP_NET_ADMIN))
1648 return -EPERM;
1649
1650 switch(cmd) {
1651 case SIOCGMIIPHY:
1652 data->phy_id = lp->ext_phy_addr;
1653
1654 /* fallthru */
6aa20a22 1655 case SIOCGMIIREG:
1da177e4
LT		 1656
1657 spin_lock_irq(&lp->lock);
1658 err = amd8111e_read_phy(lp, data->phy_id,
1659 data->reg_num & PHY_REG_ADDR_MASK, &mii_regval);
1660 spin_unlock_irq(&lp->lock);
1661
1662 data->val_out = mii_regval;
1663 return err;
1664
1665 case SIOCSMIIREG:
1666
1667 spin_lock_irq(&lp->lock);
1668 err = amd8111e_write_phy(lp, data->phy_id,
1669 data->reg_num & PHY_REG_ADDR_MASK, data->val_in);
1670 spin_unlock_irq(&lp->lock);
1671
1672 return err;
1673
1674 default:
1675 /* do nothing */
1676 break;
1677 }
1678 return -EOPNOTSUPP;
1679}
1680static int amd8111e_set_mac_address(struct net_device *dev, void *p)
1681{
1682 struct amd8111e_priv *lp = netdev_priv(dev);
1683 int i;
1684 struct sockaddr *addr = p;
1685
1686 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
1687 spin_lock_irq(&lp->lock);
1688 /* Setting the MAC address to the device */
1689 for(i = 0; i < ETH_ADDR_LEN; i++)
6aa20a22
JG		 1690 writeb( dev->dev_addr[i], lp->mmio + PADR + i );
1691
1da177e4
LT		 1692 spin_unlock_irq(&lp->lock);
1693
1694 return 0;
1695}
1696
6aa20a22 1697/*
1da177e4 1698This function changes the mtu of the device. It restarts the device to initialize the descriptor with new receive buffers.
6aa20a22 1699*/
1da177e4
LT		 1700static int amd8111e_change_mtu(struct net_device *dev, int new_mtu)
1701{
1702 struct amd8111e_priv *lp = netdev_priv(dev);
1703 int err;
1704
1705 if ((new_mtu < AMD8111E_MIN_MTU) || (new_mtu > AMD8111E_MAX_MTU))
1706 return -EINVAL;
1707
1708 if (!netif_running(dev)) {
1709 /* new_mtu will be used
6aa20a22 1710 when device starts netxt time */
1da177e4
LT		 1711 dev->mtu = new_mtu;
1712 return 0;
1713 }
1714
1715 spin_lock_irq(&lp->lock);
1716
1717 /* stop the chip */
1718 writel(RUN, lp->mmio + CMD0);
1719
1720 dev->mtu = new_mtu;
1721
1722 err = amd8111e_restart(dev);
1723 spin_unlock_irq(&lp->lock);
1724 if(!err)
1725 netif_start_queue(dev);
1726 return err;
1727}
1728
1729#if AMD8111E_VLAN_TAG_USED
1730static void amd8111e_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
1731{
1732 struct amd8111e_priv *lp = netdev_priv(dev);
1733 spin_lock_irq(&lp->lock);
1734 lp->vlgrp = grp;
1735 spin_unlock_irq(&lp->lock);
1736}
1da177e4 1737#endif
25805dcf 1738
1da177e4
LT		 1739static int amd8111e_enable_magicpkt(struct amd8111e_priv* lp)
1740{
1741 writel( VAL1|MPPLBA, lp->mmio + CMD3);
1742 writel( VAL0|MPEN_SW, lp->mmio + CMD7);
1743
1744 /* To eliminate PCI posting bug */
1745 readl(lp->mmio + CMD7);
1746 return 0;
1747}
1748
1749static int amd8111e_enable_link_change(struct amd8111e_priv* lp)
1750{
1751
1752 /* Adapter is already stoped/suspended/interrupt-disabled */
1753 writel(VAL0|LCMODE_SW,lp->mmio + CMD7);
6aa20a22 1754
1da177e4
LT		 1755 /* To eliminate PCI posting bug */
1756 readl(lp->mmio + CMD7);
1757 return 0;
6aa20a22 1758}
1da177e4
LT		 1759/* This function is called when a packet transmission fails to complete within a resonable period, on the assumption that an interrupts have been failed or the interface is locked up. This function will reinitialize the hardware */
1760
1761static void amd8111e_tx_timeout(struct net_device *dev)
1762{
1763 struct amd8111e_priv* lp = netdev_priv(dev);
1764 int err;
1765
1766 printk(KERN_ERR "%s: transmit timed out, resetting\n",
1767 dev->name);
1768 spin_lock_irq(&lp->lock);
1769 err = amd8111e_restart(dev);
1770 spin_unlock_irq(&lp->lock);
1771 if(!err)
1772 netif_wake_queue(dev);
1773}
1774static int amd8111e_suspend(struct pci_dev *pci_dev, pm_message_t state)
6aa20a22 1775{
1da177e4
LT		 1776 struct net_device *dev = pci_get_drvdata(pci_dev);
1777 struct amd8111e_priv *lp = netdev_priv(dev);
6aa20a22 1778
1da177e4
LT		 1779 if (!netif_running(dev))
1780 return 0;
1781
1782 /* disable the interrupt */
1783 spin_lock_irq(&lp->lock);
1784 amd8111e_disable_interrupt(lp);
1785 spin_unlock_irq(&lp->lock);
1786
1787 netif_device_detach(dev);
6aa20a22 1788
1da177e4
LT		 1789 /* stop chip */
1790 spin_lock_irq(&lp->lock);
6aa20a22 1791 if(lp->options & OPTION_DYN_IPG_ENABLE)
1da177e4
LT		 1792 del_timer_sync(&lp->ipg_data.ipg_timer);
1793 amd8111e_stop_chip(lp);
1794 spin_unlock_irq(&lp->lock);
1795
1796 if(lp->options & OPTION_WOL_ENABLE){
1797 /* enable wol */
1798 if(lp->options & OPTION_WAKE_MAGIC_ENABLE)
6aa20a22 1799 amd8111e_enable_magicpkt(lp);
1da177e4 1800 if(lp->options & OPTION_WAKE_PHY_ENABLE)
6aa20a22
JG		 1801 amd8111e_enable_link_change(lp);
1802
1da177e4
LT		 1803 pci_enable_wake(pci_dev, PCI_D3hot, 1);
1804 pci_enable_wake(pci_dev, PCI_D3cold, 1);
1805
1806 }
6aa20a22 1807 else{
1da177e4
LT		 1808 pci_enable_wake(pci_dev, PCI_D3hot, 0);
1809 pci_enable_wake(pci_dev, PCI_D3cold, 0);
1810 }
6aa20a22 1811
1da177e4
LT		 1812 pci_save_state(pci_dev);
1813 pci_set_power_state(pci_dev, PCI_D3hot);
1814
1815 return 0;
1816}
1817static int amd8111e_resume(struct pci_dev *pci_dev)
1818{
1819 struct net_device *dev = pci_get_drvdata(pci_dev);
1820 struct amd8111e_priv *lp = netdev_priv(dev);
6aa20a22 1821
1da177e4
LT		 1822 if (!netif_running(dev))
1823 return 0;
1824
1825 pci_set_power_state(pci_dev, PCI_D0);
1826 pci_restore_state(pci_dev);
1827
1828 pci_enable_wake(pci_dev, PCI_D3hot, 0);
1829 pci_enable_wake(pci_dev, PCI_D3cold, 0); /* D3 cold */
1830
1831 netif_device_attach(dev);
1832
1833 spin_lock_irq(&lp->lock);
1834 amd8111e_restart(dev);
1835 /* Restart ipg timer */
6aa20a22
JG		 1836 if(lp->options & OPTION_DYN_IPG_ENABLE)
1837 mod_timer(&lp->ipg_data.ipg_timer,
1da177e4
LT		 1838 jiffies + IPG_CONVERGE_JIFFIES);
1839 spin_unlock_irq(&lp->lock);
1840
1841 return 0;
1842}
1843
1844
1845static void __devexit amd8111e_remove_one(struct pci_dev *pdev)
1846{
1847 struct net_device *dev = pci_get_drvdata(pdev);
1848 if (dev) {
1849 unregister_netdev(dev);
1850 iounmap(((struct amd8111e_priv *)netdev_priv(dev))->mmio);
1851 free_netdev(dev);
1852 pci_release_regions(pdev);
1853 pci_disable_device(pdev);
1854 pci_set_drvdata(pdev, NULL);
1855 }
1856}
1857static void amd8111e_config_ipg(struct net_device* dev)
1858{
1859 struct amd8111e_priv *lp = netdev_priv(dev);
1860 struct ipg_info* ipg_data = &lp->ipg_data;
1861 void __iomem *mmio = lp->mmio;
1862 unsigned int prev_col_cnt = ipg_data->col_cnt;
1863 unsigned int total_col_cnt;
1864 unsigned int tmp_ipg;
6aa20a22 1865
1da177e4
LT		 1866 if(lp->link_config.duplex == DUPLEX_FULL){
1867 ipg_data->ipg = DEFAULT_IPG;
1868 return;
1869 }
1870
1871 if(ipg_data->ipg_state == SSTATE){
6aa20a22 1872
1da177e4 1873 if(ipg_data->timer_tick == IPG_STABLE_TIME){
6aa20a22 1874
1da177e4
LT		 1875 ipg_data->timer_tick = 0;
1876 ipg_data->ipg = MIN_IPG - IPG_STEP;
1877 ipg_data->current_ipg = MIN_IPG;
1878 ipg_data->diff_col_cnt = 0xFFFFFFFF;
1879 ipg_data->ipg_state = CSTATE;
1880 }
1881 else
1882 ipg_data->timer_tick++;
1883 }
1884
1885 if(ipg_data->ipg_state == CSTATE){
6aa20a22 1886
1da177e4
LT		 1887 /* Get the current collision count */
1888
6aa20a22 1889 total_col_cnt = ipg_data->col_cnt =
1da177e4
LT		 1890 amd8111e_read_mib(mmio, xmt_collisions);
1891
6aa20a22 1892 if ((total_col_cnt - prev_col_cnt) <
1da177e4 1893 (ipg_data->diff_col_cnt)){
6aa20a22 1894
1da177e4
LT		 1895 ipg_data->diff_col_cnt =
1896 total_col_cnt - prev_col_cnt ;
1897
1898 ipg_data->ipg = ipg_data->current_ipg;
1899 }
1900
1901 ipg_data->current_ipg += IPG_STEP;
1902
1903 if (ipg_data->current_ipg <= MAX_IPG)
1904 tmp_ipg = ipg_data->current_ipg;
1905 else{
1906 tmp_ipg = ipg_data->ipg;
1907 ipg_data->ipg_state = SSTATE;
1908 }
6aa20a22
JG		 1909 writew((u32)tmp_ipg, mmio + IPG);
1910 writew((u32)(tmp_ipg - IFS1_DELTA), mmio + IFS1);
1da177e4
LT		 1911 }
1912 mod_timer(&lp->ipg_data.ipg_timer, jiffies + IPG_CONVERGE_JIFFIES);
1913 return;
1914
1915}
1916
1917static void __devinit amd8111e_probe_ext_phy(struct net_device* dev)
1918{
1919 struct amd8111e_priv *lp = netdev_priv(dev);
1920 int i;
1921
1922 for (i = 0x1e; i >= 0; i--) {
1923 u32 id1, id2;
1924
1925 if (amd8111e_read_phy(lp, i, MII_PHYSID1, &id1))
1926 continue;
1927 if (amd8111e_read_phy(lp, i, MII_PHYSID2, &id2))
1928 continue;
1929 lp->ext_phy_id = (id1 << 16) | id2;
1930 lp->ext_phy_addr = i;
1931 return;
1932 }
1933 lp->ext_phy_id = 0;
1934 lp->ext_phy_addr = 1;
1935}
1936
1937static int __devinit amd8111e_probe_one(struct pci_dev *pdev,
1938 const struct pci_device_id *ent)
1939{
1940 int err,i,pm_cap;
1941 unsigned long reg_addr,reg_len;
1942 struct amd8111e_priv* lp;
1943 struct net_device* dev;
0795af57 1944 DECLARE_MAC_BUF(mac);
1da177e4
LT		 1945
1946 err = pci_enable_device(pdev);
1947 if(err){
2450022a 1948 printk(KERN_ERR "amd8111e: Cannot enable new PCI device, "
1da177e4
LT		 1949 "exiting.\n");
1950 return err;
1951 }
1952
1953 if(!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)){
2450022a 1954 printk(KERN_ERR "amd8111e: Cannot find PCI base address, "
1da177e4
LT		 1955 "exiting.\n");
1956 err = -ENODEV;
1957 goto err_disable_pdev;
1958 }
1959
1960 err = pci_request_regions(pdev, MODULE_NAME);
1961 if(err){
1962 printk(KERN_ERR "amd8111e: Cannot obtain PCI resources, "
1963 "exiting.\n");
1964 goto err_disable_pdev;
1965 }
1966
1967 pci_set_master(pdev);
1968
1969 /* Find power-management capability. */
1970 if((pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM))==0){
1971 printk(KERN_ERR "amd8111e: No Power Management capability, "
1972 "exiting.\n");
1973 goto err_free_reg;
1974 }
1975
1976 /* Initialize DMA */
cac8c81a 1977 if (pci_set_dma_mask(pdev, DMA_32BIT_MASK) < 0) {
1da177e4
LT		 1978 printk(KERN_ERR "amd8111e: DMA not supported,"
1979 "exiting.\n");
cac8c81a
TK		 1980 goto err_free_reg;
1981 }
6aa20a22 1982
1da177e4
LT		 1983 reg_addr = pci_resource_start(pdev, 0);
1984 reg_len = pci_resource_len(pdev, 0);
1985
1986 dev = alloc_etherdev(sizeof(struct amd8111e_priv));
1987 if (!dev) {
1988 printk(KERN_ERR "amd8111e: Etherdev alloc failed, exiting.\n");
1989 err = -ENOMEM;
1990 goto err_free_reg;
1991 }
1992
1da177e4
LT		 1993 SET_NETDEV_DEV(dev, &pdev->dev);
1994
1995#if AMD8111E_VLAN_TAG_USED
1996 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX ;
1997 dev->vlan_rx_register =amd8111e_vlan_rx_register;
6aa20a22
JG		 1998#endif
1999
1da177e4
LT		 2000 lp = netdev_priv(dev);
2001 lp->pci_dev = pdev;
2002 lp->amd8111e_net_dev = dev;
2003 lp->pm_cap = pm_cap;
2004
2005 spin_lock_init(&lp->lock);
2006
2007 lp->mmio = ioremap(reg_addr, reg_len);
ee41a82f 2008 if (!lp->mmio) {
1da177e4
LT		 2009 printk(KERN_ERR "amd8111e: Cannot map device registers, "
2010 "exiting\n");
2011 err = -ENOMEM;
2012 goto err_free_dev;
2013 }
6aa20a22 2014
1da177e4
LT		 2015 /* Initializing MAC address */
2016 for(i = 0; i < ETH_ADDR_LEN; i++)
0795af57 2017 dev->dev_addr[i] = readb(lp->mmio + PADR + i);
6aa20a22 2018
1da177e4
LT		 2019 /* Setting user defined parametrs */
2020 lp->ext_phy_option = speed_duplex[card_idx];
2021 if(coalesce[card_idx])
6aa20a22 2022 lp->options |= OPTION_INTR_COAL_ENABLE;
1da177e4 2023 if(dynamic_ipg[card_idx++])
6aa20a22 2024 lp->options |= OPTION_DYN_IPG_ENABLE;
1da177e4
LT		 2025
2026 /* Initialize driver entry points */
2027 dev->open = amd8111e_open;
2028 dev->hard_start_xmit = amd8111e_start_xmit;
2029 dev->stop = amd8111e_close;
2030 dev->get_stats = amd8111e_get_stats;
2031 dev->set_multicast_list = amd8111e_set_multicast_list;
2032 dev->set_mac_address = amd8111e_set_mac_address;
2033 dev->do_ioctl = amd8111e_ioctl;
2034 dev->change_mtu = amd8111e_change_mtu;
2035 SET_ETHTOOL_OPS(dev, &ops);
2036 dev->irq =pdev->irq;
6aa20a22
JG		 2037 dev->tx_timeout = amd8111e_tx_timeout;
2038 dev->watchdog_timeo = AMD8111E_TX_TIMEOUT;
1da177e4 2039#ifdef CONFIG_AMD8111E_NAPI
bea3348e 2040 netif_napi_add(dev, &lp->napi, amd8111e_rx_poll, 32);
1da177e4
LT		 2041#endif
2042#ifdef CONFIG_NET_POLL_CONTROLLER
6aa20a22 2043 dev->poll_controller = amd8111e_poll;
1da177e4
LT		 2044#endif
2045
2046#if AMD8111E_VLAN_TAG_USED
2047 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
2048 dev->vlan_rx_register =amd8111e_vlan_rx_register;
6aa20a22 2049#endif
1da177e4
LT		 2050 /* Probe the external PHY */
2051 amd8111e_probe_ext_phy(dev);
2052
2053 /* setting mii default values */
2054 lp->mii_if.dev = dev;
2055 lp->mii_if.mdio_read = amd8111e_mdio_read;
2056 lp->mii_if.mdio_write = amd8111e_mdio_write;
2057 lp->mii_if.phy_id = lp->ext_phy_addr;
2058
2059 /* Set receive buffer length and set jumbo option*/
2060 amd8111e_set_rx_buff_len(dev);
2061
2062
2063 err = register_netdev(dev);
2064 if (err) {
2065 printk(KERN_ERR "amd8111e: Cannot register net device, "
2066 "exiting.\n");
2067 goto err_iounmap;
2068 }
2069
2070 pci_set_drvdata(pdev, dev);
6aa20a22 2071
1da177e4 2072 /* Initialize software ipg timer */
6aa20a22 2073 if(lp->options & OPTION_DYN_IPG_ENABLE){
1da177e4
LT		 2074 init_timer(&lp->ipg_data.ipg_timer);
2075 lp->ipg_data.ipg_timer.data = (unsigned long) dev;
2076 lp->ipg_data.ipg_timer.function = (void *)&amd8111e_config_ipg;
6aa20a22 2077 lp->ipg_data.ipg_timer.expires = jiffies +
1da177e4
LT		 2078 IPG_CONVERGE_JIFFIES;
2079 lp->ipg_data.ipg = DEFAULT_IPG;
2080 lp->ipg_data.ipg_state = CSTATE;
2081 };
2082
2083 /* display driver and device information */
2084
2085 chip_version = (readl(lp->mmio + CHIPID) & 0xf0000000)>>28;
0795af57
JP		 2086 printk(KERN_INFO "%s: AMD-8111e Driver Version: %s\n",
2087 dev->name,MODULE_VERS);
2088 printk(KERN_INFO "%s: [ Rev %x ] PCI 10/100BaseT Ethernet %s\n",
2089 dev->name, chip_version, print_mac(mac, dev->dev_addr));
1da177e4
LT		 2090 if (lp->ext_phy_id)
2091 printk(KERN_INFO "%s: Found MII PHY ID 0x%08x at address 0x%02x\n",
2092 dev->name, lp->ext_phy_id, lp->ext_phy_addr);
2093 else
2094 printk(KERN_INFO "%s: Couldn't detect MII PHY, assuming address 0x01\n",
2095 dev->name);
2096 return 0;
2097err_iounmap:
2098 iounmap(lp->mmio);
2099
2100err_free_dev:
2101 free_netdev(dev);
2102
2103err_free_reg:
2104 pci_release_regions(pdev);
2105
2106err_disable_pdev:
2107 pci_disable_device(pdev);
2108 pci_set_drvdata(pdev, NULL);
2109 return err;
2110
2111}
2112
2113static struct pci_driver amd8111e_driver = {
2114 .name = MODULE_NAME,
2115 .id_table = amd8111e_pci_tbl,
2116 .probe = amd8111e_probe_one,
2117 .remove = __devexit_p(amd8111e_remove_one),
2118 .suspend = amd8111e_suspend,
2119 .resume = amd8111e_resume
2120};
2121
2122static int __init amd8111e_init(void)
2123{
29917620 2124 return pci_register_driver(&amd8111e_driver);
1da177e4
LT		 2125}
2126
2127static void __exit amd8111e_cleanup(void)
2128{
2129 pci_unregister_driver(&amd8111e_driver);
2130}
2131
2132module_init(amd8111e_init);
2133module_exit(amd8111e_cleanup);
Linux kernel - Deliverables
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