[PATCH] AT91RM9200 Ethernet: Move check_timer variable and use mod_timer()
[deliverable/linux.git] / drivers / net / arm / at91_ether.c
CommitLineData
d4b7780e
AV
1/*
2 * Ethernet driver for the Atmel AT91RM9200 (Thunder)
3 *
4 * Copyright (C) 2003 SAN People (Pty) Ltd
5 *
6 * Based on an earlier Atmel EMAC macrocell driver by Atmel and Lineo Inc.
7 * Initial version by Rick Bronson 01/11/2003
8 *
9 * Intel LXT971A PHY support by Christopher Bahns & David Knickerbocker
10 * (Polaroid Corporation)
11 *
12 * Realtek RTL8201(B)L PHY support by Roman Avramenko <roman@imsystems.ru>
13 *
14 * This program is free software; you can redistribute it and/or
15 * modify it under the terms of the GNU General Public License
16 * as published by the Free Software Foundation; either version
17 * 2 of the License, or (at your option) any later version.
18 */
19
20#include <linux/module.h>
21#include <linux/init.h>
d4b7780e
AV
22#include <linux/mii.h>
23#include <linux/netdevice.h>
24#include <linux/etherdevice.h>
25#include <linux/skbuff.h>
26#include <linux/dma-mapping.h>
27#include <linux/ethtool.h>
28#include <linux/platform_device.h>
29#include <linux/clk.h>
30
31#include <asm/io.h>
32#include <asm/uaccess.h>
33#include <asm/mach-types.h>
34
35#include <asm/arch/at91rm9200_emac.h>
36#include <asm/arch/gpio.h>
37#include <asm/arch/board.h>
38
39#include "at91_ether.h"
40
41#define DRV_NAME "at91_ether"
42#define DRV_VERSION "1.0"
43
775637df
AV
44#define LINK_POLL_INTERVAL (HZ)
45
d4b7780e
AV
46/* ..................................................................... */
47
48/*
49 * Read from a EMAC register.
50 */
51static inline unsigned long at91_emac_read(unsigned int reg)
52{
53 void __iomem *emac_base = (void __iomem *)AT91_VA_BASE_EMAC;
54
55 return __raw_readl(emac_base + reg);
56}
57
58/*
59 * Write to a EMAC register.
60 */
61static inline void at91_emac_write(unsigned int reg, unsigned long value)
62{
63 void __iomem *emac_base = (void __iomem *)AT91_VA_BASE_EMAC;
64
65 __raw_writel(value, emac_base + reg);
66}
67
68/* ........................... PHY INTERFACE ........................... */
69
70/*
71 * Enable the MDIO bit in MAC control register
72 * When not called from an interrupt-handler, access to the PHY must be
73 * protected by a spinlock.
74 */
75static void enable_mdi(void)
76{
77 unsigned long ctl;
78
79 ctl = at91_emac_read(AT91_EMAC_CTL);
80 at91_emac_write(AT91_EMAC_CTL, ctl | AT91_EMAC_MPE); /* enable management port */
81}
82
83/*
84 * Disable the MDIO bit in the MAC control register
85 */
86static void disable_mdi(void)
87{
88 unsigned long ctl;
89
90 ctl = at91_emac_read(AT91_EMAC_CTL);
91 at91_emac_write(AT91_EMAC_CTL, ctl & ~AT91_EMAC_MPE); /* disable management port */
92}
93
94/*
95 * Wait until the PHY operation is complete.
96 */
97static inline void at91_phy_wait(void) {
98 unsigned long timeout = jiffies + 2;
99
100 while (!(at91_emac_read(AT91_EMAC_SR) & AT91_EMAC_SR_IDLE)) {
101 if (time_after(jiffies, timeout)) {
102 printk("at91_ether: MIO timeout\n");
103 break;
104 }
105 cpu_relax();
106 }
107}
108
109/*
110 * Write value to the a PHY register
111 * Note: MDI interface is assumed to already have been enabled.
112 */
113static void write_phy(unsigned char phy_addr, unsigned char address, unsigned int value)
114{
115 at91_emac_write(AT91_EMAC_MAN, AT91_EMAC_MAN_802_3 | AT91_EMAC_RW_W
116 | ((phy_addr & 0x1f) << 23) | (address << 18) | (value & AT91_EMAC_DATA));
117
118 /* Wait until IDLE bit in Network Status register is cleared */
119 at91_phy_wait();
120}
121
122/*
123 * Read value stored in a PHY register.
124 * Note: MDI interface is assumed to already have been enabled.
125 */
126static void read_phy(unsigned char phy_addr, unsigned char address, unsigned int *value)
127{
128 at91_emac_write(AT91_EMAC_MAN, AT91_EMAC_MAN_802_3 | AT91_EMAC_RW_R
129 | ((phy_addr & 0x1f) << 23) | (address << 18));
130
131 /* Wait until IDLE bit in Network Status register is cleared */
132 at91_phy_wait();
133
134 *value = at91_emac_read(AT91_EMAC_MAN) & AT91_EMAC_DATA;
135}
136
137/* ........................... PHY MANAGEMENT .......................... */
138
139/*
140 * Access the PHY to determine the current link speed and mode, and update the
141 * MAC accordingly.
142 * If no link or auto-negotiation is busy, then no changes are made.
143 */
775637df 144static void update_linkspeed(struct net_device *dev, int silent)
d4b7780e 145{
c57ee096 146 struct at91_private *lp = netdev_priv(dev);
d4b7780e
AV
147 unsigned int bmsr, bmcr, lpa, mac_cfg;
148 unsigned int speed, duplex;
149
150 if (!mii_link_ok(&lp->mii)) { /* no link */
151 netif_carrier_off(dev);
775637df
AV
152 if (!silent)
153 printk(KERN_INFO "%s: Link down.\n", dev->name);
d4b7780e
AV
154 return;
155 }
156
157 /* Link up, or auto-negotiation still in progress */
158 read_phy(lp->phy_address, MII_BMSR, &bmsr);
159 read_phy(lp->phy_address, MII_BMCR, &bmcr);
160 if (bmcr & BMCR_ANENABLE) { /* AutoNegotiation is enabled */
161 if (!(bmsr & BMSR_ANEGCOMPLETE))
162 return; /* Do nothing - another interrupt generated when negotiation complete */
163
164 read_phy(lp->phy_address, MII_LPA, &lpa);
165 if ((lpa & LPA_100FULL) || (lpa & LPA_100HALF)) speed = SPEED_100;
166 else speed = SPEED_10;
167 if ((lpa & LPA_100FULL) || (lpa & LPA_10FULL)) duplex = DUPLEX_FULL;
168 else duplex = DUPLEX_HALF;
169 } else {
170 speed = (bmcr & BMCR_SPEED100) ? SPEED_100 : SPEED_10;
171 duplex = (bmcr & BMCR_FULLDPLX) ? DUPLEX_FULL : DUPLEX_HALF;
172 }
173
174 /* Update the MAC */
175 mac_cfg = at91_emac_read(AT91_EMAC_CFG) & ~(AT91_EMAC_SPD | AT91_EMAC_FD);
176 if (speed == SPEED_100) {
177 if (duplex == DUPLEX_FULL) /* 100 Full Duplex */
178 mac_cfg |= AT91_EMAC_SPD | AT91_EMAC_FD;
179 else /* 100 Half Duplex */
180 mac_cfg |= AT91_EMAC_SPD;
181 } else {
182 if (duplex == DUPLEX_FULL) /* 10 Full Duplex */
183 mac_cfg |= AT91_EMAC_FD;
184 else {} /* 10 Half Duplex */
185 }
186 at91_emac_write(AT91_EMAC_CFG, mac_cfg);
187
775637df
AV
188 if (!silent)
189 printk(KERN_INFO "%s: Link now %i-%s\n", dev->name, speed, (duplex == DUPLEX_FULL) ? "FullDuplex" : "HalfDuplex");
d4b7780e
AV
190 netif_carrier_on(dev);
191}
192
193/*
194 * Handle interrupts from the PHY
195 */
7d12e780 196static irqreturn_t at91ether_phy_interrupt(int irq, void *dev_id)
d4b7780e
AV
197{
198 struct net_device *dev = (struct net_device *) dev_id;
c57ee096 199 struct at91_private *lp = netdev_priv(dev);
d4b7780e
AV
200 unsigned int phy;
201
202 /*
203 * This hander is triggered on both edges, but the PHY chips expect
204 * level-triggering. We therefore have to check if the PHY actually has
205 * an IRQ pending.
206 */
207 enable_mdi();
208 if ((lp->phy_type == MII_DM9161_ID) || (lp->phy_type == MII_DM9161A_ID)) {
209 read_phy(lp->phy_address, MII_DSINTR_REG, &phy); /* ack interrupt in Davicom PHY */
210 if (!(phy & (1 << 0)))
211 goto done;
212 }
213 else if (lp->phy_type == MII_LXT971A_ID) {
214 read_phy(lp->phy_address, MII_ISINTS_REG, &phy); /* ack interrupt in Intel PHY */
215 if (!(phy & (1 << 2)))
216 goto done;
217 }
218 else if (lp->phy_type == MII_BCM5221_ID) {
219 read_phy(lp->phy_address, MII_BCMINTR_REG, &phy); /* ack interrupt in Broadcom PHY */
220 if (!(phy & (1 << 0)))
221 goto done;
222 }
223 else if (lp->phy_type == MII_KS8721_ID) {
224 read_phy(lp->phy_address, MII_TPISTATUS, &phy); /* ack interrupt in Micrel PHY */
225 if (!(phy & ((1 << 2) | 1)))
226 goto done;
227 }
228
775637df 229 update_linkspeed(dev, 0);
d4b7780e
AV
230
231done:
232 disable_mdi();
233
234 return IRQ_HANDLED;
235}
236
237/*
238 * Initialize and enable the PHY interrupt for link-state changes
239 */
240static void enable_phyirq(struct net_device *dev)
241{
c57ee096 242 struct at91_private *lp = netdev_priv(dev);
d4b7780e
AV
243 unsigned int dsintr, irq_number;
244 int status;
245
775637df
AV
246 irq_number = lp->board_data.phy_irq_pin;
247 if (!irq_number) {
248 /*
249 * PHY doesn't have an IRQ pin (RTL8201, DP83847, AC101L),
250 * or board does not have it connected.
251 */
cf42553a 252 mod_timer(&lp->check_timer, jiffies + LINK_POLL_INTERVAL);
d4b7780e 253 return;
775637df 254 }
d4b7780e 255
d4b7780e
AV
256 status = request_irq(irq_number, at91ether_phy_interrupt, 0, dev->name, dev);
257 if (status) {
258 printk(KERN_ERR "at91_ether: PHY IRQ %d request failed - status %d!\n", irq_number, status);
259 return;
260 }
261
262 spin_lock_irq(&lp->lock);
263 enable_mdi();
264
265 if ((lp->phy_type == MII_DM9161_ID) || (lp->phy_type == MII_DM9161A_ID)) { /* for Davicom PHY */
266 read_phy(lp->phy_address, MII_DSINTR_REG, &dsintr);
267 dsintr = dsintr & ~0xf00; /* clear bits 8..11 */
268 write_phy(lp->phy_address, MII_DSINTR_REG, dsintr);
269 }
270 else if (lp->phy_type == MII_LXT971A_ID) { /* for Intel PHY */
271 read_phy(lp->phy_address, MII_ISINTE_REG, &dsintr);
272 dsintr = dsintr | 0xf2; /* set bits 1, 4..7 */
273 write_phy(lp->phy_address, MII_ISINTE_REG, dsintr);
274 }
275 else if (lp->phy_type == MII_BCM5221_ID) { /* for Broadcom PHY */
276 dsintr = (1 << 15) | ( 1 << 14);
277 write_phy(lp->phy_address, MII_BCMINTR_REG, dsintr);
278 }
279 else if (lp->phy_type == MII_KS8721_ID) { /* for Micrel PHY */
280 dsintr = (1 << 10) | ( 1 << 8);
281 write_phy(lp->phy_address, MII_TPISTATUS, dsintr);
282 }
283
284 disable_mdi();
285 spin_unlock_irq(&lp->lock);
286}
287
288/*
289 * Disable the PHY interrupt
290 */
291static void disable_phyirq(struct net_device *dev)
292{
c57ee096 293 struct at91_private *lp = netdev_priv(dev);
d4b7780e
AV
294 unsigned int dsintr;
295 unsigned int irq_number;
296
775637df
AV
297 irq_number = lp->board_data.phy_irq_pin;
298 if (!irq_number) {
cf42553a 299 del_timer_sync(&lp->check_timer);
d4b7780e 300 return;
775637df 301 }
d4b7780e
AV
302
303 spin_lock_irq(&lp->lock);
304 enable_mdi();
305
306 if ((lp->phy_type == MII_DM9161_ID) || (lp->phy_type == MII_DM9161A_ID)) { /* for Davicom PHY */
307 read_phy(lp->phy_address, MII_DSINTR_REG, &dsintr);
308 dsintr = dsintr | 0xf00; /* set bits 8..11 */
309 write_phy(lp->phy_address, MII_DSINTR_REG, dsintr);
310 }
311 else if (lp->phy_type == MII_LXT971A_ID) { /* for Intel PHY */
312 read_phy(lp->phy_address, MII_ISINTE_REG, &dsintr);
313 dsintr = dsintr & ~0xf2; /* clear bits 1, 4..7 */
314 write_phy(lp->phy_address, MII_ISINTE_REG, dsintr);
315 }
316 else if (lp->phy_type == MII_BCM5221_ID) { /* for Broadcom PHY */
317 read_phy(lp->phy_address, MII_BCMINTR_REG, &dsintr);
318 dsintr = ~(1 << 14);
319 write_phy(lp->phy_address, MII_BCMINTR_REG, dsintr);
320 }
321 else if (lp->phy_type == MII_KS8721_ID) { /* for Micrel PHY */
322 read_phy(lp->phy_address, MII_TPISTATUS, &dsintr);
323 dsintr = ~((1 << 10) | (1 << 8));
324 write_phy(lp->phy_address, MII_TPISTATUS, dsintr);
325 }
326
327 disable_mdi();
328 spin_unlock_irq(&lp->lock);
329
d4b7780e
AV
330 free_irq(irq_number, dev); /* Free interrupt handler */
331}
332
333/*
334 * Perform a software reset of the PHY.
335 */
336#if 0
337static void reset_phy(struct net_device *dev)
338{
c57ee096 339 struct at91_private *lp = netdev_priv(dev);
d4b7780e
AV
340 unsigned int bmcr;
341
342 spin_lock_irq(&lp->lock);
343 enable_mdi();
344
345 /* Perform PHY reset */
346 write_phy(lp->phy_address, MII_BMCR, BMCR_RESET);
347
348 /* Wait until PHY reset is complete */
349 do {
350 read_phy(lp->phy_address, MII_BMCR, &bmcr);
351 } while (!(bmcr && BMCR_RESET));
352
353 disable_mdi();
354 spin_unlock_irq(&lp->lock);
355}
356#endif
357
775637df
AV
358static void at91ether_check_link(unsigned long dev_id)
359{
360 struct net_device *dev = (struct net_device *) dev_id;
cf42553a 361 struct at91_private *lp = netdev_priv(dev);
775637df
AV
362
363 enable_mdi();
364 update_linkspeed(dev, 1);
365 disable_mdi();
366
cf42553a 367 mod_timer(&lp->check_timer, jiffies + LINK_POLL_INTERVAL);
775637df
AV
368}
369
d4b7780e
AV
370/* ......................... ADDRESS MANAGEMENT ........................ */
371
372/*
373 * NOTE: Your bootloader must always set the MAC address correctly before
374 * booting into Linux.
375 *
376 * - It must always set the MAC address after reset, even if it doesn't
377 * happen to access the Ethernet while it's booting. Some versions of
378 * U-Boot on the AT91RM9200-DK do not do this.
379 *
380 * - Likewise it must store the addresses in the correct byte order.
381 * MicroMonitor (uMon) on the CSB337 does this incorrectly (and
382 * continues to do so, for bug-compatibility).
383 */
384
385static short __init unpack_mac_address(struct net_device *dev, unsigned int hi, unsigned int lo)
386{
387 char addr[6];
388
389 if (machine_is_csb337()) {
390 addr[5] = (lo & 0xff); /* The CSB337 bootloader stores the MAC the wrong-way around */
391 addr[4] = (lo & 0xff00) >> 8;
392 addr[3] = (lo & 0xff0000) >> 16;
393 addr[2] = (lo & 0xff000000) >> 24;
394 addr[1] = (hi & 0xff);
395 addr[0] = (hi & 0xff00) >> 8;
396 }
397 else {
398 addr[0] = (lo & 0xff);
399 addr[1] = (lo & 0xff00) >> 8;
400 addr[2] = (lo & 0xff0000) >> 16;
401 addr[3] = (lo & 0xff000000) >> 24;
402 addr[4] = (hi & 0xff);
403 addr[5] = (hi & 0xff00) >> 8;
404 }
405
406 if (is_valid_ether_addr(addr)) {
407 memcpy(dev->dev_addr, &addr, 6);
408 return 1;
409 }
410 return 0;
411}
412
413/*
414 * Set the ethernet MAC address in dev->dev_addr
415 */
416static void __init get_mac_address(struct net_device *dev)
417{
418 /* Check Specific-Address 1 */
419 if (unpack_mac_address(dev, at91_emac_read(AT91_EMAC_SA1H), at91_emac_read(AT91_EMAC_SA1L)))
420 return;
421 /* Check Specific-Address 2 */
422 if (unpack_mac_address(dev, at91_emac_read(AT91_EMAC_SA2H), at91_emac_read(AT91_EMAC_SA2L)))
423 return;
424 /* Check Specific-Address 3 */
425 if (unpack_mac_address(dev, at91_emac_read(AT91_EMAC_SA3H), at91_emac_read(AT91_EMAC_SA3L)))
426 return;
427 /* Check Specific-Address 4 */
428 if (unpack_mac_address(dev, at91_emac_read(AT91_EMAC_SA4H), at91_emac_read(AT91_EMAC_SA4L)))
429 return;
430
431 printk(KERN_ERR "at91_ether: Your bootloader did not configure a MAC address.\n");
432}
433
434/*
435 * Program the hardware MAC address from dev->dev_addr.
436 */
437static void update_mac_address(struct net_device *dev)
438{
439 at91_emac_write(AT91_EMAC_SA1L, (dev->dev_addr[3] << 24) | (dev->dev_addr[2] << 16) | (dev->dev_addr[1] << 8) | (dev->dev_addr[0]));
440 at91_emac_write(AT91_EMAC_SA1H, (dev->dev_addr[5] << 8) | (dev->dev_addr[4]));
441
442 at91_emac_write(AT91_EMAC_SA2L, 0);
443 at91_emac_write(AT91_EMAC_SA2H, 0);
444}
445
446/*
447 * Store the new hardware address in dev->dev_addr, and update the MAC.
448 */
449static int set_mac_address(struct net_device *dev, void* addr)
450{
451 struct sockaddr *address = addr;
452
453 if (!is_valid_ether_addr(address->sa_data))
454 return -EADDRNOTAVAIL;
455
456 memcpy(dev->dev_addr, address->sa_data, dev->addr_len);
457 update_mac_address(dev);
458
459 printk("%s: Setting MAC address to %02x:%02x:%02x:%02x:%02x:%02x\n", dev->name,
460 dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
461 dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
462
463 return 0;
464}
465
466static int inline hash_bit_value(int bitnr, __u8 *addr)
467{
468 if (addr[bitnr / 8] & (1 << (bitnr % 8)))
469 return 1;
470 return 0;
471}
472
473/*
474 * The hash address register is 64 bits long and takes up two locations in the memory map.
475 * The least significant bits are stored in EMAC_HSL and the most significant
476 * bits in EMAC_HSH.
477 *
478 * The unicast hash enable and the multicast hash enable bits in the network configuration
479 * register enable the reception of hash matched frames. The destination address is
480 * reduced to a 6 bit index into the 64 bit hash register using the following hash function.
481 * The hash function is an exclusive or of every sixth bit of the destination address.
482 * hash_index[5] = da[5] ^ da[11] ^ da[17] ^ da[23] ^ da[29] ^ da[35] ^ da[41] ^ da[47]
483 * hash_index[4] = da[4] ^ da[10] ^ da[16] ^ da[22] ^ da[28] ^ da[34] ^ da[40] ^ da[46]
484 * hash_index[3] = da[3] ^ da[09] ^ da[15] ^ da[21] ^ da[27] ^ da[33] ^ da[39] ^ da[45]
485 * hash_index[2] = da[2] ^ da[08] ^ da[14] ^ da[20] ^ da[26] ^ da[32] ^ da[38] ^ da[44]
486 * hash_index[1] = da[1] ^ da[07] ^ da[13] ^ da[19] ^ da[25] ^ da[31] ^ da[37] ^ da[43]
487 * hash_index[0] = da[0] ^ da[06] ^ da[12] ^ da[18] ^ da[24] ^ da[30] ^ da[36] ^ da[42]
488 * da[0] represents the least significant bit of the first byte received, that is, the multicast/
489 * unicast indicator, and da[47] represents the most significant bit of the last byte
490 * received.
491 * If the hash index points to a bit that is set in the hash register then the frame will be
492 * matched according to whether the frame is multicast or unicast.
493 * A multicast match will be signalled if the multicast hash enable bit is set, da[0] is 1 and
494 * the hash index points to a bit set in the hash register.
495 * A unicast match will be signalled if the unicast hash enable bit is set, da[0] is 0 and the
496 * hash index points to a bit set in the hash register.
497 * To receive all multicast frames, the hash register should be set with all ones and the
498 * multicast hash enable bit should be set in the network configuration register.
499 */
500
501/*
502 * Return the hash index value for the specified address.
503 */
504static int hash_get_index(__u8 *addr)
505{
506 int i, j, bitval;
507 int hash_index = 0;
508
509 for (j = 0; j < 6; j++) {
510 for (i = 0, bitval = 0; i < 8; i++)
511 bitval ^= hash_bit_value(i*6 + j, addr);
512
513 hash_index |= (bitval << j);
514 }
515
427d269f 516 return hash_index;
d4b7780e
AV
517}
518
519/*
520 * Add multicast addresses to the internal multicast-hash table.
521 */
522static void at91ether_sethashtable(struct net_device *dev)
523{
524 struct dev_mc_list *curr;
525 unsigned long mc_filter[2];
526 unsigned int i, bitnr;
527
528 mc_filter[0] = mc_filter[1] = 0;
529
530 curr = dev->mc_list;
531 for (i = 0; i < dev->mc_count; i++, curr = curr->next) {
532 if (!curr) break; /* unexpected end of list */
533
534 bitnr = hash_get_index(curr->dmi_addr);
535 mc_filter[bitnr >> 5] |= 1 << (bitnr & 31);
536 }
537
538 at91_emac_write(AT91_EMAC_HSH, mc_filter[0]);
539 at91_emac_write(AT91_EMAC_HSL, mc_filter[1]);
540}
541
542/*
543 * Enable/Disable promiscuous and multicast modes.
544 */
545static void at91ether_set_rx_mode(struct net_device *dev)
546{
547 unsigned long cfg;
548
549 cfg = at91_emac_read(AT91_EMAC_CFG);
550
551 if (dev->flags & IFF_PROMISC) /* Enable promiscuous mode */
552 cfg |= AT91_EMAC_CAF;
553 else if (dev->flags & (~IFF_PROMISC)) /* Disable promiscuous mode */
554 cfg &= ~AT91_EMAC_CAF;
555
556 if (dev->flags & IFF_ALLMULTI) { /* Enable all multicast mode */
557 at91_emac_write(AT91_EMAC_HSH, -1);
558 at91_emac_write(AT91_EMAC_HSL, -1);
559 cfg |= AT91_EMAC_MTI;
560 } else if (dev->mc_count > 0) { /* Enable specific multicasts */
561 at91ether_sethashtable(dev);
562 cfg |= AT91_EMAC_MTI;
563 } else if (dev->flags & (~IFF_ALLMULTI)) { /* Disable all multicast mode */
564 at91_emac_write(AT91_EMAC_HSH, 0);
565 at91_emac_write(AT91_EMAC_HSL, 0);
566 cfg &= ~AT91_EMAC_MTI;
567 }
568
569 at91_emac_write(AT91_EMAC_CFG, cfg);
570}
571
d4b7780e
AV
572/* ......................... ETHTOOL SUPPORT ........................... */
573
d4b7780e
AV
574static int mdio_read(struct net_device *dev, int phy_id, int location)
575{
576 unsigned int value;
577
578 read_phy(phy_id, location, &value);
579 return value;
580}
581
582static void mdio_write(struct net_device *dev, int phy_id, int location, int value)
583{
584 write_phy(phy_id, location, value);
585}
586
587static int at91ether_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
588{
c57ee096 589 struct at91_private *lp = netdev_priv(dev);
d4b7780e
AV
590 int ret;
591
592 spin_lock_irq(&lp->lock);
593 enable_mdi();
594
595 ret = mii_ethtool_gset(&lp->mii, cmd);
596
597 disable_mdi();
598 spin_unlock_irq(&lp->lock);
599
600 if (lp->phy_media == PORT_FIBRE) { /* override media type since mii.c doesn't know */
601 cmd->supported = SUPPORTED_FIBRE;
602 cmd->port = PORT_FIBRE;
603 }
604
605 return ret;
606}
607
608static int at91ether_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
609{
c57ee096 610 struct at91_private *lp = netdev_priv(dev);
d4b7780e
AV
611 int ret;
612
613 spin_lock_irq(&lp->lock);
614 enable_mdi();
615
616 ret = mii_ethtool_sset(&lp->mii, cmd);
617
618 disable_mdi();
619 spin_unlock_irq(&lp->lock);
620
621 return ret;
622}
623
624static int at91ether_nwayreset(struct net_device *dev)
625{
c57ee096 626 struct at91_private *lp = netdev_priv(dev);
d4b7780e
AV
627 int ret;
628
629 spin_lock_irq(&lp->lock);
630 enable_mdi();
631
632 ret = mii_nway_restart(&lp->mii);
633
634 disable_mdi();
635 spin_unlock_irq(&lp->lock);
636
637 return ret;
638}
639
640static void at91ether_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
641{
642 strlcpy(info->driver, DRV_NAME, sizeof(info->driver));
643 strlcpy(info->version, DRV_VERSION, sizeof(info->version));
644 strlcpy(info->bus_info, dev->class_dev.dev->bus_id, sizeof(info->bus_info));
645}
646
7282d491 647static const struct ethtool_ops at91ether_ethtool_ops = {
d4b7780e
AV
648 .get_settings = at91ether_get_settings,
649 .set_settings = at91ether_set_settings,
650 .get_drvinfo = at91ether_get_drvinfo,
651 .nway_reset = at91ether_nwayreset,
652 .get_link = ethtool_op_get_link,
653};
654
ca5585ed
AV
655static int at91ether_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
656{
c57ee096 657 struct at91_private *lp = netdev_priv(dev);
ca5585ed
AV
658 int res;
659
660 if (!netif_running(dev))
661 return -EINVAL;
662
663 spin_lock_irq(&lp->lock);
664 enable_mdi();
665 res = generic_mii_ioctl(&lp->mii, if_mii(rq), cmd, NULL);
666 disable_mdi();
667 spin_unlock_irq(&lp->lock);
668
669 return res;
670}
d4b7780e
AV
671
672/* ................................ MAC ................................ */
673
674/*
675 * Initialize and start the Receiver and Transmit subsystems
676 */
677static void at91ether_start(struct net_device *dev)
678{
c57ee096 679 struct at91_private *lp = netdev_priv(dev);
d4b7780e
AV
680 struct recv_desc_bufs *dlist, *dlist_phys;
681 int i;
682 unsigned long ctl;
683
684 dlist = lp->dlist;
685 dlist_phys = lp->dlist_phys;
686
687 for (i = 0; i < MAX_RX_DESCR; i++) {
688 dlist->descriptors[i].addr = (unsigned int) &dlist_phys->recv_buf[i][0];
689 dlist->descriptors[i].size = 0;
690 }
691
692 /* Set the Wrap bit on the last descriptor */
693 dlist->descriptors[i-1].addr |= EMAC_DESC_WRAP;
694
695 /* Reset buffer index */
696 lp->rxBuffIndex = 0;
697
698 /* Program address of descriptor list in Rx Buffer Queue register */
699 at91_emac_write(AT91_EMAC_RBQP, (unsigned long) dlist_phys);
700
701 /* Enable Receive and Transmit */
702 ctl = at91_emac_read(AT91_EMAC_CTL);
703 at91_emac_write(AT91_EMAC_CTL, ctl | AT91_EMAC_RE | AT91_EMAC_TE);
704}
705
706/*
707 * Open the ethernet interface
708 */
709static int at91ether_open(struct net_device *dev)
710{
c57ee096 711 struct at91_private *lp = netdev_priv(dev);
d4b7780e
AV
712 unsigned long ctl;
713
427d269f
AV
714 if (!is_valid_ether_addr(dev->dev_addr))
715 return -EADDRNOTAVAIL;
d4b7780e 716
427d269f 717 clk_enable(lp->ether_clk); /* Re-enable Peripheral clock */
d4b7780e
AV
718
719 /* Clear internal statistics */
720 ctl = at91_emac_read(AT91_EMAC_CTL);
721 at91_emac_write(AT91_EMAC_CTL, ctl | AT91_EMAC_CSR);
722
723 /* Update the MAC address (incase user has changed it) */
724 update_mac_address(dev);
725
726 /* Enable PHY interrupt */
727 enable_phyirq(dev);
728
729 /* Enable MAC interrupts */
730 at91_emac_write(AT91_EMAC_IER, AT91_EMAC_RCOM | AT91_EMAC_RBNA
731 | AT91_EMAC_TUND | AT91_EMAC_RTRY | AT91_EMAC_TCOM
732 | AT91_EMAC_ROVR | AT91_EMAC_ABT);
733
734 /* Determine current link speed */
735 spin_lock_irq(&lp->lock);
736 enable_mdi();
775637df 737 update_linkspeed(dev, 0);
d4b7780e
AV
738 disable_mdi();
739 spin_unlock_irq(&lp->lock);
740
741 at91ether_start(dev);
742 netif_start_queue(dev);
743 return 0;
744}
745
746/*
747 * Close the interface
748 */
749static int at91ether_close(struct net_device *dev)
750{
c57ee096 751 struct at91_private *lp = netdev_priv(dev);
d4b7780e
AV
752 unsigned long ctl;
753
754 /* Disable Receiver and Transmitter */
755 ctl = at91_emac_read(AT91_EMAC_CTL);
756 at91_emac_write(AT91_EMAC_CTL, ctl & ~(AT91_EMAC_TE | AT91_EMAC_RE));
757
758 /* Disable PHY interrupt */
759 disable_phyirq(dev);
760
761 /* Disable MAC interrupts */
762 at91_emac_write(AT91_EMAC_IDR, AT91_EMAC_RCOM | AT91_EMAC_RBNA
763 | AT91_EMAC_TUND | AT91_EMAC_RTRY | AT91_EMAC_TCOM
764 | AT91_EMAC_ROVR | AT91_EMAC_ABT);
765
766 netif_stop_queue(dev);
767
427d269f 768 clk_disable(lp->ether_clk); /* Disable Peripheral clock */
d4b7780e
AV
769
770 return 0;
771}
772
773/*
774 * Transmit packet.
775 */
776static int at91ether_tx(struct sk_buff *skb, struct net_device *dev)
777{
c57ee096 778 struct at91_private *lp = netdev_priv(dev);
d4b7780e
AV
779
780 if (at91_emac_read(AT91_EMAC_TSR) & AT91_EMAC_TSR_BNQ) {
781 netif_stop_queue(dev);
782
783 /* Store packet information (to free when Tx completed) */
784 lp->skb = skb;
785 lp->skb_length = skb->len;
786 lp->skb_physaddr = dma_map_single(NULL, skb->data, skb->len, DMA_TO_DEVICE);
787 lp->stats.tx_bytes += skb->len;
788
789 /* Set address of the data in the Transmit Address register */
790 at91_emac_write(AT91_EMAC_TAR, lp->skb_physaddr);
791 /* Set length of the packet in the Transmit Control register */
792 at91_emac_write(AT91_EMAC_TCR, skb->len);
793
794 dev->trans_start = jiffies;
795 } else {
796 printk(KERN_ERR "at91_ether.c: at91ether_tx() called, but device is busy!\n");
797 return 1; /* if we return anything but zero, dev.c:1055 calls kfree_skb(skb)
798 on this skb, he also reports -ENETDOWN and printk's, so either
799 we free and return(0) or don't free and return 1 */
800 }
801
802 return 0;
803}
804
805/*
806 * Update the current statistics from the internal statistics registers.
807 */
808static struct net_device_stats *at91ether_stats(struct net_device *dev)
809{
c57ee096 810 struct at91_private *lp = netdev_priv(dev);
d4b7780e
AV
811 int ale, lenerr, seqe, lcol, ecol;
812
813 if (netif_running(dev)) {
814 lp->stats.rx_packets += at91_emac_read(AT91_EMAC_OK); /* Good frames received */
815 ale = at91_emac_read(AT91_EMAC_ALE);
816 lp->stats.rx_frame_errors += ale; /* Alignment errors */
817 lenerr = at91_emac_read(AT91_EMAC_ELR) + at91_emac_read(AT91_EMAC_USF);
818 lp->stats.rx_length_errors += lenerr; /* Excessive Length or Undersize Frame error */
819 seqe = at91_emac_read(AT91_EMAC_SEQE);
820 lp->stats.rx_crc_errors += seqe; /* CRC error */
821 lp->stats.rx_fifo_errors += at91_emac_read(AT91_EMAC_DRFC); /* Receive buffer not available */
822 lp->stats.rx_errors += (ale + lenerr + seqe
823 + at91_emac_read(AT91_EMAC_CDE) + at91_emac_read(AT91_EMAC_RJB));
824
825 lp->stats.tx_packets += at91_emac_read(AT91_EMAC_FRA); /* Frames successfully transmitted */
826 lp->stats.tx_fifo_errors += at91_emac_read(AT91_EMAC_TUE); /* Transmit FIFO underruns */
827 lp->stats.tx_carrier_errors += at91_emac_read(AT91_EMAC_CSE); /* Carrier Sense errors */
828 lp->stats.tx_heartbeat_errors += at91_emac_read(AT91_EMAC_SQEE);/* Heartbeat error */
829
830 lcol = at91_emac_read(AT91_EMAC_LCOL);
831 ecol = at91_emac_read(AT91_EMAC_ECOL);
832 lp->stats.tx_window_errors += lcol; /* Late collisions */
833 lp->stats.tx_aborted_errors += ecol; /* 16 collisions */
834
835 lp->stats.collisions += (at91_emac_read(AT91_EMAC_SCOL) + at91_emac_read(AT91_EMAC_MCOL) + lcol + ecol);
836 }
837 return &lp->stats;
838}
839
840/*
841 * Extract received frame from buffer descriptors and sent to upper layers.
842 * (Called from interrupt context)
843 */
844static void at91ether_rx(struct net_device *dev)
845{
c57ee096 846 struct at91_private *lp = netdev_priv(dev);
d4b7780e
AV
847 struct recv_desc_bufs *dlist;
848 unsigned char *p_recv;
849 struct sk_buff *skb;
850 unsigned int pktlen;
851
852 dlist = lp->dlist;
853 while (dlist->descriptors[lp->rxBuffIndex].addr & EMAC_DESC_DONE) {
854 p_recv = dlist->recv_buf[lp->rxBuffIndex];
855 pktlen = dlist->descriptors[lp->rxBuffIndex].size & 0x7ff; /* Length of frame including FCS */
856 skb = alloc_skb(pktlen + 2, GFP_ATOMIC);
857 if (skb != NULL) {
858 skb_reserve(skb, 2);
859 memcpy(skb_put(skb, pktlen), p_recv, pktlen);
860
861 skb->dev = dev;
862 skb->protocol = eth_type_trans(skb, dev);
863 skb->len = pktlen;
864 dev->last_rx = jiffies;
865 lp->stats.rx_bytes += pktlen;
866 netif_rx(skb);
867 }
868 else {
869 lp->stats.rx_dropped += 1;
870 printk(KERN_NOTICE "%s: Memory squeeze, dropping packet.\n", dev->name);
871 }
872
873 if (dlist->descriptors[lp->rxBuffIndex].size & EMAC_MULTICAST)
874 lp->stats.multicast++;
875
876 dlist->descriptors[lp->rxBuffIndex].addr &= ~EMAC_DESC_DONE; /* reset ownership bit */
877 if (lp->rxBuffIndex == MAX_RX_DESCR-1) /* wrap after last buffer */
878 lp->rxBuffIndex = 0;
879 else
880 lp->rxBuffIndex++;
881 }
882}
883
884/*
885 * MAC interrupt handler
886 */
7d12e780 887static irqreturn_t at91ether_interrupt(int irq, void *dev_id)
d4b7780e
AV
888{
889 struct net_device *dev = (struct net_device *) dev_id;
c57ee096 890 struct at91_private *lp = netdev_priv(dev);
d4b7780e
AV
891 unsigned long intstatus, ctl;
892
893 /* MAC Interrupt Status register indicates what interrupts are pending.
894 It is automatically cleared once read. */
895 intstatus = at91_emac_read(AT91_EMAC_ISR);
896
897 if (intstatus & AT91_EMAC_RCOM) /* Receive complete */
898 at91ether_rx(dev);
899
427d269f 900 if (intstatus & AT91_EMAC_TCOM) { /* Transmit complete */
d4b7780e
AV
901 /* The TCOM bit is set even if the transmission failed. */
902 if (intstatus & (AT91_EMAC_TUND | AT91_EMAC_RTRY))
903 lp->stats.tx_errors += 1;
904
905 if (lp->skb) {
906 dev_kfree_skb_irq(lp->skb);
907 lp->skb = NULL;
908 dma_unmap_single(NULL, lp->skb_physaddr, lp->skb_length, DMA_TO_DEVICE);
909 }
910 netif_wake_queue(dev);
911 }
912
913 /* Work-around for Errata #11 */
914 if (intstatus & AT91_EMAC_RBNA) {
915 ctl = at91_emac_read(AT91_EMAC_CTL);
916 at91_emac_write(AT91_EMAC_CTL, ctl & ~AT91_EMAC_RE);
917 at91_emac_write(AT91_EMAC_CTL, ctl | AT91_EMAC_RE);
918 }
919
920 if (intstatus & AT91_EMAC_ROVR)
921 printk("%s: ROVR error\n", dev->name);
922
923 return IRQ_HANDLED;
924}
925
926/*
927 * Initialize the ethernet interface
928 */
427d269f
AV
929static int __init at91ether_setup(unsigned long phy_type, unsigned short phy_address,
930 struct platform_device *pdev, struct clk *ether_clk)
d4b7780e
AV
931{
932 struct at91_eth_data *board_data = pdev->dev.platform_data;
933 struct net_device *dev;
934 struct at91_private *lp;
935 unsigned int val;
936 int res;
937
d4b7780e
AV
938 dev = alloc_etherdev(sizeof(struct at91_private));
939 if (!dev)
940 return -ENOMEM;
941
942 dev->base_addr = AT91_VA_BASE_EMAC;
72729910 943 dev->irq = AT91RM9200_ID_EMAC;
d4b7780e
AV
944 SET_MODULE_OWNER(dev);
945
946 /* Install the interrupt handler */
947 if (request_irq(dev->irq, at91ether_interrupt, 0, dev->name, dev)) {
948 free_netdev(dev);
949 return -EBUSY;
950 }
951
952 /* Allocate memory for DMA Receive descriptors */
c57ee096 953 lp = netdev_priv(dev);
d4b7780e
AV
954 lp->dlist = (struct recv_desc_bufs *) dma_alloc_coherent(NULL, sizeof(struct recv_desc_bufs), (dma_addr_t *) &lp->dlist_phys, GFP_KERNEL);
955 if (lp->dlist == NULL) {
956 free_irq(dev->irq, dev);
957 free_netdev(dev);
958 return -ENOMEM;
959 }
960 lp->board_data = *board_data;
427d269f 961 lp->ether_clk = ether_clk;
d4b7780e
AV
962 platform_set_drvdata(pdev, dev);
963
964 spin_lock_init(&lp->lock);
965
966 ether_setup(dev);
967 dev->open = at91ether_open;
968 dev->stop = at91ether_close;
969 dev->hard_start_xmit = at91ether_tx;
970 dev->get_stats = at91ether_stats;
971 dev->set_multicast_list = at91ether_set_rx_mode;
972 dev->set_mac_address = set_mac_address;
973 dev->ethtool_ops = &at91ether_ethtool_ops;
ca5585ed 974 dev->do_ioctl = at91ether_ioctl;
d4b7780e
AV
975
976 SET_NETDEV_DEV(dev, &pdev->dev);
977
978 get_mac_address(dev); /* Get ethernet address and store it in dev->dev_addr */
979 update_mac_address(dev); /* Program ethernet address into MAC */
980
981 at91_emac_write(AT91_EMAC_CTL, 0);
982
983 if (lp->board_data.is_rmii)
984 at91_emac_write(AT91_EMAC_CFG, AT91_EMAC_CLK_DIV32 | AT91_EMAC_BIG | AT91_EMAC_RMII);
985 else
986 at91_emac_write(AT91_EMAC_CFG, AT91_EMAC_CLK_DIV32 | AT91_EMAC_BIG);
987
988 /* Perform PHY-specific initialization */
989 spin_lock_irq(&lp->lock);
990 enable_mdi();
991 if ((phy_type == MII_DM9161_ID) || (lp->phy_type == MII_DM9161A_ID)) {
992 read_phy(phy_address, MII_DSCR_REG, &val);
993 if ((val & (1 << 10)) == 0) /* DSCR bit 10 is 0 -- fiber mode */
994 lp->phy_media = PORT_FIBRE;
995 } else if (machine_is_csb337()) {
996 /* mix link activity status into LED2 link state */
997 write_phy(phy_address, MII_LEDCTRL_REG, 0x0d22);
998 }
999 disable_mdi();
1000 spin_unlock_irq(&lp->lock);
1001
1002 lp->mii.dev = dev; /* Support for ethtool */
1003 lp->mii.mdio_read = mdio_read;
1004 lp->mii.mdio_write = mdio_write;
ca5585ed
AV
1005 lp->mii.phy_id = phy_address;
1006 lp->mii.phy_id_mask = 0x1f;
1007 lp->mii.reg_num_mask = 0x1f;
d4b7780e
AV
1008
1009 lp->phy_type = phy_type; /* Type of PHY connected */
1010 lp->phy_address = phy_address; /* MDI address of PHY */
1011
1012 /* Register the network interface */
1013 res = register_netdev(dev);
1014 if (res) {
1015 free_irq(dev->irq, dev);
1016 free_netdev(dev);
1017 dma_free_coherent(NULL, sizeof(struct recv_desc_bufs), lp->dlist, (dma_addr_t)lp->dlist_phys);
1018 return res;
1019 }
d4b7780e
AV
1020
1021 /* Determine current link speed */
1022 spin_lock_irq(&lp->lock);
1023 enable_mdi();
775637df 1024 update_linkspeed(dev, 0);
d4b7780e
AV
1025 disable_mdi();
1026 spin_unlock_irq(&lp->lock);
1027 netif_carrier_off(dev); /* will be enabled in open() */
1028
775637df
AV
1029 /* If board has no PHY IRQ, use a timer to poll the PHY */
1030 if (!lp->board_data.phy_irq_pin) {
cf42553a
AV
1031 init_timer(&lp->check_timer);
1032 lp->check_timer.data = (unsigned long)dev;
1033 lp->check_timer.function = at91ether_check_link;
775637df
AV
1034 }
1035
d4b7780e
AV
1036 /* Display ethernet banner */
1037 printk(KERN_INFO "%s: AT91 ethernet at 0x%08x int=%d %s%s (%02x:%02x:%02x:%02x:%02x:%02x)\n",
1038 dev->name, (uint) dev->base_addr, dev->irq,
1039 at91_emac_read(AT91_EMAC_CFG) & AT91_EMAC_SPD ? "100-" : "10-",
1040 at91_emac_read(AT91_EMAC_CFG) & AT91_EMAC_FD ? "FullDuplex" : "HalfDuplex",
1041 dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
1042 dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
1043 if ((phy_type == MII_DM9161_ID) || (lp->phy_type == MII_DM9161A_ID))
427d269f 1044 printk(KERN_INFO "%s: Davicom 9161 PHY %s\n", dev->name, (lp->phy_media == PORT_FIBRE) ? "(Fiber)" : "(Copper)");
d4b7780e
AV
1045 else if (phy_type == MII_LXT971A_ID)
1046 printk(KERN_INFO "%s: Intel LXT971A PHY\n", dev->name);
1047 else if (phy_type == MII_RTL8201_ID)
1048 printk(KERN_INFO "%s: Realtek RTL8201(B)L PHY\n", dev->name);
1049 else if (phy_type == MII_BCM5221_ID)
1050 printk(KERN_INFO "%s: Broadcom BCM5221 PHY\n", dev->name);
1051 else if (phy_type == MII_DP83847_ID)
1052 printk(KERN_INFO "%s: National Semiconductor DP83847 PHY\n", dev->name);
1053 else if (phy_type == MII_AC101L_ID)
1054 printk(KERN_INFO "%s: Altima AC101L PHY\n", dev->name);
1055 else if (phy_type == MII_KS8721_ID)
1056 printk(KERN_INFO "%s: Micrel KS8721 PHY\n", dev->name);
1057
1058 return 0;
1059}
1060
1061/*
1062 * Detect MAC and PHY and perform initialization
1063 */
1064static int __init at91ether_probe(struct platform_device *pdev)
1065{
1066 unsigned int phyid1, phyid2;
1067 int detected = -1;
1068 unsigned long phy_id;
1069 unsigned short phy_address = 0;
427d269f 1070 struct clk *ether_clk;
d4b7780e
AV
1071
1072 ether_clk = clk_get(&pdev->dev, "ether_clk");
427d269f 1073 if (IS_ERR(ether_clk)) {
d4b7780e
AV
1074 printk(KERN_ERR "at91_ether: no clock defined\n");
1075 return -ENODEV;
1076 }
1077 clk_enable(ether_clk); /* Enable Peripheral clock */
1078
1079 while ((detected != 0) && (phy_address < 32)) {
1080 /* Read the PHY ID registers */
1081 enable_mdi();
1082 read_phy(phy_address, MII_PHYSID1, &phyid1);
1083 read_phy(phy_address, MII_PHYSID2, &phyid2);
1084 disable_mdi();
1085
1086 phy_id = (phyid1 << 16) | (phyid2 & 0xfff0);
1087 switch (phy_id) {
1088 case MII_DM9161_ID: /* Davicom 9161: PHY_ID1 = 0x181, PHY_ID2 = B881 */
1089 case MII_DM9161A_ID: /* Davicom 9161A: PHY_ID1 = 0x181, PHY_ID2 = B8A0 */
1090 case MII_LXT971A_ID: /* Intel LXT971A: PHY_ID1 = 0x13, PHY_ID2 = 78E0 */
1091 case MII_RTL8201_ID: /* Realtek RTL8201: PHY_ID1 = 0, PHY_ID2 = 0x8201 */
1092 case MII_BCM5221_ID: /* Broadcom BCM5221: PHY_ID1 = 0x40, PHY_ID2 = 0x61e0 */
1093 case MII_DP83847_ID: /* National Semiconductor DP83847: */
1094 case MII_AC101L_ID: /* Altima AC101L: PHY_ID1 = 0x22, PHY_ID2 = 0x5520 */
1095 case MII_KS8721_ID: /* Micrel KS8721: PHY_ID1 = 0x22, PHY_ID2 = 0x1610 */
427d269f 1096 detected = at91ether_setup(phy_id, phy_address, pdev, ether_clk);
d4b7780e
AV
1097 break;
1098 }
1099
1100 phy_address++;
1101 }
1102
1103 clk_disable(ether_clk); /* Disable Peripheral clock */
1104
1105 return detected;
1106}
1107
1108static int __devexit at91ether_remove(struct platform_device *pdev)
1109{
c57ee096
AV
1110 struct net_device *dev = platform_get_drvdata(pdev);
1111 struct at91_private *lp = netdev_priv(dev);
d4b7780e 1112
c57ee096
AV
1113 unregister_netdev(dev);
1114 free_irq(dev->irq, dev);
d4b7780e 1115 dma_free_coherent(NULL, sizeof(struct recv_desc_bufs), lp->dlist, (dma_addr_t)lp->dlist_phys);
427d269f 1116 clk_put(lp->ether_clk);
d4b7780e 1117
c57ee096
AV
1118 platform_set_drvdata(pdev, NULL);
1119 free_netdev(dev);
d4b7780e
AV
1120 return 0;
1121}
1122
00e5edcb
AV
1123#ifdef CONFIG_PM
1124
1125static int at91ether_suspend(struct platform_device *pdev, pm_message_t mesg)
1126{
00e5edcb 1127 struct net_device *net_dev = platform_get_drvdata(pdev);
c57ee096 1128 struct at91_private *lp = netdev_priv(net_dev);
00e5edcb
AV
1129 int phy_irq = lp->board_data.phy_irq_pin;
1130
1131 if (netif_running(net_dev)) {
1132 if (phy_irq)
1133 disable_irq(phy_irq);
1134
1135 netif_stop_queue(net_dev);
1136 netif_device_detach(net_dev);
1137
1138 clk_disable(lp->ether_clk);
1139 }
1140 return 0;
1141}
1142
1143static int at91ether_resume(struct platform_device *pdev)
1144{
00e5edcb 1145 struct net_device *net_dev = platform_get_drvdata(pdev);
c57ee096 1146 struct at91_private *lp = netdev_priv(net_dev);
00e5edcb
AV
1147 int phy_irq = lp->board_data.phy_irq_pin;
1148
1149 if (netif_running(net_dev)) {
1150 clk_enable(lp->ether_clk);
1151
1152 netif_device_attach(net_dev);
1153 netif_start_queue(net_dev);
1154
1155 if (phy_irq)
1156 enable_irq(phy_irq);
1157 }
1158 return 0;
1159}
1160
1161#else
1162#define at91ether_suspend NULL
1163#define at91ether_resume NULL
1164#endif
1165
d4b7780e
AV
1166static struct platform_driver at91ether_driver = {
1167 .probe = at91ether_probe,
1168 .remove = __devexit_p(at91ether_remove),
00e5edcb
AV
1169 .suspend = at91ether_suspend,
1170 .resume = at91ether_resume,
d4b7780e
AV
1171 .driver = {
1172 .name = DRV_NAME,
1173 .owner = THIS_MODULE,
1174 },
1175};
1176
1177static int __init at91ether_init(void)
1178{
1179 return platform_driver_register(&at91ether_driver);
1180}
1181
1182static void __exit at91ether_exit(void)
1183{
1184 platform_driver_unregister(&at91ether_driver);
1185}
1186
1187module_init(at91ether_init)
1188module_exit(at91ether_exit)
1189
1190MODULE_LICENSE("GPL");
1191MODULE_DESCRIPTION("AT91RM9200 EMAC Ethernet driver");
1192MODULE_AUTHOR("Andrew Victor");
This page took 0.149338 seconds and 5 git commands to generate.