Commit | Line | Data |
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1d22e05d LB |
1 | /* |
2 | * EP93xx ethernet network device driver | |
3 | * Copyright (C) 2006 Lennert Buytenhek <buytenh@wantstofly.org> | |
4 | * Dedicated to Marija Kulikova. | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License as published by | |
8 | * the Free Software Foundation; either version 2 of the License, or | |
9 | * (at your option) any later version. | |
10 | */ | |
11 | ||
1d22e05d LB |
12 | #include <linux/dma-mapping.h> |
13 | #include <linux/module.h> | |
14 | #include <linux/kernel.h> | |
15 | #include <linux/netdevice.h> | |
16 | #include <linux/mii.h> | |
17 | #include <linux/etherdevice.h> | |
18 | #include <linux/ethtool.h> | |
19 | #include <linux/init.h> | |
20 | #include <linux/moduleparam.h> | |
21 | #include <linux/platform_device.h> | |
22 | #include <linux/delay.h> | |
a09e64fb RK |
23 | #include <mach/ep93xx-regs.h> |
24 | #include <mach/platform.h> | |
1d22e05d LB |
25 | #include <asm/io.h> |
26 | ||
27 | #define DRV_MODULE_NAME "ep93xx-eth" | |
28 | #define DRV_MODULE_VERSION "0.1" | |
29 | ||
30 | #define RX_QUEUE_ENTRIES 64 | |
31 | #define TX_QUEUE_ENTRIES 8 | |
32 | ||
33 | #define MAX_PKT_SIZE 2044 | |
34 | #define PKT_BUF_SIZE 2048 | |
35 | ||
36 | #define REG_RXCTL 0x0000 | |
37 | #define REG_RXCTL_DEFAULT 0x00073800 | |
38 | #define REG_TXCTL 0x0004 | |
39 | #define REG_TXCTL_ENABLE 0x00000001 | |
40 | #define REG_MIICMD 0x0010 | |
41 | #define REG_MIICMD_READ 0x00008000 | |
42 | #define REG_MIICMD_WRITE 0x00004000 | |
43 | #define REG_MIIDATA 0x0014 | |
44 | #define REG_MIISTS 0x0018 | |
45 | #define REG_MIISTS_BUSY 0x00000001 | |
46 | #define REG_SELFCTL 0x0020 | |
47 | #define REG_SELFCTL_RESET 0x00000001 | |
48 | #define REG_INTEN 0x0024 | |
49 | #define REG_INTEN_TX 0x00000008 | |
50 | #define REG_INTEN_RX 0x00000007 | |
51 | #define REG_INTSTSP 0x0028 | |
52 | #define REG_INTSTS_TX 0x00000008 | |
53 | #define REG_INTSTS_RX 0x00000004 | |
54 | #define REG_INTSTSC 0x002c | |
55 | #define REG_AFP 0x004c | |
56 | #define REG_INDAD0 0x0050 | |
57 | #define REG_INDAD1 0x0051 | |
58 | #define REG_INDAD2 0x0052 | |
59 | #define REG_INDAD3 0x0053 | |
60 | #define REG_INDAD4 0x0054 | |
61 | #define REG_INDAD5 0x0055 | |
62 | #define REG_GIINTMSK 0x0064 | |
63 | #define REG_GIINTMSK_ENABLE 0x00008000 | |
64 | #define REG_BMCTL 0x0080 | |
65 | #define REG_BMCTL_ENABLE_TX 0x00000100 | |
66 | #define REG_BMCTL_ENABLE_RX 0x00000001 | |
67 | #define REG_BMSTS 0x0084 | |
68 | #define REG_BMSTS_RX_ACTIVE 0x00000008 | |
69 | #define REG_RXDQBADD 0x0090 | |
70 | #define REG_RXDQBLEN 0x0094 | |
71 | #define REG_RXDCURADD 0x0098 | |
72 | #define REG_RXDENQ 0x009c | |
73 | #define REG_RXSTSQBADD 0x00a0 | |
74 | #define REG_RXSTSQBLEN 0x00a4 | |
75 | #define REG_RXSTSQCURADD 0x00a8 | |
76 | #define REG_RXSTSENQ 0x00ac | |
77 | #define REG_TXDQBADD 0x00b0 | |
78 | #define REG_TXDQBLEN 0x00b4 | |
79 | #define REG_TXDQCURADD 0x00b8 | |
80 | #define REG_TXDENQ 0x00bc | |
81 | #define REG_TXSTSQBADD 0x00c0 | |
82 | #define REG_TXSTSQBLEN 0x00c4 | |
83 | #define REG_TXSTSQCURADD 0x00c8 | |
84 | #define REG_MAXFRMLEN 0x00e8 | |
85 | ||
86 | struct ep93xx_rdesc | |
87 | { | |
88 | u32 buf_addr; | |
89 | u32 rdesc1; | |
90 | }; | |
91 | ||
92 | #define RDESC1_NSOF 0x80000000 | |
93 | #define RDESC1_BUFFER_INDEX 0x7fff0000 | |
94 | #define RDESC1_BUFFER_LENGTH 0x0000ffff | |
95 | ||
96 | struct ep93xx_rstat | |
97 | { | |
98 | u32 rstat0; | |
99 | u32 rstat1; | |
100 | }; | |
101 | ||
102 | #define RSTAT0_RFP 0x80000000 | |
103 | #define RSTAT0_RWE 0x40000000 | |
104 | #define RSTAT0_EOF 0x20000000 | |
105 | #define RSTAT0_EOB 0x10000000 | |
106 | #define RSTAT0_AM 0x00c00000 | |
107 | #define RSTAT0_RX_ERR 0x00200000 | |
108 | #define RSTAT0_OE 0x00100000 | |
109 | #define RSTAT0_FE 0x00080000 | |
110 | #define RSTAT0_RUNT 0x00040000 | |
111 | #define RSTAT0_EDATA 0x00020000 | |
112 | #define RSTAT0_CRCE 0x00010000 | |
113 | #define RSTAT0_CRCI 0x00008000 | |
114 | #define RSTAT0_HTI 0x00003f00 | |
115 | #define RSTAT1_RFP 0x80000000 | |
116 | #define RSTAT1_BUFFER_INDEX 0x7fff0000 | |
117 | #define RSTAT1_FRAME_LENGTH 0x0000ffff | |
118 | ||
119 | struct ep93xx_tdesc | |
120 | { | |
121 | u32 buf_addr; | |
122 | u32 tdesc1; | |
123 | }; | |
124 | ||
125 | #define TDESC1_EOF 0x80000000 | |
126 | #define TDESC1_BUFFER_INDEX 0x7fff0000 | |
127 | #define TDESC1_BUFFER_ABORT 0x00008000 | |
128 | #define TDESC1_BUFFER_LENGTH 0x00000fff | |
129 | ||
130 | struct ep93xx_tstat | |
131 | { | |
132 | u32 tstat0; | |
133 | }; | |
134 | ||
135 | #define TSTAT0_TXFP 0x80000000 | |
136 | #define TSTAT0_TXWE 0x40000000 | |
137 | #define TSTAT0_FA 0x20000000 | |
138 | #define TSTAT0_LCRS 0x10000000 | |
139 | #define TSTAT0_OW 0x04000000 | |
140 | #define TSTAT0_TXU 0x02000000 | |
141 | #define TSTAT0_ECOLL 0x01000000 | |
142 | #define TSTAT0_NCOLL 0x001f0000 | |
143 | #define TSTAT0_BUFFER_INDEX 0x00007fff | |
144 | ||
145 | struct ep93xx_descs | |
146 | { | |
147 | struct ep93xx_rdesc rdesc[RX_QUEUE_ENTRIES]; | |
148 | struct ep93xx_tdesc tdesc[TX_QUEUE_ENTRIES]; | |
149 | struct ep93xx_rstat rstat[RX_QUEUE_ENTRIES]; | |
150 | struct ep93xx_tstat tstat[TX_QUEUE_ENTRIES]; | |
151 | }; | |
152 | ||
153 | struct ep93xx_priv | |
154 | { | |
155 | struct resource *res; | |
156 | void *base_addr; | |
157 | int irq; | |
158 | ||
159 | struct ep93xx_descs *descs; | |
160 | dma_addr_t descs_dma_addr; | |
161 | ||
162 | void *rx_buf[RX_QUEUE_ENTRIES]; | |
163 | void *tx_buf[TX_QUEUE_ENTRIES]; | |
164 | ||
165 | spinlock_t rx_lock; | |
166 | unsigned int rx_pointer; | |
167 | unsigned int tx_clean_pointer; | |
168 | unsigned int tx_pointer; | |
169 | spinlock_t tx_pending_lock; | |
170 | unsigned int tx_pending; | |
171 | ||
bea3348e SH |
172 | struct net_device *dev; |
173 | struct napi_struct napi; | |
174 | ||
1d22e05d LB |
175 | struct net_device_stats stats; |
176 | ||
177 | struct mii_if_info mii; | |
178 | u8 mdc_divisor; | |
179 | }; | |
180 | ||
181 | #define rdb(ep, off) __raw_readb((ep)->base_addr + (off)) | |
182 | #define rdw(ep, off) __raw_readw((ep)->base_addr + (off)) | |
183 | #define rdl(ep, off) __raw_readl((ep)->base_addr + (off)) | |
184 | #define wrb(ep, off, val) __raw_writeb((val), (ep)->base_addr + (off)) | |
185 | #define wrw(ep, off, val) __raw_writew((val), (ep)->base_addr + (off)) | |
186 | #define wrl(ep, off, val) __raw_writel((val), (ep)->base_addr + (off)) | |
187 | ||
188 | static int ep93xx_mdio_read(struct net_device *dev, int phy_id, int reg); | |
189 | ||
190 | static struct net_device_stats *ep93xx_get_stats(struct net_device *dev) | |
191 | { | |
192 | struct ep93xx_priv *ep = netdev_priv(dev); | |
193 | return &(ep->stats); | |
194 | } | |
195 | ||
bea3348e | 196 | static int ep93xx_rx(struct net_device *dev, int processed, int budget) |
1d22e05d LB |
197 | { |
198 | struct ep93xx_priv *ep = netdev_priv(dev); | |
1d22e05d | 199 | |
bea3348e | 200 | while (processed < budget) { |
1d22e05d LB |
201 | int entry; |
202 | struct ep93xx_rstat *rstat; | |
203 | u32 rstat0; | |
204 | u32 rstat1; | |
205 | int length; | |
206 | struct sk_buff *skb; | |
207 | ||
208 | entry = ep->rx_pointer; | |
209 | rstat = ep->descs->rstat + entry; | |
2d38caba LB |
210 | |
211 | rstat0 = rstat->rstat0; | |
212 | rstat1 = rstat->rstat1; | |
bea3348e | 213 | if (!(rstat0 & RSTAT0_RFP) || !(rstat1 & RSTAT1_RFP)) |
1d22e05d | 214 | break; |
1d22e05d | 215 | |
1d22e05d LB |
216 | rstat->rstat0 = 0; |
217 | rstat->rstat1 = 0; | |
218 | ||
1d22e05d LB |
219 | if (!(rstat0 & RSTAT0_EOF)) |
220 | printk(KERN_CRIT "ep93xx_rx: not end-of-frame " | |
221 | " %.8x %.8x\n", rstat0, rstat1); | |
222 | if (!(rstat0 & RSTAT0_EOB)) | |
223 | printk(KERN_CRIT "ep93xx_rx: not end-of-buffer " | |
224 | " %.8x %.8x\n", rstat0, rstat1); | |
1d22e05d LB |
225 | if ((rstat1 & RSTAT1_BUFFER_INDEX) >> 16 != entry) |
226 | printk(KERN_CRIT "ep93xx_rx: entry mismatch " | |
227 | " %.8x %.8x\n", rstat0, rstat1); | |
228 | ||
229 | if (!(rstat0 & RSTAT0_RWE)) { | |
1d22e05d LB |
230 | ep->stats.rx_errors++; |
231 | if (rstat0 & RSTAT0_OE) | |
232 | ep->stats.rx_fifo_errors++; | |
233 | if (rstat0 & RSTAT0_FE) | |
234 | ep->stats.rx_frame_errors++; | |
235 | if (rstat0 & (RSTAT0_RUNT | RSTAT0_EDATA)) | |
236 | ep->stats.rx_length_errors++; | |
237 | if (rstat0 & RSTAT0_CRCE) | |
238 | ep->stats.rx_crc_errors++; | |
239 | goto err; | |
240 | } | |
241 | ||
242 | length = rstat1 & RSTAT1_FRAME_LENGTH; | |
243 | if (length > MAX_PKT_SIZE) { | |
244 | printk(KERN_NOTICE "ep93xx_rx: invalid length " | |
245 | " %.8x %.8x\n", rstat0, rstat1); | |
246 | goto err; | |
247 | } | |
248 | ||
249 | /* Strip FCS. */ | |
250 | if (rstat0 & RSTAT0_CRCI) | |
251 | length -= 4; | |
252 | ||
253 | skb = dev_alloc_skb(length + 2); | |
254 | if (likely(skb != NULL)) { | |
1d22e05d LB |
255 | skb_reserve(skb, 2); |
256 | dma_sync_single(NULL, ep->descs->rdesc[entry].buf_addr, | |
257 | length, DMA_FROM_DEVICE); | |
8c7b7faa | 258 | skb_copy_to_linear_data(skb, ep->rx_buf[entry], length); |
1d22e05d LB |
259 | skb_put(skb, length); |
260 | skb->protocol = eth_type_trans(skb, dev); | |
261 | ||
1d22e05d LB |
262 | netif_receive_skb(skb); |
263 | ||
264 | ep->stats.rx_packets++; | |
265 | ep->stats.rx_bytes += length; | |
266 | } else { | |
267 | ep->stats.rx_dropped++; | |
268 | } | |
269 | ||
270 | err: | |
271 | ep->rx_pointer = (entry + 1) & (RX_QUEUE_ENTRIES - 1); | |
272 | processed++; | |
1d22e05d LB |
273 | } |
274 | ||
275 | if (processed) { | |
276 | wrw(ep, REG_RXDENQ, processed); | |
277 | wrw(ep, REG_RXSTSENQ, processed); | |
278 | } | |
279 | ||
bea3348e | 280 | return processed; |
1d22e05d LB |
281 | } |
282 | ||
283 | static int ep93xx_have_more_rx(struct ep93xx_priv *ep) | |
284 | { | |
2d38caba LB |
285 | struct ep93xx_rstat *rstat = ep->descs->rstat + ep->rx_pointer; |
286 | return !!((rstat->rstat0 & RSTAT0_RFP) && (rstat->rstat1 & RSTAT1_RFP)); | |
1d22e05d LB |
287 | } |
288 | ||
bea3348e | 289 | static int ep93xx_poll(struct napi_struct *napi, int budget) |
1d22e05d | 290 | { |
bea3348e SH |
291 | struct ep93xx_priv *ep = container_of(napi, struct ep93xx_priv, napi); |
292 | struct net_device *dev = ep->dev; | |
293 | int rx = 0; | |
1d22e05d LB |
294 | |
295 | poll_some_more: | |
bea3348e SH |
296 | rx = ep93xx_rx(dev, rx, budget); |
297 | if (rx < budget) { | |
298 | int more = 0; | |
299 | ||
300 | spin_lock_irq(&ep->rx_lock); | |
288379f0 | 301 | __napi_complete(napi); |
bea3348e SH |
302 | wrl(ep, REG_INTEN, REG_INTEN_TX | REG_INTEN_RX); |
303 | if (ep93xx_have_more_rx(ep)) { | |
304 | wrl(ep, REG_INTEN, REG_INTEN_TX); | |
305 | wrl(ep, REG_INTSTSP, REG_INTSTS_RX); | |
306 | more = 1; | |
307 | } | |
1d22e05d LB |
308 | spin_unlock_irq(&ep->rx_lock); |
309 | ||
288379f0 | 310 | if (more && napi_reschedule(napi)) |
1d22e05d | 311 | goto poll_some_more; |
1d22e05d | 312 | } |
1d22e05d | 313 | |
bea3348e | 314 | return rx; |
1d22e05d LB |
315 | } |
316 | ||
317 | static int ep93xx_xmit(struct sk_buff *skb, struct net_device *dev) | |
318 | { | |
319 | struct ep93xx_priv *ep = netdev_priv(dev); | |
320 | int entry; | |
321 | ||
79c356f4 | 322 | if (unlikely(skb->len > MAX_PKT_SIZE)) { |
1d22e05d LB |
323 | ep->stats.tx_dropped++; |
324 | dev_kfree_skb(skb); | |
325 | return NETDEV_TX_OK; | |
326 | } | |
327 | ||
328 | entry = ep->tx_pointer; | |
329 | ep->tx_pointer = (ep->tx_pointer + 1) & (TX_QUEUE_ENTRIES - 1); | |
330 | ||
331 | ep->descs->tdesc[entry].tdesc1 = | |
332 | TDESC1_EOF | (entry << 16) | (skb->len & 0xfff); | |
333 | skb_copy_and_csum_dev(skb, ep->tx_buf[entry]); | |
334 | dma_sync_single(NULL, ep->descs->tdesc[entry].buf_addr, | |
335 | skb->len, DMA_TO_DEVICE); | |
336 | dev_kfree_skb(skb); | |
337 | ||
338 | dev->trans_start = jiffies; | |
339 | ||
340 | spin_lock_irq(&ep->tx_pending_lock); | |
341 | ep->tx_pending++; | |
342 | if (ep->tx_pending == TX_QUEUE_ENTRIES) | |
343 | netif_stop_queue(dev); | |
344 | spin_unlock_irq(&ep->tx_pending_lock); | |
345 | ||
346 | wrl(ep, REG_TXDENQ, 1); | |
347 | ||
348 | return NETDEV_TX_OK; | |
349 | } | |
350 | ||
351 | static void ep93xx_tx_complete(struct net_device *dev) | |
352 | { | |
353 | struct ep93xx_priv *ep = netdev_priv(dev); | |
1d22e05d LB |
354 | int wake; |
355 | ||
1d22e05d LB |
356 | wake = 0; |
357 | ||
358 | spin_lock(&ep->tx_pending_lock); | |
359 | while (1) { | |
360 | int entry; | |
361 | struct ep93xx_tstat *tstat; | |
362 | u32 tstat0; | |
363 | ||
364 | entry = ep->tx_clean_pointer; | |
365 | tstat = ep->descs->tstat + entry; | |
1d22e05d LB |
366 | |
367 | tstat0 = tstat->tstat0; | |
2d38caba LB |
368 | if (!(tstat0 & TSTAT0_TXFP)) |
369 | break; | |
370 | ||
1d22e05d LB |
371 | tstat->tstat0 = 0; |
372 | ||
1d22e05d LB |
373 | if (tstat0 & TSTAT0_FA) |
374 | printk(KERN_CRIT "ep93xx_tx_complete: frame aborted " | |
375 | " %.8x\n", tstat0); | |
376 | if ((tstat0 & TSTAT0_BUFFER_INDEX) != entry) | |
377 | printk(KERN_CRIT "ep93xx_tx_complete: entry mismatch " | |
378 | " %.8x\n", tstat0); | |
379 | ||
380 | if (tstat0 & TSTAT0_TXWE) { | |
381 | int length = ep->descs->tdesc[entry].tdesc1 & 0xfff; | |
382 | ||
383 | ep->stats.tx_packets++; | |
384 | ep->stats.tx_bytes += length; | |
385 | } else { | |
386 | ep->stats.tx_errors++; | |
387 | } | |
388 | ||
389 | if (tstat0 & TSTAT0_OW) | |
390 | ep->stats.tx_window_errors++; | |
391 | if (tstat0 & TSTAT0_TXU) | |
392 | ep->stats.tx_fifo_errors++; | |
393 | ep->stats.collisions += (tstat0 >> 16) & 0x1f; | |
394 | ||
395 | ep->tx_clean_pointer = (entry + 1) & (TX_QUEUE_ENTRIES - 1); | |
396 | if (ep->tx_pending == TX_QUEUE_ENTRIES) | |
397 | wake = 1; | |
398 | ep->tx_pending--; | |
399 | } | |
400 | spin_unlock(&ep->tx_pending_lock); | |
401 | ||
402 | if (wake) | |
403 | netif_wake_queue(dev); | |
404 | } | |
405 | ||
7d12e780 | 406 | static irqreturn_t ep93xx_irq(int irq, void *dev_id) |
1d22e05d LB |
407 | { |
408 | struct net_device *dev = dev_id; | |
409 | struct ep93xx_priv *ep = netdev_priv(dev); | |
410 | u32 status; | |
411 | ||
412 | status = rdl(ep, REG_INTSTSC); | |
413 | if (status == 0) | |
414 | return IRQ_NONE; | |
415 | ||
416 | if (status & REG_INTSTS_RX) { | |
417 | spin_lock(&ep->rx_lock); | |
288379f0 | 418 | if (likely(napi_schedule_prep(&ep->napi))) { |
1d22e05d | 419 | wrl(ep, REG_INTEN, REG_INTEN_TX); |
288379f0 | 420 | __napi_schedule(&ep->napi); |
1d22e05d LB |
421 | } |
422 | spin_unlock(&ep->rx_lock); | |
423 | } | |
424 | ||
425 | if (status & REG_INTSTS_TX) | |
426 | ep93xx_tx_complete(dev); | |
427 | ||
428 | return IRQ_HANDLED; | |
429 | } | |
430 | ||
431 | static void ep93xx_free_buffers(struct ep93xx_priv *ep) | |
432 | { | |
433 | int i; | |
434 | ||
435 | for (i = 0; i < RX_QUEUE_ENTRIES; i += 2) { | |
436 | dma_addr_t d; | |
437 | ||
438 | d = ep->descs->rdesc[i].buf_addr; | |
439 | if (d) | |
440 | dma_unmap_single(NULL, d, PAGE_SIZE, DMA_FROM_DEVICE); | |
441 | ||
442 | if (ep->rx_buf[i] != NULL) | |
443 | free_page((unsigned long)ep->rx_buf[i]); | |
444 | } | |
445 | ||
446 | for (i = 0; i < TX_QUEUE_ENTRIES; i += 2) { | |
447 | dma_addr_t d; | |
448 | ||
449 | d = ep->descs->tdesc[i].buf_addr; | |
450 | if (d) | |
451 | dma_unmap_single(NULL, d, PAGE_SIZE, DMA_TO_DEVICE); | |
452 | ||
453 | if (ep->tx_buf[i] != NULL) | |
454 | free_page((unsigned long)ep->tx_buf[i]); | |
455 | } | |
456 | ||
457 | dma_free_coherent(NULL, sizeof(struct ep93xx_descs), ep->descs, | |
458 | ep->descs_dma_addr); | |
459 | } | |
460 | ||
461 | /* | |
462 | * The hardware enforces a sub-2K maximum packet size, so we put | |
463 | * two buffers on every hardware page. | |
464 | */ | |
465 | static int ep93xx_alloc_buffers(struct ep93xx_priv *ep) | |
466 | { | |
467 | int i; | |
468 | ||
469 | ep->descs = dma_alloc_coherent(NULL, sizeof(struct ep93xx_descs), | |
470 | &ep->descs_dma_addr, GFP_KERNEL | GFP_DMA); | |
471 | if (ep->descs == NULL) | |
472 | return 1; | |
473 | ||
474 | for (i = 0; i < RX_QUEUE_ENTRIES; i += 2) { | |
475 | void *page; | |
476 | dma_addr_t d; | |
477 | ||
478 | page = (void *)__get_free_page(GFP_KERNEL | GFP_DMA); | |
479 | if (page == NULL) | |
480 | goto err; | |
481 | ||
482 | d = dma_map_single(NULL, page, PAGE_SIZE, DMA_FROM_DEVICE); | |
8d8bb39b | 483 | if (dma_mapping_error(NULL, d)) { |
1d22e05d LB |
484 | free_page((unsigned long)page); |
485 | goto err; | |
486 | } | |
487 | ||
488 | ep->rx_buf[i] = page; | |
489 | ep->descs->rdesc[i].buf_addr = d; | |
490 | ep->descs->rdesc[i].rdesc1 = (i << 16) | PKT_BUF_SIZE; | |
491 | ||
492 | ep->rx_buf[i + 1] = page + PKT_BUF_SIZE; | |
493 | ep->descs->rdesc[i + 1].buf_addr = d + PKT_BUF_SIZE; | |
494 | ep->descs->rdesc[i + 1].rdesc1 = ((i + 1) << 16) | PKT_BUF_SIZE; | |
495 | } | |
496 | ||
497 | for (i = 0; i < TX_QUEUE_ENTRIES; i += 2) { | |
498 | void *page; | |
499 | dma_addr_t d; | |
500 | ||
501 | page = (void *)__get_free_page(GFP_KERNEL | GFP_DMA); | |
502 | if (page == NULL) | |
503 | goto err; | |
504 | ||
505 | d = dma_map_single(NULL, page, PAGE_SIZE, DMA_TO_DEVICE); | |
8d8bb39b | 506 | if (dma_mapping_error(NULL, d)) { |
1d22e05d LB |
507 | free_page((unsigned long)page); |
508 | goto err; | |
509 | } | |
510 | ||
511 | ep->tx_buf[i] = page; | |
512 | ep->descs->tdesc[i].buf_addr = d; | |
513 | ||
514 | ep->tx_buf[i + 1] = page + PKT_BUF_SIZE; | |
515 | ep->descs->tdesc[i + 1].buf_addr = d + PKT_BUF_SIZE; | |
516 | } | |
517 | ||
518 | return 0; | |
519 | ||
520 | err: | |
521 | ep93xx_free_buffers(ep); | |
522 | return 1; | |
523 | } | |
524 | ||
525 | static int ep93xx_start_hw(struct net_device *dev) | |
526 | { | |
527 | struct ep93xx_priv *ep = netdev_priv(dev); | |
528 | unsigned long addr; | |
529 | int i; | |
530 | ||
531 | wrl(ep, REG_SELFCTL, REG_SELFCTL_RESET); | |
532 | for (i = 0; i < 10; i++) { | |
533 | if ((rdl(ep, REG_SELFCTL) & REG_SELFCTL_RESET) == 0) | |
534 | break; | |
535 | msleep(1); | |
536 | } | |
537 | ||
538 | if (i == 10) { | |
539 | printk(KERN_CRIT DRV_MODULE_NAME ": hw failed to reset\n"); | |
540 | return 1; | |
541 | } | |
542 | ||
543 | wrl(ep, REG_SELFCTL, ((ep->mdc_divisor - 1) << 9)); | |
544 | ||
545 | /* Does the PHY support preamble suppress? */ | |
546 | if ((ep93xx_mdio_read(dev, ep->mii.phy_id, MII_BMSR) & 0x0040) != 0) | |
547 | wrl(ep, REG_SELFCTL, ((ep->mdc_divisor - 1) << 9) | (1 << 8)); | |
548 | ||
549 | /* Receive descriptor ring. */ | |
550 | addr = ep->descs_dma_addr + offsetof(struct ep93xx_descs, rdesc); | |
551 | wrl(ep, REG_RXDQBADD, addr); | |
552 | wrl(ep, REG_RXDCURADD, addr); | |
553 | wrw(ep, REG_RXDQBLEN, RX_QUEUE_ENTRIES * sizeof(struct ep93xx_rdesc)); | |
554 | ||
555 | /* Receive status ring. */ | |
556 | addr = ep->descs_dma_addr + offsetof(struct ep93xx_descs, rstat); | |
557 | wrl(ep, REG_RXSTSQBADD, addr); | |
558 | wrl(ep, REG_RXSTSQCURADD, addr); | |
559 | wrw(ep, REG_RXSTSQBLEN, RX_QUEUE_ENTRIES * sizeof(struct ep93xx_rstat)); | |
560 | ||
561 | /* Transmit descriptor ring. */ | |
562 | addr = ep->descs_dma_addr + offsetof(struct ep93xx_descs, tdesc); | |
563 | wrl(ep, REG_TXDQBADD, addr); | |
564 | wrl(ep, REG_TXDQCURADD, addr); | |
565 | wrw(ep, REG_TXDQBLEN, TX_QUEUE_ENTRIES * sizeof(struct ep93xx_tdesc)); | |
566 | ||
567 | /* Transmit status ring. */ | |
568 | addr = ep->descs_dma_addr + offsetof(struct ep93xx_descs, tstat); | |
569 | wrl(ep, REG_TXSTSQBADD, addr); | |
570 | wrl(ep, REG_TXSTSQCURADD, addr); | |
571 | wrw(ep, REG_TXSTSQBLEN, TX_QUEUE_ENTRIES * sizeof(struct ep93xx_tstat)); | |
572 | ||
573 | wrl(ep, REG_BMCTL, REG_BMCTL_ENABLE_TX | REG_BMCTL_ENABLE_RX); | |
574 | wrl(ep, REG_INTEN, REG_INTEN_TX | REG_INTEN_RX); | |
575 | wrl(ep, REG_GIINTMSK, 0); | |
576 | ||
577 | for (i = 0; i < 10; i++) { | |
578 | if ((rdl(ep, REG_BMSTS) & REG_BMSTS_RX_ACTIVE) != 0) | |
579 | break; | |
580 | msleep(1); | |
581 | } | |
582 | ||
583 | if (i == 10) { | |
584 | printk(KERN_CRIT DRV_MODULE_NAME ": hw failed to start\n"); | |
585 | return 1; | |
586 | } | |
587 | ||
588 | wrl(ep, REG_RXDENQ, RX_QUEUE_ENTRIES); | |
589 | wrl(ep, REG_RXSTSENQ, RX_QUEUE_ENTRIES); | |
590 | ||
591 | wrb(ep, REG_INDAD0, dev->dev_addr[0]); | |
592 | wrb(ep, REG_INDAD1, dev->dev_addr[1]); | |
593 | wrb(ep, REG_INDAD2, dev->dev_addr[2]); | |
594 | wrb(ep, REG_INDAD3, dev->dev_addr[3]); | |
595 | wrb(ep, REG_INDAD4, dev->dev_addr[4]); | |
596 | wrb(ep, REG_INDAD5, dev->dev_addr[5]); | |
597 | wrl(ep, REG_AFP, 0); | |
598 | ||
599 | wrl(ep, REG_MAXFRMLEN, (MAX_PKT_SIZE << 16) | MAX_PKT_SIZE); | |
600 | ||
601 | wrl(ep, REG_RXCTL, REG_RXCTL_DEFAULT); | |
602 | wrl(ep, REG_TXCTL, REG_TXCTL_ENABLE); | |
603 | ||
604 | return 0; | |
605 | } | |
606 | ||
607 | static void ep93xx_stop_hw(struct net_device *dev) | |
608 | { | |
609 | struct ep93xx_priv *ep = netdev_priv(dev); | |
610 | int i; | |
611 | ||
612 | wrl(ep, REG_SELFCTL, REG_SELFCTL_RESET); | |
613 | for (i = 0; i < 10; i++) { | |
614 | if ((rdl(ep, REG_SELFCTL) & REG_SELFCTL_RESET) == 0) | |
615 | break; | |
616 | msleep(1); | |
617 | } | |
618 | ||
619 | if (i == 10) | |
620 | printk(KERN_CRIT DRV_MODULE_NAME ": hw failed to reset\n"); | |
621 | } | |
622 | ||
623 | static int ep93xx_open(struct net_device *dev) | |
624 | { | |
625 | struct ep93xx_priv *ep = netdev_priv(dev); | |
626 | int err; | |
627 | ||
628 | if (ep93xx_alloc_buffers(ep)) | |
629 | return -ENOMEM; | |
630 | ||
631 | if (is_zero_ether_addr(dev->dev_addr)) { | |
632 | random_ether_addr(dev->dev_addr); | |
633 | printk(KERN_INFO "%s: generated random MAC address " | |
634 | "%.2x:%.2x:%.2x:%.2x:%.2x:%.2x.\n", dev->name, | |
635 | dev->dev_addr[0], dev->dev_addr[1], | |
636 | dev->dev_addr[2], dev->dev_addr[3], | |
637 | dev->dev_addr[4], dev->dev_addr[5]); | |
638 | } | |
639 | ||
bea3348e SH |
640 | napi_enable(&ep->napi); |
641 | ||
1d22e05d | 642 | if (ep93xx_start_hw(dev)) { |
bea3348e | 643 | napi_disable(&ep->napi); |
1d22e05d LB |
644 | ep93xx_free_buffers(ep); |
645 | return -EIO; | |
646 | } | |
647 | ||
648 | spin_lock_init(&ep->rx_lock); | |
649 | ep->rx_pointer = 0; | |
650 | ep->tx_clean_pointer = 0; | |
651 | ep->tx_pointer = 0; | |
652 | spin_lock_init(&ep->tx_pending_lock); | |
653 | ep->tx_pending = 0; | |
654 | ||
655 | err = request_irq(ep->irq, ep93xx_irq, IRQF_SHARED, dev->name, dev); | |
656 | if (err) { | |
bea3348e | 657 | napi_disable(&ep->napi); |
1d22e05d LB |
658 | ep93xx_stop_hw(dev); |
659 | ep93xx_free_buffers(ep); | |
660 | return err; | |
661 | } | |
662 | ||
663 | wrl(ep, REG_GIINTMSK, REG_GIINTMSK_ENABLE); | |
664 | ||
665 | netif_start_queue(dev); | |
666 | ||
667 | return 0; | |
668 | } | |
669 | ||
670 | static int ep93xx_close(struct net_device *dev) | |
671 | { | |
672 | struct ep93xx_priv *ep = netdev_priv(dev); | |
673 | ||
bea3348e | 674 | napi_disable(&ep->napi); |
1d22e05d LB |
675 | netif_stop_queue(dev); |
676 | ||
677 | wrl(ep, REG_GIINTMSK, 0); | |
678 | free_irq(ep->irq, dev); | |
679 | ep93xx_stop_hw(dev); | |
680 | ep93xx_free_buffers(ep); | |
681 | ||
682 | return 0; | |
683 | } | |
684 | ||
685 | static int ep93xx_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) | |
686 | { | |
687 | struct ep93xx_priv *ep = netdev_priv(dev); | |
688 | struct mii_ioctl_data *data = if_mii(ifr); | |
689 | ||
690 | return generic_mii_ioctl(&ep->mii, data, cmd, NULL); | |
691 | } | |
692 | ||
693 | static int ep93xx_mdio_read(struct net_device *dev, int phy_id, int reg) | |
694 | { | |
695 | struct ep93xx_priv *ep = netdev_priv(dev); | |
696 | int data; | |
697 | int i; | |
698 | ||
699 | wrl(ep, REG_MIICMD, REG_MIICMD_READ | (phy_id << 5) | reg); | |
700 | ||
701 | for (i = 0; i < 10; i++) { | |
702 | if ((rdl(ep, REG_MIISTS) & REG_MIISTS_BUSY) == 0) | |
703 | break; | |
704 | msleep(1); | |
705 | } | |
706 | ||
707 | if (i == 10) { | |
708 | printk(KERN_INFO DRV_MODULE_NAME ": mdio read timed out\n"); | |
709 | data = 0xffff; | |
710 | } else { | |
711 | data = rdl(ep, REG_MIIDATA); | |
712 | } | |
713 | ||
714 | return data; | |
715 | } | |
716 | ||
717 | static void ep93xx_mdio_write(struct net_device *dev, int phy_id, int reg, int data) | |
718 | { | |
719 | struct ep93xx_priv *ep = netdev_priv(dev); | |
720 | int i; | |
721 | ||
722 | wrl(ep, REG_MIIDATA, data); | |
723 | wrl(ep, REG_MIICMD, REG_MIICMD_WRITE | (phy_id << 5) | reg); | |
724 | ||
725 | for (i = 0; i < 10; i++) { | |
726 | if ((rdl(ep, REG_MIISTS) & REG_MIISTS_BUSY) == 0) | |
727 | break; | |
728 | msleep(1); | |
729 | } | |
730 | ||
731 | if (i == 10) | |
732 | printk(KERN_INFO DRV_MODULE_NAME ": mdio write timed out\n"); | |
733 | } | |
734 | ||
735 | static void ep93xx_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info) | |
736 | { | |
737 | strcpy(info->driver, DRV_MODULE_NAME); | |
738 | strcpy(info->version, DRV_MODULE_VERSION); | |
739 | } | |
740 | ||
741 | static int ep93xx_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) | |
742 | { | |
743 | struct ep93xx_priv *ep = netdev_priv(dev); | |
744 | return mii_ethtool_gset(&ep->mii, cmd); | |
745 | } | |
746 | ||
747 | static int ep93xx_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) | |
748 | { | |
749 | struct ep93xx_priv *ep = netdev_priv(dev); | |
750 | return mii_ethtool_sset(&ep->mii, cmd); | |
751 | } | |
752 | ||
753 | static int ep93xx_nway_reset(struct net_device *dev) | |
754 | { | |
755 | struct ep93xx_priv *ep = netdev_priv(dev); | |
756 | return mii_nway_restart(&ep->mii); | |
757 | } | |
758 | ||
759 | static u32 ep93xx_get_link(struct net_device *dev) | |
760 | { | |
761 | struct ep93xx_priv *ep = netdev_priv(dev); | |
762 | return mii_link_ok(&ep->mii); | |
763 | } | |
764 | ||
765 | static struct ethtool_ops ep93xx_ethtool_ops = { | |
766 | .get_drvinfo = ep93xx_get_drvinfo, | |
767 | .get_settings = ep93xx_get_settings, | |
768 | .set_settings = ep93xx_set_settings, | |
769 | .nway_reset = ep93xx_nway_reset, | |
770 | .get_link = ep93xx_get_link, | |
771 | }; | |
772 | ||
773 | struct net_device *ep93xx_dev_alloc(struct ep93xx_eth_data *data) | |
774 | { | |
775 | struct net_device *dev; | |
1d22e05d LB |
776 | |
777 | dev = alloc_etherdev(sizeof(struct ep93xx_priv)); | |
778 | if (dev == NULL) | |
779 | return NULL; | |
1d22e05d LB |
780 | |
781 | memcpy(dev->dev_addr, data->dev_addr, ETH_ALEN); | |
782 | ||
783 | dev->get_stats = ep93xx_get_stats; | |
784 | dev->ethtool_ops = &ep93xx_ethtool_ops; | |
1d22e05d LB |
785 | dev->hard_start_xmit = ep93xx_xmit; |
786 | dev->open = ep93xx_open; | |
787 | dev->stop = ep93xx_close; | |
788 | dev->do_ioctl = ep93xx_ioctl; | |
789 | ||
790 | dev->features |= NETIF_F_SG | NETIF_F_HW_CSUM; | |
1d22e05d LB |
791 | |
792 | return dev; | |
793 | } | |
794 | ||
795 | ||
796 | static int ep93xx_eth_remove(struct platform_device *pdev) | |
797 | { | |
798 | struct net_device *dev; | |
799 | struct ep93xx_priv *ep; | |
800 | ||
801 | dev = platform_get_drvdata(pdev); | |
802 | if (dev == NULL) | |
803 | return 0; | |
804 | platform_set_drvdata(pdev, NULL); | |
805 | ||
806 | ep = netdev_priv(dev); | |
807 | ||
808 | /* @@@ Force down. */ | |
809 | unregister_netdev(dev); | |
810 | ep93xx_free_buffers(ep); | |
811 | ||
812 | if (ep->base_addr != NULL) | |
813 | iounmap(ep->base_addr); | |
814 | ||
815 | if (ep->res != NULL) { | |
816 | release_resource(ep->res); | |
817 | kfree(ep->res); | |
818 | } | |
819 | ||
820 | free_netdev(dev); | |
821 | ||
822 | return 0; | |
823 | } | |
824 | ||
825 | static int ep93xx_eth_probe(struct platform_device *pdev) | |
826 | { | |
827 | struct ep93xx_eth_data *data; | |
828 | struct net_device *dev; | |
829 | struct ep93xx_priv *ep; | |
830 | int err; | |
831 | ||
1d22e05d LB |
832 | if (pdev == NULL) |
833 | return -ENODEV; | |
ebf5112c | 834 | data = pdev->dev.platform_data; |
1d22e05d LB |
835 | |
836 | dev = ep93xx_dev_alloc(data); | |
837 | if (dev == NULL) { | |
838 | err = -ENOMEM; | |
839 | goto err_out; | |
840 | } | |
841 | ep = netdev_priv(dev); | |
bea3348e SH |
842 | ep->dev = dev; |
843 | netif_napi_add(dev, &ep->napi, ep93xx_poll, 64); | |
1d22e05d LB |
844 | |
845 | platform_set_drvdata(pdev, dev); | |
846 | ||
847 | ep->res = request_mem_region(pdev->resource[0].start, | |
848 | pdev->resource[0].end - pdev->resource[0].start + 1, | |
3f978704 | 849 | dev_name(&pdev->dev)); |
1d22e05d LB |
850 | if (ep->res == NULL) { |
851 | dev_err(&pdev->dev, "Could not reserve memory region\n"); | |
852 | err = -ENOMEM; | |
853 | goto err_out; | |
854 | } | |
855 | ||
856 | ep->base_addr = ioremap(pdev->resource[0].start, | |
857 | pdev->resource[0].end - pdev->resource[0].start); | |
858 | if (ep->base_addr == NULL) { | |
859 | dev_err(&pdev->dev, "Failed to ioremap ethernet registers\n"); | |
860 | err = -EIO; | |
861 | goto err_out; | |
862 | } | |
863 | ep->irq = pdev->resource[1].start; | |
864 | ||
865 | ep->mii.phy_id = data->phy_id; | |
866 | ep->mii.phy_id_mask = 0x1f; | |
867 | ep->mii.reg_num_mask = 0x1f; | |
868 | ep->mii.dev = dev; | |
869 | ep->mii.mdio_read = ep93xx_mdio_read; | |
870 | ep->mii.mdio_write = ep93xx_mdio_write; | |
871 | ep->mdc_divisor = 40; /* Max HCLK 100 MHz, min MDIO clk 2.5 MHz. */ | |
872 | ||
873 | err = register_netdev(dev); | |
874 | if (err) { | |
875 | dev_err(&pdev->dev, "Failed to register netdev\n"); | |
876 | goto err_out; | |
877 | } | |
878 | ||
879 | printk(KERN_INFO "%s: ep93xx on-chip ethernet, IRQ %d, " | |
880 | "%.2x:%.2x:%.2x:%.2x:%.2x:%.2x.\n", dev->name, | |
881 | ep->irq, data->dev_addr[0], data->dev_addr[1], | |
882 | data->dev_addr[2], data->dev_addr[3], | |
883 | data->dev_addr[4], data->dev_addr[5]); | |
884 | ||
885 | return 0; | |
886 | ||
887 | err_out: | |
888 | ep93xx_eth_remove(pdev); | |
889 | return err; | |
890 | } | |
891 | ||
892 | ||
893 | static struct platform_driver ep93xx_eth_driver = { | |
894 | .probe = ep93xx_eth_probe, | |
895 | .remove = ep93xx_eth_remove, | |
896 | .driver = { | |
897 | .name = "ep93xx-eth", | |
72abb461 | 898 | .owner = THIS_MODULE, |
1d22e05d LB |
899 | }, |
900 | }; | |
901 | ||
902 | static int __init ep93xx_eth_init_module(void) | |
903 | { | |
904 | printk(KERN_INFO DRV_MODULE_NAME " version " DRV_MODULE_VERSION " loading\n"); | |
905 | return platform_driver_register(&ep93xx_eth_driver); | |
906 | } | |
907 | ||
908 | static void __exit ep93xx_eth_cleanup_module(void) | |
909 | { | |
910 | platform_driver_unregister(&ep93xx_eth_driver); | |
911 | } | |
912 | ||
913 | module_init(ep93xx_eth_init_module); | |
914 | module_exit(ep93xx_eth_cleanup_module); | |
915 | MODULE_LICENSE("GPL"); | |
72abb461 | 916 | MODULE_ALIAS("platform:ep93xx-eth"); |