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IXP4xx: Add PHYLIB support to Ethernet driver.
[deliverable/linux.git] / drivers / net / arm / ixp4xx_eth.c
CommitLineData
dac2f83f
KH		 1/*
2 * Intel IXP4xx Ethernet driver for Linux
3 *
4 * Copyright (C) 2007 Krzysztof Halasa <khc@pm.waw.pl>
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of version 2 of the GNU General Public License
8 * as published by the Free Software Foundation.
9 *
10 * Ethernet port config (0x00 is not present on IXP42X):
11 *
12 * logical port 0x00 0x10 0x20
13 * NPE 0 (NPE-A) 1 (NPE-B) 2 (NPE-C)
14 * physical PortId 2 0 1
15 * TX queue 23 24 25
16 * RX-free queue 26 27 28
17 * TX-done queue is always 31, per-port RX and TX-ready queues are configurable
18 *
19 *
20 * Queue entries:
21 * bits 0 -> 1 - NPE ID (RX and TX-done)
22 * bits 0 -> 2 - priority (TX, per 802.1D)
23 * bits 3 -> 4 - port ID (user-set?)
24 * bits 5 -> 31 - physical descriptor address
25 */
26
27#include <linux/delay.h>
28#include <linux/dma-mapping.h>
29#include <linux/dmapool.h>
30#include <linux/etherdevice.h>
31#include <linux/io.h>
32#include <linux/kernel.h>
2098c18d 33#include <linux/phy.h>
dac2f83f 34#include <linux/platform_device.h>
a09e64fb
RK		 35#include <mach/npe.h>
36#include <mach/qmgr.h>
dac2f83f
KH		 37
38#define DEBUG_QUEUES 0
39#define DEBUG_DESC 0
40#define DEBUG_RX 0
41#define DEBUG_TX 0
42#define DEBUG_PKT_BYTES 0
43#define DEBUG_MDIO 0
44#define DEBUG_CLOSE 0
45
46#define DRV_NAME "ixp4xx_eth"
47
48#define MAX_NPES 3
49
50#define RX_DESCS 64 /* also length of all RX queues */
51#define TX_DESCS 16 /* also length of all TX queues */
52#define TXDONE_QUEUE_LEN 64 /* dwords */
53
54#define POOL_ALLOC_SIZE (sizeof(struct desc) * (RX_DESCS + TX_DESCS))
55#define REGS_SIZE 0x1000
56#define MAX_MRU 1536 /* 0x600 */
57#define RX_BUFF_SIZE ALIGN((NET_IP_ALIGN) + MAX_MRU, 4)
58
59#define NAPI_WEIGHT 16
60#define MDIO_INTERVAL (3 * HZ)
61#define MAX_MDIO_RETRIES 100 /* microseconds, typically 30 cycles */
dac2f83f
KH		 62#define MAX_CLOSE_WAIT 1000 /* microseconds, typically 2-3 cycles */
63
64#define NPE_ID(port_id) ((port_id) >> 4)
65#define PHYSICAL_ID(port_id) ((NPE_ID(port_id) + 2) % 3)
66#define TX_QUEUE(port_id) (NPE_ID(port_id) + 23)
67#define RXFREE_QUEUE(port_id) (NPE_ID(port_id) + 26)
68#define TXDONE_QUEUE 31
69
70/* TX Control Registers */
71#define TX_CNTRL0_TX_EN 0x01
72#define TX_CNTRL0_HALFDUPLEX 0x02
73#define TX_CNTRL0_RETRY 0x04
74#define TX_CNTRL0_PAD_EN 0x08
75#define TX_CNTRL0_APPEND_FCS 0x10
76#define TX_CNTRL0_2DEFER 0x20
77#define TX_CNTRL0_RMII 0x40 /* reduced MII */
78#define TX_CNTRL1_RETRIES 0x0F /* 4 bits */
79
80/* RX Control Registers */
81#define RX_CNTRL0_RX_EN 0x01
82#define RX_CNTRL0_PADSTRIP_EN 0x02
83#define RX_CNTRL0_SEND_FCS 0x04
84#define RX_CNTRL0_PAUSE_EN 0x08
85#define RX_CNTRL0_LOOP_EN 0x10
86#define RX_CNTRL0_ADDR_FLTR_EN 0x20
87#define RX_CNTRL0_RX_RUNT_EN 0x40
88#define RX_CNTRL0_BCAST_DIS 0x80
89#define RX_CNTRL1_DEFER_EN 0x01
90
91/* Core Control Register */
92#define CORE_RESET 0x01
93#define CORE_RX_FIFO_FLUSH 0x02
94#define CORE_TX_FIFO_FLUSH 0x04
95#define CORE_SEND_JAM 0x08
96#define CORE_MDC_EN 0x10 /* MDIO using NPE-B ETH-0 only */
97
98#define DEFAULT_TX_CNTRL0 (TX_CNTRL0_TX_EN | TX_CNTRL0_RETRY | \
99 TX_CNTRL0_PAD_EN | TX_CNTRL0_APPEND_FCS | \
100 TX_CNTRL0_2DEFER)
101#define DEFAULT_RX_CNTRL0 RX_CNTRL0_RX_EN
102#define DEFAULT_CORE_CNTRL CORE_MDC_EN
103
104
105/* NPE message codes */
106#define NPE_GETSTATUS 0x00
107#define NPE_EDB_SETPORTADDRESS 0x01
108#define NPE_EDB_GETMACADDRESSDATABASE 0x02
109#define NPE_EDB_SETMACADDRESSSDATABASE 0x03
110#define NPE_GETSTATS 0x04
111#define NPE_RESETSTATS 0x05
112#define NPE_SETMAXFRAMELENGTHS 0x06
113#define NPE_VLAN_SETRXTAGMODE 0x07
114#define NPE_VLAN_SETDEFAULTRXVID 0x08
115#define NPE_VLAN_SETPORTVLANTABLEENTRY 0x09
116#define NPE_VLAN_SETPORTVLANTABLERANGE 0x0A
117#define NPE_VLAN_SETRXQOSENTRY 0x0B
118#define NPE_VLAN_SETPORTIDEXTRACTIONMODE 0x0C
119#define NPE_STP_SETBLOCKINGSTATE 0x0D
120#define NPE_FW_SETFIREWALLMODE 0x0E
121#define NPE_PC_SETFRAMECONTROLDURATIONID 0x0F
122#define NPE_PC_SETAPMACTABLE 0x11
123#define NPE_SETLOOPBACK_MODE 0x12
124#define NPE_PC_SETBSSIDTABLE 0x13
125#define NPE_ADDRESS_FILTER_CONFIG 0x14
126#define NPE_APPENDFCSCONFIG 0x15
127#define NPE_NOTIFY_MAC_RECOVERY_DONE 0x16
128#define NPE_MAC_RECOVERY_START 0x17
129
130
131#ifdef __ARMEB__
132typedef struct sk_buff buffer_t;
133#define free_buffer dev_kfree_skb
134#define free_buffer_irq dev_kfree_skb_irq
135#else
136typedef void buffer_t;
137#define free_buffer kfree
138#define free_buffer_irq kfree
139#endif
140
141struct eth_regs {
142 u32 tx_control[2], __res1[2]; /* 000 */
143 u32 rx_control[2], __res2[2]; /* 010 */
144 u32 random_seed, __res3[3]; /* 020 */
145 u32 partial_empty_threshold, __res4; /* 030 */
146 u32 partial_full_threshold, __res5; /* 038 */
147 u32 tx_start_bytes, __res6[3]; /* 040 */
148 u32 tx_deferral, rx_deferral, __res7[2];/* 050 */
149 u32 tx_2part_deferral[2], __res8[2]; /* 060 */
150 u32 slot_time, __res9[3]; /* 070 */
151 u32 mdio_command[4]; /* 080 */
152 u32 mdio_status[4]; /* 090 */
153 u32 mcast_mask[6], __res10[2]; /* 0A0 */
154 u32 mcast_addr[6], __res11[2]; /* 0C0 */
155 u32 int_clock_threshold, __res12[3]; /* 0E0 */
156 u32 hw_addr[6], __res13[61]; /* 0F0 */
157 u32 core_control; /* 1FC */
158};
159
160struct port {
161 struct resource *mem_res;
162 struct eth_regs __iomem *regs;
163 struct npe *npe;
164 struct net_device *netdev;
165 struct napi_struct napi;
2098c18d 166 struct phy_device *phydev;
dac2f83f
KH		 167 struct eth_plat_info *plat;
168 buffer_t *rx_buff_tab[RX_DESCS], *tx_buff_tab[TX_DESCS];
169 struct desc *desc_tab; /* coherent */
170 u32 desc_tab_phys;
171 int id; /* logical port ID */
2098c18d 172 int speed, duplex;
dac2f83f
KH		 173};
174
175/* NPE message structure */
176struct msg {
177#ifdef __ARMEB__
178 u8 cmd, eth_id, byte2, byte3;
179 u8 byte4, byte5, byte6, byte7;
180#else
181 u8 byte3, byte2, eth_id, cmd;
182 u8 byte7, byte6, byte5, byte4;
183#endif
184};
185
186/* Ethernet packet descriptor */
187struct desc {
188 u32 next; /* pointer to next buffer, unused */
189
190#ifdef __ARMEB__
191 u16 buf_len; /* buffer length */
192 u16 pkt_len; /* packet length */
193 u32 data; /* pointer to data buffer in RAM */
194 u8 dest_id;
195 u8 src_id;
196 u16 flags;
197 u8 qos;
198 u8 padlen;
199 u16 vlan_tci;
200#else
201 u16 pkt_len; /* packet length */
202 u16 buf_len; /* buffer length */
203 u32 data; /* pointer to data buffer in RAM */
204 u16 flags;
205 u8 src_id;
206 u8 dest_id;
207 u16 vlan_tci;
208 u8 padlen;
209 u8 qos;
210#endif
211
212#ifdef __ARMEB__
213 u8 dst_mac_0, dst_mac_1, dst_mac_2, dst_mac_3;
214 u8 dst_mac_4, dst_mac_5, src_mac_0, src_mac_1;
215 u8 src_mac_2, src_mac_3, src_mac_4, src_mac_5;
216#else
217 u8 dst_mac_3, dst_mac_2, dst_mac_1, dst_mac_0;
218 u8 src_mac_1, src_mac_0, dst_mac_5, dst_mac_4;
219 u8 src_mac_5, src_mac_4, src_mac_3, src_mac_2;
220#endif
221};
222
223
224#define rx_desc_phys(port, n) ((port)->desc_tab_phys + \
225 (n) * sizeof(struct desc))
226#define rx_desc_ptr(port, n) (&(port)->desc_tab[n])
227
228#define tx_desc_phys(port, n) ((port)->desc_tab_phys + \
229 ((n) + RX_DESCS) * sizeof(struct desc))
230#define tx_desc_ptr(port, n) (&(port)->desc_tab[(n) + RX_DESCS])
231
232#ifndef __ARMEB__
233static inline void memcpy_swab32(u32 *dest, u32 *src, int cnt)
234{
235 int i;
236 for (i = 0; i < cnt; i++)
237 dest[i] = swab32(src[i]);
238}
239#endif
240
241static spinlock_t mdio_lock;
242static struct eth_regs __iomem *mdio_regs; /* mdio command and status only */
2098c18d 243struct mii_bus *mdio_bus;
dac2f83f
KH		 244static int ports_open;
245static struct port *npe_port_tab[MAX_NPES];
246static struct dma_pool *dma_pool;
247
248
2098c18d
KH		 249static int ixp4xx_mdio_cmd(struct mii_bus *bus, int phy_id, int location,
250 int write, u16 cmd)
dac2f83f
KH		 251{
252 int cycles = 0;
253
254 if (__raw_readl(&mdio_regs->mdio_command[3]) & 0x80) {
2098c18d
KH		 255 printk(KERN_ERR "%s: MII not ready to transmit\n", bus->name);
256 return -1;
dac2f83f
KH		 257 }
258
259 if (write) {
260 __raw_writel(cmd & 0xFF, &mdio_regs->mdio_command[0]);
261 __raw_writel(cmd >> 8, &mdio_regs->mdio_command[1]);
262 }
263 __raw_writel(((phy_id << 5) | location) & 0xFF,
264 &mdio_regs->mdio_command[2]);
265 __raw_writel((phy_id >> 3) | (write << 2) | 0x80 /* GO */,
266 &mdio_regs->mdio_command[3]);
267
268 while ((cycles < MAX_MDIO_RETRIES) &&
269 (__raw_readl(&mdio_regs->mdio_command[3]) & 0x80)) {
270 udelay(1);
271 cycles++;
272 }
273
274 if (cycles == MAX_MDIO_RETRIES) {
2098c18d
KH		 275 printk(KERN_ERR "%s #%i: MII write failed\n", bus->name,
276 phy_id);
277 return -1;
dac2f83f
KH		 278 }
279
280#if DEBUG_MDIO
2098c18d
KH		 281 printk(KERN_DEBUG "%s #%i: mdio_%s() took %i cycles\n", bus->name,
282 phy_id, write ? "write" : "read", cycles);
dac2f83f
KH		 283#endif
284
285 if (write)
286 return 0;
287
288 if (__raw_readl(&mdio_regs->mdio_status[3]) & 0x80) {
2098c18d
KH		 289#if DEBUG_MDIO
290 printk(KERN_DEBUG "%s #%i: MII read failed\n", bus->name,
291 phy_id);
292#endif
293 return 0xFFFF; /* don't return error */
dac2f83f
KH		 294 }
295
296 return (__raw_readl(&mdio_regs->mdio_status[0]) & 0xFF) |
2098c18d 297 ((__raw_readl(&mdio_regs->mdio_status[1]) & 0xFF) << 8);
dac2f83f
KH		 298}
299
2098c18d 300static int ixp4xx_mdio_read(struct mii_bus *bus, int phy_id, int location)
dac2f83f
KH		 301{
302 unsigned long flags;
2098c18d 303 int ret;
dac2f83f
KH		 304
305 spin_lock_irqsave(&mdio_lock, flags);
2098c18d 306 ret = ixp4xx_mdio_cmd(bus, phy_id, location, 0, 0);
dac2f83f 307 spin_unlock_irqrestore(&mdio_lock, flags);
2098c18d
KH		 308#if DEBUG_MDIO
309 printk(KERN_DEBUG "%s #%i: MII read [%i] -> 0x%X\n", bus->name,
310 phy_id, location, ret);
311#endif
312 return ret;
dac2f83f
KH		 313}
314
2098c18d
KH		 315static int ixp4xx_mdio_write(struct mii_bus *bus, int phy_id, int location,
316 u16 val)
dac2f83f
KH		 317{
318 unsigned long flags;
2098c18d 319 int ret;
dac2f83f
KH		 320
321 spin_lock_irqsave(&mdio_lock, flags);
2098c18d 322 ret = ixp4xx_mdio_cmd(bus, phy_id, location, 1, val);
dac2f83f 323 spin_unlock_irqrestore(&mdio_lock, flags);
2098c18d
KH		 324#if DEBUG_MDIO
325 printk(KERN_DEBUG "%s #%i: MII read [%i] <- 0x%X, err = %i\n",
326 bus->name, phy_id, location, val, ret);
327#endif
328 return ret;
dac2f83f
KH		 329}
330
2098c18d 331static int ixp4xx_mdio_register(void)
dac2f83f 332{
2098c18d
KH		 333 int err;
334
335 if (!(mdio_bus = mdiobus_alloc()))
336 return -ENOMEM;
dac2f83f 337
2098c18d
KH		 338 /* All MII PHY accesses use NPE-B Ethernet registers */
339 spin_lock_init(&mdio_lock);
340 mdio_regs = (struct eth_regs __iomem *)IXP4XX_EthB_BASE_VIRT;
341 __raw_writel(DEFAULT_CORE_CNTRL, &mdio_regs->core_control);
dac2f83f 342
2098c18d
KH		 343 mdio_bus->name = "IXP4xx MII Bus";
344 mdio_bus->read = &ixp4xx_mdio_read;
345 mdio_bus->write = &ixp4xx_mdio_write;
346 strcpy(mdio_bus->id, "0");
dac2f83f 347
2098c18d
KH		 348 if ((err = mdiobus_register(mdio_bus)))
349 mdiobus_free(mdio_bus);
350 return err;
dac2f83f
KH		 351}
352
2098c18d 353static void ixp4xx_mdio_remove(void)
dac2f83f 354{
2098c18d
KH		 355 mdiobus_unregister(mdio_bus);
356 mdiobus_free(mdio_bus);
dac2f83f
KH		 357}
358
359
2098c18d 360static void ixp4xx_adjust_link(struct net_device *dev)
dac2f83f 361{
2098c18d
KH		 362 struct port *port = netdev_priv(dev);
363 struct phy_device *phydev = port->phydev;
364
365 if (!phydev->link) {
366 if (port->speed) {
367 port->speed = 0;
dac2f83f 368 printk(KERN_INFO "%s: link down\n", dev->name);
dac2f83f 369 }
2098c18d 370 return;
dac2f83f 371 }
dac2f83f 372
2098c18d
KH		 373 if (port->speed == phydev->speed && port->duplex == phydev->duplex)
374 return;
dac2f83f 375
2098c18d
KH		 376 port->speed = phydev->speed;
377 port->duplex = phydev->duplex;
dac2f83f 378
2098c18d
KH		 379 if (port->duplex)
380 __raw_writel(DEFAULT_TX_CNTRL0 & ~TX_CNTRL0_HALFDUPLEX,
381 &port->regs->tx_control[0]);
382 else
383 __raw_writel(DEFAULT_TX_CNTRL0 | TX_CNTRL0_HALFDUPLEX,
384 &port->regs->tx_control[0]);
385
386 printk(KERN_INFO "%s: link up, speed %u Mb/s, %s duplex\n",
387 dev->name, port->speed, port->duplex ? "full" : "half");
dac2f83f
KH		 388}
389
390
391static inline void debug_pkt(struct net_device *dev, const char *func,
392 u8 *data, int len)
393{
394#if DEBUG_PKT_BYTES
395 int i;
396
397 printk(KERN_DEBUG "%s: %s(%i) ", dev->name, func, len);
398 for (i = 0; i < len; i++) {
399 if (i >= DEBUG_PKT_BYTES)
400 break;
401 printk("%s%02X",
402 ((i == 6) || (i == 12) || (i >= 14)) ? " " : "",
403 data[i]);
404 }
405 printk("\n");
406#endif
407}
408
409
410static inline void debug_desc(u32 phys, struct desc *desc)
411{
412#if DEBUG_DESC
413 printk(KERN_DEBUG "%X: %X %3X %3X %08X %2X < %2X %4X %X"
414 " %X %X %02X%02X%02X%02X%02X%02X < %02X%02X%02X%02X%02X%02X\n",
415 phys, desc->next, desc->buf_len, desc->pkt_len,
416 desc->data, desc->dest_id, desc->src_id, desc->flags,
417 desc->qos, desc->padlen, desc->vlan_tci,
418 desc->dst_mac_0, desc->dst_mac_1, desc->dst_mac_2,
419 desc->dst_mac_3, desc->dst_mac_4, desc->dst_mac_5,
420 desc->src_mac_0, desc->src_mac_1, desc->src_mac_2,
421 desc->src_mac_3, desc->src_mac_4, desc->src_mac_5);
422#endif
423}
424
425static inline void debug_queue(unsigned int queue, int is_get, u32 phys)
426{
427#if DEBUG_QUEUES
428 static struct {
429 int queue;
430 char *name;
431 } names[] = {
432 { TX_QUEUE(0x10), "TX#0 " },
433 { TX_QUEUE(0x20), "TX#1 " },
434 { TX_QUEUE(0x00), "TX#2 " },
435 { RXFREE_QUEUE(0x10), "RX-free#0 " },
436 { RXFREE_QUEUE(0x20), "RX-free#1 " },
437 { RXFREE_QUEUE(0x00), "RX-free#2 " },
438 { TXDONE_QUEUE, "TX-done " },
439 };
440 int i;
441
442 for (i = 0; i < ARRAY_SIZE(names); i++)
443 if (names[i].queue == queue)
444 break;
445
446 printk(KERN_DEBUG "Queue %i %s%s %X\n", queue,
447 i < ARRAY_SIZE(names) ? names[i].name : "",
448 is_get ? "->" : "<-", phys);
449#endif
450}
451
452static inline u32 queue_get_entry(unsigned int queue)
453{
454 u32 phys = qmgr_get_entry(queue);
455 debug_queue(queue, 1, phys);
456 return phys;
457}
458
459static inline int queue_get_desc(unsigned int queue, struct port *port,
460 int is_tx)
461{
462 u32 phys, tab_phys, n_desc;
463 struct desc *tab;
464
465 if (!(phys = queue_get_entry(queue)))
466 return -1;
467
468 phys &= ~0x1F; /* mask out non-address bits */
469 tab_phys = is_tx ? tx_desc_phys(port, 0) : rx_desc_phys(port, 0);
470 tab = is_tx ? tx_desc_ptr(port, 0) : rx_desc_ptr(port, 0);
471 n_desc = (phys - tab_phys) / sizeof(struct desc);
472 BUG_ON(n_desc >= (is_tx ? TX_DESCS : RX_DESCS));
473 debug_desc(phys, &tab[n_desc]);
474 BUG_ON(tab[n_desc].next);
475 return n_desc;
476}
477
478static inline void queue_put_desc(unsigned int queue, u32 phys,
479 struct desc *desc)
480{
481 debug_queue(queue, 0, phys);
482 debug_desc(phys, desc);
483 BUG_ON(phys & 0x1F);
484 qmgr_put_entry(queue, phys);
485 BUG_ON(qmgr_stat_overflow(queue));
486}
487
488
489static inline void dma_unmap_tx(struct port *port, struct desc *desc)
490{
491#ifdef __ARMEB__
492 dma_unmap_single(&port->netdev->dev, desc->data,
493 desc->buf_len, DMA_TO_DEVICE);
494#else
495 dma_unmap_single(&port->netdev->dev, desc->data & ~3,
496 ALIGN((desc->data & 3) + desc->buf_len, 4),
497 DMA_TO_DEVICE);
498#endif
499}
500
501
502static void eth_rx_irq(void *pdev)
503{
504 struct net_device *dev = pdev;
505 struct port *port = netdev_priv(dev);
506
507#if DEBUG_RX
508 printk(KERN_DEBUG "%s: eth_rx_irq\n", dev->name);
509#endif
510 qmgr_disable_irq(port->plat->rxq);
511 netif_rx_schedule(dev, &port->napi);
512}
513
514static int eth_poll(struct napi_struct *napi, int budget)
515{
516 struct port *port = container_of(napi, struct port, napi);
517 struct net_device *dev = port->netdev;
518 unsigned int rxq = port->plat->rxq, rxfreeq = RXFREE_QUEUE(port->id);
519 int received = 0;
520
521#if DEBUG_RX
522 printk(KERN_DEBUG "%s: eth_poll\n", dev->name);
523#endif
524
525 while (received < budget) {
526 struct sk_buff *skb;
527 struct desc *desc;
528 int n;
529#ifdef __ARMEB__
530 struct sk_buff *temp;
531 u32 phys;
532#endif
533
534 if ((n = queue_get_desc(rxq, port, 0)) < 0) {
dac2f83f
KH		 535#if DEBUG_RX
536 printk(KERN_DEBUG "%s: eth_poll netif_rx_complete\n",
537 dev->name);
538#endif
539 netif_rx_complete(dev, napi);
540 qmgr_enable_irq(rxq);
541 if (!qmgr_stat_empty(rxq) &&
542 netif_rx_reschedule(dev, napi)) {
543#if DEBUG_RX
544 printk(KERN_DEBUG "%s: eth_poll"
545 " netif_rx_reschedule successed\n",
546 dev->name);
547#endif
548 qmgr_disable_irq(rxq);
549 continue;
550 }
551#if DEBUG_RX
552 printk(KERN_DEBUG "%s: eth_poll all done\n",
553 dev->name);
554#endif
9076689a 555 return received; /* all work done */
dac2f83f
KH		 556 }
557
558 desc = rx_desc_ptr(port, n);
559
560#ifdef __ARMEB__
561 if ((skb = netdev_alloc_skb(dev, RX_BUFF_SIZE))) {
562 phys = dma_map_single(&dev->dev, skb->data,
563 RX_BUFF_SIZE, DMA_FROM_DEVICE);
7144decb 564 if (dma_mapping_error(&dev->dev, phys)) {
dac2f83f
KH		 565 dev_kfree_skb(skb);
566 skb = NULL;
567 }
568 }
569#else
570 skb = netdev_alloc_skb(dev,
571 ALIGN(NET_IP_ALIGN + desc->pkt_len, 4));
572#endif
573
574 if (!skb) {
b4c7d3b0 575 dev->stats.rx_dropped++;
dac2f83f
KH		 576 /* put the desc back on RX-ready queue */
577 desc->buf_len = MAX_MRU;
578 desc->pkt_len = 0;
579 queue_put_desc(rxfreeq, rx_desc_phys(port, n), desc);
580 continue;
581 }
582
583 /* process received frame */
584#ifdef __ARMEB__
585 temp = skb;
586 skb = port->rx_buff_tab[n];
587 dma_unmap_single(&dev->dev, desc->data - NET_IP_ALIGN,
588 RX_BUFF_SIZE, DMA_FROM_DEVICE);
589#else
590 dma_sync_single(&dev->dev, desc->data - NET_IP_ALIGN,
591 RX_BUFF_SIZE, DMA_FROM_DEVICE);
592 memcpy_swab32((u32 *)skb->data, (u32 *)port->rx_buff_tab[n],
593 ALIGN(NET_IP_ALIGN + desc->pkt_len, 4) / 4);
594#endif
595 skb_reserve(skb, NET_IP_ALIGN);
596 skb_put(skb, desc->pkt_len);
597
598 debug_pkt(dev, "eth_poll", skb->data, skb->len);
599
600 skb->protocol = eth_type_trans(skb, dev);
b4c7d3b0
KH		 601 dev->stats.rx_packets++;
602 dev->stats.rx_bytes += skb->len;
dac2f83f
KH		 603 netif_receive_skb(skb);
604
605 /* put the new buffer on RX-free queue */
606#ifdef __ARMEB__
607 port->rx_buff_tab[n] = temp;
608 desc->data = phys + NET_IP_ALIGN;
609#endif
610 desc->buf_len = MAX_MRU;
611 desc->pkt_len = 0;
612 queue_put_desc(rxfreeq, rx_desc_phys(port, n), desc);
613 received++;
614 }
615
616#if DEBUG_RX
617 printk(KERN_DEBUG "eth_poll(): end, not all work done\n");
618#endif
619 return received; /* not all work done */
620}
621
622
623static void eth_txdone_irq(void *unused)
624{
625 u32 phys;
626
627#if DEBUG_TX
628 printk(KERN_DEBUG DRV_NAME ": eth_txdone_irq\n");
629#endif
630 while ((phys = queue_get_entry(TXDONE_QUEUE)) != 0) {
631 u32 npe_id, n_desc;
632 struct port *port;
633 struct desc *desc;
634 int start;
635
636 npe_id = phys & 3;
637 BUG_ON(npe_id >= MAX_NPES);
638 port = npe_port_tab[npe_id];
639 BUG_ON(!port);
640 phys &= ~0x1F; /* mask out non-address bits */
641 n_desc = (phys - tx_desc_phys(port, 0)) / sizeof(struct desc);
642 BUG_ON(n_desc >= TX_DESCS);
643 desc = tx_desc_ptr(port, n_desc);
644 debug_desc(phys, desc);
645
646 if (port->tx_buff_tab[n_desc]) { /* not the draining packet */
b4c7d3b0
KH		 647 port->netdev->stats.tx_packets++;
648 port->netdev->stats.tx_bytes += desc->pkt_len;
dac2f83f
KH		 649
650 dma_unmap_tx(port, desc);
651#if DEBUG_TX
652 printk(KERN_DEBUG "%s: eth_txdone_irq free %p\n",
653 port->netdev->name, port->tx_buff_tab[n_desc]);
654#endif
655 free_buffer_irq(port->tx_buff_tab[n_desc]);
656 port->tx_buff_tab[n_desc] = NULL;
657 }
658
659 start = qmgr_stat_empty(port->plat->txreadyq);
660 queue_put_desc(port->plat->txreadyq, phys, desc);
661 if (start) {
662#if DEBUG_TX
663 printk(KERN_DEBUG "%s: eth_txdone_irq xmit ready\n",
664 port->netdev->name);
665#endif
666 netif_wake_queue(port->netdev);
667 }
668 }
669}
670
671static int eth_xmit(struct sk_buff *skb, struct net_device *dev)
672{
673 struct port *port = netdev_priv(dev);
674 unsigned int txreadyq = port->plat->txreadyq;
675 int len, offset, bytes, n;
676 void *mem;
677 u32 phys;
678 struct desc *desc;
679
680#if DEBUG_TX
681 printk(KERN_DEBUG "%s: eth_xmit\n", dev->name);
682#endif
683
684 if (unlikely(skb->len > MAX_MRU)) {
685 dev_kfree_skb(skb);
b4c7d3b0 686 dev->stats.tx_errors++;
dac2f83f
KH		 687 return NETDEV_TX_OK;
688 }
689
690 debug_pkt(dev, "eth_xmit", skb->data, skb->len);
691
692 len = skb->len;
693#ifdef __ARMEB__
694 offset = 0; /* no need to keep alignment */
695 bytes = len;
696 mem = skb->data;
697#else
698 offset = (int)skb->data & 3; /* keep 32-bit alignment */
699 bytes = ALIGN(offset + len, 4);
700 if (!(mem = kmalloc(bytes, GFP_ATOMIC))) {
701 dev_kfree_skb(skb);
b4c7d3b0 702 dev->stats.tx_dropped++;
dac2f83f
KH		 703 return NETDEV_TX_OK;
704 }
705 memcpy_swab32(mem, (u32 *)((int)skb->data & ~3), bytes / 4);
706 dev_kfree_skb(skb);
707#endif
708
709 phys = dma_map_single(&dev->dev, mem, bytes, DMA_TO_DEVICE);
7144decb 710 if (dma_mapping_error(&dev->dev, phys)) {
dac2f83f
KH		 711#ifdef __ARMEB__
712 dev_kfree_skb(skb);
713#else
714 kfree(mem);
715#endif
b4c7d3b0 716 dev->stats.tx_dropped++;
dac2f83f
KH		 717 return NETDEV_TX_OK;
718 }
719
720 n = queue_get_desc(txreadyq, port, 1);
721 BUG_ON(n < 0);
722 desc = tx_desc_ptr(port, n);
723
724#ifdef __ARMEB__
725 port->tx_buff_tab[n] = skb;
726#else
727 port->tx_buff_tab[n] = mem;
728#endif
729 desc->data = phys + offset;
730 desc->buf_len = desc->pkt_len = len;
731
732 /* NPE firmware pads short frames with zeros internally */
733 wmb();
734 queue_put_desc(TX_QUEUE(port->id), tx_desc_phys(port, n), desc);
735 dev->trans_start = jiffies;
736
737 if (qmgr_stat_empty(txreadyq)) {
738#if DEBUG_TX
739 printk(KERN_DEBUG "%s: eth_xmit queue full\n", dev->name);
740#endif
741 netif_stop_queue(dev);
742 /* we could miss TX ready interrupt */
743 if (!qmgr_stat_empty(txreadyq)) {
744#if DEBUG_TX
745 printk(KERN_DEBUG "%s: eth_xmit ready again\n",
746 dev->name);
747#endif
748 netif_wake_queue(dev);
749 }
750 }
751
752#if DEBUG_TX
753 printk(KERN_DEBUG "%s: eth_xmit end\n", dev->name);
754#endif
755 return NETDEV_TX_OK;
756}
757
758
dac2f83f
KH		 759static void eth_set_mcast_list(struct net_device *dev)
760{
761 struct port *port = netdev_priv(dev);
762 struct dev_mc_list *mclist = dev->mc_list;
763 u8 diffs[ETH_ALEN], *addr;
764 int cnt = dev->mc_count, i;
765
766 if ((dev->flags & IFF_PROMISC) || !mclist || !cnt) {
767 __raw_writel(DEFAULT_RX_CNTRL0 & ~RX_CNTRL0_ADDR_FLTR_EN,
768 &port->regs->rx_control[0]);
769 return;
770 }
771
772 memset(diffs, 0, ETH_ALEN);
773 addr = mclist->dmi_addr; /* first MAC address */
774
775 while (--cnt && (mclist = mclist->next))
776 for (i = 0; i < ETH_ALEN; i++)
777 diffs[i] |= addr[i] ^ mclist->dmi_addr[i];
778
779 for (i = 0; i < ETH_ALEN; i++) {
780 __raw_writel(addr[i], &port->regs->mcast_addr[i]);
781 __raw_writel(~diffs[i], &port->regs->mcast_mask[i]);
782 }
783
784 __raw_writel(DEFAULT_RX_CNTRL0 | RX_CNTRL0_ADDR_FLTR_EN,
785 &port->regs->rx_control[0]);
786}
787
788
789static int eth_ioctl(struct net_device *dev, struct ifreq *req, int cmd)
790{
dac2f83f
KH		 791 if (!netif_running(dev))
792 return -EINVAL;
2098c18d 793 return -EINVAL;
dac2f83f
KH		 794}
795
796
797static int request_queues(struct port *port)
798{
799 int err;
800
801 err = qmgr_request_queue(RXFREE_QUEUE(port->id), RX_DESCS, 0, 0);
802 if (err)
803 return err;
804
805 err = qmgr_request_queue(port->plat->rxq, RX_DESCS, 0, 0);
806 if (err)
807 goto rel_rxfree;
808
809 err = qmgr_request_queue(TX_QUEUE(port->id), TX_DESCS, 0, 0);
810 if (err)
811 goto rel_rx;
812
813 err = qmgr_request_queue(port->plat->txreadyq, TX_DESCS, 0, 0);
814 if (err)
815 goto rel_tx;
816
817 /* TX-done queue handles skbs sent out by the NPEs */
818 if (!ports_open) {
819 err = qmgr_request_queue(TXDONE_QUEUE, TXDONE_QUEUE_LEN, 0, 0);
820 if (err)
821 goto rel_txready;
822 }
823 return 0;
824
825rel_txready:
826 qmgr_release_queue(port->plat->txreadyq);
827rel_tx:
828 qmgr_release_queue(TX_QUEUE(port->id));
829rel_rx:
830 qmgr_release_queue(port->plat->rxq);
831rel_rxfree:
832 qmgr_release_queue(RXFREE_QUEUE(port->id));
833 printk(KERN_DEBUG "%s: unable to request hardware queues\n",
834 port->netdev->name);
835 return err;
836}
837
838static void release_queues(struct port *port)
839{
840 qmgr_release_queue(RXFREE_QUEUE(port->id));
841 qmgr_release_queue(port->plat->rxq);
842 qmgr_release_queue(TX_QUEUE(port->id));
843 qmgr_release_queue(port->plat->txreadyq);
844
845 if (!ports_open)
846 qmgr_release_queue(TXDONE_QUEUE);
847}
848
849static int init_queues(struct port *port)
850{
851 int i;
852
853 if (!ports_open)
854 if (!(dma_pool = dma_pool_create(DRV_NAME, NULL,
855 POOL_ALLOC_SIZE, 32, 0)))
856 return -ENOMEM;
857
858 if (!(port->desc_tab = dma_pool_alloc(dma_pool, GFP_KERNEL,
859 &port->desc_tab_phys)))
860 return -ENOMEM;
861 memset(port->desc_tab, 0, POOL_ALLOC_SIZE);
862 memset(port->rx_buff_tab, 0, sizeof(port->rx_buff_tab)); /* tables */
863 memset(port->tx_buff_tab, 0, sizeof(port->tx_buff_tab));
864
865 /* Setup RX buffers */
866 for (i = 0; i < RX_DESCS; i++) {
867 struct desc *desc = rx_desc_ptr(port, i);
868 buffer_t *buff; /* skb or kmalloc()ated memory */
869 void *data;
870#ifdef __ARMEB__
871 if (!(buff = netdev_alloc_skb(port->netdev, RX_BUFF_SIZE)))
872 return -ENOMEM;
873 data = buff->data;
874#else
875 if (!(buff = kmalloc(RX_BUFF_SIZE, GFP_KERNEL)))
876 return -ENOMEM;
877 data = buff;
878#endif
879 desc->buf_len = MAX_MRU;
880 desc->data = dma_map_single(&port->netdev->dev, data,
881 RX_BUFF_SIZE, DMA_FROM_DEVICE);
7144decb 882 if (dma_mapping_error(&port->netdev->dev, desc->data)) {
dac2f83f
KH		 883 free_buffer(buff);
884 return -EIO;
885 }
886 desc->data += NET_IP_ALIGN;
887 port->rx_buff_tab[i] = buff;
888 }
889
890 return 0;
891}
892
893static void destroy_queues(struct port *port)
894{
895 int i;
896
897 if (port->desc_tab) {
898 for (i = 0; i < RX_DESCS; i++) {
899 struct desc *desc = rx_desc_ptr(port, i);
900 buffer_t *buff = port->rx_buff_tab[i];
901 if (buff) {
902 dma_unmap_single(&port->netdev->dev,
903 desc->data - NET_IP_ALIGN,
904 RX_BUFF_SIZE, DMA_FROM_DEVICE);
905 free_buffer(buff);
906 }
907 }
908 for (i = 0; i < TX_DESCS; i++) {
909 struct desc *desc = tx_desc_ptr(port, i);
910 buffer_t *buff = port->tx_buff_tab[i];
911 if (buff) {
912 dma_unmap_tx(port, desc);
913 free_buffer(buff);
914 }
915 }
916 dma_pool_free(dma_pool, port->desc_tab, port->desc_tab_phys);
917 port->desc_tab = NULL;
918 }
919
920 if (!ports_open && dma_pool) {
921 dma_pool_destroy(dma_pool);
922 dma_pool = NULL;
923 }
924}
925
926static int eth_open(struct net_device *dev)
927{
928 struct port *port = netdev_priv(dev);
929 struct npe *npe = port->npe;
930 struct msg msg;
931 int i, err;
932
933 if (!npe_running(npe)) {
934 err = npe_load_firmware(npe, npe_name(npe), &dev->dev);
935 if (err)
936 return err;
937
938 if (npe_recv_message(npe, &msg, "ETH_GET_STATUS")) {
939 printk(KERN_ERR "%s: %s not responding\n", dev->name,
940 npe_name(npe));
941 return -EIO;
942 }
943 }
944
dac2f83f
KH		 945 memset(&msg, 0, sizeof(msg));
946 msg.cmd = NPE_VLAN_SETRXQOSENTRY;
947 msg.eth_id = port->id;
948 msg.byte5 = port->plat->rxq | 0x80;
949 msg.byte7 = port->plat->rxq << 4;
950 for (i = 0; i < 8; i++) {
951 msg.byte3 = i;
952 if (npe_send_recv_message(port->npe, &msg, "ETH_SET_RXQ"))
953 return -EIO;
954 }
955
956 msg.cmd = NPE_EDB_SETPORTADDRESS;
957 msg.eth_id = PHYSICAL_ID(port->id);
958 msg.byte2 = dev->dev_addr[0];
959 msg.byte3 = dev->dev_addr[1];
960 msg.byte4 = dev->dev_addr[2];
961 msg.byte5 = dev->dev_addr[3];
962 msg.byte6 = dev->dev_addr[4];
963 msg.byte7 = dev->dev_addr[5];
964 if (npe_send_recv_message(port->npe, &msg, "ETH_SET_MAC"))
965 return -EIO;
966
967 memset(&msg, 0, sizeof(msg));
968 msg.cmd = NPE_FW_SETFIREWALLMODE;
969 msg.eth_id = port->id;
970 if (npe_send_recv_message(port->npe, &msg, "ETH_SET_FIREWALL_MODE"))
971 return -EIO;
972
973 if ((err = request_queues(port)) != 0)
974 return err;
975
976 if ((err = init_queues(port)) != 0) {
977 destroy_queues(port);
978 release_queues(port);
979 return err;
980 }
981
2098c18d
KH		 982 port->speed = 0; /* force "link up" message */
983 phy_start(port->phydev);
984
dac2f83f
KH		 985 for (i = 0; i < ETH_ALEN; i++)
986 __raw_writel(dev->dev_addr[i], &port->regs->hw_addr[i]);
987 __raw_writel(0x08, &port->regs->random_seed);
988 __raw_writel(0x12, &port->regs->partial_empty_threshold);
989 __raw_writel(0x30, &port->regs->partial_full_threshold);
990 __raw_writel(0x08, &port->regs->tx_start_bytes);
991 __raw_writel(0x15, &port->regs->tx_deferral);
992 __raw_writel(0x08, &port->regs->tx_2part_deferral[0]);
993 __raw_writel(0x07, &port->regs->tx_2part_deferral[1]);
994 __raw_writel(0x80, &port->regs->slot_time);
995 __raw_writel(0x01, &port->regs->int_clock_threshold);
996
997 /* Populate queues with buffers, no failure after this point */
998 for (i = 0; i < TX_DESCS; i++)
999 queue_put_desc(port->plat->txreadyq,
1000 tx_desc_phys(port, i), tx_desc_ptr(port, i));
1001
1002 for (i = 0; i < RX_DESCS; i++)
1003 queue_put_desc(RXFREE_QUEUE(port->id),
1004 rx_desc_phys(port, i), rx_desc_ptr(port, i));
1005
1006 __raw_writel(TX_CNTRL1_RETRIES, &port->regs->tx_control[1]);
1007 __raw_writel(DEFAULT_TX_CNTRL0, &port->regs->tx_control[0]);
1008 __raw_writel(0, &port->regs->rx_control[1]);
1009 __raw_writel(DEFAULT_RX_CNTRL0, &port->regs->rx_control[0]);
1010
1011 napi_enable(&port->napi);
dac2f83f
KH		 1012 eth_set_mcast_list(dev);
1013 netif_start_queue(dev);
dac2f83f
KH		 1014
1015 qmgr_set_irq(port->plat->rxq, QUEUE_IRQ_SRC_NOT_EMPTY,
1016 eth_rx_irq, dev);
1017 if (!ports_open) {
1018 qmgr_set_irq(TXDONE_QUEUE, QUEUE_IRQ_SRC_NOT_EMPTY,
1019 eth_txdone_irq, NULL);
1020 qmgr_enable_irq(TXDONE_QUEUE);
1021 }
1022 ports_open++;
1023 /* we may already have RX data, enables IRQ */
1024 netif_rx_schedule(dev, &port->napi);
1025 return 0;
1026}
1027
1028static int eth_close(struct net_device *dev)
1029{
1030 struct port *port = netdev_priv(dev);
1031 struct msg msg;
1032 int buffs = RX_DESCS; /* allocated RX buffers */
1033 int i;
1034
1035 ports_open--;
1036 qmgr_disable_irq(port->plat->rxq);
1037 napi_disable(&port->napi);
1038 netif_stop_queue(dev);
1039
1040 while (queue_get_desc(RXFREE_QUEUE(port->id), port, 0) >= 0)
1041 buffs--;
1042
1043 memset(&msg, 0, sizeof(msg));
1044 msg.cmd = NPE_SETLOOPBACK_MODE;
1045 msg.eth_id = port->id;
1046 msg.byte3 = 1;
1047 if (npe_send_recv_message(port->npe, &msg, "ETH_ENABLE_LOOPBACK"))
1048 printk(KERN_CRIT "%s: unable to enable loopback\n", dev->name);
1049
1050 i = 0;
1051 do { /* drain RX buffers */
1052 while (queue_get_desc(port->plat->rxq, port, 0) >= 0)
1053 buffs--;
1054 if (!buffs)
1055 break;
1056 if (qmgr_stat_empty(TX_QUEUE(port->id))) {
1057 /* we have to inject some packet */
1058 struct desc *desc;
1059 u32 phys;
1060 int n = queue_get_desc(port->plat->txreadyq, port, 1);
1061 BUG_ON(n < 0);
1062 desc = tx_desc_ptr(port, n);
1063 phys = tx_desc_phys(port, n);
1064 desc->buf_len = desc->pkt_len = 1;
1065 wmb();
1066 queue_put_desc(TX_QUEUE(port->id), phys, desc);
1067 }
1068 udelay(1);
1069 } while (++i < MAX_CLOSE_WAIT);
1070
1071 if (buffs)
1072 printk(KERN_CRIT "%s: unable to drain RX queue, %i buffer(s)"
1073 " left in NPE\n", dev->name, buffs);
1074#if DEBUG_CLOSE
1075 if (!buffs)
1076 printk(KERN_DEBUG "Draining RX queue took %i cycles\n", i);
1077#endif
1078
1079 buffs = TX_DESCS;
1080 while (queue_get_desc(TX_QUEUE(port->id), port, 1) >= 0)
1081 buffs--; /* cancel TX */
1082
1083 i = 0;
1084 do {
1085 while (queue_get_desc(port->plat->txreadyq, port, 1) >= 0)
1086 buffs--;
1087 if (!buffs)
1088 break;
1089 } while (++i < MAX_CLOSE_WAIT);
1090
1091 if (buffs)
1092 printk(KERN_CRIT "%s: unable to drain TX queue, %i buffer(s) "
1093 "left in NPE\n", dev->name, buffs);
1094#if DEBUG_CLOSE
1095 if (!buffs)
1096 printk(KERN_DEBUG "Draining TX queues took %i cycles\n", i);
1097#endif
1098
1099 msg.byte3 = 0;
1100 if (npe_send_recv_message(port->npe, &msg, "ETH_DISABLE_LOOPBACK"))
1101 printk(KERN_CRIT "%s: unable to disable loopback\n",
1102 dev->name);
1103
2098c18d 1104 phy_stop(port->phydev);
dac2f83f
KH		 1105
1106 if (!ports_open)
1107 qmgr_disable_irq(TXDONE_QUEUE);
dac2f83f
KH		 1108 destroy_queues(port);
1109 release_queues(port);
1110 return 0;
1111}
1112
1113static int __devinit eth_init_one(struct platform_device *pdev)
1114{
1115 struct port *port;
1116 struct net_device *dev;
1117 struct eth_plat_info *plat = pdev->dev.platform_data;
1118 u32 regs_phys;
2098c18d 1119 char phy_id[BUS_ID_SIZE];
dac2f83f
KH		 1120 int err;
1121
1122 if (!(dev = alloc_etherdev(sizeof(struct port))))
1123 return -ENOMEM;
1124
1125 SET_NETDEV_DEV(dev, &pdev->dev);
1126 port = netdev_priv(dev);
1127 port->netdev = dev;
1128 port->id = pdev->id;
1129
1130 switch (port->id) {
1131 case IXP4XX_ETH_NPEA:
1132 port->regs = (struct eth_regs __iomem *)IXP4XX_EthA_BASE_VIRT;
1133 regs_phys = IXP4XX_EthA_BASE_PHYS;
1134 break;
1135 case IXP4XX_ETH_NPEB:
1136 port->regs = (struct eth_regs __iomem *)IXP4XX_EthB_BASE_VIRT;
1137 regs_phys = IXP4XX_EthB_BASE_PHYS;
1138 break;
1139 case IXP4XX_ETH_NPEC:
1140 port->regs = (struct eth_regs __iomem *)IXP4XX_EthC_BASE_VIRT;
1141 regs_phys = IXP4XX_EthC_BASE_PHYS;
1142 break;
1143 default:
1144 err = -ENOSYS;
1145 goto err_free;
1146 }
1147
1148 dev->open = eth_open;
1149 dev->hard_start_xmit = eth_xmit;
1150 dev->stop = eth_close;
dac2f83f
KH		 1151 dev->do_ioctl = eth_ioctl;
1152 dev->set_multicast_list = eth_set_mcast_list;
1153 dev->tx_queue_len = 100;
1154
1155 netif_napi_add(dev, &port->napi, eth_poll, NAPI_WEIGHT);
1156
1157 if (!(port->npe = npe_request(NPE_ID(port->id)))) {
1158 err = -EIO;
1159 goto err_free;
1160 }
1161
1162 if (register_netdev(dev)) {
1163 err = -EIO;
1164 goto err_npe_rel;
1165 }
1166
1167 port->mem_res = request_mem_region(regs_phys, REGS_SIZE, dev->name);
1168 if (!port->mem_res) {
1169 err = -EBUSY;
1170 goto err_unreg;
1171 }
1172
1173 port->plat = plat;
1174 npe_port_tab[NPE_ID(port->id)] = port;
1175 memcpy(dev->dev_addr, plat->hwaddr, ETH_ALEN);
1176
1177 platform_set_drvdata(pdev, dev);
1178
1179 __raw_writel(DEFAULT_CORE_CNTRL | CORE_RESET,
1180 &port->regs->core_control);
1181 udelay(50);
1182 __raw_writel(DEFAULT_CORE_CNTRL, &port->regs->core_control);
1183 udelay(50);
1184
2098c18d
KH		 1185 snprintf(phy_id, BUS_ID_SIZE, PHY_ID_FMT, "0", plat->phy);
1186 port->phydev = phy_connect(dev, phy_id, &ixp4xx_adjust_link, 0,
1187 PHY_INTERFACE_MODE_MII);
1188 if (IS_ERR(port->phydev)) {
1189 printk(KERN_ERR "%s: Could not attach to PHY\n", dev->name);
1190 return PTR_ERR(port->phydev);
1191 }
1192
1193 port->phydev->irq = PHY_POLL;
dac2f83f
KH		 1194
1195 printk(KERN_INFO "%s: MII PHY %i on %s\n", dev->name, plat->phy,
1196 npe_name(port->npe));
1197
dac2f83f
KH		 1198 return 0;
1199
1200err_unreg:
1201 unregister_netdev(dev);
1202err_npe_rel:
1203 npe_release(port->npe);
1204err_free:
1205 free_netdev(dev);
1206 return err;
1207}
1208
1209static int __devexit eth_remove_one(struct platform_device *pdev)
1210{
1211 struct net_device *dev = platform_get_drvdata(pdev);
1212 struct port *port = netdev_priv(dev);
1213
1214 unregister_netdev(dev);
1215 npe_port_tab[NPE_ID(port->id)] = NULL;
1216 platform_set_drvdata(pdev, NULL);
1217 npe_release(port->npe);
1218 release_resource(port->mem_res);
1219 free_netdev(dev);
1220 return 0;
1221}
1222
3c36a837 1223static struct platform_driver ixp4xx_eth_driver = {
dac2f83f
KH		 1224 .driver.name = DRV_NAME,
1225 .probe = eth_init_one,
1226 .remove = eth_remove_one,
1227};
1228
1229static int __init eth_init_module(void)
1230{
2098c18d 1231 int err;
dac2f83f
KH		 1232 if (!(ixp4xx_read_feature_bits() & IXP4XX_FEATURE_NPEB_ETH0))
1233 return -ENOSYS;
1234
2098c18d
KH		 1235 if ((err = ixp4xx_mdio_register()))
1236 return err;
3c36a837 1237 return platform_driver_register(&ixp4xx_eth_driver);
dac2f83f
KH		 1238}
1239
1240static void __exit eth_cleanup_module(void)
1241{
3c36a837 1242 platform_driver_unregister(&ixp4xx_eth_driver);
2098c18d 1243 ixp4xx_mdio_remove();
dac2f83f
KH		 1244}
1245
1246MODULE_AUTHOR("Krzysztof Halasa");
1247MODULE_DESCRIPTION("Intel IXP4xx Ethernet driver");
1248MODULE_LICENSE("GPL v2");
1249MODULE_ALIAS("platform:ixp4xx_eth");
1250module_init(eth_init_module);
1251module_exit(eth_cleanup_module);
Linux kernel - Deliverables
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