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IXP4xx: Ethernet and WAN drivers now support "high" hardware queues.
[deliverable/linux.git] / drivers / net / arm / ixp4xx_eth.c
CommitLineData
dac2f83f
KH		 1/*
2 * Intel IXP4xx Ethernet driver for Linux
3 *
4 * Copyright (C) 2007 Krzysztof Halasa <khc@pm.waw.pl>
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of version 2 of the GNU General Public License
8 * as published by the Free Software Foundation.
9 *
10 * Ethernet port config (0x00 is not present on IXP42X):
11 *
12 * logical port 0x00 0x10 0x20
13 * NPE 0 (NPE-A) 1 (NPE-B) 2 (NPE-C)
14 * physical PortId 2 0 1
15 * TX queue 23 24 25
16 * RX-free queue 26 27 28
17 * TX-done queue is always 31, per-port RX and TX-ready queues are configurable
18 *
19 *
20 * Queue entries:
21 * bits 0 -> 1 - NPE ID (RX and TX-done)
22 * bits 0 -> 2 - priority (TX, per 802.1D)
23 * bits 3 -> 4 - port ID (user-set?)
24 * bits 5 -> 31 - physical descriptor address
25 */
26
27#include <linux/delay.h>
28#include <linux/dma-mapping.h>
29#include <linux/dmapool.h>
30#include <linux/etherdevice.h>
31#include <linux/io.h>
32#include <linux/kernel.h>
2098c18d 33#include <linux/phy.h>
dac2f83f 34#include <linux/platform_device.h>
a09e64fb
RK		 35#include <mach/npe.h>
36#include <mach/qmgr.h>
dac2f83f 37
dac2f83f
KH		 38#define DEBUG_DESC 0
39#define DEBUG_RX 0
40#define DEBUG_TX 0
41#define DEBUG_PKT_BYTES 0
42#define DEBUG_MDIO 0
43#define DEBUG_CLOSE 0
44
45#define DRV_NAME "ixp4xx_eth"
46
47#define MAX_NPES 3
48
49#define RX_DESCS 64 /* also length of all RX queues */
50#define TX_DESCS 16 /* also length of all TX queues */
51#define TXDONE_QUEUE_LEN 64 /* dwords */
52
53#define POOL_ALLOC_SIZE (sizeof(struct desc) * (RX_DESCS + TX_DESCS))
54#define REGS_SIZE 0x1000
55#define MAX_MRU 1536 /* 0x600 */
56#define RX_BUFF_SIZE ALIGN((NET_IP_ALIGN) + MAX_MRU, 4)
57
58#define NAPI_WEIGHT 16
59#define MDIO_INTERVAL (3 * HZ)
60#define MAX_MDIO_RETRIES 100 /* microseconds, typically 30 cycles */
dac2f83f
KH		 61#define MAX_CLOSE_WAIT 1000 /* microseconds, typically 2-3 cycles */
62
63#define NPE_ID(port_id) ((port_id) >> 4)
64#define PHYSICAL_ID(port_id) ((NPE_ID(port_id) + 2) % 3)
65#define TX_QUEUE(port_id) (NPE_ID(port_id) + 23)
66#define RXFREE_QUEUE(port_id) (NPE_ID(port_id) + 26)
67#define TXDONE_QUEUE 31
68
69/* TX Control Registers */
70#define TX_CNTRL0_TX_EN 0x01
71#define TX_CNTRL0_HALFDUPLEX 0x02
72#define TX_CNTRL0_RETRY 0x04
73#define TX_CNTRL0_PAD_EN 0x08
74#define TX_CNTRL0_APPEND_FCS 0x10
75#define TX_CNTRL0_2DEFER 0x20
76#define TX_CNTRL0_RMII 0x40 /* reduced MII */
77#define TX_CNTRL1_RETRIES 0x0F /* 4 bits */
78
79/* RX Control Registers */
80#define RX_CNTRL0_RX_EN 0x01
81#define RX_CNTRL0_PADSTRIP_EN 0x02
82#define RX_CNTRL0_SEND_FCS 0x04
83#define RX_CNTRL0_PAUSE_EN 0x08
84#define RX_CNTRL0_LOOP_EN 0x10
85#define RX_CNTRL0_ADDR_FLTR_EN 0x20
86#define RX_CNTRL0_RX_RUNT_EN 0x40
87#define RX_CNTRL0_BCAST_DIS 0x80
88#define RX_CNTRL1_DEFER_EN 0x01
89
90/* Core Control Register */
91#define CORE_RESET 0x01
92#define CORE_RX_FIFO_FLUSH 0x02
93#define CORE_TX_FIFO_FLUSH 0x04
94#define CORE_SEND_JAM 0x08
95#define CORE_MDC_EN 0x10 /* MDIO using NPE-B ETH-0 only */
96
97#define DEFAULT_TX_CNTRL0 (TX_CNTRL0_TX_EN | TX_CNTRL0_RETRY | \
98 TX_CNTRL0_PAD_EN | TX_CNTRL0_APPEND_FCS | \
99 TX_CNTRL0_2DEFER)
100#define DEFAULT_RX_CNTRL0 RX_CNTRL0_RX_EN
101#define DEFAULT_CORE_CNTRL CORE_MDC_EN
102
103
104/* NPE message codes */
105#define NPE_GETSTATUS 0x00
106#define NPE_EDB_SETPORTADDRESS 0x01
107#define NPE_EDB_GETMACADDRESSDATABASE 0x02
108#define NPE_EDB_SETMACADDRESSSDATABASE 0x03
109#define NPE_GETSTATS 0x04
110#define NPE_RESETSTATS 0x05
111#define NPE_SETMAXFRAMELENGTHS 0x06
112#define NPE_VLAN_SETRXTAGMODE 0x07
113#define NPE_VLAN_SETDEFAULTRXVID 0x08
114#define NPE_VLAN_SETPORTVLANTABLEENTRY 0x09
115#define NPE_VLAN_SETPORTVLANTABLERANGE 0x0A
116#define NPE_VLAN_SETRXQOSENTRY 0x0B
117#define NPE_VLAN_SETPORTIDEXTRACTIONMODE 0x0C
118#define NPE_STP_SETBLOCKINGSTATE 0x0D
119#define NPE_FW_SETFIREWALLMODE 0x0E
120#define NPE_PC_SETFRAMECONTROLDURATIONID 0x0F
121#define NPE_PC_SETAPMACTABLE 0x11
122#define NPE_SETLOOPBACK_MODE 0x12
123#define NPE_PC_SETBSSIDTABLE 0x13
124#define NPE_ADDRESS_FILTER_CONFIG 0x14
125#define NPE_APPENDFCSCONFIG 0x15
126#define NPE_NOTIFY_MAC_RECOVERY_DONE 0x16
127#define NPE_MAC_RECOVERY_START 0x17
128
129
130#ifdef __ARMEB__
131typedef struct sk_buff buffer_t;
132#define free_buffer dev_kfree_skb
133#define free_buffer_irq dev_kfree_skb_irq
134#else
135typedef void buffer_t;
136#define free_buffer kfree
137#define free_buffer_irq kfree
138#endif
139
140struct eth_regs {
141 u32 tx_control[2], __res1[2]; /* 000 */
142 u32 rx_control[2], __res2[2]; /* 010 */
143 u32 random_seed, __res3[3]; /* 020 */
144 u32 partial_empty_threshold, __res4; /* 030 */
145 u32 partial_full_threshold, __res5; /* 038 */
146 u32 tx_start_bytes, __res6[3]; /* 040 */
147 u32 tx_deferral, rx_deferral, __res7[2];/* 050 */
148 u32 tx_2part_deferral[2], __res8[2]; /* 060 */
149 u32 slot_time, __res9[3]; /* 070 */
150 u32 mdio_command[4]; /* 080 */
151 u32 mdio_status[4]; /* 090 */
152 u32 mcast_mask[6], __res10[2]; /* 0A0 */
153 u32 mcast_addr[6], __res11[2]; /* 0C0 */
154 u32 int_clock_threshold, __res12[3]; /* 0E0 */
155 u32 hw_addr[6], __res13[61]; /* 0F0 */
156 u32 core_control; /* 1FC */
157};
158
159struct port {
160 struct resource *mem_res;
161 struct eth_regs __iomem *regs;
162 struct npe *npe;
163 struct net_device *netdev;
164 struct napi_struct napi;
2098c18d 165 struct phy_device *phydev;
dac2f83f
KH		 166 struct eth_plat_info *plat;
167 buffer_t *rx_buff_tab[RX_DESCS], *tx_buff_tab[TX_DESCS];
168 struct desc *desc_tab; /* coherent */
169 u32 desc_tab_phys;
170 int id; /* logical port ID */
2098c18d 171 int speed, duplex;
490b7722 172 u8 firmware[4];
dac2f83f
KH		 173};
174
175/* NPE message structure */
176struct msg {
177#ifdef __ARMEB__
178 u8 cmd, eth_id, byte2, byte3;
179 u8 byte4, byte5, byte6, byte7;
180#else
181 u8 byte3, byte2, eth_id, cmd;
182 u8 byte7, byte6, byte5, byte4;
183#endif
184};
185
186/* Ethernet packet descriptor */
187struct desc {
188 u32 next; /* pointer to next buffer, unused */
189
190#ifdef __ARMEB__
191 u16 buf_len; /* buffer length */
192 u16 pkt_len; /* packet length */
193 u32 data; /* pointer to data buffer in RAM */
194 u8 dest_id;
195 u8 src_id;
196 u16 flags;
197 u8 qos;
198 u8 padlen;
199 u16 vlan_tci;
200#else
201 u16 pkt_len; /* packet length */
202 u16 buf_len; /* buffer length */
203 u32 data; /* pointer to data buffer in RAM */
204 u16 flags;
205 u8 src_id;
206 u8 dest_id;
207 u16 vlan_tci;
208 u8 padlen;
209 u8 qos;
210#endif
211
212#ifdef __ARMEB__
213 u8 dst_mac_0, dst_mac_1, dst_mac_2, dst_mac_3;
214 u8 dst_mac_4, dst_mac_5, src_mac_0, src_mac_1;
215 u8 src_mac_2, src_mac_3, src_mac_4, src_mac_5;
216#else
217 u8 dst_mac_3, dst_mac_2, dst_mac_1, dst_mac_0;
218 u8 src_mac_1, src_mac_0, dst_mac_5, dst_mac_4;
219 u8 src_mac_5, src_mac_4, src_mac_3, src_mac_2;
220#endif
221};
222
223
224#define rx_desc_phys(port, n) ((port)->desc_tab_phys + \
225 (n) * sizeof(struct desc))
226#define rx_desc_ptr(port, n) (&(port)->desc_tab[n])
227
228#define tx_desc_phys(port, n) ((port)->desc_tab_phys + \
229 ((n) + RX_DESCS) * sizeof(struct desc))
230#define tx_desc_ptr(port, n) (&(port)->desc_tab[(n) + RX_DESCS])
231
232#ifndef __ARMEB__
233static inline void memcpy_swab32(u32 *dest, u32 *src, int cnt)
234{
235 int i;
236 for (i = 0; i < cnt; i++)
237 dest[i] = swab32(src[i]);
238}
239#endif
240
241static spinlock_t mdio_lock;
242static struct eth_regs __iomem *mdio_regs; /* mdio command and status only */
2098c18d 243struct mii_bus *mdio_bus;
dac2f83f
KH		 244static int ports_open;
245static struct port *npe_port_tab[MAX_NPES];
246static struct dma_pool *dma_pool;
247
248
2098c18d
KH		 249static int ixp4xx_mdio_cmd(struct mii_bus *bus, int phy_id, int location,
250 int write, u16 cmd)
dac2f83f
KH		 251{
252 int cycles = 0;
253
254 if (__raw_readl(&mdio_regs->mdio_command[3]) & 0x80) {
2098c18d
KH		 255 printk(KERN_ERR "%s: MII not ready to transmit\n", bus->name);
256 return -1;
dac2f83f
KH		 257 }
258
259 if (write) {
260 __raw_writel(cmd & 0xFF, &mdio_regs->mdio_command[0]);
261 __raw_writel(cmd >> 8, &mdio_regs->mdio_command[1]);
262 }
263 __raw_writel(((phy_id << 5) | location) & 0xFF,
264 &mdio_regs->mdio_command[2]);
265 __raw_writel((phy_id >> 3) | (write << 2) | 0x80 /* GO */,
266 &mdio_regs->mdio_command[3]);
267
268 while ((cycles < MAX_MDIO_RETRIES) &&
269 (__raw_readl(&mdio_regs->mdio_command[3]) & 0x80)) {
270 udelay(1);
271 cycles++;
272 }
273
274 if (cycles == MAX_MDIO_RETRIES) {
2098c18d
KH		 275 printk(KERN_ERR "%s #%i: MII write failed\n", bus->name,
276 phy_id);
277 return -1;
dac2f83f
KH		 278 }
279
280#if DEBUG_MDIO
2098c18d
KH		 281 printk(KERN_DEBUG "%s #%i: mdio_%s() took %i cycles\n", bus->name,
282 phy_id, write ? "write" : "read", cycles);
dac2f83f
KH		 283#endif
284
285 if (write)
286 return 0;
287
288 if (__raw_readl(&mdio_regs->mdio_status[3]) & 0x80) {
2098c18d
KH		 289#if DEBUG_MDIO
290 printk(KERN_DEBUG "%s #%i: MII read failed\n", bus->name,
291 phy_id);
292#endif
293 return 0xFFFF; /* don't return error */
dac2f83f
KH		 294 }
295
296 return (__raw_readl(&mdio_regs->mdio_status[0]) & 0xFF) |
2098c18d 297 ((__raw_readl(&mdio_regs->mdio_status[1]) & 0xFF) << 8);
dac2f83f
KH		 298}
299
2098c18d 300static int ixp4xx_mdio_read(struct mii_bus *bus, int phy_id, int location)
dac2f83f
KH		 301{
302 unsigned long flags;
2098c18d 303 int ret;
dac2f83f
KH		 304
305 spin_lock_irqsave(&mdio_lock, flags);
2098c18d 306 ret = ixp4xx_mdio_cmd(bus, phy_id, location, 0, 0);
dac2f83f 307 spin_unlock_irqrestore(&mdio_lock, flags);
2098c18d
KH		 308#if DEBUG_MDIO
309 printk(KERN_DEBUG "%s #%i: MII read [%i] -> 0x%X\n", bus->name,
310 phy_id, location, ret);
311#endif
312 return ret;
dac2f83f
KH		 313}
314
2098c18d
KH		 315static int ixp4xx_mdio_write(struct mii_bus *bus, int phy_id, int location,
316 u16 val)
dac2f83f
KH		 317{
318 unsigned long flags;
2098c18d 319 int ret;
dac2f83f
KH		 320
321 spin_lock_irqsave(&mdio_lock, flags);
2098c18d 322 ret = ixp4xx_mdio_cmd(bus, phy_id, location, 1, val);
dac2f83f 323 spin_unlock_irqrestore(&mdio_lock, flags);
2098c18d
KH		 324#if DEBUG_MDIO
325 printk(KERN_DEBUG "%s #%i: MII read [%i] <- 0x%X, err = %i\n",
326 bus->name, phy_id, location, val, ret);
327#endif
328 return ret;
dac2f83f
KH		 329}
330
2098c18d 331static int ixp4xx_mdio_register(void)
dac2f83f 332{
2098c18d 333 int err;
dac2f83f 334
2098c18d
KH		 335 if (!(mdio_bus = mdiobus_alloc()))
336 return -ENOMEM;
dac2f83f 337
5ca328d2
KH		 338 if (cpu_is_ixp43x()) {
339 /* IXP43x lacks NPE-B and uses NPE-C for MII PHY access */
340 if (!(ixp4xx_read_feature_bits() & IXP4XX_FEATURE_NPEC_ETH))
3ba8c792 341 return -ENODEV;
5ca328d2
KH		 342 mdio_regs = (struct eth_regs __iomem *)IXP4XX_EthC_BASE_VIRT;
343 } else {
344 /* All MII PHY accesses use NPE-B Ethernet registers */
345 if (!(ixp4xx_read_feature_bits() & IXP4XX_FEATURE_NPEB_ETH0))
3ba8c792 346 return -ENODEV;
5ca328d2
KH		 347 mdio_regs = (struct eth_regs __iomem *)IXP4XX_EthB_BASE_VIRT;
348 }
dac2f83f 349
5ca328d2
KH		 350 __raw_writel(DEFAULT_CORE_CNTRL, &mdio_regs->core_control);
351 spin_lock_init(&mdio_lock);
2098c18d
KH		 352 mdio_bus->name = "IXP4xx MII Bus";
353 mdio_bus->read = &ixp4xx_mdio_read;
354 mdio_bus->write = &ixp4xx_mdio_write;
355 strcpy(mdio_bus->id, "0");
dac2f83f 356
2098c18d
KH		 357 if ((err = mdiobus_register(mdio_bus)))
358 mdiobus_free(mdio_bus);
359 return err;
dac2f83f
KH		 360}
361
2098c18d 362static void ixp4xx_mdio_remove(void)
dac2f83f 363{
2098c18d
KH		 364 mdiobus_unregister(mdio_bus);
365 mdiobus_free(mdio_bus);
dac2f83f
KH		 366}
367
368
2098c18d 369static void ixp4xx_adjust_link(struct net_device *dev)
dac2f83f 370{
2098c18d
KH		 371 struct port *port = netdev_priv(dev);
372 struct phy_device *phydev = port->phydev;
373
374 if (!phydev->link) {
375 if (port->speed) {
376 port->speed = 0;
dac2f83f 377 printk(KERN_INFO "%s: link down\n", dev->name);
dac2f83f 378 }
2098c18d 379 return;
dac2f83f 380 }
dac2f83f 381
2098c18d
KH		 382 if (port->speed == phydev->speed && port->duplex == phydev->duplex)
383 return;
dac2f83f 384
2098c18d
KH		 385 port->speed = phydev->speed;
386 port->duplex = phydev->duplex;
dac2f83f 387
2098c18d
KH		 388 if (port->duplex)
389 __raw_writel(DEFAULT_TX_CNTRL0 & ~TX_CNTRL0_HALFDUPLEX,
390 &port->regs->tx_control[0]);
391 else
392 __raw_writel(DEFAULT_TX_CNTRL0 | TX_CNTRL0_HALFDUPLEX,
393 &port->regs->tx_control[0]);
dac2f83f 394
2098c18d
KH		 395 printk(KERN_INFO "%s: link up, speed %u Mb/s, %s duplex\n",
396 dev->name, port->speed, port->duplex ? "full" : "half");
dac2f83f
KH		 397}
398
399
400static inline void debug_pkt(struct net_device *dev, const char *func,
401 u8 *data, int len)
402{
403#if DEBUG_PKT_BYTES
404 int i;
405
406 printk(KERN_DEBUG "%s: %s(%i) ", dev->name, func, len);
407 for (i = 0; i < len; i++) {
408 if (i >= DEBUG_PKT_BYTES)
409 break;
410 printk("%s%02X",
411 ((i == 6) || (i == 12) || (i >= 14)) ? " " : "",
412 data[i]);
413 }
414 printk("\n");
415#endif
416}
417
418
419static inline void debug_desc(u32 phys, struct desc *desc)
420{
421#if DEBUG_DESC
422 printk(KERN_DEBUG "%X: %X %3X %3X %08X %2X < %2X %4X %X"
423 " %X %X %02X%02X%02X%02X%02X%02X < %02X%02X%02X%02X%02X%02X\n",
424 phys, desc->next, desc->buf_len, desc->pkt_len,
425 desc->data, desc->dest_id, desc->src_id, desc->flags,
426 desc->qos, desc->padlen, desc->vlan_tci,
427 desc->dst_mac_0, desc->dst_mac_1, desc->dst_mac_2,
428 desc->dst_mac_3, desc->dst_mac_4, desc->dst_mac_5,
429 desc->src_mac_0, desc->src_mac_1, desc->src_mac_2,
430 desc->src_mac_3, desc->src_mac_4, desc->src_mac_5);
431#endif
432}
433
dac2f83f
KH		 434static inline int queue_get_desc(unsigned int queue, struct port *port,
435 int is_tx)
436{
437 u32 phys, tab_phys, n_desc;
438 struct desc *tab;
439
e6da96ac 440 if (!(phys = qmgr_get_entry(queue)))
dac2f83f
KH		 441 return -1;
442
443 phys &= ~0x1F; /* mask out non-address bits */
444 tab_phys = is_tx ? tx_desc_phys(port, 0) : rx_desc_phys(port, 0);
445 tab = is_tx ? tx_desc_ptr(port, 0) : rx_desc_ptr(port, 0);
446 n_desc = (phys - tab_phys) / sizeof(struct desc);
447 BUG_ON(n_desc >= (is_tx ? TX_DESCS : RX_DESCS));
448 debug_desc(phys, &tab[n_desc]);
449 BUG_ON(tab[n_desc].next);
450 return n_desc;
451}
452
453static inline void queue_put_desc(unsigned int queue, u32 phys,
454 struct desc *desc)
455{
dac2f83f
KH		 456 debug_desc(phys, desc);
457 BUG_ON(phys & 0x1F);
458 qmgr_put_entry(queue, phys);
6a68afe3
KH		 459 /* Don't check for queue overflow here, we've allocated sufficient
460 length and queues >= 32 don't support this check anyway. */
dac2f83f
KH		 461}
462
463
464static inline void dma_unmap_tx(struct port *port, struct desc *desc)
465{
466#ifdef __ARMEB__
467 dma_unmap_single(&port->netdev->dev, desc->data,
468 desc->buf_len, DMA_TO_DEVICE);
469#else
470 dma_unmap_single(&port->netdev->dev, desc->data & ~3,
471 ALIGN((desc->data & 3) + desc->buf_len, 4),
472 DMA_TO_DEVICE);
473#endif
474}
475
476
477static void eth_rx_irq(void *pdev)
478{
479 struct net_device *dev = pdev;
480 struct port *port = netdev_priv(dev);
481
482#if DEBUG_RX
483 printk(KERN_DEBUG "%s: eth_rx_irq\n", dev->name);
484#endif
485 qmgr_disable_irq(port->plat->rxq);
288379f0 486 napi_schedule(&port->napi);
dac2f83f
KH		 487}
488
489static int eth_poll(struct napi_struct *napi, int budget)
490{
491 struct port *port = container_of(napi, struct port, napi);
492 struct net_device *dev = port->netdev;
493 unsigned int rxq = port->plat->rxq, rxfreeq = RXFREE_QUEUE(port->id);
494 int received = 0;
495
496#if DEBUG_RX
497 printk(KERN_DEBUG "%s: eth_poll\n", dev->name);
498#endif
499
500 while (received < budget) {
501 struct sk_buff *skb;
502 struct desc *desc;
503 int n;
504#ifdef __ARMEB__
505 struct sk_buff *temp;
506 u32 phys;
507#endif
508
509 if ((n = queue_get_desc(rxq, port, 0)) < 0) {
dac2f83f 510#if DEBUG_RX
288379f0 511 printk(KERN_DEBUG "%s: eth_poll napi_complete\n",
dac2f83f
KH		 512 dev->name);
513#endif
288379f0 514 napi_complete(napi);
dac2f83f 515 qmgr_enable_irq(rxq);
6a68afe3
KH		 516 if (!qmgr_stat_nearly_empty(rxq) &&
517 napi_reschedule(napi)) { /* really empty in fact */
dac2f83f
KH		 518#if DEBUG_RX
519 printk(KERN_DEBUG "%s: eth_poll"
288379f0 520 " napi_reschedule successed\n",
dac2f83f
KH		 521 dev->name);
522#endif
523 qmgr_disable_irq(rxq);
524 continue;
525 }
526#if DEBUG_RX
527 printk(KERN_DEBUG "%s: eth_poll all done\n",
528 dev->name);
529#endif
9076689a 530 return received; /* all work done */
dac2f83f
KH		 531 }
532
533 desc = rx_desc_ptr(port, n);
534
535#ifdef __ARMEB__
536 if ((skb = netdev_alloc_skb(dev, RX_BUFF_SIZE))) {
537 phys = dma_map_single(&dev->dev, skb->data,
538 RX_BUFF_SIZE, DMA_FROM_DEVICE);
7144decb 539 if (dma_mapping_error(&dev->dev, phys)) {
dac2f83f
KH		 540 dev_kfree_skb(skb);
541 skb = NULL;
542 }
543 }
544#else
545 skb = netdev_alloc_skb(dev,
546 ALIGN(NET_IP_ALIGN + desc->pkt_len, 4));
547#endif
548
549 if (!skb) {
b4c7d3b0 550 dev->stats.rx_dropped++;
dac2f83f
KH		 551 /* put the desc back on RX-ready queue */
552 desc->buf_len = MAX_MRU;
553 desc->pkt_len = 0;
554 queue_put_desc(rxfreeq, rx_desc_phys(port, n), desc);
555 continue;
556 }
557
558 /* process received frame */
559#ifdef __ARMEB__
560 temp = skb;
561 skb = port->rx_buff_tab[n];
562 dma_unmap_single(&dev->dev, desc->data - NET_IP_ALIGN,
563 RX_BUFF_SIZE, DMA_FROM_DEVICE);
564#else
565 dma_sync_single(&dev->dev, desc->data - NET_IP_ALIGN,
566 RX_BUFF_SIZE, DMA_FROM_DEVICE);
567 memcpy_swab32((u32 *)skb->data, (u32 *)port->rx_buff_tab[n],
568 ALIGN(NET_IP_ALIGN + desc->pkt_len, 4) / 4);
569#endif
570 skb_reserve(skb, NET_IP_ALIGN);
571 skb_put(skb, desc->pkt_len);
572
573 debug_pkt(dev, "eth_poll", skb->data, skb->len);
574
575 skb->protocol = eth_type_trans(skb, dev);
b4c7d3b0
KH		 576 dev->stats.rx_packets++;
577 dev->stats.rx_bytes += skb->len;
dac2f83f
KH		 578 netif_receive_skb(skb);
579
580 /* put the new buffer on RX-free queue */
581#ifdef __ARMEB__
582 port->rx_buff_tab[n] = temp;
583 desc->data = phys + NET_IP_ALIGN;
584#endif
585 desc->buf_len = MAX_MRU;
586 desc->pkt_len = 0;
587 queue_put_desc(rxfreeq, rx_desc_phys(port, n), desc);
588 received++;
589 }
590
591#if DEBUG_RX
592 printk(KERN_DEBUG "eth_poll(): end, not all work done\n");
593#endif
594 return received; /* not all work done */
595}
596
597
598static void eth_txdone_irq(void *unused)
599{
600 u32 phys;
601
602#if DEBUG_TX
603 printk(KERN_DEBUG DRV_NAME ": eth_txdone_irq\n");
604#endif
e6da96ac 605 while ((phys = qmgr_get_entry(TXDONE_QUEUE)) != 0) {
dac2f83f
KH		 606 u32 npe_id, n_desc;
607 struct port *port;
608 struct desc *desc;
609 int start;
610
611 npe_id = phys & 3;
612 BUG_ON(npe_id >= MAX_NPES);
613 port = npe_port_tab[npe_id];
614 BUG_ON(!port);
615 phys &= ~0x1F; /* mask out non-address bits */
616 n_desc = (phys - tx_desc_phys(port, 0)) / sizeof(struct desc);
617 BUG_ON(n_desc >= TX_DESCS);
618 desc = tx_desc_ptr(port, n_desc);
619 debug_desc(phys, desc);
620
621 if (port->tx_buff_tab[n_desc]) { /* not the draining packet */
b4c7d3b0
KH		 622 port->netdev->stats.tx_packets++;
623 port->netdev->stats.tx_bytes += desc->pkt_len;
dac2f83f
KH		 624
625 dma_unmap_tx(port, desc);
626#if DEBUG_TX
627 printk(KERN_DEBUG "%s: eth_txdone_irq free %p\n",
628 port->netdev->name, port->tx_buff_tab[n_desc]);
629#endif
630 free_buffer_irq(port->tx_buff_tab[n_desc]);
631 port->tx_buff_tab[n_desc] = NULL;
632 }
633
6a68afe3
KH		 634 /* really empty in fact */
635 start = qmgr_stat_nearly_empty(port->plat->txreadyq);
dac2f83f
KH		 636 queue_put_desc(port->plat->txreadyq, phys, desc);
637 if (start) {
638#if DEBUG_TX
639 printk(KERN_DEBUG "%s: eth_txdone_irq xmit ready\n",
640 port->netdev->name);
641#endif
642 netif_wake_queue(port->netdev);
643 }
644 }
645}
646
647static int eth_xmit(struct sk_buff *skb, struct net_device *dev)
648{
649 struct port *port = netdev_priv(dev);
650 unsigned int txreadyq = port->plat->txreadyq;
651 int len, offset, bytes, n;
652 void *mem;
653 u32 phys;
654 struct desc *desc;
655
656#if DEBUG_TX
657 printk(KERN_DEBUG "%s: eth_xmit\n", dev->name);
658#endif
659
660 if (unlikely(skb->len > MAX_MRU)) {
661 dev_kfree_skb(skb);
b4c7d3b0 662 dev->stats.tx_errors++;
dac2f83f
KH		 663 return NETDEV_TX_OK;
664 }
665
666 debug_pkt(dev, "eth_xmit", skb->data, skb->len);
667
668 len = skb->len;
669#ifdef __ARMEB__
670 offset = 0; /* no need to keep alignment */
671 bytes = len;
672 mem = skb->data;
673#else
674 offset = (int)skb->data & 3; /* keep 32-bit alignment */
675 bytes = ALIGN(offset + len, 4);
676 if (!(mem = kmalloc(bytes, GFP_ATOMIC))) {
677 dev_kfree_skb(skb);
b4c7d3b0 678 dev->stats.tx_dropped++;
dac2f83f
KH		 679 return NETDEV_TX_OK;
680 }
681 memcpy_swab32(mem, (u32 *)((int)skb->data & ~3), bytes / 4);
682 dev_kfree_skb(skb);
683#endif
684
685 phys = dma_map_single(&dev->dev, mem, bytes, DMA_TO_DEVICE);
7144decb 686 if (dma_mapping_error(&dev->dev, phys)) {
dac2f83f
KH		 687#ifdef __ARMEB__
688 dev_kfree_skb(skb);
689#else
690 kfree(mem);
691#endif
b4c7d3b0 692 dev->stats.tx_dropped++;
dac2f83f
KH		 693 return NETDEV_TX_OK;
694 }
695
696 n = queue_get_desc(txreadyq, port, 1);
697 BUG_ON(n < 0);
698 desc = tx_desc_ptr(port, n);
699
700#ifdef __ARMEB__
701 port->tx_buff_tab[n] = skb;
702#else
703 port->tx_buff_tab[n] = mem;
704#endif
705 desc->data = phys + offset;
706 desc->buf_len = desc->pkt_len = len;
707
708 /* NPE firmware pads short frames with zeros internally */
709 wmb();
710 queue_put_desc(TX_QUEUE(port->id), tx_desc_phys(port, n), desc);
711 dev->trans_start = jiffies;
712
6a68afe3 713 if (qmgr_stat_nearly_empty(txreadyq)) { /* really empty in fact */
dac2f83f
KH		 714#if DEBUG_TX
715 printk(KERN_DEBUG "%s: eth_xmit queue full\n", dev->name);
716#endif
717 netif_stop_queue(dev);
718 /* we could miss TX ready interrupt */
6a68afe3
KH		 719 /* really empty in fact */
720 if (!qmgr_stat_nearly_empty(txreadyq)) {
dac2f83f
KH		 721#if DEBUG_TX
722 printk(KERN_DEBUG "%s: eth_xmit ready again\n",
723 dev->name);
724#endif
725 netif_wake_queue(dev);
726 }
727 }
728
729#if DEBUG_TX
730 printk(KERN_DEBUG "%s: eth_xmit end\n", dev->name);
731#endif
732 return NETDEV_TX_OK;
733}
734
735
dac2f83f
KH		 736static void eth_set_mcast_list(struct net_device *dev)
737{
738 struct port *port = netdev_priv(dev);
739 struct dev_mc_list *mclist = dev->mc_list;
740 u8 diffs[ETH_ALEN], *addr;
741 int cnt = dev->mc_count, i;
742
743 if ((dev->flags & IFF_PROMISC) || !mclist || !cnt) {
744 __raw_writel(DEFAULT_RX_CNTRL0 & ~RX_CNTRL0_ADDR_FLTR_EN,
745 &port->regs->rx_control[0]);
746 return;
747 }
748
749 memset(diffs, 0, ETH_ALEN);
750 addr = mclist->dmi_addr; /* first MAC address */
751
752 while (--cnt && (mclist = mclist->next))
753 for (i = 0; i < ETH_ALEN; i++)
754 diffs[i] |= addr[i] ^ mclist->dmi_addr[i];
755
756 for (i = 0; i < ETH_ALEN; i++) {
757 __raw_writel(addr[i], &port->regs->mcast_addr[i]);
758 __raw_writel(~diffs[i], &port->regs->mcast_mask[i]);
759 }
760
761 __raw_writel(DEFAULT_RX_CNTRL0 | RX_CNTRL0_ADDR_FLTR_EN,
762 &port->regs->rx_control[0]);
763}
764
765
766static int eth_ioctl(struct net_device *dev, struct ifreq *req, int cmd)
767{
768 struct port *port = netdev_priv(dev);
dac2f83f
KH		 769
770 if (!netif_running(dev))
771 return -EINVAL;
4954936e 772 return phy_mii_ioctl(port->phydev, if_mii(req), cmd);
dac2f83f
KH		 773}
774
490b7722
KH		 775/* ethtool support */
776
777static void ixp4xx_get_drvinfo(struct net_device *dev,
778 struct ethtool_drvinfo *info)
779{
780 struct port *port = netdev_priv(dev);
781 strcpy(info->driver, DRV_NAME);
782 snprintf(info->fw_version, sizeof(info->fw_version), "%u:%u:%u:%u",
783 port->firmware[0], port->firmware[1],
784 port->firmware[2], port->firmware[3]);
785 strcpy(info->bus_info, "internal");
dac2f83f
KH		 786}
787
490b7722
KH		 788static int ixp4xx_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
789{
790 struct port *port = netdev_priv(dev);
791 return phy_ethtool_gset(port->phydev, cmd);
792}
793
794static int ixp4xx_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
795{
796 struct port *port = netdev_priv(dev);
797 return phy_ethtool_sset(port->phydev, cmd);
798}
799
800static int ixp4xx_nway_reset(struct net_device *dev)
801{
802 struct port *port = netdev_priv(dev);
803 return phy_start_aneg(port->phydev);
804}
805
806static struct ethtool_ops ixp4xx_ethtool_ops = {
807 .get_drvinfo = ixp4xx_get_drvinfo,
808 .get_settings = ixp4xx_get_settings,
809 .set_settings = ixp4xx_set_settings,
810 .nway_reset = ixp4xx_nway_reset,
811 .get_link = ethtool_op_get_link,
812};
813
dac2f83f
KH		 814
815static int request_queues(struct port *port)
816{
817 int err;
818
e6da96ac
KH		 819 err = qmgr_request_queue(RXFREE_QUEUE(port->id), RX_DESCS, 0, 0,
820 "%s:RX-free", port->netdev->name);
dac2f83f
KH		 821 if (err)
822 return err;
823
e6da96ac
KH		 824 err = qmgr_request_queue(port->plat->rxq, RX_DESCS, 0, 0,
825 "%s:RX", port->netdev->name);
dac2f83f
KH		 826 if (err)
827 goto rel_rxfree;
828
e6da96ac
KH		 829 err = qmgr_request_queue(TX_QUEUE(port->id), TX_DESCS, 0, 0,
830 "%s:TX", port->netdev->name);
dac2f83f
KH		 831 if (err)
832 goto rel_rx;
833
e6da96ac
KH		 834 err = qmgr_request_queue(port->plat->txreadyq, TX_DESCS, 0, 0,
835 "%s:TX-ready", port->netdev->name);
dac2f83f
KH		 836 if (err)
837 goto rel_tx;
838
839 /* TX-done queue handles skbs sent out by the NPEs */
840 if (!ports_open) {
e6da96ac
KH		 841 err = qmgr_request_queue(TXDONE_QUEUE, TXDONE_QUEUE_LEN, 0, 0,
842 "%s:TX-done", DRV_NAME);
dac2f83f
KH		 843 if (err)
844 goto rel_txready;
845 }
846 return 0;
847
848rel_txready:
849 qmgr_release_queue(port->plat->txreadyq);
850rel_tx:
851 qmgr_release_queue(TX_QUEUE(port->id));
852rel_rx:
853 qmgr_release_queue(port->plat->rxq);
854rel_rxfree:
855 qmgr_release_queue(RXFREE_QUEUE(port->id));
856 printk(KERN_DEBUG "%s: unable to request hardware queues\n",
857 port->netdev->name);
858 return err;
859}
860
861static void release_queues(struct port *port)
862{
863 qmgr_release_queue(RXFREE_QUEUE(port->id));
864 qmgr_release_queue(port->plat->rxq);
865 qmgr_release_queue(TX_QUEUE(port->id));
866 qmgr_release_queue(port->plat->txreadyq);
867
868 if (!ports_open)
869 qmgr_release_queue(TXDONE_QUEUE);
870}
871
872static int init_queues(struct port *port)
873{
874 int i;
875
876 if (!ports_open)
877 if (!(dma_pool = dma_pool_create(DRV_NAME, NULL,
878 POOL_ALLOC_SIZE, 32, 0)))
879 return -ENOMEM;
880
881 if (!(port->desc_tab = dma_pool_alloc(dma_pool, GFP_KERNEL,
882 &port->desc_tab_phys)))
883 return -ENOMEM;
884 memset(port->desc_tab, 0, POOL_ALLOC_SIZE);
885 memset(port->rx_buff_tab, 0, sizeof(port->rx_buff_tab)); /* tables */
886 memset(port->tx_buff_tab, 0, sizeof(port->tx_buff_tab));
887
888 /* Setup RX buffers */
889 for (i = 0; i < RX_DESCS; i++) {
890 struct desc *desc = rx_desc_ptr(port, i);
891 buffer_t *buff; /* skb or kmalloc()ated memory */
892 void *data;
893#ifdef __ARMEB__
894 if (!(buff = netdev_alloc_skb(port->netdev, RX_BUFF_SIZE)))
895 return -ENOMEM;
896 data = buff->data;
897#else
898 if (!(buff = kmalloc(RX_BUFF_SIZE, GFP_KERNEL)))
899 return -ENOMEM;
900 data = buff;
901#endif
902 desc->buf_len = MAX_MRU;
903 desc->data = dma_map_single(&port->netdev->dev, data,
904 RX_BUFF_SIZE, DMA_FROM_DEVICE);
7144decb 905 if (dma_mapping_error(&port->netdev->dev, desc->data)) {
dac2f83f
KH		 906 free_buffer(buff);
907 return -EIO;
908 }
909 desc->data += NET_IP_ALIGN;
910 port->rx_buff_tab[i] = buff;
911 }
912
913 return 0;
914}
915
916static void destroy_queues(struct port *port)
917{
918 int i;
919
920 if (port->desc_tab) {
921 for (i = 0; i < RX_DESCS; i++) {
922 struct desc *desc = rx_desc_ptr(port, i);
923 buffer_t *buff = port->rx_buff_tab[i];
924 if (buff) {
925 dma_unmap_single(&port->netdev->dev,
926 desc->data - NET_IP_ALIGN,
927 RX_BUFF_SIZE, DMA_FROM_DEVICE);
928 free_buffer(buff);
929 }
930 }
931 for (i = 0; i < TX_DESCS; i++) {
932 struct desc *desc = tx_desc_ptr(port, i);
933 buffer_t *buff = port->tx_buff_tab[i];
934 if (buff) {
935 dma_unmap_tx(port, desc);
936 free_buffer(buff);
937 }
938 }
939 dma_pool_free(dma_pool, port->desc_tab, port->desc_tab_phys);
940 port->desc_tab = NULL;
941 }
942
943 if (!ports_open && dma_pool) {
944 dma_pool_destroy(dma_pool);
945 dma_pool = NULL;
946 }
947}
948
949static int eth_open(struct net_device *dev)
950{
951 struct port *port = netdev_priv(dev);
952 struct npe *npe = port->npe;
953 struct msg msg;
954 int i, err;
955
956 if (!npe_running(npe)) {
957 err = npe_load_firmware(npe, npe_name(npe), &dev->dev);
958 if (err)
959 return err;
960
961 if (npe_recv_message(npe, &msg, "ETH_GET_STATUS")) {
962 printk(KERN_ERR "%s: %s not responding\n", dev->name,
963 npe_name(npe));
964 return -EIO;
965 }
490b7722
KH		 966 port->firmware[0] = msg.byte4;
967 port->firmware[1] = msg.byte5;
968 port->firmware[2] = msg.byte6;
969 port->firmware[3] = msg.byte7;
dac2f83f
KH		 970 }
971
dac2f83f
KH		 972 memset(&msg, 0, sizeof(msg));
973 msg.cmd = NPE_VLAN_SETRXQOSENTRY;
974 msg.eth_id = port->id;
975 msg.byte5 = port->plat->rxq | 0x80;
976 msg.byte7 = port->plat->rxq << 4;
977 for (i = 0; i < 8; i++) {
978 msg.byte3 = i;
979 if (npe_send_recv_message(port->npe, &msg, "ETH_SET_RXQ"))
980 return -EIO;
981 }
982
983 msg.cmd = NPE_EDB_SETPORTADDRESS;
984 msg.eth_id = PHYSICAL_ID(port->id);
985 msg.byte2 = dev->dev_addr[0];
986 msg.byte3 = dev->dev_addr[1];
987 msg.byte4 = dev->dev_addr[2];
988 msg.byte5 = dev->dev_addr[3];
989 msg.byte6 = dev->dev_addr[4];
990 msg.byte7 = dev->dev_addr[5];
991 if (npe_send_recv_message(port->npe, &msg, "ETH_SET_MAC"))
992 return -EIO;
993
994 memset(&msg, 0, sizeof(msg));
995 msg.cmd = NPE_FW_SETFIREWALLMODE;
996 msg.eth_id = port->id;
997 if (npe_send_recv_message(port->npe, &msg, "ETH_SET_FIREWALL_MODE"))
998 return -EIO;
999
1000 if ((err = request_queues(port)) != 0)
1001 return err;
1002
1003 if ((err = init_queues(port)) != 0) {
1004 destroy_queues(port);
1005 release_queues(port);
1006 return err;
1007 }
1008
2098c18d
KH		 1009 port->speed = 0; /* force "link up" message */
1010 phy_start(port->phydev);
1011
dac2f83f
KH		 1012 for (i = 0; i < ETH_ALEN; i++)
1013 __raw_writel(dev->dev_addr[i], &port->regs->hw_addr[i]);
1014 __raw_writel(0x08, &port->regs->random_seed);
1015 __raw_writel(0x12, &port->regs->partial_empty_threshold);
1016 __raw_writel(0x30, &port->regs->partial_full_threshold);
1017 __raw_writel(0x08, &port->regs->tx_start_bytes);
1018 __raw_writel(0x15, &port->regs->tx_deferral);
1019 __raw_writel(0x08, &port->regs->tx_2part_deferral[0]);
1020 __raw_writel(0x07, &port->regs->tx_2part_deferral[1]);
1021 __raw_writel(0x80, &port->regs->slot_time);
1022 __raw_writel(0x01, &port->regs->int_clock_threshold);
1023
1024 /* Populate queues with buffers, no failure after this point */
1025 for (i = 0; i < TX_DESCS; i++)
1026 queue_put_desc(port->plat->txreadyq,
1027 tx_desc_phys(port, i), tx_desc_ptr(port, i));
1028
1029 for (i = 0; i < RX_DESCS; i++)
1030 queue_put_desc(RXFREE_QUEUE(port->id),
1031 rx_desc_phys(port, i), rx_desc_ptr(port, i));
1032
1033 __raw_writel(TX_CNTRL1_RETRIES, &port->regs->tx_control[1]);
1034 __raw_writel(DEFAULT_TX_CNTRL0, &port->regs->tx_control[0]);
1035 __raw_writel(0, &port->regs->rx_control[1]);
1036 __raw_writel(DEFAULT_RX_CNTRL0, &port->regs->rx_control[0]);
1037
1038 napi_enable(&port->napi);
dac2f83f
KH		 1039 eth_set_mcast_list(dev);
1040 netif_start_queue(dev);
dac2f83f
KH		 1041
1042 qmgr_set_irq(port->plat->rxq, QUEUE_IRQ_SRC_NOT_EMPTY,
1043 eth_rx_irq, dev);
1044 if (!ports_open) {
1045 qmgr_set_irq(TXDONE_QUEUE, QUEUE_IRQ_SRC_NOT_EMPTY,
1046 eth_txdone_irq, NULL);
1047 qmgr_enable_irq(TXDONE_QUEUE);
1048 }
1049 ports_open++;
1050 /* we may already have RX data, enables IRQ */
288379f0 1051 napi_schedule(&port->napi);
dac2f83f
KH		 1052 return 0;
1053}
1054
1055static int eth_close(struct net_device *dev)
1056{
1057 struct port *port = netdev_priv(dev);
1058 struct msg msg;
1059 int buffs = RX_DESCS; /* allocated RX buffers */
1060 int i;
1061
1062 ports_open--;
1063 qmgr_disable_irq(port->plat->rxq);
1064 napi_disable(&port->napi);
1065 netif_stop_queue(dev);
1066
1067 while (queue_get_desc(RXFREE_QUEUE(port->id), port, 0) >= 0)
1068 buffs--;
1069
1070 memset(&msg, 0, sizeof(msg));
1071 msg.cmd = NPE_SETLOOPBACK_MODE;
1072 msg.eth_id = port->id;
1073 msg.byte3 = 1;
1074 if (npe_send_recv_message(port->npe, &msg, "ETH_ENABLE_LOOPBACK"))
1075 printk(KERN_CRIT "%s: unable to enable loopback\n", dev->name);
1076
1077 i = 0;
1078 do { /* drain RX buffers */
1079 while (queue_get_desc(port->plat->rxq, port, 0) >= 0)
1080 buffs--;
1081 if (!buffs)
1082 break;
1083 if (qmgr_stat_empty(TX_QUEUE(port->id))) {
1084 /* we have to inject some packet */
1085 struct desc *desc;
1086 u32 phys;
1087 int n = queue_get_desc(port->plat->txreadyq, port, 1);
1088 BUG_ON(n < 0);
1089 desc = tx_desc_ptr(port, n);
1090 phys = tx_desc_phys(port, n);
1091 desc->buf_len = desc->pkt_len = 1;
1092 wmb();
1093 queue_put_desc(TX_QUEUE(port->id), phys, desc);
1094 }
1095 udelay(1);
1096 } while (++i < MAX_CLOSE_WAIT);
1097
1098 if (buffs)
1099 printk(KERN_CRIT "%s: unable to drain RX queue, %i buffer(s)"
1100 " left in NPE\n", dev->name, buffs);
1101#if DEBUG_CLOSE
1102 if (!buffs)
1103 printk(KERN_DEBUG "Draining RX queue took %i cycles\n", i);
1104#endif
1105
1106 buffs = TX_DESCS;
1107 while (queue_get_desc(TX_QUEUE(port->id), port, 1) >= 0)
1108 buffs--; /* cancel TX */
1109
1110 i = 0;
1111 do {
1112 while (queue_get_desc(port->plat->txreadyq, port, 1) >= 0)
1113 buffs--;
1114 if (!buffs)
1115 break;
1116 } while (++i < MAX_CLOSE_WAIT);
1117
1118 if (buffs)
1119 printk(KERN_CRIT "%s: unable to drain TX queue, %i buffer(s) "
1120 "left in NPE\n", dev->name, buffs);
1121#if DEBUG_CLOSE
1122 if (!buffs)
1123 printk(KERN_DEBUG "Draining TX queues took %i cycles\n", i);
1124#endif
1125
1126 msg.byte3 = 0;
1127 if (npe_send_recv_message(port->npe, &msg, "ETH_DISABLE_LOOPBACK"))
1128 printk(KERN_CRIT "%s: unable to disable loopback\n",
1129 dev->name);
1130
2098c18d 1131 phy_stop(port->phydev);
dac2f83f
KH		 1132
1133 if (!ports_open)
1134 qmgr_disable_irq(TXDONE_QUEUE);
dac2f83f
KH		 1135 destroy_queues(port);
1136 release_queues(port);
1137 return 0;
1138}
1139
59f8500e
KH		 1140static const struct net_device_ops ixp4xx_netdev_ops = {
1141 .ndo_open = eth_open,
1142 .ndo_stop = eth_close,
1143 .ndo_start_xmit = eth_xmit,
1144 .ndo_set_multicast_list = eth_set_mcast_list,
1145 .ndo_do_ioctl = eth_ioctl,
1146
1147};
1148
dac2f83f
KH		 1149static int __devinit eth_init_one(struct platform_device *pdev)
1150{
1151 struct port *port;
1152 struct net_device *dev;
1153 struct eth_plat_info *plat = pdev->dev.platform_data;
1154 u32 regs_phys;
2098c18d 1155 char phy_id[BUS_ID_SIZE];
dac2f83f
KH		 1156 int err;
1157
1158 if (!(dev = alloc_etherdev(sizeof(struct port))))
1159 return -ENOMEM;
1160
1161 SET_NETDEV_DEV(dev, &pdev->dev);
1162 port = netdev_priv(dev);
1163 port->netdev = dev;
1164 port->id = pdev->id;
1165
1166 switch (port->id) {
1167 case IXP4XX_ETH_NPEA:
1168 port->regs = (struct eth_regs __iomem *)IXP4XX_EthA_BASE_VIRT;
1169 regs_phys = IXP4XX_EthA_BASE_PHYS;
1170 break;
1171 case IXP4XX_ETH_NPEB:
1172 port->regs = (struct eth_regs __iomem *)IXP4XX_EthB_BASE_VIRT;
1173 regs_phys = IXP4XX_EthB_BASE_PHYS;
1174 break;
1175 case IXP4XX_ETH_NPEC:
1176 port->regs = (struct eth_regs __iomem *)IXP4XX_EthC_BASE_VIRT;
1177 regs_phys = IXP4XX_EthC_BASE_PHYS;
1178 break;
1179 default:
3ba8c792 1180 err = -ENODEV;
dac2f83f
KH		 1181 goto err_free;
1182 }
1183
59f8500e 1184 dev->netdev_ops = &ixp4xx_netdev_ops;
490b7722 1185 dev->ethtool_ops = &ixp4xx_ethtool_ops;
dac2f83f
KH		 1186 dev->tx_queue_len = 100;
1187
1188 netif_napi_add(dev, &port->napi, eth_poll, NAPI_WEIGHT);
1189
1190 if (!(port->npe = npe_request(NPE_ID(port->id)))) {
1191 err = -EIO;
1192 goto err_free;
1193 }
1194
dac2f83f
KH		 1195 port->mem_res = request_mem_region(regs_phys, REGS_SIZE, dev->name);
1196 if (!port->mem_res) {
1197 err = -EBUSY;
7aa6a478 1198 goto err_npe_rel;
dac2f83f
KH		 1199 }
1200
1201 port->plat = plat;
1202 npe_port_tab[NPE_ID(port->id)] = port;
1203 memcpy(dev->dev_addr, plat->hwaddr, ETH_ALEN);
1204
1205 platform_set_drvdata(pdev, dev);
1206
1207 __raw_writel(DEFAULT_CORE_CNTRL | CORE_RESET,
1208 &port->regs->core_control);
1209 udelay(50);
1210 __raw_writel(DEFAULT_CORE_CNTRL, &port->regs->core_control);
1211 udelay(50);
1212
2098c18d
KH		 1213 snprintf(phy_id, BUS_ID_SIZE, PHY_ID_FMT, "0", plat->phy);
1214 port->phydev = phy_connect(dev, phy_id, &ixp4xx_adjust_link, 0,
1215 PHY_INTERFACE_MODE_MII);
7aa6a478
KH		 1216 if ((err = IS_ERR(port->phydev)))
1217 goto err_free_mem;
2098c18d
KH		 1218
1219 port->phydev->irq = PHY_POLL;
dac2f83f 1220
7aa6a478
KH		 1221 if ((err = register_netdev(dev)))
1222 goto err_phy_dis;
1223
dac2f83f
KH		 1224 printk(KERN_INFO "%s: MII PHY %i on %s\n", dev->name, plat->phy,
1225 npe_name(port->npe));
1226
dac2f83f
KH		 1227 return 0;
1228
7aa6a478
KH		 1229err_phy_dis:
1230 phy_disconnect(port->phydev);
1231err_free_mem:
1232 npe_port_tab[NPE_ID(port->id)] = NULL;
1233 platform_set_drvdata(pdev, NULL);
1234 release_resource(port->mem_res);
dac2f83f
KH		 1235err_npe_rel:
1236 npe_release(port->npe);
1237err_free:
1238 free_netdev(dev);
1239 return err;
1240}
1241
1242static int __devexit eth_remove_one(struct platform_device *pdev)
1243{
1244 struct net_device *dev = platform_get_drvdata(pdev);
1245 struct port *port = netdev_priv(dev);
1246
1247 unregister_netdev(dev);
7aa6a478 1248 phy_disconnect(port->phydev);
dac2f83f
KH		 1249 npe_port_tab[NPE_ID(port->id)] = NULL;
1250 platform_set_drvdata(pdev, NULL);
1251 npe_release(port->npe);
1252 release_resource(port->mem_res);
1253 free_netdev(dev);
1254 return 0;
1255}
1256
3c36a837 1257static struct platform_driver ixp4xx_eth_driver = {
dac2f83f
KH		 1258 .driver.name = DRV_NAME,
1259 .probe = eth_init_one,
1260 .remove = eth_remove_one,
1261};
1262
1263static int __init eth_init_module(void)
1264{
2098c18d 1265 int err;
2098c18d
KH		 1266 if ((err = ixp4xx_mdio_register()))
1267 return err;
3c36a837 1268 return platform_driver_register(&ixp4xx_eth_driver);
dac2f83f
KH		 1269}
1270
1271static void __exit eth_cleanup_module(void)
1272{
3c36a837 1273 platform_driver_unregister(&ixp4xx_eth_driver);
2098c18d 1274 ixp4xx_mdio_remove();
dac2f83f
KH		 1275}
1276
1277MODULE_AUTHOR("Krzysztof Halasa");
1278MODULE_DESCRIPTION("Intel IXP4xx Ethernet driver");
1279MODULE_LICENSE("GPL v2");
1280MODULE_ALIAS("platform:ixp4xx_eth");
1281module_init(eth_init_module);
1282module_exit(eth_cleanup_module);
Linux kernel - Deliverables
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