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drivers/net/typhoon.c: Use (pr|netdev)_<level> macro helpers
[deliverable/linux.git] / drivers / net / arm / w90p910_ether.c
CommitLineData
a50a97d4
WZ		 1/*
2 * Copyright (c) 2008-2009 Nuvoton technology corporation.
3 *
4 * Wan ZongShun <mcuos.com@gmail.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation;version 2 of the License.
9 *
10 */
11
12#include <linux/module.h>
13#include <linux/init.h>
14#include <linux/mii.h>
15#include <linux/netdevice.h>
16#include <linux/etherdevice.h>
17#include <linux/skbuff.h>
18#include <linux/ethtool.h>
19#include <linux/platform_device.h>
20#include <linux/clk.h>
21
22#define DRV_MODULE_NAME "w90p910-emc"
23#define DRV_MODULE_VERSION "0.1"
24
25/* Ethernet MAC Registers */
26#define REG_CAMCMR 0x00
27#define REG_CAMEN 0x04
28#define REG_CAMM_BASE 0x08
29#define REG_CAML_BASE 0x0c
30#define REG_TXDLSA 0x88
31#define REG_RXDLSA 0x8C
32#define REG_MCMDR 0x90
33#define REG_MIID 0x94
34#define REG_MIIDA 0x98
35#define REG_FFTCR 0x9C
36#define REG_TSDR 0xa0
37#define REG_RSDR 0xa4
38#define REG_DMARFC 0xa8
39#define REG_MIEN 0xac
40#define REG_MISTA 0xb0
41#define REG_CTXDSA 0xcc
42#define REG_CTXBSA 0xd0
43#define REG_CRXDSA 0xd4
44#define REG_CRXBSA 0xd8
45
46/* mac controller bit */
47#define MCMDR_RXON 0x01
48#define MCMDR_ACP (0x01 << 3)
49#define MCMDR_SPCRC (0x01 << 5)
50#define MCMDR_TXON (0x01 << 8)
51#define MCMDR_FDUP (0x01 << 18)
52#define MCMDR_ENMDC (0x01 << 19)
53#define MCMDR_OPMOD (0x01 << 20)
54#define SWR (0x01 << 24)
55
56/* cam command regiser */
57#define CAMCMR_AUP 0x01
58#define CAMCMR_AMP (0x01 << 1)
59#define CAMCMR_ABP (0x01 << 2)
60#define CAMCMR_CCAM (0x01 << 3)
61#define CAMCMR_ECMP (0x01 << 4)
62#define CAM0EN 0x01
63
64/* mac mii controller bit */
65#define MDCCR (0x0a << 20)
66#define PHYAD (0x01 << 8)
67#define PHYWR (0x01 << 16)
68#define PHYBUSY (0x01 << 17)
69#define PHYPRESP (0x01 << 18)
70#define CAM_ENTRY_SIZE 0x08
71
72/* rx and tx status */
73#define TXDS_TXCP (0x01 << 19)
74#define RXDS_CRCE (0x01 << 17)
75#define RXDS_PTLE (0x01 << 19)
76#define RXDS_RXGD (0x01 << 20)
77#define RXDS_ALIE (0x01 << 21)
78#define RXDS_RP (0x01 << 22)
79
80/* mac interrupt status*/
81#define MISTA_EXDEF (0x01 << 19)
82#define MISTA_TXBERR (0x01 << 24)
83#define MISTA_TDU (0x01 << 23)
84#define MISTA_RDU (0x01 << 10)
85#define MISTA_RXBERR (0x01 << 11)
86
87#define ENSTART 0x01
88#define ENRXINTR 0x01
89#define ENRXGD (0x01 << 4)
90#define ENRXBERR (0x01 << 11)
91#define ENTXINTR (0x01 << 16)
92#define ENTXCP (0x01 << 18)
93#define ENTXABT (0x01 << 21)
94#define ENTXBERR (0x01 << 24)
95#define ENMDC (0x01 << 19)
96#define PHYBUSY (0x01 << 17)
97#define MDCCR_VAL 0xa00000
98
99/* rx and tx owner bit */
100#define RX_OWEN_DMA (0x01 << 31)
101#define RX_OWEN_CPU (~(0x03 << 30))
102#define TX_OWEN_DMA (0x01 << 31)
103#define TX_OWEN_CPU (~(0x01 << 31))
104
105/* tx frame desc controller bit */
106#define MACTXINTEN 0x04
107#define CRCMODE 0x02
108#define PADDINGMODE 0x01
109
110/* fftcr controller bit */
111#define TXTHD (0x03 << 8)
112#define BLENGTH (0x01 << 20)
113
114/* global setting for driver */
115#define RX_DESC_SIZE 50
116#define TX_DESC_SIZE 10
117#define MAX_RBUFF_SZ 0x600
118#define MAX_TBUFF_SZ 0x600
119#define TX_TIMEOUT 50
120#define DELAY 1000
121#define CAM0 0x0
122
123static int w90p910_mdio_read(struct net_device *dev, int phy_id, int reg);
124
125struct w90p910_rxbd {
126 unsigned int sl;
127 unsigned int buffer;
128 unsigned int reserved;
129 unsigned int next;
130};
131
132struct w90p910_txbd {
133 unsigned int mode;
134 unsigned int buffer;
135 unsigned int sl;
136 unsigned int next;
137};
138
139struct recv_pdesc {
140 struct w90p910_rxbd desclist[RX_DESC_SIZE];
141 char recv_buf[RX_DESC_SIZE][MAX_RBUFF_SZ];
142};
143
144struct tran_pdesc {
145 struct w90p910_txbd desclist[TX_DESC_SIZE];
1e5053b7 146 char tran_buf[TX_DESC_SIZE][MAX_TBUFF_SZ];
a50a97d4
WZ		 147};
148
149struct w90p910_ether {
150 struct recv_pdesc *rdesc;
a50a97d4 151 struct tran_pdesc *tdesc;
1e5053b7
WZ		 152 dma_addr_t rdesc_phys;
153 dma_addr_t tdesc_phys;
a50a97d4
WZ		 154 struct net_device_stats stats;
155 struct platform_device *pdev;
1e5053b7 156 struct resource *res;
a50a97d4
WZ		 157 struct sk_buff *skb;
158 struct clk *clk;
159 struct clk *rmiiclk;
160 struct mii_if_info mii;
161 struct timer_list check_timer;
162 void __iomem *reg;
ddb14175
WZ		 163 int rxirq;
164 int txirq;
a50a97d4
WZ		 165 unsigned int cur_tx;
166 unsigned int cur_rx;
167 unsigned int finish_tx;
168 unsigned int rx_packets;
169 unsigned int rx_bytes;
170 unsigned int start_tx_ptr;
171 unsigned int start_rx_ptr;
172 unsigned int linkflag;
a50a97d4
WZ		 173};
174
175static void update_linkspeed_register(struct net_device *dev,
176 unsigned int speed, unsigned int duplex)
177{
178 struct w90p910_ether *ether = netdev_priv(dev);
179 unsigned int val;
180
181 val = __raw_readl(ether->reg + REG_MCMDR);
182
183 if (speed == SPEED_100) {
184 /* 100 full/half duplex */
185 if (duplex == DUPLEX_FULL) {
186 val |= (MCMDR_OPMOD | MCMDR_FDUP);
187 } else {
188 val |= MCMDR_OPMOD;
189 val &= ~MCMDR_FDUP;
190 }
191 } else {
192 /* 10 full/half duplex */
193 if (duplex == DUPLEX_FULL) {
194 val |= MCMDR_FDUP;
195 val &= ~MCMDR_OPMOD;
196 } else {
197 val &= ~(MCMDR_FDUP | MCMDR_OPMOD);
198 }
199 }
200
201 __raw_writel(val, ether->reg + REG_MCMDR);
202}
203
204static void update_linkspeed(struct net_device *dev)
205{
206 struct w90p910_ether *ether = netdev_priv(dev);
207 struct platform_device *pdev;
208 unsigned int bmsr, bmcr, lpa, speed, duplex;
209
210 pdev = ether->pdev;
211
212 if (!mii_link_ok(&ether->mii)) {
213 ether->linkflag = 0x0;
214 netif_carrier_off(dev);
215 dev_warn(&pdev->dev, "%s: Link down.\n", dev->name);
216 return;
217 }
218
219 if (ether->linkflag == 1)
220 return;
221
222 bmsr = w90p910_mdio_read(dev, ether->mii.phy_id, MII_BMSR);
223 bmcr = w90p910_mdio_read(dev, ether->mii.phy_id, MII_BMCR);
224
225 if (bmcr & BMCR_ANENABLE) {
226 if (!(bmsr & BMSR_ANEGCOMPLETE))
227 return;
228
229 lpa = w90p910_mdio_read(dev, ether->mii.phy_id, MII_LPA);
230
231 if ((lpa & LPA_100FULL) || (lpa & LPA_100HALF))
232 speed = SPEED_100;
233 else
234 speed = SPEED_10;
235
236 if ((lpa & LPA_100FULL) || (lpa & LPA_10FULL))
237 duplex = DUPLEX_FULL;
238 else
239 duplex = DUPLEX_HALF;
240
241 } else {
242 speed = (bmcr & BMCR_SPEED100) ? SPEED_100 : SPEED_10;
243 duplex = (bmcr & BMCR_FULLDPLX) ? DUPLEX_FULL : DUPLEX_HALF;
244 }
245
246 update_linkspeed_register(dev, speed, duplex);
247
248 dev_info(&pdev->dev, "%s: Link now %i-%s\n", dev->name, speed,
249 (duplex == DUPLEX_FULL) ? "FullDuplex" : "HalfDuplex");
250 ether->linkflag = 0x01;
251
252 netif_carrier_on(dev);
253}
254
255static void w90p910_check_link(unsigned long dev_id)
256{
257 struct net_device *dev = (struct net_device *) dev_id;
258 struct w90p910_ether *ether = netdev_priv(dev);
259
260 update_linkspeed(dev);
261 mod_timer(&ether->check_timer, jiffies + msecs_to_jiffies(1000));
262}
263
264static void w90p910_write_cam(struct net_device *dev,
265 unsigned int x, unsigned char *pval)
266{
267 struct w90p910_ether *ether = netdev_priv(dev);
268 unsigned int msw, lsw;
269
270 msw = (pval[0] << 24) | (pval[1] << 16) | (pval[2] << 8) | pval[3];
271
272 lsw = (pval[4] << 24) | (pval[5] << 16);
273
274 __raw_writel(lsw, ether->reg + REG_CAML_BASE + x * CAM_ENTRY_SIZE);
275 __raw_writel(msw, ether->reg + REG_CAMM_BASE + x * CAM_ENTRY_SIZE);
276}
277
1e5053b7 278static int w90p910_init_desc(struct net_device *dev)
a50a97d4
WZ		 279{
280 struct w90p910_ether *ether;
1e5053b7
WZ		 281 struct w90p910_txbd *tdesc;
282 struct w90p910_rxbd *rdesc;
283 struct platform_device *pdev;
284 unsigned int i;
a50a97d4
WZ		 285
286 ether = netdev_priv(dev);
1e5053b7 287 pdev = ether->pdev;
a50a97d4
WZ		 288
289 ether->tdesc = (struct tran_pdesc *)
1e5053b7
WZ		 290 dma_alloc_coherent(&pdev->dev, sizeof(struct tran_pdesc),
291 &ether->tdesc_phys, GFP_KERNEL);
292
293 if (!ether->tdesc) {
294 dev_err(&pdev->dev, "Failed to allocate memory for tx desc\n");
295 return -ENOMEM;
296 }
a50a97d4
WZ		 297
298 ether->rdesc = (struct recv_pdesc *)
1e5053b7
WZ		 299 dma_alloc_coherent(&pdev->dev, sizeof(struct recv_pdesc),
300 &ether->rdesc_phys, GFP_KERNEL);
301
302 if (!ether->rdesc) {
303 dev_err(&pdev->dev, "Failed to allocate memory for rx desc\n");
304 dma_free_coherent(&pdev->dev, sizeof(struct tran_pdesc),
305 ether->tdesc, ether->tdesc_phys);
306 return -ENOMEM;
307 }
a50a97d4
WZ		 308
309 for (i = 0; i < TX_DESC_SIZE; i++) {
1e5053b7 310 unsigned int offset;
a50a97d4 311
1e5053b7 312 tdesc = &(ether->tdesc->desclist[i]);
a50a97d4 313
1e5053b7
WZ		 314 if (i == TX_DESC_SIZE - 1)
315 offset = offsetof(struct tran_pdesc, desclist[0]);
316 else
317 offset = offsetof(struct tran_pdesc, desclist[i + 1]);
a50a97d4 318
1e5053b7
WZ		 319 tdesc->next = ether->tdesc_phys + offset;
320 tdesc->buffer = ether->tdesc_phys +
321 offsetof(struct tran_pdesc, tran_buf[i]);
a50a97d4
WZ		 322 tdesc->sl = 0;
323 tdesc->mode = 0;
324 }
325
1e5053b7
WZ		 326 ether->start_tx_ptr = ether->tdesc_phys;
327
a50a97d4 328 for (i = 0; i < RX_DESC_SIZE; i++) {
1e5053b7 329 unsigned int offset;
a50a97d4 330
1e5053b7 331 rdesc = &(ether->rdesc->desclist[i]);
a50a97d4 332
1e5053b7
WZ		 333 if (i == RX_DESC_SIZE - 1)
334 offset = offsetof(struct recv_pdesc, desclist[0]);
335 else
336 offset = offsetof(struct recv_pdesc, desclist[i + 1]);
a50a97d4 337
1e5053b7 338 rdesc->next = ether->rdesc_phys + offset;
a50a97d4 339 rdesc->sl = RX_OWEN_DMA;
1e5053b7
WZ		 340 rdesc->buffer = ether->rdesc_phys +
341 offsetof(struct recv_pdesc, recv_buf[i]);
a50a97d4 342 }
1e5053b7
WZ		 343
344 ether->start_rx_ptr = ether->rdesc_phys;
345
346 return 0;
a50a97d4
WZ		 347}
348
349static void w90p910_set_fifo_threshold(struct net_device *dev)
350{
351 struct w90p910_ether *ether = netdev_priv(dev);
352 unsigned int val;
353
354 val = TXTHD | BLENGTH;
355 __raw_writel(val, ether->reg + REG_FFTCR);
356}
357
358static void w90p910_return_default_idle(struct net_device *dev)
359{
360 struct w90p910_ether *ether = netdev_priv(dev);
361 unsigned int val;
362
363 val = __raw_readl(ether->reg + REG_MCMDR);
364 val |= SWR;
365 __raw_writel(val, ether->reg + REG_MCMDR);
366}
367
368static void w90p910_trigger_rx(struct net_device *dev)
369{
370 struct w90p910_ether *ether = netdev_priv(dev);
371
372 __raw_writel(ENSTART, ether->reg + REG_RSDR);
373}
374
375static void w90p910_trigger_tx(struct net_device *dev)
376{
377 struct w90p910_ether *ether = netdev_priv(dev);
378
379 __raw_writel(ENSTART, ether->reg + REG_TSDR);
380}
381
382static void w90p910_enable_mac_interrupt(struct net_device *dev)
383{
384 struct w90p910_ether *ether = netdev_priv(dev);
385 unsigned int val;
386
387 val = ENTXINTR | ENRXINTR | ENRXGD | ENTXCP;
388 val |= ENTXBERR | ENRXBERR | ENTXABT;
389
390 __raw_writel(val, ether->reg + REG_MIEN);
391}
392
393static void w90p910_get_and_clear_int(struct net_device *dev,
394 unsigned int *val)
395{
396 struct w90p910_ether *ether = netdev_priv(dev);
397
398 *val = __raw_readl(ether->reg + REG_MISTA);
399 __raw_writel(*val, ether->reg + REG_MISTA);
400}
401
402static void w90p910_set_global_maccmd(struct net_device *dev)
403{
404 struct w90p910_ether *ether = netdev_priv(dev);
405 unsigned int val;
406
407 val = __raw_readl(ether->reg + REG_MCMDR);
408 val |= MCMDR_SPCRC | MCMDR_ENMDC | MCMDR_ACP | ENMDC;
409 __raw_writel(val, ether->reg + REG_MCMDR);
410}
411
412static void w90p910_enable_cam(struct net_device *dev)
413{
414 struct w90p910_ether *ether = netdev_priv(dev);
415 unsigned int val;
416
417 w90p910_write_cam(dev, CAM0, dev->dev_addr);
418
419 val = __raw_readl(ether->reg + REG_CAMEN);
420 val |= CAM0EN;
421 __raw_writel(val, ether->reg + REG_CAMEN);
422}
423
424static void w90p910_enable_cam_command(struct net_device *dev)
425{
426 struct w90p910_ether *ether = netdev_priv(dev);
427 unsigned int val;
428
429 val = CAMCMR_ECMP | CAMCMR_ABP | CAMCMR_AMP;
430 __raw_writel(val, ether->reg + REG_CAMCMR);
431}
432
433static void w90p910_enable_tx(struct net_device *dev, unsigned int enable)
434{
435 struct w90p910_ether *ether = netdev_priv(dev);
436 unsigned int val;
437
438 val = __raw_readl(ether->reg + REG_MCMDR);
439
440 if (enable)
441 val |= MCMDR_TXON;
442 else
443 val &= ~MCMDR_TXON;
444
445 __raw_writel(val, ether->reg + REG_MCMDR);
446}
447
448static void w90p910_enable_rx(struct net_device *dev, unsigned int enable)
449{
450 struct w90p910_ether *ether = netdev_priv(dev);
451 unsigned int val;
452
453 val = __raw_readl(ether->reg + REG_MCMDR);
454
455 if (enable)
456 val |= MCMDR_RXON;
457 else
458 val &= ~MCMDR_RXON;
459
460 __raw_writel(val, ether->reg + REG_MCMDR);
461}
462
463static void w90p910_set_curdest(struct net_device *dev)
464{
465 struct w90p910_ether *ether = netdev_priv(dev);
466
467 __raw_writel(ether->start_rx_ptr, ether->reg + REG_RXDLSA);
468 __raw_writel(ether->start_tx_ptr, ether->reg + REG_TXDLSA);
469}
470
471static void w90p910_reset_mac(struct net_device *dev)
472{
473 struct w90p910_ether *ether = netdev_priv(dev);
474
a50a97d4
WZ		 475 w90p910_enable_tx(dev, 0);
476 w90p910_enable_rx(dev, 0);
477 w90p910_set_fifo_threshold(dev);
478 w90p910_return_default_idle(dev);
479
480 if (!netif_queue_stopped(dev))
481 netif_stop_queue(dev);
482
483 w90p910_init_desc(dev);
484
485 dev->trans_start = jiffies;
486 ether->cur_tx = 0x0;
487 ether->finish_tx = 0x0;
488 ether->cur_rx = 0x0;
489
490 w90p910_set_curdest(dev);
491 w90p910_enable_cam(dev);
492 w90p910_enable_cam_command(dev);
493 w90p910_enable_mac_interrupt(dev);
494 w90p910_enable_tx(dev, 1);
495 w90p910_enable_rx(dev, 1);
496 w90p910_trigger_tx(dev);
497 w90p910_trigger_rx(dev);
498
499 dev->trans_start = jiffies;
500
501 if (netif_queue_stopped(dev))
502 netif_wake_queue(dev);
a50a97d4
WZ		 503}
504
505static void w90p910_mdio_write(struct net_device *dev,
506 int phy_id, int reg, int data)
507{
508 struct w90p910_ether *ether = netdev_priv(dev);
509 struct platform_device *pdev;
510 unsigned int val, i;
511
512 pdev = ether->pdev;
513
514 __raw_writel(data, ether->reg + REG_MIID);
515
516 val = (phy_id << 0x08) | reg;
517 val |= PHYBUSY | PHYWR | MDCCR_VAL;
518 __raw_writel(val, ether->reg + REG_MIIDA);
519
520 for (i = 0; i < DELAY; i++) {
521 if ((__raw_readl(ether->reg + REG_MIIDA) & PHYBUSY) == 0)
522 break;
523 }
524
525 if (i == DELAY)
526 dev_warn(&pdev->dev, "mdio write timed out\n");
527}
528
529static int w90p910_mdio_read(struct net_device *dev, int phy_id, int reg)
530{
531 struct w90p910_ether *ether = netdev_priv(dev);
532 struct platform_device *pdev;
533 unsigned int val, i, data;
534
535 pdev = ether->pdev;
536
537 val = (phy_id << 0x08) | reg;
538 val |= PHYBUSY | MDCCR_VAL;
539 __raw_writel(val, ether->reg + REG_MIIDA);
540
541 for (i = 0; i < DELAY; i++) {
542 if ((__raw_readl(ether->reg + REG_MIIDA) & PHYBUSY) == 0)
543 break;
544 }
545
546 if (i == DELAY) {
547 dev_warn(&pdev->dev, "mdio read timed out\n");
548 data = 0xffff;
549 } else {
550 data = __raw_readl(ether->reg + REG_MIID);
551 }
552
553 return data;
554}
555
1e5053b7 556static int w90p910_set_mac_address(struct net_device *dev, void *addr)
a50a97d4
WZ		 557{
558 struct sockaddr *address = addr;
559
560 if (!is_valid_ether_addr(address->sa_data))
561 return -EADDRNOTAVAIL;
562
563 memcpy(dev->dev_addr, address->sa_data, dev->addr_len);
564 w90p910_write_cam(dev, CAM0, dev->dev_addr);
565
566 return 0;
567}
568
569static int w90p910_ether_close(struct net_device *dev)
570{
571 struct w90p910_ether *ether = netdev_priv(dev);
1e5053b7 572 struct platform_device *pdev;
a50a97d4 573
1e5053b7
WZ		 574 pdev = ether->pdev;
575
576 dma_free_coherent(&pdev->dev, sizeof(struct recv_pdesc),
577 ether->rdesc, ether->rdesc_phys);
578 dma_free_coherent(&pdev->dev, sizeof(struct tran_pdesc),
579 ether->tdesc, ether->tdesc_phys);
a50a97d4
WZ		 580
581 netif_stop_queue(dev);
582
583 del_timer_sync(&ether->check_timer);
584 clk_disable(ether->rmiiclk);
585 clk_disable(ether->clk);
586
587 free_irq(ether->txirq, dev);
588 free_irq(ether->rxirq, dev);
589
590 return 0;
591}
592
593static struct net_device_stats *w90p910_ether_stats(struct net_device *dev)
594{
595 struct w90p910_ether *ether;
596
597 ether = netdev_priv(dev);
598
599 return &ether->stats;
600}
601
602static int w90p910_send_frame(struct net_device *dev,
603 unsigned char *data, int length)
604{
605 struct w90p910_ether *ether;
606 struct w90p910_txbd *txbd;
607 struct platform_device *pdev;
608 unsigned char *buffer;
609
610 ether = netdev_priv(dev);
611 pdev = ether->pdev;
612
613 txbd = &ether->tdesc->desclist[ether->cur_tx];
614 buffer = ether->tdesc->tran_buf[ether->cur_tx];
1e5053b7 615
a50a97d4
WZ		 616 if (length > 1514) {
617 dev_err(&pdev->dev, "send data %d bytes, check it\n", length);
618 length = 1514;
619 }
620
621 txbd->sl = length & 0xFFFF;
622
623 memcpy(buffer, data, length);
624
625 txbd->mode = TX_OWEN_DMA | PADDINGMODE | CRCMODE | MACTXINTEN;
626
627 w90p910_enable_tx(dev, 1);
628
629 w90p910_trigger_tx(dev);
630
1e5053b7
WZ		 631 if (++ether->cur_tx >= TX_DESC_SIZE)
632 ether->cur_tx = 0;
633
a50a97d4
WZ		 634 txbd = &ether->tdesc->desclist[ether->cur_tx];
635
636 dev->trans_start = jiffies;
637
638 if (txbd->mode & TX_OWEN_DMA)
639 netif_stop_queue(dev);
640
641 return 0;
642}
643
644static int w90p910_ether_start_xmit(struct sk_buff *skb, struct net_device *dev)
645{
646 struct w90p910_ether *ether = netdev_priv(dev);
647
648 if (!(w90p910_send_frame(dev, skb->data, skb->len))) {
649 ether->skb = skb;
650 dev_kfree_skb_irq(skb);
651 return 0;
652 }
1e5053b7 653 return -EAGAIN;
a50a97d4
WZ		 654}
655
656static irqreturn_t w90p910_tx_interrupt(int irq, void *dev_id)
657{
658 struct w90p910_ether *ether;
659 struct w90p910_txbd *txbd;
660 struct platform_device *pdev;
a50a97d4
WZ		 661 struct net_device *dev;
662 unsigned int cur_entry, entry, status;
663
1e5053b7 664 dev = dev_id;
a50a97d4
WZ		 665 ether = netdev_priv(dev);
666 pdev = ether->pdev;
667
a50a97d4
WZ		 668 w90p910_get_and_clear_int(dev, &status);
669
670 cur_entry = __raw_readl(ether->reg + REG_CTXDSA);
671
1e5053b7
WZ		 672 entry = ether->tdesc_phys +
673 offsetof(struct tran_pdesc, desclist[ether->finish_tx]);
a50a97d4
WZ		 674
675 while (entry != cur_entry) {
676 txbd = &ether->tdesc->desclist[ether->finish_tx];
677
1e5053b7
WZ		 678 if (++ether->finish_tx >= TX_DESC_SIZE)
679 ether->finish_tx = 0;
a50a97d4
WZ		 680
681 if (txbd->sl & TXDS_TXCP) {
682 ether->stats.tx_packets++;
683 ether->stats.tx_bytes += txbd->sl & 0xFFFF;
684 } else {
685 ether->stats.tx_errors++;
686 }
687
688 txbd->sl = 0x0;
689 txbd->mode = 0x0;
690
691 if (netif_queue_stopped(dev))
692 netif_wake_queue(dev);
693
1e5053b7
WZ		 694 entry = ether->tdesc_phys +
695 offsetof(struct tran_pdesc, desclist[ether->finish_tx]);
a50a97d4
WZ		 696 }
697
698 if (status & MISTA_EXDEF) {
699 dev_err(&pdev->dev, "emc defer exceed interrupt\n");
700 } else if (status & MISTA_TXBERR) {
1e5053b7
WZ		 701 dev_err(&pdev->dev, "emc bus error interrupt\n");
702 w90p910_reset_mac(dev);
703 } else if (status & MISTA_TDU) {
704 if (netif_queue_stopped(dev))
705 netif_wake_queue(dev);
706 }
a50a97d4
WZ		 707
708 return IRQ_HANDLED;
709}
710
711static void netdev_rx(struct net_device *dev)
712{
713 struct w90p910_ether *ether;
714 struct w90p910_rxbd *rxbd;
715 struct platform_device *pdev;
a50a97d4
WZ		 716 struct sk_buff *skb;
717 unsigned char *data;
718 unsigned int length, status, val, entry;
719
720 ether = netdev_priv(dev);
721 pdev = ether->pdev;
a50a97d4
WZ		 722
723 rxbd = &ether->rdesc->desclist[ether->cur_rx];
724
725 do {
726 val = __raw_readl(ether->reg + REG_CRXDSA);
1e5053b7
WZ		 727
728 entry = ether->rdesc_phys +
729 offsetof(struct recv_pdesc, desclist[ether->cur_rx]);
a50a97d4
WZ		 730
731 if (val == entry)
732 break;
733
734 status = rxbd->sl;
735 length = status & 0xFFFF;
736
737 if (status & RXDS_RXGD) {
738 data = ether->rdesc->recv_buf[ether->cur_rx];
739 skb = dev_alloc_skb(length+2);
740 if (!skb) {
741 dev_err(&pdev->dev, "get skb buffer error\n");
742 ether->stats.rx_dropped++;
743 return;
744 }
745
746 skb->dev = dev;
747 skb_reserve(skb, 2);
748 skb_put(skb, length);
749 skb_copy_to_linear_data(skb, data, length);
750 skb->protocol = eth_type_trans(skb, dev);
751 ether->stats.rx_packets++;
752 ether->stats.rx_bytes += length;
753 netif_rx(skb);
754 } else {
755 ether->stats.rx_errors++;
756
757 if (status & RXDS_RP) {
758 dev_err(&pdev->dev, "rx runt err\n");
759 ether->stats.rx_length_errors++;
760 } else if (status & RXDS_CRCE) {
1e5053b7
WZ		 761 dev_err(&pdev->dev, "rx crc err\n");
762 ether->stats.rx_crc_errors++;
763 } else if (status & RXDS_ALIE) {
a50a97d4
WZ		 764 dev_err(&pdev->dev, "rx aligment err\n");
765 ether->stats.rx_frame_errors++;
766 } else if (status & RXDS_PTLE) {
1e5053b7
WZ		 767 dev_err(&pdev->dev, "rx longer err\n");
768 ether->stats.rx_over_errors++;
a50a97d4 769 }
1e5053b7 770 }
a50a97d4
WZ		 771
772 rxbd->sl = RX_OWEN_DMA;
773 rxbd->reserved = 0x0;
1e5053b7
WZ		 774
775 if (++ether->cur_rx >= RX_DESC_SIZE)
776 ether->cur_rx = 0;
777
a50a97d4
WZ		 778 rxbd = &ether->rdesc->desclist[ether->cur_rx];
779
a50a97d4
WZ		 780 } while (1);
781}
782
783static irqreturn_t w90p910_rx_interrupt(int irq, void *dev_id)
784{
785 struct net_device *dev;
786 struct w90p910_ether *ether;
787 struct platform_device *pdev;
788 unsigned int status;
789
1e5053b7 790 dev = dev_id;
a50a97d4
WZ		 791 ether = netdev_priv(dev);
792 pdev = ether->pdev;
793
a50a97d4
WZ		 794 w90p910_get_and_clear_int(dev, &status);
795
796 if (status & MISTA_RDU) {
797 netdev_rx(dev);
a50a97d4
WZ		 798 w90p910_trigger_rx(dev);
799
a50a97d4
WZ		 800 return IRQ_HANDLED;
801 } else if (status & MISTA_RXBERR) {
1e5053b7
WZ		 802 dev_err(&pdev->dev, "emc rx bus error\n");
803 w90p910_reset_mac(dev);
804 }
a50a97d4
WZ		 805
806 netdev_rx(dev);
a50a97d4
WZ		 807 return IRQ_HANDLED;
808}
809
810static int w90p910_ether_open(struct net_device *dev)
811{
812 struct w90p910_ether *ether;
813 struct platform_device *pdev;
814
815 ether = netdev_priv(dev);
816 pdev = ether->pdev;
817
818 w90p910_reset_mac(dev);
819 w90p910_set_fifo_threshold(dev);
820 w90p910_set_curdest(dev);
821 w90p910_enable_cam(dev);
822 w90p910_enable_cam_command(dev);
823 w90p910_enable_mac_interrupt(dev);
824 w90p910_set_global_maccmd(dev);
825 w90p910_enable_rx(dev, 1);
826
827 ether->rx_packets = 0x0;
828 ether->rx_bytes = 0x0;
829
830 if (request_irq(ether->txirq, w90p910_tx_interrupt,
831 0x0, pdev->name, dev)) {
832 dev_err(&pdev->dev, "register irq tx failed\n");
833 return -EAGAIN;
834 }
835
836 if (request_irq(ether->rxirq, w90p910_rx_interrupt,
837 0x0, pdev->name, dev)) {
838 dev_err(&pdev->dev, "register irq rx failed\n");
1e5053b7 839 free_irq(ether->txirq, dev);
a50a97d4
WZ		 840 return -EAGAIN;
841 }
842
843 mod_timer(&ether->check_timer, jiffies + msecs_to_jiffies(1000));
844 netif_start_queue(dev);
845 w90p910_trigger_rx(dev);
846
847 dev_info(&pdev->dev, "%s is OPENED\n", dev->name);
848
849 return 0;
850}
851
852static void w90p910_ether_set_multicast_list(struct net_device *dev)
853{
854 struct w90p910_ether *ether;
855 unsigned int rx_mode;
856
857 ether = netdev_priv(dev);
858
859 if (dev->flags & IFF_PROMISC)
860 rx_mode = CAMCMR_AUP | CAMCMR_AMP | CAMCMR_ABP | CAMCMR_ECMP;
861 else if ((dev->flags & IFF_ALLMULTI) || dev->mc_list)
862 rx_mode = CAMCMR_AMP | CAMCMR_ABP | CAMCMR_ECMP;
863 else
864 rx_mode = CAMCMR_ECMP | CAMCMR_ABP;
865 __raw_writel(rx_mode, ether->reg + REG_CAMCMR);
866}
867
868static int w90p910_ether_ioctl(struct net_device *dev,
869 struct ifreq *ifr, int cmd)
870{
871 struct w90p910_ether *ether = netdev_priv(dev);
872 struct mii_ioctl_data *data = if_mii(ifr);
873
874 return generic_mii_ioctl(&ether->mii, data, cmd, NULL);
875}
876
877static void w90p910_get_drvinfo(struct net_device *dev,
878 struct ethtool_drvinfo *info)
879{
880 strcpy(info->driver, DRV_MODULE_NAME);
881 strcpy(info->version, DRV_MODULE_VERSION);
882}
883
884static int w90p910_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
885{
886 struct w90p910_ether *ether = netdev_priv(dev);
887 return mii_ethtool_gset(&ether->mii, cmd);
888}
889
890static int w90p910_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
891{
892 struct w90p910_ether *ether = netdev_priv(dev);
893 return mii_ethtool_sset(&ether->mii, cmd);
894}
895
896static int w90p910_nway_reset(struct net_device *dev)
897{
898 struct w90p910_ether *ether = netdev_priv(dev);
899 return mii_nway_restart(&ether->mii);
900}
901
902static u32 w90p910_get_link(struct net_device *dev)
903{
904 struct w90p910_ether *ether = netdev_priv(dev);
905 return mii_link_ok(&ether->mii);
906}
907
908static const struct ethtool_ops w90p910_ether_ethtool_ops = {
909 .get_settings = w90p910_get_settings,
910 .set_settings = w90p910_set_settings,
911 .get_drvinfo = w90p910_get_drvinfo,
912 .nway_reset = w90p910_nway_reset,
913 .get_link = w90p910_get_link,
914};
915
916static const struct net_device_ops w90p910_ether_netdev_ops = {
917 .ndo_open = w90p910_ether_open,
918 .ndo_stop = w90p910_ether_close,
919 .ndo_start_xmit = w90p910_ether_start_xmit,
920 .ndo_get_stats = w90p910_ether_stats,
921 .ndo_set_multicast_list = w90p910_ether_set_multicast_list,
1e5053b7 922 .ndo_set_mac_address = w90p910_set_mac_address,
a50a97d4
WZ		 923 .ndo_do_ioctl = w90p910_ether_ioctl,
924 .ndo_validate_addr = eth_validate_addr,
925 .ndo_change_mtu = eth_change_mtu,
926};
927
928static void __init get_mac_address(struct net_device *dev)
929{
930 struct w90p910_ether *ether = netdev_priv(dev);
931 struct platform_device *pdev;
932 char addr[6];
933
934 pdev = ether->pdev;
935
936 addr[0] = 0x00;
937 addr[1] = 0x02;
938 addr[2] = 0xac;
939 addr[3] = 0x55;
940 addr[4] = 0x88;
941 addr[5] = 0xa8;
942
943 if (is_valid_ether_addr(addr))
944 memcpy(dev->dev_addr, &addr, 0x06);
945 else
946 dev_err(&pdev->dev, "invalid mac address\n");
947}
948
949static int w90p910_ether_setup(struct net_device *dev)
950{
951 struct w90p910_ether *ether = netdev_priv(dev);
952
953 ether_setup(dev);
954 dev->netdev_ops = &w90p910_ether_netdev_ops;
955 dev->ethtool_ops = &w90p910_ether_ethtool_ops;
956
957 dev->tx_queue_len = 16;
958 dev->dma = 0x0;
959 dev->watchdog_timeo = TX_TIMEOUT;
960
961 get_mac_address(dev);
962
a50a97d4
WZ		 963 ether->cur_tx = 0x0;
964 ether->cur_rx = 0x0;
965 ether->finish_tx = 0x0;
966 ether->linkflag = 0x0;
967 ether->mii.phy_id = 0x01;
968 ether->mii.phy_id_mask = 0x1f;
969 ether->mii.reg_num_mask = 0x1f;
970 ether->mii.dev = dev;
971 ether->mii.mdio_read = w90p910_mdio_read;
972 ether->mii.mdio_write = w90p910_mdio_write;
973
974 setup_timer(&ether->check_timer, w90p910_check_link,
975 (unsigned long)dev);
976
977 return 0;
978}
979
980static int __devinit w90p910_ether_probe(struct platform_device *pdev)
981{
982 struct w90p910_ether *ether;
983 struct net_device *dev;
a50a97d4
WZ		 984 int error;
985
986 dev = alloc_etherdev(sizeof(struct w90p910_ether));
987 if (!dev)
988 return -ENOMEM;
989
1e5053b7
WZ		 990 ether = netdev_priv(dev);
991
992 ether->res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
993 if (ether->res == NULL) {
a50a97d4
WZ		 994 dev_err(&pdev->dev, "failed to get I/O memory\n");
995 error = -ENXIO;
996 goto failed_free;
997 }
998
1e5053b7
WZ		 999 if (!request_mem_region(ether->res->start,
1000 resource_size(ether->res), pdev->name)) {
a50a97d4
WZ		 1001 dev_err(&pdev->dev, "failed to request I/O memory\n");
1002 error = -EBUSY;
1003 goto failed_free;
1004 }
1005
1e5053b7 1006 ether->reg = ioremap(ether->res->start, resource_size(ether->res));
a50a97d4
WZ		 1007 if (ether->reg == NULL) {
1008 dev_err(&pdev->dev, "failed to remap I/O memory\n");
1009 error = -ENXIO;
1010 goto failed_free_mem;
1011 }
1012
1013 ether->txirq = platform_get_irq(pdev, 0);
1014 if (ether->txirq < 0) {
1015 dev_err(&pdev->dev, "failed to get ether tx irq\n");
1016 error = -ENXIO;
1017 goto failed_free_io;
1018 }
1019
1020 ether->rxirq = platform_get_irq(pdev, 1);
1021 if (ether->rxirq < 0) {
1022 dev_err(&pdev->dev, "failed to get ether rx irq\n");
1023 error = -ENXIO;
1024 goto failed_free_txirq;
1025 }
1026
1027 platform_set_drvdata(pdev, dev);
1028
1029 ether->clk = clk_get(&pdev->dev, NULL);
1030 if (IS_ERR(ether->clk)) {
1031 dev_err(&pdev->dev, "failed to get ether clock\n");
1032 error = PTR_ERR(ether->clk);
1033 goto failed_free_rxirq;
1034 }
1035
1036 ether->rmiiclk = clk_get(&pdev->dev, "RMII");
1037 if (IS_ERR(ether->rmiiclk)) {
1038 dev_err(&pdev->dev, "failed to get ether clock\n");
1039 error = PTR_ERR(ether->rmiiclk);
1040 goto failed_put_clk;
1041 }
1042
1043 ether->pdev = pdev;
1044
1045 w90p910_ether_setup(dev);
1046
1047 error = register_netdev(dev);
1048 if (error != 0) {
1049 dev_err(&pdev->dev, "Regiter EMC w90p910 FAILED\n");
1050 error = -ENODEV;
1051 goto failed_put_rmiiclk;
1052 }
1053
1054 return 0;
1055failed_put_rmiiclk:
1056 clk_put(ether->rmiiclk);
1057failed_put_clk:
1058 clk_put(ether->clk);
1059failed_free_rxirq:
1060 free_irq(ether->rxirq, pdev);
1061 platform_set_drvdata(pdev, NULL);
1062failed_free_txirq:
1063 free_irq(ether->txirq, pdev);
1064failed_free_io:
1065 iounmap(ether->reg);
1066failed_free_mem:
1e5053b7 1067 release_mem_region(ether->res->start, resource_size(ether->res));
a50a97d4
WZ		 1068failed_free:
1069 free_netdev(dev);
1070 return error;
1071}
1072
1073static int __devexit w90p910_ether_remove(struct platform_device *pdev)
1074{
1075 struct net_device *dev = platform_get_drvdata(pdev);
1076 struct w90p910_ether *ether = netdev_priv(dev);
1077
1078 unregister_netdev(dev);
1e5053b7 1079
a50a97d4
WZ		 1080 clk_put(ether->rmiiclk);
1081 clk_put(ether->clk);
1e5053b7
WZ		 1082
1083 iounmap(ether->reg);
1084 release_mem_region(ether->res->start, resource_size(ether->res));
1085
1086 free_irq(ether->txirq, dev);
1087 free_irq(ether->rxirq, dev);
1088
a50a97d4
WZ		 1089 del_timer_sync(&ether->check_timer);
1090 platform_set_drvdata(pdev, NULL);
1e5053b7 1091
a50a97d4
WZ		 1092 free_netdev(dev);
1093 return 0;
1094}
1095
1096static struct platform_driver w90p910_ether_driver = {
1097 .probe = w90p910_ether_probe,
1098 .remove = __devexit_p(w90p910_ether_remove),
1099 .driver = {
456d8991 1100 .name = "nuc900-emc",
a50a97d4
WZ		 1101 .owner = THIS_MODULE,
1102 },
1103};
1104
1105static int __init w90p910_ether_init(void)
1106{
1107 return platform_driver_register(&w90p910_ether_driver);
1108}
1109
1110static void __exit w90p910_ether_exit(void)
1111{
1112 platform_driver_unregister(&w90p910_ether_driver);
1113}
1114
1115module_init(w90p910_ether_init);
1116module_exit(w90p910_ether_exit);
1117
1118MODULE_AUTHOR("Wan ZongShun <mcuos.com@gmail.com>");
1119MODULE_DESCRIPTION("w90p910 MAC driver!");
1120MODULE_LICENSE("GPL");
456d8991 1121MODULE_ALIAS("platform:nuc900-emc");
a50a97d4 1122
Linux kernel - Deliverables
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