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signals: consolidate checks for whether or not to ignore a signal
[deliverable/linux.git] / drivers / net / atlx / atl1.c
CommitLineData
f3cc28c7
JC		 1/*
2 * Copyright(c) 2005 - 2006 Attansic Corporation. All rights reserved.
305282ba 3 * Copyright(c) 2006 - 2007 Chris Snook <csnook@redhat.com>
f3cc28c7
JC		 4 * Copyright(c) 2006 Jay Cliburn <jcliburn@gmail.com>
5 *
6 * Derived from Intel e1000 driver
7 * Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved.
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the Free
11 * Software Foundation; either version 2 of the License, or (at your option)
12 * any later version.
13 *
14 * This program is distributed in the hope that it will be useful, but WITHOUT
15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
17 * more details.
18 *
19 * You should have received a copy of the GNU General Public License along with
20 * this program; if not, write to the Free Software Foundation, Inc., 59
21 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
22 *
23 * The full GNU General Public License is included in this distribution in the
24 * file called COPYING.
25 *
26 * Contact Information:
27 * Xiong Huang <xiong_huang@attansic.com>
28 * Attansic Technology Corp. 3F 147, Xianzheng 9th Road, Zhubei,
29 * Xinzhu 302, TAIWAN, REPUBLIC OF CHINA
30 *
31 * Chris Snook <csnook@redhat.com>
32 * Jay Cliburn <jcliburn@gmail.com>
33 *
34 * This version is adapted from the Attansic reference driver for
35 * inclusion in the Linux kernel. It is currently under heavy development.
36 * A very incomplete list of things that need to be dealt with:
37 *
38 * TODO:
f3cc28c7 39 * Wake on LAN.
53ffb42c 40 * Add more ethtool functions.
f3cc28c7
JC		 41 * Fix abstruse irq enable/disable condition described here:
42 * http://marc.theaimsgroup.com/?l=linux-netdev&m=116398508500553&w=2
43 *
44 * NEEDS TESTING:
45 * VLAN
46 * multicast
47 * promiscuous mode
48 * interrupt coalescing
49 * SMP torture testing
50 */
51
305282ba
JC		 52#include <asm/atomic.h>
53#include <asm/byteorder.h>
54
55#include <linux/compiler.h>
56#include <linux/crc32.h>
57#include <linux/delay.h>
58#include <linux/dma-mapping.h>
f3cc28c7 59#include <linux/etherdevice.h>
f3cc28c7 60#include <linux/hardirq.h>
305282ba
JC		 61#include <linux/if_ether.h>
62#include <linux/if_vlan.h>
63#include <linux/in.h>
f3cc28c7 64#include <linux/interrupt.h>
305282ba 65#include <linux/ip.h>
f3cc28c7 66#include <linux/irqflags.h>
305282ba
JC		 67#include <linux/irqreturn.h>
68#include <linux/jiffies.h>
69#include <linux/mii.h>
70#include <linux/module.h>
71#include <linux/moduleparam.h>
f3cc28c7 72#include <linux/net.h>
305282ba
JC		 73#include <linux/netdevice.h>
74#include <linux/pci.h>
75#include <linux/pci_ids.h>
f3cc28c7 76#include <linux/pm.h>
305282ba
JC		 77#include <linux/skbuff.h>
78#include <linux/slab.h>
79#include <linux/spinlock.h>
80#include <linux/string.h>
f3cc28c7 81#include <linux/tcp.h>
305282ba
JC		 82#include <linux/timer.h>
83#include <linux/types.h>
84#include <linux/workqueue.h>
f3cc28c7 85
f3cc28c7
JC		 86#include <net/checksum.h>
87
f3cc28c7
JC		 88#include "atl1.h"
89
305282ba
JC		 90/* Temporary hack for merging atl1 and atl2 */
91#include "atlx.c"
f3cc28c7 92
8ec7226a
CS		 93/*
94 * This is the only thing that needs to be changed to adjust the
95 * maximum number of ports that the driver can manage.
96 */
97#define ATL1_MAX_NIC 4
98
99#define OPTION_UNSET -1
100#define OPTION_DISABLED 0
101#define OPTION_ENABLED 1
102
103#define ATL1_PARAM_INIT { [0 ... ATL1_MAX_NIC] = OPTION_UNSET }
104
105/*
106 * Interrupt Moderate Timer in units of 2 us
107 *
108 * Valid Range: 10-65535
109 *
110 * Default Value: 100 (200us)
111 */
112static int __devinitdata int_mod_timer[ATL1_MAX_NIC+1] = ATL1_PARAM_INIT;
113static int num_int_mod_timer;
114module_param_array_named(int_mod_timer, int_mod_timer, int,
115 &num_int_mod_timer, 0);
116MODULE_PARM_DESC(int_mod_timer, "Interrupt moderator timer");
117
118#define DEFAULT_INT_MOD_CNT 100 /* 200us */
119#define MAX_INT_MOD_CNT 65000
120#define MIN_INT_MOD_CNT 50
121
122struct atl1_option {
123 enum { enable_option, range_option, list_option } type;
124 char *name;
125 char *err;
126 int def;
127 union {
128 struct { /* range_option info */
129 int min;
130 int max;
131 } r;
132 struct { /* list_option info */
133 int nr;
134 struct atl1_opt_list {
135 int i;
136 char *str;
137 } *p;
138 } l;
139 } arg;
140};
141
142static int __devinit atl1_validate_option(int *value, struct atl1_option *opt,
143 struct pci_dev *pdev)
144{
145 if (*value == OPTION_UNSET) {
146 *value = opt->def;
147 return 0;
148 }
149
150 switch (opt->type) {
151 case enable_option:
152 switch (*value) {
153 case OPTION_ENABLED:
154 dev_info(&pdev->dev, "%s enabled\n", opt->name);
155 return 0;
156 case OPTION_DISABLED:
157 dev_info(&pdev->dev, "%s disabled\n", opt->name);
158 return 0;
159 }
160 break;
161 case range_option:
162 if (*value >= opt->arg.r.min && *value <= opt->arg.r.max) {
163 dev_info(&pdev->dev, "%s set to %i\n", opt->name,
164 *value);
165 return 0;
166 }
167 break;
168 case list_option:{
169 int i;
170 struct atl1_opt_list *ent;
171
172 for (i = 0; i < opt->arg.l.nr; i++) {
173 ent = &opt->arg.l.p[i];
174 if (*value == ent->i) {
175 if (ent->str[0] != '\0')
176 dev_info(&pdev->dev, "%s\n",
177 ent->str);
178 return 0;
179 }
180 }
181 }
182 break;
183
184 default:
185 break;
186 }
187
188 dev_info(&pdev->dev, "invalid %s specified (%i) %s\n",
189 opt->name, *value, opt->err);
190 *value = opt->def;
191 return -1;
192}
193
194/*
195 * atl1_check_options - Range Checking for Command Line Parameters
196 * @adapter: board private structure
197 *
198 * This routine checks all command line parameters for valid user
199 * input. If an invalid value is given, or if no user specified
200 * value exists, a default value is used. The final value is stored
201 * in a variable in the adapter structure.
202 */
203void __devinit atl1_check_options(struct atl1_adapter *adapter)
204{
205 struct pci_dev *pdev = adapter->pdev;
206 int bd = adapter->bd_number;
207 if (bd >= ATL1_MAX_NIC) {
208 dev_notice(&pdev->dev, "no configuration for board#%i\n", bd);
209 dev_notice(&pdev->dev, "using defaults for all values\n");
210 }
211 { /* Interrupt Moderate Timer */
212 struct atl1_option opt = {
213 .type = range_option,
214 .name = "Interrupt Moderator Timer",
215 .err = "using default of "
216 __MODULE_STRING(DEFAULT_INT_MOD_CNT),
217 .def = DEFAULT_INT_MOD_CNT,
218 .arg = {.r = {.min = MIN_INT_MOD_CNT,
219 .max = MAX_INT_MOD_CNT} }
220 };
221 int val;
222 if (num_int_mod_timer > bd) {
223 val = int_mod_timer[bd];
224 atl1_validate_option(&val, &opt, pdev);
225 adapter->imt = (u16) val;
226 } else
227 adapter->imt = (u16) (opt.def);
228 }
229}
230
f3cc28c7
JC		 231/*
232 * atl1_pci_tbl - PCI Device ID Table
233 */
234static const struct pci_device_id atl1_pci_tbl[] = {
e81e557a 235 {PCI_DEVICE(PCI_VENDOR_ID_ATTANSIC, PCI_DEVICE_ID_ATTANSIC_L1)},
f3cc28c7
JC		 236 /* required last entry */
237 {0,}
238};
f3cc28c7
JC		 239MODULE_DEVICE_TABLE(pci, atl1_pci_tbl);
240
460578bf
JC		 241static const u32 atl1_default_msg = NETIF_MSG_DRV | NETIF_MSG_PROBE |
242 NETIF_MSG_LINK | NETIF_MSG_TIMER | NETIF_MSG_IFDOWN | NETIF_MSG_IFUP;
243
244static int debug = -1;
245module_param(debug, int, 0);
246MODULE_PARM_DESC(debug, "Message level (0=none,...,16=all)");
247
f3cc28c7 248/*
6446a860
JC		 249 * Reset the transmit and receive units; mask and clear all interrupts.
250 * hw - Struct containing variables accessed by shared code
251 * return : 0 or idle status (if error)
f3cc28c7 252 */
6446a860 253static s32 atl1_reset_hw(struct atl1_hw *hw)
f3cc28c7 254{
6446a860
JC		 255 struct pci_dev *pdev = hw->back->pdev;
256 struct atl1_adapter *adapter = hw->back;
257 u32 icr;
258 int i;
f3cc28c7 259
6446a860
JC		 260 /*
261 * Clear Interrupt mask to stop board from generating
262 * interrupts & Clear any pending interrupt events
263 */
264 /*
265 * iowrite32(0, hw->hw_addr + REG_IMR);
266 * iowrite32(0xffffffff, hw->hw_addr + REG_ISR);
267 */
f3cc28c7 268
6446a860
JC		 269 /*
270 * Issue Soft Reset to the MAC. This will reset the chip's
271 * transmit, receive, DMA. It will not effect
272 * the current PCI configuration. The global reset bit is self-
273 * clearing, and should clear within a microsecond.
274 */
275 iowrite32(MASTER_CTRL_SOFT_RST, hw->hw_addr + REG_MASTER_CTRL);
276 ioread32(hw->hw_addr + REG_MASTER_CTRL);
f3cc28c7 277
6446a860
JC		 278 iowrite16(1, hw->hw_addr + REG_PHY_ENABLE);
279 ioread16(hw->hw_addr + REG_PHY_ENABLE);
f3cc28c7 280
6446a860
JC		 281 /* delay about 1ms */
282 msleep(1);
f3cc28c7 283
6446a860
JC		 284 /* Wait at least 10ms for All module to be Idle */
285 for (i = 0; i < 10; i++) {
286 icr = ioread32(hw->hw_addr + REG_IDLE_STATUS);
287 if (!icr)
288 break;
289 /* delay 1 ms */
290 msleep(1);
291 /* FIXME: still the right way to do this? */
292 cpu_relax();
293 }
05ffdd7b 294
6446a860
JC		 295 if (icr) {
296 if (netif_msg_hw(adapter))
297 dev_dbg(&pdev->dev, "ICR = 0x%x\n", icr);
298 return icr;
299 }
05ffdd7b 300
6446a860 301 return 0;
05ffdd7b
JC		 302}
303
6446a860
JC		 304/* function about EEPROM
305 *
306 * check_eeprom_exist
307 * return 0 if eeprom exist
308 */
309static int atl1_check_eeprom_exist(struct atl1_hw *hw)
05ffdd7b 310{
6446a860
JC		 311 u32 value;
312 value = ioread32(hw->hw_addr + REG_SPI_FLASH_CTRL);
313 if (value & SPI_FLASH_CTRL_EN_VPD) {
314 value &= ~SPI_FLASH_CTRL_EN_VPD;
315 iowrite32(value, hw->hw_addr + REG_SPI_FLASH_CTRL);
316 }
05ffdd7b 317
6446a860
JC		 318 value = ioread16(hw->hw_addr + REG_PCIE_CAP_LIST);
319 return ((value & 0xFF00) == 0x6C00) ? 0 : 1;
05ffdd7b
JC		 320}
321
6446a860 322static bool atl1_read_eeprom(struct atl1_hw *hw, u32 offset, u32 *p_value)
05ffdd7b 323{
6446a860
JC		 324 int i;
325 u32 control;
05ffdd7b 326
6446a860
JC		 327 if (offset & 3)
328 /* address do not align */
329 return false;
05ffdd7b 330
6446a860
JC		 331 iowrite32(0, hw->hw_addr + REG_VPD_DATA);
332 control = (offset & VPD_CAP_VPD_ADDR_MASK) << VPD_CAP_VPD_ADDR_SHIFT;
333 iowrite32(control, hw->hw_addr + REG_VPD_CAP);
334 ioread32(hw->hw_addr + REG_VPD_CAP);
05ffdd7b 335
6446a860
JC		 336 for (i = 0; i < 10; i++) {
337 msleep(2);
338 control = ioread32(hw->hw_addr + REG_VPD_CAP);
339 if (control & VPD_CAP_VPD_FLAG)
340 break;
341 }
342 if (control & VPD_CAP_VPD_FLAG) {
343 *p_value = ioread32(hw->hw_addr + REG_VPD_DATA);
344 return true;
345 }
346 /* timeout */
347 return false;
05ffdd7b
JC		 348}
349
f3cc28c7 350/*
6446a860
JC		 351 * Reads the value from a PHY register
352 * hw - Struct containing variables accessed by shared code
353 * reg_addr - address of the PHY register to read
f3cc28c7 354 */
6446a860 355s32 atl1_read_phy_reg(struct atl1_hw *hw, u16 reg_addr, u16 *phy_data)
f3cc28c7 356{
6446a860
JC		 357 u32 val;
358 int i;
f3cc28c7 359
6446a860
JC		 360 val = ((u32) (reg_addr & MDIO_REG_ADDR_MASK)) << MDIO_REG_ADDR_SHIFT |
361 MDIO_START | MDIO_SUP_PREAMBLE | MDIO_RW | MDIO_CLK_25_4 <<
362 MDIO_CLK_SEL_SHIFT;
363 iowrite32(val, hw->hw_addr + REG_MDIO_CTRL);
364 ioread32(hw->hw_addr + REG_MDIO_CTRL);
f3cc28c7 365
6446a860
JC		 366 for (i = 0; i < MDIO_WAIT_TIMES; i++) {
367 udelay(2);
368 val = ioread32(hw->hw_addr + REG_MDIO_CTRL);
369 if (!(val & (MDIO_START | MDIO_BUSY)))
370 break;
371 }
372 if (!(val & (MDIO_START | MDIO_BUSY))) {
373 *phy_data = (u16) val;
374 return 0;
f3cc28c7 375 }
6446a860
JC		 376 return ATLX_ERR_PHY;
377}
f3cc28c7 378
6446a860
JC		 379#define CUSTOM_SPI_CS_SETUP 2
380#define CUSTOM_SPI_CLK_HI 2
381#define CUSTOM_SPI_CLK_LO 2
382#define CUSTOM_SPI_CS_HOLD 2
383#define CUSTOM_SPI_CS_HI 3
f3cc28c7 384
6446a860
JC		 385static bool atl1_spi_read(struct atl1_hw *hw, u32 addr, u32 *buf)
386{
387 int i;
388 u32 value;
f3cc28c7 389
6446a860
JC		 390 iowrite32(0, hw->hw_addr + REG_SPI_DATA);
391 iowrite32(addr, hw->hw_addr + REG_SPI_ADDR);
2ca13da7 392
6446a860
JC		 393 value = SPI_FLASH_CTRL_WAIT_READY |
394 (CUSTOM_SPI_CS_SETUP & SPI_FLASH_CTRL_CS_SETUP_MASK) <<
395 SPI_FLASH_CTRL_CS_SETUP_SHIFT | (CUSTOM_SPI_CLK_HI &
396 SPI_FLASH_CTRL_CLK_HI_MASK) <<
397 SPI_FLASH_CTRL_CLK_HI_SHIFT | (CUSTOM_SPI_CLK_LO &
398 SPI_FLASH_CTRL_CLK_LO_MASK) <<
399 SPI_FLASH_CTRL_CLK_LO_SHIFT | (CUSTOM_SPI_CS_HOLD &
400 SPI_FLASH_CTRL_CS_HOLD_MASK) <<
401 SPI_FLASH_CTRL_CS_HOLD_SHIFT | (CUSTOM_SPI_CS_HI &
402 SPI_FLASH_CTRL_CS_HI_MASK) <<
403 SPI_FLASH_CTRL_CS_HI_SHIFT | (1 & SPI_FLASH_CTRL_INS_MASK) <<
404 SPI_FLASH_CTRL_INS_SHIFT;
f3cc28c7 405
6446a860 406 iowrite32(value, hw->hw_addr + REG_SPI_FLASH_CTRL);
f3cc28c7 407
6446a860
JC		 408 value |= SPI_FLASH_CTRL_START;
409 iowrite32(value, hw->hw_addr + REG_SPI_FLASH_CTRL);
410 ioread32(hw->hw_addr + REG_SPI_FLASH_CTRL);
f3cc28c7 411
6446a860
JC		 412 for (i = 0; i < 10; i++) {
413 msleep(1);
414 value = ioread32(hw->hw_addr + REG_SPI_FLASH_CTRL);
415 if (!(value & SPI_FLASH_CTRL_START))
416 break;
417 }
f3cc28c7 418
6446a860
JC		 419 if (value & SPI_FLASH_CTRL_START)
420 return false;
f3cc28c7 421
6446a860 422 *buf = ioread32(hw->hw_addr + REG_SPI_DATA);
2ca13da7 423
6446a860 424 return true;
f3cc28c7
JC		 425}
426
f3cc28c7 427/*
6446a860
JC		 428 * get_permanent_address
429 * return 0 if get valid mac address,
f3cc28c7 430 */
6446a860 431static int atl1_get_permanent_address(struct atl1_hw *hw)
f3cc28c7 432{
6446a860
JC		 433 u32 addr[2];
434 u32 i, control;
435 u16 reg;
436 u8 eth_addr[ETH_ALEN];
437 bool key_valid;
f3cc28c7 438
6446a860
JC		 439 if (is_valid_ether_addr(hw->perm_mac_addr))
440 return 0;
441
442 /* init */
443 addr[0] = addr[1] = 0;
444
445 if (!atl1_check_eeprom_exist(hw)) {
446 reg = 0;
447 key_valid = false;
448 /* Read out all EEPROM content */
449 i = 0;
450 while (1) {
451 if (atl1_read_eeprom(hw, i + 0x100, &control)) {
452 if (key_valid) {
453 if (reg == REG_MAC_STA_ADDR)
454 addr[0] = control;
455 else if (reg == (REG_MAC_STA_ADDR + 4))
456 addr[1] = control;
457 key_valid = false;
458 } else if ((control & 0xff) == 0x5A) {
459 key_valid = true;
460 reg = (u16) (control >> 16);
461 } else
462 break;
463 } else
464 /* read error */
465 break;
466 i += 4;
05ffdd7b 467 }
6446a860
JC		 468
469 *(u32 *) &eth_addr[2] = swab32(addr[0]);
470 *(u16 *) &eth_addr[0] = swab16(*(u16 *) &addr[1]);
471 if (is_valid_ether_addr(eth_addr)) {
472 memcpy(hw->perm_mac_addr, eth_addr, ETH_ALEN);
473 return 0;
05ffdd7b 474 }
6446a860 475 return 1;
05ffdd7b 476 }
f3cc28c7 477
6446a860
JC		 478 /* see if SPI FLAGS exist ? */
479 addr[0] = addr[1] = 0;
480 reg = 0;
481 key_valid = false;
482 i = 0;
483 while (1) {
484 if (atl1_spi_read(hw, i + 0x1f000, &control)) {
485 if (key_valid) {
486 if (reg == REG_MAC_STA_ADDR)
487 addr[0] = control;
488 else if (reg == (REG_MAC_STA_ADDR + 4))
489 addr[1] = control;
490 key_valid = false;
491 } else if ((control & 0xff) == 0x5A) {
492 key_valid = true;
493 reg = (u16) (control >> 16);
494 } else
495 /* data end */
496 break;
497 } else
498 /* read error */
499 break;
500 i += 4;
501 }
f3cc28c7 502
6446a860
JC		 503 *(u32 *) &eth_addr[2] = swab32(addr[0]);
504 *(u16 *) &eth_addr[0] = swab16(*(u16 *) &addr[1]);
505 if (is_valid_ether_addr(eth_addr)) {
506 memcpy(hw->perm_mac_addr, eth_addr, ETH_ALEN);
507 return 0;
508 }
f3cc28c7 509
6446a860
JC		 510 /*
511 * On some motherboards, the MAC address is written by the
512 * BIOS directly to the MAC register during POST, and is
513 * not stored in eeprom. If all else thus far has failed
514 * to fetch the permanent MAC address, try reading it directly.
515 */
516 addr[0] = ioread32(hw->hw_addr + REG_MAC_STA_ADDR);
517 addr[1] = ioread16(hw->hw_addr + (REG_MAC_STA_ADDR + 4));
518 *(u32 *) &eth_addr[2] = swab32(addr[0]);
519 *(u16 *) &eth_addr[0] = swab16(*(u16 *) &addr[1]);
520 if (is_valid_ether_addr(eth_addr)) {
521 memcpy(hw->perm_mac_addr, eth_addr, ETH_ALEN);
522 return 0;
523 }
f3cc28c7 524
6446a860 525 return 1;
f3cc28c7
JC		 526}
527
05ffdd7b 528/*
6446a860
JC		 529 * Reads the adapter's MAC address from the EEPROM
530 * hw - Struct containing variables accessed by shared code
05ffdd7b 531 */
6446a860 532s32 atl1_read_mac_addr(struct atl1_hw *hw)
f3cc28c7 533{
6446a860 534 u16 i;
f3cc28c7 535
6446a860
JC		 536 if (atl1_get_permanent_address(hw))
537 random_ether_addr(hw->perm_mac_addr);
f3cc28c7 538
6446a860
JC		 539 for (i = 0; i < ETH_ALEN; i++)
540 hw->mac_addr[i] = hw->perm_mac_addr[i];
541 return 0;
f3cc28c7
JC		 542}
543
544/*
6446a860
JC		 545 * Hashes an address to determine its location in the multicast table
546 * hw - Struct containing variables accessed by shared code
547 * mc_addr - the multicast address to hash
05ffdd7b 548 *
6446a860
JC		 549 * atl1_hash_mc_addr
550 * purpose
551 * set hash value for a multicast address
552 * hash calcu processing :
553 * 1. calcu 32bit CRC for multicast address
554 * 2. reverse crc with MSB to LSB
f3cc28c7 555 */
6446a860 556u32 atl1_hash_mc_addr(struct atl1_hw *hw, u8 *mc_addr)
f3cc28c7 557{
6446a860
JC		 558 u32 crc32, value = 0;
559 int i;
f3cc28c7 560
6446a860
JC		 561 crc32 = ether_crc_le(6, mc_addr);
562 for (i = 0; i < 32; i++)
563 value |= (((crc32 >> i) & 1) << (31 - i));
f3cc28c7 564
6446a860 565 return value;
f3cc28c7
JC		 566}
567
6446a860
JC		 568/*
569 * Sets the bit in the multicast table corresponding to the hash value.
570 * hw - Struct containing variables accessed by shared code
571 * hash_value - Multicast address hash value
572 */
573void atl1_hash_set(struct atl1_hw *hw, u32 hash_value)
f3cc28c7 574{
6446a860
JC		 575 u32 hash_bit, hash_reg;
576 u32 mta;
577
578 /*
579 * The HASH Table is a register array of 2 32-bit registers.
580 * It is treated like an array of 64 bits. We want to set
581 * bit BitArray[hash_value]. So we figure out what register
582 * the bit is in, read it, OR in the new bit, then write
583 * back the new value. The register is determined by the
584 * upper 7 bits of the hash value and the bit within that
585 * register are determined by the lower 5 bits of the value.
05ffdd7b 586 */
6446a860
JC		 587 hash_reg = (hash_value >> 31) & 0x1;
588 hash_bit = (hash_value >> 26) & 0x1F;
589 mta = ioread32((hw->hw_addr + REG_RX_HASH_TABLE) + (hash_reg << 2));
590 mta |= (1 << hash_bit);
591 iowrite32(mta, (hw->hw_addr + REG_RX_HASH_TABLE) + (hash_reg << 2));
05ffdd7b 592}
f3cc28c7 593
6446a860
JC		 594/*
595 * Writes a value to a PHY register
596 * hw - Struct containing variables accessed by shared code
597 * reg_addr - address of the PHY register to write
598 * data - data to write to the PHY
599 */
600static s32 atl1_write_phy_reg(struct atl1_hw *hw, u32 reg_addr, u16 phy_data)
05ffdd7b 601{
6446a860
JC		 602 int i;
603 u32 val;
f3cc28c7 604
6446a860
JC		 605 val = ((u32) (phy_data & MDIO_DATA_MASK)) << MDIO_DATA_SHIFT |
606 (reg_addr & MDIO_REG_ADDR_MASK) << MDIO_REG_ADDR_SHIFT |
607 MDIO_SUP_PREAMBLE |
608 MDIO_START | MDIO_CLK_25_4 << MDIO_CLK_SEL_SHIFT;
609 iowrite32(val, hw->hw_addr + REG_MDIO_CTRL);
610 ioread32(hw->hw_addr + REG_MDIO_CTRL);
f3cc28c7 611
6446a860
JC		 612 for (i = 0; i < MDIO_WAIT_TIMES; i++) {
613 udelay(2);
614 val = ioread32(hw->hw_addr + REG_MDIO_CTRL);
615 if (!(val & (MDIO_START | MDIO_BUSY)))
616 break;
05ffdd7b 617 }
f3cc28c7 618
6446a860 619 if (!(val & (MDIO_START | MDIO_BUSY)))
305282ba 620 return 0;
f3cc28c7 621
6446a860
JC		 622 return ATLX_ERR_PHY;
623}
f3cc28c7 624
6446a860
JC		 625/*
626 * Make L001's PHY out of Power Saving State (bug)
627 * hw - Struct containing variables accessed by shared code
628 * when power on, L001's PHY always on Power saving State
629 * (Gigabit Link forbidden)
630 */
631static s32 atl1_phy_leave_power_saving(struct atl1_hw *hw)
632{
633 s32 ret;
634 ret = atl1_write_phy_reg(hw, 29, 0x0029);
635 if (ret)
636 return ret;
637 return atl1_write_phy_reg(hw, 30, 0);
638}
639
640/*
641 *TODO: do something or get rid of this
642 */
76fef2b6 643#ifdef CONFIG_PM
6446a860
JC		 644static s32 atl1_phy_enter_power_saving(struct atl1_hw *hw)
645{
646/* s32 ret_val;
647 * u16 phy_data;
648 */
649
650/*
651 ret_val = atl1_write_phy_reg(hw, ...);
652 ret_val = atl1_write_phy_reg(hw, ...);
653 ....
654*/
655 return 0;
656}
76fef2b6 657#endif
6446a860
JC		 658
659/*
660 * Resets the PHY and make all config validate
661 * hw - Struct containing variables accessed by shared code
662 *
663 * Sets bit 15 and 12 of the MII Control regiser (for F001 bug)
664 */
665static s32 atl1_phy_reset(struct atl1_hw *hw)
666{
667 struct pci_dev *pdev = hw->back->pdev;
668 struct atl1_adapter *adapter = hw->back;
669 s32 ret_val;
670 u16 phy_data;
671
672 if (hw->media_type == MEDIA_TYPE_AUTO_SENSOR ||
673 hw->media_type == MEDIA_TYPE_1000M_FULL)
674 phy_data = MII_CR_RESET | MII_CR_AUTO_NEG_EN;
675 else {
05ffdd7b
JC		 676 switch (hw->media_type) {
677 case MEDIA_TYPE_100M_FULL:
6446a860
JC		 678 phy_data =
679 MII_CR_FULL_DUPLEX | MII_CR_SPEED_100 |
680 MII_CR_RESET;
05ffdd7b
JC		 681 break;
682 case MEDIA_TYPE_100M_HALF:
683 phy_data = MII_CR_SPEED_100 | MII_CR_RESET;
684 break;
685 case MEDIA_TYPE_10M_FULL:
686 phy_data =
687 MII_CR_FULL_DUPLEX | MII_CR_SPEED_10 | MII_CR_RESET;
688 break;
305282ba
JC		 689 default:
690 /* MEDIA_TYPE_10M_HALF: */
05ffdd7b
JC		 691 phy_data = MII_CR_SPEED_10 | MII_CR_RESET;
692 break;
f3cc28c7 693 }
f3cc28c7 694 }
f3cc28c7 695
6446a860
JC		 696 ret_val = atl1_write_phy_reg(hw, MII_BMCR, phy_data);
697 if (ret_val) {
698 u32 val;
699 int i;
700 /* pcie serdes link may be down! */
701 if (netif_msg_hw(adapter))
702 dev_dbg(&pdev->dev, "pcie phy link down\n");
703
704 for (i = 0; i < 25; i++) {
705 msleep(1);
706 val = ioread32(hw->hw_addr + REG_MDIO_CTRL);
707 if (!(val & (MDIO_START | MDIO_BUSY)))
708 break;
709 }
f3cc28c7 710
6446a860
JC		 711 if ((val & (MDIO_START | MDIO_BUSY)) != 0) {
712 if (netif_msg_hw(adapter))
713 dev_warn(&pdev->dev,
714 "pcie link down at least 25ms\n");
715 return ret_val;
716 }
717 }
305282ba 718 return 0;
2ca13da7
JC		 719}
720
6446a860
JC		 721/*
722 * Configures PHY autoneg and flow control advertisement settings
723 * hw - Struct containing variables accessed by shared code
724 */
725static s32 atl1_phy_setup_autoneg_adv(struct atl1_hw *hw)
05ffdd7b 726{
6446a860
JC		 727 s32 ret_val;
728 s16 mii_autoneg_adv_reg;
729 s16 mii_1000t_ctrl_reg;
f3cc28c7 730
6446a860
JC		 731 /* Read the MII Auto-Neg Advertisement Register (Address 4). */
732 mii_autoneg_adv_reg = MII_AR_DEFAULT_CAP_MASK;
f3cc28c7 733
6446a860
JC		 734 /* Read the MII 1000Base-T Control Register (Address 9). */
735 mii_1000t_ctrl_reg = MII_ATLX_CR_1000T_DEFAULT_CAP_MASK;
f3cc28c7 736
6446a860
JC		 737 /*
738 * First we clear all the 10/100 mb speed bits in the Auto-Neg
739 * Advertisement Register (Address 4) and the 1000 mb speed bits in
740 * the 1000Base-T Control Register (Address 9).
741 */
742 mii_autoneg_adv_reg &= ~MII_AR_SPEED_MASK;
743 mii_1000t_ctrl_reg &= ~MII_ATLX_CR_1000T_SPEED_MASK;
f3cc28c7 744
6446a860
JC		 745 /*
746 * Need to parse media_type and set up
747 * the appropriate PHY registers.
748 */
749 switch (hw->media_type) {
750 case MEDIA_TYPE_AUTO_SENSOR:
751 mii_autoneg_adv_reg |= (MII_AR_10T_HD_CAPS |
752 MII_AR_10T_FD_CAPS |
753 MII_AR_100TX_HD_CAPS |
754 MII_AR_100TX_FD_CAPS);
755 mii_1000t_ctrl_reg |= MII_ATLX_CR_1000T_FD_CAPS;
756 break;
f3cc28c7 757
6446a860
JC		 758 case MEDIA_TYPE_1000M_FULL:
759 mii_1000t_ctrl_reg |= MII_ATLX_CR_1000T_FD_CAPS;
760 break;
f3cc28c7 761
6446a860
JC		 762 case MEDIA_TYPE_100M_FULL:
763 mii_autoneg_adv_reg |= MII_AR_100TX_FD_CAPS;
764 break;
f3cc28c7 765
6446a860
JC		 766 case MEDIA_TYPE_100M_HALF:
767 mii_autoneg_adv_reg |= MII_AR_100TX_HD_CAPS;
768 break;
f3cc28c7 769
6446a860
JC		 770 case MEDIA_TYPE_10M_FULL:
771 mii_autoneg_adv_reg |= MII_AR_10T_FD_CAPS;
05ffdd7b 772 break;
6446a860 773
05ffdd7b 774 default:
6446a860 775 mii_autoneg_adv_reg |= MII_AR_10T_HD_CAPS;
05ffdd7b 776 break;
f3cc28c7 777 }
f3cc28c7 778
6446a860
JC		 779 /* flow control fixed to enable all */
780 mii_autoneg_adv_reg |= (MII_AR_ASM_DIR | MII_AR_PAUSE);
f3cc28c7 781
6446a860
JC		 782 hw->mii_autoneg_adv_reg = mii_autoneg_adv_reg;
783 hw->mii_1000t_ctrl_reg = mii_1000t_ctrl_reg;
f3cc28c7 784
6446a860
JC		 785 ret_val = atl1_write_phy_reg(hw, MII_ADVERTISE, mii_autoneg_adv_reg);
786 if (ret_val)
787 return ret_val;
f3cc28c7 788
6446a860
JC		 789 ret_val = atl1_write_phy_reg(hw, MII_ATLX_CR, mii_1000t_ctrl_reg);
790 if (ret_val)
791 return ret_val;
f3cc28c7 792
6446a860 793 return 0;
f3cc28c7 794}
f3cc28c7 795
05ffdd7b 796/*
6446a860
JC		 797 * Configures link settings.
798 * hw - Struct containing variables accessed by shared code
799 * Assumes the hardware has previously been reset and the
800 * transmitter and receiver are not enabled.
05ffdd7b 801 */
6446a860 802static s32 atl1_setup_link(struct atl1_hw *hw)
f3cc28c7 803{
6446a860
JC		 804 struct pci_dev *pdev = hw->back->pdev;
805 struct atl1_adapter *adapter = hw->back;
806 s32 ret_val;
f3cc28c7 807
6446a860
JC		 808 /*
809 * Options:
810 * PHY will advertise value(s) parsed from
811 * autoneg_advertised and fc
812 * no matter what autoneg is , We will not wait link result.
813 */
814 ret_val = atl1_phy_setup_autoneg_adv(hw);
815 if (ret_val) {
816 if (netif_msg_link(adapter))
817 dev_dbg(&pdev->dev,
818 "error setting up autonegotiation\n");
819 return ret_val;
820 }
821 /* SW.Reset , En-Auto-Neg if needed */
822 ret_val = atl1_phy_reset(hw);
823 if (ret_val) {
824 if (netif_msg_link(adapter))
825 dev_dbg(&pdev->dev, "error resetting phy\n");
826 return ret_val;
827 }
828 hw->phy_configured = true;
829 return ret_val;
830}
f3cc28c7 831
6446a860 832static void atl1_init_flash_opcode(struct atl1_hw *hw)
f3cc28c7 833{
6446a860
JC		 834 if (hw->flash_vendor >= ARRAY_SIZE(flash_table))
835 /* Atmel */
836 hw->flash_vendor = 0;
f3cc28c7 837
6446a860
JC		 838 /* Init OP table */
839 iowrite8(flash_table[hw->flash_vendor].cmd_program,
840 hw->hw_addr + REG_SPI_FLASH_OP_PROGRAM);
841 iowrite8(flash_table[hw->flash_vendor].cmd_sector_erase,
842 hw->hw_addr + REG_SPI_FLASH_OP_SC_ERASE);
843 iowrite8(flash_table[hw->flash_vendor].cmd_chip_erase,
844 hw->hw_addr + REG_SPI_FLASH_OP_CHIP_ERASE);
845 iowrite8(flash_table[hw->flash_vendor].cmd_rdid,
846 hw->hw_addr + REG_SPI_FLASH_OP_RDID);
847 iowrite8(flash_table[hw->flash_vendor].cmd_wren,
848 hw->hw_addr + REG_SPI_FLASH_OP_WREN);
849 iowrite8(flash_table[hw->flash_vendor].cmd_rdsr,
850 hw->hw_addr + REG_SPI_FLASH_OP_RDSR);
851 iowrite8(flash_table[hw->flash_vendor].cmd_wrsr,
852 hw->hw_addr + REG_SPI_FLASH_OP_WRSR);
853 iowrite8(flash_table[hw->flash_vendor].cmd_read,
854 hw->hw_addr + REG_SPI_FLASH_OP_READ);
f3cc28c7 855}
f3cc28c7 856
6446a860
JC		 857/*
858 * Performs basic configuration of the adapter.
859 * hw - Struct containing variables accessed by shared code
860 * Assumes that the controller has previously been reset and is in a
861 * post-reset uninitialized state. Initializes multicast table,
862 * and Calls routines to setup link
863 * Leaves the transmit and receive units disabled and uninitialized.
864 */
865static s32 atl1_init_hw(struct atl1_hw *hw)
05ffdd7b 866{
6446a860 867 u32 ret_val = 0;
f3cc28c7 868
6446a860
JC		 869 /* Zero out the Multicast HASH table */
870 iowrite32(0, hw->hw_addr + REG_RX_HASH_TABLE);
871 /* clear the old settings from the multicast hash table */
872 iowrite32(0, (hw->hw_addr + REG_RX_HASH_TABLE) + (1 << 2));
f3cc28c7 873
6446a860 874 atl1_init_flash_opcode(hw);
f3cc28c7 875
6446a860
JC		 876 if (!hw->phy_configured) {
877 /* enable GPHY LinkChange Interrrupt */
878 ret_val = atl1_write_phy_reg(hw, 18, 0xC00);
879 if (ret_val)
880 return ret_val;
881 /* make PHY out of power-saving state */
882 ret_val = atl1_phy_leave_power_saving(hw);
883 if (ret_val)
884 return ret_val;
885 /* Call a subroutine to configure the link */
886 ret_val = atl1_setup_link(hw);
887 }
888 return ret_val;
f3cc28c7 889}
f3cc28c7
JC		 890
891/*
6446a860
JC		 892 * Detects the current speed and duplex settings of the hardware.
893 * hw - Struct containing variables accessed by shared code
894 * speed - Speed of the connection
895 * duplex - Duplex setting of the connection
f3cc28c7 896 */
6446a860 897static s32 atl1_get_speed_and_duplex(struct atl1_hw *hw, u16 *speed, u16 *duplex)
f3cc28c7 898{
6446a860
JC		 899 struct pci_dev *pdev = hw->back->pdev;
900 struct atl1_adapter *adapter = hw->back;
901 s32 ret_val;
902 u16 phy_data;
f3cc28c7 903
6446a860
JC		 904 /* ; --- Read PHY Specific Status Register (17) */
905 ret_val = atl1_read_phy_reg(hw, MII_ATLX_PSSR, &phy_data);
906 if (ret_val)
907 return ret_val;
f3cc28c7 908
6446a860
JC		 909 if (!(phy_data & MII_ATLX_PSSR_SPD_DPLX_RESOLVED))
910 return ATLX_ERR_PHY_RES;
f3cc28c7 911
6446a860
JC		 912 switch (phy_data & MII_ATLX_PSSR_SPEED) {
913 case MII_ATLX_PSSR_1000MBS:
914 *speed = SPEED_1000;
915 break;
916 case MII_ATLX_PSSR_100MBS:
917 *speed = SPEED_100;
918 break;
919 case MII_ATLX_PSSR_10MBS:
920 *speed = SPEED_10;
921 break;
922 default:
923 if (netif_msg_hw(adapter))
924 dev_dbg(&pdev->dev, "error getting speed\n");
925 return ATLX_ERR_PHY_SPEED;
926 break;
f3cc28c7 927 }
6446a860
JC		 928 if (phy_data & MII_ATLX_PSSR_DPLX)
929 *duplex = FULL_DUPLEX;
930 else
931 *duplex = HALF_DUPLEX;
932
933 return 0;
05ffdd7b 934}
f3cc28c7 935
6446a860 936void atl1_set_mac_addr(struct atl1_hw *hw)
05ffdd7b 937{
6446a860
JC		 938 u32 value;
939 /*
940 * 00-0B-6A-F6-00-DC
941 * 0: 6AF600DC 1: 000B
942 * low dword
943 */
944 value = (((u32) hw->mac_addr[2]) << 24) |
945 (((u32) hw->mac_addr[3]) << 16) |
946 (((u32) hw->mac_addr[4]) << 8) | (((u32) hw->mac_addr[5]));
947 iowrite32(value, hw->hw_addr + REG_MAC_STA_ADDR);
948 /* high dword */
949 value = (((u32) hw->mac_addr[0]) << 8) | (((u32) hw->mac_addr[1]));
950 iowrite32(value, (hw->hw_addr + REG_MAC_STA_ADDR) + (1 << 2));
05ffdd7b 951}
f3cc28c7
JC		 952
953/*
954 * atl1_sw_init - Initialize general software structures (struct atl1_adapter)
955 * @adapter: board private structure to initialize
956 *
957 * atl1_sw_init initializes the Adapter private data structure.
958 * Fields are initialized based on PCI device information and
959 * OS network device settings (MTU size).
960 */
961static int __devinit atl1_sw_init(struct atl1_adapter *adapter)
962{
963 struct atl1_hw *hw = &adapter->hw;
964 struct net_device *netdev = adapter->netdev;
f3cc28c7 965
2a49128f 966 hw->max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN;
a3093d9b 967 hw->min_frame_size = ETH_ZLEN + ETH_FCS_LEN;
f3cc28c7
JC		 968
969 adapter->wol = 0;
970 adapter->rx_buffer_len = (hw->max_frame_size + 7) & ~7;
6446a860 971 adapter->ict = 50000; /* 100ms */
f3cc28c7
JC		 972 adapter->link_speed = SPEED_0; /* hardware init */
973 adapter->link_duplex = FULL_DUPLEX;
974
975 hw->phy_configured = false;
976 hw->preamble_len = 7;
977 hw->ipgt = 0x60;
978 hw->min_ifg = 0x50;
979 hw->ipgr1 = 0x40;
980 hw->ipgr2 = 0x60;
981 hw->max_retry = 0xf;
982 hw->lcol = 0x37;
983 hw->jam_ipg = 7;
984 hw->rfd_burst = 8;
985 hw->rrd_burst = 8;
986 hw->rfd_fetch_gap = 1;
987 hw->rx_jumbo_th = adapter->rx_buffer_len / 8;
988 hw->rx_jumbo_lkah = 1;
989 hw->rrd_ret_timer = 16;
990 hw->tpd_burst = 4;
991 hw->tpd_fetch_th = 16;
992 hw->txf_burst = 0x100;
993 hw->tx_jumbo_task_th = (hw->max_frame_size + 7) >> 3;
994 hw->tpd_fetch_gap = 1;
995 hw->rcb_value = atl1_rcb_64;
996 hw->dma_ord = atl1_dma_ord_enh;
997 hw->dmar_block = atl1_dma_req_256;
998 hw->dmaw_block = atl1_dma_req_256;
999 hw->cmb_rrd = 4;
1000 hw->cmb_tpd = 4;
1001 hw->cmb_rx_timer = 1; /* about 2us */
1002 hw->cmb_tx_timer = 1; /* about 2us */
1003 hw->smb_timer = 100000; /* about 200ms */
1004
f3cc28c7
JC		 1005 spin_lock_init(&adapter->lock);
1006 spin_lock_init(&adapter->mb_lock);
1007
1008 return 0;
1009}
1010
05ffdd7b
JC		 1011static int mdio_read(struct net_device *netdev, int phy_id, int reg_num)
1012{
1013 struct atl1_adapter *adapter = netdev_priv(netdev);
1014 u16 result;
1015
1016 atl1_read_phy_reg(&adapter->hw, reg_num & 0x1f, &result);
1017
1018 return result;
1019}
1020
1021static void mdio_write(struct net_device *netdev, int phy_id, int reg_num,
1022 int val)
1023{
1024 struct atl1_adapter *adapter = netdev_priv(netdev);
1025
1026 atl1_write_phy_reg(&adapter->hw, reg_num, val);
1027}
1028
1029/*
1030 * atl1_mii_ioctl -
1031 * @netdev:
1032 * @ifreq:
1033 * @cmd:
1034 */
1035static int atl1_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
1036{
1037 struct atl1_adapter *adapter = netdev_priv(netdev);
1038 unsigned long flags;
1039 int retval;
1040
1041 if (!netif_running(netdev))
1042 return -EINVAL;
1043
1044 spin_lock_irqsave(&adapter->lock, flags);
1045 retval = generic_mii_ioctl(&adapter->mii, if_mii(ifr), cmd, NULL);
1046 spin_unlock_irqrestore(&adapter->lock, flags);
1047
1048 return retval;
1049}
1050
f3cc28c7
JC		 1051/*
1052 * atl1_setup_mem_resources - allocate Tx / RX descriptor resources
1053 * @adapter: board private structure
1054 *
1055 * Return 0 on success, negative on failure
1056 */
6446a860 1057static s32 atl1_setup_ring_resources(struct atl1_adapter *adapter)
f3cc28c7
JC		 1058{
1059 struct atl1_tpd_ring *tpd_ring = &adapter->tpd_ring;
1060 struct atl1_rfd_ring *rfd_ring = &adapter->rfd_ring;
1061 struct atl1_rrd_ring *rrd_ring = &adapter->rrd_ring;
1062 struct atl1_ring_header *ring_header = &adapter->ring_header;
1063 struct pci_dev *pdev = adapter->pdev;
1064 int size;
1065 u8 offset = 0;
1066
1067 size = sizeof(struct atl1_buffer) * (tpd_ring->count + rfd_ring->count);
1068 tpd_ring->buffer_info = kzalloc(size, GFP_KERNEL);
1069 if (unlikely(!tpd_ring->buffer_info)) {
6446a860
JC		 1070 if (netif_msg_drv(adapter))
1071 dev_err(&pdev->dev, "kzalloc failed , size = D%d\n",
1072 size);
f3cc28c7
JC		 1073 goto err_nomem;
1074 }
1075 rfd_ring->buffer_info =
53ffb42c 1076 (struct atl1_buffer *)(tpd_ring->buffer_info + tpd_ring->count);
f3cc28c7 1077
6446a860
JC		 1078 /*
1079 * real ring DMA buffer
53ffb42c
JC		 1080 * each ring/block may need up to 8 bytes for alignment, hence the
1081 * additional 40 bytes tacked onto the end.
1082 */
1083 ring_header->size = size =
1084 sizeof(struct tx_packet_desc) * tpd_ring->count
1085 + sizeof(struct rx_free_desc) * rfd_ring->count
1086 + sizeof(struct rx_return_desc) * rrd_ring->count
1087 + sizeof(struct coals_msg_block)
1088 + sizeof(struct stats_msg_block)
1089 + 40;
f3cc28c7
JC		 1090
1091 ring_header->desc = pci_alloc_consistent(pdev, ring_header->size,
53ffb42c 1092 &ring_header->dma);
f3cc28c7 1093 if (unlikely(!ring_header->desc)) {
6446a860
JC		 1094 if (netif_msg_drv(adapter))
1095 dev_err(&pdev->dev, "pci_alloc_consistent failed\n");
f3cc28c7
JC		 1096 goto err_nomem;
1097 }
1098
1099 memset(ring_header->desc, 0, ring_header->size);
1100
1101 /* init TPD ring */
1102 tpd_ring->dma = ring_header->dma;
1103 offset = (tpd_ring->dma & 0x7) ? (8 - (ring_header->dma & 0x7)) : 0;
1104 tpd_ring->dma += offset;
1105 tpd_ring->desc = (u8 *) ring_header->desc + offset;
1106 tpd_ring->size = sizeof(struct tx_packet_desc) * tpd_ring->count;
f3cc28c7
JC		 1107
1108 /* init RFD ring */
1109 rfd_ring->dma = tpd_ring->dma + tpd_ring->size;
1110 offset = (rfd_ring->dma & 0x7) ? (8 - (rfd_ring->dma & 0x7)) : 0;
1111 rfd_ring->dma += offset;
1112 rfd_ring->desc = (u8 *) tpd_ring->desc + (tpd_ring->size + offset);
1113 rfd_ring->size = sizeof(struct rx_free_desc) * rfd_ring->count;
2ca13da7 1114
f3cc28c7
JC		 1115
1116 /* init RRD ring */
1117 rrd_ring->dma = rfd_ring->dma + rfd_ring->size;
1118 offset = (rrd_ring->dma & 0x7) ? (8 - (rrd_ring->dma & 0x7)) : 0;
1119 rrd_ring->dma += offset;
1120 rrd_ring->desc = (u8 *) rfd_ring->desc + (rfd_ring->size + offset);
1121 rrd_ring->size = sizeof(struct rx_return_desc) * rrd_ring->count;
2ca13da7 1122
f3cc28c7
JC		 1123
1124 /* init CMB */
1125 adapter->cmb.dma = rrd_ring->dma + rrd_ring->size;
1126 offset = (adapter->cmb.dma & 0x7) ? (8 - (adapter->cmb.dma & 0x7)) : 0;
1127 adapter->cmb.dma += offset;
53ffb42c
JC		 1128 adapter->cmb.cmb = (struct coals_msg_block *)
1129 ((u8 *) rrd_ring->desc + (rrd_ring->size + offset));
f3cc28c7
JC		 1130
1131 /* init SMB */
1132 adapter->smb.dma = adapter->cmb.dma + sizeof(struct coals_msg_block);
1133 offset = (adapter->smb.dma & 0x7) ? (8 - (adapter->smb.dma & 0x7)) : 0;
1134 adapter->smb.dma += offset;
1135 adapter->smb.smb = (struct stats_msg_block *)
53ffb42c
JC		 1136 ((u8 *) adapter->cmb.cmb +
1137 (sizeof(struct coals_msg_block) + offset));
f3cc28c7 1138
6446a860 1139 return 0;
f3cc28c7
JC		 1140
1141err_nomem:
1142 kfree(tpd_ring->buffer_info);
1143 return -ENOMEM;
1144}
1145
3d2557f6 1146static void atl1_init_ring_ptrs(struct atl1_adapter *adapter)
f3cc28c7 1147{
2ca13da7
JC		 1148 struct atl1_tpd_ring *tpd_ring = &adapter->tpd_ring;
1149 struct atl1_rfd_ring *rfd_ring = &adapter->rfd_ring;
1150 struct atl1_rrd_ring *rrd_ring = &adapter->rrd_ring;
f3cc28c7 1151
2ca13da7
JC		 1152 atomic_set(&tpd_ring->next_to_use, 0);
1153 atomic_set(&tpd_ring->next_to_clean, 0);
f3cc28c7 1154
2ca13da7
JC		 1155 rfd_ring->next_to_clean = 0;
1156 atomic_set(&rfd_ring->next_to_use, 0);
1157
1158 rrd_ring->next_to_use = 0;
1159 atomic_set(&rrd_ring->next_to_clean, 0);
f3cc28c7
JC		 1160}
1161
f3cc28c7 1162/*
05ffdd7b 1163 * atl1_clean_rx_ring - Free RFD Buffers
f3cc28c7
JC		 1164 * @adapter: board private structure
1165 */
05ffdd7b 1166static void atl1_clean_rx_ring(struct atl1_adapter *adapter)
f3cc28c7 1167{
05ffdd7b
JC		 1168 struct atl1_rfd_ring *rfd_ring = &adapter->rfd_ring;
1169 struct atl1_rrd_ring *rrd_ring = &adapter->rrd_ring;
1170 struct atl1_buffer *buffer_info;
1171 struct pci_dev *pdev = adapter->pdev;
1172 unsigned long size;
1173 unsigned int i;
f3cc28c7 1174
05ffdd7b
JC		 1175 /* Free all the Rx ring sk_buffs */
1176 for (i = 0; i < rfd_ring->count; i++) {
1177 buffer_info = &rfd_ring->buffer_info[i];
1178 if (buffer_info->dma) {
1179 pci_unmap_page(pdev, buffer_info->dma,
1180 buffer_info->length, PCI_DMA_FROMDEVICE);
1181 buffer_info->dma = 0;
1182 }
1183 if (buffer_info->skb) {
1184 dev_kfree_skb(buffer_info->skb);
1185 buffer_info->skb = NULL;
1186 }
1187 }
f3cc28c7 1188
05ffdd7b
JC		 1189 size = sizeof(struct atl1_buffer) * rfd_ring->count;
1190 memset(rfd_ring->buffer_info, 0, size);
f3cc28c7 1191
05ffdd7b
JC		 1192 /* Zero out the descriptor ring */
1193 memset(rfd_ring->desc, 0, rfd_ring->size);
f3cc28c7 1194
05ffdd7b
JC		 1195 rfd_ring->next_to_clean = 0;
1196 atomic_set(&rfd_ring->next_to_use, 0);
f3cc28c7 1197
05ffdd7b
JC		 1198 rrd_ring->next_to_use = 0;
1199 atomic_set(&rrd_ring->next_to_clean, 0);
f3cc28c7
JC		 1200}
1201
05ffdd7b
JC		 1202/*
1203 * atl1_clean_tx_ring - Free Tx Buffers
1204 * @adapter: board private structure
1205 */
1206static void atl1_clean_tx_ring(struct atl1_adapter *adapter)
f3cc28c7 1207{
05ffdd7b
JC		 1208 struct atl1_tpd_ring *tpd_ring = &adapter->tpd_ring;
1209 struct atl1_buffer *buffer_info;
53ffb42c 1210 struct pci_dev *pdev = adapter->pdev;
05ffdd7b
JC		 1211 unsigned long size;
1212 unsigned int i;
f3cc28c7 1213
05ffdd7b
JC		 1214 /* Free all the Tx ring sk_buffs */
1215 for (i = 0; i < tpd_ring->count; i++) {
1216 buffer_info = &tpd_ring->buffer_info[i];
1217 if (buffer_info->dma) {
1218 pci_unmap_page(pdev, buffer_info->dma,
1219 buffer_info->length, PCI_DMA_TODEVICE);
1220 buffer_info->dma = 0;
f3cc28c7
JC		 1221 }
1222 }
1223
05ffdd7b
JC		 1224 for (i = 0; i < tpd_ring->count; i++) {
1225 buffer_info = &tpd_ring->buffer_info[i];
1226 if (buffer_info->skb) {
1227 dev_kfree_skb_any(buffer_info->skb);
1228 buffer_info->skb = NULL;
f3cc28c7 1229 }
f3cc28c7
JC		 1230 }
1231
05ffdd7b
JC		 1232 size = sizeof(struct atl1_buffer) * tpd_ring->count;
1233 memset(tpd_ring->buffer_info, 0, size);
f3cc28c7 1234
05ffdd7b
JC		 1235 /* Zero out the descriptor ring */
1236 memset(tpd_ring->desc, 0, tpd_ring->size);
f3cc28c7 1237
05ffdd7b
JC		 1238 atomic_set(&tpd_ring->next_to_use, 0);
1239 atomic_set(&tpd_ring->next_to_clean, 0);
f3cc28c7
JC		 1240}
1241
1242/*
05ffdd7b
JC		 1243 * atl1_free_ring_resources - Free Tx / RX descriptor Resources
1244 * @adapter: board private structure
1245 *
1246 * Free all transmit software resources
f3cc28c7 1247 */
6446a860 1248static void atl1_free_ring_resources(struct atl1_adapter *adapter)
f3cc28c7 1249{
f3cc28c7 1250 struct pci_dev *pdev = adapter->pdev;
05ffdd7b
JC		 1251 struct atl1_tpd_ring *tpd_ring = &adapter->tpd_ring;
1252 struct atl1_rfd_ring *rfd_ring = &adapter->rfd_ring;
1253 struct atl1_rrd_ring *rrd_ring = &adapter->rrd_ring;
1254 struct atl1_ring_header *ring_header = &adapter->ring_header;
f3cc28c7 1255
05ffdd7b
JC		 1256 atl1_clean_tx_ring(adapter);
1257 atl1_clean_rx_ring(adapter);
f3cc28c7 1258
05ffdd7b
JC		 1259 kfree(tpd_ring->buffer_info);
1260 pci_free_consistent(pdev, ring_header->size, ring_header->desc,
1261 ring_header->dma);
f3cc28c7 1262
05ffdd7b
JC		 1263 tpd_ring->buffer_info = NULL;
1264 tpd_ring->desc = NULL;
1265 tpd_ring->dma = 0;
f3cc28c7 1266
05ffdd7b
JC		 1267 rfd_ring->buffer_info = NULL;
1268 rfd_ring->desc = NULL;
1269 rfd_ring->dma = 0;
f3cc28c7 1270
05ffdd7b
JC		 1271 rrd_ring->desc = NULL;
1272 rrd_ring->dma = 0;
f3cc28c7
JC		 1273}
1274
05ffdd7b 1275static void atl1_setup_mac_ctrl(struct atl1_adapter *adapter)
f3cc28c7 1276{
f3cc28c7 1277 u32 value;
05ffdd7b
JC		 1278 struct atl1_hw *hw = &adapter->hw;
1279 struct net_device *netdev = adapter->netdev;
1280 /* Config MAC CTRL Register */
1281 value = MAC_CTRL_TX_EN | MAC_CTRL_RX_EN;
1282 /* duplex */
1283 if (FULL_DUPLEX == adapter->link_duplex)
1284 value |= MAC_CTRL_DUPLX;
1285 /* speed */
1286 value |= ((u32) ((SPEED_1000 == adapter->link_speed) ?
1287 MAC_CTRL_SPEED_1000 : MAC_CTRL_SPEED_10_100) <<
1288 MAC_CTRL_SPEED_SHIFT);
1289 /* flow control */
1290 value |= (MAC_CTRL_TX_FLOW | MAC_CTRL_RX_FLOW);
1291 /* PAD & CRC */
1292 value |= (MAC_CTRL_ADD_CRC | MAC_CTRL_PAD);
1293 /* preamble length */
1294 value |= (((u32) adapter->hw.preamble_len
1295 & MAC_CTRL_PRMLEN_MASK) << MAC_CTRL_PRMLEN_SHIFT);
1296 /* vlan */
1297 if (adapter->vlgrp)
1298 value |= MAC_CTRL_RMV_VLAN;
1299 /* rx checksum
1300 if (adapter->rx_csum)
1301 value |= MAC_CTRL_RX_CHKSUM_EN;
1302 */
1303 /* filter mode */
1304 value |= MAC_CTRL_BC_EN;
1305 if (netdev->flags & IFF_PROMISC)
1306 value |= MAC_CTRL_PROMIS_EN;
1307 else if (netdev->flags & IFF_ALLMULTI)
1308 value |= MAC_CTRL_MC_ALL_EN;
1309 /* value |= MAC_CTRL_LOOPBACK; */
1310 iowrite32(value, hw->hw_addr + REG_MAC_CTRL);
1311}
f3cc28c7 1312
05ffdd7b
JC		 1313static u32 atl1_check_link(struct atl1_adapter *adapter)
1314{
1315 struct atl1_hw *hw = &adapter->hw;
1316 struct net_device *netdev = adapter->netdev;
1317 u32 ret_val;
1318 u16 speed, duplex, phy_data;
1319 int reconfig = 0;
f3cc28c7 1320
05ffdd7b
JC		 1321 /* MII_BMSR must read twice */
1322 atl1_read_phy_reg(hw, MII_BMSR, &phy_data);
1323 atl1_read_phy_reg(hw, MII_BMSR, &phy_data);
6446a860
JC		 1324 if (!(phy_data & BMSR_LSTATUS)) {
1325 /* link down */
1326 if (netif_carrier_ok(netdev)) {
1327 /* old link state: Up */
1328 if (netif_msg_link(adapter))
1329 dev_info(&adapter->pdev->dev, "link is down\n");
05ffdd7b
JC		 1330 adapter->link_speed = SPEED_0;
1331 netif_carrier_off(netdev);
1332 netif_stop_queue(netdev);
f3cc28c7 1333 }
6446a860 1334 return 0;
f3cc28c7
JC		 1335 }
1336
05ffdd7b
JC		 1337 /* Link Up */
1338 ret_val = atl1_get_speed_and_duplex(hw, &speed, &duplex);
1339 if (ret_val)
1340 return ret_val;
f3cc28c7 1341
05ffdd7b
JC		 1342 switch (hw->media_type) {
1343 case MEDIA_TYPE_1000M_FULL:
1344 if (speed != SPEED_1000 || duplex != FULL_DUPLEX)
1345 reconfig = 1;
1346 break;
1347 case MEDIA_TYPE_100M_FULL:
1348 if (speed != SPEED_100 || duplex != FULL_DUPLEX)
1349 reconfig = 1;
1350 break;
1351 case MEDIA_TYPE_100M_HALF:
1352 if (speed != SPEED_100 || duplex != HALF_DUPLEX)
1353 reconfig = 1;
1354 break;
1355 case MEDIA_TYPE_10M_FULL:
1356 if (speed != SPEED_10 || duplex != FULL_DUPLEX)
1357 reconfig = 1;
1358 break;
1359 case MEDIA_TYPE_10M_HALF:
1360 if (speed != SPEED_10 || duplex != HALF_DUPLEX)
1361 reconfig = 1;
1362 break;
1363 }
f3cc28c7 1364
05ffdd7b
JC		 1365 /* link result is our setting */
1366 if (!reconfig) {
1367 if (adapter->link_speed != speed
1368 || adapter->link_duplex != duplex) {
1369 adapter->link_speed = speed;
1370 adapter->link_duplex = duplex;
1371 atl1_setup_mac_ctrl(adapter);
6446a860
JC		 1372 if (netif_msg_link(adapter))
1373 dev_info(&adapter->pdev->dev,
1374 "%s link is up %d Mbps %s\n",
1375 netdev->name, adapter->link_speed,
1376 adapter->link_duplex == FULL_DUPLEX ?
1377 "full duplex" : "half duplex");
05ffdd7b 1378 }
6446a860
JC		 1379 if (!netif_carrier_ok(netdev)) {
1380 /* Link down -> Up */
05ffdd7b
JC		 1381 netif_carrier_on(netdev);
1382 netif_wake_queue(netdev);
1383 }
6446a860 1384 return 0;
f3cc28c7 1385 }
f3cc28c7 1386
6446a860 1387 /* change original link status */
05ffdd7b
JC		 1388 if (netif_carrier_ok(netdev)) {
1389 adapter->link_speed = SPEED_0;
1390 netif_carrier_off(netdev);
1391 netif_stop_queue(netdev);
f3cc28c7 1392 }
f3cc28c7 1393
05ffdd7b
JC		 1394 if (hw->media_type != MEDIA_TYPE_AUTO_SENSOR &&
1395 hw->media_type != MEDIA_TYPE_1000M_FULL) {
1396 switch (hw->media_type) {
1397 case MEDIA_TYPE_100M_FULL:
1398 phy_data = MII_CR_FULL_DUPLEX | MII_CR_SPEED_100 |
1399 MII_CR_RESET;
1400 break;
1401 case MEDIA_TYPE_100M_HALF:
1402 phy_data = MII_CR_SPEED_100 | MII_CR_RESET;
1403 break;
1404 case MEDIA_TYPE_10M_FULL:
1405 phy_data =
1406 MII_CR_FULL_DUPLEX | MII_CR_SPEED_10 | MII_CR_RESET;
1407 break;
6446a860
JC		 1408 default:
1409 /* MEDIA_TYPE_10M_HALF: */
05ffdd7b
JC		 1410 phy_data = MII_CR_SPEED_10 | MII_CR_RESET;
1411 break;
f3cc28c7 1412 }
05ffdd7b 1413 atl1_write_phy_reg(hw, MII_BMCR, phy_data);
6446a860 1414 return 0;
f3cc28c7 1415 }
f3cc28c7 1416
05ffdd7b
JC		 1417 /* auto-neg, insert timer to re-config phy */
1418 if (!adapter->phy_timer_pending) {
1419 adapter->phy_timer_pending = true;
1420 mod_timer(&adapter->phy_config_timer, jiffies + 3 * HZ);
f3cc28c7 1421 }
f3cc28c7 1422
05ffdd7b
JC		 1423 return 0;
1424}
f3cc28c7 1425
05ffdd7b
JC		 1426static void set_flow_ctrl_old(struct atl1_adapter *adapter)
1427{
1428 u32 hi, lo, value;
f3cc28c7 1429
05ffdd7b
JC		 1430 /* RFD Flow Control */
1431 value = adapter->rfd_ring.count;
1432 hi = value / 16;
1433 if (hi < 2)
1434 hi = 2;
1435 lo = value * 7 / 8;
f3cc28c7 1436
05ffdd7b
JC		 1437 value = ((hi & RXQ_RXF_PAUSE_TH_HI_MASK) << RXQ_RXF_PAUSE_TH_HI_SHIFT) |
1438 ((lo & RXQ_RXF_PAUSE_TH_LO_MASK) << RXQ_RXF_PAUSE_TH_LO_SHIFT);
1439 iowrite32(value, adapter->hw.hw_addr + REG_RXQ_RXF_PAUSE_THRESH);
f3cc28c7 1440
05ffdd7b
JC		 1441 /* RRD Flow Control */
1442 value = adapter->rrd_ring.count;
1443 lo = value / 16;
1444 hi = value * 7 / 8;
1445 if (lo < 2)
1446 lo = 2;
1447 value = ((hi & RXQ_RRD_PAUSE_TH_HI_MASK) << RXQ_RRD_PAUSE_TH_HI_SHIFT) |
1448 ((lo & RXQ_RRD_PAUSE_TH_LO_MASK) << RXQ_RRD_PAUSE_TH_LO_SHIFT);
1449 iowrite32(value, adapter->hw.hw_addr + REG_RXQ_RRD_PAUSE_THRESH);
1450}
f3cc28c7 1451
05ffdd7b
JC		 1452static void set_flow_ctrl_new(struct atl1_hw *hw)
1453{
1454 u32 hi, lo, value;
1455
1456 /* RXF Flow Control */
1457 value = ioread32(hw->hw_addr + REG_SRAM_RXF_LEN);
1458 lo = value / 16;
1459 if (lo < 192)
1460 lo = 192;
1461 hi = value * 7 / 8;
1462 if (hi < lo)
1463 hi = lo + 16;
1464 value = ((hi & RXQ_RXF_PAUSE_TH_HI_MASK) << RXQ_RXF_PAUSE_TH_HI_SHIFT) |
1465 ((lo & RXQ_RXF_PAUSE_TH_LO_MASK) << RXQ_RXF_PAUSE_TH_LO_SHIFT);
1466 iowrite32(value, hw->hw_addr + REG_RXQ_RXF_PAUSE_THRESH);
1467
1468 /* RRD Flow Control */
1469 value = ioread32(hw->hw_addr + REG_SRAM_RRD_LEN);
1470 lo = value / 8;
1471 hi = value * 7 / 8;
1472 if (lo < 2)
1473 lo = 2;
1474 if (hi < lo)
1475 hi = lo + 3;
1476 value = ((hi & RXQ_RRD_PAUSE_TH_HI_MASK) << RXQ_RRD_PAUSE_TH_HI_SHIFT) |
1477 ((lo & RXQ_RRD_PAUSE_TH_LO_MASK) << RXQ_RRD_PAUSE_TH_LO_SHIFT);
1478 iowrite32(value, hw->hw_addr + REG_RXQ_RRD_PAUSE_THRESH);
1479}
1480
1481/*
1482 * atl1_configure - Configure Transmit&Receive Unit after Reset
1483 * @adapter: board private structure
1484 *
1485 * Configure the Tx /Rx unit of the MAC after a reset.
1486 */
1487static u32 atl1_configure(struct atl1_adapter *adapter)
1488{
1489 struct atl1_hw *hw = &adapter->hw;
1490 u32 value;
1491
1492 /* clear interrupt status */
1493 iowrite32(0xffffffff, adapter->hw.hw_addr + REG_ISR);
1494
1495 /* set MAC Address */
1496 value = (((u32) hw->mac_addr[2]) << 24) |
1497 (((u32) hw->mac_addr[3]) << 16) |
1498 (((u32) hw->mac_addr[4]) << 8) |
1499 (((u32) hw->mac_addr[5]));
1500 iowrite32(value, hw->hw_addr + REG_MAC_STA_ADDR);
1501 value = (((u32) hw->mac_addr[0]) << 8) | (((u32) hw->mac_addr[1]));
1502 iowrite32(value, hw->hw_addr + (REG_MAC_STA_ADDR + 4));
1503
1504 /* tx / rx ring */
f3cc28c7 1505
05ffdd7b
JC		 1506 /* HI base address */
1507 iowrite32((u32) ((adapter->tpd_ring.dma & 0xffffffff00000000ULL) >> 32),
1508 hw->hw_addr + REG_DESC_BASE_ADDR_HI);
1509 /* LO base address */
1510 iowrite32((u32) (adapter->rfd_ring.dma & 0x00000000ffffffffULL),
1511 hw->hw_addr + REG_DESC_RFD_ADDR_LO);
1512 iowrite32((u32) (adapter->rrd_ring.dma & 0x00000000ffffffffULL),
1513 hw->hw_addr + REG_DESC_RRD_ADDR_LO);
1514 iowrite32((u32) (adapter->tpd_ring.dma & 0x00000000ffffffffULL),
1515 hw->hw_addr + REG_DESC_TPD_ADDR_LO);
1516 iowrite32((u32) (adapter->cmb.dma & 0x00000000ffffffffULL),
1517 hw->hw_addr + REG_DESC_CMB_ADDR_LO);
1518 iowrite32((u32) (adapter->smb.dma & 0x00000000ffffffffULL),
1519 hw->hw_addr + REG_DESC_SMB_ADDR_LO);
f3cc28c7 1520
05ffdd7b
JC		 1521 /* element count */
1522 value = adapter->rrd_ring.count;
1523 value <<= 16;
1524 value += adapter->rfd_ring.count;
1525 iowrite32(value, hw->hw_addr + REG_DESC_RFD_RRD_RING_SIZE);
1526 iowrite32(adapter->tpd_ring.count, hw->hw_addr +
1527 REG_DESC_TPD_RING_SIZE);
f3cc28c7 1528
05ffdd7b
JC		 1529 /* Load Ptr */
1530 iowrite32(1, hw->hw_addr + REG_LOAD_PTR);
f3cc28c7 1531
05ffdd7b
JC		 1532 /* config Mailbox */
1533 value = ((atomic_read(&adapter->tpd_ring.next_to_use)
1534 & MB_TPD_PROD_INDX_MASK) << MB_TPD_PROD_INDX_SHIFT) |
1535 ((atomic_read(&adapter->rrd_ring.next_to_clean)
1536 & MB_RRD_CONS_INDX_MASK) << MB_RRD_CONS_INDX_SHIFT) |
1537 ((atomic_read(&adapter->rfd_ring.next_to_use)
1538 & MB_RFD_PROD_INDX_MASK) << MB_RFD_PROD_INDX_SHIFT);
1539 iowrite32(value, hw->hw_addr + REG_MAILBOX);
f3cc28c7 1540
05ffdd7b
JC		 1541 /* config IPG/IFG */
1542 value = (((u32) hw->ipgt & MAC_IPG_IFG_IPGT_MASK)
1543 << MAC_IPG_IFG_IPGT_SHIFT) |
1544 (((u32) hw->min_ifg & MAC_IPG_IFG_MIFG_MASK)
1545 << MAC_IPG_IFG_MIFG_SHIFT) |
1546 (((u32) hw->ipgr1 & MAC_IPG_IFG_IPGR1_MASK)
1547 << MAC_IPG_IFG_IPGR1_SHIFT) |
1548 (((u32) hw->ipgr2 & MAC_IPG_IFG_IPGR2_MASK)
1549 << MAC_IPG_IFG_IPGR2_SHIFT);
1550 iowrite32(value, hw->hw_addr + REG_MAC_IPG_IFG);
f3cc28c7 1551
05ffdd7b
JC		 1552 /* config Half-Duplex Control */
1553 value = ((u32) hw->lcol & MAC_HALF_DUPLX_CTRL_LCOL_MASK) |
1554 (((u32) hw->max_retry & MAC_HALF_DUPLX_CTRL_RETRY_MASK)
1555 << MAC_HALF_DUPLX_CTRL_RETRY_SHIFT) |
1556 MAC_HALF_DUPLX_CTRL_EXC_DEF_EN |
1557 (0xa << MAC_HALF_DUPLX_CTRL_ABEBT_SHIFT) |
1558 (((u32) hw->jam_ipg & MAC_HALF_DUPLX_CTRL_JAMIPG_MASK)
1559 << MAC_HALF_DUPLX_CTRL_JAMIPG_SHIFT);
1560 iowrite32(value, hw->hw_addr + REG_MAC_HALF_DUPLX_CTRL);
f3cc28c7 1561
05ffdd7b
JC		 1562 /* set Interrupt Moderator Timer */
1563 iowrite16(adapter->imt, hw->hw_addr + REG_IRQ_MODU_TIMER_INIT);
1564 iowrite32(MASTER_CTRL_ITIMER_EN, hw->hw_addr + REG_MASTER_CTRL);
f3cc28c7 1565
05ffdd7b
JC		 1566 /* set Interrupt Clear Timer */
1567 iowrite16(adapter->ict, hw->hw_addr + REG_CMBDISDMA_TIMER);
f3cc28c7 1568
2a49128f
JC		 1569 /* set max frame size hw will accept */
1570 iowrite32(hw->max_frame_size, hw->hw_addr + REG_MTU);
f3cc28c7 1571
05ffdd7b
JC		 1572 /* jumbo size & rrd retirement timer */
1573 value = (((u32) hw->rx_jumbo_th & RXQ_JMBOSZ_TH_MASK)
1574 << RXQ_JMBOSZ_TH_SHIFT) |
1575 (((u32) hw->rx_jumbo_lkah & RXQ_JMBO_LKAH_MASK)
1576 << RXQ_JMBO_LKAH_SHIFT) |
1577 (((u32) hw->rrd_ret_timer & RXQ_RRD_TIMER_MASK)
1578 << RXQ_RRD_TIMER_SHIFT);
1579 iowrite32(value, hw->hw_addr + REG_RXQ_JMBOSZ_RRDTIM);
f3cc28c7 1580
05ffdd7b
JC		 1581 /* Flow Control */
1582 switch (hw->dev_rev) {
1583 case 0x8001:
1584 case 0x9001:
1585 case 0x9002:
1586 case 0x9003:
1587 set_flow_ctrl_old(adapter);
1588 break;
1589 default:
1590 set_flow_ctrl_new(hw);
1591 break;
f3cc28c7 1592 }
f3cc28c7 1593
05ffdd7b
JC		 1594 /* config TXQ */
1595 value = (((u32) hw->tpd_burst & TXQ_CTRL_TPD_BURST_NUM_MASK)
1596 << TXQ_CTRL_TPD_BURST_NUM_SHIFT) |
1597 (((u32) hw->txf_burst & TXQ_CTRL_TXF_BURST_NUM_MASK)
1598 << TXQ_CTRL_TXF_BURST_NUM_SHIFT) |
1599 (((u32) hw->tpd_fetch_th & TXQ_CTRL_TPD_FETCH_TH_MASK)
1600 << TXQ_CTRL_TPD_FETCH_TH_SHIFT) | TXQ_CTRL_ENH_MODE |
1601 TXQ_CTRL_EN;
1602 iowrite32(value, hw->hw_addr + REG_TXQ_CTRL);
f3cc28c7 1603
05ffdd7b
JC		 1604 /* min tpd fetch gap & tx jumbo packet size threshold for taskoffload */
1605 value = (((u32) hw->tx_jumbo_task_th & TX_JUMBO_TASK_TH_MASK)
1606 << TX_JUMBO_TASK_TH_SHIFT) |
1607 (((u32) hw->tpd_fetch_gap & TX_TPD_MIN_IPG_MASK)
1608 << TX_TPD_MIN_IPG_SHIFT);
1609 iowrite32(value, hw->hw_addr + REG_TX_JUMBO_TASK_TH_TPD_IPG);
f3cc28c7 1610
05ffdd7b
JC		 1611 /* config RXQ */
1612 value = (((u32) hw->rfd_burst & RXQ_CTRL_RFD_BURST_NUM_MASK)
1613 << RXQ_CTRL_RFD_BURST_NUM_SHIFT) |
1614 (((u32) hw->rrd_burst & RXQ_CTRL_RRD_BURST_THRESH_MASK)
1615 << RXQ_CTRL_RRD_BURST_THRESH_SHIFT) |
1616 (((u32) hw->rfd_fetch_gap & RXQ_CTRL_RFD_PREF_MIN_IPG_MASK)
1617 << RXQ_CTRL_RFD_PREF_MIN_IPG_SHIFT) | RXQ_CTRL_CUT_THRU_EN |
1618 RXQ_CTRL_EN;
1619 iowrite32(value, hw->hw_addr + REG_RXQ_CTRL);
f3cc28c7 1620
05ffdd7b
JC		 1621 /* config DMA Engine */
1622 value = ((((u32) hw->dmar_block) & DMA_CTRL_DMAR_BURST_LEN_MASK)
1623 << DMA_CTRL_DMAR_BURST_LEN_SHIFT) |
3f516c00
JC		 1624 ((((u32) hw->dmaw_block) & DMA_CTRL_DMAW_BURST_LEN_MASK)
1625 << DMA_CTRL_DMAW_BURST_LEN_SHIFT) | DMA_CTRL_DMAR_EN |
05ffdd7b
JC		 1626 DMA_CTRL_DMAW_EN;
1627 value |= (u32) hw->dma_ord;
1628 if (atl1_rcb_128 == hw->rcb_value)
1629 value |= DMA_CTRL_RCB_VALUE;
1630 iowrite32(value, hw->hw_addr + REG_DMA_CTRL);
f3cc28c7 1631
05ffdd7b 1632 /* config CMB / SMB */
91a500ac
JC		 1633 value = (hw->cmb_tpd > adapter->tpd_ring.count) ?
1634 hw->cmb_tpd : adapter->tpd_ring.count;
1635 value <<= 16;
1636 value |= hw->cmb_rrd;
05ffdd7b
JC		 1637 iowrite32(value, hw->hw_addr + REG_CMB_WRITE_TH);
1638 value = hw->cmb_rx_timer | ((u32) hw->cmb_tx_timer << 16);
1639 iowrite32(value, hw->hw_addr + REG_CMB_WRITE_TIMER);
1640 iowrite32(hw->smb_timer, hw->hw_addr + REG_SMB_TIMER);
f3cc28c7 1641
05ffdd7b
JC		 1642 /* --- enable CMB / SMB */
1643 value = CSMB_CTRL_CMB_EN | CSMB_CTRL_SMB_EN;
1644 iowrite32(value, hw->hw_addr + REG_CSMB_CTRL);
f3cc28c7 1645
05ffdd7b
JC		 1646 value = ioread32(adapter->hw.hw_addr + REG_ISR);
1647 if (unlikely((value & ISR_PHY_LINKDOWN) != 0))
1648 value = 1; /* config failed */
1649 else
1650 value = 0;
f3cc28c7 1651
05ffdd7b
JC		 1652 /* clear all interrupt status */
1653 iowrite32(0x3fffffff, adapter->hw.hw_addr + REG_ISR);
1654 iowrite32(0, adapter->hw.hw_addr + REG_ISR);
1655 return value;
f3cc28c7 1656}
f3cc28c7 1657
05ffdd7b
JC		 1658/*
1659 * atl1_pcie_patch - Patch for PCIE module
1660 */
1661static void atl1_pcie_patch(struct atl1_adapter *adapter)
f3cc28c7 1662{
05ffdd7b 1663 u32 value;
f3cc28c7 1664
05ffdd7b
JC		 1665 /* much vendor magic here */
1666 value = 0x6500;
1667 iowrite32(value, adapter->hw.hw_addr + 0x12FC);
1668 /* pcie flow control mode change */
1669 value = ioread32(adapter->hw.hw_addr + 0x1008);
1670 value |= 0x8000;
1671 iowrite32(value, adapter->hw.hw_addr + 0x1008);
f3cc28c7 1672}
f3cc28c7 1673
f3cc28c7 1674/*
05ffdd7b
JC		 1675 * When ACPI resume on some VIA MotherBoard, the Interrupt Disable bit/0x400
1676 * on PCI Command register is disable.
1677 * The function enable this bit.
1678 * Brackett, 2006/03/15
f3cc28c7 1679 */
05ffdd7b 1680static void atl1_via_workaround(struct atl1_adapter *adapter)
f3cc28c7 1681{
05ffdd7b 1682 unsigned long value;
f3cc28c7 1683
05ffdd7b
JC		 1684 value = ioread16(adapter->hw.hw_addr + PCI_COMMAND);
1685 if (value & PCI_COMMAND_INTX_DISABLE)
1686 value &= ~PCI_COMMAND_INTX_DISABLE;
1687 iowrite32(value, adapter->hw.hw_addr + PCI_COMMAND);
f3cc28c7
JC		 1688}
1689
05ffdd7b
JC		 1690static void atl1_inc_smb(struct atl1_adapter *adapter)
1691{
1692 struct stats_msg_block *smb = adapter->smb.smb;
f3cc28c7 1693
05ffdd7b
JC		 1694 /* Fill out the OS statistics structure */
1695 adapter->soft_stats.rx_packets += smb->rx_ok;
1696 adapter->soft_stats.tx_packets += smb->tx_ok;
1697 adapter->soft_stats.rx_bytes += smb->rx_byte_cnt;
1698 adapter->soft_stats.tx_bytes += smb->tx_byte_cnt;
1699 adapter->soft_stats.multicast += smb->rx_mcast;
1700 adapter->soft_stats.collisions += (smb->tx_1_col + smb->tx_2_col * 2 +
1701 smb->tx_late_col + smb->tx_abort_col * adapter->hw.max_retry);
f3cc28c7 1702
05ffdd7b
JC		 1703 /* Rx Errors */
1704 adapter->soft_stats.rx_errors += (smb->rx_frag + smb->rx_fcs_err +
1705 smb->rx_len_err + smb->rx_sz_ov + smb->rx_rxf_ov +
1706 smb->rx_rrd_ov + smb->rx_align_err);
1707 adapter->soft_stats.rx_fifo_errors += smb->rx_rxf_ov;
1708 adapter->soft_stats.rx_length_errors += smb->rx_len_err;
1709 adapter->soft_stats.rx_crc_errors += smb->rx_fcs_err;
1710 adapter->soft_stats.rx_frame_errors += smb->rx_align_err;
1711 adapter->soft_stats.rx_missed_errors += (smb->rx_rrd_ov +
1712 smb->rx_rxf_ov);
f3cc28c7 1713
05ffdd7b
JC		 1714 adapter->soft_stats.rx_pause += smb->rx_pause;
1715 adapter->soft_stats.rx_rrd_ov += smb->rx_rrd_ov;
1716 adapter->soft_stats.rx_trunc += smb->rx_sz_ov;
f3cc28c7 1717
05ffdd7b
JC		 1718 /* Tx Errors */
1719 adapter->soft_stats.tx_errors += (smb->tx_late_col +
1720 smb->tx_abort_col + smb->tx_underrun + smb->tx_trunc);
1721 adapter->soft_stats.tx_fifo_errors += smb->tx_underrun;
1722 adapter->soft_stats.tx_aborted_errors += smb->tx_abort_col;
1723 adapter->soft_stats.tx_window_errors += smb->tx_late_col;
f3cc28c7 1724
05ffdd7b
JC		 1725 adapter->soft_stats.excecol += smb->tx_abort_col;
1726 adapter->soft_stats.deffer += smb->tx_defer;
1727 adapter->soft_stats.scc += smb->tx_1_col;
1728 adapter->soft_stats.mcc += smb->tx_2_col;
1729 adapter->soft_stats.latecol += smb->tx_late_col;
1730 adapter->soft_stats.tx_underun += smb->tx_underrun;
1731 adapter->soft_stats.tx_trunc += smb->tx_trunc;
1732 adapter->soft_stats.tx_pause += smb->tx_pause;
f3cc28c7 1733
05ffdd7b
JC		 1734 adapter->net_stats.rx_packets = adapter->soft_stats.rx_packets;
1735 adapter->net_stats.tx_packets = adapter->soft_stats.tx_packets;
1736 adapter->net_stats.rx_bytes = adapter->soft_stats.rx_bytes;
1737 adapter->net_stats.tx_bytes = adapter->soft_stats.tx_bytes;
1738 adapter->net_stats.multicast = adapter->soft_stats.multicast;
1739 adapter->net_stats.collisions = adapter->soft_stats.collisions;
1740 adapter->net_stats.rx_errors = adapter->soft_stats.rx_errors;
1741 adapter->net_stats.rx_over_errors =
1742 adapter->soft_stats.rx_missed_errors;
1743 adapter->net_stats.rx_length_errors =
1744 adapter->soft_stats.rx_length_errors;
1745 adapter->net_stats.rx_crc_errors = adapter->soft_stats.rx_crc_errors;
1746 adapter->net_stats.rx_frame_errors =
1747 adapter->soft_stats.rx_frame_errors;
1748 adapter->net_stats.rx_fifo_errors = adapter->soft_stats.rx_fifo_errors;
1749 adapter->net_stats.rx_missed_errors =
1750 adapter->soft_stats.rx_missed_errors;
1751 adapter->net_stats.tx_errors = adapter->soft_stats.tx_errors;
1752 adapter->net_stats.tx_fifo_errors = adapter->soft_stats.tx_fifo_errors;
1753 adapter->net_stats.tx_aborted_errors =
1754 adapter->soft_stats.tx_aborted_errors;
1755 adapter->net_stats.tx_window_errors =
1756 adapter->soft_stats.tx_window_errors;
1757 adapter->net_stats.tx_carrier_errors =
1758 adapter->soft_stats.tx_carrier_errors;
f3cc28c7
JC		 1759}
1760
05ffdd7b 1761static void atl1_update_mailbox(struct atl1_adapter *adapter)
f3cc28c7 1762{
05ffdd7b
JC		 1763 unsigned long flags;
1764 u32 tpd_next_to_use;
1765 u32 rfd_next_to_use;
1766 u32 rrd_next_to_clean;
f3cc28c7 1767 u32 value;
f3cc28c7 1768
05ffdd7b 1769 spin_lock_irqsave(&adapter->mb_lock, flags);
f3cc28c7 1770
05ffdd7b
JC		 1771 tpd_next_to_use = atomic_read(&adapter->tpd_ring.next_to_use);
1772 rfd_next_to_use = atomic_read(&adapter->rfd_ring.next_to_use);
1773 rrd_next_to_clean = atomic_read(&adapter->rrd_ring.next_to_clean);
f3cc28c7 1774
05ffdd7b
JC		 1775 value = ((rfd_next_to_use & MB_RFD_PROD_INDX_MASK) <<
1776 MB_RFD_PROD_INDX_SHIFT) |
1777 ((rrd_next_to_clean & MB_RRD_CONS_INDX_MASK) <<
1778 MB_RRD_CONS_INDX_SHIFT) |
1779 ((tpd_next_to_use & MB_TPD_PROD_INDX_MASK) <<
1780 MB_TPD_PROD_INDX_SHIFT);
1781 iowrite32(value, adapter->hw.hw_addr + REG_MAILBOX);
f3cc28c7 1782
05ffdd7b 1783 spin_unlock_irqrestore(&adapter->mb_lock, flags);
f3cc28c7
JC		 1784}
1785
05ffdd7b
JC		 1786static void atl1_clean_alloc_flag(struct atl1_adapter *adapter,
1787 struct rx_return_desc *rrd, u16 offset)
f3cc28c7 1788{
05ffdd7b 1789 struct atl1_rfd_ring *rfd_ring = &adapter->rfd_ring;
f3cc28c7 1790
05ffdd7b
JC		 1791 while (rfd_ring->next_to_clean != (rrd->buf_indx + offset)) {
1792 rfd_ring->buffer_info[rfd_ring->next_to_clean].alloced = 0;
1793 if (++rfd_ring->next_to_clean == rfd_ring->count) {
1794 rfd_ring->next_to_clean = 0;
f3cc28c7 1795 }
f3cc28c7 1796 }
05ffdd7b 1797}
f3cc28c7 1798
05ffdd7b
JC		 1799static void atl1_update_rfd_index(struct atl1_adapter *adapter,
1800 struct rx_return_desc *rrd)
1801{
1802 u16 num_buf;
f3cc28c7 1803
05ffdd7b
JC		 1804 num_buf = (rrd->xsz.xsum_sz.pkt_size + adapter->rx_buffer_len - 1) /
1805 adapter->rx_buffer_len;
1806 if (rrd->num_buf == num_buf)
1807 /* clean alloc flag for bad rrd */
1808 atl1_clean_alloc_flag(adapter, rrd, num_buf);
1809}
f3cc28c7 1810
05ffdd7b
JC		 1811static void atl1_rx_checksum(struct atl1_adapter *adapter,
1812 struct rx_return_desc *rrd, struct sk_buff *skb)
1813{
1814 struct pci_dev *pdev = adapter->pdev;
f3cc28c7 1815
05ffdd7b 1816 skb->ip_summed = CHECKSUM_NONE;
f3cc28c7 1817
05ffdd7b
JC		 1818 if (unlikely(rrd->pkt_flg & PACKET_FLAG_ERR)) {
1819 if (rrd->err_flg & (ERR_FLAG_CRC | ERR_FLAG_TRUNC |
1820 ERR_FLAG_CODE | ERR_FLAG_OV)) {
1821 adapter->hw_csum_err++;
6446a860
JC		 1822 if (netif_msg_rx_err(adapter))
1823 dev_printk(KERN_DEBUG, &pdev->dev,
1824 "rx checksum error\n");
05ffdd7b 1825 return;
f3cc28c7 1826 }
f3cc28c7
JC		 1827 }
1828
05ffdd7b
JC		 1829 /* not IPv4 */
1830 if (!(rrd->pkt_flg & PACKET_FLAG_IPV4))
1831 /* checksum is invalid, but it's not an IPv4 pkt, so ok */
1832 return;
1833
1834 /* IPv4 packet */
1835 if (likely(!(rrd->err_flg &
1836 (ERR_FLAG_IP_CHKSUM | ERR_FLAG_L4_CHKSUM)))) {
1837 skb->ip_summed = CHECKSUM_UNNECESSARY;
1838 adapter->hw_csum_good++;
1839 return;
f3cc28c7
JC		 1840 }
1841
05ffdd7b 1842 /* IPv4, but hardware thinks its checksum is wrong */
6446a860
JC		 1843 if (netif_msg_rx_err(adapter))
1844 dev_printk(KERN_DEBUG, &pdev->dev,
1845 "hw csum wrong, pkt_flag:%x, err_flag:%x\n",
1846 rrd->pkt_flg, rrd->err_flg);
05ffdd7b
JC		 1847 skb->ip_summed = CHECKSUM_COMPLETE;
1848 skb->csum = htons(rrd->xsz.xsum_sz.rx_chksum);
1849 adapter->hw_csum_err++;
1850 return;
f3cc28c7
JC		 1851}
1852
05ffdd7b
JC		 1853/*
1854 * atl1_alloc_rx_buffers - Replace used receive buffers
1855 * @adapter: address of board private structure
1856 */
1857static u16 atl1_alloc_rx_buffers(struct atl1_adapter *adapter)
f3cc28c7 1858{
05ffdd7b
JC		 1859 struct atl1_rfd_ring *rfd_ring = &adapter->rfd_ring;
1860 struct pci_dev *pdev = adapter->pdev;
1861 struct page *page;
1862 unsigned long offset;
1863 struct atl1_buffer *buffer_info, *next_info;
1864 struct sk_buff *skb;
1865 u16 num_alloc = 0;
1866 u16 rfd_next_to_use, next_next;
1867 struct rx_free_desc *rfd_desc;
f3cc28c7 1868
05ffdd7b
JC		 1869 next_next = rfd_next_to_use = atomic_read(&rfd_ring->next_to_use);
1870 if (++next_next == rfd_ring->count)
1871 next_next = 0;
1872 buffer_info = &rfd_ring->buffer_info[rfd_next_to_use];
1873 next_info = &rfd_ring->buffer_info[next_next];
f3cc28c7 1874
05ffdd7b
JC		 1875 while (!buffer_info->alloced && !next_info->alloced) {
1876 if (buffer_info->skb) {
1877 buffer_info->alloced = 1;
1878 goto next;
1879 }
f3cc28c7 1880
05ffdd7b 1881 rfd_desc = ATL1_RFD_DESC(rfd_ring, rfd_next_to_use);
f3cc28c7 1882
05ffdd7b 1883 skb = dev_alloc_skb(adapter->rx_buffer_len + NET_IP_ALIGN);
6446a860
JC		 1884 if (unlikely(!skb)) {
1885 /* Better luck next round */
05ffdd7b
JC		 1886 adapter->net_stats.rx_dropped++;
1887 break;
1888 }
f3cc28c7 1889
05ffdd7b
JC		 1890 /*
1891 * Make buffer alignment 2 beyond a 16 byte boundary
1892 * this will result in a 16 byte aligned IP header after
1893 * the 14 byte MAC header is removed
1894 */
1895 skb_reserve(skb, NET_IP_ALIGN);
f3cc28c7 1896
05ffdd7b
JC		 1897 buffer_info->alloced = 1;
1898 buffer_info->skb = skb;
1899 buffer_info->length = (u16) adapter->rx_buffer_len;
1900 page = virt_to_page(skb->data);
1901 offset = (unsigned long)skb->data & ~PAGE_MASK;
1902 buffer_info->dma = pci_map_page(pdev, page, offset,
1903 adapter->rx_buffer_len,
1904 PCI_DMA_FROMDEVICE);
1905 rfd_desc->buffer_addr = cpu_to_le64(buffer_info->dma);
1906 rfd_desc->buf_len = cpu_to_le16(adapter->rx_buffer_len);
1907 rfd_desc->coalese = 0;
f3cc28c7 1908
05ffdd7b
JC		 1909next:
1910 rfd_next_to_use = next_next;
1911 if (unlikely(++next_next == rfd_ring->count))
1912 next_next = 0;
f3cc28c7 1913
05ffdd7b
JC		 1914 buffer_info = &rfd_ring->buffer_info[rfd_next_to_use];
1915 next_info = &rfd_ring->buffer_info[next_next];
1916 num_alloc++;
1917 }
f3cc28c7 1918
05ffdd7b
JC		 1919 if (num_alloc) {
1920 /*
1921 * Force memory writes to complete before letting h/w
1922 * know there are new descriptors to fetch. (Only
1923 * applicable for weak-ordered memory model archs,
1924 * such as IA-64).
1925 */
1926 wmb();
1927 atomic_set(&rfd_ring->next_to_use, (int)rfd_next_to_use);
1928 }
1929 return num_alloc;
f3cc28c7
JC		 1930}
1931
05ffdd7b 1932static void atl1_intr_rx(struct atl1_adapter *adapter)
f3cc28c7 1933{
05ffdd7b
JC		 1934 int i, count;
1935 u16 length;
1936 u16 rrd_next_to_clean;
f3cc28c7 1937 u32 value;
05ffdd7b
JC		 1938 struct atl1_rfd_ring *rfd_ring = &adapter->rfd_ring;
1939 struct atl1_rrd_ring *rrd_ring = &adapter->rrd_ring;
1940 struct atl1_buffer *buffer_info;
1941 struct rx_return_desc *rrd;
1942 struct sk_buff *skb;
f3cc28c7 1943
05ffdd7b 1944 count = 0;
f3cc28c7 1945
05ffdd7b 1946 rrd_next_to_clean = atomic_read(&rrd_ring->next_to_clean);
f3cc28c7 1947
05ffdd7b
JC		 1948 while (1) {
1949 rrd = ATL1_RRD_DESC(rrd_ring, rrd_next_to_clean);
1950 i = 1;
1951 if (likely(rrd->xsz.valid)) { /* packet valid */
1952chk_rrd:
1953 /* check rrd status */
1954 if (likely(rrd->num_buf == 1))
1955 goto rrd_ok;
6446a860
JC		 1956 else if (netif_msg_rx_err(adapter)) {
1957 dev_printk(KERN_DEBUG, &adapter->pdev->dev,
1958 "unexpected RRD buffer count\n");
1959 dev_printk(KERN_DEBUG, &adapter->pdev->dev,
1960 "rx_buf_len = %d\n",
1961 adapter->rx_buffer_len);
1962 dev_printk(KERN_DEBUG, &adapter->pdev->dev,
1963 "RRD num_buf = %d\n",
1964 rrd->num_buf);
1965 dev_printk(KERN_DEBUG, &adapter->pdev->dev,
1966 "RRD pkt_len = %d\n",
1967 rrd->xsz.xsum_sz.pkt_size);
1968 dev_printk(KERN_DEBUG, &adapter->pdev->dev,
1969 "RRD pkt_flg = 0x%08X\n",
1970 rrd->pkt_flg);
1971 dev_printk(KERN_DEBUG, &adapter->pdev->dev,
1972 "RRD err_flg = 0x%08X\n",
1973 rrd->err_flg);
1974 dev_printk(KERN_DEBUG, &adapter->pdev->dev,
1975 "RRD vlan_tag = 0x%08X\n",
1976 rrd->vlan_tag);
1977 }
f3cc28c7 1978
05ffdd7b
JC		 1979 /* rrd seems to be bad */
1980 if (unlikely(i-- > 0)) {
1981 /* rrd may not be DMAed completely */
05ffdd7b
JC		 1982 udelay(1);
1983 goto chk_rrd;
1984 }
1985 /* bad rrd */
6446a860
JC		 1986 if (netif_msg_rx_err(adapter))
1987 dev_printk(KERN_DEBUG, &adapter->pdev->dev,
1988 "bad RRD\n");
05ffdd7b
JC		 1989 /* see if update RFD index */
1990 if (rrd->num_buf > 1)
1991 atl1_update_rfd_index(adapter, rrd);
f3cc28c7 1992
05ffdd7b
JC		 1993 /* update rrd */
1994 rrd->xsz.valid = 0;
1995 if (++rrd_next_to_clean == rrd_ring->count)
1996 rrd_next_to_clean = 0;
1997 count++;
1998 continue;
1999 } else { /* current rrd still not be updated */
f3cc28c7 2000
05ffdd7b
JC		 2001 break;
2002 }
2003rrd_ok:
2004 /* clean alloc flag for bad rrd */
2005 atl1_clean_alloc_flag(adapter, rrd, 0);
f3cc28c7 2006
05ffdd7b
JC		 2007 buffer_info = &rfd_ring->buffer_info[rrd->buf_indx];
2008 if (++rfd_ring->next_to_clean == rfd_ring->count)
2009 rfd_ring->next_to_clean = 0;
f3cc28c7 2010
05ffdd7b
JC		 2011 /* update rrd next to clean */
2012 if (++rrd_next_to_clean == rrd_ring->count)
2013 rrd_next_to_clean = 0;
2014 count++;
f3cc28c7 2015
05ffdd7b
JC		 2016 if (unlikely(rrd->pkt_flg & PACKET_FLAG_ERR)) {
2017 if (!(rrd->err_flg &
2018 (ERR_FLAG_IP_CHKSUM | ERR_FLAG_L4_CHKSUM
2019 | ERR_FLAG_LEN))) {
2020 /* packet error, don't need upstream */
2021 buffer_info->alloced = 0;
2022 rrd->xsz.valid = 0;
2023 continue;
2024 }
2025 }
f3cc28c7 2026
05ffdd7b
JC		 2027 /* Good Receive */
2028 pci_unmap_page(adapter->pdev, buffer_info->dma,
2029 buffer_info->length, PCI_DMA_FROMDEVICE);
2030 skb = buffer_info->skb;
2031 length = le16_to_cpu(rrd->xsz.xsum_sz.pkt_size);
f3cc28c7 2032
a3093d9b 2033 skb_put(skb, length - ETH_FCS_LEN);
f3cc28c7 2034
05ffdd7b
JC		 2035 /* Receive Checksum Offload */
2036 atl1_rx_checksum(adapter, rrd, skb);
2037 skb->protocol = eth_type_trans(skb, adapter->netdev);
f3cc28c7 2038
05ffdd7b
JC		 2039 if (adapter->vlgrp && (rrd->pkt_flg & PACKET_FLAG_VLAN_INS)) {
2040 u16 vlan_tag = (rrd->vlan_tag >> 4) |
2041 ((rrd->vlan_tag & 7) << 13) |
2042 ((rrd->vlan_tag & 8) << 9);
2043 vlan_hwaccel_rx(skb, adapter->vlgrp, vlan_tag);
2044 } else
2045 netif_rx(skb);
f3cc28c7 2046
05ffdd7b
JC		 2047 /* let protocol layer free skb */
2048 buffer_info->skb = NULL;
2049 buffer_info->alloced = 0;
2050 rrd->xsz.valid = 0;
f3cc28c7 2051
05ffdd7b
JC		 2052 adapter->netdev->last_rx = jiffies;
2053 }
f3cc28c7 2054
05ffdd7b 2055 atomic_set(&rrd_ring->next_to_clean, rrd_next_to_clean);
f3cc28c7 2056
05ffdd7b 2057 atl1_alloc_rx_buffers(adapter);
f3cc28c7 2058
05ffdd7b
JC		 2059 /* update mailbox ? */
2060 if (count) {
2061 u32 tpd_next_to_use;
2062 u32 rfd_next_to_use;
f3cc28c7 2063
05ffdd7b 2064 spin_lock(&adapter->mb_lock);
f3cc28c7 2065
05ffdd7b
JC		 2066 tpd_next_to_use = atomic_read(&adapter->tpd_ring.next_to_use);
2067 rfd_next_to_use =
2068 atomic_read(&adapter->rfd_ring.next_to_use);
2069 rrd_next_to_clean =
2070 atomic_read(&adapter->rrd_ring.next_to_clean);
2071 value = ((rfd_next_to_use & MB_RFD_PROD_INDX_MASK) <<
2072 MB_RFD_PROD_INDX_SHIFT) |
2073 ((rrd_next_to_clean & MB_RRD_CONS_INDX_MASK) <<
2074 MB_RRD_CONS_INDX_SHIFT) |
2075 ((tpd_next_to_use & MB_TPD_PROD_INDX_MASK) <<
2076 MB_TPD_PROD_INDX_SHIFT);
2077 iowrite32(value, adapter->hw.hw_addr + REG_MAILBOX);
2078 spin_unlock(&adapter->mb_lock);
2079 }
f3cc28c7
JC		 2080}
2081
05ffdd7b 2082static void atl1_intr_tx(struct atl1_adapter *adapter)
f3cc28c7 2083{
05ffdd7b
JC		 2084 struct atl1_tpd_ring *tpd_ring = &adapter->tpd_ring;
2085 struct atl1_buffer *buffer_info;
2086 u16 sw_tpd_next_to_clean;
2087 u16 cmb_tpd_next_to_clean;
f3cc28c7 2088
05ffdd7b
JC		 2089 sw_tpd_next_to_clean = atomic_read(&tpd_ring->next_to_clean);
2090 cmb_tpd_next_to_clean = le16_to_cpu(adapter->cmb.cmb->tpd_cons_idx);
f3cc28c7 2091
05ffdd7b
JC		 2092 while (cmb_tpd_next_to_clean != sw_tpd_next_to_clean) {
2093 struct tx_packet_desc *tpd;
f3cc28c7 2094
05ffdd7b
JC		 2095 tpd = ATL1_TPD_DESC(tpd_ring, sw_tpd_next_to_clean);
2096 buffer_info = &tpd_ring->buffer_info[sw_tpd_next_to_clean];
2097 if (buffer_info->dma) {
2098 pci_unmap_page(adapter->pdev, buffer_info->dma,
2099 buffer_info->length, PCI_DMA_TODEVICE);
2100 buffer_info->dma = 0;
2101 }
f3cc28c7 2102
05ffdd7b
JC		 2103 if (buffer_info->skb) {
2104 dev_kfree_skb_irq(buffer_info->skb);
2105 buffer_info->skb = NULL;
2106 }
f3cc28c7 2107
05ffdd7b
JC		 2108 if (++sw_tpd_next_to_clean == tpd_ring->count)
2109 sw_tpd_next_to_clean = 0;
2110 }
2111 atomic_set(&tpd_ring->next_to_clean, sw_tpd_next_to_clean);
2112
2113 if (netif_queue_stopped(adapter->netdev)
2114 && netif_carrier_ok(adapter->netdev))
2115 netif_wake_queue(adapter->netdev);
f3cc28c7
JC		 2116}
2117
e6a7ff4a 2118static u16 atl1_tpd_avail(struct atl1_tpd_ring *tpd_ring)
f3cc28c7
JC		 2119{
2120 u16 next_to_clean = atomic_read(&tpd_ring->next_to_clean);
2121 u16 next_to_use = atomic_read(&tpd_ring->next_to_use);
53ffb42c
JC		 2122 return ((next_to_clean > next_to_use) ?
2123 next_to_clean - next_to_use - 1 :
2124 tpd_ring->count + next_to_clean - next_to_use - 1);
f3cc28c7
JC		 2125}
2126
2127static int atl1_tso(struct atl1_adapter *adapter, struct sk_buff *skb,
6446a860 2128 struct tx_packet_desc *ptpd)
f3cc28c7 2129{
6446a860
JC		 2130 /* spinlock held */
2131 u8 hdr_len, ip_off;
2132 u32 real_len;
f3cc28c7
JC		 2133 int err;
2134
2135 if (skb_shinfo(skb)->gso_size) {
2136 if (skb_header_cloned(skb)) {
2137 err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
2138 if (unlikely(err))
6446a860 2139 return -1;
f3cc28c7
JC		 2140 }
2141
2142 if (skb->protocol == ntohs(ETH_P_IP)) {
eddc9ec5
ACM		 2143 struct iphdr *iph = ip_hdr(skb);
2144
6446a860
JC		 2145 real_len = (((unsigned char *)iph - skb->data) +
2146 ntohs(iph->tot_len));
2147 if (real_len < skb->len)
2148 pskb_trim(skb, real_len);
2149 hdr_len = (skb_transport_offset(skb) + tcp_hdrlen(skb));
2150 if (skb->len == hdr_len) {
2151 iph->check = 0;
2152 tcp_hdr(skb)->check =
2153 ~csum_tcpudp_magic(iph->saddr,
2154 iph->daddr, tcp_hdrlen(skb),
2155 IPPROTO_TCP, 0);
2156 ptpd->word3 |= (iph->ihl & TPD_IPHL_MASK) <<
2157 TPD_IPHL_SHIFT;
2158 ptpd->word3 |= ((tcp_hdrlen(skb) >> 2) &
2159 TPD_TCPHDRLEN_MASK) <<
2160 TPD_TCPHDRLEN_SHIFT;
2161 ptpd->word3 |= 1 << TPD_IP_CSUM_SHIFT;
2162 ptpd->word3 |= 1 << TPD_TCP_CSUM_SHIFT;
2163 return 1;
2164 }
2165
eddc9ec5 2166 iph->check = 0;
aa8223c7 2167 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
6446a860
JC		 2168 iph->daddr, 0, IPPROTO_TCP, 0);
2169 ip_off = (unsigned char *)iph -
2170 (unsigned char *) skb_network_header(skb);
2171 if (ip_off == 8) /* 802.3-SNAP frame */
2172 ptpd->word3 |= 1 << TPD_ETHTYPE_SHIFT;
2173 else if (ip_off != 0)
2174 return -2;
2175
2176 ptpd->word3 |= (iph->ihl & TPD_IPHL_MASK) <<
2177 TPD_IPHL_SHIFT;
2178 ptpd->word3 |= ((tcp_hdrlen(skb) >> 2) &
2179 TPD_TCPHDRLEN_MASK) << TPD_TCPHDRLEN_SHIFT;
2180 ptpd->word3 |= (skb_shinfo(skb)->gso_size &
2181 TPD_MSS_MASK) << TPD_MSS_SHIFT;
2182 ptpd->word3 |= 1 << TPD_SEGMENT_EN_SHIFT;
2183 return 3;
f3cc28c7
JC		 2184 }
2185 }
2186 return false;
2187}
2188
2189static int atl1_tx_csum(struct atl1_adapter *adapter, struct sk_buff *skb,
6446a860 2190 struct tx_packet_desc *ptpd)
f3cc28c7
JC		 2191{
2192 u8 css, cso;
2193
2194 if (likely(skb->ip_summed == CHECKSUM_PARTIAL)) {
6446a860
JC		 2195 css = (u8) (skb->csum_start - skb_headroom(skb));
2196 cso = css + (u8) skb->csum_offset;
2197 if (unlikely(css & 0x1)) {
2198 /* L1 hardware requires an even number here */
2199 if (netif_msg_tx_err(adapter))
2200 dev_printk(KERN_DEBUG, &adapter->pdev->dev,
2201 "payload offset not an even number\n");
f3cc28c7
JC		 2202 return -1;
2203 }
6446a860
JC		 2204 ptpd->word3 |= (css & TPD_PLOADOFFSET_MASK) <<
2205 TPD_PLOADOFFSET_SHIFT;
2206 ptpd->word3 |= (cso & TPD_CCSUMOFFSET_MASK) <<
2207 TPD_CCSUMOFFSET_SHIFT;
2208 ptpd->word3 |= 1 << TPD_CUST_CSUM_EN_SHIFT;
f3cc28c7
JC		 2209 return true;
2210 }
6446a860 2211 return 0;
f3cc28c7
JC		 2212}
2213
53ffb42c 2214static void atl1_tx_map(struct atl1_adapter *adapter, struct sk_buff *skb,
6446a860 2215 struct tx_packet_desc *ptpd)
f3cc28c7 2216{
6446a860 2217 /* spinlock held */
f3cc28c7
JC		 2218 struct atl1_tpd_ring *tpd_ring = &adapter->tpd_ring;
2219 struct atl1_buffer *buffer_info;
6446a860 2220 u16 buf_len = skb->len;
f3cc28c7 2221 struct page *page;
f3cc28c7
JC		 2222 unsigned long offset;
2223 unsigned int nr_frags;
2224 unsigned int f;
6446a860
JC		 2225 int retval;
2226 u16 next_to_use;
2227 u16 data_len;
2228 u8 hdr_len;
f3cc28c7 2229
6446a860 2230 buf_len -= skb->data_len;
f3cc28c7 2231 nr_frags = skb_shinfo(skb)->nr_frags;
6446a860
JC		 2232 next_to_use = atomic_read(&tpd_ring->next_to_use);
2233 buffer_info = &tpd_ring->buffer_info[next_to_use];
f3cc28c7
JC		 2234 if (unlikely(buffer_info->skb))
2235 BUG();
6446a860
JC		 2236 /* put skb in last TPD */
2237 buffer_info->skb = NULL;
f3cc28c7 2238
6446a860
JC		 2239 retval = (ptpd->word3 >> TPD_SEGMENT_EN_SHIFT) & TPD_SEGMENT_EN_MASK;
2240 if (retval) {
2241 /* TSO */
2242 hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
2243 buffer_info->length = hdr_len;
f3cc28c7
JC		 2244 page = virt_to_page(skb->data);
2245 offset = (unsigned long)skb->data & ~PAGE_MASK;
2246 buffer_info->dma = pci_map_page(adapter->pdev, page,
6446a860 2247 offset, hdr_len,
f3cc28c7
JC		 2248 PCI_DMA_TODEVICE);
2249
6446a860
JC		 2250 if (++next_to_use == tpd_ring->count)
2251 next_to_use = 0;
f3cc28c7 2252
6446a860
JC		 2253 if (buf_len > hdr_len) {
2254 int i, nseg;
ddfce6bb 2255
6446a860
JC		 2256 data_len = buf_len - hdr_len;
2257 nseg = (data_len + ATL1_MAX_TX_BUF_LEN - 1) /
53ffb42c 2258 ATL1_MAX_TX_BUF_LEN;
6446a860 2259 for (i = 0; i < nseg; i++) {
f3cc28c7 2260 buffer_info =
6446a860 2261 &tpd_ring->buffer_info[next_to_use];
f3cc28c7
JC		 2262 buffer_info->skb = NULL;
2263 buffer_info->length =
2b116145 2264 (ATL1_MAX_TX_BUF_LEN >=
6446a860
JC		 2265 data_len) ? ATL1_MAX_TX_BUF_LEN : data_len;
2266 data_len -= buffer_info->length;
f3cc28c7 2267 page = virt_to_page(skb->data +
6446a860 2268 (hdr_len + i * ATL1_MAX_TX_BUF_LEN));
f3cc28c7 2269 offset = (unsigned long)(skb->data +
6446a860
JC		 2270 (hdr_len + i * ATL1_MAX_TX_BUF_LEN)) &
2271 ~PAGE_MASK;
53ffb42c
JC		 2272 buffer_info->dma = pci_map_page(adapter->pdev,
2273 page, offset, buffer_info->length,
2274 PCI_DMA_TODEVICE);
6446a860
JC		 2275 if (++next_to_use == tpd_ring->count)
2276 next_to_use = 0;
f3cc28c7
JC		 2277 }
2278 }
2279 } else {
6446a860
JC		 2280 /* not TSO */
2281 buffer_info->length = buf_len;
f3cc28c7
JC		 2282 page = virt_to_page(skb->data);
2283 offset = (unsigned long)skb->data & ~PAGE_MASK;
2284 buffer_info->dma = pci_map_page(adapter->pdev, page,
6446a860
JC		 2285 offset, buf_len, PCI_DMA_TODEVICE);
2286 if (++next_to_use == tpd_ring->count)
2287 next_to_use = 0;
f3cc28c7
JC		 2288 }
2289
2290 for (f = 0; f < nr_frags; f++) {
2291 struct skb_frag_struct *frag;
6446a860 2292 u16 i, nseg;
f3cc28c7
JC		 2293
2294 frag = &skb_shinfo(skb)->frags[f];
6446a860 2295 buf_len = frag->size;
f3cc28c7 2296
6446a860
JC		 2297 nseg = (buf_len + ATL1_MAX_TX_BUF_LEN - 1) /
2298 ATL1_MAX_TX_BUF_LEN;
2299 for (i = 0; i < nseg; i++) {
2300 buffer_info = &tpd_ring->buffer_info[next_to_use];
f3cc28c7
JC		 2301 if (unlikely(buffer_info->skb))
2302 BUG();
2303 buffer_info->skb = NULL;
6446a860
JC		 2304 buffer_info->length = (buf_len > ATL1_MAX_TX_BUF_LEN) ?
2305 ATL1_MAX_TX_BUF_LEN : buf_len;
2306 buf_len -= buffer_info->length;
53ffb42c
JC		 2307 buffer_info->dma = pci_map_page(adapter->pdev,
2308 frag->page,
2309 frag->page_offset + (i * ATL1_MAX_TX_BUF_LEN),
2310 buffer_info->length, PCI_DMA_TODEVICE);
f3cc28c7 2311
6446a860
JC		 2312 if (++next_to_use == tpd_ring->count)
2313 next_to_use = 0;
f3cc28c7
JC		 2314 }
2315 }
2316
2317 /* last tpd's buffer-info */
2318 buffer_info->skb = skb;
2319}
2320
6446a860
JC		 2321static void atl1_tx_queue(struct atl1_adapter *adapter, u16 count,
2322 struct tx_packet_desc *ptpd)
f3cc28c7 2323{
6446a860 2324 /* spinlock held */
f3cc28c7 2325 struct atl1_tpd_ring *tpd_ring = &adapter->tpd_ring;
f3cc28c7
JC		 2326 struct atl1_buffer *buffer_info;
2327 struct tx_packet_desc *tpd;
6446a860
JC		 2328 u16 j;
2329 u32 val;
2330 u16 next_to_use = (u16) atomic_read(&tpd_ring->next_to_use);
f3cc28c7
JC		 2331
2332 for (j = 0; j < count; j++) {
6446a860
JC		 2333 buffer_info = &tpd_ring->buffer_info[next_to_use];
2334 tpd = ATL1_TPD_DESC(&adapter->tpd_ring, next_to_use);
2335 if (tpd != ptpd)
2336 memcpy(tpd, ptpd, sizeof(struct tx_packet_desc));
f3cc28c7 2337 tpd->buffer_addr = cpu_to_le64(buffer_info->dma);
6446a860
JC		 2338 tpd->word2 = (cpu_to_le16(buffer_info->length) &
2339 TPD_BUFLEN_MASK) << TPD_BUFLEN_SHIFT;
f3cc28c7 2340
6446a860
JC		 2341 /*
2342 * if this is the first packet in a TSO chain, set
2343 * TPD_HDRFLAG, otherwise, clear it.
2344 */
2345 val = (tpd->word3 >> TPD_SEGMENT_EN_SHIFT) &
2346 TPD_SEGMENT_EN_MASK;
2347 if (val) {
2348 if (!j)
2349 tpd->word3 |= 1 << TPD_HDRFLAG_SHIFT;
2350 else
2351 tpd->word3 &= ~(1 << TPD_HDRFLAG_SHIFT);
2352 }
f3cc28c7
JC		 2353
2354 if (j == (count - 1))
6446a860 2355 tpd->word3 |= 1 << TPD_EOP_SHIFT;
f3cc28c7 2356
6446a860
JC		 2357 if (++next_to_use == tpd_ring->count)
2358 next_to_use = 0;
f3cc28c7
JC		 2359 }
2360 /*
2361 * Force memory writes to complete before letting h/w
2362 * know there are new descriptors to fetch. (Only
2363 * applicable for weak-ordered memory model archs,
2364 * such as IA-64).
2365 */
2366 wmb();
2367
6446a860 2368 atomic_set(&tpd_ring->next_to_use, next_to_use);
f3cc28c7
JC		 2369}
2370
f3cc28c7
JC		 2371static int atl1_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
2372{
2373 struct atl1_adapter *adapter = netdev_priv(netdev);
6446a860 2374 struct atl1_tpd_ring *tpd_ring = &adapter->tpd_ring;
f3cc28c7
JC		 2375 int len = skb->len;
2376 int tso;
2377 int count = 1;
2378 int ret_val;
6446a860 2379 struct tx_packet_desc *ptpd;
f3cc28c7
JC		 2380 u16 frag_size;
2381 u16 vlan_tag;
2382 unsigned long flags;
2383 unsigned int nr_frags = 0;
2384 unsigned int mss = 0;
2385 unsigned int f;
2386 unsigned int proto_hdr_len;
2387
2388 len -= skb->data_len;
2389
6446a860 2390 if (unlikely(skb->len <= 0)) {
f3cc28c7
JC		 2391 dev_kfree_skb_any(skb);
2392 return NETDEV_TX_OK;
2393 }
2394
f3cc28c7
JC		 2395 nr_frags = skb_shinfo(skb)->nr_frags;
2396 for (f = 0; f < nr_frags; f++) {
2397 frag_size = skb_shinfo(skb)->frags[f].size;
2398 if (frag_size)
53ffb42c
JC		 2399 count += (frag_size + ATL1_MAX_TX_BUF_LEN - 1) /
2400 ATL1_MAX_TX_BUF_LEN;
f3cc28c7
JC		 2401 }
2402
f3cc28c7
JC		 2403 mss = skb_shinfo(skb)->gso_size;
2404 if (mss) {
6446a860 2405 if (skb->protocol == ntohs(ETH_P_IP)) {
ea2ae17d 2406 proto_hdr_len = (skb_transport_offset(skb) +
ab6a5bb6 2407 tcp_hdrlen(skb));
f3cc28c7
JC		 2408 if (unlikely(proto_hdr_len > len)) {
2409 dev_kfree_skb_any(skb);
2410 return NETDEV_TX_OK;
2411 }
2412 /* need additional TPD ? */
2413 if (proto_hdr_len != len)
2414 count += (len - proto_hdr_len +
53ffb42c
JC		 2415 ATL1_MAX_TX_BUF_LEN - 1) /
2416 ATL1_MAX_TX_BUF_LEN;
f3cc28c7
JC		 2417 }
2418 }
2419
5845b677 2420 if (!spin_trylock_irqsave(&adapter->lock, flags)) {
f3cc28c7 2421 /* Can't get lock - tell upper layer to requeue */
6446a860
JC		 2422 if (netif_msg_tx_queued(adapter))
2423 dev_printk(KERN_DEBUG, &adapter->pdev->dev,
2424 "tx locked\n");
f3cc28c7
JC		 2425 return NETDEV_TX_LOCKED;
2426 }
2427
e6a7ff4a 2428 if (atl1_tpd_avail(&adapter->tpd_ring) < count) {
f3cc28c7
JC		 2429 /* not enough descriptors */
2430 netif_stop_queue(netdev);
2431 spin_unlock_irqrestore(&adapter->lock, flags);
6446a860
JC		 2432 if (netif_msg_tx_queued(adapter))
2433 dev_printk(KERN_DEBUG, &adapter->pdev->dev,
2434 "tx busy\n");
f3cc28c7
JC		 2435 return NETDEV_TX_BUSY;
2436 }
2437
6446a860
JC		 2438 ptpd = ATL1_TPD_DESC(tpd_ring,
2439 (u16) atomic_read(&tpd_ring->next_to_use));
2440 memset(ptpd, 0, sizeof(struct tx_packet_desc));
f3cc28c7
JC		 2441
2442 if (adapter->vlgrp && vlan_tx_tag_present(skb)) {
2443 vlan_tag = vlan_tx_tag_get(skb);
2444 vlan_tag = (vlan_tag << 4) | (vlan_tag >> 13) |
2445 ((vlan_tag >> 9) & 0x8);
6446a860
JC		 2446 ptpd->word3 |= 1 << TPD_INS_VL_TAG_SHIFT;
2447 ptpd->word3 |= (vlan_tag & TPD_VL_TAGGED_MASK) <<
2448 TPD_VL_TAGGED_SHIFT;
f3cc28c7
JC		 2449 }
2450
6446a860 2451 tso = atl1_tso(adapter, skb, ptpd);
f3cc28c7
JC		 2452 if (tso < 0) {
2453 spin_unlock_irqrestore(&adapter->lock, flags);
2454 dev_kfree_skb_any(skb);
2455 return NETDEV_TX_OK;
2456 }
2457
2458 if (!tso) {
6446a860 2459 ret_val = atl1_tx_csum(adapter, skb, ptpd);
f3cc28c7
JC		 2460 if (ret_val < 0) {
2461 spin_unlock_irqrestore(&adapter->lock, flags);
2462 dev_kfree_skb_any(skb);
2463 return NETDEV_TX_OK;
2464 }
2465 }
2466
6446a860
JC		 2467 atl1_tx_map(adapter, skb, ptpd);
2468 atl1_tx_queue(adapter, count, ptpd);
f3cc28c7 2469 atl1_update_mailbox(adapter);
6446a860
JC		 2470 spin_unlock_irqrestore(&adapter->lock, flags);
2471 netdev->trans_start = jiffies;
f3cc28c7
JC		 2472 return NETDEV_TX_OK;
2473}
2474
2475/*
05ffdd7b
JC		 2476 * atl1_intr - Interrupt Handler
2477 * @irq: interrupt number
2478 * @data: pointer to a network interface device structure
2479 * @pt_regs: CPU registers structure
f3cc28c7 2480 */
05ffdd7b 2481static irqreturn_t atl1_intr(int irq, void *data)
f3cc28c7 2482{
05ffdd7b
JC		 2483 struct atl1_adapter *adapter = netdev_priv(data);
2484 u32 status;
05ffdd7b 2485 int max_ints = 10;
f3cc28c7 2486
05ffdd7b
JC		 2487 status = adapter->cmb.cmb->int_stats;
2488 if (!status)
2489 return IRQ_NONE;
f3cc28c7 2490
05ffdd7b
JC		 2491 do {
2492 /* clear CMB interrupt status at once */
2493 adapter->cmb.cmb->int_stats = 0;
2494
2495 if (status & ISR_GPHY) /* clear phy status */
6446a860 2496 atlx_clear_phy_int(adapter);
05ffdd7b
JC		 2497
2498 /* clear ISR status, and Enable CMB DMA/Disable Interrupt */
2499 iowrite32(status | ISR_DIS_INT, adapter->hw.hw_addr + REG_ISR);
2500
2501 /* check if SMB intr */
2502 if (status & ISR_SMB)
2503 atl1_inc_smb(adapter);
2504
2505 /* check if PCIE PHY Link down */
2506 if (status & ISR_PHY_LINKDOWN) {
6446a860
JC		 2507 if (netif_msg_intr(adapter))
2508 dev_printk(KERN_DEBUG, &adapter->pdev->dev,
2509 "pcie phy link down %x\n", status);
05ffdd7b
JC		 2510 if (netif_running(adapter->netdev)) { /* reset MAC */
2511 iowrite32(0, adapter->hw.hw_addr + REG_IMR);
2512 schedule_work(&adapter->pcie_dma_to_rst_task);
2513 return IRQ_HANDLED;
2514 }
f3cc28c7 2515 }
05ffdd7b
JC		 2516
2517 /* check if DMA read/write error ? */
2518 if (status & (ISR_DMAR_TO_RST | ISR_DMAW_TO_RST)) {
6446a860
JC		 2519 if (netif_msg_intr(adapter))
2520 dev_printk(KERN_DEBUG, &adapter->pdev->dev,
2521 "pcie DMA r/w error (status = 0x%x)\n",
2522 status);
05ffdd7b
JC		 2523 iowrite32(0, adapter->hw.hw_addr + REG_IMR);
2524 schedule_work(&adapter->pcie_dma_to_rst_task);
2525 return IRQ_HANDLED;
f3cc28c7 2526 }
f3cc28c7 2527
05ffdd7b
JC		 2528 /* link event */
2529 if (status & ISR_GPHY) {
2530 adapter->soft_stats.tx_carrier_errors++;
2531 atl1_check_for_link(adapter);
2532 }
f3cc28c7 2533
05ffdd7b
JC		 2534 /* transmit event */
2535 if (status & ISR_CMB_TX)
2536 atl1_intr_tx(adapter);
f3cc28c7 2537
05ffdd7b
JC		 2538 /* rx exception */
2539 if (unlikely(status & (ISR_RXF_OV | ISR_RFD_UNRUN |
2540 ISR_RRD_OV | ISR_HOST_RFD_UNRUN |
2541 ISR_HOST_RRD_OV | ISR_CMB_RX))) {
2542 if (status & (ISR_RXF_OV | ISR_RFD_UNRUN |
2543 ISR_RRD_OV | ISR_HOST_RFD_UNRUN |
2544 ISR_HOST_RRD_OV))
6446a860
JC		 2545 if (netif_msg_intr(adapter))
2546 dev_printk(KERN_DEBUG,
2547 &adapter->pdev->dev,
2548 "rx exception, ISR = 0x%x\n",
2549 status);
05ffdd7b
JC		 2550 atl1_intr_rx(adapter);
2551 }
f3cc28c7 2552
05ffdd7b
JC		 2553 if (--max_ints < 0)
2554 break;
2555
2556 } while ((status = adapter->cmb.cmb->int_stats));
2557
2558 /* re-enable Interrupt */
2559 iowrite32(ISR_DIS_SMB | ISR_DIS_DMA, adapter->hw.hw_addr + REG_ISR);
2560 return IRQ_HANDLED;
f3cc28c7
JC		 2561}
2562
2563/*
05ffdd7b
JC		 2564 * atl1_watchdog - Timer Call-back
2565 * @data: pointer to netdev cast into an unsigned long
f3cc28c7 2566 */
05ffdd7b 2567static void atl1_watchdog(unsigned long data)
f3cc28c7 2568{
05ffdd7b 2569 struct atl1_adapter *adapter = (struct atl1_adapter *)data;
f3cc28c7 2570
05ffdd7b
JC		 2571 /* Reset the timer */
2572 mod_timer(&adapter->watchdog_timer, jiffies + 2 * HZ);
2573}
f3cc28c7 2574
05ffdd7b
JC		 2575/*
2576 * atl1_phy_config - Timer Call-back
2577 * @data: pointer to netdev cast into an unsigned long
2578 */
2579static void atl1_phy_config(unsigned long data)
2580{
6446a860
JC		 2581 struct atl1_adapter *adapter = (struct atl1_adapter *)data;
2582 struct atl1_hw *hw = &adapter->hw;
05ffdd7b 2583 unsigned long flags;
f3cc28c7 2584
05ffdd7b 2585 spin_lock_irqsave(&adapter->lock, flags);
6446a860
JC		 2586 adapter->phy_timer_pending = false;
2587 atl1_write_phy_reg(hw, MII_ADVERTISE, hw->mii_autoneg_adv_reg);
2588 atl1_write_phy_reg(hw, MII_ATLX_CR, hw->mii_1000t_ctrl_reg);
2589 atl1_write_phy_reg(hw, MII_BMCR, MII_CR_RESET | MII_CR_AUTO_NEG_EN);
05ffdd7b
JC		 2590 spin_unlock_irqrestore(&adapter->lock, flags);
2591}
2592
6446a860
JC		 2593/*
2594 * Orphaned vendor comment left intact here:
2595 * <vendor comment>
2596 * If TPD Buffer size equal to 0, PCIE DMAR_TO_INT
2597 * will assert. We do soft reset <0x1400=1> according
2598 * with the SPEC. BUT, it seemes that PCIE or DMA
2599 * state-machine will not be reset. DMAR_TO_INT will
2600 * assert again and again.
2601 * </vendor comment>
2602 */
05ffdd7b 2603
6446a860 2604static int atl1_reset(struct atl1_adapter *adapter)
05ffdd7b
JC		 2605{
2606 int ret;
05ffdd7b 2607 ret = atl1_reset_hw(&adapter->hw);
6446a860 2608 if (ret)
05ffdd7b
JC		 2609 return ret;
2610 return atl1_init_hw(&adapter->hw);
f3cc28c7
JC		 2611}
2612
6446a860 2613static s32 atl1_up(struct atl1_adapter *adapter)
f3cc28c7
JC		 2614{
2615 struct net_device *netdev = adapter->netdev;
2616 int err;
2617 int irq_flags = IRQF_SAMPLE_RANDOM;
2618
2619 /* hardware has been reset, we need to reload some things */
6446a860 2620 atlx_set_multi(netdev);
2ca13da7 2621 atl1_init_ring_ptrs(adapter);
6446a860 2622 atlx_restore_vlan(adapter);
f3cc28c7 2623 err = atl1_alloc_rx_buffers(adapter);
6446a860
JC		 2624 if (unlikely(!err))
2625 /* no RX BUFFER allocated */
f3cc28c7
JC		 2626 return -ENOMEM;
2627
2628 if (unlikely(atl1_configure(adapter))) {
2629 err = -EIO;
2630 goto err_up;
2631 }
2632
2633 err = pci_enable_msi(adapter->pdev);
2634 if (err) {
6446a860
JC		 2635 if (netif_msg_ifup(adapter))
2636 dev_info(&adapter->pdev->dev,
2637 "Unable to enable MSI: %d\n", err);
f3cc28c7
JC		 2638 irq_flags |= IRQF_SHARED;
2639 }
2640
2641 err = request_irq(adapter->pdev->irq, &atl1_intr, irq_flags,
2642 netdev->name, netdev);
2643 if (unlikely(err))
2644 goto err_up;
2645
2646 mod_timer(&adapter->watchdog_timer, jiffies);
6446a860 2647 atlx_irq_enable(adapter);
f3cc28c7
JC		 2648 atl1_check_link(adapter);
2649 return 0;
2650
f3cc28c7
JC		 2651err_up:
2652 pci_disable_msi(adapter->pdev);
2653 /* free rx_buffers */
2654 atl1_clean_rx_ring(adapter);
2655 return err;
2656}
2657
6446a860 2658static void atl1_down(struct atl1_adapter *adapter)
f3cc28c7
JC		 2659{
2660 struct net_device *netdev = adapter->netdev;
2661
2662 del_timer_sync(&adapter->watchdog_timer);
2663 del_timer_sync(&adapter->phy_config_timer);
2664 adapter->phy_timer_pending = false;
2665
6446a860 2666 atlx_irq_disable(adapter);
f3cc28c7
JC		 2667 free_irq(adapter->pdev->irq, netdev);
2668 pci_disable_msi(adapter->pdev);
2669 atl1_reset_hw(&adapter->hw);
2670 adapter->cmb.cmb->int_stats = 0;
2671
2672 adapter->link_speed = SPEED_0;
2673 adapter->link_duplex = -1;
2674 netif_carrier_off(netdev);
2675 netif_stop_queue(netdev);
f3cc28c7 2676
f3cc28c7
JC		 2677 atl1_clean_tx_ring(adapter);
2678 atl1_clean_rx_ring(adapter);
f3cc28c7
JC		 2679}
2680
6446a860
JC		 2681static void atl1_tx_timeout_task(struct work_struct *work)
2682{
2683 struct atl1_adapter *adapter =
2684 container_of(work, struct atl1_adapter, tx_timeout_task);
2685 struct net_device *netdev = adapter->netdev;
2686
2687 netif_device_detach(netdev);
2688 atl1_down(adapter);
305282ba 2689 atl1_up(adapter);
6446a860 2690 netif_device_attach(netdev);
305282ba
JC		 2691}
2692
6446a860
JC		 2693/*
2694 * atl1_change_mtu - Change the Maximum Transfer Unit
2695 * @netdev: network interface device structure
2696 * @new_mtu: new value for maximum frame size
2697 *
2698 * Returns 0 on success, negative on failure
2699 */
2700static int atl1_change_mtu(struct net_device *netdev, int new_mtu)
305282ba
JC		 2701{
2702 struct atl1_adapter *adapter = netdev_priv(netdev);
6446a860
JC		 2703 int old_mtu = netdev->mtu;
2704 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN;
305282ba 2705
6446a860
JC		 2706 if ((max_frame < ETH_ZLEN + ETH_FCS_LEN) ||
2707 (max_frame > MAX_JUMBO_FRAME_SIZE)) {
2708 if (netif_msg_link(adapter))
2709 dev_warn(&adapter->pdev->dev, "invalid MTU setting\n");
2710 return -EINVAL;
305282ba 2711 }
6446a860
JC		 2712
2713 adapter->hw.max_frame_size = max_frame;
2714 adapter->hw.tx_jumbo_task_th = (max_frame + 7) >> 3;
2715 adapter->rx_buffer_len = (max_frame + 7) & ~7;
2716 adapter->hw.rx_jumbo_th = adapter->rx_buffer_len / 8;
2717
2718 netdev->mtu = new_mtu;
2719 if ((old_mtu != new_mtu) && netif_running(netdev)) {
2720 atl1_down(adapter);
2721 atl1_up(adapter);
2722 }
2723
2724 return 0;
305282ba
JC		 2725}
2726
f3cc28c7
JC		 2727/*
2728 * atl1_open - Called when a network interface is made active
2729 * @netdev: network interface device structure
2730 *
2731 * Returns 0 on success, negative value on failure
2732 *
2733 * The open entry point is called when a network interface is made
2734 * active by the system (IFF_UP). At this point all resources needed
2735 * for transmit and receive operations are allocated, the interrupt
2736 * handler is registered with the OS, the watchdog timer is started,
2737 * and the stack is notified that the interface is ready.
2738 */
2739static int atl1_open(struct net_device *netdev)
2740{
2741 struct atl1_adapter *adapter = netdev_priv(netdev);
2742 int err;
2743
2744 /* allocate transmit descriptors */
2745 err = atl1_setup_ring_resources(adapter);
2746 if (err)
2747 return err;
2748
2749 err = atl1_up(adapter);
2750 if (err)
2751 goto err_up;
2752
2753 return 0;
2754
2755err_up:
2756 atl1_reset(adapter);
2757 return err;
2758}
2759
2760/*
2761 * atl1_close - Disables a network interface
2762 * @netdev: network interface device structure
2763 *
2764 * Returns 0, this is not allowed to fail
2765 *
2766 * The close entry point is called when an interface is de-activated
2767 * by the OS. The hardware is still under the drivers control, but
2768 * needs to be disabled. A global MAC reset is issued to stop the
2769 * hardware, and all transmit and receive resources are freed.
2770 */
2771static int atl1_close(struct net_device *netdev)
2772{
2773 struct atl1_adapter *adapter = netdev_priv(netdev);
2774 atl1_down(adapter);
2775 atl1_free_ring_resources(adapter);
2776 return 0;
2777}
2778
05ffdd7b
JC		 2779#ifdef CONFIG_PM
2780static int atl1_suspend(struct pci_dev *pdev, pm_message_t state)
f3cc28c7 2781{
05ffdd7b
JC		 2782 struct net_device *netdev = pci_get_drvdata(pdev);
2783 struct atl1_adapter *adapter = netdev_priv(netdev);
2784 struct atl1_hw *hw = &adapter->hw;
2785 u32 ctrl = 0;
2786 u32 wufc = adapter->wol;
f3cc28c7
JC		 2787
2788 netif_device_detach(netdev);
05ffdd7b
JC		 2789 if (netif_running(netdev))
2790 atl1_down(adapter);
f3cc28c7 2791
05ffdd7b
JC		 2792 atl1_read_phy_reg(hw, MII_BMSR, (u16 *) & ctrl);
2793 atl1_read_phy_reg(hw, MII_BMSR, (u16 *) & ctrl);
2794 if (ctrl & BMSR_LSTATUS)
6446a860 2795 wufc &= ~ATLX_WUFC_LNKC;
f3cc28c7 2796
05ffdd7b
JC		 2797 /* reduce speed to 10/100M */
2798 if (wufc) {
2799 atl1_phy_enter_power_saving(hw);
2800 /* if resume, let driver to re- setup link */
2801 hw->phy_configured = false;
2802 atl1_set_mac_addr(hw);
6446a860 2803 atlx_set_multi(netdev);
05ffdd7b
JC		 2804
2805 ctrl = 0;
2806 /* turn on magic packet wol */
6446a860 2807 if (wufc & ATLX_WUFC_MAG)
05ffdd7b
JC		 2808 ctrl = WOL_MAGIC_EN | WOL_MAGIC_PME_EN;
2809
2810 /* turn on Link change WOL */
6446a860 2811 if (wufc & ATLX_WUFC_LNKC)
05ffdd7b
JC		 2812 ctrl |= (WOL_LINK_CHG_EN | WOL_LINK_CHG_PME_EN);
2813 iowrite32(ctrl, hw->hw_addr + REG_WOL_CTRL);
2814
2815 /* turn on all-multi mode if wake on multicast is enabled */
2816 ctrl = ioread32(hw->hw_addr + REG_MAC_CTRL);
2817 ctrl &= ~MAC_CTRL_DBG;
2818 ctrl &= ~MAC_CTRL_PROMIS_EN;
6446a860 2819 if (wufc & ATLX_WUFC_MC)
05ffdd7b
JC		 2820 ctrl |= MAC_CTRL_MC_ALL_EN;
2821 else
2822 ctrl &= ~MAC_CTRL_MC_ALL_EN;
2823
2824 /* turn on broadcast mode if wake on-BC is enabled */
6446a860 2825 if (wufc & ATLX_WUFC_BC)
05ffdd7b
JC		 2826 ctrl |= MAC_CTRL_BC_EN;
2827 else
2828 ctrl &= ~MAC_CTRL_BC_EN;
2829
2830 /* enable RX */
2831 ctrl |= MAC_CTRL_RX_EN;
2832 iowrite32(ctrl, hw->hw_addr + REG_MAC_CTRL);
2833 pci_enable_wake(pdev, PCI_D3hot, 1);
2834 pci_enable_wake(pdev, PCI_D3cold, 1);
2835 } else {
2836 iowrite32(0, hw->hw_addr + REG_WOL_CTRL);
2837 pci_enable_wake(pdev, PCI_D3hot, 0);
2838 pci_enable_wake(pdev, PCI_D3cold, 0);
2839 }
2840
2841 pci_save_state(pdev);
2842 pci_disable_device(pdev);
2843
2844 pci_set_power_state(pdev, PCI_D3hot);
2845
2846 return 0;
f3cc28c7
JC		 2847}
2848
05ffdd7b 2849static int atl1_resume(struct pci_dev *pdev)
f3cc28c7 2850{
05ffdd7b
JC		 2851 struct net_device *netdev = pci_get_drvdata(pdev);
2852 struct atl1_adapter *adapter = netdev_priv(netdev);
6446a860 2853 u32 err;
53ffb42c 2854
6446a860 2855 pci_set_power_state(pdev, PCI_D0);
05ffdd7b
JC		 2856 pci_restore_state(pdev);
2857
6446a860
JC		 2858 /* FIXME: check and handle */
2859 err = pci_enable_device(pdev);
05ffdd7b
JC		 2860 pci_enable_wake(pdev, PCI_D3hot, 0);
2861 pci_enable_wake(pdev, PCI_D3cold, 0);
2862
2863 iowrite32(0, adapter->hw.hw_addr + REG_WOL_CTRL);
2864 atl1_reset(adapter);
2865
2866 if (netif_running(netdev))
2867 atl1_up(adapter);
2868 netif_device_attach(netdev);
2869
2870 atl1_via_workaround(adapter);
2871
2872 return 0;
f3cc28c7 2873}
05ffdd7b
JC		 2874#else
2875#define atl1_suspend NULL
2876#define atl1_resume NULL
2877#endif
f3cc28c7 2878
05ffdd7b
JC		 2879#ifdef CONFIG_NET_POLL_CONTROLLER
2880static void atl1_poll_controller(struct net_device *netdev)
f3cc28c7 2881{
05ffdd7b
JC		 2882 disable_irq(netdev->irq);
2883 atl1_intr(netdev->irq, netdev);
2884 enable_irq(netdev->irq);
f3cc28c7 2885}
05ffdd7b 2886#endif
f3cc28c7
JC		 2887
2888/*
2889 * atl1_probe - Device Initialization Routine
2890 * @pdev: PCI device information struct
2891 * @ent: entry in atl1_pci_tbl
2892 *
2893 * Returns 0 on success, negative on failure
2894 *
2895 * atl1_probe initializes an adapter identified by a pci_dev structure.
2896 * The OS initialization, configuring of the adapter private structure,
2897 * and a hardware reset occur.
2898 */
2899static int __devinit atl1_probe(struct pci_dev *pdev,
53ffb42c 2900 const struct pci_device_id *ent)
f3cc28c7
JC		 2901{
2902 struct net_device *netdev;
2903 struct atl1_adapter *adapter;
2904 static int cards_found = 0;
f3cc28c7
JC		 2905 int err;
2906
2907 err = pci_enable_device(pdev);
2908 if (err)
2909 return err;
2910
5f08e46b 2911 /*
cdcc520d
CS		 2912 * The atl1 chip can DMA to 64-bit addresses, but it uses a single
2913 * shared register for the high 32 bits, so only a single, aligned,
2914 * 4 GB physical address range can be used at a time.
2915 *
2916 * Supporting 64-bit DMA on this hardware is more trouble than it's
2917 * worth. It is far easier to limit to 32-bit DMA than update
2918 * various kernel subsystems to support the mechanics required by a
2919 * fixed-high-32-bit system.
5f08e46b
LT		 2920 */
2921 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
f3cc28c7 2922 if (err) {
5f08e46b
LT		 2923 dev_err(&pdev->dev, "no usable DMA configuration\n");
2924 goto err_dma;
f3cc28c7 2925 }
6446a860
JC		 2926 /*
2927 * Mark all PCI regions associated with PCI device
f3cc28c7
JC		 2928 * pdev as being reserved by owner atl1_driver_name
2929 */
6446a860 2930 err = pci_request_regions(pdev, ATLX_DRIVER_NAME);
f3cc28c7
JC		 2931 if (err)
2932 goto err_request_regions;
2933
6446a860
JC		 2934 /*
2935 * Enables bus-mastering on the device and calls
f3cc28c7
JC		 2936 * pcibios_set_master to do the needed arch specific settings
2937 */
2938 pci_set_master(pdev);
2939
2940 netdev = alloc_etherdev(sizeof(struct atl1_adapter));
2941 if (!netdev) {
2942 err = -ENOMEM;
2943 goto err_alloc_etherdev;
2944 }
f3cc28c7
JC		 2945 SET_NETDEV_DEV(netdev, &pdev->dev);
2946
2947 pci_set_drvdata(pdev, netdev);
2948 adapter = netdev_priv(netdev);
2949 adapter->netdev = netdev;
2950 adapter->pdev = pdev;
2951 adapter->hw.back = adapter;
6446a860 2952 adapter->msg_enable = netif_msg_init(debug, atl1_default_msg);
f3cc28c7
JC		 2953
2954 adapter->hw.hw_addr = pci_iomap(pdev, 0, 0);
2955 if (!adapter->hw.hw_addr) {
2956 err = -EIO;
2957 goto err_pci_iomap;
2958 }
2959 /* get device revision number */
1e006364 2960 adapter->hw.dev_rev = ioread16(adapter->hw.hw_addr +
53ffb42c 2961 (REG_MASTER_CTRL + 2));
6446a860
JC		 2962 if (netif_msg_probe(adapter))
2963 dev_info(&pdev->dev, "version %s\n", ATLX_DRIVER_VERSION);
f3cc28c7
JC		 2964
2965 /* set default ring resource counts */
2966 adapter->rfd_ring.count = adapter->rrd_ring.count = ATL1_DEFAULT_RFD;
2967 adapter->tpd_ring.count = ATL1_DEFAULT_TPD;
2968
2969 adapter->mii.dev = netdev;
2970 adapter->mii.mdio_read = mdio_read;
2971 adapter->mii.mdio_write = mdio_write;
2972 adapter->mii.phy_id_mask = 0x1f;
2973 adapter->mii.reg_num_mask = 0x1f;
2974
2975 netdev->open = &atl1_open;
2976 netdev->stop = &atl1_close;
2977 netdev->hard_start_xmit = &atl1_xmit_frame;
6446a860
JC		 2978 netdev->get_stats = &atlx_get_stats;
2979 netdev->set_multicast_list = &atlx_set_multi;
f3cc28c7
JC		 2980 netdev->set_mac_address = &atl1_set_mac;
2981 netdev->change_mtu = &atl1_change_mtu;
6446a860
JC		 2982 netdev->do_ioctl = &atlx_ioctl;
2983 netdev->tx_timeout = &atlx_tx_timeout;
f3cc28c7 2984 netdev->watchdog_timeo = 5 * HZ;
497f050c
AD		 2985#ifdef CONFIG_NET_POLL_CONTROLLER
2986 netdev->poll_controller = atl1_poll_controller;
2987#endif
6446a860 2988 netdev->vlan_rx_register = atlx_vlan_rx_register;
cb434e38 2989
f3cc28c7
JC		 2990 netdev->ethtool_ops = &atl1_ethtool_ops;
2991 adapter->bd_number = cards_found;
f3cc28c7
JC		 2992
2993 /* setup the private structure */
2994 err = atl1_sw_init(adapter);
2995 if (err)
2996 goto err_common;
2997
2998 netdev->features = NETIF_F_HW_CSUM;
2999 netdev->features |= NETIF_F_SG;
3000 netdev->features |= (NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX);
6446a860 3001 netdev->features |= NETIF_F_TSO;
f3cc28c7
JC		 3002 netdev->features |= NETIF_F_LLTX;
3003
3004 /*
3005 * patch for some L1 of old version,
3006 * the final version of L1 may not need these
3007 * patches
3008 */
3009 /* atl1_pcie_patch(adapter); */
3010
3011 /* really reset GPHY core */
6446a860 3012 iowrite16(0, adapter->hw.hw_addr + REG_PHY_ENABLE);
f3cc28c7
JC		 3013
3014 /*
3015 * reset the controller to
3016 * put the device in a known good starting state
3017 */
3018 if (atl1_reset_hw(&adapter->hw)) {
3019 err = -EIO;
3020 goto err_common;
3021 }
3022
3023 /* copy the MAC address out of the EEPROM */
3024 atl1_read_mac_addr(&adapter->hw);
3025 memcpy(netdev->dev_addr, adapter->hw.mac_addr, netdev->addr_len);
3026
3027 if (!is_valid_ether_addr(netdev->dev_addr)) {
3028 err = -EIO;
3029 goto err_common;
3030 }
3031
3032 atl1_check_options(adapter);
3033
3034 /* pre-init the MAC, and setup link */
3035 err = atl1_init_hw(&adapter->hw);
3036 if (err) {
3037 err = -EIO;
3038 goto err_common;
3039 }
3040
3041 atl1_pcie_patch(adapter);
3042 /* assume we have no link for now */
3043 netif_carrier_off(netdev);
3044 netif_stop_queue(netdev);
3045
3046 init_timer(&adapter->watchdog_timer);
3047 adapter->watchdog_timer.function = &atl1_watchdog;
3048 adapter->watchdog_timer.data = (unsigned long)adapter;
3049
3050 init_timer(&adapter->phy_config_timer);
3051 adapter->phy_config_timer.function = &atl1_phy_config;
3052 adapter->phy_config_timer.data = (unsigned long)adapter;
3053 adapter->phy_timer_pending = false;
3054
3055 INIT_WORK(&adapter->tx_timeout_task, atl1_tx_timeout_task);
3056
6446a860 3057 INIT_WORK(&adapter->link_chg_task, atlx_link_chg_task);
f3cc28c7
JC		 3058
3059 INIT_WORK(&adapter->pcie_dma_to_rst_task, atl1_tx_timeout_task);
3060
3061 err = register_netdev(netdev);
3062 if (err)
3063 goto err_common;
3064
3065 cards_found++;
3066 atl1_via_workaround(adapter);
3067 return 0;
3068
3069err_common:
3070 pci_iounmap(pdev, adapter->hw.hw_addr);
3071err_pci_iomap:
3072 free_netdev(netdev);
3073err_alloc_etherdev:
3074 pci_release_regions(pdev);
3075err_dma:
3076err_request_regions:
3077 pci_disable_device(pdev);
3078 return err;
3079}
3080
3081/*
3082 * atl1_remove - Device Removal Routine
3083 * @pdev: PCI device information struct
3084 *
3085 * atl1_remove is called by the PCI subsystem to alert the driver
3086 * that it should release a PCI device. The could be caused by a
3087 * Hot-Plug event, or because the driver is going to be removed from
3088 * memory.
3089 */
3090static void __devexit atl1_remove(struct pci_dev *pdev)
3091{
3092 struct net_device *netdev = pci_get_drvdata(pdev);
3093 struct atl1_adapter *adapter;
3094 /* Device not available. Return. */
3095 if (!netdev)
3096 return;
3097
3098 adapter = netdev_priv(netdev);
8c754a04 3099
6446a860
JC		 3100 /*
3101 * Some atl1 boards lack persistent storage for their MAC, and get it
8c754a04
CS		 3102 * from the BIOS during POST. If we've been messing with the MAC
3103 * address, we need to save the permanent one.
3104 */
3105 if (memcmp(adapter->hw.mac_addr, adapter->hw.perm_mac_addr, ETH_ALEN)) {
53ffb42c
JC		 3106 memcpy(adapter->hw.mac_addr, adapter->hw.perm_mac_addr,
3107 ETH_ALEN);
8c754a04
CS		 3108 atl1_set_mac_addr(&adapter->hw);
3109 }
3110
6446a860 3111 iowrite16(0, adapter->hw.hw_addr + REG_PHY_ENABLE);
f3cc28c7
JC		 3112 unregister_netdev(netdev);
3113 pci_iounmap(pdev, adapter->hw.hw_addr);
3114 pci_release_regions(pdev);
3115 free_netdev(netdev);
3116 pci_disable_device(pdev);
3117}
3118
f3cc28c7 3119static struct pci_driver atl1_driver = {
6446a860 3120 .name = ATLX_DRIVER_NAME,
f3cc28c7
JC		 3121 .id_table = atl1_pci_tbl,
3122 .probe = atl1_probe,
3123 .remove = __devexit_p(atl1_remove),
f3cc28c7
JC		 3124 .suspend = atl1_suspend,
3125 .resume = atl1_resume
3126};
3127
3128/*
3129 * atl1_exit_module - Driver Exit Cleanup Routine
3130 *
3131 * atl1_exit_module is called just before the driver is removed
3132 * from memory.
3133 */
3134static void __exit atl1_exit_module(void)
3135{
3136 pci_unregister_driver(&atl1_driver);
3137}
3138
3139/*
3140 * atl1_init_module - Driver Registration Routine
3141 *
3142 * atl1_init_module is the first routine called when the driver is
3143 * loaded. All it does is register with the PCI subsystem.
3144 */
3145static int __init atl1_init_module(void)
3146{
f3cc28c7
JC		 3147 return pci_register_driver(&atl1_driver);
3148}
3149
3150module_init(atl1_init_module);
3151module_exit(atl1_exit_module);
6446a860
JC		 3152
3153struct atl1_stats {
3154 char stat_string[ETH_GSTRING_LEN];
3155 int sizeof_stat;
3156 int stat_offset;
3157};
3158
3159#define ATL1_STAT(m) \
3160 sizeof(((struct atl1_adapter *)0)->m), offsetof(struct atl1_adapter, m)
3161
3162static struct atl1_stats atl1_gstrings_stats[] = {
3163 {"rx_packets", ATL1_STAT(soft_stats.rx_packets)},
3164 {"tx_packets", ATL1_STAT(soft_stats.tx_packets)},
3165 {"rx_bytes", ATL1_STAT(soft_stats.rx_bytes)},
3166 {"tx_bytes", ATL1_STAT(soft_stats.tx_bytes)},
3167 {"rx_errors", ATL1_STAT(soft_stats.rx_errors)},
3168 {"tx_errors", ATL1_STAT(soft_stats.tx_errors)},
3169 {"rx_dropped", ATL1_STAT(net_stats.rx_dropped)},
3170 {"tx_dropped", ATL1_STAT(net_stats.tx_dropped)},
3171 {"multicast", ATL1_STAT(soft_stats.multicast)},
3172 {"collisions", ATL1_STAT(soft_stats.collisions)},
3173 {"rx_length_errors", ATL1_STAT(soft_stats.rx_length_errors)},
3174 {"rx_over_errors", ATL1_STAT(soft_stats.rx_missed_errors)},
3175 {"rx_crc_errors", ATL1_STAT(soft_stats.rx_crc_errors)},
3176 {"rx_frame_errors", ATL1_STAT(soft_stats.rx_frame_errors)},
3177 {"rx_fifo_errors", ATL1_STAT(soft_stats.rx_fifo_errors)},
3178 {"rx_missed_errors", ATL1_STAT(soft_stats.rx_missed_errors)},
3179 {"tx_aborted_errors", ATL1_STAT(soft_stats.tx_aborted_errors)},
3180 {"tx_carrier_errors", ATL1_STAT(soft_stats.tx_carrier_errors)},
3181 {"tx_fifo_errors", ATL1_STAT(soft_stats.tx_fifo_errors)},
3182 {"tx_window_errors", ATL1_STAT(soft_stats.tx_window_errors)},
3183 {"tx_abort_exce_coll", ATL1_STAT(soft_stats.excecol)},
3184 {"tx_abort_late_coll", ATL1_STAT(soft_stats.latecol)},
3185 {"tx_deferred_ok", ATL1_STAT(soft_stats.deffer)},
3186 {"tx_single_coll_ok", ATL1_STAT(soft_stats.scc)},
3187 {"tx_multi_coll_ok", ATL1_STAT(soft_stats.mcc)},
3188 {"tx_underun", ATL1_STAT(soft_stats.tx_underun)},
3189 {"tx_trunc", ATL1_STAT(soft_stats.tx_trunc)},
3190 {"tx_pause", ATL1_STAT(soft_stats.tx_pause)},
3191 {"rx_pause", ATL1_STAT(soft_stats.rx_pause)},
3192 {"rx_rrd_ov", ATL1_STAT(soft_stats.rx_rrd_ov)},
3193 {"rx_trunc", ATL1_STAT(soft_stats.rx_trunc)}
3194};
3195
3196static void atl1_get_ethtool_stats(struct net_device *netdev,
3197 struct ethtool_stats *stats, u64 *data)
305282ba 3198{
6446a860 3199 struct atl1_adapter *adapter = netdev_priv(netdev);
305282ba 3200 int i;
6446a860 3201 char *p;
305282ba 3202
6446a860
JC		 3203 for (i = 0; i < ARRAY_SIZE(atl1_gstrings_stats); i++) {
3204 p = (char *)adapter+atl1_gstrings_stats[i].stat_offset;
3205 data[i] = (atl1_gstrings_stats[i].sizeof_stat ==
3206 sizeof(u64)) ? *(u64 *)p : *(u32 *)p;
305282ba
JC		 3207 }
3208
305282ba
JC		 3209}
3210
6446a860 3211static int atl1_get_sset_count(struct net_device *netdev, int sset)
305282ba 3212{
6446a860
JC		 3213 switch (sset) {
3214 case ETH_SS_STATS:
3215 return ARRAY_SIZE(atl1_gstrings_stats);
3216 default:
3217 return -EOPNOTSUPP;
3218 }
305282ba
JC		 3219}
3220
6446a860
JC		 3221static int atl1_get_settings(struct net_device *netdev,
3222 struct ethtool_cmd *ecmd)
305282ba 3223{
6446a860
JC		 3224 struct atl1_adapter *adapter = netdev_priv(netdev);
3225 struct atl1_hw *hw = &adapter->hw;
3226
3227 ecmd->supported = (SUPPORTED_10baseT_Half |
3228 SUPPORTED_10baseT_Full |
3229 SUPPORTED_100baseT_Half |
3230 SUPPORTED_100baseT_Full |
3231 SUPPORTED_1000baseT_Full |
3232 SUPPORTED_Autoneg | SUPPORTED_TP);
3233 ecmd->advertising = ADVERTISED_TP;
3234 if (hw->media_type == MEDIA_TYPE_AUTO_SENSOR ||
3235 hw->media_type == MEDIA_TYPE_1000M_FULL) {
3236 ecmd->advertising |= ADVERTISED_Autoneg;
3237 if (hw->media_type == MEDIA_TYPE_AUTO_SENSOR) {
3238 ecmd->advertising |= ADVERTISED_Autoneg;
3239 ecmd->advertising |=
3240 (ADVERTISED_10baseT_Half |
3241 ADVERTISED_10baseT_Full |
3242 ADVERTISED_100baseT_Half |
3243 ADVERTISED_100baseT_Full |
3244 ADVERTISED_1000baseT_Full);
3245 } else
3246 ecmd->advertising |= (ADVERTISED_1000baseT_Full);
3247 }
3248 ecmd->port = PORT_TP;
3249 ecmd->phy_address = 0;
3250 ecmd->transceiver = XCVR_INTERNAL;
3251
3252 if (netif_carrier_ok(adapter->netdev)) {
3253 u16 link_speed, link_duplex;
3254 atl1_get_speed_and_duplex(hw, &link_speed, &link_duplex);
3255 ecmd->speed = link_speed;
3256 if (link_duplex == FULL_DUPLEX)
3257 ecmd->duplex = DUPLEX_FULL;
3258 else
3259 ecmd->duplex = DUPLEX_HALF;
3260 } else {
3261 ecmd->speed = -1;
3262 ecmd->duplex = -1;
3263 }
3264 if (hw->media_type == MEDIA_TYPE_AUTO_SENSOR ||
3265 hw->media_type == MEDIA_TYPE_1000M_FULL)
3266 ecmd->autoneg = AUTONEG_ENABLE;
3267 else
3268 ecmd->autoneg = AUTONEG_DISABLE;
305282ba 3269
305282ba
JC		 3270 return 0;
3271}
3272
6446a860
JC		 3273static int atl1_set_settings(struct net_device *netdev,
3274 struct ethtool_cmd *ecmd)
305282ba 3275{
6446a860
JC		 3276 struct atl1_adapter *adapter = netdev_priv(netdev);
3277 struct atl1_hw *hw = &adapter->hw;
305282ba 3278 u16 phy_data;
6446a860
JC		 3279 int ret_val = 0;
3280 u16 old_media_type = hw->media_type;
305282ba 3281
6446a860
JC		 3282 if (netif_running(adapter->netdev)) {
3283 if (netif_msg_link(adapter))
3284 dev_dbg(&adapter->pdev->dev,
3285 "ethtool shutting down adapter\n");
3286 atl1_down(adapter);
3287 }
3288
3289 if (ecmd->autoneg == AUTONEG_ENABLE)
3290 hw->media_type = MEDIA_TYPE_AUTO_SENSOR;
3291 else {
3292 if (ecmd->speed == SPEED_1000) {
3293 if (ecmd->duplex != DUPLEX_FULL) {
3294 if (netif_msg_link(adapter))
3295 dev_warn(&adapter->pdev->dev,
3296 "1000M half is invalid\n");
3297 ret_val = -EINVAL;
3298 goto exit_sset;
3299 }
3300 hw->media_type = MEDIA_TYPE_1000M_FULL;
3301 } else if (ecmd->speed == SPEED_100) {
3302 if (ecmd->duplex == DUPLEX_FULL)
3303 hw->media_type = MEDIA_TYPE_100M_FULL;
3304 else
3305 hw->media_type = MEDIA_TYPE_100M_HALF;
3306 } else {
3307 if (ecmd->duplex == DUPLEX_FULL)
3308 hw->media_type = MEDIA_TYPE_10M_FULL;
3309 else
3310 hw->media_type = MEDIA_TYPE_10M_HALF;
3311 }
3312 }
3313 switch (hw->media_type) {
3314 case MEDIA_TYPE_AUTO_SENSOR:
3315 ecmd->advertising =
3316 ADVERTISED_10baseT_Half |
3317 ADVERTISED_10baseT_Full |
3318 ADVERTISED_100baseT_Half |
3319 ADVERTISED_100baseT_Full |
3320 ADVERTISED_1000baseT_Full |
3321 ADVERTISED_Autoneg | ADVERTISED_TP;
3322 break;
3323 case MEDIA_TYPE_1000M_FULL:
3324 ecmd->advertising =
3325 ADVERTISED_1000baseT_Full |
3326 ADVERTISED_Autoneg | ADVERTISED_TP;
3327 break;
3328 default:
3329 ecmd->advertising = 0;
3330 break;
3331 }
3332 if (atl1_phy_setup_autoneg_adv(hw)) {
3333 ret_val = -EINVAL;
3334 if (netif_msg_link(adapter))
3335 dev_warn(&adapter->pdev->dev,
3336 "invalid ethtool speed/duplex setting\n");
3337 goto exit_sset;
3338 }
305282ba
JC		 3339 if (hw->media_type == MEDIA_TYPE_AUTO_SENSOR ||
3340 hw->media_type == MEDIA_TYPE_1000M_FULL)
3341 phy_data = MII_CR_RESET | MII_CR_AUTO_NEG_EN;
3342 else {
3343 switch (hw->media_type) {
3344 case MEDIA_TYPE_100M_FULL:
3345 phy_data =
3346 MII_CR_FULL_DUPLEX | MII_CR_SPEED_100 |
3347 MII_CR_RESET;
3348 break;
3349 case MEDIA_TYPE_100M_HALF:
3350 phy_data = MII_CR_SPEED_100 | MII_CR_RESET;
3351 break;
3352 case MEDIA_TYPE_10M_FULL:
3353 phy_data =
3354 MII_CR_FULL_DUPLEX | MII_CR_SPEED_10 | MII_CR_RESET;
3355 break;
3356 default:
3357 /* MEDIA_TYPE_10M_HALF: */
3358 phy_data = MII_CR_SPEED_10 | MII_CR_RESET;
3359 break;
3360 }
3361 }
6446a860
JC		 3362 atl1_write_phy_reg(hw, MII_BMCR, phy_data);
3363exit_sset:
3364 if (ret_val)
3365 hw->media_type = old_media_type;
305282ba 3366
6446a860
JC		 3367 if (netif_running(adapter->netdev)) {
3368 if (netif_msg_link(adapter))
3369 dev_dbg(&adapter->pdev->dev,
3370 "ethtool starting adapter\n");
3371 atl1_up(adapter);
3372 } else if (!ret_val) {
3373 if (netif_msg_link(adapter))
3374 dev_dbg(&adapter->pdev->dev,
3375 "ethtool resetting adapter\n");
3376 atl1_reset(adapter);
3377 }
3378 return ret_val;
3379}
305282ba 3380
6446a860
JC		 3381static void atl1_get_drvinfo(struct net_device *netdev,
3382 struct ethtool_drvinfo *drvinfo)
3383{
3384 struct atl1_adapter *adapter = netdev_priv(netdev);
305282ba 3385
6446a860
JC		 3386 strncpy(drvinfo->driver, ATLX_DRIVER_NAME, sizeof(drvinfo->driver));
3387 strncpy(drvinfo->version, ATLX_DRIVER_VERSION,
3388 sizeof(drvinfo->version));
3389 strncpy(drvinfo->fw_version, "N/A", sizeof(drvinfo->fw_version));
3390 strncpy(drvinfo->bus_info, pci_name(adapter->pdev),
3391 sizeof(drvinfo->bus_info));
3392 drvinfo->eedump_len = ATL1_EEDUMP_LEN;
3393}
3394
3395static void atl1_get_wol(struct net_device *netdev,
3396 struct ethtool_wolinfo *wol)
3397{
3398 struct atl1_adapter *adapter = netdev_priv(netdev);
3399
3400 wol->supported = WAKE_UCAST | WAKE_MCAST | WAKE_BCAST | WAKE_MAGIC;
3401 wol->wolopts = 0;
3402 if (adapter->wol & ATLX_WUFC_EX)
3403 wol->wolopts |= WAKE_UCAST;
3404 if (adapter->wol & ATLX_WUFC_MC)
3405 wol->wolopts |= WAKE_MCAST;
3406 if (adapter->wol & ATLX_WUFC_BC)
3407 wol->wolopts |= WAKE_BCAST;
3408 if (adapter->wol & ATLX_WUFC_MAG)
3409 wol->wolopts |= WAKE_MAGIC;
3410 return;
3411}
3412
3413static int atl1_set_wol(struct net_device *netdev,
3414 struct ethtool_wolinfo *wol)
3415{
3416 struct atl1_adapter *adapter = netdev_priv(netdev);
3417
3418 if (wol->wolopts & (WAKE_PHY | WAKE_ARP | WAKE_MAGICSECURE))
3419 return -EOPNOTSUPP;
3420 adapter->wol = 0;
3421 if (wol->wolopts & WAKE_UCAST)
3422 adapter->wol |= ATLX_WUFC_EX;
3423 if (wol->wolopts & WAKE_MCAST)
3424 adapter->wol |= ATLX_WUFC_MC;
3425 if (wol->wolopts & WAKE_BCAST)
3426 adapter->wol |= ATLX_WUFC_BC;
3427 if (wol->wolopts & WAKE_MAGIC)
3428 adapter->wol |= ATLX_WUFC_MAG;
305282ba
JC		 3429 return 0;
3430}
3431
6446a860 3432static u32 atl1_get_msglevel(struct net_device *netdev)
305282ba 3433{
6446a860
JC		 3434 struct atl1_adapter *adapter = netdev_priv(netdev);
3435 return adapter->msg_enable;
3436}
305282ba 3437
6446a860
JC		 3438static void atl1_set_msglevel(struct net_device *netdev, u32 value)
3439{
3440 struct atl1_adapter *adapter = netdev_priv(netdev);
3441 adapter->msg_enable = value;
3442}
305282ba 3443
6446a860
JC		 3444static int atl1_get_regs_len(struct net_device *netdev)
3445{
3446 return ATL1_REG_COUNT * sizeof(u32);
3447}
305282ba 3448
6446a860
JC		 3449static void atl1_get_regs(struct net_device *netdev, struct ethtool_regs *regs,
3450 void *p)
3451{
3452 struct atl1_adapter *adapter = netdev_priv(netdev);
3453 struct atl1_hw *hw = &adapter->hw;
3454 unsigned int i;
3455 u32 *regbuf = p;
305282ba 3456
6446a860
JC		 3457 for (i = 0; i < ATL1_REG_COUNT; i++) {
3458 /*
3459 * This switch statement avoids reserved regions
3460 * of register space.
3461 */
3462 switch (i) {
3463 case 6 ... 9:
3464 case 14:
3465 case 29 ... 31:
3466 case 34 ... 63:
3467 case 75 ... 127:
3468 case 136 ... 1023:
3469 case 1027 ... 1087:
3470 case 1091 ... 1151:
3471 case 1194 ... 1195:
3472 case 1200 ... 1201:
3473 case 1206 ... 1213:
3474 case 1216 ... 1279:
3475 case 1290 ... 1311:
3476 case 1323 ... 1343:
3477 case 1358 ... 1359:
3478 case 1368 ... 1375:
3479 case 1378 ... 1383:
3480 case 1388 ... 1391:
3481 case 1393 ... 1395:
3482 case 1402 ... 1403:
3483 case 1410 ... 1471:
3484 case 1522 ... 1535:
3485 /* reserved region; don't read it */
3486 regbuf[i] = 0;
3487 break;
3488 default:
3489 /* unreserved region */
3490 regbuf[i] = ioread32(hw->hw_addr + (i * sizeof(u32)));
3491 }
3492 }
3493}
305282ba 3494
6446a860
JC		 3495static void atl1_get_ringparam(struct net_device *netdev,
3496 struct ethtool_ringparam *ring)
3497{
3498 struct atl1_adapter *adapter = netdev_priv(netdev);
3499 struct atl1_tpd_ring *txdr = &adapter->tpd_ring;
3500 struct atl1_rfd_ring *rxdr = &adapter->rfd_ring;
305282ba 3501
6446a860
JC		 3502 ring->rx_max_pending = ATL1_MAX_RFD;
3503 ring->tx_max_pending = ATL1_MAX_TPD;
3504 ring->rx_mini_max_pending = 0;
3505 ring->rx_jumbo_max_pending = 0;
3506 ring->rx_pending = rxdr->count;
3507 ring->tx_pending = txdr->count;
3508 ring->rx_mini_pending = 0;
3509 ring->rx_jumbo_pending = 0;
3510}
305282ba 3511
6446a860
JC		 3512static int atl1_set_ringparam(struct net_device *netdev,
3513 struct ethtool_ringparam *ring)
3514{
3515 struct atl1_adapter *adapter = netdev_priv(netdev);
3516 struct atl1_tpd_ring *tpdr = &adapter->tpd_ring;
3517 struct atl1_rrd_ring *rrdr = &adapter->rrd_ring;
3518 struct atl1_rfd_ring *rfdr = &adapter->rfd_ring;
305282ba 3519
6446a860
JC		 3520 struct atl1_tpd_ring tpd_old, tpd_new;
3521 struct atl1_rfd_ring rfd_old, rfd_new;
3522 struct atl1_rrd_ring rrd_old, rrd_new;
3523 struct atl1_ring_header rhdr_old, rhdr_new;
3524 int err;
305282ba 3525
6446a860
JC		 3526 tpd_old = adapter->tpd_ring;
3527 rfd_old = adapter->rfd_ring;
3528 rrd_old = adapter->rrd_ring;
3529 rhdr_old = adapter->ring_header;
305282ba 3530
6446a860
JC		 3531 if (netif_running(adapter->netdev))
3532 atl1_down(adapter);
305282ba 3533
6446a860
JC		 3534 rfdr->count = (u16) max(ring->rx_pending, (u32) ATL1_MIN_RFD);
3535 rfdr->count = rfdr->count > ATL1_MAX_RFD ? ATL1_MAX_RFD :
3536 rfdr->count;
3537 rfdr->count = (rfdr->count + 3) & ~3;
3538 rrdr->count = rfdr->count;
305282ba 3539
6446a860
JC		 3540 tpdr->count = (u16) max(ring->tx_pending, (u32) ATL1_MIN_TPD);
3541 tpdr->count = tpdr->count > ATL1_MAX_TPD ? ATL1_MAX_TPD :
3542 tpdr->count;
3543 tpdr->count = (tpdr->count + 3) & ~3;
3544
3545 if (netif_running(adapter->netdev)) {
3546 /* try to get new resources before deleting old */
3547 err = atl1_setup_ring_resources(adapter);
3548 if (err)
3549 goto err_setup_ring;
3550
3551 /*
3552 * save the new, restore the old in order to free it,
3553 * then restore the new back again
3554 */
305282ba 3555
6446a860
JC		 3556 rfd_new = adapter->rfd_ring;
3557 rrd_new = adapter->rrd_ring;
3558 tpd_new = adapter->tpd_ring;
3559 rhdr_new = adapter->ring_header;
3560 adapter->rfd_ring = rfd_old;
3561 adapter->rrd_ring = rrd_old;
3562 adapter->tpd_ring = tpd_old;
3563 adapter->ring_header = rhdr_old;
3564 atl1_free_ring_resources(adapter);
3565 adapter->rfd_ring = rfd_new;
3566 adapter->rrd_ring = rrd_new;
3567 adapter->tpd_ring = tpd_new;
3568 adapter->ring_header = rhdr_new;
305282ba 3569
6446a860
JC		 3570 err = atl1_up(adapter);
3571 if (err)
3572 return err;
3573 }
305282ba 3574 return 0;
6446a860
JC		 3575
3576err_setup_ring:
3577 adapter->rfd_ring = rfd_old;
3578 adapter->rrd_ring = rrd_old;
3579 adapter->tpd_ring = tpd_old;
3580 adapter->ring_header = rhdr_old;
3581 atl1_up(adapter);
3582 return err;
305282ba
JC		 3583}
3584
6446a860
JC		 3585static void atl1_get_pauseparam(struct net_device *netdev,
3586 struct ethtool_pauseparam *epause)
305282ba 3587{
6446a860
JC		 3588 struct atl1_adapter *adapter = netdev_priv(netdev);
3589 struct atl1_hw *hw = &adapter->hw;
305282ba 3590
6446a860
JC		 3591 if (hw->media_type == MEDIA_TYPE_AUTO_SENSOR ||
3592 hw->media_type == MEDIA_TYPE_1000M_FULL) {
3593 epause->autoneg = AUTONEG_ENABLE;
3594 } else {
3595 epause->autoneg = AUTONEG_DISABLE;
305282ba 3596 }
6446a860
JC		 3597 epause->rx_pause = 1;
3598 epause->tx_pause = 1;
305282ba
JC		 3599}
3600
6446a860
JC		 3601static int atl1_set_pauseparam(struct net_device *netdev,
3602 struct ethtool_pauseparam *epause)
305282ba 3603{
6446a860
JC		 3604 struct atl1_adapter *adapter = netdev_priv(netdev);
3605 struct atl1_hw *hw = &adapter->hw;
305282ba 3606
6446a860
JC		 3607 if (hw->media_type == MEDIA_TYPE_AUTO_SENSOR ||
3608 hw->media_type == MEDIA_TYPE_1000M_FULL) {
3609 epause->autoneg = AUTONEG_ENABLE;
3610 } else {
3611 epause->autoneg = AUTONEG_DISABLE;
3612 }
3613
3614 epause->rx_pause = 1;
3615 epause->tx_pause = 1;
3616
3617 return 0;
305282ba
JC		 3618}
3619
6446a860
JC		 3620/* FIXME: is this right? -- CHS */
3621static u32 atl1_get_rx_csum(struct net_device *netdev)
305282ba 3622{
6446a860
JC		 3623 return 1;
3624}
305282ba 3625
6446a860
JC		 3626static void atl1_get_strings(struct net_device *netdev, u32 stringset,
3627 u8 *data)
3628{
3629 u8 *p = data;
3630 int i;
305282ba 3631
6446a860
JC		 3632 switch (stringset) {
3633 case ETH_SS_STATS:
3634 for (i = 0; i < ARRAY_SIZE(atl1_gstrings_stats); i++) {
3635 memcpy(p, atl1_gstrings_stats[i].stat_string,
3636 ETH_GSTRING_LEN);
3637 p += ETH_GSTRING_LEN;
3638 }
3639 break;
305282ba 3640 }
305282ba
JC		 3641}
3642
6446a860 3643static int atl1_nway_reset(struct net_device *netdev)
305282ba 3644{
6446a860
JC		 3645 struct atl1_adapter *adapter = netdev_priv(netdev);
3646 struct atl1_hw *hw = &adapter->hw;
305282ba 3647
6446a860
JC		 3648 if (netif_running(netdev)) {
3649 u16 phy_data;
3650 atl1_down(adapter);
305282ba 3651
6446a860
JC		 3652 if (hw->media_type == MEDIA_TYPE_AUTO_SENSOR ||
3653 hw->media_type == MEDIA_TYPE_1000M_FULL) {
3654 phy_data = MII_CR_RESET | MII_CR_AUTO_NEG_EN;
3655 } else {
3656 switch (hw->media_type) {
3657 case MEDIA_TYPE_100M_FULL:
3658 phy_data = MII_CR_FULL_DUPLEX |
3659 MII_CR_SPEED_100 | MII_CR_RESET;
3660 break;
3661 case MEDIA_TYPE_100M_HALF:
3662 phy_data = MII_CR_SPEED_100 | MII_CR_RESET;
3663 break;
3664 case MEDIA_TYPE_10M_FULL:
3665 phy_data = MII_CR_FULL_DUPLEX |
3666 MII_CR_SPEED_10 | MII_CR_RESET;
3667 break;
3668 default:
3669 /* MEDIA_TYPE_10M_HALF */
3670 phy_data = MII_CR_SPEED_10 | MII_CR_RESET;
3671 }
3672 }
3673 atl1_write_phy_reg(hw, MII_BMCR, phy_data);
3674 atl1_up(adapter);
305282ba 3675 }
305282ba
JC		 3676 return 0;
3677}
3678
6446a860
JC		 3679const struct ethtool_ops atl1_ethtool_ops = {
3680 .get_settings = atl1_get_settings,
3681 .set_settings = atl1_set_settings,
3682 .get_drvinfo = atl1_get_drvinfo,
3683 .get_wol = atl1_get_wol,
3684 .set_wol = atl1_set_wol,
3685 .get_msglevel = atl1_get_msglevel,
3686 .set_msglevel = atl1_set_msglevel,
3687 .get_regs_len = atl1_get_regs_len,
3688 .get_regs = atl1_get_regs,
3689 .get_ringparam = atl1_get_ringparam,
3690 .set_ringparam = atl1_set_ringparam,
3691 .get_pauseparam = atl1_get_pauseparam,
3692 .set_pauseparam = atl1_set_pauseparam,
3693 .get_rx_csum = atl1_get_rx_csum,
3694 .set_tx_csum = ethtool_op_set_tx_hw_csum,
3695 .get_link = ethtool_op_get_link,
3696 .set_sg = ethtool_op_set_sg,
3697 .get_strings = atl1_get_strings,
3698 .nway_reset = atl1_nway_reset,
3699 .get_ethtool_stats = atl1_get_ethtool_stats,
3700 .get_sset_count = atl1_get_sset_count,
3701 .set_tso = ethtool_op_set_tso,
3702};
Linux kernel - Deliverables
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