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f3cc28c7 JC |
1 | /* |
2 | * Copyright(c) 2005 - 2006 Attansic Corporation. All rights reserved. | |
305282ba | 3 | * Copyright(c) 2006 - 2007 Chris Snook <csnook@redhat.com> |
f3cc28c7 JC |
4 | * Copyright(c) 2006 Jay Cliburn <jcliburn@gmail.com> |
5 | * | |
6 | * Derived from Intel e1000 driver | |
7 | * Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved. | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify it | |
10 | * under the terms of the GNU General Public License as published by the Free | |
11 | * Software Foundation; either version 2 of the License, or (at your option) | |
12 | * any later version. | |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
15 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
16 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
17 | * more details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License along with | |
20 | * this program; if not, write to the Free Software Foundation, Inc., 59 | |
21 | * Temple Place - Suite 330, Boston, MA 02111-1307, USA. | |
22 | */ | |
23 | ||
305282ba JC |
24 | #ifndef ATL1_H |
25 | #define ATL1_H | |
f3cc28c7 | 26 | |
305282ba JC |
27 | #include <linux/compiler.h> |
28 | #include <linux/ethtool.h> | |
f3cc28c7 | 29 | #include <linux/if_vlan.h> |
305282ba JC |
30 | #include <linux/mii.h> |
31 | #include <linux/module.h> | |
32 | #include <linux/skbuff.h> | |
33 | #include <linux/spinlock.h> | |
34 | #include <linux/timer.h> | |
35 | #include <linux/types.h> | |
36 | #include <linux/workqueue.h> | |
37 | ||
38 | #include "atlx.h" | |
39 | ||
40 | #define ATLX_DRIVER_NAME "atl1" | |
f3cc28c7 | 41 | |
305282ba JC |
42 | MODULE_DESCRIPTION("Atheros L1 Gigabit Ethernet Driver"); |
43 | ||
44 | #define atlx_adapter atl1_adapter | |
45 | #define atlx_check_for_link atl1_check_for_link | |
46 | #define atlx_check_link atl1_check_link | |
47 | #define atlx_hash_mc_addr atl1_hash_mc_addr | |
48 | #define atlx_hash_set atl1_hash_set | |
49 | #define atlx_hw atl1_hw | |
50 | #define atlx_mii_ioctl atl1_mii_ioctl | |
51 | #define atlx_read_phy_reg atl1_read_phy_reg | |
52 | #define atlx_set_mac atl1_set_mac | |
53 | #define atlx_set_mac_addr atl1_set_mac_addr | |
54 | ||
55 | struct atl1_adapter; | |
56 | struct atl1_hw; | |
f3cc28c7 JC |
57 | |
58 | /* function prototypes needed by multiple files */ | |
305282ba JC |
59 | s32 atl1_phy_setup_autoneg_adv(struct atl1_hw *hw); |
60 | s32 atl1_write_phy_reg(struct atl1_hw *hw, u32 reg_addr, u16 phy_data); | |
61 | s32 atl1_get_speed_and_duplex(struct atl1_hw *hw, u16 *speed, u16 *duplex); | |
62 | s32 atl1_read_mac_addr(struct atl1_hw *hw); | |
63 | s32 atl1_init_hw(struct atl1_hw *hw); | |
64 | s32 atl1_get_speed_and_duplex(struct atl1_hw *hw, u16 *speed, u16 *duplex); | |
65 | s32 atl1_set_speed_and_duplex(struct atl1_hw *hw, u16 speed, u16 duplex); | |
66 | u32 atl1_hash_mc_addr(struct atl1_hw *hw, u8 *mc_addr); | |
67 | void atl1_hash_set(struct atl1_hw *hw, u32 hash_value); | |
68 | s32 atl1_read_phy_reg(struct atl1_hw *hw, u16 reg_addr, u16 *phy_data); | |
69 | void atl1_set_mac_addr(struct atl1_hw *hw); | |
70 | s32 atl1_phy_enter_power_saving(struct atl1_hw *hw); | |
71 | s32 atl1_reset_hw(struct atl1_hw *hw); | |
72 | void atl1_check_options(struct atl1_adapter *adapter); | |
73 | static int atl1_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, | |
74 | int cmd); | |
75 | static u32 atl1_check_link(struct atl1_adapter *adapter); | |
f3cc28c7 JC |
76 | s32 atl1_up(struct atl1_adapter *adapter); |
77 | void atl1_down(struct atl1_adapter *adapter); | |
78 | int atl1_reset(struct atl1_adapter *adapter); | |
f3cc28c7 | 79 | |
f3cc28c7 JC |
80 | extern const struct ethtool_ops atl1_ethtool_ops; |
81 | ||
305282ba JC |
82 | /* hardware definitions specific to L1 */ |
83 | ||
84 | /* Block IDLE Status Register */ | |
85 | #define IDLE_STATUS_RXMAC 0x1 | |
86 | #define IDLE_STATUS_TXMAC 0x2 | |
87 | #define IDLE_STATUS_RXQ 0x4 | |
88 | #define IDLE_STATUS_TXQ 0x8 | |
89 | #define IDLE_STATUS_DMAR 0x10 | |
90 | #define IDLE_STATUS_DMAW 0x20 | |
91 | #define IDLE_STATUS_SMB 0x40 | |
92 | #define IDLE_STATUS_CMB 0x80 | |
93 | ||
94 | /* MDIO Control Register */ | |
95 | #define MDIO_WAIT_TIMES 30 | |
96 | ||
97 | /* MAC Control Register */ | |
98 | #define MAC_CTRL_TX_PAUSE 0x10000 | |
99 | #define MAC_CTRL_SCNT 0x20000 | |
100 | #define MAC_CTRL_SRST_TX 0x40000 | |
101 | #define MAC_CTRL_TX_SIMURST 0x80000 | |
102 | #define MAC_CTRL_SPEED_SHIFT 20 | |
103 | #define MAC_CTRL_SPEED_MASK 0x300000 | |
104 | #define MAC_CTRL_SPEED_1000 0x2 | |
105 | #define MAC_CTRL_SPEED_10_100 0x1 | |
106 | #define MAC_CTRL_DBG_TX_BKPRESURE 0x400000 | |
107 | #define MAC_CTRL_TX_HUGE 0x800000 | |
108 | #define MAC_CTRL_RX_CHKSUM_EN 0x1000000 | |
109 | #define MAC_CTRL_DBG 0x8000000 | |
110 | ||
111 | /* Wake-On-Lan control register */ | |
112 | #define WOL_CLK_SWITCH_EN 0x8000 | |
113 | #define WOL_PT5_EN 0x200000 | |
114 | #define WOL_PT6_EN 0x400000 | |
115 | #define WOL_PT5_MATCH 0x8000000 | |
116 | #define WOL_PT6_MATCH 0x10000000 | |
117 | ||
118 | /* WOL Length ( 2 DWORD ) */ | |
119 | #define REG_WOL_PATTERN_LEN 0x14A4 | |
120 | #define WOL_PT_LEN_MASK 0x7F | |
121 | #define WOL_PT0_LEN_SHIFT 0 | |
122 | #define WOL_PT1_LEN_SHIFT 8 | |
123 | #define WOL_PT2_LEN_SHIFT 16 | |
124 | #define WOL_PT3_LEN_SHIFT 24 | |
125 | #define WOL_PT4_LEN_SHIFT 0 | |
126 | #define WOL_PT5_LEN_SHIFT 8 | |
127 | #define WOL_PT6_LEN_SHIFT 16 | |
128 | ||
129 | /* Internal SRAM Partition Registers, low 32 bits */ | |
130 | #define REG_SRAM_RFD_LEN 0x1504 | |
131 | #define REG_SRAM_RRD_ADDR 0x1508 | |
132 | #define REG_SRAM_RRD_LEN 0x150C | |
133 | #define REG_SRAM_TPD_ADDR 0x1510 | |
134 | #define REG_SRAM_TPD_LEN 0x1514 | |
135 | #define REG_SRAM_TRD_ADDR 0x1518 | |
136 | #define REG_SRAM_TRD_LEN 0x151C | |
137 | #define REG_SRAM_RXF_ADDR 0x1520 | |
138 | #define REG_SRAM_RXF_LEN 0x1524 | |
139 | #define REG_SRAM_TXF_ADDR 0x1528 | |
140 | #define REG_SRAM_TXF_LEN 0x152C | |
141 | #define REG_SRAM_TCPH_PATH_ADDR 0x1530 | |
142 | #define SRAM_TCPH_ADDR_MASK 0xFFF | |
143 | #define SRAM_TCPH_ADDR_SHIFT 0 | |
144 | #define SRAM_PATH_ADDR_MASK 0xFFF | |
145 | #define SRAM_PATH_ADDR_SHIFT 16 | |
146 | ||
147 | /* Load Ptr Register */ | |
148 | #define REG_LOAD_PTR 0x1534 | |
149 | ||
150 | /* Descriptor Control registers, low 32 bits */ | |
151 | #define REG_DESC_RFD_ADDR_LO 0x1544 | |
152 | #define REG_DESC_RRD_ADDR_LO 0x1548 | |
153 | #define REG_DESC_TPD_ADDR_LO 0x154C | |
154 | #define REG_DESC_CMB_ADDR_LO 0x1550 | |
155 | #define REG_DESC_SMB_ADDR_LO 0x1554 | |
156 | #define REG_DESC_RFD_RRD_RING_SIZE 0x1558 | |
157 | #define DESC_RFD_RING_SIZE_MASK 0x7FF | |
158 | #define DESC_RFD_RING_SIZE_SHIFT 0 | |
159 | #define DESC_RRD_RING_SIZE_MASK 0x7FF | |
160 | #define DESC_RRD_RING_SIZE_SHIFT 16 | |
161 | #define REG_DESC_TPD_RING_SIZE 0x155C | |
162 | #define DESC_TPD_RING_SIZE_MASK 0x3FF | |
163 | #define DESC_TPD_RING_SIZE_SHIFT 0 | |
164 | ||
165 | /* TXQ Control Register */ | |
166 | #define REG_TXQ_CTRL 0x1580 | |
167 | #define TXQ_CTRL_TPD_BURST_NUM_SHIFT 0 | |
168 | #define TXQ_CTRL_TPD_BURST_NUM_MASK 0x1F | |
169 | #define TXQ_CTRL_EN 0x20 | |
170 | #define TXQ_CTRL_ENH_MODE 0x40 | |
171 | #define TXQ_CTRL_TPD_FETCH_TH_SHIFT 8 | |
172 | #define TXQ_CTRL_TPD_FETCH_TH_MASK 0x3F | |
173 | #define TXQ_CTRL_TXF_BURST_NUM_SHIFT 16 | |
174 | #define TXQ_CTRL_TXF_BURST_NUM_MASK 0xFFFF | |
175 | ||
176 | /* Jumbo packet Threshold for task offload */ | |
177 | #define REG_TX_JUMBO_TASK_TH_TPD_IPG 0x1584 | |
178 | #define TX_JUMBO_TASK_TH_MASK 0x7FF | |
179 | #define TX_JUMBO_TASK_TH_SHIFT 0 | |
180 | #define TX_TPD_MIN_IPG_MASK 0x1F | |
181 | #define TX_TPD_MIN_IPG_SHIFT 16 | |
182 | ||
183 | /* RXQ Control Register */ | |
184 | #define REG_RXQ_CTRL 0x15A0 | |
185 | #define RXQ_CTRL_RFD_BURST_NUM_SHIFT 0 | |
186 | #define RXQ_CTRL_RFD_BURST_NUM_MASK 0xFF | |
187 | #define RXQ_CTRL_RRD_BURST_THRESH_SHIFT 8 | |
188 | #define RXQ_CTRL_RRD_BURST_THRESH_MASK 0xFF | |
189 | #define RXQ_CTRL_RFD_PREF_MIN_IPG_SHIFT 16 | |
190 | #define RXQ_CTRL_RFD_PREF_MIN_IPG_MASK 0x1F | |
191 | #define RXQ_CTRL_CUT_THRU_EN 0x40000000 | |
192 | #define RXQ_CTRL_EN 0x80000000 | |
193 | ||
194 | /* Rx jumbo packet threshold and rrd retirement timer */ | |
195 | #define REG_RXQ_JMBOSZ_RRDTIM 0x15A4 | |
196 | #define RXQ_JMBOSZ_TH_MASK 0x7FF | |
197 | #define RXQ_JMBOSZ_TH_SHIFT 0 | |
198 | #define RXQ_JMBO_LKAH_MASK 0xF | |
199 | #define RXQ_JMBO_LKAH_SHIFT 11 | |
200 | #define RXQ_RRD_TIMER_MASK 0xFFFF | |
201 | #define RXQ_RRD_TIMER_SHIFT 16 | |
202 | ||
203 | /* RFD flow control register */ | |
204 | #define REG_RXQ_RXF_PAUSE_THRESH 0x15A8 | |
205 | #define RXQ_RXF_PAUSE_TH_HI_SHIFT 16 | |
206 | #define RXQ_RXF_PAUSE_TH_HI_MASK 0xFFF | |
207 | #define RXQ_RXF_PAUSE_TH_LO_SHIFT 0 | |
208 | #define RXQ_RXF_PAUSE_TH_LO_MASK 0xFFF | |
209 | ||
210 | /* RRD flow control register */ | |
211 | #define REG_RXQ_RRD_PAUSE_THRESH 0x15AC | |
212 | #define RXQ_RRD_PAUSE_TH_HI_SHIFT 0 | |
213 | #define RXQ_RRD_PAUSE_TH_HI_MASK 0xFFF | |
214 | #define RXQ_RRD_PAUSE_TH_LO_SHIFT 16 | |
215 | #define RXQ_RRD_PAUSE_TH_LO_MASK 0xFFF | |
216 | ||
217 | /* DMA Engine Control Register */ | |
218 | #define REG_DMA_CTRL 0x15C0 | |
219 | #define DMA_CTRL_DMAR_IN_ORDER 0x1 | |
220 | #define DMA_CTRL_DMAR_ENH_ORDER 0x2 | |
221 | #define DMA_CTRL_DMAR_OUT_ORDER 0x4 | |
222 | #define DMA_CTRL_RCB_VALUE 0x8 | |
223 | #define DMA_CTRL_DMAR_BURST_LEN_SHIFT 4 | |
224 | #define DMA_CTRL_DMAR_BURST_LEN_MASK 7 | |
225 | #define DMA_CTRL_DMAW_BURST_LEN_SHIFT 7 | |
226 | #define DMA_CTRL_DMAW_BURST_LEN_MASK 7 | |
227 | #define DMA_CTRL_DMAR_EN 0x400 | |
228 | #define DMA_CTRL_DMAW_EN 0x800 | |
229 | ||
230 | /* CMB/SMB Control Register */ | |
231 | #define REG_CSMB_CTRL 0x15D0 | |
232 | #define CSMB_CTRL_CMB_NOW 1 | |
233 | #define CSMB_CTRL_SMB_NOW 2 | |
234 | #define CSMB_CTRL_CMB_EN 4 | |
235 | #define CSMB_CTRL_SMB_EN 8 | |
236 | ||
237 | /* CMB DMA Write Threshold Register */ | |
238 | #define REG_CMB_WRITE_TH 0x15D4 | |
239 | #define CMB_RRD_TH_SHIFT 0 | |
240 | #define CMB_RRD_TH_MASK 0x7FF | |
241 | #define CMB_TPD_TH_SHIFT 16 | |
242 | #define CMB_TPD_TH_MASK 0x7FF | |
243 | ||
244 | /* RX/TX count-down timer to trigger CMB-write. 2us resolution. */ | |
245 | #define REG_CMB_WRITE_TIMER 0x15D8 | |
246 | #define CMB_RX_TM_SHIFT 0 | |
247 | #define CMB_RX_TM_MASK 0xFFFF | |
248 | #define CMB_TX_TM_SHIFT 16 | |
249 | #define CMB_TX_TM_MASK 0xFFFF | |
250 | ||
251 | /* Number of packet received since last CMB write */ | |
252 | #define REG_CMB_RX_PKT_CNT 0x15DC | |
253 | ||
254 | /* Number of packet transmitted since last CMB write */ | |
255 | #define REG_CMB_TX_PKT_CNT 0x15E0 | |
256 | ||
257 | /* SMB auto DMA timer register */ | |
258 | #define REG_SMB_TIMER 0x15E4 | |
259 | ||
260 | /* Mailbox Register */ | |
261 | #define REG_MAILBOX 0x15F0 | |
262 | #define MB_RFD_PROD_INDX_SHIFT 0 | |
263 | #define MB_RFD_PROD_INDX_MASK 0x7FF | |
264 | #define MB_RRD_CONS_INDX_SHIFT 11 | |
265 | #define MB_RRD_CONS_INDX_MASK 0x7FF | |
266 | #define MB_TPD_PROD_INDX_SHIFT 22 | |
267 | #define MB_TPD_PROD_INDX_MASK 0x3FF | |
268 | ||
269 | /* Interrupt Status Register */ | |
270 | #define ISR_SMB 0x1 | |
271 | #define ISR_TIMER 0x2 | |
272 | #define ISR_MANUAL 0x4 | |
273 | #define ISR_RXF_OV 0x8 | |
274 | #define ISR_RFD_UNRUN 0x10 | |
275 | #define ISR_RRD_OV 0x20 | |
276 | #define ISR_TXF_UNRUN 0x40 | |
277 | #define ISR_LINK 0x80 | |
278 | #define ISR_HOST_RFD_UNRUN 0x100 | |
279 | #define ISR_HOST_RRD_OV 0x200 | |
280 | #define ISR_DMAR_TO_RST 0x400 | |
281 | #define ISR_DMAW_TO_RST 0x800 | |
282 | #define ISR_GPHY 0x1000 | |
283 | #define ISR_RX_PKT 0x10000 | |
284 | #define ISR_TX_PKT 0x20000 | |
285 | #define ISR_TX_DMA 0x40000 | |
286 | #define ISR_RX_DMA 0x80000 | |
287 | #define ISR_CMB_RX 0x100000 | |
288 | #define ISR_CMB_TX 0x200000 | |
289 | #define ISR_MAC_RX 0x400000 | |
290 | #define ISR_MAC_TX 0x800000 | |
291 | #define ISR_DIS_SMB 0x20000000 | |
292 | #define ISR_DIS_DMA 0x40000000 | |
293 | ||
294 | /* Normal Interrupt mask */ | |
295 | #define IMR_NORMAL_MASK (\ | |
296 | ISR_SMB |\ | |
297 | ISR_GPHY |\ | |
298 | ISR_PHY_LINKDOWN|\ | |
299 | ISR_DMAR_TO_RST |\ | |
300 | ISR_DMAW_TO_RST |\ | |
301 | ISR_CMB_TX |\ | |
302 | ISR_CMB_RX) | |
303 | ||
304 | /* Debug Interrupt Mask (enable all interrupt) */ | |
305 | #define IMR_DEBUG_MASK (\ | |
306 | ISR_SMB |\ | |
307 | ISR_TIMER |\ | |
308 | ISR_MANUAL |\ | |
309 | ISR_RXF_OV |\ | |
310 | ISR_RFD_UNRUN |\ | |
311 | ISR_RRD_OV |\ | |
312 | ISR_TXF_UNRUN |\ | |
313 | ISR_LINK |\ | |
314 | ISR_CMB_TX |\ | |
315 | ISR_CMB_RX |\ | |
316 | ISR_RX_PKT |\ | |
317 | ISR_TX_PKT |\ | |
318 | ISR_MAC_RX |\ | |
319 | ISR_MAC_TX) | |
320 | ||
321 | #define MEDIA_TYPE_1000M_FULL 1 | |
322 | #define MEDIA_TYPE_100M_FULL 2 | |
323 | #define MEDIA_TYPE_100M_HALF 3 | |
324 | #define MEDIA_TYPE_10M_FULL 4 | |
325 | #define MEDIA_TYPE_10M_HALF 5 | |
326 | ||
327 | #define AUTONEG_ADVERTISE_SPEED_DEFAULT 0x002F /* All but 1000-Half */ | |
328 | ||
329 | #define MAX_JUMBO_FRAME_SIZE 10240 | |
330 | ||
331 | #define ATL1_EEDUMP_LEN 48 | |
332 | ||
333 | /* Statistics counters collected by the MAC */ | |
334 | struct stats_msg_block { | |
335 | /* rx */ | |
336 | u32 rx_ok; /* good RX packets */ | |
337 | u32 rx_bcast; /* good RX broadcast packets */ | |
338 | u32 rx_mcast; /* good RX multicast packets */ | |
339 | u32 rx_pause; /* RX pause frames */ | |
340 | u32 rx_ctrl; /* RX control packets other than pause frames */ | |
341 | u32 rx_fcs_err; /* RX packets with bad FCS */ | |
342 | u32 rx_len_err; /* RX packets with length != actual size */ | |
343 | u32 rx_byte_cnt; /* good bytes received. FCS is NOT included */ | |
344 | u32 rx_runt; /* RX packets < 64 bytes with good FCS */ | |
345 | u32 rx_frag; /* RX packets < 64 bytes with bad FCS */ | |
346 | u32 rx_sz_64; /* 64 byte RX packets */ | |
347 | u32 rx_sz_65_127; | |
348 | u32 rx_sz_128_255; | |
349 | u32 rx_sz_256_511; | |
350 | u32 rx_sz_512_1023; | |
351 | u32 rx_sz_1024_1518; | |
352 | u32 rx_sz_1519_max; /* 1519 byte to MTU RX packets */ | |
353 | u32 rx_sz_ov; /* truncated RX packets > MTU */ | |
354 | u32 rx_rxf_ov; /* frames dropped due to RX FIFO overflow */ | |
355 | u32 rx_rrd_ov; /* frames dropped due to RRD overflow */ | |
356 | u32 rx_align_err; /* alignment errors */ | |
357 | u32 rx_bcast_byte_cnt; /* RX broadcast bytes, excluding FCS */ | |
358 | u32 rx_mcast_byte_cnt; /* RX multicast bytes, excluding FCS */ | |
359 | u32 rx_err_addr; /* packets dropped due to address filtering */ | |
360 | ||
361 | /* tx */ | |
362 | u32 tx_ok; /* good TX packets */ | |
363 | u32 tx_bcast; /* good TX broadcast packets */ | |
364 | u32 tx_mcast; /* good TX multicast packets */ | |
365 | u32 tx_pause; /* TX pause frames */ | |
366 | u32 tx_exc_defer; /* TX packets deferred excessively */ | |
367 | u32 tx_ctrl; /* TX control frames, excluding pause frames */ | |
368 | u32 tx_defer; /* TX packets deferred */ | |
369 | u32 tx_byte_cnt; /* bytes transmitted, FCS is NOT included */ | |
370 | u32 tx_sz_64; /* 64 byte TX packets */ | |
371 | u32 tx_sz_65_127; | |
372 | u32 tx_sz_128_255; | |
373 | u32 tx_sz_256_511; | |
374 | u32 tx_sz_512_1023; | |
375 | u32 tx_sz_1024_1518; | |
376 | u32 tx_sz_1519_max; /* 1519 byte to MTU TX packets */ | |
377 | u32 tx_1_col; /* packets TX after a single collision */ | |
378 | u32 tx_2_col; /* packets TX after multiple collisions */ | |
379 | u32 tx_late_col; /* TX packets with late collisions */ | |
380 | u32 tx_abort_col; /* TX packets aborted w/excessive collisions */ | |
381 | u32 tx_underrun; /* TX packets aborted due to TX FIFO underrun | |
382 | * or TRD FIFO underrun */ | |
383 | u32 tx_rd_eop; /* reads beyond the EOP into the next frame | |
384 | * when TRD was not written timely */ | |
385 | u32 tx_len_err; /* TX packets where length != actual size */ | |
386 | u32 tx_trunc; /* TX packets truncated due to size > MTU */ | |
387 | u32 tx_bcast_byte; /* broadcast bytes transmitted, excluding FCS */ | |
388 | u32 tx_mcast_byte; /* multicast bytes transmitted, excluding FCS */ | |
389 | u32 smb_updated; /* 1: SMB Updated. This is used by software to | |
390 | * indicate the statistics update. Software | |
391 | * should clear this bit after retrieving the | |
392 | * statistics information. */ | |
393 | }; | |
394 | ||
395 | /* Coalescing Message Block */ | |
396 | struct coals_msg_block { | |
397 | u32 int_stats; /* interrupt status */ | |
398 | u16 rrd_prod_idx; /* TRD Producer Index. */ | |
399 | u16 rfd_cons_idx; /* RFD Consumer Index. */ | |
400 | u16 update; /* Selene sets this bit every time it DMAs the | |
401 | * CMB to host memory. Software should clear | |
402 | * this bit when CMB info is processed. */ | |
403 | u16 tpd_cons_idx; /* TPD Consumer Index. */ | |
404 | }; | |
405 | ||
406 | /* RRD descriptor */ | |
407 | struct rx_return_desc { | |
408 | u8 num_buf; /* Number of RFD buffers used by the received packet */ | |
409 | u8 resved; | |
410 | u16 buf_indx; /* RFD Index of the first buffer */ | |
411 | union { | |
412 | u32 valid; | |
413 | struct { | |
414 | u16 rx_chksum; | |
415 | u16 pkt_size; | |
416 | } xsum_sz; | |
417 | } xsz; | |
418 | ||
419 | u16 pkt_flg; /* Packet flags */ | |
420 | u16 err_flg; /* Error flags */ | |
421 | u16 resved2; | |
422 | u16 vlan_tag; /* VLAN TAG */ | |
423 | }; | |
424 | ||
425 | #define PACKET_FLAG_ETH_TYPE 0x0080 | |
426 | #define PACKET_FLAG_VLAN_INS 0x0100 | |
427 | #define PACKET_FLAG_ERR 0x0200 | |
428 | #define PACKET_FLAG_IPV4 0x0400 | |
429 | #define PACKET_FLAG_UDP 0x0800 | |
430 | #define PACKET_FLAG_TCP 0x1000 | |
431 | #define PACKET_FLAG_BCAST 0x2000 | |
432 | #define PACKET_FLAG_MCAST 0x4000 | |
433 | #define PACKET_FLAG_PAUSE 0x8000 | |
434 | ||
435 | #define ERR_FLAG_CRC 0x0001 | |
436 | #define ERR_FLAG_CODE 0x0002 | |
437 | #define ERR_FLAG_DRIBBLE 0x0004 | |
438 | #define ERR_FLAG_RUNT 0x0008 | |
439 | #define ERR_FLAG_OV 0x0010 | |
440 | #define ERR_FLAG_TRUNC 0x0020 | |
441 | #define ERR_FLAG_IP_CHKSUM 0x0040 | |
442 | #define ERR_FLAG_L4_CHKSUM 0x0080 | |
443 | #define ERR_FLAG_LEN 0x0100 | |
444 | #define ERR_FLAG_DES_ADDR 0x0200 | |
445 | ||
446 | /* RFD descriptor */ | |
447 | struct rx_free_desc { | |
448 | __le64 buffer_addr; /* Address of the descriptor's data buffer */ | |
449 | __le16 buf_len; /* Size of the receive buffer in host memory */ | |
450 | u16 coalese; /* Update consumer index to host after the | |
451 | * reception of this frame */ | |
452 | /* __attribute__ ((packed)) is required */ | |
453 | } __attribute__ ((packed)); | |
454 | ||
455 | /* tsopu defines */ | |
456 | #define TSO_PARAM_BUFLEN_MASK 0x3FFF | |
457 | #define TSO_PARAM_BUFLEN_SHIFT 0 | |
458 | #define TSO_PARAM_DMAINT_MASK 0x0001 | |
459 | #define TSO_PARAM_DMAINT_SHIFT 14 | |
460 | #define TSO_PARAM_PKTNT_MASK 0x0001 | |
461 | #define TSO_PARAM_PKTINT_SHIFT 15 | |
462 | #define TSO_PARAM_VLANTAG_MASK 0xFFFF | |
463 | #define TSO_PARAM_VLAN_SHIFT 16 | |
464 | ||
465 | /* tsopl defines */ | |
466 | #define TSO_PARAM_EOP_MASK 0x0001 | |
467 | #define TSO_PARAM_EOP_SHIFT 0 | |
468 | #define TSO_PARAM_COALESCE_MASK 0x0001 | |
469 | #define TSO_PARAM_COALESCE_SHIFT 1 | |
470 | #define TSO_PARAM_INSVLAG_MASK 0x0001 | |
471 | #define TSO_PARAM_INSVLAG_SHIFT 2 | |
472 | #define TSO_PARAM_CUSTOMCKSUM_MASK 0x0001 | |
473 | #define TSO_PARAM_CUSTOMCKSUM_SHIFT 3 | |
474 | #define TSO_PARAM_SEGMENT_MASK 0x0001 | |
475 | #define TSO_PARAM_SEGMENT_SHIFT 4 | |
476 | #define TSO_PARAM_IPCKSUM_MASK 0x0001 | |
477 | #define TSO_PARAM_IPCKSUM_SHIFT 5 | |
478 | #define TSO_PARAM_TCPCKSUM_MASK 0x0001 | |
479 | #define TSO_PARAM_TCPCKSUM_SHIFT 6 | |
480 | #define TSO_PARAM_UDPCKSUM_MASK 0x0001 | |
481 | #define TSO_PARAM_UDPCKSUM_SHIFT 7 | |
482 | #define TSO_PARAM_VLANTAGGED_MASK 0x0001 | |
483 | #define TSO_PARAM_VLANTAGGED_SHIFT 8 | |
484 | #define TSO_PARAM_ETHTYPE_MASK 0x0001 | |
485 | #define TSO_PARAM_ETHTYPE_SHIFT 9 | |
486 | #define TSO_PARAM_IPHL_MASK 0x000F | |
487 | #define TSO_PARAM_IPHL_SHIFT 10 | |
488 | #define TSO_PARAM_TCPHDRLEN_MASK 0x000F | |
489 | #define TSO_PARAM_TCPHDRLEN_SHIFT 14 | |
490 | #define TSO_PARAM_HDRFLAG_MASK 0x0001 | |
491 | #define TSO_PARAM_HDRFLAG_SHIFT 18 | |
492 | #define TSO_PARAM_MSS_MASK 0x1FFF | |
493 | #define TSO_PARAM_MSS_SHIFT 19 | |
494 | ||
495 | /* csumpu defines */ | |
496 | #define CSUM_PARAM_BUFLEN_MASK 0x3FFF | |
497 | #define CSUM_PARAM_BUFLEN_SHIFT 0 | |
498 | #define CSUM_PARAM_DMAINT_MASK 0x0001 | |
499 | #define CSUM_PARAM_DMAINT_SHIFT 14 | |
500 | #define CSUM_PARAM_PKTINT_MASK 0x0001 | |
501 | #define CSUM_PARAM_PKTINT_SHIFT 15 | |
502 | #define CSUM_PARAM_VALANTAG_MASK 0xFFFF | |
503 | #define CSUM_PARAM_VALAN_SHIFT 16 | |
504 | ||
505 | /* csumpl defines*/ | |
506 | #define CSUM_PARAM_EOP_MASK 0x0001 | |
507 | #define CSUM_PARAM_EOP_SHIFT 0 | |
508 | #define CSUM_PARAM_COALESCE_MASK 0x0001 | |
509 | #define CSUM_PARAM_COALESCE_SHIFT 1 | |
510 | #define CSUM_PARAM_INSVLAG_MASK 0x0001 | |
511 | #define CSUM_PARAM_INSVLAG_SHIFT 2 | |
512 | #define CSUM_PARAM_CUSTOMCKSUM_MASK 0x0001 | |
513 | #define CSUM_PARAM_CUSTOMCKSUM_SHIFT 3 | |
514 | #define CSUM_PARAM_SEGMENT_MASK 0x0001 | |
515 | #define CSUM_PARAM_SEGMENT_SHIFT 4 | |
516 | #define CSUM_PARAM_IPCKSUM_MASK 0x0001 | |
517 | #define CSUM_PARAM_IPCKSUM_SHIFT 5 | |
518 | #define CSUM_PARAM_TCPCKSUM_MASK 0x0001 | |
519 | #define CSUM_PARAM_TCPCKSUM_SHIFT 6 | |
520 | #define CSUM_PARAM_UDPCKSUM_MASK 0x0001 | |
521 | #define CSUM_PARAM_UDPCKSUM_SHIFT 7 | |
522 | #define CSUM_PARAM_VLANTAGGED_MASK 0x0001 | |
523 | #define CSUM_PARAM_VLANTAGGED_SHIFT 8 | |
524 | #define CSUM_PARAM_ETHTYPE_MASK 0x0001 | |
525 | #define CSUM_PARAM_ETHTYPE_SHIFT 9 | |
526 | #define CSUM_PARAM_IPHL_MASK 0x000F | |
527 | #define CSUM_PARAM_IPHL_SHIFT 10 | |
528 | #define CSUM_PARAM_PLOADOFFSET_MASK 0x00FF | |
529 | #define CSUM_PARAM_PLOADOFFSET_SHIFT 16 | |
530 | #define CSUM_PARAM_XSUMOFFSET_MASK 0x00FF | |
531 | #define CSUM_PARAM_XSUMOFFSET_SHIFT 24 | |
532 | ||
533 | /* TPD descriptor */ | |
534 | struct tso_param { | |
535 | /* The order of these declarations is important -- don't change it */ | |
536 | u32 tsopu; /* tso_param upper word */ | |
537 | u32 tsopl; /* tso_param lower word */ | |
538 | }; | |
539 | ||
540 | struct csum_param { | |
541 | /* The order of these declarations is important -- don't change it */ | |
542 | u32 csumpu; /* csum_param upper word */ | |
543 | u32 csumpl; /* csum_param lower word */ | |
544 | }; | |
545 | ||
546 | union tpd_descr { | |
547 | u64 data; | |
548 | struct csum_param csum; | |
549 | struct tso_param tso; | |
550 | }; | |
551 | ||
552 | struct tx_packet_desc { | |
553 | __le64 buffer_addr; | |
554 | union tpd_descr desc; | |
555 | }; | |
556 | ||
557 | /* DMA Order Settings */ | |
558 | enum atl1_dma_order { | |
559 | atl1_dma_ord_in = 1, | |
560 | atl1_dma_ord_enh = 2, | |
561 | atl1_dma_ord_out = 4 | |
562 | }; | |
563 | ||
564 | enum atl1_dma_rcb { | |
565 | atl1_rcb_64 = 0, | |
566 | atl1_rcb_128 = 1 | |
567 | }; | |
568 | ||
569 | enum atl1_dma_req_block { | |
570 | atl1_dma_req_128 = 0, | |
571 | atl1_dma_req_256 = 1, | |
572 | atl1_dma_req_512 = 2, | |
573 | atl1_dma_req_1024 = 3, | |
574 | atl1_dma_req_2048 = 4, | |
575 | atl1_dma_req_4096 = 5 | |
576 | }; | |
f3cc28c7 JC |
577 | |
578 | #define ATL1_MAX_INTR 3 | |
2b116145 | 579 | #define ATL1_MAX_TX_BUF_LEN 0x3000 /* 12288 bytes */ |
f3cc28c7 JC |
580 | |
581 | #define ATL1_DEFAULT_TPD 256 | |
582 | #define ATL1_MAX_TPD 1024 | |
583 | #define ATL1_MIN_TPD 64 | |
584 | #define ATL1_DEFAULT_RFD 512 | |
585 | #define ATL1_MIN_RFD 128 | |
586 | #define ATL1_MAX_RFD 2048 | |
c67c9a2f | 587 | #define ATL1_REG_COUNT 1538 |
f3cc28c7 JC |
588 | |
589 | #define ATL1_GET_DESC(R, i, type) (&(((type *)((R)->desc))[i])) | |
590 | #define ATL1_RFD_DESC(R, i) ATL1_GET_DESC(R, i, struct rx_free_desc) | |
591 | #define ATL1_TPD_DESC(R, i) ATL1_GET_DESC(R, i, struct tx_packet_desc) | |
592 | #define ATL1_RRD_DESC(R, i) ATL1_GET_DESC(R, i, struct rx_return_desc) | |
593 | ||
2b116145 JC |
594 | /* |
595 | * atl1_ring_header represents a single, contiguous block of DMA space | |
596 | * mapped for the three descriptor rings (tpd, rfd, rrd) and the two | |
597 | * message blocks (cmb, smb) described below | |
f3cc28c7 | 598 | */ |
2b116145 JC |
599 | struct atl1_ring_header { |
600 | void *desc; /* virtual address */ | |
601 | dma_addr_t dma; /* physical address*/ | |
602 | unsigned int size; /* length in bytes */ | |
603 | }; | |
f3cc28c7 JC |
604 | |
605 | /* | |
2b116145 JC |
606 | * atl1_buffer is wrapper around a pointer to a socket buffer |
607 | * so a DMA handle can be stored along with the skb | |
f3cc28c7 JC |
608 | */ |
609 | struct atl1_buffer { | |
2b116145 JC |
610 | struct sk_buff *skb; /* socket buffer */ |
611 | u16 length; /* rx buffer length */ | |
612 | u16 alloced; /* 1 if skb allocated */ | |
f3cc28c7 JC |
613 | dma_addr_t dma; |
614 | }; | |
615 | ||
2b116145 | 616 | /* transmit packet descriptor (tpd) ring */ |
f3cc28c7 | 617 | struct atl1_tpd_ring { |
2b116145 JC |
618 | void *desc; /* descriptor ring virtual address */ |
619 | dma_addr_t dma; /* descriptor ring physical address */ | |
620 | u16 size; /* descriptor ring length in bytes */ | |
f3cc28c7 JC |
621 | u16 count; /* number of descriptors in the ring */ |
622 | u16 hw_idx; /* hardware index */ | |
623 | atomic_t next_to_clean; | |
624 | atomic_t next_to_use; | |
625 | struct atl1_buffer *buffer_info; | |
626 | }; | |
627 | ||
2b116145 | 628 | /* receive free descriptor (rfd) ring */ |
f3cc28c7 | 629 | struct atl1_rfd_ring { |
2b116145 JC |
630 | void *desc; /* descriptor ring virtual address */ |
631 | dma_addr_t dma; /* descriptor ring physical address */ | |
632 | u16 size; /* descriptor ring length in bytes */ | |
633 | u16 count; /* number of descriptors in the ring */ | |
f3cc28c7 JC |
634 | atomic_t next_to_use; |
635 | u16 next_to_clean; | |
636 | struct atl1_buffer *buffer_info; | |
637 | }; | |
638 | ||
2b116145 | 639 | /* receive return descriptor (rrd) ring */ |
f3cc28c7 | 640 | struct atl1_rrd_ring { |
2b116145 JC |
641 | void *desc; /* descriptor ring virtual address */ |
642 | dma_addr_t dma; /* descriptor ring physical address */ | |
643 | unsigned int size; /* descriptor ring length in bytes */ | |
644 | u16 count; /* number of descriptors in the ring */ | |
f3cc28c7 JC |
645 | u16 next_to_use; |
646 | atomic_t next_to_clean; | |
647 | }; | |
648 | ||
2b116145 | 649 | /* coalescing message block (cmb) */ |
f3cc28c7 JC |
650 | struct atl1_cmb { |
651 | struct coals_msg_block *cmb; | |
652 | dma_addr_t dma; | |
653 | }; | |
654 | ||
2b116145 | 655 | /* statistics message block (smb) */ |
f3cc28c7 JC |
656 | struct atl1_smb { |
657 | struct stats_msg_block *smb; | |
658 | dma_addr_t dma; | |
659 | }; | |
660 | ||
661 | /* Statistics counters */ | |
662 | struct atl1_sft_stats { | |
663 | u64 rx_packets; | |
664 | u64 tx_packets; | |
665 | u64 rx_bytes; | |
666 | u64 tx_bytes; | |
667 | u64 multicast; | |
668 | u64 collisions; | |
669 | u64 rx_errors; | |
670 | u64 rx_length_errors; | |
671 | u64 rx_crc_errors; | |
672 | u64 rx_frame_errors; | |
673 | u64 rx_fifo_errors; | |
674 | u64 rx_missed_errors; | |
675 | u64 tx_errors; | |
676 | u64 tx_fifo_errors; | |
677 | u64 tx_aborted_errors; | |
678 | u64 tx_window_errors; | |
679 | u64 tx_carrier_errors; | |
305282ba JC |
680 | u64 tx_pause; /* TX pause frames */ |
681 | u64 excecol; /* TX packets w/ excessive collisions */ | |
682 | u64 deffer; /* TX packets deferred */ | |
683 | u64 scc; /* packets TX after a single collision */ | |
684 | u64 mcc; /* packets TX after multiple collisions */ | |
685 | u64 latecol; /* TX packets w/ late collisions */ | |
686 | u64 tx_underun; /* TX packets aborted due to TX FIFO underrun | |
687 | * or TRD FIFO underrun */ | |
688 | u64 tx_trunc; /* TX packets truncated due to size > MTU */ | |
f3cc28c7 JC |
689 | u64 rx_pause; /* num Pause packets received. */ |
690 | u64 rx_rrd_ov; | |
691 | u64 rx_trunc; | |
692 | }; | |
693 | ||
2b116145 | 694 | /* hardware structure */ |
f3cc28c7 JC |
695 | struct atl1_hw { |
696 | u8 __iomem *hw_addr; | |
697 | struct atl1_adapter *back; | |
698 | enum atl1_dma_order dma_ord; | |
699 | enum atl1_dma_rcb rcb_value; | |
700 | enum atl1_dma_req_block dmar_block; | |
701 | enum atl1_dma_req_block dmaw_block; | |
702 | u8 preamble_len; | |
305282ba | 703 | u8 max_retry; |
2b116145 JC |
704 | u8 jam_ipg; /* IPG to start JAM for collision based flow |
705 | * control in half-duplex mode. In units of | |
706 | * 8-bit time */ | |
707 | u8 ipgt; /* Desired back to back inter-packet gap. | |
708 | * The default is 96-bit time */ | |
709 | u8 min_ifg; /* Minimum number of IFG to enforce in between | |
710 | * receive frames. Frame gap below such IFP | |
711 | * is dropped */ | |
f3cc28c7 JC |
712 | u8 ipgr1; /* 64bit Carrier-Sense window */ |
713 | u8 ipgr2; /* 96-bit IPG window */ | |
2b116145 JC |
714 | u8 tpd_burst; /* Number of TPD to prefetch in cache-aligned |
715 | * burst. Each TPD is 16 bytes long */ | |
716 | u8 rfd_burst; /* Number of RFD to prefetch in cache-aligned | |
717 | * burst. Each RFD is 12 bytes long */ | |
f3cc28c7 | 718 | u8 rfd_fetch_gap; |
2b116145 JC |
719 | u8 rrd_burst; /* Threshold number of RRDs that can be retired |
720 | * in a burst. Each RRD is 16 bytes long */ | |
f3cc28c7 JC |
721 | u8 tpd_fetch_th; |
722 | u8 tpd_fetch_gap; | |
723 | u16 tx_jumbo_task_th; | |
2b116145 JC |
724 | u16 txf_burst; /* Number of data bytes to read in a cache- |
725 | * aligned burst. Each SRAM entry is 8 bytes */ | |
726 | u16 rx_jumbo_th; /* Jumbo packet size for non-VLAN packet. VLAN | |
727 | * packets should add 4 bytes */ | |
f3cc28c7 | 728 | u16 rx_jumbo_lkah; |
2b116145 JC |
729 | u16 rrd_ret_timer; /* RRD retirement timer. Decrement by 1 after |
730 | * every 512ns passes. */ | |
f3cc28c7 JC |
731 | u16 lcol; /* Collision Window */ |
732 | ||
733 | u16 cmb_tpd; | |
734 | u16 cmb_rrd; | |
735 | u16 cmb_rx_timer; | |
736 | u16 cmb_tx_timer; | |
737 | u32 smb_timer; | |
738 | u16 media_type; | |
739 | u16 autoneg_advertised; | |
f3cc28c7 JC |
740 | |
741 | u16 mii_autoneg_adv_reg; | |
742 | u16 mii_1000t_ctrl_reg; | |
743 | ||
f3cc28c7 JC |
744 | u32 max_frame_size; |
745 | u32 min_frame_size; | |
f3cc28c7 JC |
746 | |
747 | u16 dev_rev; | |
f3cc28c7 JC |
748 | |
749 | /* spi flash */ | |
750 | u8 flash_vendor; | |
751 | ||
f3cc28c7 JC |
752 | u8 mac_addr[ETH_ALEN]; |
753 | u8 perm_mac_addr[ETH_ALEN]; | |
754 | ||
f3cc28c7 JC |
755 | bool phy_configured; |
756 | }; | |
757 | ||
758 | struct atl1_adapter { | |
f3cc28c7 JC |
759 | struct net_device *netdev; |
760 | struct pci_dev *pdev; | |
761 | struct net_device_stats net_stats; | |
762 | struct atl1_sft_stats soft_stats; | |
f3cc28c7 JC |
763 | struct vlan_group *vlgrp; |
764 | u32 rx_buffer_len; | |
765 | u32 wol; | |
766 | u16 link_speed; | |
767 | u16 link_duplex; | |
768 | spinlock_t lock; | |
f3cc28c7 JC |
769 | struct work_struct tx_timeout_task; |
770 | struct work_struct link_chg_task; | |
771 | struct work_struct pcie_dma_to_rst_task; | |
772 | struct timer_list watchdog_timer; | |
773 | struct timer_list phy_config_timer; | |
774 | bool phy_timer_pending; | |
775 | ||
2b116145 | 776 | /* all descriptor rings' memory */ |
f3cc28c7 JC |
777 | struct atl1_ring_header ring_header; |
778 | ||
779 | /* TX */ | |
780 | struct atl1_tpd_ring tpd_ring; | |
781 | spinlock_t mb_lock; | |
782 | ||
783 | /* RX */ | |
784 | struct atl1_rfd_ring rfd_ring; | |
785 | struct atl1_rrd_ring rrd_ring; | |
786 | u64 hw_csum_err; | |
787 | u64 hw_csum_good; | |
788 | ||
305282ba JC |
789 | u16 imt; /* interrupt moderator timer (2us resolution) */ |
790 | u16 ict; /* interrupt clear timer (2us resolution */ | |
791 | struct mii_if_info mii; /* MII interface info */ | |
f3cc28c7 | 792 | |
305282ba | 793 | u32 bd_number; /* board number */ |
f3cc28c7 JC |
794 | bool pci_using_64; |
795 | struct atl1_hw hw; | |
796 | struct atl1_smb smb; | |
797 | struct atl1_cmb cmb; | |
f3cc28c7 JC |
798 | }; |
799 | ||
305282ba | 800 | #endif /* ATL1_H */ |