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[deliverable/linux.git] / drivers / net / atlx / atl2.c
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452c1ce2
CS		 1/*
2 * Copyright(c) 2006 - 2007 Atheros Corporation. All rights reserved.
3 * Copyright(c) 2007 - 2008 Chris Snook <csnook@redhat.com>
4 *
5 * Derived from Intel e1000 driver
6 * Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the Free
10 * Software Foundation; either version 2 of the License, or (at your option)
11 * any later version.
12 *
13 * This program is distributed in the hope that it will be useful, but WITHOUT
14 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 * more details.
17 *
18 * You should have received a copy of the GNU General Public License along with
19 * this program; if not, write to the Free Software Foundation, Inc., 59
20 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
21 */
22
23#include <asm/atomic.h>
24#include <linux/crc32.h>
25#include <linux/dma-mapping.h>
26#include <linux/etherdevice.h>
27#include <linux/ethtool.h>
28#include <linux/hardirq.h>
29#include <linux/if_vlan.h>
30#include <linux/in.h>
31#include <linux/interrupt.h>
32#include <linux/ip.h>
33#include <linux/irqflags.h>
34#include <linux/irqreturn.h>
35#include <linux/mii.h>
36#include <linux/net.h>
37#include <linux/netdevice.h>
38#include <linux/pci.h>
39#include <linux/pci_ids.h>
40#include <linux/pm.h>
41#include <linux/skbuff.h>
5a0e3ad6 42#include <linux/slab.h>
452c1ce2
CS		 43#include <linux/spinlock.h>
44#include <linux/string.h>
45#include <linux/tcp.h>
46#include <linux/timer.h>
47#include <linux/types.h>
48#include <linux/workqueue.h>
49
50#include "atl2.h"
51
52#define ATL2_DRV_VERSION "2.2.3"
53
f27e21a8 54static const char atl2_driver_name[] = "atl2";
452c1ce2 55static const char atl2_driver_string[] = "Atheros(R) L2 Ethernet Driver";
f27e21a8
SH		 56static const char atl2_copyright[] = "Copyright (c) 2007 Atheros Corporation.";
57static const char atl2_driver_version[] = ATL2_DRV_VERSION;
452c1ce2
CS		 58
59MODULE_AUTHOR("Atheros Corporation <xiong.huang@atheros.com>, Chris Snook <csnook@redhat.com>");
60MODULE_DESCRIPTION("Atheros Fast Ethernet Network Driver");
61MODULE_LICENSE("GPL");
62MODULE_VERSION(ATL2_DRV_VERSION);
63
64/*
65 * atl2_pci_tbl - PCI Device ID Table
66 */
a3aa1884 67static DEFINE_PCI_DEVICE_TABLE(atl2_pci_tbl) = {
452c1ce2
CS		 68 {PCI_DEVICE(PCI_VENDOR_ID_ATTANSIC, PCI_DEVICE_ID_ATTANSIC_L2)},
69 /* required last entry */
70 {0,}
71};
72MODULE_DEVICE_TABLE(pci, atl2_pci_tbl);
73
74static void atl2_set_ethtool_ops(struct net_device *netdev);
75
76static void atl2_check_options(struct atl2_adapter *adapter);
77
78/*
79 * atl2_sw_init - Initialize general software structures (struct atl2_adapter)
80 * @adapter: board private structure to initialize
81 *
82 * atl2_sw_init initializes the Adapter private data structure.
83 * Fields are initialized based on PCI device information and
84 * OS network device settings (MTU size).
85 */
86static int __devinit atl2_sw_init(struct atl2_adapter *adapter)
87{
88 struct atl2_hw *hw = &adapter->hw;
89 struct pci_dev *pdev = adapter->pdev;
90
91 /* PCI config space info */
92 hw->vendor_id = pdev->vendor;
93 hw->device_id = pdev->device;
94 hw->subsystem_vendor_id = pdev->subsystem_vendor;
95 hw->subsystem_id = pdev->subsystem_device;
ff938e43 96 hw->revision_id = pdev->revision;
452c1ce2 97
452c1ce2
CS		 98 pci_read_config_word(pdev, PCI_COMMAND, &hw->pci_cmd_word);
99
100 adapter->wol = 0;
101 adapter->ict = 50000; /* ~100ms */
102 adapter->link_speed = SPEED_0; /* hardware init */
103 adapter->link_duplex = FULL_DUPLEX;
104
105 hw->phy_configured = false;
106 hw->preamble_len = 7;
107 hw->ipgt = 0x60;
108 hw->min_ifg = 0x50;
109 hw->ipgr1 = 0x40;
110 hw->ipgr2 = 0x60;
111 hw->retry_buf = 2;
112 hw->max_retry = 0xf;
113 hw->lcol = 0x37;
114 hw->jam_ipg = 7;
115 hw->fc_rxd_hi = 0;
116 hw->fc_rxd_lo = 0;
117 hw->max_frame_size = adapter->netdev->mtu;
118
119 spin_lock_init(&adapter->stats_lock);
452c1ce2
CS		 120
121 set_bit(__ATL2_DOWN, &adapter->flags);
122
123 return 0;
124}
125
126/*
127 * atl2_set_multi - Multicast and Promiscuous mode set
128 * @netdev: network interface device structure
129 *
130 * The set_multi entry point is called whenever the multicast address
131 * list or the network interface flags are updated. This routine is
132 * responsible for configuring the hardware for proper multicast,
133 * promiscuous mode, and all-multi behavior.
134 */
135static void atl2_set_multi(struct net_device *netdev)
136{
137 struct atl2_adapter *adapter = netdev_priv(netdev);
138 struct atl2_hw *hw = &adapter->hw;
22bedad3 139 struct netdev_hw_addr *ha;
452c1ce2
CS		 140 u32 rctl;
141 u32 hash_value;
142
143 /* Check for Promiscuous and All Multicast modes */
144 rctl = ATL2_READ_REG(hw, REG_MAC_CTRL);
145
146 if (netdev->flags & IFF_PROMISC) {
147 rctl |= MAC_CTRL_PROMIS_EN;
148 } else if (netdev->flags & IFF_ALLMULTI) {
149 rctl |= MAC_CTRL_MC_ALL_EN;
150 rctl &= ~MAC_CTRL_PROMIS_EN;
151 } else
152 rctl &= ~(MAC_CTRL_PROMIS_EN | MAC_CTRL_MC_ALL_EN);
153
154 ATL2_WRITE_REG(hw, REG_MAC_CTRL, rctl);
155
156 /* clear the old settings from the multicast hash table */
157 ATL2_WRITE_REG(hw, REG_RX_HASH_TABLE, 0);
158 ATL2_WRITE_REG_ARRAY(hw, REG_RX_HASH_TABLE, 1, 0);
159
160 /* comoute mc addresses' hash value ,and put it into hash table */
22bedad3
JP		 161 netdev_for_each_mc_addr(ha, netdev) {
162 hash_value = atl2_hash_mc_addr(hw, ha->addr);
452c1ce2
CS		 163 atl2_hash_set(hw, hash_value);
164 }
165}
166
167static void init_ring_ptrs(struct atl2_adapter *adapter)
168{
169 /* Read / Write Ptr Initialize: */
170 adapter->txd_write_ptr = 0;
171 atomic_set(&adapter->txd_read_ptr, 0);
172
173 adapter->rxd_read_ptr = 0;
174 adapter->rxd_write_ptr = 0;
175
176 atomic_set(&adapter->txs_write_ptr, 0);
177 adapter->txs_next_clear = 0;
178}
179
180/*
181 * atl2_configure - Configure Transmit&Receive Unit after Reset
182 * @adapter: board private structure
183 *
184 * Configure the Tx /Rx unit of the MAC after a reset.
185 */
186static int atl2_configure(struct atl2_adapter *adapter)
187{
188 struct atl2_hw *hw = &adapter->hw;
189 u32 value;
190
191 /* clear interrupt status */
192 ATL2_WRITE_REG(&adapter->hw, REG_ISR, 0xffffffff);
193
194 /* set MAC Address */
195 value = (((u32)hw->mac_addr[2]) << 24) |
196 (((u32)hw->mac_addr[3]) << 16) |
197 (((u32)hw->mac_addr[4]) << 8) |
198 (((u32)hw->mac_addr[5]));
199 ATL2_WRITE_REG(hw, REG_MAC_STA_ADDR, value);
200 value = (((u32)hw->mac_addr[0]) << 8) |
201 (((u32)hw->mac_addr[1]));
202 ATL2_WRITE_REG(hw, (REG_MAC_STA_ADDR+4), value);
203
204 /* HI base address */
205 ATL2_WRITE_REG(hw, REG_DESC_BASE_ADDR_HI,
206 (u32)((adapter->ring_dma & 0xffffffff00000000ULL) >> 32));
207
208 /* LO base address */
209 ATL2_WRITE_REG(hw, REG_TXD_BASE_ADDR_LO,
210 (u32)(adapter->txd_dma & 0x00000000ffffffffULL));
211 ATL2_WRITE_REG(hw, REG_TXS_BASE_ADDR_LO,
212 (u32)(adapter->txs_dma & 0x00000000ffffffffULL));
213 ATL2_WRITE_REG(hw, REG_RXD_BASE_ADDR_LO,
214 (u32)(adapter->rxd_dma & 0x00000000ffffffffULL));
215
216 /* element count */
217 ATL2_WRITE_REGW(hw, REG_TXD_MEM_SIZE, (u16)(adapter->txd_ring_size/4));
218 ATL2_WRITE_REGW(hw, REG_TXS_MEM_SIZE, (u16)adapter->txs_ring_size);
219 ATL2_WRITE_REGW(hw, REG_RXD_BUF_NUM, (u16)adapter->rxd_ring_size);
220
221 /* config Internal SRAM */
222/*
223 ATL2_WRITE_REGW(hw, REG_SRAM_TXRAM_END, sram_tx_end);
224 ATL2_WRITE_REGW(hw, REG_SRAM_TXRAM_END, sram_rx_end);
225*/
226
227 /* config IPG/IFG */
228 value = (((u32)hw->ipgt & MAC_IPG_IFG_IPGT_MASK) <<
229 MAC_IPG_IFG_IPGT_SHIFT) |
230 (((u32)hw->min_ifg & MAC_IPG_IFG_MIFG_MASK) <<
231 MAC_IPG_IFG_MIFG_SHIFT) |
232 (((u32)hw->ipgr1 & MAC_IPG_IFG_IPGR1_MASK) <<
233 MAC_IPG_IFG_IPGR1_SHIFT)|
234 (((u32)hw->ipgr2 & MAC_IPG_IFG_IPGR2_MASK) <<
235 MAC_IPG_IFG_IPGR2_SHIFT);
236 ATL2_WRITE_REG(hw, REG_MAC_IPG_IFG, value);
237
238 /* config Half-Duplex Control */
239 value = ((u32)hw->lcol & MAC_HALF_DUPLX_CTRL_LCOL_MASK) |
240 (((u32)hw->max_retry & MAC_HALF_DUPLX_CTRL_RETRY_MASK) <<
241 MAC_HALF_DUPLX_CTRL_RETRY_SHIFT) |
242 MAC_HALF_DUPLX_CTRL_EXC_DEF_EN |
243 (0xa << MAC_HALF_DUPLX_CTRL_ABEBT_SHIFT) |
244 (((u32)hw->jam_ipg & MAC_HALF_DUPLX_CTRL_JAMIPG_MASK) <<
245 MAC_HALF_DUPLX_CTRL_JAMIPG_SHIFT);
246 ATL2_WRITE_REG(hw, REG_MAC_HALF_DUPLX_CTRL, value);
247
248 /* set Interrupt Moderator Timer */
249 ATL2_WRITE_REGW(hw, REG_IRQ_MODU_TIMER_INIT, adapter->imt);
250 ATL2_WRITE_REG(hw, REG_MASTER_CTRL, MASTER_CTRL_ITIMER_EN);
251
252 /* set Interrupt Clear Timer */
253 ATL2_WRITE_REGW(hw, REG_CMBDISDMA_TIMER, adapter->ict);
254
255 /* set MTU */
256 ATL2_WRITE_REG(hw, REG_MTU, adapter->netdev->mtu +
257 ENET_HEADER_SIZE + VLAN_SIZE + ETHERNET_FCS_SIZE);
258
259 /* 1590 */
260 ATL2_WRITE_REG(hw, REG_TX_CUT_THRESH, 0x177);
261
262 /* flow control */
263 ATL2_WRITE_REGW(hw, REG_PAUSE_ON_TH, hw->fc_rxd_hi);
264 ATL2_WRITE_REGW(hw, REG_PAUSE_OFF_TH, hw->fc_rxd_lo);
265
266 /* Init mailbox */
267 ATL2_WRITE_REGW(hw, REG_MB_TXD_WR_IDX, (u16)adapter->txd_write_ptr);
268 ATL2_WRITE_REGW(hw, REG_MB_RXD_RD_IDX, (u16)adapter->rxd_read_ptr);
269
270 /* enable DMA read/write */
271 ATL2_WRITE_REGB(hw, REG_DMAR, DMAR_EN);
272 ATL2_WRITE_REGB(hw, REG_DMAW, DMAW_EN);
273
274 value = ATL2_READ_REG(&adapter->hw, REG_ISR);
275 if ((value & ISR_PHY_LINKDOWN) != 0)
276 value = 1; /* config failed */
277 else
278 value = 0;
279
280 /* clear all interrupt status */
281 ATL2_WRITE_REG(&adapter->hw, REG_ISR, 0x3fffffff);
282 ATL2_WRITE_REG(&adapter->hw, REG_ISR, 0);
283 return value;
284}
285
286/*
287 * atl2_setup_ring_resources - allocate Tx / RX descriptor resources
288 * @adapter: board private structure
289 *
290 * Return 0 on success, negative on failure
291 */
292static s32 atl2_setup_ring_resources(struct atl2_adapter *adapter)
293{
294 struct pci_dev *pdev = adapter->pdev;
295 int size;
296 u8 offset = 0;
297
298 /* real ring DMA buffer */
299 adapter->ring_size = size =
300 adapter->txd_ring_size * 1 + 7 + /* dword align */
301 adapter->txs_ring_size * 4 + 7 + /* dword align */
302 adapter->rxd_ring_size * 1536 + 127; /* 128bytes align */
303
304 adapter->ring_vir_addr = pci_alloc_consistent(pdev, size,
305 &adapter->ring_dma);
306 if (!adapter->ring_vir_addr)
307 return -ENOMEM;
308 memset(adapter->ring_vir_addr, 0, adapter->ring_size);
309
310 /* Init TXD Ring */
311 adapter->txd_dma = adapter->ring_dma ;
312 offset = (adapter->txd_dma & 0x7) ? (8 - (adapter->txd_dma & 0x7)) : 0;
313 adapter->txd_dma += offset;
314 adapter->txd_ring = (struct tx_pkt_header *) (adapter->ring_vir_addr +
315 offset);
316
317 /* Init TXS Ring */
318 adapter->txs_dma = adapter->txd_dma + adapter->txd_ring_size;
319 offset = (adapter->txs_dma & 0x7) ? (8 - (adapter->txs_dma & 0x7)) : 0;
320 adapter->txs_dma += offset;
321 adapter->txs_ring = (struct tx_pkt_status *)
322 (((u8 *)adapter->txd_ring) + (adapter->txd_ring_size + offset));
323
324 /* Init RXD Ring */
325 adapter->rxd_dma = adapter->txs_dma + adapter->txs_ring_size * 4;
326 offset = (adapter->rxd_dma & 127) ?
327 (128 - (adapter->rxd_dma & 127)) : 0;
328 if (offset > 7)
329 offset -= 8;
330 else
331 offset += (128 - 8);
332
333 adapter->rxd_dma += offset;
334 adapter->rxd_ring = (struct rx_desc *) (((u8 *)adapter->txs_ring) +
335 (adapter->txs_ring_size * 4 + offset));
336
337/*
338 * Read / Write Ptr Initialize:
339 * init_ring_ptrs(adapter);
340 */
341 return 0;
342}
343
344/*
345 * atl2_irq_enable - Enable default interrupt generation settings
346 * @adapter: board private structure
347 */
348static inline void atl2_irq_enable(struct atl2_adapter *adapter)
349{
350 ATL2_WRITE_REG(&adapter->hw, REG_IMR, IMR_NORMAL_MASK);
351 ATL2_WRITE_FLUSH(&adapter->hw);
352}
353
354/*
355 * atl2_irq_disable - Mask off interrupt generation on the NIC
356 * @adapter: board private structure
357 */
358static inline void atl2_irq_disable(struct atl2_adapter *adapter)
359{
360 ATL2_WRITE_REG(&adapter->hw, REG_IMR, 0);
361 ATL2_WRITE_FLUSH(&adapter->hw);
362 synchronize_irq(adapter->pdev->irq);
363}
364
365#ifdef NETIF_F_HW_VLAN_TX
366static void atl2_vlan_rx_register(struct net_device *netdev,
367 struct vlan_group *grp)
368{
369 struct atl2_adapter *adapter = netdev_priv(netdev);
370 u32 ctrl;
371
372 atl2_irq_disable(adapter);
373 adapter->vlgrp = grp;
374
375 if (grp) {
376 /* enable VLAN tag insert/strip */
377 ctrl = ATL2_READ_REG(&adapter->hw, REG_MAC_CTRL);
378 ctrl |= MAC_CTRL_RMV_VLAN;
379 ATL2_WRITE_REG(&adapter->hw, REG_MAC_CTRL, ctrl);
380 } else {
381 /* disable VLAN tag insert/strip */
382 ctrl = ATL2_READ_REG(&adapter->hw, REG_MAC_CTRL);
383 ctrl &= ~MAC_CTRL_RMV_VLAN;
384 ATL2_WRITE_REG(&adapter->hw, REG_MAC_CTRL, ctrl);
385 }
386
387 atl2_irq_enable(adapter);
388}
389
390static void atl2_restore_vlan(struct atl2_adapter *adapter)
391{
392 atl2_vlan_rx_register(adapter->netdev, adapter->vlgrp);
393}
394#endif
395
396static void atl2_intr_rx(struct atl2_adapter *adapter)
397{
398 struct net_device *netdev = adapter->netdev;
399 struct rx_desc *rxd;
400 struct sk_buff *skb;
401
402 do {
403 rxd = adapter->rxd_ring+adapter->rxd_write_ptr;
404 if (!rxd->status.update)
405 break; /* end of tx */
406
407 /* clear this flag at once */
408 rxd->status.update = 0;
409
410 if (rxd->status.ok && rxd->status.pkt_size >= 60) {
411 int rx_size = (int)(rxd->status.pkt_size - 4);
412 /* alloc new buffer */
89d71a66 413 skb = netdev_alloc_skb_ip_align(netdev, rx_size);
452c1ce2
CS		 414 if (NULL == skb) {
415 printk(KERN_WARNING
416 "%s: Mem squeeze, deferring packet.\n",
417 netdev->name);
418 /*
419 * Check that some rx space is free. If not,
420 * free one and mark stats->rx_dropped++.
421 */
02e71731 422 netdev->stats.rx_dropped++;
452c1ce2
CS		 423 break;
424 }
452c1ce2
CS		 425 memcpy(skb->data, rxd->packet, rx_size);
426 skb_put(skb, rx_size);
427 skb->protocol = eth_type_trans(skb, netdev);
428#ifdef NETIF_F_HW_VLAN_TX
429 if (adapter->vlgrp && (rxd->status.vlan)) {
430 u16 vlan_tag = (rxd->status.vtag>>4) |
431 ((rxd->status.vtag&7) << 13) |
432 ((rxd->status.vtag&8) << 9);
433 vlan_hwaccel_rx(skb, adapter->vlgrp, vlan_tag);
434 } else
435#endif
436 netif_rx(skb);
02e71731
SH		 437 netdev->stats.rx_bytes += rx_size;
438 netdev->stats.rx_packets++;
452c1ce2 439 } else {
02e71731 440 netdev->stats.rx_errors++;
452c1ce2
CS		 441
442 if (rxd->status.ok && rxd->status.pkt_size <= 60)
02e71731 443 netdev->stats.rx_length_errors++;
452c1ce2 444 if (rxd->status.mcast)
02e71731 445 netdev->stats.multicast++;
452c1ce2 446 if (rxd->status.crc)
02e71731 447 netdev->stats.rx_crc_errors++;
452c1ce2 448 if (rxd->status.align)
02e71731 449 netdev->stats.rx_frame_errors++;
452c1ce2
CS		 450 }
451
452 /* advance write ptr */
453 if (++adapter->rxd_write_ptr == adapter->rxd_ring_size)
454 adapter->rxd_write_ptr = 0;
455 } while (1);
456
457 /* update mailbox? */
458 adapter->rxd_read_ptr = adapter->rxd_write_ptr;
459 ATL2_WRITE_REGW(&adapter->hw, REG_MB_RXD_RD_IDX, adapter->rxd_read_ptr);
460}
461
462static void atl2_intr_tx(struct atl2_adapter *adapter)
463{
02e71731 464 struct net_device *netdev = adapter->netdev;
452c1ce2
CS		 465 u32 txd_read_ptr;
466 u32 txs_write_ptr;
467 struct tx_pkt_status *txs;
468 struct tx_pkt_header *txph;
469 int free_hole = 0;
470
471 do {
472 txs_write_ptr = (u32) atomic_read(&adapter->txs_write_ptr);
473 txs = adapter->txs_ring + txs_write_ptr;
474 if (!txs->update)
475 break; /* tx stop here */
476
477 free_hole = 1;
478 txs->update = 0;
479
480 if (++txs_write_ptr == adapter->txs_ring_size)
481 txs_write_ptr = 0;
482 atomic_set(&adapter->txs_write_ptr, (int)txs_write_ptr);
483
484 txd_read_ptr = (u32) atomic_read(&adapter->txd_read_ptr);
485 txph = (struct tx_pkt_header *)
486 (((u8 *)adapter->txd_ring) + txd_read_ptr);
487
488 if (txph->pkt_size != txs->pkt_size) {
489 struct tx_pkt_status *old_txs = txs;
490 printk(KERN_WARNING
491 "%s: txs packet size not consistent with txd"
492 " txd_:0x%08x, txs_:0x%08x!\n",
493 adapter->netdev->name,
494 *(u32 *)txph, *(u32 *)txs);
495 printk(KERN_WARNING
496 "txd read ptr: 0x%x\n",
497 txd_read_ptr);
498 txs = adapter->txs_ring + txs_write_ptr;
499 printk(KERN_WARNING
500 "txs-behind:0x%08x\n",
501 *(u32 *)txs);
502 if (txs_write_ptr < 2) {
503 txs = adapter->txs_ring +
504 (adapter->txs_ring_size +
505 txs_write_ptr - 2);
506 } else {
507 txs = adapter->txs_ring + (txs_write_ptr - 2);
508 }
509 printk(KERN_WARNING
510 "txs-before:0x%08x\n",
511 *(u32 *)txs);
512 txs = old_txs;
513 }
514
515 /* 4for TPH */
516 txd_read_ptr += (((u32)(txph->pkt_size) + 7) & ~3);
517 if (txd_read_ptr >= adapter->txd_ring_size)
518 txd_read_ptr -= adapter->txd_ring_size;
519
520 atomic_set(&adapter->txd_read_ptr, (int)txd_read_ptr);
521
522 /* tx statistics: */
e2f092ff 523 if (txs->ok) {
02e71731
SH		 524 netdev->stats.tx_bytes += txs->pkt_size;
525 netdev->stats.tx_packets++;
e2f092ff 526 }
452c1ce2 527 else
02e71731 528 netdev->stats.tx_errors++;
452c1ce2
CS		 529
530 if (txs->defer)
02e71731 531 netdev->stats.collisions++;
452c1ce2 532 if (txs->abort_col)
02e71731 533 netdev->stats.tx_aborted_errors++;
452c1ce2 534 if (txs->late_col)
02e71731 535 netdev->stats.tx_window_errors++;
452c1ce2 536 if (txs->underun)
02e71731 537 netdev->stats.tx_fifo_errors++;
452c1ce2
CS		 538 } while (1);
539
540 if (free_hole) {
541 if (netif_queue_stopped(adapter->netdev) &&
542 netif_carrier_ok(adapter->netdev))
543 netif_wake_queue(adapter->netdev);
544 }
545}
546
547static void atl2_check_for_link(struct atl2_adapter *adapter)
548{
549 struct net_device *netdev = adapter->netdev;
550 u16 phy_data = 0;
551
552 spin_lock(&adapter->stats_lock);
553 atl2_read_phy_reg(&adapter->hw, MII_BMSR, &phy_data);
554 atl2_read_phy_reg(&adapter->hw, MII_BMSR, &phy_data);
555 spin_unlock(&adapter->stats_lock);
556
557 /* notify upper layer link down ASAP */
558 if (!(phy_data & BMSR_LSTATUS)) { /* Link Down */
559 if (netif_carrier_ok(netdev)) { /* old link state: Up */
560 printk(KERN_INFO "%s: %s NIC Link is Down\n",
561 atl2_driver_name, netdev->name);
562 adapter->link_speed = SPEED_0;
563 netif_carrier_off(netdev);
564 netif_stop_queue(netdev);
565 }
566 }
567 schedule_work(&adapter->link_chg_task);
568}
569
570static inline void atl2_clear_phy_int(struct atl2_adapter *adapter)
571{
572 u16 phy_data;
573 spin_lock(&adapter->stats_lock);
574 atl2_read_phy_reg(&adapter->hw, 19, &phy_data);
575 spin_unlock(&adapter->stats_lock);
576}
577
578/*
579 * atl2_intr - Interrupt Handler
580 * @irq: interrupt number
581 * @data: pointer to a network interface device structure
582 * @pt_regs: CPU registers structure
583 */
584static irqreturn_t atl2_intr(int irq, void *data)
585{
586 struct atl2_adapter *adapter = netdev_priv(data);
587 struct atl2_hw *hw = &adapter->hw;
588 u32 status;
589
590 status = ATL2_READ_REG(hw, REG_ISR);
591 if (0 == status)
592 return IRQ_NONE;
593
594 /* link event */
595 if (status & ISR_PHY)
596 atl2_clear_phy_int(adapter);
597
598 /* clear ISR status, and Enable CMB DMA/Disable Interrupt */
599 ATL2_WRITE_REG(hw, REG_ISR, status | ISR_DIS_INT);
600
601 /* check if PCIE PHY Link down */
602 if (status & ISR_PHY_LINKDOWN) {
603 if (netif_running(adapter->netdev)) { /* reset MAC */
604 ATL2_WRITE_REG(hw, REG_ISR, 0);
605 ATL2_WRITE_REG(hw, REG_IMR, 0);
606 ATL2_WRITE_FLUSH(hw);
607 schedule_work(&adapter->reset_task);
608 return IRQ_HANDLED;
609 }
610 }
611
612 /* check if DMA read/write error? */
613 if (status & (ISR_DMAR_TO_RST | ISR_DMAW_TO_RST)) {
614 ATL2_WRITE_REG(hw, REG_ISR, 0);
615 ATL2_WRITE_REG(hw, REG_IMR, 0);
616 ATL2_WRITE_FLUSH(hw);
617 schedule_work(&adapter->reset_task);
618 return IRQ_HANDLED;
619 }
620
621 /* link event */
622 if (status & (ISR_PHY | ISR_MANUAL)) {
02e71731 623 adapter->netdev->stats.tx_carrier_errors++;
452c1ce2
CS		 624 atl2_check_for_link(adapter);
625 }
626
627 /* transmit event */
628 if (status & ISR_TX_EVENT)
629 atl2_intr_tx(adapter);
630
631 /* rx exception */
632 if (status & ISR_RX_EVENT)
633 atl2_intr_rx(adapter);
634
635 /* re-enable Interrupt */
636 ATL2_WRITE_REG(&adapter->hw, REG_ISR, 0);
637 return IRQ_HANDLED;
638}
639
640static int atl2_request_irq(struct atl2_adapter *adapter)
641{
642 struct net_device *netdev = adapter->netdev;
643 int flags, err = 0;
644
645 flags = IRQF_SHARED;
452c1ce2
CS		 646 adapter->have_msi = true;
647 err = pci_enable_msi(adapter->pdev);
648 if (err)
649 adapter->have_msi = false;
650
651 if (adapter->have_msi)
652 flags &= ~IRQF_SHARED;
452c1ce2 653
a0607fd3 654 return request_irq(adapter->pdev->irq, atl2_intr, flags, netdev->name,
452c1ce2
CS		 655 netdev);
656}
657
658/*
659 * atl2_free_ring_resources - Free Tx / RX descriptor Resources
660 * @adapter: board private structure
661 *
662 * Free all transmit software resources
663 */
664static void atl2_free_ring_resources(struct atl2_adapter *adapter)
665{
666 struct pci_dev *pdev = adapter->pdev;
667 pci_free_consistent(pdev, adapter->ring_size, adapter->ring_vir_addr,
668 adapter->ring_dma);
669}
670
671/*
672 * atl2_open - Called when a network interface is made active
673 * @netdev: network interface device structure
674 *
675 * Returns 0 on success, negative value on failure
676 *
677 * The open entry point is called when a network interface is made
678 * active by the system (IFF_UP). At this point all resources needed
679 * for transmit and receive operations are allocated, the interrupt
680 * handler is registered with the OS, the watchdog timer is started,
681 * and the stack is notified that the interface is ready.
682 */
683static int atl2_open(struct net_device *netdev)
684{
685 struct atl2_adapter *adapter = netdev_priv(netdev);
686 int err;
687 u32 val;
688
689 /* disallow open during test */
690 if (test_bit(__ATL2_TESTING, &adapter->flags))
691 return -EBUSY;
692
693 /* allocate transmit descriptors */
694 err = atl2_setup_ring_resources(adapter);
695 if (err)
696 return err;
697
698 err = atl2_init_hw(&adapter->hw);
699 if (err) {
700 err = -EIO;
701 goto err_init_hw;
702 }
703
704 /* hardware has been reset, we need to reload some things */
705 atl2_set_multi(netdev);
706 init_ring_ptrs(adapter);
707
708#ifdef NETIF_F_HW_VLAN_TX
709 atl2_restore_vlan(adapter);
710#endif
711
712 if (atl2_configure(adapter)) {
713 err = -EIO;
714 goto err_config;
715 }
716
717 err = atl2_request_irq(adapter);
718 if (err)
719 goto err_req_irq;
720
721 clear_bit(__ATL2_DOWN, &adapter->flags);
722
e053b628 723 mod_timer(&adapter->watchdog_timer, round_jiffies(jiffies + 4*HZ));
452c1ce2
CS		 724
725 val = ATL2_READ_REG(&adapter->hw, REG_MASTER_CTRL);
726 ATL2_WRITE_REG(&adapter->hw, REG_MASTER_CTRL,
727 val | MASTER_CTRL_MANUAL_INT);
728
729 atl2_irq_enable(adapter);
730
731 return 0;
732
733err_init_hw:
734err_req_irq:
735err_config:
736 atl2_free_ring_resources(adapter);
737 atl2_reset_hw(&adapter->hw);
738
739 return err;
740}
741
742static void atl2_down(struct atl2_adapter *adapter)
743{
744 struct net_device *netdev = adapter->netdev;
745
746 /* signal that we're down so the interrupt handler does not
747 * reschedule our watchdog timer */
748 set_bit(__ATL2_DOWN, &adapter->flags);
749
452c1ce2 750 netif_tx_disable(netdev);
452c1ce2
CS		 751
752 /* reset MAC to disable all RX/TX */
753 atl2_reset_hw(&adapter->hw);
754 msleep(1);
755
756 atl2_irq_disable(adapter);
757
758 del_timer_sync(&adapter->watchdog_timer);
759 del_timer_sync(&adapter->phy_config_timer);
760 clear_bit(0, &adapter->cfg_phy);
761
762 netif_carrier_off(netdev);
763 adapter->link_speed = SPEED_0;
764 adapter->link_duplex = -1;
765}
766
767static void atl2_free_irq(struct atl2_adapter *adapter)
768{
769 struct net_device *netdev = adapter->netdev;
770
771 free_irq(adapter->pdev->irq, netdev);
772
773#ifdef CONFIG_PCI_MSI
774 if (adapter->have_msi)
775 pci_disable_msi(adapter->pdev);
776#endif
777}
778
779/*
780 * atl2_close - Disables a network interface
781 * @netdev: network interface device structure
782 *
783 * Returns 0, this is not allowed to fail
784 *
785 * The close entry point is called when an interface is de-activated
786 * by the OS. The hardware is still under the drivers control, but
787 * needs to be disabled. A global MAC reset is issued to stop the
788 * hardware, and all transmit and receive resources are freed.
789 */
790static int atl2_close(struct net_device *netdev)
791{
792 struct atl2_adapter *adapter = netdev_priv(netdev);
793
794 WARN_ON(test_bit(__ATL2_RESETTING, &adapter->flags));
795
796 atl2_down(adapter);
797 atl2_free_irq(adapter);
798 atl2_free_ring_resources(adapter);
799
800 return 0;
801}
802
803static inline int TxsFreeUnit(struct atl2_adapter *adapter)
804{
805 u32 txs_write_ptr = (u32) atomic_read(&adapter->txs_write_ptr);
806
807 return (adapter->txs_next_clear >= txs_write_ptr) ?
808 (int) (adapter->txs_ring_size - adapter->txs_next_clear +
809 txs_write_ptr - 1) :
810 (int) (txs_write_ptr - adapter->txs_next_clear - 1);
811}
812
813static inline int TxdFreeBytes(struct atl2_adapter *adapter)
814{
815 u32 txd_read_ptr = (u32)atomic_read(&adapter->txd_read_ptr);
816
817 return (adapter->txd_write_ptr >= txd_read_ptr) ?
818 (int) (adapter->txd_ring_size - adapter->txd_write_ptr +
819 txd_read_ptr - 1) :
820 (int) (txd_read_ptr - adapter->txd_write_ptr - 1);
821}
822
61357325
SH		 823static netdev_tx_t atl2_xmit_frame(struct sk_buff *skb,
824 struct net_device *netdev)
452c1ce2
CS		 825{
826 struct atl2_adapter *adapter = netdev_priv(netdev);
452c1ce2
CS		 827 struct tx_pkt_header *txph;
828 u32 offset, copy_len;
829 int txs_unused;
830 int txbuf_unused;
831
832 if (test_bit(__ATL2_DOWN, &adapter->flags)) {
833 dev_kfree_skb_any(skb);
834 return NETDEV_TX_OK;
835 }
836
837 if (unlikely(skb->len <= 0)) {
838 dev_kfree_skb_any(skb);
839 return NETDEV_TX_OK;
840 }
841
452c1ce2
CS		 842 txs_unused = TxsFreeUnit(adapter);
843 txbuf_unused = TxdFreeBytes(adapter);
844
845 if (skb->len + sizeof(struct tx_pkt_header) + 4 > txbuf_unused ||
846 txs_unused < 1) {
847 /* not enough resources */
848 netif_stop_queue(netdev);
452c1ce2
CS		 849 return NETDEV_TX_BUSY;
850 }
851
852 offset = adapter->txd_write_ptr;
853
854 txph = (struct tx_pkt_header *) (((u8 *)adapter->txd_ring) + offset);
855
856 *(u32 *)txph = 0;
857 txph->pkt_size = skb->len;
858
859 offset += 4;
860 if (offset >= adapter->txd_ring_size)
861 offset -= adapter->txd_ring_size;
862 copy_len = adapter->txd_ring_size - offset;
863 if (copy_len >= skb->len) {
864 memcpy(((u8 *)adapter->txd_ring) + offset, skb->data, skb->len);
865 offset += ((u32)(skb->len + 3) & ~3);
866 } else {
867 memcpy(((u8 *)adapter->txd_ring)+offset, skb->data, copy_len);
868 memcpy((u8 *)adapter->txd_ring, skb->data+copy_len,
869 skb->len-copy_len);
870 offset = ((u32)(skb->len-copy_len + 3) & ~3);
871 }
872#ifdef NETIF_F_HW_VLAN_TX
eab6d18d 873 if (vlan_tx_tag_present(skb)) {
452c1ce2
CS		 874 u16 vlan_tag = vlan_tx_tag_get(skb);
875 vlan_tag = (vlan_tag << 4) |
876 (vlan_tag >> 13) |
877 ((vlan_tag >> 9) & 0x8);
878 txph->ins_vlan = 1;
879 txph->vlan = vlan_tag;
880 }
881#endif
882 if (offset >= adapter->txd_ring_size)
883 offset -= adapter->txd_ring_size;
884 adapter->txd_write_ptr = offset;
885
886 /* clear txs before send */
887 adapter->txs_ring[adapter->txs_next_clear].update = 0;
888 if (++adapter->txs_next_clear == adapter->txs_ring_size)
889 adapter->txs_next_clear = 0;
890
891 ATL2_WRITE_REGW(&adapter->hw, REG_MB_TXD_WR_IDX,
892 (adapter->txd_write_ptr >> 2));
893
87241840 894 mmiowb();
452c1ce2
CS		 895 dev_kfree_skb_any(skb);
896 return NETDEV_TX_OK;
897}
898
452c1ce2
CS		 899/*
900 * atl2_change_mtu - Change the Maximum Transfer Unit
901 * @netdev: network interface device structure
902 * @new_mtu: new value for maximum frame size
903 *
904 * Returns 0 on success, negative on failure
905 */
906static int atl2_change_mtu(struct net_device *netdev, int new_mtu)
907{
908 struct atl2_adapter *adapter = netdev_priv(netdev);
909 struct atl2_hw *hw = &adapter->hw;
910
911 if ((new_mtu < 40) || (new_mtu > (ETH_DATA_LEN + VLAN_SIZE)))
912 return -EINVAL;
913
914 /* set MTU */
915 if (hw->max_frame_size != new_mtu) {
916 netdev->mtu = new_mtu;
917 ATL2_WRITE_REG(hw, REG_MTU, new_mtu + ENET_HEADER_SIZE +
918 VLAN_SIZE + ETHERNET_FCS_SIZE);
919 }
920
921 return 0;
922}
923
924/*
925 * atl2_set_mac - Change the Ethernet Address of the NIC
926 * @netdev: network interface device structure
927 * @p: pointer to an address structure
928 *
929 * Returns 0 on success, negative on failure
930 */
931static int atl2_set_mac(struct net_device *netdev, void *p)
932{
933 struct atl2_adapter *adapter = netdev_priv(netdev);
934 struct sockaddr *addr = p;
935
936 if (!is_valid_ether_addr(addr->sa_data))
937 return -EADDRNOTAVAIL;
938
939 if (netif_running(netdev))
940 return -EBUSY;
941
942 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
943 memcpy(adapter->hw.mac_addr, addr->sa_data, netdev->addr_len);
944
945 atl2_set_mac_addr(&adapter->hw);
946
947 return 0;
948}
949
950/*
951 * atl2_mii_ioctl -
952 * @netdev:
953 * @ifreq:
954 * @cmd:
955 */
956static int atl2_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
957{
958 struct atl2_adapter *adapter = netdev_priv(netdev);
959 struct mii_ioctl_data *data = if_mii(ifr);
960 unsigned long flags;
961
962 switch (cmd) {
963 case SIOCGMIIPHY:
964 data->phy_id = 0;
965 break;
966 case SIOCGMIIREG:
452c1ce2
CS		 967 spin_lock_irqsave(&adapter->stats_lock, flags);
968 if (atl2_read_phy_reg(&adapter->hw,
969 data->reg_num & 0x1F, &data->val_out)) {
970 spin_unlock_irqrestore(&adapter->stats_lock, flags);
971 return -EIO;
972 }
973 spin_unlock_irqrestore(&adapter->stats_lock, flags);
974 break;
975 case SIOCSMIIREG:
452c1ce2
CS		 976 if (data->reg_num & ~(0x1F))
977 return -EFAULT;
978 spin_lock_irqsave(&adapter->stats_lock, flags);
979 if (atl2_write_phy_reg(&adapter->hw, data->reg_num,
980 data->val_in)) {
981 spin_unlock_irqrestore(&adapter->stats_lock, flags);
982 return -EIO;
983 }
984 spin_unlock_irqrestore(&adapter->stats_lock, flags);
985 break;
986 default:
987 return -EOPNOTSUPP;
988 }
989 return 0;
990}
991
992/*
993 * atl2_ioctl -
994 * @netdev:
995 * @ifreq:
996 * @cmd:
997 */
998static int atl2_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
999{
1000 switch (cmd) {
1001 case SIOCGMIIPHY:
1002 case SIOCGMIIREG:
1003 case SIOCSMIIREG:
1004 return atl2_mii_ioctl(netdev, ifr, cmd);
1005#ifdef ETHTOOL_OPS_COMPAT
1006 case SIOCETHTOOL:
1007 return ethtool_ioctl(ifr);
1008#endif
1009 default:
1010 return -EOPNOTSUPP;
1011 }
1012}
1013
1014/*
1015 * atl2_tx_timeout - Respond to a Tx Hang
1016 * @netdev: network interface device structure
1017 */
1018static void atl2_tx_timeout(struct net_device *netdev)
1019{
1020 struct atl2_adapter *adapter = netdev_priv(netdev);
1021
1022 /* Do the reset outside of interrupt context */
1023 schedule_work(&adapter->reset_task);
1024}
1025
1026/*
1027 * atl2_watchdog - Timer Call-back
1028 * @data: pointer to netdev cast into an unsigned long
1029 */
1030static void atl2_watchdog(unsigned long data)
1031{
1032 struct atl2_adapter *adapter = (struct atl2_adapter *) data;
452c1ce2
CS		 1033
1034 if (!test_bit(__ATL2_DOWN, &adapter->flags)) {
02e71731
SH		 1035 u32 drop_rxd, drop_rxs;
1036 unsigned long flags;
1037
452c1ce2
CS		 1038 spin_lock_irqsave(&adapter->stats_lock, flags);
1039 drop_rxd = ATL2_READ_REG(&adapter->hw, REG_STS_RXD_OV);
1040 drop_rxs = ATL2_READ_REG(&adapter->hw, REG_STS_RXS_OV);
452c1ce2
CS		 1041 spin_unlock_irqrestore(&adapter->stats_lock, flags);
1042
02e71731
SH		 1043 adapter->netdev->stats.rx_over_errors += drop_rxd + drop_rxs;
1044
452c1ce2 1045 /* Reset the timer */
e053b628
SH		 1046 mod_timer(&adapter->watchdog_timer,
1047 round_jiffies(jiffies + 4 * HZ));
452c1ce2
CS		 1048 }
1049}
1050
1051/*
1052 * atl2_phy_config - Timer Call-back
1053 * @data: pointer to netdev cast into an unsigned long
1054 */
1055static void atl2_phy_config(unsigned long data)
1056{
1057 struct atl2_adapter *adapter = (struct atl2_adapter *) data;
1058 struct atl2_hw *hw = &adapter->hw;
1059 unsigned long flags;
1060
1061 spin_lock_irqsave(&adapter->stats_lock, flags);
1062 atl2_write_phy_reg(hw, MII_ADVERTISE, hw->mii_autoneg_adv_reg);
1063 atl2_write_phy_reg(hw, MII_BMCR, MII_CR_RESET | MII_CR_AUTO_NEG_EN |
1064 MII_CR_RESTART_AUTO_NEG);
1065 spin_unlock_irqrestore(&adapter->stats_lock, flags);
1066 clear_bit(0, &adapter->cfg_phy);
1067}
1068
1069static int atl2_up(struct atl2_adapter *adapter)
1070{
1071 struct net_device *netdev = adapter->netdev;
1072 int err = 0;
1073 u32 val;
1074
1075 /* hardware has been reset, we need to reload some things */
1076
1077 err = atl2_init_hw(&adapter->hw);
1078 if (err) {
1079 err = -EIO;
1080 return err;
1081 }
1082
1083 atl2_set_multi(netdev);
1084 init_ring_ptrs(adapter);
1085
1086#ifdef NETIF_F_HW_VLAN_TX
1087 atl2_restore_vlan(adapter);
1088#endif
1089
1090 if (atl2_configure(adapter)) {
1091 err = -EIO;
1092 goto err_up;
1093 }
1094
1095 clear_bit(__ATL2_DOWN, &adapter->flags);
1096
1097 val = ATL2_READ_REG(&adapter->hw, REG_MASTER_CTRL);
1098 ATL2_WRITE_REG(&adapter->hw, REG_MASTER_CTRL, val |
1099 MASTER_CTRL_MANUAL_INT);
1100
1101 atl2_irq_enable(adapter);
1102
1103err_up:
1104 return err;
1105}
1106
1107static void atl2_reinit_locked(struct atl2_adapter *adapter)
1108{
1109 WARN_ON(in_interrupt());
1110 while (test_and_set_bit(__ATL2_RESETTING, &adapter->flags))
1111 msleep(1);
1112 atl2_down(adapter);
1113 atl2_up(adapter);
1114 clear_bit(__ATL2_RESETTING, &adapter->flags);
1115}
1116
1117static void atl2_reset_task(struct work_struct *work)
1118{
1119 struct atl2_adapter *adapter;
1120 adapter = container_of(work, struct atl2_adapter, reset_task);
1121
1122 atl2_reinit_locked(adapter);
1123}
1124
1125static void atl2_setup_mac_ctrl(struct atl2_adapter *adapter)
1126{
1127 u32 value;
1128 struct atl2_hw *hw = &adapter->hw;
1129 struct net_device *netdev = adapter->netdev;
1130
1131 /* Config MAC CTRL Register */
1132 value = MAC_CTRL_TX_EN | MAC_CTRL_RX_EN | MAC_CTRL_MACLP_CLK_PHY;
1133
1134 /* duplex */
1135 if (FULL_DUPLEX == adapter->link_duplex)
1136 value |= MAC_CTRL_DUPLX;
1137
1138 /* flow control */
1139 value |= (MAC_CTRL_TX_FLOW | MAC_CTRL_RX_FLOW);
1140
1141 /* PAD & CRC */
1142 value |= (MAC_CTRL_ADD_CRC | MAC_CTRL_PAD);
1143
1144 /* preamble length */
1145 value |= (((u32)adapter->hw.preamble_len & MAC_CTRL_PRMLEN_MASK) <<
1146 MAC_CTRL_PRMLEN_SHIFT);
1147
1148 /* vlan */
1149 if (adapter->vlgrp)
1150 value |= MAC_CTRL_RMV_VLAN;
1151
1152 /* filter mode */
1153 value |= MAC_CTRL_BC_EN;
1154 if (netdev->flags & IFF_PROMISC)
1155 value |= MAC_CTRL_PROMIS_EN;
1156 else if (netdev->flags & IFF_ALLMULTI)
1157 value |= MAC_CTRL_MC_ALL_EN;
1158
1159 /* half retry buffer */
1160 value |= (((u32)(adapter->hw.retry_buf &
1161 MAC_CTRL_HALF_LEFT_BUF_MASK)) << MAC_CTRL_HALF_LEFT_BUF_SHIFT);
1162
1163 ATL2_WRITE_REG(hw, REG_MAC_CTRL, value);
1164}
1165
1166static int atl2_check_link(struct atl2_adapter *adapter)
1167{
1168 struct atl2_hw *hw = &adapter->hw;
1169 struct net_device *netdev = adapter->netdev;
1170 int ret_val;
1171 u16 speed, duplex, phy_data;
1172 int reconfig = 0;
1173
1174 /* MII_BMSR must read twise */
1175 atl2_read_phy_reg(hw, MII_BMSR, &phy_data);
1176 atl2_read_phy_reg(hw, MII_BMSR, &phy_data);
1177 if (!(phy_data&BMSR_LSTATUS)) { /* link down */
1178 if (netif_carrier_ok(netdev)) { /* old link state: Up */
1179 u32 value;
1180 /* disable rx */
1181 value = ATL2_READ_REG(hw, REG_MAC_CTRL);
1182 value &= ~MAC_CTRL_RX_EN;
1183 ATL2_WRITE_REG(hw, REG_MAC_CTRL, value);
1184 adapter->link_speed = SPEED_0;
1185 netif_carrier_off(netdev);
1186 netif_stop_queue(netdev);
1187 }
1188 return 0;
1189 }
1190
1191 /* Link Up */
1192 ret_val = atl2_get_speed_and_duplex(hw, &speed, &duplex);
1193 if (ret_val)
1194 return ret_val;
1195 switch (hw->MediaType) {
1196 case MEDIA_TYPE_100M_FULL:
1197 if (speed != SPEED_100 || duplex != FULL_DUPLEX)
1198 reconfig = 1;
1199 break;
1200 case MEDIA_TYPE_100M_HALF:
1201 if (speed != SPEED_100 || duplex != HALF_DUPLEX)
1202 reconfig = 1;
1203 break;
1204 case MEDIA_TYPE_10M_FULL:
1205 if (speed != SPEED_10 || duplex != FULL_DUPLEX)
1206 reconfig = 1;
1207 break;
1208 case MEDIA_TYPE_10M_HALF:
1209 if (speed != SPEED_10 || duplex != HALF_DUPLEX)
1210 reconfig = 1;
1211 break;
1212 }
1213 /* link result is our setting */
1214 if (reconfig == 0) {
1215 if (adapter->link_speed != speed ||
1216 adapter->link_duplex != duplex) {
1217 adapter->link_speed = speed;
1218 adapter->link_duplex = duplex;
1219 atl2_setup_mac_ctrl(adapter);
1220 printk(KERN_INFO "%s: %s NIC Link is Up<%d Mbps %s>\n",
1221 atl2_driver_name, netdev->name,
1222 adapter->link_speed,
1223 adapter->link_duplex == FULL_DUPLEX ?
1224 "Full Duplex" : "Half Duplex");
1225 }
1226
1227 if (!netif_carrier_ok(netdev)) { /* Link down -> Up */
1228 netif_carrier_on(netdev);
1229 netif_wake_queue(netdev);
1230 }
1231 return 0;
1232 }
1233
1234 /* change original link status */
1235 if (netif_carrier_ok(netdev)) {
1236 u32 value;
1237 /* disable rx */
1238 value = ATL2_READ_REG(hw, REG_MAC_CTRL);
1239 value &= ~MAC_CTRL_RX_EN;
1240 ATL2_WRITE_REG(hw, REG_MAC_CTRL, value);
1241
1242 adapter->link_speed = SPEED_0;
1243 netif_carrier_off(netdev);
1244 netif_stop_queue(netdev);
1245 }
1246
1247 /* auto-neg, insert timer to re-config phy
1248 * (if interval smaller than 5 seconds, something strange) */
1249 if (!test_bit(__ATL2_DOWN, &adapter->flags)) {
1250 if (!test_and_set_bit(0, &adapter->cfg_phy))
e053b628
SH		 1251 mod_timer(&adapter->phy_config_timer,
1252 round_jiffies(jiffies + 5 * HZ));
452c1ce2
CS		 1253 }
1254
1255 return 0;
1256}
1257
1258/*
1259 * atl2_link_chg_task - deal with link change event Out of interrupt context
1260 * @netdev: network interface device structure
1261 */
1262static void atl2_link_chg_task(struct work_struct *work)
1263{
1264 struct atl2_adapter *adapter;
1265 unsigned long flags;
1266
1267 adapter = container_of(work, struct atl2_adapter, link_chg_task);
1268
1269 spin_lock_irqsave(&adapter->stats_lock, flags);
1270 atl2_check_link(adapter);
1271 spin_unlock_irqrestore(&adapter->stats_lock, flags);
1272}
1273
1274static void atl2_setup_pcicmd(struct pci_dev *pdev)
1275{
1276 u16 cmd;
1277
1278 pci_read_config_word(pdev, PCI_COMMAND, &cmd);
1279
1280 if (cmd & PCI_COMMAND_INTX_DISABLE)
1281 cmd &= ~PCI_COMMAND_INTX_DISABLE;
1282 if (cmd & PCI_COMMAND_IO)
1283 cmd &= ~PCI_COMMAND_IO;
1284 if (0 == (cmd & PCI_COMMAND_MEMORY))
1285 cmd |= PCI_COMMAND_MEMORY;
1286 if (0 == (cmd & PCI_COMMAND_MASTER))
1287 cmd |= PCI_COMMAND_MASTER;
1288 pci_write_config_word(pdev, PCI_COMMAND, cmd);
1289
1290 /*
1291 * some motherboards BIOS(PXE/EFI) driver may set PME
1292 * while they transfer control to OS (Windows/Linux)
1293 * so we should clear this bit before NIC work normally
1294 */
1295 pci_write_config_dword(pdev, REG_PM_CTRLSTAT, 0);
1296}
1297
8d1b1fc9
KH		 1298#ifdef CONFIG_NET_POLL_CONTROLLER
1299static void atl2_poll_controller(struct net_device *netdev)
1300{
1301 disable_irq(netdev->irq);
1302 atl2_intr(netdev->irq, netdev);
1303 enable_irq(netdev->irq);
1304}
1305#endif
1306
825a84d1
SH		 1307
1308static const struct net_device_ops atl2_netdev_ops = {
1309 .ndo_open = atl2_open,
1310 .ndo_stop = atl2_close,
00829823 1311 .ndo_start_xmit = atl2_xmit_frame,
825a84d1
SH		 1312 .ndo_set_multicast_list = atl2_set_multi,
1313 .ndo_validate_addr = eth_validate_addr,
1314 .ndo_set_mac_address = atl2_set_mac,
1315 .ndo_change_mtu = atl2_change_mtu,
1316 .ndo_do_ioctl = atl2_ioctl,
1317 .ndo_tx_timeout = atl2_tx_timeout,
1318 .ndo_vlan_rx_register = atl2_vlan_rx_register,
1319#ifdef CONFIG_NET_POLL_CONTROLLER
1320 .ndo_poll_controller = atl2_poll_controller,
1321#endif
1322};
1323
452c1ce2
CS		 1324/*
1325 * atl2_probe - Device Initialization Routine
1326 * @pdev: PCI device information struct
1327 * @ent: entry in atl2_pci_tbl
1328 *
1329 * Returns 0 on success, negative on failure
1330 *
1331 * atl2_probe initializes an adapter identified by a pci_dev structure.
1332 * The OS initialization, configuring of the adapter private structure,
1333 * and a hardware reset occur.
1334 */
1335static int __devinit atl2_probe(struct pci_dev *pdev,
1336 const struct pci_device_id *ent)
1337{
1338 struct net_device *netdev;
1339 struct atl2_adapter *adapter;
1340 static int cards_found;
1341 unsigned long mmio_start;
1342 int mmio_len;
1343 int err;
1344
1345 cards_found = 0;
1346
1347 err = pci_enable_device(pdev);
1348 if (err)
1349 return err;
1350
1351 /*
1352 * atl2 is a shared-high-32-bit device, so we're stuck with 32-bit DMA
1353 * until the kernel has the proper infrastructure to support 64-bit DMA
1354 * on these devices.
1355 */
284901a9
YH		 1356 if (pci_set_dma_mask(pdev, DMA_BIT_MASK(32)) &&
1357 pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32))) {
452c1ce2
CS		 1358 printk(KERN_ERR "atl2: No usable DMA configuration, aborting\n");
1359 goto err_dma;
1360 }
1361
1362 /* Mark all PCI regions associated with PCI device
1363 * pdev as being reserved by owner atl2_driver_name */
1364 err = pci_request_regions(pdev, atl2_driver_name);
1365 if (err)
1366 goto err_pci_reg;
1367
1368 /* Enables bus-mastering on the device and calls
1369 * pcibios_set_master to do the needed arch specific settings */
1370 pci_set_master(pdev);
1371
1372 err = -ENOMEM;
1373 netdev = alloc_etherdev(sizeof(struct atl2_adapter));
1374 if (!netdev)
1375 goto err_alloc_etherdev;
1376
1377 SET_NETDEV_DEV(netdev, &pdev->dev);
1378
1379 pci_set_drvdata(pdev, netdev);
1380 adapter = netdev_priv(netdev);
1381 adapter->netdev = netdev;
1382 adapter->pdev = pdev;
1383 adapter->hw.back = adapter;
1384
1385 mmio_start = pci_resource_start(pdev, 0x0);
1386 mmio_len = pci_resource_len(pdev, 0x0);
1387
1388 adapter->hw.mem_rang = (u32)mmio_len;
1389 adapter->hw.hw_addr = ioremap(mmio_start, mmio_len);
1390 if (!adapter->hw.hw_addr) {
1391 err = -EIO;
1392 goto err_ioremap;
1393 }
1394
1395 atl2_setup_pcicmd(pdev);
1396
825a84d1 1397 netdev->netdev_ops = &atl2_netdev_ops;
452c1ce2 1398 atl2_set_ethtool_ops(netdev);
452c1ce2 1399 netdev->watchdog_timeo = 5 * HZ;
452c1ce2
CS		 1400 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
1401
1402 netdev->mem_start = mmio_start;
1403 netdev->mem_end = mmio_start + mmio_len;
1404 adapter->bd_number = cards_found;
1405 adapter->pci_using_64 = false;
1406
1407 /* setup the private structure */
1408 err = atl2_sw_init(adapter);
1409 if (err)
1410 goto err_sw_init;
1411
1412 err = -EIO;
1413
782d640a 1414 netdev->hw_features = NETIF_F_SG;
452c1ce2 1415 netdev->features |= (NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX);
452c1ce2 1416
452c1ce2
CS		 1417 /* Init PHY as early as possible due to power saving issue */
1418 atl2_phy_init(&adapter->hw);
1419
1420 /* reset the controller to
1421 * put the device in a known good starting state */
1422
1423 if (atl2_reset_hw(&adapter->hw)) {
1424 err = -EIO;
1425 goto err_reset;
1426 }
1427
1428 /* copy the MAC address out of the EEPROM */
1429 atl2_read_mac_addr(&adapter->hw);
1430 memcpy(netdev->dev_addr, adapter->hw.mac_addr, netdev->addr_len);
1431/* FIXME: do we still need this? */
1432#ifdef ETHTOOL_GPERMADDR
1433 memcpy(netdev->perm_addr, adapter->hw.mac_addr, netdev->addr_len);
1434
1435 if (!is_valid_ether_addr(netdev->perm_addr)) {
1436#else
1437 if (!is_valid_ether_addr(netdev->dev_addr)) {
1438#endif
1439 err = -EIO;
1440 goto err_eeprom;
1441 }
1442
1443 atl2_check_options(adapter);
1444
1445 init_timer(&adapter->watchdog_timer);
c061b18d 1446 adapter->watchdog_timer.function = atl2_watchdog;
452c1ce2
CS		 1447 adapter->watchdog_timer.data = (unsigned long) adapter;
1448
1449 init_timer(&adapter->phy_config_timer);
c061b18d 1450 adapter->phy_config_timer.function = atl2_phy_config;
452c1ce2
CS		 1451 adapter->phy_config_timer.data = (unsigned long) adapter;
1452
1453 INIT_WORK(&adapter->reset_task, atl2_reset_task);
1454 INIT_WORK(&adapter->link_chg_task, atl2_link_chg_task);
1455
1456 strcpy(netdev->name, "eth%d"); /* ?? */
1457 err = register_netdev(netdev);
1458 if (err)
1459 goto err_register;
1460
1461 /* assume we have no link for now */
1462 netif_carrier_off(netdev);
1463 netif_stop_queue(netdev);
1464
1465 cards_found++;
1466
1467 return 0;
1468
1469err_reset:
1470err_register:
1471err_sw_init:
1472err_eeprom:
1473 iounmap(adapter->hw.hw_addr);
1474err_ioremap:
1475 free_netdev(netdev);
1476err_alloc_etherdev:
1477 pci_release_regions(pdev);
1478err_pci_reg:
1479err_dma:
1480 pci_disable_device(pdev);
1481 return err;
1482}
1483
1484/*
1485 * atl2_remove - Device Removal Routine
1486 * @pdev: PCI device information struct
1487 *
1488 * atl2_remove is called by the PCI subsystem to alert the driver
1489 * that it should release a PCI device. The could be caused by a
1490 * Hot-Plug event, or because the driver is going to be removed from
1491 * memory.
1492 */
1493/* FIXME: write the original MAC address back in case it was changed from a
1494 * BIOS-set value, as in atl1 -- CHS */
1495static void __devexit atl2_remove(struct pci_dev *pdev)
1496{
1497 struct net_device *netdev = pci_get_drvdata(pdev);
1498 struct atl2_adapter *adapter = netdev_priv(netdev);
1499
1500 /* flush_scheduled work may reschedule our watchdog task, so
1501 * explicitly disable watchdog tasks from being rescheduled */
1502 set_bit(__ATL2_DOWN, &adapter->flags);
1503
1504 del_timer_sync(&adapter->watchdog_timer);
1505 del_timer_sync(&adapter->phy_config_timer);
23f333a2
TH		 1506 cancel_work_sync(&adapter->reset_task);
1507 cancel_work_sync(&adapter->link_chg_task);
452c1ce2
CS		 1508
1509 unregister_netdev(netdev);
1510
1511 atl2_force_ps(&adapter->hw);
1512
1513 iounmap(adapter->hw.hw_addr);
1514 pci_release_regions(pdev);
1515
1516 free_netdev(netdev);
1517
1518 pci_disable_device(pdev);
1519}
1520
1521static int atl2_suspend(struct pci_dev *pdev, pm_message_t state)
1522{
1523 struct net_device *netdev = pci_get_drvdata(pdev);
1524 struct atl2_adapter *adapter = netdev_priv(netdev);
1525 struct atl2_hw *hw = &adapter->hw;
1526 u16 speed, duplex;
1527 u32 ctrl = 0;
1528 u32 wufc = adapter->wol;
1529
1530#ifdef CONFIG_PM
1531 int retval = 0;
1532#endif
1533
1534 netif_device_detach(netdev);
1535
1536 if (netif_running(netdev)) {
1537 WARN_ON(test_bit(__ATL2_RESETTING, &adapter->flags));
1538 atl2_down(adapter);
1539 }
1540
1541#ifdef CONFIG_PM
1542 retval = pci_save_state(pdev);
1543 if (retval)
1544 return retval;
1545#endif
1546
1547 atl2_read_phy_reg(hw, MII_BMSR, (u16 *)&ctrl);
1548 atl2_read_phy_reg(hw, MII_BMSR, (u16 *)&ctrl);
1549 if (ctrl & BMSR_LSTATUS)
1550 wufc &= ~ATLX_WUFC_LNKC;
1551
1552 if (0 != (ctrl & BMSR_LSTATUS) && 0 != wufc) {
1553 u32 ret_val;
1554 /* get current link speed & duplex */
1555 ret_val = atl2_get_speed_and_duplex(hw, &speed, &duplex);
1556 if (ret_val) {
1557 printk(KERN_DEBUG
1558 "%s: get speed&duplex error while suspend\n",
1559 atl2_driver_name);
1560 goto wol_dis;
1561 }
1562
1563 ctrl = 0;
1564
1565 /* turn on magic packet wol */
1566 if (wufc & ATLX_WUFC_MAG)
1567 ctrl |= (WOL_MAGIC_EN | WOL_MAGIC_PME_EN);
1568
1569 /* ignore Link Chg event when Link is up */
1570 ATL2_WRITE_REG(hw, REG_WOL_CTRL, ctrl);
1571
1572 /* Config MAC CTRL Register */
1573 ctrl = MAC_CTRL_RX_EN | MAC_CTRL_MACLP_CLK_PHY;
1574 if (FULL_DUPLEX == adapter->link_duplex)
1575 ctrl |= MAC_CTRL_DUPLX;
1576 ctrl |= (MAC_CTRL_ADD_CRC | MAC_CTRL_PAD);
1577 ctrl |= (((u32)adapter->hw.preamble_len &
1578 MAC_CTRL_PRMLEN_MASK) << MAC_CTRL_PRMLEN_SHIFT);
1579 ctrl |= (((u32)(adapter->hw.retry_buf &
1580 MAC_CTRL_HALF_LEFT_BUF_MASK)) <<
1581 MAC_CTRL_HALF_LEFT_BUF_SHIFT);
1582 if (wufc & ATLX_WUFC_MAG) {
1583 /* magic packet maybe Broadcast&multicast&Unicast */
1584 ctrl |= MAC_CTRL_BC_EN;
1585 }
1586
1587 ATL2_WRITE_REG(hw, REG_MAC_CTRL, ctrl);
1588
1589 /* pcie patch */
1590 ctrl = ATL2_READ_REG(hw, REG_PCIE_PHYMISC);
1591 ctrl |= PCIE_PHYMISC_FORCE_RCV_DET;
1592 ATL2_WRITE_REG(hw, REG_PCIE_PHYMISC, ctrl);
1593 ctrl = ATL2_READ_REG(hw, REG_PCIE_DLL_TX_CTRL1);
1594 ctrl |= PCIE_DLL_TX_CTRL1_SEL_NOR_CLK;
1595 ATL2_WRITE_REG(hw, REG_PCIE_DLL_TX_CTRL1, ctrl);
1596
1597 pci_enable_wake(pdev, pci_choose_state(pdev, state), 1);
1598 goto suspend_exit;
1599 }
1600
1601 if (0 == (ctrl&BMSR_LSTATUS) && 0 != (wufc&ATLX_WUFC_LNKC)) {
1602 /* link is down, so only LINK CHG WOL event enable */
1603 ctrl |= (WOL_LINK_CHG_EN | WOL_LINK_CHG_PME_EN);
1604 ATL2_WRITE_REG(hw, REG_WOL_CTRL, ctrl);
1605 ATL2_WRITE_REG(hw, REG_MAC_CTRL, 0);
1606
1607 /* pcie patch */
1608 ctrl = ATL2_READ_REG(hw, REG_PCIE_PHYMISC);
1609 ctrl |= PCIE_PHYMISC_FORCE_RCV_DET;
1610 ATL2_WRITE_REG(hw, REG_PCIE_PHYMISC, ctrl);
1611 ctrl = ATL2_READ_REG(hw, REG_PCIE_DLL_TX_CTRL1);
1612 ctrl |= PCIE_DLL_TX_CTRL1_SEL_NOR_CLK;
1613 ATL2_WRITE_REG(hw, REG_PCIE_DLL_TX_CTRL1, ctrl);
1614
1615 hw->phy_configured = false; /* re-init PHY when resume */
1616
1617 pci_enable_wake(pdev, pci_choose_state(pdev, state), 1);
1618
1619 goto suspend_exit;
1620 }
1621
1622wol_dis:
1623 /* WOL disabled */
1624 ATL2_WRITE_REG(hw, REG_WOL_CTRL, 0);
1625
1626 /* pcie patch */
1627 ctrl = ATL2_READ_REG(hw, REG_PCIE_PHYMISC);
1628 ctrl |= PCIE_PHYMISC_FORCE_RCV_DET;
1629 ATL2_WRITE_REG(hw, REG_PCIE_PHYMISC, ctrl);
1630 ctrl = ATL2_READ_REG(hw, REG_PCIE_DLL_TX_CTRL1);
1631 ctrl |= PCIE_DLL_TX_CTRL1_SEL_NOR_CLK;
1632 ATL2_WRITE_REG(hw, REG_PCIE_DLL_TX_CTRL1, ctrl);
1633
1634 atl2_force_ps(hw);
1635 hw->phy_configured = false; /* re-init PHY when resume */
1636
1637 pci_enable_wake(pdev, pci_choose_state(pdev, state), 0);
1638
1639suspend_exit:
1640 if (netif_running(netdev))
1641 atl2_free_irq(adapter);
1642
1643 pci_disable_device(pdev);
1644
1645 pci_set_power_state(pdev, pci_choose_state(pdev, state));
1646
1647 return 0;
1648}
1649
1650#ifdef CONFIG_PM
1651static int atl2_resume(struct pci_dev *pdev)
1652{
1653 struct net_device *netdev = pci_get_drvdata(pdev);
1654 struct atl2_adapter *adapter = netdev_priv(netdev);
1655 u32 err;
1656
1657 pci_set_power_state(pdev, PCI_D0);
1658 pci_restore_state(pdev);
1659
1660 err = pci_enable_device(pdev);
1661 if (err) {
1662 printk(KERN_ERR
1663 "atl2: Cannot enable PCI device from suspend\n");
1664 return err;
1665 }
1666
1667 pci_set_master(pdev);
1668
1669 ATL2_READ_REG(&adapter->hw, REG_WOL_CTRL); /* clear WOL status */
1670
1671 pci_enable_wake(pdev, PCI_D3hot, 0);
1672 pci_enable_wake(pdev, PCI_D3cold, 0);
1673
1674 ATL2_WRITE_REG(&adapter->hw, REG_WOL_CTRL, 0);
1675
a849854f
AJ		 1676 if (netif_running(netdev)) {
1677 err = atl2_request_irq(adapter);
1678 if (err)
1679 return err;
1680 }
452c1ce2
CS		 1681
1682 atl2_reset_hw(&adapter->hw);
1683
1684 if (netif_running(netdev))
1685 atl2_up(adapter);
1686
1687 netif_device_attach(netdev);
1688
1689 return 0;
1690}
1691#endif
1692
1693static void atl2_shutdown(struct pci_dev *pdev)
1694{
1695 atl2_suspend(pdev, PMSG_SUSPEND);
1696}
1697
1698static struct pci_driver atl2_driver = {
1699 .name = atl2_driver_name,
1700 .id_table = atl2_pci_tbl,
1701 .probe = atl2_probe,
1702 .remove = __devexit_p(atl2_remove),
25985edc 1703 /* Power Management Hooks */
452c1ce2
CS		 1704 .suspend = atl2_suspend,
1705#ifdef CONFIG_PM
1706 .resume = atl2_resume,
1707#endif
1708 .shutdown = atl2_shutdown,
1709};
1710
1711/*
1712 * atl2_init_module - Driver Registration Routine
1713 *
1714 * atl2_init_module is the first routine called when the driver is
1715 * loaded. All it does is register with the PCI subsystem.
1716 */
1717static int __init atl2_init_module(void)
1718{
1719 printk(KERN_INFO "%s - version %s\n", atl2_driver_string,
1720 atl2_driver_version);
1721 printk(KERN_INFO "%s\n", atl2_copyright);
1722 return pci_register_driver(&atl2_driver);
1723}
1724module_init(atl2_init_module);
1725
1726/*
1727 * atl2_exit_module - Driver Exit Cleanup Routine
1728 *
1729 * atl2_exit_module is called just before the driver is removed
1730 * from memory.
1731 */
1732static void __exit atl2_exit_module(void)
1733{
1734 pci_unregister_driver(&atl2_driver);
1735}
1736module_exit(atl2_exit_module);
1737
1738static void atl2_read_pci_cfg(struct atl2_hw *hw, u32 reg, u16 *value)
1739{
1740 struct atl2_adapter *adapter = hw->back;
1741 pci_read_config_word(adapter->pdev, reg, value);
1742}
1743
1744static void atl2_write_pci_cfg(struct atl2_hw *hw, u32 reg, u16 *value)
1745{
1746 struct atl2_adapter *adapter = hw->back;
1747 pci_write_config_word(adapter->pdev, reg, *value);
1748}
1749
1750static int atl2_get_settings(struct net_device *netdev,
1751 struct ethtool_cmd *ecmd)
1752{
1753 struct atl2_adapter *adapter = netdev_priv(netdev);
1754 struct atl2_hw *hw = &adapter->hw;
1755
1756 ecmd->supported = (SUPPORTED_10baseT_Half |
1757 SUPPORTED_10baseT_Full |
1758 SUPPORTED_100baseT_Half |
1759 SUPPORTED_100baseT_Full |
1760 SUPPORTED_Autoneg |
1761 SUPPORTED_TP);
1762 ecmd->advertising = ADVERTISED_TP;
1763
1764 ecmd->advertising |= ADVERTISED_Autoneg;
1765 ecmd->advertising |= hw->autoneg_advertised;
1766
1767 ecmd->port = PORT_TP;
1768 ecmd->phy_address = 0;
1769 ecmd->transceiver = XCVR_INTERNAL;
1770
1771 if (adapter->link_speed != SPEED_0) {
70739497 1772 ethtool_cmd_speed_set(ecmd, adapter->link_speed);
452c1ce2
CS		 1773 if (adapter->link_duplex == FULL_DUPLEX)
1774 ecmd->duplex = DUPLEX_FULL;
1775 else
1776 ecmd->duplex = DUPLEX_HALF;
1777 } else {
70739497 1778 ethtool_cmd_speed_set(ecmd, -1);
452c1ce2
CS		 1779 ecmd->duplex = -1;
1780 }
1781
1782 ecmd->autoneg = AUTONEG_ENABLE;
1783 return 0;
1784}
1785
1786static int atl2_set_settings(struct net_device *netdev,
1787 struct ethtool_cmd *ecmd)
1788{
1789 struct atl2_adapter *adapter = netdev_priv(netdev);
1790 struct atl2_hw *hw = &adapter->hw;
1791
1792 while (test_and_set_bit(__ATL2_RESETTING, &adapter->flags))
1793 msleep(1);
1794
1795 if (ecmd->autoneg == AUTONEG_ENABLE) {
1796#define MY_ADV_MASK (ADVERTISE_10_HALF | \
1797 ADVERTISE_10_FULL | \
1798 ADVERTISE_100_HALF| \
1799 ADVERTISE_100_FULL)
1800
1801 if ((ecmd->advertising & MY_ADV_MASK) == MY_ADV_MASK) {
1802 hw->MediaType = MEDIA_TYPE_AUTO_SENSOR;
1803 hw->autoneg_advertised = MY_ADV_MASK;
1804 } else if ((ecmd->advertising & MY_ADV_MASK) ==
1805 ADVERTISE_100_FULL) {
1806 hw->MediaType = MEDIA_TYPE_100M_FULL;
1807 hw->autoneg_advertised = ADVERTISE_100_FULL;
1808 } else if ((ecmd->advertising & MY_ADV_MASK) ==
1809 ADVERTISE_100_HALF) {
1810 hw->MediaType = MEDIA_TYPE_100M_HALF;
1811 hw->autoneg_advertised = ADVERTISE_100_HALF;
1812 } else if ((ecmd->advertising & MY_ADV_MASK) ==
1813 ADVERTISE_10_FULL) {
1814 hw->MediaType = MEDIA_TYPE_10M_FULL;
1815 hw->autoneg_advertised = ADVERTISE_10_FULL;
1816 } else if ((ecmd->advertising & MY_ADV_MASK) ==
1817 ADVERTISE_10_HALF) {
1818 hw->MediaType = MEDIA_TYPE_10M_HALF;
1819 hw->autoneg_advertised = ADVERTISE_10_HALF;
1820 } else {
1821 clear_bit(__ATL2_RESETTING, &adapter->flags);
1822 return -EINVAL;
1823 }
1824 ecmd->advertising = hw->autoneg_advertised |
1825 ADVERTISED_TP | ADVERTISED_Autoneg;
1826 } else {
1827 clear_bit(__ATL2_RESETTING, &adapter->flags);
1828 return -EINVAL;
1829 }
1830
1831 /* reset the link */
1832 if (netif_running(adapter->netdev)) {
1833 atl2_down(adapter);
1834 atl2_up(adapter);
1835 } else
1836 atl2_reset_hw(&adapter->hw);
1837
1838 clear_bit(__ATL2_RESETTING, &adapter->flags);
1839 return 0;
1840}
1841
452c1ce2
CS		 1842static u32 atl2_get_msglevel(struct net_device *netdev)
1843{
1844 return 0;
1845}
1846
1847/*
1848 * It's sane for this to be empty, but we might want to take advantage of this.
1849 */
1850static void atl2_set_msglevel(struct net_device *netdev, u32 data)
1851{
1852}
1853
1854static int atl2_get_regs_len(struct net_device *netdev)
1855{
1856#define ATL2_REGS_LEN 42
1857 return sizeof(u32) * ATL2_REGS_LEN;
1858}
1859
1860static void atl2_get_regs(struct net_device *netdev,
1861 struct ethtool_regs *regs, void *p)
1862{
1863 struct atl2_adapter *adapter = netdev_priv(netdev);
1864 struct atl2_hw *hw = &adapter->hw;
1865 u32 *regs_buff = p;
1866 u16 phy_data;
1867
1868 memset(p, 0, sizeof(u32) * ATL2_REGS_LEN);
1869
1870 regs->version = (1 << 24) | (hw->revision_id << 16) | hw->device_id;
1871
1872 regs_buff[0] = ATL2_READ_REG(hw, REG_VPD_CAP);
1873 regs_buff[1] = ATL2_READ_REG(hw, REG_SPI_FLASH_CTRL);
1874 regs_buff[2] = ATL2_READ_REG(hw, REG_SPI_FLASH_CONFIG);
1875 regs_buff[3] = ATL2_READ_REG(hw, REG_TWSI_CTRL);
1876 regs_buff[4] = ATL2_READ_REG(hw, REG_PCIE_DEV_MISC_CTRL);
1877 regs_buff[5] = ATL2_READ_REG(hw, REG_MASTER_CTRL);
1878 regs_buff[6] = ATL2_READ_REG(hw, REG_MANUAL_TIMER_INIT);
1879 regs_buff[7] = ATL2_READ_REG(hw, REG_IRQ_MODU_TIMER_INIT);
1880 regs_buff[8] = ATL2_READ_REG(hw, REG_PHY_ENABLE);
1881 regs_buff[9] = ATL2_READ_REG(hw, REG_CMBDISDMA_TIMER);
1882 regs_buff[10] = ATL2_READ_REG(hw, REG_IDLE_STATUS);
1883 regs_buff[11] = ATL2_READ_REG(hw, REG_MDIO_CTRL);
1884 regs_buff[12] = ATL2_READ_REG(hw, REG_SERDES_LOCK);
1885 regs_buff[13] = ATL2_READ_REG(hw, REG_MAC_CTRL);
1886 regs_buff[14] = ATL2_READ_REG(hw, REG_MAC_IPG_IFG);
1887 regs_buff[15] = ATL2_READ_REG(hw, REG_MAC_STA_ADDR);
1888 regs_buff[16] = ATL2_READ_REG(hw, REG_MAC_STA_ADDR+4);
1889 regs_buff[17] = ATL2_READ_REG(hw, REG_RX_HASH_TABLE);
1890 regs_buff[18] = ATL2_READ_REG(hw, REG_RX_HASH_TABLE+4);
1891 regs_buff[19] = ATL2_READ_REG(hw, REG_MAC_HALF_DUPLX_CTRL);
1892 regs_buff[20] = ATL2_READ_REG(hw, REG_MTU);
1893 regs_buff[21] = ATL2_READ_REG(hw, REG_WOL_CTRL);
1894 regs_buff[22] = ATL2_READ_REG(hw, REG_SRAM_TXRAM_END);
1895 regs_buff[23] = ATL2_READ_REG(hw, REG_DESC_BASE_ADDR_HI);
1896 regs_buff[24] = ATL2_READ_REG(hw, REG_TXD_BASE_ADDR_LO);
1897 regs_buff[25] = ATL2_READ_REG(hw, REG_TXD_MEM_SIZE);
1898 regs_buff[26] = ATL2_READ_REG(hw, REG_TXS_BASE_ADDR_LO);
1899 regs_buff[27] = ATL2_READ_REG(hw, REG_TXS_MEM_SIZE);
1900 regs_buff[28] = ATL2_READ_REG(hw, REG_RXD_BASE_ADDR_LO);
1901 regs_buff[29] = ATL2_READ_REG(hw, REG_RXD_BUF_NUM);
1902 regs_buff[30] = ATL2_READ_REG(hw, REG_DMAR);
1903 regs_buff[31] = ATL2_READ_REG(hw, REG_TX_CUT_THRESH);
1904 regs_buff[32] = ATL2_READ_REG(hw, REG_DMAW);
1905 regs_buff[33] = ATL2_READ_REG(hw, REG_PAUSE_ON_TH);
1906 regs_buff[34] = ATL2_READ_REG(hw, REG_PAUSE_OFF_TH);
1907 regs_buff[35] = ATL2_READ_REG(hw, REG_MB_TXD_WR_IDX);
1908 regs_buff[36] = ATL2_READ_REG(hw, REG_MB_RXD_RD_IDX);
1909 regs_buff[38] = ATL2_READ_REG(hw, REG_ISR);
1910 regs_buff[39] = ATL2_READ_REG(hw, REG_IMR);
1911
1912 atl2_read_phy_reg(hw, MII_BMCR, &phy_data);
1913 regs_buff[40] = (u32)phy_data;
1914 atl2_read_phy_reg(hw, MII_BMSR, &phy_data);
1915 regs_buff[41] = (u32)phy_data;
1916}
1917
1918static int atl2_get_eeprom_len(struct net_device *netdev)
1919{
1920 struct atl2_adapter *adapter = netdev_priv(netdev);
1921
1922 if (!atl2_check_eeprom_exist(&adapter->hw))
1923 return 512;
1924 else
1925 return 0;
1926}
1927
1928static int atl2_get_eeprom(struct net_device *netdev,
1929 struct ethtool_eeprom *eeprom, u8 *bytes)
1930{
1931 struct atl2_adapter *adapter = netdev_priv(netdev);
1932 struct atl2_hw *hw = &adapter->hw;
1933 u32 *eeprom_buff;
1934 int first_dword, last_dword;
1935 int ret_val = 0;
1936 int i;
1937
1938 if (eeprom->len == 0)
1939 return -EINVAL;
1940
1941 if (atl2_check_eeprom_exist(hw))
1942 return -EINVAL;
1943
1944 eeprom->magic = hw->vendor_id | (hw->device_id << 16);
1945
1946 first_dword = eeprom->offset >> 2;
1947 last_dword = (eeprom->offset + eeprom->len - 1) >> 2;
1948
1949 eeprom_buff = kmalloc(sizeof(u32) * (last_dword - first_dword + 1),
1950 GFP_KERNEL);
1951 if (!eeprom_buff)
1952 return -ENOMEM;
1953
1954 for (i = first_dword; i < last_dword; i++) {
2467ab95
JS		 1955 if (!atl2_read_eeprom(hw, i*4, &(eeprom_buff[i-first_dword]))) {
1956 ret_val = -EIO;
1957 goto free;
1958 }
452c1ce2
CS		 1959 }
1960
1961 memcpy(bytes, (u8 *)eeprom_buff + (eeprom->offset & 3),
1962 eeprom->len);
2467ab95 1963free:
452c1ce2
CS		 1964 kfree(eeprom_buff);
1965
1966 return ret_val;
1967}
1968
1969static int atl2_set_eeprom(struct net_device *netdev,
1970 struct ethtool_eeprom *eeprom, u8 *bytes)
1971{
1972 struct atl2_adapter *adapter = netdev_priv(netdev);
1973 struct atl2_hw *hw = &adapter->hw;
1974 u32 *eeprom_buff;
1975 u32 *ptr;
1976 int max_len, first_dword, last_dword, ret_val = 0;
1977 int i;
1978
1979 if (eeprom->len == 0)
1980 return -EOPNOTSUPP;
1981
1982 if (eeprom->magic != (hw->vendor_id | (hw->device_id << 16)))
1983 return -EFAULT;
1984
1985 max_len = 512;
1986
1987 first_dword = eeprom->offset >> 2;
1988 last_dword = (eeprom->offset + eeprom->len - 1) >> 2;
1989 eeprom_buff = kmalloc(max_len, GFP_KERNEL);
1990 if (!eeprom_buff)
1991 return -ENOMEM;
1992
ad19031b 1993 ptr = eeprom_buff;
452c1ce2
CS		 1994
1995 if (eeprom->offset & 3) {
1996 /* need read/modify/write of first changed EEPROM word */
1997 /* only the second byte of the word is being modified */
ad19031b
JJ		 1998 if (!atl2_read_eeprom(hw, first_dword*4, &(eeprom_buff[0]))) {
1999 ret_val = -EIO;
2000 goto out;
2001 }
452c1ce2
CS		 2002 ptr++;
2003 }
2004 if (((eeprom->offset + eeprom->len) & 3)) {
2005 /*
2006 * need read/modify/write of last changed EEPROM word
2007 * only the first byte of the word is being modified
2008 */
2009 if (!atl2_read_eeprom(hw, last_dword * 4,
ad19031b
JJ		 2010 &(eeprom_buff[last_dword - first_dword]))) {
2011 ret_val = -EIO;
2012 goto out;
2013 }
452c1ce2
CS		 2014 }
2015
2016 /* Device's eeprom is always little-endian, word addressable */
2017 memcpy(ptr, bytes, eeprom->len);
2018
2019 for (i = 0; i < last_dword - first_dword + 1; i++) {
ad19031b
JJ		 2020 if (!atl2_write_eeprom(hw, ((first_dword+i)*4), eeprom_buff[i])) {
2021 ret_val = -EIO;
2022 goto out;
2023 }
452c1ce2 2024 }
ad19031b 2025 out:
452c1ce2
CS		 2026 kfree(eeprom_buff);
2027 return ret_val;
2028}
2029
2030static void atl2_get_drvinfo(struct net_device *netdev,
2031 struct ethtool_drvinfo *drvinfo)
2032{
2033 struct atl2_adapter *adapter = netdev_priv(netdev);
2034
2035 strncpy(drvinfo->driver, atl2_driver_name, 32);
2036 strncpy(drvinfo->version, atl2_driver_version, 32);
2037 strncpy(drvinfo->fw_version, "L2", 32);
2038 strncpy(drvinfo->bus_info, pci_name(adapter->pdev), 32);
2039 drvinfo->n_stats = 0;
2040 drvinfo->testinfo_len = 0;
2041 drvinfo->regdump_len = atl2_get_regs_len(netdev);
2042 drvinfo->eedump_len = atl2_get_eeprom_len(netdev);
2043}
2044
2045static void atl2_get_wol(struct net_device *netdev,
2046 struct ethtool_wolinfo *wol)
2047{
2048 struct atl2_adapter *adapter = netdev_priv(netdev);
2049
2050 wol->supported = WAKE_MAGIC;
2051 wol->wolopts = 0;
2052
2053 if (adapter->wol & ATLX_WUFC_EX)
2054 wol->wolopts |= WAKE_UCAST;
2055 if (adapter->wol & ATLX_WUFC_MC)
2056 wol->wolopts |= WAKE_MCAST;
2057 if (adapter->wol & ATLX_WUFC_BC)
2058 wol->wolopts |= WAKE_BCAST;
2059 if (adapter->wol & ATLX_WUFC_MAG)
2060 wol->wolopts |= WAKE_MAGIC;
2061 if (adapter->wol & ATLX_WUFC_LNKC)
2062 wol->wolopts |= WAKE_PHY;
2063}
2064
2065static int atl2_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
2066{
2067 struct atl2_adapter *adapter = netdev_priv(netdev);
2068
2069 if (wol->wolopts & (WAKE_ARP | WAKE_MAGICSECURE))
2070 return -EOPNOTSUPP;
2071
41796e91 2072 if (wol->wolopts & (WAKE_UCAST | WAKE_BCAST | WAKE_MCAST))
452c1ce2
CS		 2073 return -EOPNOTSUPP;
2074
2075 /* these settings will always override what we currently have */
2076 adapter->wol = 0;
2077
2078 if (wol->wolopts & WAKE_MAGIC)
2079 adapter->wol |= ATLX_WUFC_MAG;
2080 if (wol->wolopts & WAKE_PHY)
2081 adapter->wol |= ATLX_WUFC_LNKC;
2082
2083 return 0;
2084}
2085
2086static int atl2_nway_reset(struct net_device *netdev)
2087{
2088 struct atl2_adapter *adapter = netdev_priv(netdev);
2089 if (netif_running(netdev))
2090 atl2_reinit_locked(adapter);
2091 return 0;
2092}
2093
0fc0b732 2094static const struct ethtool_ops atl2_ethtool_ops = {
452c1ce2
CS		 2095 .get_settings = atl2_get_settings,
2096 .set_settings = atl2_set_settings,
2097 .get_drvinfo = atl2_get_drvinfo,
2098 .get_regs_len = atl2_get_regs_len,
2099 .get_regs = atl2_get_regs,
2100 .get_wol = atl2_get_wol,
2101 .set_wol = atl2_set_wol,
2102 .get_msglevel = atl2_get_msglevel,
2103 .set_msglevel = atl2_set_msglevel,
2104 .nway_reset = atl2_nway_reset,
2105 .get_link = ethtool_op_get_link,
2106 .get_eeprom_len = atl2_get_eeprom_len,
2107 .get_eeprom = atl2_get_eeprom,
2108 .set_eeprom = atl2_set_eeprom,
452c1ce2
CS		 2109};
2110
2111static void atl2_set_ethtool_ops(struct net_device *netdev)
2112{
2113 SET_ETHTOOL_OPS(netdev, &atl2_ethtool_ops);
2114}
2115
2116#define LBYTESWAP(a) ((((a) & 0x00ff00ff) << 8) | \
2117 (((a) & 0xff00ff00) >> 8))
2118#define LONGSWAP(a) ((LBYTESWAP(a) << 16) | (LBYTESWAP(a) >> 16))
2119#define SHORTSWAP(a) (((a) << 8) | ((a) >> 8))
2120
2121/*
2122 * Reset the transmit and receive units; mask and clear all interrupts.
2123 *
2124 * hw - Struct containing variables accessed by shared code
2125 * return : 0 or idle status (if error)
2126 */
2127static s32 atl2_reset_hw(struct atl2_hw *hw)
2128{
2129 u32 icr;
2130 u16 pci_cfg_cmd_word;
2131 int i;
2132
2133 /* Workaround for PCI problem when BIOS sets MMRBC incorrectly. */
2134 atl2_read_pci_cfg(hw, PCI_REG_COMMAND, &pci_cfg_cmd_word);
2135 if ((pci_cfg_cmd_word &
2136 (CMD_IO_SPACE|CMD_MEMORY_SPACE|CMD_BUS_MASTER)) !=
2137 (CMD_IO_SPACE|CMD_MEMORY_SPACE|CMD_BUS_MASTER)) {
2138 pci_cfg_cmd_word |=
2139 (CMD_IO_SPACE|CMD_MEMORY_SPACE|CMD_BUS_MASTER);
2140 atl2_write_pci_cfg(hw, PCI_REG_COMMAND, &pci_cfg_cmd_word);
2141 }
2142
2143 /* Clear Interrupt mask to stop board from generating
2144 * interrupts & Clear any pending interrupt events
2145 */
2146 /* FIXME */
2147 /* ATL2_WRITE_REG(hw, REG_IMR, 0); */
2148 /* ATL2_WRITE_REG(hw, REG_ISR, 0xffffffff); */
2149
2150 /* Issue Soft Reset to the MAC. This will reset the chip's
2151 * transmit, receive, DMA. It will not effect
2152 * the current PCI configuration. The global reset bit is self-
2153 * clearing, and should clear within a microsecond.
2154 */
2155 ATL2_WRITE_REG(hw, REG_MASTER_CTRL, MASTER_CTRL_SOFT_RST);
2156 wmb();
2157 msleep(1); /* delay about 1ms */
2158
2159 /* Wait at least 10ms for All module to be Idle */
2160 for (i = 0; i < 10; i++) {
2161 icr = ATL2_READ_REG(hw, REG_IDLE_STATUS);
2162 if (!icr)
2163 break;
2164 msleep(1); /* delay 1 ms */
2165 cpu_relax();
2166 }
2167
2168 if (icr)
2169 return icr;
2170
2171 return 0;
2172}
2173
2174#define CUSTOM_SPI_CS_SETUP 2
2175#define CUSTOM_SPI_CLK_HI 2
2176#define CUSTOM_SPI_CLK_LO 2
2177#define CUSTOM_SPI_CS_HOLD 2
2178#define CUSTOM_SPI_CS_HI 3
2179
2180static struct atl2_spi_flash_dev flash_table[] =
2181{
2182/* MFR WRSR READ PROGRAM WREN WRDI RDSR RDID SECTOR_ERASE CHIP_ERASE */
2183{"Atmel", 0x0, 0x03, 0x02, 0x06, 0x04, 0x05, 0x15, 0x52, 0x62 },
2184{"SST", 0x01, 0x03, 0x02, 0x06, 0x04, 0x05, 0x90, 0x20, 0x60 },
2185{"ST", 0x01, 0x03, 0x02, 0x06, 0x04, 0x05, 0xAB, 0xD8, 0xC7 },
2186};
2187
2188static bool atl2_spi_read(struct atl2_hw *hw, u32 addr, u32 *buf)
2189{
2190 int i;
2191 u32 value;
2192
2193 ATL2_WRITE_REG(hw, REG_SPI_DATA, 0);
2194 ATL2_WRITE_REG(hw, REG_SPI_ADDR, addr);
2195
2196 value = SPI_FLASH_CTRL_WAIT_READY |
2197 (CUSTOM_SPI_CS_SETUP & SPI_FLASH_CTRL_CS_SETUP_MASK) <<
2198 SPI_FLASH_CTRL_CS_SETUP_SHIFT |
2199 (CUSTOM_SPI_CLK_HI & SPI_FLASH_CTRL_CLK_HI_MASK) <<
2200 SPI_FLASH_CTRL_CLK_HI_SHIFT |
2201 (CUSTOM_SPI_CLK_LO & SPI_FLASH_CTRL_CLK_LO_MASK) <<
2202 SPI_FLASH_CTRL_CLK_LO_SHIFT |
2203 (CUSTOM_SPI_CS_HOLD & SPI_FLASH_CTRL_CS_HOLD_MASK) <<
2204 SPI_FLASH_CTRL_CS_HOLD_SHIFT |
2205 (CUSTOM_SPI_CS_HI & SPI_FLASH_CTRL_CS_HI_MASK) <<
2206 SPI_FLASH_CTRL_CS_HI_SHIFT |
2207 (0x1 & SPI_FLASH_CTRL_INS_MASK) << SPI_FLASH_CTRL_INS_SHIFT;
2208
2209 ATL2_WRITE_REG(hw, REG_SPI_FLASH_CTRL, value);
2210
2211 value |= SPI_FLASH_CTRL_START;
2212
2213 ATL2_WRITE_REG(hw, REG_SPI_FLASH_CTRL, value);
2214
2215 for (i = 0; i < 10; i++) {
2216 msleep(1);
2217 value = ATL2_READ_REG(hw, REG_SPI_FLASH_CTRL);
2218 if (!(value & SPI_FLASH_CTRL_START))
2219 break;
2220 }
2221
2222 if (value & SPI_FLASH_CTRL_START)
2223 return false;
2224
2225 *buf = ATL2_READ_REG(hw, REG_SPI_DATA);
2226
2227 return true;
2228}
2229
2230/*
2231 * get_permanent_address
2232 * return 0 if get valid mac address,
2233 */
2234static int get_permanent_address(struct atl2_hw *hw)
2235{
2236 u32 Addr[2];
2237 u32 i, Control;
2238 u16 Register;
2239 u8 EthAddr[NODE_ADDRESS_SIZE];
2240 bool KeyValid;
2241
2242 if (is_valid_ether_addr(hw->perm_mac_addr))
2243 return 0;
2244
2245 Addr[0] = 0;
2246 Addr[1] = 0;
2247
2248 if (!atl2_check_eeprom_exist(hw)) { /* eeprom exists */
2249 Register = 0;
2250 KeyValid = false;
2251
2252 /* Read out all EEPROM content */
2253 i = 0;
2254 while (1) {
2255 if (atl2_read_eeprom(hw, i + 0x100, &Control)) {
2256 if (KeyValid) {
2257 if (Register == REG_MAC_STA_ADDR)
2258 Addr[0] = Control;
2259 else if (Register ==
2260 (REG_MAC_STA_ADDR + 4))
2261 Addr[1] = Control;
2262 KeyValid = false;
2263 } else if ((Control & 0xff) == 0x5A) {
2264 KeyValid = true;
2265 Register = (u16) (Control >> 16);
2266 } else {
2267 /* assume data end while encount an invalid KEYWORD */
2268 break;
2269 }
2270 } else {
2271 break; /* read error */
2272 }
2273 i += 4;
2274 }
2275
2276 *(u32 *) &EthAddr[2] = LONGSWAP(Addr[0]);
2277 *(u16 *) &EthAddr[0] = SHORTSWAP(*(u16 *) &Addr[1]);
2278
2279 if (is_valid_ether_addr(EthAddr)) {
2280 memcpy(hw->perm_mac_addr, EthAddr, NODE_ADDRESS_SIZE);
2281 return 0;
2282 }
2283 return 1;
2284 }
2285
2286 /* see if SPI flash exists? */
2287 Addr[0] = 0;
2288 Addr[1] = 0;
2289 Register = 0;
2290 KeyValid = false;
2291 i = 0;
2292 while (1) {
2293 if (atl2_spi_read(hw, i + 0x1f000, &Control)) {
2294 if (KeyValid) {
2295 if (Register == REG_MAC_STA_ADDR)
2296 Addr[0] = Control;
2297 else if (Register == (REG_MAC_STA_ADDR + 4))
2298 Addr[1] = Control;
2299 KeyValid = false;
2300 } else if ((Control & 0xff) == 0x5A) {
2301 KeyValid = true;
2302 Register = (u16) (Control >> 16);
2303 } else {
2304 break; /* data end */
2305 }
2306 } else {
2307 break; /* read error */
2308 }
2309 i += 4;
2310 }
2311
2312 *(u32 *) &EthAddr[2] = LONGSWAP(Addr[0]);
2313 *(u16 *) &EthAddr[0] = SHORTSWAP(*(u16 *)&Addr[1]);
2314 if (is_valid_ether_addr(EthAddr)) {
2315 memcpy(hw->perm_mac_addr, EthAddr, NODE_ADDRESS_SIZE);
2316 return 0;
2317 }
2318 /* maybe MAC-address is from BIOS */
2319 Addr[0] = ATL2_READ_REG(hw, REG_MAC_STA_ADDR);
2320 Addr[1] = ATL2_READ_REG(hw, REG_MAC_STA_ADDR + 4);
2321 *(u32 *) &EthAddr[2] = LONGSWAP(Addr[0]);
2322 *(u16 *) &EthAddr[0] = SHORTSWAP(*(u16 *) &Addr[1]);
2323
2324 if (is_valid_ether_addr(EthAddr)) {
2325 memcpy(hw->perm_mac_addr, EthAddr, NODE_ADDRESS_SIZE);
2326 return 0;
2327 }
2328
2329 return 1;
2330}
2331
2332/*
2333 * Reads the adapter's MAC address from the EEPROM
2334 *
2335 * hw - Struct containing variables accessed by shared code
2336 */
2337static s32 atl2_read_mac_addr(struct atl2_hw *hw)
2338{
2339 u16 i;
2340
2341 if (get_permanent_address(hw)) {
2342 /* for test */
2343 /* FIXME: shouldn't we use random_ether_addr() here? */
2344 hw->perm_mac_addr[0] = 0x00;
2345 hw->perm_mac_addr[1] = 0x13;
2346 hw->perm_mac_addr[2] = 0x74;
2347 hw->perm_mac_addr[3] = 0x00;
2348 hw->perm_mac_addr[4] = 0x5c;
2349 hw->perm_mac_addr[5] = 0x38;
2350 }
2351
2352 for (i = 0; i < NODE_ADDRESS_SIZE; i++)
2353 hw->mac_addr[i] = hw->perm_mac_addr[i];
2354
2355 return 0;
2356}
2357
2358/*
2359 * Hashes an address to determine its location in the multicast table
2360 *
2361 * hw - Struct containing variables accessed by shared code
2362 * mc_addr - the multicast address to hash
2363 *
2364 * atl2_hash_mc_addr
2365 * purpose
2366 * set hash value for a multicast address
2367 * hash calcu processing :
2368 * 1. calcu 32bit CRC for multicast address
2369 * 2. reverse crc with MSB to LSB
2370 */
2371static u32 atl2_hash_mc_addr(struct atl2_hw *hw, u8 *mc_addr)
2372{
2373 u32 crc32, value;
2374 int i;
2375
2376 value = 0;
2377 crc32 = ether_crc_le(6, mc_addr);
2378
2379 for (i = 0; i < 32; i++)
2380 value |= (((crc32 >> i) & 1) << (31 - i));
2381
2382 return value;
2383}
2384
2385/*
2386 * Sets the bit in the multicast table corresponding to the hash value.
2387 *
2388 * hw - Struct containing variables accessed by shared code
2389 * hash_value - Multicast address hash value
2390 */
2391static void atl2_hash_set(struct atl2_hw *hw, u32 hash_value)
2392{
2393 u32 hash_bit, hash_reg;
2394 u32 mta;
2395
2396 /* The HASH Table is a register array of 2 32-bit registers.
2397 * It is treated like an array of 64 bits. We want to set
2398 * bit BitArray[hash_value]. So we figure out what register
2399 * the bit is in, read it, OR in the new bit, then write
2400 * back the new value. The register is determined by the
2401 * upper 7 bits of the hash value and the bit within that
2402 * register are determined by the lower 5 bits of the value.
2403 */
2404 hash_reg = (hash_value >> 31) & 0x1;
2405 hash_bit = (hash_value >> 26) & 0x1F;
2406
2407 mta = ATL2_READ_REG_ARRAY(hw, REG_RX_HASH_TABLE, hash_reg);
2408
2409 mta |= (1 << hash_bit);
2410
2411 ATL2_WRITE_REG_ARRAY(hw, REG_RX_HASH_TABLE, hash_reg, mta);
2412}
2413
2414/*
2415 * atl2_init_pcie - init PCIE module
2416 */
2417static void atl2_init_pcie(struct atl2_hw *hw)
2418{
2419 u32 value;
2420 value = LTSSM_TEST_MODE_DEF;
2421 ATL2_WRITE_REG(hw, REG_LTSSM_TEST_MODE, value);
2422
2423 value = PCIE_DLL_TX_CTRL1_DEF;
2424 ATL2_WRITE_REG(hw, REG_PCIE_DLL_TX_CTRL1, value);
2425}
2426
2427static void atl2_init_flash_opcode(struct atl2_hw *hw)
2428{
2429 if (hw->flash_vendor >= ARRAY_SIZE(flash_table))
2430 hw->flash_vendor = 0; /* ATMEL */
2431
2432 /* Init OP table */
2433 ATL2_WRITE_REGB(hw, REG_SPI_FLASH_OP_PROGRAM,
2434 flash_table[hw->flash_vendor].cmdPROGRAM);
2435 ATL2_WRITE_REGB(hw, REG_SPI_FLASH_OP_SC_ERASE,
2436 flash_table[hw->flash_vendor].cmdSECTOR_ERASE);
2437 ATL2_WRITE_REGB(hw, REG_SPI_FLASH_OP_CHIP_ERASE,
2438 flash_table[hw->flash_vendor].cmdCHIP_ERASE);
2439 ATL2_WRITE_REGB(hw, REG_SPI_FLASH_OP_RDID,
2440 flash_table[hw->flash_vendor].cmdRDID);
2441 ATL2_WRITE_REGB(hw, REG_SPI_FLASH_OP_WREN,
2442 flash_table[hw->flash_vendor].cmdWREN);
2443 ATL2_WRITE_REGB(hw, REG_SPI_FLASH_OP_RDSR,
2444 flash_table[hw->flash_vendor].cmdRDSR);
2445 ATL2_WRITE_REGB(hw, REG_SPI_FLASH_OP_WRSR,
2446 flash_table[hw->flash_vendor].cmdWRSR);
2447 ATL2_WRITE_REGB(hw, REG_SPI_FLASH_OP_READ,
2448 flash_table[hw->flash_vendor].cmdREAD);
2449}
2450
2451/********************************************************************
2452* Performs basic configuration of the adapter.
2453*
2454* hw - Struct containing variables accessed by shared code
2455* Assumes that the controller has previously been reset and is in a
2456* post-reset uninitialized state. Initializes multicast table,
2457* and Calls routines to setup link
2458* Leaves the transmit and receive units disabled and uninitialized.
2459********************************************************************/
2460static s32 atl2_init_hw(struct atl2_hw *hw)
2461{
2462 u32 ret_val = 0;
2463
2464 atl2_init_pcie(hw);
2465
2466 /* Zero out the Multicast HASH table */
2467 /* clear the old settings from the multicast hash table */
2468 ATL2_WRITE_REG(hw, REG_RX_HASH_TABLE, 0);
2469 ATL2_WRITE_REG_ARRAY(hw, REG_RX_HASH_TABLE, 1, 0);
2470
2471 atl2_init_flash_opcode(hw);
2472
2473 ret_val = atl2_phy_init(hw);
2474
2475 return ret_val;
2476}
2477
2478/*
2479 * Detects the current speed and duplex settings of the hardware.
2480 *
2481 * hw - Struct containing variables accessed by shared code
2482 * speed - Speed of the connection
2483 * duplex - Duplex setting of the connection
2484 */
2485static s32 atl2_get_speed_and_duplex(struct atl2_hw *hw, u16 *speed,
2486 u16 *duplex)
2487{
2488 s32 ret_val;
2489 u16 phy_data;
2490
2491 /* Read PHY Specific Status Register (17) */
2492 ret_val = atl2_read_phy_reg(hw, MII_ATLX_PSSR, &phy_data);
2493 if (ret_val)
2494 return ret_val;
2495
2496 if (!(phy_data & MII_ATLX_PSSR_SPD_DPLX_RESOLVED))
2497 return ATLX_ERR_PHY_RES;
2498
2499 switch (phy_data & MII_ATLX_PSSR_SPEED) {
2500 case MII_ATLX_PSSR_100MBS:
2501 *speed = SPEED_100;
2502 break;
2503 case MII_ATLX_PSSR_10MBS:
2504 *speed = SPEED_10;
2505 break;
2506 default:
2507 return ATLX_ERR_PHY_SPEED;
2508 break;
2509 }
2510
2511 if (phy_data & MII_ATLX_PSSR_DPLX)
2512 *duplex = FULL_DUPLEX;
2513 else
2514 *duplex = HALF_DUPLEX;
2515
2516 return 0;
2517}
2518
2519/*
2520 * Reads the value from a PHY register
2521 * hw - Struct containing variables accessed by shared code
2522 * reg_addr - address of the PHY register to read
2523 */
2524static s32 atl2_read_phy_reg(struct atl2_hw *hw, u16 reg_addr, u16 *phy_data)
2525{
2526 u32 val;
2527 int i;
2528
2529 val = ((u32)(reg_addr & MDIO_REG_ADDR_MASK)) << MDIO_REG_ADDR_SHIFT |
2530 MDIO_START |
2531 MDIO_SUP_PREAMBLE |
2532 MDIO_RW |
2533 MDIO_CLK_25_4 << MDIO_CLK_SEL_SHIFT;
2534 ATL2_WRITE_REG(hw, REG_MDIO_CTRL, val);
2535
2536 wmb();
2537
2538 for (i = 0; i < MDIO_WAIT_TIMES; i++) {
2539 udelay(2);
2540 val = ATL2_READ_REG(hw, REG_MDIO_CTRL);
2541 if (!(val & (MDIO_START | MDIO_BUSY)))
2542 break;
2543 wmb();
2544 }
2545 if (!(val & (MDIO_START | MDIO_BUSY))) {
2546 *phy_data = (u16)val;
2547 return 0;
2548 }
2549
2550 return ATLX_ERR_PHY;
2551}
2552
2553/*
2554 * Writes a value to a PHY register
2555 * hw - Struct containing variables accessed by shared code
2556 * reg_addr - address of the PHY register to write
2557 * data - data to write to the PHY
2558 */
2559static s32 atl2_write_phy_reg(struct atl2_hw *hw, u32 reg_addr, u16 phy_data)
2560{
2561 int i;
2562 u32 val;
2563
2564 val = ((u32)(phy_data & MDIO_DATA_MASK)) << MDIO_DATA_SHIFT |
2565 (reg_addr & MDIO_REG_ADDR_MASK) << MDIO_REG_ADDR_SHIFT |
2566 MDIO_SUP_PREAMBLE |
2567 MDIO_START |
2568 MDIO_CLK_25_4 << MDIO_CLK_SEL_SHIFT;
2569 ATL2_WRITE_REG(hw, REG_MDIO_CTRL, val);
2570
2571 wmb();
2572
2573 for (i = 0; i < MDIO_WAIT_TIMES; i++) {
2574 udelay(2);
2575 val = ATL2_READ_REG(hw, REG_MDIO_CTRL);
2576 if (!(val & (MDIO_START | MDIO_BUSY)))
2577 break;
2578
2579 wmb();
2580 }
2581
2582 if (!(val & (MDIO_START | MDIO_BUSY)))
2583 return 0;
2584
2585 return ATLX_ERR_PHY;
2586}
2587
2588/*
2589 * Configures PHY autoneg and flow control advertisement settings
2590 *
2591 * hw - Struct containing variables accessed by shared code
2592 */
2593static s32 atl2_phy_setup_autoneg_adv(struct atl2_hw *hw)
2594{
2595 s32 ret_val;
2596 s16 mii_autoneg_adv_reg;
2597
2598 /* Read the MII Auto-Neg Advertisement Register (Address 4). */
2599 mii_autoneg_adv_reg = MII_AR_DEFAULT_CAP_MASK;
2600
2601 /* Need to parse autoneg_advertised and set up
2602 * the appropriate PHY registers. First we will parse for
2603 * autoneg_advertised software override. Since we can advertise
2604 * a plethora of combinations, we need to check each bit
2605 * individually.
2606 */
2607
2608 /* First we clear all the 10/100 mb speed bits in the Auto-Neg
2609 * Advertisement Register (Address 4) and the 1000 mb speed bits in
2610 * the 1000Base-T Control Register (Address 9). */
2611 mii_autoneg_adv_reg &= ~MII_AR_SPEED_MASK;
2612
2613 /* Need to parse MediaType and setup the
2614 * appropriate PHY registers. */
2615 switch (hw->MediaType) {
2616 case MEDIA_TYPE_AUTO_SENSOR:
2617 mii_autoneg_adv_reg |=
2618 (MII_AR_10T_HD_CAPS |
2619 MII_AR_10T_FD_CAPS |
2620 MII_AR_100TX_HD_CAPS|
2621 MII_AR_100TX_FD_CAPS);
2622 hw->autoneg_advertised =
2623 ADVERTISE_10_HALF |
2624 ADVERTISE_10_FULL |
2625 ADVERTISE_100_HALF|
2626 ADVERTISE_100_FULL;
2627 break;
2628 case MEDIA_TYPE_100M_FULL:
2629 mii_autoneg_adv_reg |= MII_AR_100TX_FD_CAPS;
2630 hw->autoneg_advertised = ADVERTISE_100_FULL;
2631 break;
2632 case MEDIA_TYPE_100M_HALF:
2633 mii_autoneg_adv_reg |= MII_AR_100TX_HD_CAPS;
2634 hw->autoneg_advertised = ADVERTISE_100_HALF;
2635 break;
2636 case MEDIA_TYPE_10M_FULL:
2637 mii_autoneg_adv_reg |= MII_AR_10T_FD_CAPS;
2638 hw->autoneg_advertised = ADVERTISE_10_FULL;
2639 break;
2640 default:
2641 mii_autoneg_adv_reg |= MII_AR_10T_HD_CAPS;
2642 hw->autoneg_advertised = ADVERTISE_10_HALF;
2643 break;
2644 }
2645
2646 /* flow control fixed to enable all */
2647 mii_autoneg_adv_reg |= (MII_AR_ASM_DIR | MII_AR_PAUSE);
2648
2649 hw->mii_autoneg_adv_reg = mii_autoneg_adv_reg;
2650
2651 ret_val = atl2_write_phy_reg(hw, MII_ADVERTISE, mii_autoneg_adv_reg);
2652
2653 if (ret_val)
2654 return ret_val;
2655
2656 return 0;
2657}
2658
2659/*
2660 * Resets the PHY and make all config validate
2661 *
2662 * hw - Struct containing variables accessed by shared code
2663 *
2664 * Sets bit 15 and 12 of the MII Control regiser (for F001 bug)
2665 */
2666static s32 atl2_phy_commit(struct atl2_hw *hw)
2667{
2668 s32 ret_val;
2669 u16 phy_data;
2670
2671 phy_data = MII_CR_RESET | MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG;
2672 ret_val = atl2_write_phy_reg(hw, MII_BMCR, phy_data);
2673 if (ret_val) {
2674 u32 val;
2675 int i;
2676 /* pcie serdes link may be down ! */
2677 for (i = 0; i < 25; i++) {
2678 msleep(1);
2679 val = ATL2_READ_REG(hw, REG_MDIO_CTRL);
2680 if (!(val & (MDIO_START | MDIO_BUSY)))
2681 break;
2682 }
2683
2684 if (0 != (val & (MDIO_START | MDIO_BUSY))) {
2685 printk(KERN_ERR "atl2: PCIe link down for at least 25ms !\n");
2686 return ret_val;
2687 }
2688 }
2689 return 0;
2690}
2691
2692static s32 atl2_phy_init(struct atl2_hw *hw)
2693{
2694 s32 ret_val;
2695 u16 phy_val;
2696
2697 if (hw->phy_configured)
2698 return 0;
2699
2700 /* Enable PHY */
2701 ATL2_WRITE_REGW(hw, REG_PHY_ENABLE, 1);
2702 ATL2_WRITE_FLUSH(hw);
2703 msleep(1);
2704
2705 /* check if the PHY is in powersaving mode */
2706 atl2_write_phy_reg(hw, MII_DBG_ADDR, 0);
2707 atl2_read_phy_reg(hw, MII_DBG_DATA, &phy_val);
2708
2709 /* 024E / 124E 0r 0274 / 1274 ? */
2710 if (phy_val & 0x1000) {
2711 phy_val &= ~0x1000;
2712 atl2_write_phy_reg(hw, MII_DBG_DATA, phy_val);
2713 }
2714
2715 msleep(1);
2716
2717 /*Enable PHY LinkChange Interrupt */
2718 ret_val = atl2_write_phy_reg(hw, 18, 0xC00);
2719 if (ret_val)
2720 return ret_val;
2721
2722 /* setup AutoNeg parameters */
2723 ret_val = atl2_phy_setup_autoneg_adv(hw);
2724 if (ret_val)
2725 return ret_val;
2726
2727 /* SW.Reset & En-Auto-Neg to restart Auto-Neg */
2728 ret_val = atl2_phy_commit(hw);
2729 if (ret_val)
2730 return ret_val;
2731
2732 hw->phy_configured = true;
2733
2734 return ret_val;
2735}
2736
2737static void atl2_set_mac_addr(struct atl2_hw *hw)
2738{
2739 u32 value;
2740 /* 00-0B-6A-F6-00-DC
2741 * 0: 6AF600DC 1: 000B
2742 * low dword */
2743 value = (((u32)hw->mac_addr[2]) << 24) |
2744 (((u32)hw->mac_addr[3]) << 16) |
2745 (((u32)hw->mac_addr[4]) << 8) |
2746 (((u32)hw->mac_addr[5]));
2747 ATL2_WRITE_REG_ARRAY(hw, REG_MAC_STA_ADDR, 0, value);
2748 /* hight dword */
2749 value = (((u32)hw->mac_addr[0]) << 8) |
2750 (((u32)hw->mac_addr[1]));
2751 ATL2_WRITE_REG_ARRAY(hw, REG_MAC_STA_ADDR, 1, value);
2752}
2753
2754/*
2755 * check_eeprom_exist
2756 * return 0 if eeprom exist
2757 */
2758static int atl2_check_eeprom_exist(struct atl2_hw *hw)
2759{
2760 u32 value;
2761
2762 value = ATL2_READ_REG(hw, REG_SPI_FLASH_CTRL);
2763 if (value & SPI_FLASH_CTRL_EN_VPD) {
2764 value &= ~SPI_FLASH_CTRL_EN_VPD;
2765 ATL2_WRITE_REG(hw, REG_SPI_FLASH_CTRL, value);
2766 }
2767 value = ATL2_READ_REGW(hw, REG_PCIE_CAP_LIST);
2768 return ((value & 0xFF00) == 0x6C00) ? 0 : 1;
2769}
2770
2771/* FIXME: This doesn't look right. -- CHS */
2772static bool atl2_write_eeprom(struct atl2_hw *hw, u32 offset, u32 value)
2773{
2774 return true;
2775}
2776
2777static bool atl2_read_eeprom(struct atl2_hw *hw, u32 Offset, u32 *pValue)
2778{
2779 int i;
2780 u32 Control;
2781
2782 if (Offset & 0x3)
2783 return false; /* address do not align */
2784
2785 ATL2_WRITE_REG(hw, REG_VPD_DATA, 0);
2786 Control = (Offset & VPD_CAP_VPD_ADDR_MASK) << VPD_CAP_VPD_ADDR_SHIFT;
2787 ATL2_WRITE_REG(hw, REG_VPD_CAP, Control);
2788
2789 for (i = 0; i < 10; i++) {
2790 msleep(2);
2791 Control = ATL2_READ_REG(hw, REG_VPD_CAP);
2792 if (Control & VPD_CAP_VPD_FLAG)
2793 break;
2794 }
2795
2796 if (Control & VPD_CAP_VPD_FLAG) {
2797 *pValue = ATL2_READ_REG(hw, REG_VPD_DATA);
2798 return true;
2799 }
2800 return false; /* timeout */
2801}
2802
2803static void atl2_force_ps(struct atl2_hw *hw)
2804{
2805 u16 phy_val;
2806
2807 atl2_write_phy_reg(hw, MII_DBG_ADDR, 0);
2808 atl2_read_phy_reg(hw, MII_DBG_DATA, &phy_val);
2809 atl2_write_phy_reg(hw, MII_DBG_DATA, phy_val | 0x1000);
2810
2811 atl2_write_phy_reg(hw, MII_DBG_ADDR, 2);
2812 atl2_write_phy_reg(hw, MII_DBG_DATA, 0x3000);
2813 atl2_write_phy_reg(hw, MII_DBG_ADDR, 3);
2814 atl2_write_phy_reg(hw, MII_DBG_DATA, 0);
2815}
2816
2817/* This is the only thing that needs to be changed to adjust the
2818 * maximum number of ports that the driver can manage.
2819 */
2820#define ATL2_MAX_NIC 4
2821
2822#define OPTION_UNSET -1
2823#define OPTION_DISABLED 0
2824#define OPTION_ENABLED 1
2825
2826/* All parameters are treated the same, as an integer array of values.
2827 * This macro just reduces the need to repeat the same declaration code
2828 * over and over (plus this helps to avoid typo bugs).
2829 */
2830#define ATL2_PARAM_INIT {[0 ... ATL2_MAX_NIC] = OPTION_UNSET}
2831#ifndef module_param_array
2832/* Module Parameters are always initialized to -1, so that the driver
2833 * can tell the difference between no user specified value or the
2834 * user asking for the default value.
2835 * The true default values are loaded in when atl2_check_options is called.
2836 *
2837 * This is a GCC extension to ANSI C.
2838 * See the item "Labeled Elements in Initializers" in the section
2839 * "Extensions to the C Language Family" of the GCC documentation.
2840 */
2841
2842#define ATL2_PARAM(X, desc) \
2843 static const int __devinitdata X[ATL2_MAX_NIC + 1] = ATL2_PARAM_INIT; \
2844 MODULE_PARM(X, "1-" __MODULE_STRING(ATL2_MAX_NIC) "i"); \
2845 MODULE_PARM_DESC(X, desc);
2846#else
2847#define ATL2_PARAM(X, desc) \
2848 static int __devinitdata X[ATL2_MAX_NIC+1] = ATL2_PARAM_INIT; \
b79d8fff 2849 static unsigned int num_##X; \
452c1ce2
CS		 2850 module_param_array_named(X, X, int, &num_##X, 0); \
2851 MODULE_PARM_DESC(X, desc);
2852#endif
2853
2854/*
2855 * Transmit Memory Size
2856 * Valid Range: 64-2048
2857 * Default Value: 128
2858 */
2859#define ATL2_MIN_TX_MEMSIZE 4 /* 4KB */
2860#define ATL2_MAX_TX_MEMSIZE 64 /* 64KB */
2861#define ATL2_DEFAULT_TX_MEMSIZE 8 /* 8KB */
2862ATL2_PARAM(TxMemSize, "Bytes of Transmit Memory");
2863
2864/*
2865 * Receive Memory Block Count
2866 * Valid Range: 16-512
2867 * Default Value: 128
2868 */
2869#define ATL2_MIN_RXD_COUNT 16
2870#define ATL2_MAX_RXD_COUNT 512
2871#define ATL2_DEFAULT_RXD_COUNT 64
2872ATL2_PARAM(RxMemBlock, "Number of receive memory block");
2873
2874/*
2875 * User Specified MediaType Override
2876 *
2877 * Valid Range: 0-5
2878 * - 0 - auto-negotiate at all supported speeds
2879 * - 1 - only link at 1000Mbps Full Duplex
2880 * - 2 - only link at 100Mbps Full Duplex
2881 * - 3 - only link at 100Mbps Half Duplex
2882 * - 4 - only link at 10Mbps Full Duplex
2883 * - 5 - only link at 10Mbps Half Duplex
2884 * Default Value: 0
2885 */
2886ATL2_PARAM(MediaType, "MediaType Select");
2887
2888/*
2889 * Interrupt Moderate Timer in units of 2048 ns (~2 us)
2890 * Valid Range: 10-65535
2891 * Default Value: 45000(90ms)
2892 */
2893#define INT_MOD_DEFAULT_CNT 100 /* 200us */
2894#define INT_MOD_MAX_CNT 65000
2895#define INT_MOD_MIN_CNT 50
2896ATL2_PARAM(IntModTimer, "Interrupt Moderator Timer");
2897
2898/*
2899 * FlashVendor
2900 * Valid Range: 0-2
2901 * 0 - Atmel
2902 * 1 - SST
2903 * 2 - ST
2904 */
2905ATL2_PARAM(FlashVendor, "SPI Flash Vendor");
2906
2907#define AUTONEG_ADV_DEFAULT 0x2F
2908#define AUTONEG_ADV_MASK 0x2F
2909#define FLOW_CONTROL_DEFAULT FLOW_CONTROL_FULL
2910
2911#define FLASH_VENDOR_DEFAULT 0
2912#define FLASH_VENDOR_MIN 0
2913#define FLASH_VENDOR_MAX 2
2914
2915struct atl2_option {
2916 enum { enable_option, range_option, list_option } type;
2917 char *name;
2918 char *err;
2919 int def;
2920 union {
2921 struct { /* range_option info */
2922 int min;
2923 int max;
2924 } r;
2925 struct { /* list_option info */
2926 int nr;
2927 struct atl2_opt_list { int i; char *str; } *p;
2928 } l;
2929 } arg;
2930};
2931
2932static int __devinit atl2_validate_option(int *value, struct atl2_option *opt)
2933{
2934 int i;
2935 struct atl2_opt_list *ent;
2936
2937 if (*value == OPTION_UNSET) {
2938 *value = opt->def;
2939 return 0;
2940 }
2941
2942 switch (opt->type) {
2943 case enable_option:
2944 switch (*value) {
2945 case OPTION_ENABLED:
2946 printk(KERN_INFO "%s Enabled\n", opt->name);
2947 return 0;
2948 break;
2949 case OPTION_DISABLED:
2950 printk(KERN_INFO "%s Disabled\n", opt->name);
2951 return 0;
2952 break;
2953 }
2954 break;
2955 case range_option:
2956 if (*value >= opt->arg.r.min && *value <= opt->arg.r.max) {
2957 printk(KERN_INFO "%s set to %i\n", opt->name, *value);
2958 return 0;
2959 }
2960 break;
2961 case list_option:
2962 for (i = 0; i < opt->arg.l.nr; i++) {
2963 ent = &opt->arg.l.p[i];
2964 if (*value == ent->i) {
2965 if (ent->str[0] != '\0')
2966 printk(KERN_INFO "%s\n", ent->str);
2967 return 0;
2968 }
2969 }
2970 break;
2971 default:
2972 BUG();
2973 }
2974
2975 printk(KERN_INFO "Invalid %s specified (%i) %s\n",
2976 opt->name, *value, opt->err);
2977 *value = opt->def;
2978 return -1;
2979}
2980
2981/*
2982 * atl2_check_options - Range Checking for Command Line Parameters
2983 * @adapter: board private structure
2984 *
2985 * This routine checks all command line parameters for valid user
2986 * input. If an invalid value is given, or if no user specified
2987 * value exists, a default value is used. The final value is stored
2988 * in a variable in the adapter structure.
2989 */
2990static void __devinit atl2_check_options(struct atl2_adapter *adapter)
2991{
2992 int val;
2993 struct atl2_option opt;
2994 int bd = adapter->bd_number;
2995 if (bd >= ATL2_MAX_NIC) {
2996 printk(KERN_NOTICE "Warning: no configuration for board #%i\n",
2997 bd);
2998 printk(KERN_NOTICE "Using defaults for all values\n");
2999#ifndef module_param_array
3000 bd = ATL2_MAX_NIC;
3001#endif
3002 }
3003
3004 /* Bytes of Transmit Memory */
3005 opt.type = range_option;
3006 opt.name = "Bytes of Transmit Memory";
3007 opt.err = "using default of " __MODULE_STRING(ATL2_DEFAULT_TX_MEMSIZE);
3008 opt.def = ATL2_DEFAULT_TX_MEMSIZE;
3009 opt.arg.r.min = ATL2_MIN_TX_MEMSIZE;
3010 opt.arg.r.max = ATL2_MAX_TX_MEMSIZE;
3011#ifdef module_param_array
3012 if (num_TxMemSize > bd) {
3013#endif
3014 val = TxMemSize[bd];
3015 atl2_validate_option(&val, &opt);
3016 adapter->txd_ring_size = ((u32) val) * 1024;
3017#ifdef module_param_array
3018 } else
3019 adapter->txd_ring_size = ((u32)opt.def) * 1024;
3020#endif
3021 /* txs ring size: */
3022 adapter->txs_ring_size = adapter->txd_ring_size / 128;
3023 if (adapter->txs_ring_size > 160)
3024 adapter->txs_ring_size = 160;
3025
3026 /* Receive Memory Block Count */
3027 opt.type = range_option;
3028 opt.name = "Number of receive memory block";
3029 opt.err = "using default of " __MODULE_STRING(ATL2_DEFAULT_RXD_COUNT);
3030 opt.def = ATL2_DEFAULT_RXD_COUNT;
3031 opt.arg.r.min = ATL2_MIN_RXD_COUNT;
3032 opt.arg.r.max = ATL2_MAX_RXD_COUNT;
3033#ifdef module_param_array
3034 if (num_RxMemBlock > bd) {
3035#endif
3036 val = RxMemBlock[bd];
3037 atl2_validate_option(&val, &opt);
3038 adapter->rxd_ring_size = (u32)val;
3039 /* FIXME */
3040 /* ((u16)val)&~1; */ /* even number */
3041#ifdef module_param_array
3042 } else
3043 adapter->rxd_ring_size = (u32)opt.def;
3044#endif
3045 /* init RXD Flow control value */
3046 adapter->hw.fc_rxd_hi = (adapter->rxd_ring_size / 8) * 7;
3047 adapter->hw.fc_rxd_lo = (ATL2_MIN_RXD_COUNT / 8) >
3048 (adapter->rxd_ring_size / 12) ? (ATL2_MIN_RXD_COUNT / 8) :
3049 (adapter->rxd_ring_size / 12);
3050
3051 /* Interrupt Moderate Timer */
3052 opt.type = range_option;
3053 opt.name = "Interrupt Moderate Timer";
3054 opt.err = "using default of " __MODULE_STRING(INT_MOD_DEFAULT_CNT);
3055 opt.def = INT_MOD_DEFAULT_CNT;
3056 opt.arg.r.min = INT_MOD_MIN_CNT;
3057 opt.arg.r.max = INT_MOD_MAX_CNT;
3058#ifdef module_param_array
3059 if (num_IntModTimer > bd) {
3060#endif
3061 val = IntModTimer[bd];
3062 atl2_validate_option(&val, &opt);
3063 adapter->imt = (u16) val;
3064#ifdef module_param_array
3065 } else
3066 adapter->imt = (u16)(opt.def);
3067#endif
3068 /* Flash Vendor */
3069 opt.type = range_option;
3070 opt.name = "SPI Flash Vendor";
3071 opt.err = "using default of " __MODULE_STRING(FLASH_VENDOR_DEFAULT);
3072 opt.def = FLASH_VENDOR_DEFAULT;
3073 opt.arg.r.min = FLASH_VENDOR_MIN;
3074 opt.arg.r.max = FLASH_VENDOR_MAX;
3075#ifdef module_param_array
3076 if (num_FlashVendor > bd) {
3077#endif
3078 val = FlashVendor[bd];
3079 atl2_validate_option(&val, &opt);
3080 adapter->hw.flash_vendor = (u8) val;
3081#ifdef module_param_array
3082 } else
3083 adapter->hw.flash_vendor = (u8)(opt.def);
3084#endif
3085 /* MediaType */
3086 opt.type = range_option;
3087 opt.name = "Speed/Duplex Selection";
3088 opt.err = "using default of " __MODULE_STRING(MEDIA_TYPE_AUTO_SENSOR);
3089 opt.def = MEDIA_TYPE_AUTO_SENSOR;
3090 opt.arg.r.min = MEDIA_TYPE_AUTO_SENSOR;
3091 opt.arg.r.max = MEDIA_TYPE_10M_HALF;
3092#ifdef module_param_array
3093 if (num_MediaType > bd) {
3094#endif
3095 val = MediaType[bd];
3096 atl2_validate_option(&val, &opt);
3097 adapter->hw.MediaType = (u16) val;
3098#ifdef module_param_array
3099 } else
3100 adapter->hw.MediaType = (u16)(opt.def);
3101#endif
3102}
Linux kernel - Deliverables
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