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drivers/net: request_irq - Remove unnecessary leading & from second arg
[deliverable/linux.git] / drivers / net / atlx / atl2.c
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452c1ce2
CS		 1/*
2 * Copyright(c) 2006 - 2007 Atheros Corporation. All rights reserved.
3 * Copyright(c) 2007 - 2008 Chris Snook <csnook@redhat.com>
4 *
5 * Derived from Intel e1000 driver
6 * Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the Free
10 * Software Foundation; either version 2 of the License, or (at your option)
11 * any later version.
12 *
13 * This program is distributed in the hope that it will be useful, but WITHOUT
14 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 * more details.
17 *
18 * You should have received a copy of the GNU General Public License along with
19 * this program; if not, write to the Free Software Foundation, Inc., 59
20 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
21 */
22
23#include <asm/atomic.h>
24#include <linux/crc32.h>
25#include <linux/dma-mapping.h>
26#include <linux/etherdevice.h>
27#include <linux/ethtool.h>
28#include <linux/hardirq.h>
29#include <linux/if_vlan.h>
30#include <linux/in.h>
31#include <linux/interrupt.h>
32#include <linux/ip.h>
33#include <linux/irqflags.h>
34#include <linux/irqreturn.h>
35#include <linux/mii.h>
36#include <linux/net.h>
37#include <linux/netdevice.h>
38#include <linux/pci.h>
39#include <linux/pci_ids.h>
40#include <linux/pm.h>
41#include <linux/skbuff.h>
42#include <linux/spinlock.h>
43#include <linux/string.h>
44#include <linux/tcp.h>
45#include <linux/timer.h>
46#include <linux/types.h>
47#include <linux/workqueue.h>
48
49#include "atl2.h"
50
51#define ATL2_DRV_VERSION "2.2.3"
52
53static char atl2_driver_name[] = "atl2";
54static const char atl2_driver_string[] = "Atheros(R) L2 Ethernet Driver";
55static char atl2_copyright[] = "Copyright (c) 2007 Atheros Corporation.";
56static char atl2_driver_version[] = ATL2_DRV_VERSION;
57
58MODULE_AUTHOR("Atheros Corporation <xiong.huang@atheros.com>, Chris Snook <csnook@redhat.com>");
59MODULE_DESCRIPTION("Atheros Fast Ethernet Network Driver");
60MODULE_LICENSE("GPL");
61MODULE_VERSION(ATL2_DRV_VERSION);
62
63/*
64 * atl2_pci_tbl - PCI Device ID Table
65 */
66static struct pci_device_id atl2_pci_tbl[] = {
67 {PCI_DEVICE(PCI_VENDOR_ID_ATTANSIC, PCI_DEVICE_ID_ATTANSIC_L2)},
68 /* required last entry */
69 {0,}
70};
71MODULE_DEVICE_TABLE(pci, atl2_pci_tbl);
72
73static void atl2_set_ethtool_ops(struct net_device *netdev);
74
75static void atl2_check_options(struct atl2_adapter *adapter);
76
77/*
78 * atl2_sw_init - Initialize general software structures (struct atl2_adapter)
79 * @adapter: board private structure to initialize
80 *
81 * atl2_sw_init initializes the Adapter private data structure.
82 * Fields are initialized based on PCI device information and
83 * OS network device settings (MTU size).
84 */
85static int __devinit atl2_sw_init(struct atl2_adapter *adapter)
86{
87 struct atl2_hw *hw = &adapter->hw;
88 struct pci_dev *pdev = adapter->pdev;
89
90 /* PCI config space info */
91 hw->vendor_id = pdev->vendor;
92 hw->device_id = pdev->device;
93 hw->subsystem_vendor_id = pdev->subsystem_vendor;
94 hw->subsystem_id = pdev->subsystem_device;
95
96 pci_read_config_byte(pdev, PCI_REVISION_ID, &hw->revision_id);
97 pci_read_config_word(pdev, PCI_COMMAND, &hw->pci_cmd_word);
98
99 adapter->wol = 0;
100 adapter->ict = 50000; /* ~100ms */
101 adapter->link_speed = SPEED_0; /* hardware init */
102 adapter->link_duplex = FULL_DUPLEX;
103
104 hw->phy_configured = false;
105 hw->preamble_len = 7;
106 hw->ipgt = 0x60;
107 hw->min_ifg = 0x50;
108 hw->ipgr1 = 0x40;
109 hw->ipgr2 = 0x60;
110 hw->retry_buf = 2;
111 hw->max_retry = 0xf;
112 hw->lcol = 0x37;
113 hw->jam_ipg = 7;
114 hw->fc_rxd_hi = 0;
115 hw->fc_rxd_lo = 0;
116 hw->max_frame_size = adapter->netdev->mtu;
117
118 spin_lock_init(&adapter->stats_lock);
452c1ce2
CS		 119
120 set_bit(__ATL2_DOWN, &adapter->flags);
121
122 return 0;
123}
124
125/*
126 * atl2_set_multi - Multicast and Promiscuous mode set
127 * @netdev: network interface device structure
128 *
129 * The set_multi entry point is called whenever the multicast address
130 * list or the network interface flags are updated. This routine is
131 * responsible for configuring the hardware for proper multicast,
132 * promiscuous mode, and all-multi behavior.
133 */
134static void atl2_set_multi(struct net_device *netdev)
135{
136 struct atl2_adapter *adapter = netdev_priv(netdev);
137 struct atl2_hw *hw = &adapter->hw;
138 struct dev_mc_list *mc_ptr;
139 u32 rctl;
140 u32 hash_value;
141
142 /* Check for Promiscuous and All Multicast modes */
143 rctl = ATL2_READ_REG(hw, REG_MAC_CTRL);
144
145 if (netdev->flags & IFF_PROMISC) {
146 rctl |= MAC_CTRL_PROMIS_EN;
147 } else if (netdev->flags & IFF_ALLMULTI) {
148 rctl |= MAC_CTRL_MC_ALL_EN;
149 rctl &= ~MAC_CTRL_PROMIS_EN;
150 } else
151 rctl &= ~(MAC_CTRL_PROMIS_EN | MAC_CTRL_MC_ALL_EN);
152
153 ATL2_WRITE_REG(hw, REG_MAC_CTRL, rctl);
154
155 /* clear the old settings from the multicast hash table */
156 ATL2_WRITE_REG(hw, REG_RX_HASH_TABLE, 0);
157 ATL2_WRITE_REG_ARRAY(hw, REG_RX_HASH_TABLE, 1, 0);
158
159 /* comoute mc addresses' hash value ,and put it into hash table */
160 for (mc_ptr = netdev->mc_list; mc_ptr; mc_ptr = mc_ptr->next) {
161 hash_value = atl2_hash_mc_addr(hw, mc_ptr->dmi_addr);
162 atl2_hash_set(hw, hash_value);
163 }
164}
165
166static void init_ring_ptrs(struct atl2_adapter *adapter)
167{
168 /* Read / Write Ptr Initialize: */
169 adapter->txd_write_ptr = 0;
170 atomic_set(&adapter->txd_read_ptr, 0);
171
172 adapter->rxd_read_ptr = 0;
173 adapter->rxd_write_ptr = 0;
174
175 atomic_set(&adapter->txs_write_ptr, 0);
176 adapter->txs_next_clear = 0;
177}
178
179/*
180 * atl2_configure - Configure Transmit&Receive Unit after Reset
181 * @adapter: board private structure
182 *
183 * Configure the Tx /Rx unit of the MAC after a reset.
184 */
185static int atl2_configure(struct atl2_adapter *adapter)
186{
187 struct atl2_hw *hw = &adapter->hw;
188 u32 value;
189
190 /* clear interrupt status */
191 ATL2_WRITE_REG(&adapter->hw, REG_ISR, 0xffffffff);
192
193 /* set MAC Address */
194 value = (((u32)hw->mac_addr[2]) << 24) |
195 (((u32)hw->mac_addr[3]) << 16) |
196 (((u32)hw->mac_addr[4]) << 8) |
197 (((u32)hw->mac_addr[5]));
198 ATL2_WRITE_REG(hw, REG_MAC_STA_ADDR, value);
199 value = (((u32)hw->mac_addr[0]) << 8) |
200 (((u32)hw->mac_addr[1]));
201 ATL2_WRITE_REG(hw, (REG_MAC_STA_ADDR+4), value);
202
203 /* HI base address */
204 ATL2_WRITE_REG(hw, REG_DESC_BASE_ADDR_HI,
205 (u32)((adapter->ring_dma & 0xffffffff00000000ULL) >> 32));
206
207 /* LO base address */
208 ATL2_WRITE_REG(hw, REG_TXD_BASE_ADDR_LO,
209 (u32)(adapter->txd_dma & 0x00000000ffffffffULL));
210 ATL2_WRITE_REG(hw, REG_TXS_BASE_ADDR_LO,
211 (u32)(adapter->txs_dma & 0x00000000ffffffffULL));
212 ATL2_WRITE_REG(hw, REG_RXD_BASE_ADDR_LO,
213 (u32)(adapter->rxd_dma & 0x00000000ffffffffULL));
214
215 /* element count */
216 ATL2_WRITE_REGW(hw, REG_TXD_MEM_SIZE, (u16)(adapter->txd_ring_size/4));
217 ATL2_WRITE_REGW(hw, REG_TXS_MEM_SIZE, (u16)adapter->txs_ring_size);
218 ATL2_WRITE_REGW(hw, REG_RXD_BUF_NUM, (u16)adapter->rxd_ring_size);
219
220 /* config Internal SRAM */
221/*
222 ATL2_WRITE_REGW(hw, REG_SRAM_TXRAM_END, sram_tx_end);
223 ATL2_WRITE_REGW(hw, REG_SRAM_TXRAM_END, sram_rx_end);
224*/
225
226 /* config IPG/IFG */
227 value = (((u32)hw->ipgt & MAC_IPG_IFG_IPGT_MASK) <<
228 MAC_IPG_IFG_IPGT_SHIFT) |
229 (((u32)hw->min_ifg & MAC_IPG_IFG_MIFG_MASK) <<
230 MAC_IPG_IFG_MIFG_SHIFT) |
231 (((u32)hw->ipgr1 & MAC_IPG_IFG_IPGR1_MASK) <<
232 MAC_IPG_IFG_IPGR1_SHIFT)|
233 (((u32)hw->ipgr2 & MAC_IPG_IFG_IPGR2_MASK) <<
234 MAC_IPG_IFG_IPGR2_SHIFT);
235 ATL2_WRITE_REG(hw, REG_MAC_IPG_IFG, value);
236
237 /* config Half-Duplex Control */
238 value = ((u32)hw->lcol & MAC_HALF_DUPLX_CTRL_LCOL_MASK) |
239 (((u32)hw->max_retry & MAC_HALF_DUPLX_CTRL_RETRY_MASK) <<
240 MAC_HALF_DUPLX_CTRL_RETRY_SHIFT) |
241 MAC_HALF_DUPLX_CTRL_EXC_DEF_EN |
242 (0xa << MAC_HALF_DUPLX_CTRL_ABEBT_SHIFT) |
243 (((u32)hw->jam_ipg & MAC_HALF_DUPLX_CTRL_JAMIPG_MASK) <<
244 MAC_HALF_DUPLX_CTRL_JAMIPG_SHIFT);
245 ATL2_WRITE_REG(hw, REG_MAC_HALF_DUPLX_CTRL, value);
246
247 /* set Interrupt Moderator Timer */
248 ATL2_WRITE_REGW(hw, REG_IRQ_MODU_TIMER_INIT, adapter->imt);
249 ATL2_WRITE_REG(hw, REG_MASTER_CTRL, MASTER_CTRL_ITIMER_EN);
250
251 /* set Interrupt Clear Timer */
252 ATL2_WRITE_REGW(hw, REG_CMBDISDMA_TIMER, adapter->ict);
253
254 /* set MTU */
255 ATL2_WRITE_REG(hw, REG_MTU, adapter->netdev->mtu +
256 ENET_HEADER_SIZE + VLAN_SIZE + ETHERNET_FCS_SIZE);
257
258 /* 1590 */
259 ATL2_WRITE_REG(hw, REG_TX_CUT_THRESH, 0x177);
260
261 /* flow control */
262 ATL2_WRITE_REGW(hw, REG_PAUSE_ON_TH, hw->fc_rxd_hi);
263 ATL2_WRITE_REGW(hw, REG_PAUSE_OFF_TH, hw->fc_rxd_lo);
264
265 /* Init mailbox */
266 ATL2_WRITE_REGW(hw, REG_MB_TXD_WR_IDX, (u16)adapter->txd_write_ptr);
267 ATL2_WRITE_REGW(hw, REG_MB_RXD_RD_IDX, (u16)adapter->rxd_read_ptr);
268
269 /* enable DMA read/write */
270 ATL2_WRITE_REGB(hw, REG_DMAR, DMAR_EN);
271 ATL2_WRITE_REGB(hw, REG_DMAW, DMAW_EN);
272
273 value = ATL2_READ_REG(&adapter->hw, REG_ISR);
274 if ((value & ISR_PHY_LINKDOWN) != 0)
275 value = 1; /* config failed */
276 else
277 value = 0;
278
279 /* clear all interrupt status */
280 ATL2_WRITE_REG(&adapter->hw, REG_ISR, 0x3fffffff);
281 ATL2_WRITE_REG(&adapter->hw, REG_ISR, 0);
282 return value;
283}
284
285/*
286 * atl2_setup_ring_resources - allocate Tx / RX descriptor resources
287 * @adapter: board private structure
288 *
289 * Return 0 on success, negative on failure
290 */
291static s32 atl2_setup_ring_resources(struct atl2_adapter *adapter)
292{
293 struct pci_dev *pdev = adapter->pdev;
294 int size;
295 u8 offset = 0;
296
297 /* real ring DMA buffer */
298 adapter->ring_size = size =
299 adapter->txd_ring_size * 1 + 7 + /* dword align */
300 adapter->txs_ring_size * 4 + 7 + /* dword align */
301 adapter->rxd_ring_size * 1536 + 127; /* 128bytes align */
302
303 adapter->ring_vir_addr = pci_alloc_consistent(pdev, size,
304 &adapter->ring_dma);
305 if (!adapter->ring_vir_addr)
306 return -ENOMEM;
307 memset(adapter->ring_vir_addr, 0, adapter->ring_size);
308
309 /* Init TXD Ring */
310 adapter->txd_dma = adapter->ring_dma ;
311 offset = (adapter->txd_dma & 0x7) ? (8 - (adapter->txd_dma & 0x7)) : 0;
312 adapter->txd_dma += offset;
313 adapter->txd_ring = (struct tx_pkt_header *) (adapter->ring_vir_addr +
314 offset);
315
316 /* Init TXS Ring */
317 adapter->txs_dma = adapter->txd_dma + adapter->txd_ring_size;
318 offset = (adapter->txs_dma & 0x7) ? (8 - (adapter->txs_dma & 0x7)) : 0;
319 adapter->txs_dma += offset;
320 adapter->txs_ring = (struct tx_pkt_status *)
321 (((u8 *)adapter->txd_ring) + (adapter->txd_ring_size + offset));
322
323 /* Init RXD Ring */
324 adapter->rxd_dma = adapter->txs_dma + adapter->txs_ring_size * 4;
325 offset = (adapter->rxd_dma & 127) ?
326 (128 - (adapter->rxd_dma & 127)) : 0;
327 if (offset > 7)
328 offset -= 8;
329 else
330 offset += (128 - 8);
331
332 adapter->rxd_dma += offset;
333 adapter->rxd_ring = (struct rx_desc *) (((u8 *)adapter->txs_ring) +
334 (adapter->txs_ring_size * 4 + offset));
335
336/*
337 * Read / Write Ptr Initialize:
338 * init_ring_ptrs(adapter);
339 */
340 return 0;
341}
342
343/*
344 * atl2_irq_enable - Enable default interrupt generation settings
345 * @adapter: board private structure
346 */
347static inline void atl2_irq_enable(struct atl2_adapter *adapter)
348{
349 ATL2_WRITE_REG(&adapter->hw, REG_IMR, IMR_NORMAL_MASK);
350 ATL2_WRITE_FLUSH(&adapter->hw);
351}
352
353/*
354 * atl2_irq_disable - Mask off interrupt generation on the NIC
355 * @adapter: board private structure
356 */
357static inline void atl2_irq_disable(struct atl2_adapter *adapter)
358{
359 ATL2_WRITE_REG(&adapter->hw, REG_IMR, 0);
360 ATL2_WRITE_FLUSH(&adapter->hw);
361 synchronize_irq(adapter->pdev->irq);
362}
363
364#ifdef NETIF_F_HW_VLAN_TX
365static void atl2_vlan_rx_register(struct net_device *netdev,
366 struct vlan_group *grp)
367{
368 struct atl2_adapter *adapter = netdev_priv(netdev);
369 u32 ctrl;
370
371 atl2_irq_disable(adapter);
372 adapter->vlgrp = grp;
373
374 if (grp) {
375 /* enable VLAN tag insert/strip */
376 ctrl = ATL2_READ_REG(&adapter->hw, REG_MAC_CTRL);
377 ctrl |= MAC_CTRL_RMV_VLAN;
378 ATL2_WRITE_REG(&adapter->hw, REG_MAC_CTRL, ctrl);
379 } else {
380 /* disable VLAN tag insert/strip */
381 ctrl = ATL2_READ_REG(&adapter->hw, REG_MAC_CTRL);
382 ctrl &= ~MAC_CTRL_RMV_VLAN;
383 ATL2_WRITE_REG(&adapter->hw, REG_MAC_CTRL, ctrl);
384 }
385
386 atl2_irq_enable(adapter);
387}
388
389static void atl2_restore_vlan(struct atl2_adapter *adapter)
390{
391 atl2_vlan_rx_register(adapter->netdev, adapter->vlgrp);
392}
393#endif
394
395static void atl2_intr_rx(struct atl2_adapter *adapter)
396{
397 struct net_device *netdev = adapter->netdev;
398 struct rx_desc *rxd;
399 struct sk_buff *skb;
400
401 do {
402 rxd = adapter->rxd_ring+adapter->rxd_write_ptr;
403 if (!rxd->status.update)
404 break; /* end of tx */
405
406 /* clear this flag at once */
407 rxd->status.update = 0;
408
409 if (rxd->status.ok && rxd->status.pkt_size >= 60) {
410 int rx_size = (int)(rxd->status.pkt_size - 4);
411 /* alloc new buffer */
89d71a66 412 skb = netdev_alloc_skb_ip_align(netdev, rx_size);
452c1ce2
CS		 413 if (NULL == skb) {
414 printk(KERN_WARNING
415 "%s: Mem squeeze, deferring packet.\n",
416 netdev->name);
417 /*
418 * Check that some rx space is free. If not,
419 * free one and mark stats->rx_dropped++.
420 */
02e71731 421 netdev->stats.rx_dropped++;
452c1ce2
CS		 422 break;
423 }
452c1ce2
CS		 424 skb->dev = netdev;
425 memcpy(skb->data, rxd->packet, rx_size);
426 skb_put(skb, rx_size);
427 skb->protocol = eth_type_trans(skb, netdev);
428#ifdef NETIF_F_HW_VLAN_TX
429 if (adapter->vlgrp && (rxd->status.vlan)) {
430 u16 vlan_tag = (rxd->status.vtag>>4) |
431 ((rxd->status.vtag&7) << 13) |
432 ((rxd->status.vtag&8) << 9);
433 vlan_hwaccel_rx(skb, adapter->vlgrp, vlan_tag);
434 } else
435#endif
436 netif_rx(skb);
02e71731
SH		 437 netdev->stats.rx_bytes += rx_size;
438 netdev->stats.rx_packets++;
452c1ce2 439 } else {
02e71731 440 netdev->stats.rx_errors++;
452c1ce2
CS		 441
442 if (rxd->status.ok && rxd->status.pkt_size <= 60)
02e71731 443 netdev->stats.rx_length_errors++;
452c1ce2 444 if (rxd->status.mcast)
02e71731 445 netdev->stats.multicast++;
452c1ce2 446 if (rxd->status.crc)
02e71731 447 netdev->stats.rx_crc_errors++;
452c1ce2 448 if (rxd->status.align)
02e71731 449 netdev->stats.rx_frame_errors++;
452c1ce2
CS		 450 }
451
452 /* advance write ptr */
453 if (++adapter->rxd_write_ptr == adapter->rxd_ring_size)
454 adapter->rxd_write_ptr = 0;
455 } while (1);
456
457 /* update mailbox? */
458 adapter->rxd_read_ptr = adapter->rxd_write_ptr;
459 ATL2_WRITE_REGW(&adapter->hw, REG_MB_RXD_RD_IDX, adapter->rxd_read_ptr);
460}
461
462static void atl2_intr_tx(struct atl2_adapter *adapter)
463{
02e71731 464 struct net_device *netdev = adapter->netdev;
452c1ce2
CS		 465 u32 txd_read_ptr;
466 u32 txs_write_ptr;
467 struct tx_pkt_status *txs;
468 struct tx_pkt_header *txph;
469 int free_hole = 0;
470
471 do {
472 txs_write_ptr = (u32) atomic_read(&adapter->txs_write_ptr);
473 txs = adapter->txs_ring + txs_write_ptr;
474 if (!txs->update)
475 break; /* tx stop here */
476
477 free_hole = 1;
478 txs->update = 0;
479
480 if (++txs_write_ptr == adapter->txs_ring_size)
481 txs_write_ptr = 0;
482 atomic_set(&adapter->txs_write_ptr, (int)txs_write_ptr);
483
484 txd_read_ptr = (u32) atomic_read(&adapter->txd_read_ptr);
485 txph = (struct tx_pkt_header *)
486 (((u8 *)adapter->txd_ring) + txd_read_ptr);
487
488 if (txph->pkt_size != txs->pkt_size) {
489 struct tx_pkt_status *old_txs = txs;
490 printk(KERN_WARNING
491 "%s: txs packet size not consistent with txd"
492 " txd_:0x%08x, txs_:0x%08x!\n",
493 adapter->netdev->name,
494 *(u32 *)txph, *(u32 *)txs);
495 printk(KERN_WARNING
496 "txd read ptr: 0x%x\n",
497 txd_read_ptr);
498 txs = adapter->txs_ring + txs_write_ptr;
499 printk(KERN_WARNING
500 "txs-behind:0x%08x\n",
501 *(u32 *)txs);
502 if (txs_write_ptr < 2) {
503 txs = adapter->txs_ring +
504 (adapter->txs_ring_size +
505 txs_write_ptr - 2);
506 } else {
507 txs = adapter->txs_ring + (txs_write_ptr - 2);
508 }
509 printk(KERN_WARNING
510 "txs-before:0x%08x\n",
511 *(u32 *)txs);
512 txs = old_txs;
513 }
514
515 /* 4for TPH */
516 txd_read_ptr += (((u32)(txph->pkt_size) + 7) & ~3);
517 if (txd_read_ptr >= adapter->txd_ring_size)
518 txd_read_ptr -= adapter->txd_ring_size;
519
520 atomic_set(&adapter->txd_read_ptr, (int)txd_read_ptr);
521
522 /* tx statistics: */
e2f092ff 523 if (txs->ok) {
02e71731
SH		 524 netdev->stats.tx_bytes += txs->pkt_size;
525 netdev->stats.tx_packets++;
e2f092ff 526 }
452c1ce2 527 else
02e71731 528 netdev->stats.tx_errors++;
452c1ce2
CS		 529
530 if (txs->defer)
02e71731 531 netdev->stats.collisions++;
452c1ce2 532 if (txs->abort_col)
02e71731 533 netdev->stats.tx_aborted_errors++;
452c1ce2 534 if (txs->late_col)
02e71731 535 netdev->stats.tx_window_errors++;
452c1ce2 536 if (txs->underun)
02e71731 537 netdev->stats.tx_fifo_errors++;
452c1ce2
CS		 538 } while (1);
539
540 if (free_hole) {
541 if (netif_queue_stopped(adapter->netdev) &&
542 netif_carrier_ok(adapter->netdev))
543 netif_wake_queue(adapter->netdev);
544 }
545}
546
547static void atl2_check_for_link(struct atl2_adapter *adapter)
548{
549 struct net_device *netdev = adapter->netdev;
550 u16 phy_data = 0;
551
552 spin_lock(&adapter->stats_lock);
553 atl2_read_phy_reg(&adapter->hw, MII_BMSR, &phy_data);
554 atl2_read_phy_reg(&adapter->hw, MII_BMSR, &phy_data);
555 spin_unlock(&adapter->stats_lock);
556
557 /* notify upper layer link down ASAP */
558 if (!(phy_data & BMSR_LSTATUS)) { /* Link Down */
559 if (netif_carrier_ok(netdev)) { /* old link state: Up */
560 printk(KERN_INFO "%s: %s NIC Link is Down\n",
561 atl2_driver_name, netdev->name);
562 adapter->link_speed = SPEED_0;
563 netif_carrier_off(netdev);
564 netif_stop_queue(netdev);
565 }
566 }
567 schedule_work(&adapter->link_chg_task);
568}
569
570static inline void atl2_clear_phy_int(struct atl2_adapter *adapter)
571{
572 u16 phy_data;
573 spin_lock(&adapter->stats_lock);
574 atl2_read_phy_reg(&adapter->hw, 19, &phy_data);
575 spin_unlock(&adapter->stats_lock);
576}
577
578/*
579 * atl2_intr - Interrupt Handler
580 * @irq: interrupt number
581 * @data: pointer to a network interface device structure
582 * @pt_regs: CPU registers structure
583 */
584static irqreturn_t atl2_intr(int irq, void *data)
585{
586 struct atl2_adapter *adapter = netdev_priv(data);
587 struct atl2_hw *hw = &adapter->hw;
588 u32 status;
589
590 status = ATL2_READ_REG(hw, REG_ISR);
591 if (0 == status)
592 return IRQ_NONE;
593
594 /* link event */
595 if (status & ISR_PHY)
596 atl2_clear_phy_int(adapter);
597
598 /* clear ISR status, and Enable CMB DMA/Disable Interrupt */
599 ATL2_WRITE_REG(hw, REG_ISR, status | ISR_DIS_INT);
600
601 /* check if PCIE PHY Link down */
602 if (status & ISR_PHY_LINKDOWN) {
603 if (netif_running(adapter->netdev)) { /* reset MAC */
604 ATL2_WRITE_REG(hw, REG_ISR, 0);
605 ATL2_WRITE_REG(hw, REG_IMR, 0);
606 ATL2_WRITE_FLUSH(hw);
607 schedule_work(&adapter->reset_task);
608 return IRQ_HANDLED;
609 }
610 }
611
612 /* check if DMA read/write error? */
613 if (status & (ISR_DMAR_TO_RST | ISR_DMAW_TO_RST)) {
614 ATL2_WRITE_REG(hw, REG_ISR, 0);
615 ATL2_WRITE_REG(hw, REG_IMR, 0);
616 ATL2_WRITE_FLUSH(hw);
617 schedule_work(&adapter->reset_task);
618 return IRQ_HANDLED;
619 }
620
621 /* link event */
622 if (status & (ISR_PHY | ISR_MANUAL)) {
02e71731 623 adapter->netdev->stats.tx_carrier_errors++;
452c1ce2
CS		 624 atl2_check_for_link(adapter);
625 }
626
627 /* transmit event */
628 if (status & ISR_TX_EVENT)
629 atl2_intr_tx(adapter);
630
631 /* rx exception */
632 if (status & ISR_RX_EVENT)
633 atl2_intr_rx(adapter);
634
635 /* re-enable Interrupt */
636 ATL2_WRITE_REG(&adapter->hw, REG_ISR, 0);
637 return IRQ_HANDLED;
638}
639
640static int atl2_request_irq(struct atl2_adapter *adapter)
641{
642 struct net_device *netdev = adapter->netdev;
643 int flags, err = 0;
644
645 flags = IRQF_SHARED;
452c1ce2
CS		 646 adapter->have_msi = true;
647 err = pci_enable_msi(adapter->pdev);
648 if (err)
649 adapter->have_msi = false;
650
651 if (adapter->have_msi)
652 flags &= ~IRQF_SHARED;
452c1ce2 653
a0607fd3 654 return request_irq(adapter->pdev->irq, atl2_intr, flags, netdev->name,
452c1ce2
CS		 655 netdev);
656}
657
658/*
659 * atl2_free_ring_resources - Free Tx / RX descriptor Resources
660 * @adapter: board private structure
661 *
662 * Free all transmit software resources
663 */
664static void atl2_free_ring_resources(struct atl2_adapter *adapter)
665{
666 struct pci_dev *pdev = adapter->pdev;
667 pci_free_consistent(pdev, adapter->ring_size, adapter->ring_vir_addr,
668 adapter->ring_dma);
669}
670
671/*
672 * atl2_open - Called when a network interface is made active
673 * @netdev: network interface device structure
674 *
675 * Returns 0 on success, negative value on failure
676 *
677 * The open entry point is called when a network interface is made
678 * active by the system (IFF_UP). At this point all resources needed
679 * for transmit and receive operations are allocated, the interrupt
680 * handler is registered with the OS, the watchdog timer is started,
681 * and the stack is notified that the interface is ready.
682 */
683static int atl2_open(struct net_device *netdev)
684{
685 struct atl2_adapter *adapter = netdev_priv(netdev);
686 int err;
687 u32 val;
688
689 /* disallow open during test */
690 if (test_bit(__ATL2_TESTING, &adapter->flags))
691 return -EBUSY;
692
693 /* allocate transmit descriptors */
694 err = atl2_setup_ring_resources(adapter);
695 if (err)
696 return err;
697
698 err = atl2_init_hw(&adapter->hw);
699 if (err) {
700 err = -EIO;
701 goto err_init_hw;
702 }
703
704 /* hardware has been reset, we need to reload some things */
705 atl2_set_multi(netdev);
706 init_ring_ptrs(adapter);
707
708#ifdef NETIF_F_HW_VLAN_TX
709 atl2_restore_vlan(adapter);
710#endif
711
712 if (atl2_configure(adapter)) {
713 err = -EIO;
714 goto err_config;
715 }
716
717 err = atl2_request_irq(adapter);
718 if (err)
719 goto err_req_irq;
720
721 clear_bit(__ATL2_DOWN, &adapter->flags);
722
e053b628 723 mod_timer(&adapter->watchdog_timer, round_jiffies(jiffies + 4*HZ));
452c1ce2
CS		 724
725 val = ATL2_READ_REG(&adapter->hw, REG_MASTER_CTRL);
726 ATL2_WRITE_REG(&adapter->hw, REG_MASTER_CTRL,
727 val | MASTER_CTRL_MANUAL_INT);
728
729 atl2_irq_enable(adapter);
730
731 return 0;
732
733err_init_hw:
734err_req_irq:
735err_config:
736 atl2_free_ring_resources(adapter);
737 atl2_reset_hw(&adapter->hw);
738
739 return err;
740}
741
742static void atl2_down(struct atl2_adapter *adapter)
743{
744 struct net_device *netdev = adapter->netdev;
745
746 /* signal that we're down so the interrupt handler does not
747 * reschedule our watchdog timer */
748 set_bit(__ATL2_DOWN, &adapter->flags);
749
452c1ce2 750 netif_tx_disable(netdev);
452c1ce2
CS		 751
752 /* reset MAC to disable all RX/TX */
753 atl2_reset_hw(&adapter->hw);
754 msleep(1);
755
756 atl2_irq_disable(adapter);
757
758 del_timer_sync(&adapter->watchdog_timer);
759 del_timer_sync(&adapter->phy_config_timer);
760 clear_bit(0, &adapter->cfg_phy);
761
762 netif_carrier_off(netdev);
763 adapter->link_speed = SPEED_0;
764 adapter->link_duplex = -1;
765}
766
767static void atl2_free_irq(struct atl2_adapter *adapter)
768{
769 struct net_device *netdev = adapter->netdev;
770
771 free_irq(adapter->pdev->irq, netdev);
772
773#ifdef CONFIG_PCI_MSI
774 if (adapter->have_msi)
775 pci_disable_msi(adapter->pdev);
776#endif
777}
778
779/*
780 * atl2_close - Disables a network interface
781 * @netdev: network interface device structure
782 *
783 * Returns 0, this is not allowed to fail
784 *
785 * The close entry point is called when an interface is de-activated
786 * by the OS. The hardware is still under the drivers control, but
787 * needs to be disabled. A global MAC reset is issued to stop the
788 * hardware, and all transmit and receive resources are freed.
789 */
790static int atl2_close(struct net_device *netdev)
791{
792 struct atl2_adapter *adapter = netdev_priv(netdev);
793
794 WARN_ON(test_bit(__ATL2_RESETTING, &adapter->flags));
795
796 atl2_down(adapter);
797 atl2_free_irq(adapter);
798 atl2_free_ring_resources(adapter);
799
800 return 0;
801}
802
803static inline int TxsFreeUnit(struct atl2_adapter *adapter)
804{
805 u32 txs_write_ptr = (u32) atomic_read(&adapter->txs_write_ptr);
806
807 return (adapter->txs_next_clear >= txs_write_ptr) ?
808 (int) (adapter->txs_ring_size - adapter->txs_next_clear +
809 txs_write_ptr - 1) :
810 (int) (txs_write_ptr - adapter->txs_next_clear - 1);
811}
812
813static inline int TxdFreeBytes(struct atl2_adapter *adapter)
814{
815 u32 txd_read_ptr = (u32)atomic_read(&adapter->txd_read_ptr);
816
817 return (adapter->txd_write_ptr >= txd_read_ptr) ?
818 (int) (adapter->txd_ring_size - adapter->txd_write_ptr +
819 txd_read_ptr - 1) :
820 (int) (txd_read_ptr - adapter->txd_write_ptr - 1);
821}
822
61357325
SH		 823static netdev_tx_t atl2_xmit_frame(struct sk_buff *skb,
824 struct net_device *netdev)
452c1ce2
CS		 825{
826 struct atl2_adapter *adapter = netdev_priv(netdev);
452c1ce2
CS		 827 struct tx_pkt_header *txph;
828 u32 offset, copy_len;
829 int txs_unused;
830 int txbuf_unused;
831
832 if (test_bit(__ATL2_DOWN, &adapter->flags)) {
833 dev_kfree_skb_any(skb);
834 return NETDEV_TX_OK;
835 }
836
837 if (unlikely(skb->len <= 0)) {
838 dev_kfree_skb_any(skb);
839 return NETDEV_TX_OK;
840 }
841
452c1ce2
CS		 842 txs_unused = TxsFreeUnit(adapter);
843 txbuf_unused = TxdFreeBytes(adapter);
844
845 if (skb->len + sizeof(struct tx_pkt_header) + 4 > txbuf_unused ||
846 txs_unused < 1) {
847 /* not enough resources */
848 netif_stop_queue(netdev);
452c1ce2
CS		 849 return NETDEV_TX_BUSY;
850 }
851
852 offset = adapter->txd_write_ptr;
853
854 txph = (struct tx_pkt_header *) (((u8 *)adapter->txd_ring) + offset);
855
856 *(u32 *)txph = 0;
857 txph->pkt_size = skb->len;
858
859 offset += 4;
860 if (offset >= adapter->txd_ring_size)
861 offset -= adapter->txd_ring_size;
862 copy_len = adapter->txd_ring_size - offset;
863 if (copy_len >= skb->len) {
864 memcpy(((u8 *)adapter->txd_ring) + offset, skb->data, skb->len);
865 offset += ((u32)(skb->len + 3) & ~3);
866 } else {
867 memcpy(((u8 *)adapter->txd_ring)+offset, skb->data, copy_len);
868 memcpy((u8 *)adapter->txd_ring, skb->data+copy_len,
869 skb->len-copy_len);
870 offset = ((u32)(skb->len-copy_len + 3) & ~3);
871 }
872#ifdef NETIF_F_HW_VLAN_TX
873 if (adapter->vlgrp && vlan_tx_tag_present(skb)) {
874 u16 vlan_tag = vlan_tx_tag_get(skb);
875 vlan_tag = (vlan_tag << 4) |
876 (vlan_tag >> 13) |
877 ((vlan_tag >> 9) & 0x8);
878 txph->ins_vlan = 1;
879 txph->vlan = vlan_tag;
880 }
881#endif
882 if (offset >= adapter->txd_ring_size)
883 offset -= adapter->txd_ring_size;
884 adapter->txd_write_ptr = offset;
885
886 /* clear txs before send */
887 adapter->txs_ring[adapter->txs_next_clear].update = 0;
888 if (++adapter->txs_next_clear == adapter->txs_ring_size)
889 adapter->txs_next_clear = 0;
890
891 ATL2_WRITE_REGW(&adapter->hw, REG_MB_TXD_WR_IDX,
892 (adapter->txd_write_ptr >> 2));
893
87241840 894 mmiowb();
452c1ce2
CS		 895 netdev->trans_start = jiffies;
896 dev_kfree_skb_any(skb);
897 return NETDEV_TX_OK;
898}
899
452c1ce2
CS		 900/*
901 * atl2_change_mtu - Change the Maximum Transfer Unit
902 * @netdev: network interface device structure
903 * @new_mtu: new value for maximum frame size
904 *
905 * Returns 0 on success, negative on failure
906 */
907static int atl2_change_mtu(struct net_device *netdev, int new_mtu)
908{
909 struct atl2_adapter *adapter = netdev_priv(netdev);
910 struct atl2_hw *hw = &adapter->hw;
911
912 if ((new_mtu < 40) || (new_mtu > (ETH_DATA_LEN + VLAN_SIZE)))
913 return -EINVAL;
914
915 /* set MTU */
916 if (hw->max_frame_size != new_mtu) {
917 netdev->mtu = new_mtu;
918 ATL2_WRITE_REG(hw, REG_MTU, new_mtu + ENET_HEADER_SIZE +
919 VLAN_SIZE + ETHERNET_FCS_SIZE);
920 }
921
922 return 0;
923}
924
925/*
926 * atl2_set_mac - Change the Ethernet Address of the NIC
927 * @netdev: network interface device structure
928 * @p: pointer to an address structure
929 *
930 * Returns 0 on success, negative on failure
931 */
932static int atl2_set_mac(struct net_device *netdev, void *p)
933{
934 struct atl2_adapter *adapter = netdev_priv(netdev);
935 struct sockaddr *addr = p;
936
937 if (!is_valid_ether_addr(addr->sa_data))
938 return -EADDRNOTAVAIL;
939
940 if (netif_running(netdev))
941 return -EBUSY;
942
943 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
944 memcpy(adapter->hw.mac_addr, addr->sa_data, netdev->addr_len);
945
946 atl2_set_mac_addr(&adapter->hw);
947
948 return 0;
949}
950
951/*
952 * atl2_mii_ioctl -
953 * @netdev:
954 * @ifreq:
955 * @cmd:
956 */
957static int atl2_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
958{
959 struct atl2_adapter *adapter = netdev_priv(netdev);
960 struct mii_ioctl_data *data = if_mii(ifr);
961 unsigned long flags;
962
963 switch (cmd) {
964 case SIOCGMIIPHY:
965 data->phy_id = 0;
966 break;
967 case SIOCGMIIREG:
452c1ce2
CS		 968 spin_lock_irqsave(&adapter->stats_lock, flags);
969 if (atl2_read_phy_reg(&adapter->hw,
970 data->reg_num & 0x1F, &data->val_out)) {
971 spin_unlock_irqrestore(&adapter->stats_lock, flags);
972 return -EIO;
973 }
974 spin_unlock_irqrestore(&adapter->stats_lock, flags);
975 break;
976 case SIOCSMIIREG:
452c1ce2
CS		 977 if (data->reg_num & ~(0x1F))
978 return -EFAULT;
979 spin_lock_irqsave(&adapter->stats_lock, flags);
980 if (atl2_write_phy_reg(&adapter->hw, data->reg_num,
981 data->val_in)) {
982 spin_unlock_irqrestore(&adapter->stats_lock, flags);
983 return -EIO;
984 }
985 spin_unlock_irqrestore(&adapter->stats_lock, flags);
986 break;
987 default:
988 return -EOPNOTSUPP;
989 }
990 return 0;
991}
992
993/*
994 * atl2_ioctl -
995 * @netdev:
996 * @ifreq:
997 * @cmd:
998 */
999static int atl2_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
1000{
1001 switch (cmd) {
1002 case SIOCGMIIPHY:
1003 case SIOCGMIIREG:
1004 case SIOCSMIIREG:
1005 return atl2_mii_ioctl(netdev, ifr, cmd);
1006#ifdef ETHTOOL_OPS_COMPAT
1007 case SIOCETHTOOL:
1008 return ethtool_ioctl(ifr);
1009#endif
1010 default:
1011 return -EOPNOTSUPP;
1012 }
1013}
1014
1015/*
1016 * atl2_tx_timeout - Respond to a Tx Hang
1017 * @netdev: network interface device structure
1018 */
1019static void atl2_tx_timeout(struct net_device *netdev)
1020{
1021 struct atl2_adapter *adapter = netdev_priv(netdev);
1022
1023 /* Do the reset outside of interrupt context */
1024 schedule_work(&adapter->reset_task);
1025}
1026
1027/*
1028 * atl2_watchdog - Timer Call-back
1029 * @data: pointer to netdev cast into an unsigned long
1030 */
1031static void atl2_watchdog(unsigned long data)
1032{
1033 struct atl2_adapter *adapter = (struct atl2_adapter *) data;
452c1ce2
CS		 1034
1035 if (!test_bit(__ATL2_DOWN, &adapter->flags)) {
02e71731
SH		 1036 u32 drop_rxd, drop_rxs;
1037 unsigned long flags;
1038
452c1ce2
CS		 1039 spin_lock_irqsave(&adapter->stats_lock, flags);
1040 drop_rxd = ATL2_READ_REG(&adapter->hw, REG_STS_RXD_OV);
1041 drop_rxs = ATL2_READ_REG(&adapter->hw, REG_STS_RXS_OV);
452c1ce2
CS		 1042 spin_unlock_irqrestore(&adapter->stats_lock, flags);
1043
02e71731
SH		 1044 adapter->netdev->stats.rx_over_errors += drop_rxd + drop_rxs;
1045
452c1ce2 1046 /* Reset the timer */
e053b628
SH		 1047 mod_timer(&adapter->watchdog_timer,
1048 round_jiffies(jiffies + 4 * HZ));
452c1ce2
CS		 1049 }
1050}
1051
1052/*
1053 * atl2_phy_config - Timer Call-back
1054 * @data: pointer to netdev cast into an unsigned long
1055 */
1056static void atl2_phy_config(unsigned long data)
1057{
1058 struct atl2_adapter *adapter = (struct atl2_adapter *) data;
1059 struct atl2_hw *hw = &adapter->hw;
1060 unsigned long flags;
1061
1062 spin_lock_irqsave(&adapter->stats_lock, flags);
1063 atl2_write_phy_reg(hw, MII_ADVERTISE, hw->mii_autoneg_adv_reg);
1064 atl2_write_phy_reg(hw, MII_BMCR, MII_CR_RESET | MII_CR_AUTO_NEG_EN |
1065 MII_CR_RESTART_AUTO_NEG);
1066 spin_unlock_irqrestore(&adapter->stats_lock, flags);
1067 clear_bit(0, &adapter->cfg_phy);
1068}
1069
1070static int atl2_up(struct atl2_adapter *adapter)
1071{
1072 struct net_device *netdev = adapter->netdev;
1073 int err = 0;
1074 u32 val;
1075
1076 /* hardware has been reset, we need to reload some things */
1077
1078 err = atl2_init_hw(&adapter->hw);
1079 if (err) {
1080 err = -EIO;
1081 return err;
1082 }
1083
1084 atl2_set_multi(netdev);
1085 init_ring_ptrs(adapter);
1086
1087#ifdef NETIF_F_HW_VLAN_TX
1088 atl2_restore_vlan(adapter);
1089#endif
1090
1091 if (atl2_configure(adapter)) {
1092 err = -EIO;
1093 goto err_up;
1094 }
1095
1096 clear_bit(__ATL2_DOWN, &adapter->flags);
1097
1098 val = ATL2_READ_REG(&adapter->hw, REG_MASTER_CTRL);
1099 ATL2_WRITE_REG(&adapter->hw, REG_MASTER_CTRL, val |
1100 MASTER_CTRL_MANUAL_INT);
1101
1102 atl2_irq_enable(adapter);
1103
1104err_up:
1105 return err;
1106}
1107
1108static void atl2_reinit_locked(struct atl2_adapter *adapter)
1109{
1110 WARN_ON(in_interrupt());
1111 while (test_and_set_bit(__ATL2_RESETTING, &adapter->flags))
1112 msleep(1);
1113 atl2_down(adapter);
1114 atl2_up(adapter);
1115 clear_bit(__ATL2_RESETTING, &adapter->flags);
1116}
1117
1118static void atl2_reset_task(struct work_struct *work)
1119{
1120 struct atl2_adapter *adapter;
1121 adapter = container_of(work, struct atl2_adapter, reset_task);
1122
1123 atl2_reinit_locked(adapter);
1124}
1125
1126static void atl2_setup_mac_ctrl(struct atl2_adapter *adapter)
1127{
1128 u32 value;
1129 struct atl2_hw *hw = &adapter->hw;
1130 struct net_device *netdev = adapter->netdev;
1131
1132 /* Config MAC CTRL Register */
1133 value = MAC_CTRL_TX_EN | MAC_CTRL_RX_EN | MAC_CTRL_MACLP_CLK_PHY;
1134
1135 /* duplex */
1136 if (FULL_DUPLEX == adapter->link_duplex)
1137 value |= MAC_CTRL_DUPLX;
1138
1139 /* flow control */
1140 value |= (MAC_CTRL_TX_FLOW | MAC_CTRL_RX_FLOW);
1141
1142 /* PAD & CRC */
1143 value |= (MAC_CTRL_ADD_CRC | MAC_CTRL_PAD);
1144
1145 /* preamble length */
1146 value |= (((u32)adapter->hw.preamble_len & MAC_CTRL_PRMLEN_MASK) <<
1147 MAC_CTRL_PRMLEN_SHIFT);
1148
1149 /* vlan */
1150 if (adapter->vlgrp)
1151 value |= MAC_CTRL_RMV_VLAN;
1152
1153 /* filter mode */
1154 value |= MAC_CTRL_BC_EN;
1155 if (netdev->flags & IFF_PROMISC)
1156 value |= MAC_CTRL_PROMIS_EN;
1157 else if (netdev->flags & IFF_ALLMULTI)
1158 value |= MAC_CTRL_MC_ALL_EN;
1159
1160 /* half retry buffer */
1161 value |= (((u32)(adapter->hw.retry_buf &
1162 MAC_CTRL_HALF_LEFT_BUF_MASK)) << MAC_CTRL_HALF_LEFT_BUF_SHIFT);
1163
1164 ATL2_WRITE_REG(hw, REG_MAC_CTRL, value);
1165}
1166
1167static int atl2_check_link(struct atl2_adapter *adapter)
1168{
1169 struct atl2_hw *hw = &adapter->hw;
1170 struct net_device *netdev = adapter->netdev;
1171 int ret_val;
1172 u16 speed, duplex, phy_data;
1173 int reconfig = 0;
1174
1175 /* MII_BMSR must read twise */
1176 atl2_read_phy_reg(hw, MII_BMSR, &phy_data);
1177 atl2_read_phy_reg(hw, MII_BMSR, &phy_data);
1178 if (!(phy_data&BMSR_LSTATUS)) { /* link down */
1179 if (netif_carrier_ok(netdev)) { /* old link state: Up */
1180 u32 value;
1181 /* disable rx */
1182 value = ATL2_READ_REG(hw, REG_MAC_CTRL);
1183 value &= ~MAC_CTRL_RX_EN;
1184 ATL2_WRITE_REG(hw, REG_MAC_CTRL, value);
1185 adapter->link_speed = SPEED_0;
1186 netif_carrier_off(netdev);
1187 netif_stop_queue(netdev);
1188 }
1189 return 0;
1190 }
1191
1192 /* Link Up */
1193 ret_val = atl2_get_speed_and_duplex(hw, &speed, &duplex);
1194 if (ret_val)
1195 return ret_val;
1196 switch (hw->MediaType) {
1197 case MEDIA_TYPE_100M_FULL:
1198 if (speed != SPEED_100 || duplex != FULL_DUPLEX)
1199 reconfig = 1;
1200 break;
1201 case MEDIA_TYPE_100M_HALF:
1202 if (speed != SPEED_100 || duplex != HALF_DUPLEX)
1203 reconfig = 1;
1204 break;
1205 case MEDIA_TYPE_10M_FULL:
1206 if (speed != SPEED_10 || duplex != FULL_DUPLEX)
1207 reconfig = 1;
1208 break;
1209 case MEDIA_TYPE_10M_HALF:
1210 if (speed != SPEED_10 || duplex != HALF_DUPLEX)
1211 reconfig = 1;
1212 break;
1213 }
1214 /* link result is our setting */
1215 if (reconfig == 0) {
1216 if (adapter->link_speed != speed ||
1217 adapter->link_duplex != duplex) {
1218 adapter->link_speed = speed;
1219 adapter->link_duplex = duplex;
1220 atl2_setup_mac_ctrl(adapter);
1221 printk(KERN_INFO "%s: %s NIC Link is Up<%d Mbps %s>\n",
1222 atl2_driver_name, netdev->name,
1223 adapter->link_speed,
1224 adapter->link_duplex == FULL_DUPLEX ?
1225 "Full Duplex" : "Half Duplex");
1226 }
1227
1228 if (!netif_carrier_ok(netdev)) { /* Link down -> Up */
1229 netif_carrier_on(netdev);
1230 netif_wake_queue(netdev);
1231 }
1232 return 0;
1233 }
1234
1235 /* change original link status */
1236 if (netif_carrier_ok(netdev)) {
1237 u32 value;
1238 /* disable rx */
1239 value = ATL2_READ_REG(hw, REG_MAC_CTRL);
1240 value &= ~MAC_CTRL_RX_EN;
1241 ATL2_WRITE_REG(hw, REG_MAC_CTRL, value);
1242
1243 adapter->link_speed = SPEED_0;
1244 netif_carrier_off(netdev);
1245 netif_stop_queue(netdev);
1246 }
1247
1248 /* auto-neg, insert timer to re-config phy
1249 * (if interval smaller than 5 seconds, something strange) */
1250 if (!test_bit(__ATL2_DOWN, &adapter->flags)) {
1251 if (!test_and_set_bit(0, &adapter->cfg_phy))
e053b628
SH		 1252 mod_timer(&adapter->phy_config_timer,
1253 round_jiffies(jiffies + 5 * HZ));
452c1ce2
CS		 1254 }
1255
1256 return 0;
1257}
1258
1259/*
1260 * atl2_link_chg_task - deal with link change event Out of interrupt context
1261 * @netdev: network interface device structure
1262 */
1263static void atl2_link_chg_task(struct work_struct *work)
1264{
1265 struct atl2_adapter *adapter;
1266 unsigned long flags;
1267
1268 adapter = container_of(work, struct atl2_adapter, link_chg_task);
1269
1270 spin_lock_irqsave(&adapter->stats_lock, flags);
1271 atl2_check_link(adapter);
1272 spin_unlock_irqrestore(&adapter->stats_lock, flags);
1273}
1274
1275static void atl2_setup_pcicmd(struct pci_dev *pdev)
1276{
1277 u16 cmd;
1278
1279 pci_read_config_word(pdev, PCI_COMMAND, &cmd);
1280
1281 if (cmd & PCI_COMMAND_INTX_DISABLE)
1282 cmd &= ~PCI_COMMAND_INTX_DISABLE;
1283 if (cmd & PCI_COMMAND_IO)
1284 cmd &= ~PCI_COMMAND_IO;
1285 if (0 == (cmd & PCI_COMMAND_MEMORY))
1286 cmd |= PCI_COMMAND_MEMORY;
1287 if (0 == (cmd & PCI_COMMAND_MASTER))
1288 cmd |= PCI_COMMAND_MASTER;
1289 pci_write_config_word(pdev, PCI_COMMAND, cmd);
1290
1291 /*
1292 * some motherboards BIOS(PXE/EFI) driver may set PME
1293 * while they transfer control to OS (Windows/Linux)
1294 * so we should clear this bit before NIC work normally
1295 */
1296 pci_write_config_dword(pdev, REG_PM_CTRLSTAT, 0);
1297}
1298
8d1b1fc9
KH		 1299#ifdef CONFIG_NET_POLL_CONTROLLER
1300static void atl2_poll_controller(struct net_device *netdev)
1301{
1302 disable_irq(netdev->irq);
1303 atl2_intr(netdev->irq, netdev);
1304 enable_irq(netdev->irq);
1305}
1306#endif
1307
825a84d1
SH		 1308
1309static const struct net_device_ops atl2_netdev_ops = {
1310 .ndo_open = atl2_open,
1311 .ndo_stop = atl2_close,
00829823 1312 .ndo_start_xmit = atl2_xmit_frame,
825a84d1
SH		 1313 .ndo_set_multicast_list = atl2_set_multi,
1314 .ndo_validate_addr = eth_validate_addr,
1315 .ndo_set_mac_address = atl2_set_mac,
1316 .ndo_change_mtu = atl2_change_mtu,
1317 .ndo_do_ioctl = atl2_ioctl,
1318 .ndo_tx_timeout = atl2_tx_timeout,
1319 .ndo_vlan_rx_register = atl2_vlan_rx_register,
1320#ifdef CONFIG_NET_POLL_CONTROLLER
1321 .ndo_poll_controller = atl2_poll_controller,
1322#endif
1323};
1324
452c1ce2
CS		 1325/*
1326 * atl2_probe - Device Initialization Routine
1327 * @pdev: PCI device information struct
1328 * @ent: entry in atl2_pci_tbl
1329 *
1330 * Returns 0 on success, negative on failure
1331 *
1332 * atl2_probe initializes an adapter identified by a pci_dev structure.
1333 * The OS initialization, configuring of the adapter private structure,
1334 * and a hardware reset occur.
1335 */
1336static int __devinit atl2_probe(struct pci_dev *pdev,
1337 const struct pci_device_id *ent)
1338{
1339 struct net_device *netdev;
1340 struct atl2_adapter *adapter;
1341 static int cards_found;
1342 unsigned long mmio_start;
1343 int mmio_len;
1344 int err;
1345
1346 cards_found = 0;
1347
1348 err = pci_enable_device(pdev);
1349 if (err)
1350 return err;
1351
1352 /*
1353 * atl2 is a shared-high-32-bit device, so we're stuck with 32-bit DMA
1354 * until the kernel has the proper infrastructure to support 64-bit DMA
1355 * on these devices.
1356 */
284901a9
YH		 1357 if (pci_set_dma_mask(pdev, DMA_BIT_MASK(32)) &&
1358 pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32))) {
452c1ce2
CS		 1359 printk(KERN_ERR "atl2: No usable DMA configuration, aborting\n");
1360 goto err_dma;
1361 }
1362
1363 /* Mark all PCI regions associated with PCI device
1364 * pdev as being reserved by owner atl2_driver_name */
1365 err = pci_request_regions(pdev, atl2_driver_name);
1366 if (err)
1367 goto err_pci_reg;
1368
1369 /* Enables bus-mastering on the device and calls
1370 * pcibios_set_master to do the needed arch specific settings */
1371 pci_set_master(pdev);
1372
1373 err = -ENOMEM;
1374 netdev = alloc_etherdev(sizeof(struct atl2_adapter));
1375 if (!netdev)
1376 goto err_alloc_etherdev;
1377
1378 SET_NETDEV_DEV(netdev, &pdev->dev);
1379
1380 pci_set_drvdata(pdev, netdev);
1381 adapter = netdev_priv(netdev);
1382 adapter->netdev = netdev;
1383 adapter->pdev = pdev;
1384 adapter->hw.back = adapter;
1385
1386 mmio_start = pci_resource_start(pdev, 0x0);
1387 mmio_len = pci_resource_len(pdev, 0x0);
1388
1389 adapter->hw.mem_rang = (u32)mmio_len;
1390 adapter->hw.hw_addr = ioremap(mmio_start, mmio_len);
1391 if (!adapter->hw.hw_addr) {
1392 err = -EIO;
1393 goto err_ioremap;
1394 }
1395
1396 atl2_setup_pcicmd(pdev);
1397
825a84d1 1398 netdev->netdev_ops = &atl2_netdev_ops;
452c1ce2 1399 atl2_set_ethtool_ops(netdev);
452c1ce2 1400 netdev->watchdog_timeo = 5 * HZ;
452c1ce2
CS		 1401 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
1402
1403 netdev->mem_start = mmio_start;
1404 netdev->mem_end = mmio_start + mmio_len;
1405 adapter->bd_number = cards_found;
1406 adapter->pci_using_64 = false;
1407
1408 /* setup the private structure */
1409 err = atl2_sw_init(adapter);
1410 if (err)
1411 goto err_sw_init;
1412
1413 err = -EIO;
1414
1415#ifdef NETIF_F_HW_VLAN_TX
1416 netdev->features |= (NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX);
1417#endif
1418
452c1ce2
CS		 1419 /* Init PHY as early as possible due to power saving issue */
1420 atl2_phy_init(&adapter->hw);
1421
1422 /* reset the controller to
1423 * put the device in a known good starting state */
1424
1425 if (atl2_reset_hw(&adapter->hw)) {
1426 err = -EIO;
1427 goto err_reset;
1428 }
1429
1430 /* copy the MAC address out of the EEPROM */
1431 atl2_read_mac_addr(&adapter->hw);
1432 memcpy(netdev->dev_addr, adapter->hw.mac_addr, netdev->addr_len);
1433/* FIXME: do we still need this? */
1434#ifdef ETHTOOL_GPERMADDR
1435 memcpy(netdev->perm_addr, adapter->hw.mac_addr, netdev->addr_len);
1436
1437 if (!is_valid_ether_addr(netdev->perm_addr)) {
1438#else
1439 if (!is_valid_ether_addr(netdev->dev_addr)) {
1440#endif
1441 err = -EIO;
1442 goto err_eeprom;
1443 }
1444
1445 atl2_check_options(adapter);
1446
1447 init_timer(&adapter->watchdog_timer);
1448 adapter->watchdog_timer.function = &atl2_watchdog;
1449 adapter->watchdog_timer.data = (unsigned long) adapter;
1450
1451 init_timer(&adapter->phy_config_timer);
1452 adapter->phy_config_timer.function = &atl2_phy_config;
1453 adapter->phy_config_timer.data = (unsigned long) adapter;
1454
1455 INIT_WORK(&adapter->reset_task, atl2_reset_task);
1456 INIT_WORK(&adapter->link_chg_task, atl2_link_chg_task);
1457
1458 strcpy(netdev->name, "eth%d"); /* ?? */
1459 err = register_netdev(netdev);
1460 if (err)
1461 goto err_register;
1462
1463 /* assume we have no link for now */
1464 netif_carrier_off(netdev);
1465 netif_stop_queue(netdev);
1466
1467 cards_found++;
1468
1469 return 0;
1470
1471err_reset:
1472err_register:
1473err_sw_init:
1474err_eeprom:
1475 iounmap(adapter->hw.hw_addr);
1476err_ioremap:
1477 free_netdev(netdev);
1478err_alloc_etherdev:
1479 pci_release_regions(pdev);
1480err_pci_reg:
1481err_dma:
1482 pci_disable_device(pdev);
1483 return err;
1484}
1485
1486/*
1487 * atl2_remove - Device Removal Routine
1488 * @pdev: PCI device information struct
1489 *
1490 * atl2_remove is called by the PCI subsystem to alert the driver
1491 * that it should release a PCI device. The could be caused by a
1492 * Hot-Plug event, or because the driver is going to be removed from
1493 * memory.
1494 */
1495/* FIXME: write the original MAC address back in case it was changed from a
1496 * BIOS-set value, as in atl1 -- CHS */
1497static void __devexit atl2_remove(struct pci_dev *pdev)
1498{
1499 struct net_device *netdev = pci_get_drvdata(pdev);
1500 struct atl2_adapter *adapter = netdev_priv(netdev);
1501
1502 /* flush_scheduled work may reschedule our watchdog task, so
1503 * explicitly disable watchdog tasks from being rescheduled */
1504 set_bit(__ATL2_DOWN, &adapter->flags);
1505
1506 del_timer_sync(&adapter->watchdog_timer);
1507 del_timer_sync(&adapter->phy_config_timer);
1508
1509 flush_scheduled_work();
1510
1511 unregister_netdev(netdev);
1512
1513 atl2_force_ps(&adapter->hw);
1514
1515 iounmap(adapter->hw.hw_addr);
1516 pci_release_regions(pdev);
1517
1518 free_netdev(netdev);
1519
1520 pci_disable_device(pdev);
1521}
1522
1523static int atl2_suspend(struct pci_dev *pdev, pm_message_t state)
1524{
1525 struct net_device *netdev = pci_get_drvdata(pdev);
1526 struct atl2_adapter *adapter = netdev_priv(netdev);
1527 struct atl2_hw *hw = &adapter->hw;
1528 u16 speed, duplex;
1529 u32 ctrl = 0;
1530 u32 wufc = adapter->wol;
1531
1532#ifdef CONFIG_PM
1533 int retval = 0;
1534#endif
1535
1536 netif_device_detach(netdev);
1537
1538 if (netif_running(netdev)) {
1539 WARN_ON(test_bit(__ATL2_RESETTING, &adapter->flags));
1540 atl2_down(adapter);
1541 }
1542
1543#ifdef CONFIG_PM
1544 retval = pci_save_state(pdev);
1545 if (retval)
1546 return retval;
1547#endif
1548
1549 atl2_read_phy_reg(hw, MII_BMSR, (u16 *)&ctrl);
1550 atl2_read_phy_reg(hw, MII_BMSR, (u16 *)&ctrl);
1551 if (ctrl & BMSR_LSTATUS)
1552 wufc &= ~ATLX_WUFC_LNKC;
1553
1554 if (0 != (ctrl & BMSR_LSTATUS) && 0 != wufc) {
1555 u32 ret_val;
1556 /* get current link speed & duplex */
1557 ret_val = atl2_get_speed_and_duplex(hw, &speed, &duplex);
1558 if (ret_val) {
1559 printk(KERN_DEBUG
1560 "%s: get speed&duplex error while suspend\n",
1561 atl2_driver_name);
1562 goto wol_dis;
1563 }
1564
1565 ctrl = 0;
1566
1567 /* turn on magic packet wol */
1568 if (wufc & ATLX_WUFC_MAG)
1569 ctrl |= (WOL_MAGIC_EN | WOL_MAGIC_PME_EN);
1570
1571 /* ignore Link Chg event when Link is up */
1572 ATL2_WRITE_REG(hw, REG_WOL_CTRL, ctrl);
1573
1574 /* Config MAC CTRL Register */
1575 ctrl = MAC_CTRL_RX_EN | MAC_CTRL_MACLP_CLK_PHY;
1576 if (FULL_DUPLEX == adapter->link_duplex)
1577 ctrl |= MAC_CTRL_DUPLX;
1578 ctrl |= (MAC_CTRL_ADD_CRC | MAC_CTRL_PAD);
1579 ctrl |= (((u32)adapter->hw.preamble_len &
1580 MAC_CTRL_PRMLEN_MASK) << MAC_CTRL_PRMLEN_SHIFT);
1581 ctrl |= (((u32)(adapter->hw.retry_buf &
1582 MAC_CTRL_HALF_LEFT_BUF_MASK)) <<
1583 MAC_CTRL_HALF_LEFT_BUF_SHIFT);
1584 if (wufc & ATLX_WUFC_MAG) {
1585 /* magic packet maybe Broadcast&multicast&Unicast */
1586 ctrl |= MAC_CTRL_BC_EN;
1587 }
1588
1589 ATL2_WRITE_REG(hw, REG_MAC_CTRL, ctrl);
1590
1591 /* pcie patch */
1592 ctrl = ATL2_READ_REG(hw, REG_PCIE_PHYMISC);
1593 ctrl |= PCIE_PHYMISC_FORCE_RCV_DET;
1594 ATL2_WRITE_REG(hw, REG_PCIE_PHYMISC, ctrl);
1595 ctrl = ATL2_READ_REG(hw, REG_PCIE_DLL_TX_CTRL1);
1596 ctrl |= PCIE_DLL_TX_CTRL1_SEL_NOR_CLK;
1597 ATL2_WRITE_REG(hw, REG_PCIE_DLL_TX_CTRL1, ctrl);
1598
1599 pci_enable_wake(pdev, pci_choose_state(pdev, state), 1);
1600 goto suspend_exit;
1601 }
1602
1603 if (0 == (ctrl&BMSR_LSTATUS) && 0 != (wufc&ATLX_WUFC_LNKC)) {
1604 /* link is down, so only LINK CHG WOL event enable */
1605 ctrl |= (WOL_LINK_CHG_EN | WOL_LINK_CHG_PME_EN);
1606 ATL2_WRITE_REG(hw, REG_WOL_CTRL, ctrl);
1607 ATL2_WRITE_REG(hw, REG_MAC_CTRL, 0);
1608
1609 /* pcie patch */
1610 ctrl = ATL2_READ_REG(hw, REG_PCIE_PHYMISC);
1611 ctrl |= PCIE_PHYMISC_FORCE_RCV_DET;
1612 ATL2_WRITE_REG(hw, REG_PCIE_PHYMISC, ctrl);
1613 ctrl = ATL2_READ_REG(hw, REG_PCIE_DLL_TX_CTRL1);
1614 ctrl |= PCIE_DLL_TX_CTRL1_SEL_NOR_CLK;
1615 ATL2_WRITE_REG(hw, REG_PCIE_DLL_TX_CTRL1, ctrl);
1616
1617 hw->phy_configured = false; /* re-init PHY when resume */
1618
1619 pci_enable_wake(pdev, pci_choose_state(pdev, state), 1);
1620
1621 goto suspend_exit;
1622 }
1623
1624wol_dis:
1625 /* WOL disabled */
1626 ATL2_WRITE_REG(hw, REG_WOL_CTRL, 0);
1627
1628 /* pcie patch */
1629 ctrl = ATL2_READ_REG(hw, REG_PCIE_PHYMISC);
1630 ctrl |= PCIE_PHYMISC_FORCE_RCV_DET;
1631 ATL2_WRITE_REG(hw, REG_PCIE_PHYMISC, ctrl);
1632 ctrl = ATL2_READ_REG(hw, REG_PCIE_DLL_TX_CTRL1);
1633 ctrl |= PCIE_DLL_TX_CTRL1_SEL_NOR_CLK;
1634 ATL2_WRITE_REG(hw, REG_PCIE_DLL_TX_CTRL1, ctrl);
1635
1636 atl2_force_ps(hw);
1637 hw->phy_configured = false; /* re-init PHY when resume */
1638
1639 pci_enable_wake(pdev, pci_choose_state(pdev, state), 0);
1640
1641suspend_exit:
1642 if (netif_running(netdev))
1643 atl2_free_irq(adapter);
1644
1645 pci_disable_device(pdev);
1646
1647 pci_set_power_state(pdev, pci_choose_state(pdev, state));
1648
1649 return 0;
1650}
1651
1652#ifdef CONFIG_PM
1653static int atl2_resume(struct pci_dev *pdev)
1654{
1655 struct net_device *netdev = pci_get_drvdata(pdev);
1656 struct atl2_adapter *adapter = netdev_priv(netdev);
1657 u32 err;
1658
1659 pci_set_power_state(pdev, PCI_D0);
1660 pci_restore_state(pdev);
1661
1662 err = pci_enable_device(pdev);
1663 if (err) {
1664 printk(KERN_ERR
1665 "atl2: Cannot enable PCI device from suspend\n");
1666 return err;
1667 }
1668
1669 pci_set_master(pdev);
1670
1671 ATL2_READ_REG(&adapter->hw, REG_WOL_CTRL); /* clear WOL status */
1672
1673 pci_enable_wake(pdev, PCI_D3hot, 0);
1674 pci_enable_wake(pdev, PCI_D3cold, 0);
1675
1676 ATL2_WRITE_REG(&adapter->hw, REG_WOL_CTRL, 0);
1677
a849854f
AJ		 1678 if (netif_running(netdev)) {
1679 err = atl2_request_irq(adapter);
1680 if (err)
1681 return err;
1682 }
452c1ce2
CS		 1683
1684 atl2_reset_hw(&adapter->hw);
1685
1686 if (netif_running(netdev))
1687 atl2_up(adapter);
1688
1689 netif_device_attach(netdev);
1690
1691 return 0;
1692}
1693#endif
1694
1695static void atl2_shutdown(struct pci_dev *pdev)
1696{
1697 atl2_suspend(pdev, PMSG_SUSPEND);
1698}
1699
1700static struct pci_driver atl2_driver = {
1701 .name = atl2_driver_name,
1702 .id_table = atl2_pci_tbl,
1703 .probe = atl2_probe,
1704 .remove = __devexit_p(atl2_remove),
1705 /* Power Managment Hooks */
1706 .suspend = atl2_suspend,
1707#ifdef CONFIG_PM
1708 .resume = atl2_resume,
1709#endif
1710 .shutdown = atl2_shutdown,
1711};
1712
1713/*
1714 * atl2_init_module - Driver Registration Routine
1715 *
1716 * atl2_init_module is the first routine called when the driver is
1717 * loaded. All it does is register with the PCI subsystem.
1718 */
1719static int __init atl2_init_module(void)
1720{
1721 printk(KERN_INFO "%s - version %s\n", atl2_driver_string,
1722 atl2_driver_version);
1723 printk(KERN_INFO "%s\n", atl2_copyright);
1724 return pci_register_driver(&atl2_driver);
1725}
1726module_init(atl2_init_module);
1727
1728/*
1729 * atl2_exit_module - Driver Exit Cleanup Routine
1730 *
1731 * atl2_exit_module is called just before the driver is removed
1732 * from memory.
1733 */
1734static void __exit atl2_exit_module(void)
1735{
1736 pci_unregister_driver(&atl2_driver);
1737}
1738module_exit(atl2_exit_module);
1739
1740static void atl2_read_pci_cfg(struct atl2_hw *hw, u32 reg, u16 *value)
1741{
1742 struct atl2_adapter *adapter = hw->back;
1743 pci_read_config_word(adapter->pdev, reg, value);
1744}
1745
1746static void atl2_write_pci_cfg(struct atl2_hw *hw, u32 reg, u16 *value)
1747{
1748 struct atl2_adapter *adapter = hw->back;
1749 pci_write_config_word(adapter->pdev, reg, *value);
1750}
1751
1752static int atl2_get_settings(struct net_device *netdev,
1753 struct ethtool_cmd *ecmd)
1754{
1755 struct atl2_adapter *adapter = netdev_priv(netdev);
1756 struct atl2_hw *hw = &adapter->hw;
1757
1758 ecmd->supported = (SUPPORTED_10baseT_Half |
1759 SUPPORTED_10baseT_Full |
1760 SUPPORTED_100baseT_Half |
1761 SUPPORTED_100baseT_Full |
1762 SUPPORTED_Autoneg |
1763 SUPPORTED_TP);
1764 ecmd->advertising = ADVERTISED_TP;
1765
1766 ecmd->advertising |= ADVERTISED_Autoneg;
1767 ecmd->advertising |= hw->autoneg_advertised;
1768
1769 ecmd->port = PORT_TP;
1770 ecmd->phy_address = 0;
1771 ecmd->transceiver = XCVR_INTERNAL;
1772
1773 if (adapter->link_speed != SPEED_0) {
1774 ecmd->speed = adapter->link_speed;
1775 if (adapter->link_duplex == FULL_DUPLEX)
1776 ecmd->duplex = DUPLEX_FULL;
1777 else
1778 ecmd->duplex = DUPLEX_HALF;
1779 } else {
1780 ecmd->speed = -1;
1781 ecmd->duplex = -1;
1782 }
1783
1784 ecmd->autoneg = AUTONEG_ENABLE;
1785 return 0;
1786}
1787
1788static int atl2_set_settings(struct net_device *netdev,
1789 struct ethtool_cmd *ecmd)
1790{
1791 struct atl2_adapter *adapter = netdev_priv(netdev);
1792 struct atl2_hw *hw = &adapter->hw;
1793
1794 while (test_and_set_bit(__ATL2_RESETTING, &adapter->flags))
1795 msleep(1);
1796
1797 if (ecmd->autoneg == AUTONEG_ENABLE) {
1798#define MY_ADV_MASK (ADVERTISE_10_HALF | \
1799 ADVERTISE_10_FULL | \
1800 ADVERTISE_100_HALF| \
1801 ADVERTISE_100_FULL)
1802
1803 if ((ecmd->advertising & MY_ADV_MASK) == MY_ADV_MASK) {
1804 hw->MediaType = MEDIA_TYPE_AUTO_SENSOR;
1805 hw->autoneg_advertised = MY_ADV_MASK;
1806 } else if ((ecmd->advertising & MY_ADV_MASK) ==
1807 ADVERTISE_100_FULL) {
1808 hw->MediaType = MEDIA_TYPE_100M_FULL;
1809 hw->autoneg_advertised = ADVERTISE_100_FULL;
1810 } else if ((ecmd->advertising & MY_ADV_MASK) ==
1811 ADVERTISE_100_HALF) {
1812 hw->MediaType = MEDIA_TYPE_100M_HALF;
1813 hw->autoneg_advertised = ADVERTISE_100_HALF;
1814 } else if ((ecmd->advertising & MY_ADV_MASK) ==
1815 ADVERTISE_10_FULL) {
1816 hw->MediaType = MEDIA_TYPE_10M_FULL;
1817 hw->autoneg_advertised = ADVERTISE_10_FULL;
1818 } else if ((ecmd->advertising & MY_ADV_MASK) ==
1819 ADVERTISE_10_HALF) {
1820 hw->MediaType = MEDIA_TYPE_10M_HALF;
1821 hw->autoneg_advertised = ADVERTISE_10_HALF;
1822 } else {
1823 clear_bit(__ATL2_RESETTING, &adapter->flags);
1824 return -EINVAL;
1825 }
1826 ecmd->advertising = hw->autoneg_advertised |
1827 ADVERTISED_TP | ADVERTISED_Autoneg;
1828 } else {
1829 clear_bit(__ATL2_RESETTING, &adapter->flags);
1830 return -EINVAL;
1831 }
1832
1833 /* reset the link */
1834 if (netif_running(adapter->netdev)) {
1835 atl2_down(adapter);
1836 atl2_up(adapter);
1837 } else
1838 atl2_reset_hw(&adapter->hw);
1839
1840 clear_bit(__ATL2_RESETTING, &adapter->flags);
1841 return 0;
1842}
1843
1844static u32 atl2_get_tx_csum(struct net_device *netdev)
1845{
1846 return (netdev->features & NETIF_F_HW_CSUM) != 0;
1847}
1848
1849static u32 atl2_get_msglevel(struct net_device *netdev)
1850{
1851 return 0;
1852}
1853
1854/*
1855 * It's sane for this to be empty, but we might want to take advantage of this.
1856 */
1857static void atl2_set_msglevel(struct net_device *netdev, u32 data)
1858{
1859}
1860
1861static int atl2_get_regs_len(struct net_device *netdev)
1862{
1863#define ATL2_REGS_LEN 42
1864 return sizeof(u32) * ATL2_REGS_LEN;
1865}
1866
1867static void atl2_get_regs(struct net_device *netdev,
1868 struct ethtool_regs *regs, void *p)
1869{
1870 struct atl2_adapter *adapter = netdev_priv(netdev);
1871 struct atl2_hw *hw = &adapter->hw;
1872 u32 *regs_buff = p;
1873 u16 phy_data;
1874
1875 memset(p, 0, sizeof(u32) * ATL2_REGS_LEN);
1876
1877 regs->version = (1 << 24) | (hw->revision_id << 16) | hw->device_id;
1878
1879 regs_buff[0] = ATL2_READ_REG(hw, REG_VPD_CAP);
1880 regs_buff[1] = ATL2_READ_REG(hw, REG_SPI_FLASH_CTRL);
1881 regs_buff[2] = ATL2_READ_REG(hw, REG_SPI_FLASH_CONFIG);
1882 regs_buff[3] = ATL2_READ_REG(hw, REG_TWSI_CTRL);
1883 regs_buff[4] = ATL2_READ_REG(hw, REG_PCIE_DEV_MISC_CTRL);
1884 regs_buff[5] = ATL2_READ_REG(hw, REG_MASTER_CTRL);
1885 regs_buff[6] = ATL2_READ_REG(hw, REG_MANUAL_TIMER_INIT);
1886 regs_buff[7] = ATL2_READ_REG(hw, REG_IRQ_MODU_TIMER_INIT);
1887 regs_buff[8] = ATL2_READ_REG(hw, REG_PHY_ENABLE);
1888 regs_buff[9] = ATL2_READ_REG(hw, REG_CMBDISDMA_TIMER);
1889 regs_buff[10] = ATL2_READ_REG(hw, REG_IDLE_STATUS);
1890 regs_buff[11] = ATL2_READ_REG(hw, REG_MDIO_CTRL);
1891 regs_buff[12] = ATL2_READ_REG(hw, REG_SERDES_LOCK);
1892 regs_buff[13] = ATL2_READ_REG(hw, REG_MAC_CTRL);
1893 regs_buff[14] = ATL2_READ_REG(hw, REG_MAC_IPG_IFG);
1894 regs_buff[15] = ATL2_READ_REG(hw, REG_MAC_STA_ADDR);
1895 regs_buff[16] = ATL2_READ_REG(hw, REG_MAC_STA_ADDR+4);
1896 regs_buff[17] = ATL2_READ_REG(hw, REG_RX_HASH_TABLE);
1897 regs_buff[18] = ATL2_READ_REG(hw, REG_RX_HASH_TABLE+4);
1898 regs_buff[19] = ATL2_READ_REG(hw, REG_MAC_HALF_DUPLX_CTRL);
1899 regs_buff[20] = ATL2_READ_REG(hw, REG_MTU);
1900 regs_buff[21] = ATL2_READ_REG(hw, REG_WOL_CTRL);
1901 regs_buff[22] = ATL2_READ_REG(hw, REG_SRAM_TXRAM_END);
1902 regs_buff[23] = ATL2_READ_REG(hw, REG_DESC_BASE_ADDR_HI);
1903 regs_buff[24] = ATL2_READ_REG(hw, REG_TXD_BASE_ADDR_LO);
1904 regs_buff[25] = ATL2_READ_REG(hw, REG_TXD_MEM_SIZE);
1905 regs_buff[26] = ATL2_READ_REG(hw, REG_TXS_BASE_ADDR_LO);
1906 regs_buff[27] = ATL2_READ_REG(hw, REG_TXS_MEM_SIZE);
1907 regs_buff[28] = ATL2_READ_REG(hw, REG_RXD_BASE_ADDR_LO);
1908 regs_buff[29] = ATL2_READ_REG(hw, REG_RXD_BUF_NUM);
1909 regs_buff[30] = ATL2_READ_REG(hw, REG_DMAR);
1910 regs_buff[31] = ATL2_READ_REG(hw, REG_TX_CUT_THRESH);
1911 regs_buff[32] = ATL2_READ_REG(hw, REG_DMAW);
1912 regs_buff[33] = ATL2_READ_REG(hw, REG_PAUSE_ON_TH);
1913 regs_buff[34] = ATL2_READ_REG(hw, REG_PAUSE_OFF_TH);
1914 regs_buff[35] = ATL2_READ_REG(hw, REG_MB_TXD_WR_IDX);
1915 regs_buff[36] = ATL2_READ_REG(hw, REG_MB_RXD_RD_IDX);
1916 regs_buff[38] = ATL2_READ_REG(hw, REG_ISR);
1917 regs_buff[39] = ATL2_READ_REG(hw, REG_IMR);
1918
1919 atl2_read_phy_reg(hw, MII_BMCR, &phy_data);
1920 regs_buff[40] = (u32)phy_data;
1921 atl2_read_phy_reg(hw, MII_BMSR, &phy_data);
1922 regs_buff[41] = (u32)phy_data;
1923}
1924
1925static int atl2_get_eeprom_len(struct net_device *netdev)
1926{
1927 struct atl2_adapter *adapter = netdev_priv(netdev);
1928
1929 if (!atl2_check_eeprom_exist(&adapter->hw))
1930 return 512;
1931 else
1932 return 0;
1933}
1934
1935static int atl2_get_eeprom(struct net_device *netdev,
1936 struct ethtool_eeprom *eeprom, u8 *bytes)
1937{
1938 struct atl2_adapter *adapter = netdev_priv(netdev);
1939 struct atl2_hw *hw = &adapter->hw;
1940 u32 *eeprom_buff;
1941 int first_dword, last_dword;
1942 int ret_val = 0;
1943 int i;
1944
1945 if (eeprom->len == 0)
1946 return -EINVAL;
1947
1948 if (atl2_check_eeprom_exist(hw))
1949 return -EINVAL;
1950
1951 eeprom->magic = hw->vendor_id | (hw->device_id << 16);
1952
1953 first_dword = eeprom->offset >> 2;
1954 last_dword = (eeprom->offset + eeprom->len - 1) >> 2;
1955
1956 eeprom_buff = kmalloc(sizeof(u32) * (last_dword - first_dword + 1),
1957 GFP_KERNEL);
1958 if (!eeprom_buff)
1959 return -ENOMEM;
1960
1961 for (i = first_dword; i < last_dword; i++) {
1962 if (!atl2_read_eeprom(hw, i*4, &(eeprom_buff[i-first_dword])))
1963 return -EIO;
1964 }
1965
1966 memcpy(bytes, (u8 *)eeprom_buff + (eeprom->offset & 3),
1967 eeprom->len);
1968 kfree(eeprom_buff);
1969
1970 return ret_val;
1971}
1972
1973static int atl2_set_eeprom(struct net_device *netdev,
1974 struct ethtool_eeprom *eeprom, u8 *bytes)
1975{
1976 struct atl2_adapter *adapter = netdev_priv(netdev);
1977 struct atl2_hw *hw = &adapter->hw;
1978 u32 *eeprom_buff;
1979 u32 *ptr;
1980 int max_len, first_dword, last_dword, ret_val = 0;
1981 int i;
1982
1983 if (eeprom->len == 0)
1984 return -EOPNOTSUPP;
1985
1986 if (eeprom->magic != (hw->vendor_id | (hw->device_id << 16)))
1987 return -EFAULT;
1988
1989 max_len = 512;
1990
1991 first_dword = eeprom->offset >> 2;
1992 last_dword = (eeprom->offset + eeprom->len - 1) >> 2;
1993 eeprom_buff = kmalloc(max_len, GFP_KERNEL);
1994 if (!eeprom_buff)
1995 return -ENOMEM;
1996
1997 ptr = (u32 *)eeprom_buff;
1998
1999 if (eeprom->offset & 3) {
2000 /* need read/modify/write of first changed EEPROM word */
2001 /* only the second byte of the word is being modified */
2002 if (!atl2_read_eeprom(hw, first_dword*4, &(eeprom_buff[0])))
2003 return -EIO;
2004 ptr++;
2005 }
2006 if (((eeprom->offset + eeprom->len) & 3)) {
2007 /*
2008 * need read/modify/write of last changed EEPROM word
2009 * only the first byte of the word is being modified
2010 */
2011 if (!atl2_read_eeprom(hw, last_dword * 4,
2012 &(eeprom_buff[last_dword - first_dword])))
2013 return -EIO;
2014 }
2015
2016 /* Device's eeprom is always little-endian, word addressable */
2017 memcpy(ptr, bytes, eeprom->len);
2018
2019 for (i = 0; i < last_dword - first_dword + 1; i++) {
2020 if (!atl2_write_eeprom(hw, ((first_dword+i)*4), eeprom_buff[i]))
2021 return -EIO;
2022 }
2023
2024 kfree(eeprom_buff);
2025 return ret_val;
2026}
2027
2028static void atl2_get_drvinfo(struct net_device *netdev,
2029 struct ethtool_drvinfo *drvinfo)
2030{
2031 struct atl2_adapter *adapter = netdev_priv(netdev);
2032
2033 strncpy(drvinfo->driver, atl2_driver_name, 32);
2034 strncpy(drvinfo->version, atl2_driver_version, 32);
2035 strncpy(drvinfo->fw_version, "L2", 32);
2036 strncpy(drvinfo->bus_info, pci_name(adapter->pdev), 32);
2037 drvinfo->n_stats = 0;
2038 drvinfo->testinfo_len = 0;
2039 drvinfo->regdump_len = atl2_get_regs_len(netdev);
2040 drvinfo->eedump_len = atl2_get_eeprom_len(netdev);
2041}
2042
2043static void atl2_get_wol(struct net_device *netdev,
2044 struct ethtool_wolinfo *wol)
2045{
2046 struct atl2_adapter *adapter = netdev_priv(netdev);
2047
2048 wol->supported = WAKE_MAGIC;
2049 wol->wolopts = 0;
2050
2051 if (adapter->wol & ATLX_WUFC_EX)
2052 wol->wolopts |= WAKE_UCAST;
2053 if (adapter->wol & ATLX_WUFC_MC)
2054 wol->wolopts |= WAKE_MCAST;
2055 if (adapter->wol & ATLX_WUFC_BC)
2056 wol->wolopts |= WAKE_BCAST;
2057 if (adapter->wol & ATLX_WUFC_MAG)
2058 wol->wolopts |= WAKE_MAGIC;
2059 if (adapter->wol & ATLX_WUFC_LNKC)
2060 wol->wolopts |= WAKE_PHY;
2061}
2062
2063static int atl2_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
2064{
2065 struct atl2_adapter *adapter = netdev_priv(netdev);
2066
2067 if (wol->wolopts & (WAKE_ARP | WAKE_MAGICSECURE))
2068 return -EOPNOTSUPP;
2069
41796e91 2070 if (wol->wolopts & (WAKE_UCAST | WAKE_BCAST | WAKE_MCAST))
452c1ce2
CS		 2071 return -EOPNOTSUPP;
2072
2073 /* these settings will always override what we currently have */
2074 adapter->wol = 0;
2075
2076 if (wol->wolopts & WAKE_MAGIC)
2077 adapter->wol |= ATLX_WUFC_MAG;
2078 if (wol->wolopts & WAKE_PHY)
2079 adapter->wol |= ATLX_WUFC_LNKC;
2080
2081 return 0;
2082}
2083
2084static int atl2_nway_reset(struct net_device *netdev)
2085{
2086 struct atl2_adapter *adapter = netdev_priv(netdev);
2087 if (netif_running(netdev))
2088 atl2_reinit_locked(adapter);
2089 return 0;
2090}
2091
0fc0b732 2092static const struct ethtool_ops atl2_ethtool_ops = {
452c1ce2
CS		 2093 .get_settings = atl2_get_settings,
2094 .set_settings = atl2_set_settings,
2095 .get_drvinfo = atl2_get_drvinfo,
2096 .get_regs_len = atl2_get_regs_len,
2097 .get_regs = atl2_get_regs,
2098 .get_wol = atl2_get_wol,
2099 .set_wol = atl2_set_wol,
2100 .get_msglevel = atl2_get_msglevel,
2101 .set_msglevel = atl2_set_msglevel,
2102 .nway_reset = atl2_nway_reset,
2103 .get_link = ethtool_op_get_link,
2104 .get_eeprom_len = atl2_get_eeprom_len,
2105 .get_eeprom = atl2_get_eeprom,
2106 .set_eeprom = atl2_set_eeprom,
2107 .get_tx_csum = atl2_get_tx_csum,
2108 .get_sg = ethtool_op_get_sg,
2109 .set_sg = ethtool_op_set_sg,
2110#ifdef NETIF_F_TSO
2111 .get_tso = ethtool_op_get_tso,
2112#endif
2113};
2114
2115static void atl2_set_ethtool_ops(struct net_device *netdev)
2116{
2117 SET_ETHTOOL_OPS(netdev, &atl2_ethtool_ops);
2118}
2119
2120#define LBYTESWAP(a) ((((a) & 0x00ff00ff) << 8) | \
2121 (((a) & 0xff00ff00) >> 8))
2122#define LONGSWAP(a) ((LBYTESWAP(a) << 16) | (LBYTESWAP(a) >> 16))
2123#define SHORTSWAP(a) (((a) << 8) | ((a) >> 8))
2124
2125/*
2126 * Reset the transmit and receive units; mask and clear all interrupts.
2127 *
2128 * hw - Struct containing variables accessed by shared code
2129 * return : 0 or idle status (if error)
2130 */
2131static s32 atl2_reset_hw(struct atl2_hw *hw)
2132{
2133 u32 icr;
2134 u16 pci_cfg_cmd_word;
2135 int i;
2136
2137 /* Workaround for PCI problem when BIOS sets MMRBC incorrectly. */
2138 atl2_read_pci_cfg(hw, PCI_REG_COMMAND, &pci_cfg_cmd_word);
2139 if ((pci_cfg_cmd_word &
2140 (CMD_IO_SPACE|CMD_MEMORY_SPACE|CMD_BUS_MASTER)) !=
2141 (CMD_IO_SPACE|CMD_MEMORY_SPACE|CMD_BUS_MASTER)) {
2142 pci_cfg_cmd_word |=
2143 (CMD_IO_SPACE|CMD_MEMORY_SPACE|CMD_BUS_MASTER);
2144 atl2_write_pci_cfg(hw, PCI_REG_COMMAND, &pci_cfg_cmd_word);
2145 }
2146
2147 /* Clear Interrupt mask to stop board from generating
2148 * interrupts & Clear any pending interrupt events
2149 */
2150 /* FIXME */
2151 /* ATL2_WRITE_REG(hw, REG_IMR, 0); */
2152 /* ATL2_WRITE_REG(hw, REG_ISR, 0xffffffff); */
2153
2154 /* Issue Soft Reset to the MAC. This will reset the chip's
2155 * transmit, receive, DMA. It will not effect
2156 * the current PCI configuration. The global reset bit is self-
2157 * clearing, and should clear within a microsecond.
2158 */
2159 ATL2_WRITE_REG(hw, REG_MASTER_CTRL, MASTER_CTRL_SOFT_RST);
2160 wmb();
2161 msleep(1); /* delay about 1ms */
2162
2163 /* Wait at least 10ms for All module to be Idle */
2164 for (i = 0; i < 10; i++) {
2165 icr = ATL2_READ_REG(hw, REG_IDLE_STATUS);
2166 if (!icr)
2167 break;
2168 msleep(1); /* delay 1 ms */
2169 cpu_relax();
2170 }
2171
2172 if (icr)
2173 return icr;
2174
2175 return 0;
2176}
2177
2178#define CUSTOM_SPI_CS_SETUP 2
2179#define CUSTOM_SPI_CLK_HI 2
2180#define CUSTOM_SPI_CLK_LO 2
2181#define CUSTOM_SPI_CS_HOLD 2
2182#define CUSTOM_SPI_CS_HI 3
2183
2184static struct atl2_spi_flash_dev flash_table[] =
2185{
2186/* MFR WRSR READ PROGRAM WREN WRDI RDSR RDID SECTOR_ERASE CHIP_ERASE */
2187{"Atmel", 0x0, 0x03, 0x02, 0x06, 0x04, 0x05, 0x15, 0x52, 0x62 },
2188{"SST", 0x01, 0x03, 0x02, 0x06, 0x04, 0x05, 0x90, 0x20, 0x60 },
2189{"ST", 0x01, 0x03, 0x02, 0x06, 0x04, 0x05, 0xAB, 0xD8, 0xC7 },
2190};
2191
2192static bool atl2_spi_read(struct atl2_hw *hw, u32 addr, u32 *buf)
2193{
2194 int i;
2195 u32 value;
2196
2197 ATL2_WRITE_REG(hw, REG_SPI_DATA, 0);
2198 ATL2_WRITE_REG(hw, REG_SPI_ADDR, addr);
2199
2200 value = SPI_FLASH_CTRL_WAIT_READY |
2201 (CUSTOM_SPI_CS_SETUP & SPI_FLASH_CTRL_CS_SETUP_MASK) <<
2202 SPI_FLASH_CTRL_CS_SETUP_SHIFT |
2203 (CUSTOM_SPI_CLK_HI & SPI_FLASH_CTRL_CLK_HI_MASK) <<
2204 SPI_FLASH_CTRL_CLK_HI_SHIFT |
2205 (CUSTOM_SPI_CLK_LO & SPI_FLASH_CTRL_CLK_LO_MASK) <<
2206 SPI_FLASH_CTRL_CLK_LO_SHIFT |
2207 (CUSTOM_SPI_CS_HOLD & SPI_FLASH_CTRL_CS_HOLD_MASK) <<
2208 SPI_FLASH_CTRL_CS_HOLD_SHIFT |
2209 (CUSTOM_SPI_CS_HI & SPI_FLASH_CTRL_CS_HI_MASK) <<
2210 SPI_FLASH_CTRL_CS_HI_SHIFT |
2211 (0x1 & SPI_FLASH_CTRL_INS_MASK) << SPI_FLASH_CTRL_INS_SHIFT;
2212
2213 ATL2_WRITE_REG(hw, REG_SPI_FLASH_CTRL, value);
2214
2215 value |= SPI_FLASH_CTRL_START;
2216
2217 ATL2_WRITE_REG(hw, REG_SPI_FLASH_CTRL, value);
2218
2219 for (i = 0; i < 10; i++) {
2220 msleep(1);
2221 value = ATL2_READ_REG(hw, REG_SPI_FLASH_CTRL);
2222 if (!(value & SPI_FLASH_CTRL_START))
2223 break;
2224 }
2225
2226 if (value & SPI_FLASH_CTRL_START)
2227 return false;
2228
2229 *buf = ATL2_READ_REG(hw, REG_SPI_DATA);
2230
2231 return true;
2232}
2233
2234/*
2235 * get_permanent_address
2236 * return 0 if get valid mac address,
2237 */
2238static int get_permanent_address(struct atl2_hw *hw)
2239{
2240 u32 Addr[2];
2241 u32 i, Control;
2242 u16 Register;
2243 u8 EthAddr[NODE_ADDRESS_SIZE];
2244 bool KeyValid;
2245
2246 if (is_valid_ether_addr(hw->perm_mac_addr))
2247 return 0;
2248
2249 Addr[0] = 0;
2250 Addr[1] = 0;
2251
2252 if (!atl2_check_eeprom_exist(hw)) { /* eeprom exists */
2253 Register = 0;
2254 KeyValid = false;
2255
2256 /* Read out all EEPROM content */
2257 i = 0;
2258 while (1) {
2259 if (atl2_read_eeprom(hw, i + 0x100, &Control)) {
2260 if (KeyValid) {
2261 if (Register == REG_MAC_STA_ADDR)
2262 Addr[0] = Control;
2263 else if (Register ==
2264 (REG_MAC_STA_ADDR + 4))
2265 Addr[1] = Control;
2266 KeyValid = false;
2267 } else if ((Control & 0xff) == 0x5A) {
2268 KeyValid = true;
2269 Register = (u16) (Control >> 16);
2270 } else {
2271 /* assume data end while encount an invalid KEYWORD */
2272 break;
2273 }
2274 } else {
2275 break; /* read error */
2276 }
2277 i += 4;
2278 }
2279
2280 *(u32 *) &EthAddr[2] = LONGSWAP(Addr[0]);
2281 *(u16 *) &EthAddr[0] = SHORTSWAP(*(u16 *) &Addr[1]);
2282
2283 if (is_valid_ether_addr(EthAddr)) {
2284 memcpy(hw->perm_mac_addr, EthAddr, NODE_ADDRESS_SIZE);
2285 return 0;
2286 }
2287 return 1;
2288 }
2289
2290 /* see if SPI flash exists? */
2291 Addr[0] = 0;
2292 Addr[1] = 0;
2293 Register = 0;
2294 KeyValid = false;
2295 i = 0;
2296 while (1) {
2297 if (atl2_spi_read(hw, i + 0x1f000, &Control)) {
2298 if (KeyValid) {
2299 if (Register == REG_MAC_STA_ADDR)
2300 Addr[0] = Control;
2301 else if (Register == (REG_MAC_STA_ADDR + 4))
2302 Addr[1] = Control;
2303 KeyValid = false;
2304 } else if ((Control & 0xff) == 0x5A) {
2305 KeyValid = true;
2306 Register = (u16) (Control >> 16);
2307 } else {
2308 break; /* data end */
2309 }
2310 } else {
2311 break; /* read error */
2312 }
2313 i += 4;
2314 }
2315
2316 *(u32 *) &EthAddr[2] = LONGSWAP(Addr[0]);
2317 *(u16 *) &EthAddr[0] = SHORTSWAP(*(u16 *)&Addr[1]);
2318 if (is_valid_ether_addr(EthAddr)) {
2319 memcpy(hw->perm_mac_addr, EthAddr, NODE_ADDRESS_SIZE);
2320 return 0;
2321 }
2322 /* maybe MAC-address is from BIOS */
2323 Addr[0] = ATL2_READ_REG(hw, REG_MAC_STA_ADDR);
2324 Addr[1] = ATL2_READ_REG(hw, REG_MAC_STA_ADDR + 4);
2325 *(u32 *) &EthAddr[2] = LONGSWAP(Addr[0]);
2326 *(u16 *) &EthAddr[0] = SHORTSWAP(*(u16 *) &Addr[1]);
2327
2328 if (is_valid_ether_addr(EthAddr)) {
2329 memcpy(hw->perm_mac_addr, EthAddr, NODE_ADDRESS_SIZE);
2330 return 0;
2331 }
2332
2333 return 1;
2334}
2335
2336/*
2337 * Reads the adapter's MAC address from the EEPROM
2338 *
2339 * hw - Struct containing variables accessed by shared code
2340 */
2341static s32 atl2_read_mac_addr(struct atl2_hw *hw)
2342{
2343 u16 i;
2344
2345 if (get_permanent_address(hw)) {
2346 /* for test */
2347 /* FIXME: shouldn't we use random_ether_addr() here? */
2348 hw->perm_mac_addr[0] = 0x00;
2349 hw->perm_mac_addr[1] = 0x13;
2350 hw->perm_mac_addr[2] = 0x74;
2351 hw->perm_mac_addr[3] = 0x00;
2352 hw->perm_mac_addr[4] = 0x5c;
2353 hw->perm_mac_addr[5] = 0x38;
2354 }
2355
2356 for (i = 0; i < NODE_ADDRESS_SIZE; i++)
2357 hw->mac_addr[i] = hw->perm_mac_addr[i];
2358
2359 return 0;
2360}
2361
2362/*
2363 * Hashes an address to determine its location in the multicast table
2364 *
2365 * hw - Struct containing variables accessed by shared code
2366 * mc_addr - the multicast address to hash
2367 *
2368 * atl2_hash_mc_addr
2369 * purpose
2370 * set hash value for a multicast address
2371 * hash calcu processing :
2372 * 1. calcu 32bit CRC for multicast address
2373 * 2. reverse crc with MSB to LSB
2374 */
2375static u32 atl2_hash_mc_addr(struct atl2_hw *hw, u8 *mc_addr)
2376{
2377 u32 crc32, value;
2378 int i;
2379
2380 value = 0;
2381 crc32 = ether_crc_le(6, mc_addr);
2382
2383 for (i = 0; i < 32; i++)
2384 value |= (((crc32 >> i) & 1) << (31 - i));
2385
2386 return value;
2387}
2388
2389/*
2390 * Sets the bit in the multicast table corresponding to the hash value.
2391 *
2392 * hw - Struct containing variables accessed by shared code
2393 * hash_value - Multicast address hash value
2394 */
2395static void atl2_hash_set(struct atl2_hw *hw, u32 hash_value)
2396{
2397 u32 hash_bit, hash_reg;
2398 u32 mta;
2399
2400 /* The HASH Table is a register array of 2 32-bit registers.
2401 * It is treated like an array of 64 bits. We want to set
2402 * bit BitArray[hash_value]. So we figure out what register
2403 * the bit is in, read it, OR in the new bit, then write
2404 * back the new value. The register is determined by the
2405 * upper 7 bits of the hash value and the bit within that
2406 * register are determined by the lower 5 bits of the value.
2407 */
2408 hash_reg = (hash_value >> 31) & 0x1;
2409 hash_bit = (hash_value >> 26) & 0x1F;
2410
2411 mta = ATL2_READ_REG_ARRAY(hw, REG_RX_HASH_TABLE, hash_reg);
2412
2413 mta |= (1 << hash_bit);
2414
2415 ATL2_WRITE_REG_ARRAY(hw, REG_RX_HASH_TABLE, hash_reg, mta);
2416}
2417
2418/*
2419 * atl2_init_pcie - init PCIE module
2420 */
2421static void atl2_init_pcie(struct atl2_hw *hw)
2422{
2423 u32 value;
2424 value = LTSSM_TEST_MODE_DEF;
2425 ATL2_WRITE_REG(hw, REG_LTSSM_TEST_MODE, value);
2426
2427 value = PCIE_DLL_TX_CTRL1_DEF;
2428 ATL2_WRITE_REG(hw, REG_PCIE_DLL_TX_CTRL1, value);
2429}
2430
2431static void atl2_init_flash_opcode(struct atl2_hw *hw)
2432{
2433 if (hw->flash_vendor >= ARRAY_SIZE(flash_table))
2434 hw->flash_vendor = 0; /* ATMEL */
2435
2436 /* Init OP table */
2437 ATL2_WRITE_REGB(hw, REG_SPI_FLASH_OP_PROGRAM,
2438 flash_table[hw->flash_vendor].cmdPROGRAM);
2439 ATL2_WRITE_REGB(hw, REG_SPI_FLASH_OP_SC_ERASE,
2440 flash_table[hw->flash_vendor].cmdSECTOR_ERASE);
2441 ATL2_WRITE_REGB(hw, REG_SPI_FLASH_OP_CHIP_ERASE,
2442 flash_table[hw->flash_vendor].cmdCHIP_ERASE);
2443 ATL2_WRITE_REGB(hw, REG_SPI_FLASH_OP_RDID,
2444 flash_table[hw->flash_vendor].cmdRDID);
2445 ATL2_WRITE_REGB(hw, REG_SPI_FLASH_OP_WREN,
2446 flash_table[hw->flash_vendor].cmdWREN);
2447 ATL2_WRITE_REGB(hw, REG_SPI_FLASH_OP_RDSR,
2448 flash_table[hw->flash_vendor].cmdRDSR);
2449 ATL2_WRITE_REGB(hw, REG_SPI_FLASH_OP_WRSR,
2450 flash_table[hw->flash_vendor].cmdWRSR);
2451 ATL2_WRITE_REGB(hw, REG_SPI_FLASH_OP_READ,
2452 flash_table[hw->flash_vendor].cmdREAD);
2453}
2454
2455/********************************************************************
2456* Performs basic configuration of the adapter.
2457*
2458* hw - Struct containing variables accessed by shared code
2459* Assumes that the controller has previously been reset and is in a
2460* post-reset uninitialized state. Initializes multicast table,
2461* and Calls routines to setup link
2462* Leaves the transmit and receive units disabled and uninitialized.
2463********************************************************************/
2464static s32 atl2_init_hw(struct atl2_hw *hw)
2465{
2466 u32 ret_val = 0;
2467
2468 atl2_init_pcie(hw);
2469
2470 /* Zero out the Multicast HASH table */
2471 /* clear the old settings from the multicast hash table */
2472 ATL2_WRITE_REG(hw, REG_RX_HASH_TABLE, 0);
2473 ATL2_WRITE_REG_ARRAY(hw, REG_RX_HASH_TABLE, 1, 0);
2474
2475 atl2_init_flash_opcode(hw);
2476
2477 ret_val = atl2_phy_init(hw);
2478
2479 return ret_val;
2480}
2481
2482/*
2483 * Detects the current speed and duplex settings of the hardware.
2484 *
2485 * hw - Struct containing variables accessed by shared code
2486 * speed - Speed of the connection
2487 * duplex - Duplex setting of the connection
2488 */
2489static s32 atl2_get_speed_and_duplex(struct atl2_hw *hw, u16 *speed,
2490 u16 *duplex)
2491{
2492 s32 ret_val;
2493 u16 phy_data;
2494
2495 /* Read PHY Specific Status Register (17) */
2496 ret_val = atl2_read_phy_reg(hw, MII_ATLX_PSSR, &phy_data);
2497 if (ret_val)
2498 return ret_val;
2499
2500 if (!(phy_data & MII_ATLX_PSSR_SPD_DPLX_RESOLVED))
2501 return ATLX_ERR_PHY_RES;
2502
2503 switch (phy_data & MII_ATLX_PSSR_SPEED) {
2504 case MII_ATLX_PSSR_100MBS:
2505 *speed = SPEED_100;
2506 break;
2507 case MII_ATLX_PSSR_10MBS:
2508 *speed = SPEED_10;
2509 break;
2510 default:
2511 return ATLX_ERR_PHY_SPEED;
2512 break;
2513 }
2514
2515 if (phy_data & MII_ATLX_PSSR_DPLX)
2516 *duplex = FULL_DUPLEX;
2517 else
2518 *duplex = HALF_DUPLEX;
2519
2520 return 0;
2521}
2522
2523/*
2524 * Reads the value from a PHY register
2525 * hw - Struct containing variables accessed by shared code
2526 * reg_addr - address of the PHY register to read
2527 */
2528static s32 atl2_read_phy_reg(struct atl2_hw *hw, u16 reg_addr, u16 *phy_data)
2529{
2530 u32 val;
2531 int i;
2532
2533 val = ((u32)(reg_addr & MDIO_REG_ADDR_MASK)) << MDIO_REG_ADDR_SHIFT |
2534 MDIO_START |
2535 MDIO_SUP_PREAMBLE |
2536 MDIO_RW |
2537 MDIO_CLK_25_4 << MDIO_CLK_SEL_SHIFT;
2538 ATL2_WRITE_REG(hw, REG_MDIO_CTRL, val);
2539
2540 wmb();
2541
2542 for (i = 0; i < MDIO_WAIT_TIMES; i++) {
2543 udelay(2);
2544 val = ATL2_READ_REG(hw, REG_MDIO_CTRL);
2545 if (!(val & (MDIO_START | MDIO_BUSY)))
2546 break;
2547 wmb();
2548 }
2549 if (!(val & (MDIO_START | MDIO_BUSY))) {
2550 *phy_data = (u16)val;
2551 return 0;
2552 }
2553
2554 return ATLX_ERR_PHY;
2555}
2556
2557/*
2558 * Writes a value to a PHY register
2559 * hw - Struct containing variables accessed by shared code
2560 * reg_addr - address of the PHY register to write
2561 * data - data to write to the PHY
2562 */
2563static s32 atl2_write_phy_reg(struct atl2_hw *hw, u32 reg_addr, u16 phy_data)
2564{
2565 int i;
2566 u32 val;
2567
2568 val = ((u32)(phy_data & MDIO_DATA_MASK)) << MDIO_DATA_SHIFT |
2569 (reg_addr & MDIO_REG_ADDR_MASK) << MDIO_REG_ADDR_SHIFT |
2570 MDIO_SUP_PREAMBLE |
2571 MDIO_START |
2572 MDIO_CLK_25_4 << MDIO_CLK_SEL_SHIFT;
2573 ATL2_WRITE_REG(hw, REG_MDIO_CTRL, val);
2574
2575 wmb();
2576
2577 for (i = 0; i < MDIO_WAIT_TIMES; i++) {
2578 udelay(2);
2579 val = ATL2_READ_REG(hw, REG_MDIO_CTRL);
2580 if (!(val & (MDIO_START | MDIO_BUSY)))
2581 break;
2582
2583 wmb();
2584 }
2585
2586 if (!(val & (MDIO_START | MDIO_BUSY)))
2587 return 0;
2588
2589 return ATLX_ERR_PHY;
2590}
2591
2592/*
2593 * Configures PHY autoneg and flow control advertisement settings
2594 *
2595 * hw - Struct containing variables accessed by shared code
2596 */
2597static s32 atl2_phy_setup_autoneg_adv(struct atl2_hw *hw)
2598{
2599 s32 ret_val;
2600 s16 mii_autoneg_adv_reg;
2601
2602 /* Read the MII Auto-Neg Advertisement Register (Address 4). */
2603 mii_autoneg_adv_reg = MII_AR_DEFAULT_CAP_MASK;
2604
2605 /* Need to parse autoneg_advertised and set up
2606 * the appropriate PHY registers. First we will parse for
2607 * autoneg_advertised software override. Since we can advertise
2608 * a plethora of combinations, we need to check each bit
2609 * individually.
2610 */
2611
2612 /* First we clear all the 10/100 mb speed bits in the Auto-Neg
2613 * Advertisement Register (Address 4) and the 1000 mb speed bits in
2614 * the 1000Base-T Control Register (Address 9). */
2615 mii_autoneg_adv_reg &= ~MII_AR_SPEED_MASK;
2616
2617 /* Need to parse MediaType and setup the
2618 * appropriate PHY registers. */
2619 switch (hw->MediaType) {
2620 case MEDIA_TYPE_AUTO_SENSOR:
2621 mii_autoneg_adv_reg |=
2622 (MII_AR_10T_HD_CAPS |
2623 MII_AR_10T_FD_CAPS |
2624 MII_AR_100TX_HD_CAPS|
2625 MII_AR_100TX_FD_CAPS);
2626 hw->autoneg_advertised =
2627 ADVERTISE_10_HALF |
2628 ADVERTISE_10_FULL |
2629 ADVERTISE_100_HALF|
2630 ADVERTISE_100_FULL;
2631 break;
2632 case MEDIA_TYPE_100M_FULL:
2633 mii_autoneg_adv_reg |= MII_AR_100TX_FD_CAPS;
2634 hw->autoneg_advertised = ADVERTISE_100_FULL;
2635 break;
2636 case MEDIA_TYPE_100M_HALF:
2637 mii_autoneg_adv_reg |= MII_AR_100TX_HD_CAPS;
2638 hw->autoneg_advertised = ADVERTISE_100_HALF;
2639 break;
2640 case MEDIA_TYPE_10M_FULL:
2641 mii_autoneg_adv_reg |= MII_AR_10T_FD_CAPS;
2642 hw->autoneg_advertised = ADVERTISE_10_FULL;
2643 break;
2644 default:
2645 mii_autoneg_adv_reg |= MII_AR_10T_HD_CAPS;
2646 hw->autoneg_advertised = ADVERTISE_10_HALF;
2647 break;
2648 }
2649
2650 /* flow control fixed to enable all */
2651 mii_autoneg_adv_reg |= (MII_AR_ASM_DIR | MII_AR_PAUSE);
2652
2653 hw->mii_autoneg_adv_reg = mii_autoneg_adv_reg;
2654
2655 ret_val = atl2_write_phy_reg(hw, MII_ADVERTISE, mii_autoneg_adv_reg);
2656
2657 if (ret_val)
2658 return ret_val;
2659
2660 return 0;
2661}
2662
2663/*
2664 * Resets the PHY and make all config validate
2665 *
2666 * hw - Struct containing variables accessed by shared code
2667 *
2668 * Sets bit 15 and 12 of the MII Control regiser (for F001 bug)
2669 */
2670static s32 atl2_phy_commit(struct atl2_hw *hw)
2671{
2672 s32 ret_val;
2673 u16 phy_data;
2674
2675 phy_data = MII_CR_RESET | MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG;
2676 ret_val = atl2_write_phy_reg(hw, MII_BMCR, phy_data);
2677 if (ret_val) {
2678 u32 val;
2679 int i;
2680 /* pcie serdes link may be down ! */
2681 for (i = 0; i < 25; i++) {
2682 msleep(1);
2683 val = ATL2_READ_REG(hw, REG_MDIO_CTRL);
2684 if (!(val & (MDIO_START | MDIO_BUSY)))
2685 break;
2686 }
2687
2688 if (0 != (val & (MDIO_START | MDIO_BUSY))) {
2689 printk(KERN_ERR "atl2: PCIe link down for at least 25ms !\n");
2690 return ret_val;
2691 }
2692 }
2693 return 0;
2694}
2695
2696static s32 atl2_phy_init(struct atl2_hw *hw)
2697{
2698 s32 ret_val;
2699 u16 phy_val;
2700
2701 if (hw->phy_configured)
2702 return 0;
2703
2704 /* Enable PHY */
2705 ATL2_WRITE_REGW(hw, REG_PHY_ENABLE, 1);
2706 ATL2_WRITE_FLUSH(hw);
2707 msleep(1);
2708
2709 /* check if the PHY is in powersaving mode */
2710 atl2_write_phy_reg(hw, MII_DBG_ADDR, 0);
2711 atl2_read_phy_reg(hw, MII_DBG_DATA, &phy_val);
2712
2713 /* 024E / 124E 0r 0274 / 1274 ? */
2714 if (phy_val & 0x1000) {
2715 phy_val &= ~0x1000;
2716 atl2_write_phy_reg(hw, MII_DBG_DATA, phy_val);
2717 }
2718
2719 msleep(1);
2720
2721 /*Enable PHY LinkChange Interrupt */
2722 ret_val = atl2_write_phy_reg(hw, 18, 0xC00);
2723 if (ret_val)
2724 return ret_val;
2725
2726 /* setup AutoNeg parameters */
2727 ret_val = atl2_phy_setup_autoneg_adv(hw);
2728 if (ret_val)
2729 return ret_val;
2730
2731 /* SW.Reset & En-Auto-Neg to restart Auto-Neg */
2732 ret_val = atl2_phy_commit(hw);
2733 if (ret_val)
2734 return ret_val;
2735
2736 hw->phy_configured = true;
2737
2738 return ret_val;
2739}
2740
2741static void atl2_set_mac_addr(struct atl2_hw *hw)
2742{
2743 u32 value;
2744 /* 00-0B-6A-F6-00-DC
2745 * 0: 6AF600DC 1: 000B
2746 * low dword */
2747 value = (((u32)hw->mac_addr[2]) << 24) |
2748 (((u32)hw->mac_addr[3]) << 16) |
2749 (((u32)hw->mac_addr[4]) << 8) |
2750 (((u32)hw->mac_addr[5]));
2751 ATL2_WRITE_REG_ARRAY(hw, REG_MAC_STA_ADDR, 0, value);
2752 /* hight dword */
2753 value = (((u32)hw->mac_addr[0]) << 8) |
2754 (((u32)hw->mac_addr[1]));
2755 ATL2_WRITE_REG_ARRAY(hw, REG_MAC_STA_ADDR, 1, value);
2756}
2757
2758/*
2759 * check_eeprom_exist
2760 * return 0 if eeprom exist
2761 */
2762static int atl2_check_eeprom_exist(struct atl2_hw *hw)
2763{
2764 u32 value;
2765
2766 value = ATL2_READ_REG(hw, REG_SPI_FLASH_CTRL);
2767 if (value & SPI_FLASH_CTRL_EN_VPD) {
2768 value &= ~SPI_FLASH_CTRL_EN_VPD;
2769 ATL2_WRITE_REG(hw, REG_SPI_FLASH_CTRL, value);
2770 }
2771 value = ATL2_READ_REGW(hw, REG_PCIE_CAP_LIST);
2772 return ((value & 0xFF00) == 0x6C00) ? 0 : 1;
2773}
2774
2775/* FIXME: This doesn't look right. -- CHS */
2776static bool atl2_write_eeprom(struct atl2_hw *hw, u32 offset, u32 value)
2777{
2778 return true;
2779}
2780
2781static bool atl2_read_eeprom(struct atl2_hw *hw, u32 Offset, u32 *pValue)
2782{
2783 int i;
2784 u32 Control;
2785
2786 if (Offset & 0x3)
2787 return false; /* address do not align */
2788
2789 ATL2_WRITE_REG(hw, REG_VPD_DATA, 0);
2790 Control = (Offset & VPD_CAP_VPD_ADDR_MASK) << VPD_CAP_VPD_ADDR_SHIFT;
2791 ATL2_WRITE_REG(hw, REG_VPD_CAP, Control);
2792
2793 for (i = 0; i < 10; i++) {
2794 msleep(2);
2795 Control = ATL2_READ_REG(hw, REG_VPD_CAP);
2796 if (Control & VPD_CAP_VPD_FLAG)
2797 break;
2798 }
2799
2800 if (Control & VPD_CAP_VPD_FLAG) {
2801 *pValue = ATL2_READ_REG(hw, REG_VPD_DATA);
2802 return true;
2803 }
2804 return false; /* timeout */
2805}
2806
2807static void atl2_force_ps(struct atl2_hw *hw)
2808{
2809 u16 phy_val;
2810
2811 atl2_write_phy_reg(hw, MII_DBG_ADDR, 0);
2812 atl2_read_phy_reg(hw, MII_DBG_DATA, &phy_val);
2813 atl2_write_phy_reg(hw, MII_DBG_DATA, phy_val | 0x1000);
2814
2815 atl2_write_phy_reg(hw, MII_DBG_ADDR, 2);
2816 atl2_write_phy_reg(hw, MII_DBG_DATA, 0x3000);
2817 atl2_write_phy_reg(hw, MII_DBG_ADDR, 3);
2818 atl2_write_phy_reg(hw, MII_DBG_DATA, 0);
2819}
2820
2821/* This is the only thing that needs to be changed to adjust the
2822 * maximum number of ports that the driver can manage.
2823 */
2824#define ATL2_MAX_NIC 4
2825
2826#define OPTION_UNSET -1
2827#define OPTION_DISABLED 0
2828#define OPTION_ENABLED 1
2829
2830/* All parameters are treated the same, as an integer array of values.
2831 * This macro just reduces the need to repeat the same declaration code
2832 * over and over (plus this helps to avoid typo bugs).
2833 */
2834#define ATL2_PARAM_INIT {[0 ... ATL2_MAX_NIC] = OPTION_UNSET}
2835#ifndef module_param_array
2836/* Module Parameters are always initialized to -1, so that the driver
2837 * can tell the difference between no user specified value or the
2838 * user asking for the default value.
2839 * The true default values are loaded in when atl2_check_options is called.
2840 *
2841 * This is a GCC extension to ANSI C.
2842 * See the item "Labeled Elements in Initializers" in the section
2843 * "Extensions to the C Language Family" of the GCC documentation.
2844 */
2845
2846#define ATL2_PARAM(X, desc) \
2847 static const int __devinitdata X[ATL2_MAX_NIC + 1] = ATL2_PARAM_INIT; \
2848 MODULE_PARM(X, "1-" __MODULE_STRING(ATL2_MAX_NIC) "i"); \
2849 MODULE_PARM_DESC(X, desc);
2850#else
2851#define ATL2_PARAM(X, desc) \
2852 static int __devinitdata X[ATL2_MAX_NIC+1] = ATL2_PARAM_INIT; \
b79d8fff 2853 static unsigned int num_##X; \
452c1ce2
CS		 2854 module_param_array_named(X, X, int, &num_##X, 0); \
2855 MODULE_PARM_DESC(X, desc);
2856#endif
2857
2858/*
2859 * Transmit Memory Size
2860 * Valid Range: 64-2048
2861 * Default Value: 128
2862 */
2863#define ATL2_MIN_TX_MEMSIZE 4 /* 4KB */
2864#define ATL2_MAX_TX_MEMSIZE 64 /* 64KB */
2865#define ATL2_DEFAULT_TX_MEMSIZE 8 /* 8KB */
2866ATL2_PARAM(TxMemSize, "Bytes of Transmit Memory");
2867
2868/*
2869 * Receive Memory Block Count
2870 * Valid Range: 16-512
2871 * Default Value: 128
2872 */
2873#define ATL2_MIN_RXD_COUNT 16
2874#define ATL2_MAX_RXD_COUNT 512
2875#define ATL2_DEFAULT_RXD_COUNT 64
2876ATL2_PARAM(RxMemBlock, "Number of receive memory block");
2877
2878/*
2879 * User Specified MediaType Override
2880 *
2881 * Valid Range: 0-5
2882 * - 0 - auto-negotiate at all supported speeds
2883 * - 1 - only link at 1000Mbps Full Duplex
2884 * - 2 - only link at 100Mbps Full Duplex
2885 * - 3 - only link at 100Mbps Half Duplex
2886 * - 4 - only link at 10Mbps Full Duplex
2887 * - 5 - only link at 10Mbps Half Duplex
2888 * Default Value: 0
2889 */
2890ATL2_PARAM(MediaType, "MediaType Select");
2891
2892/*
2893 * Interrupt Moderate Timer in units of 2048 ns (~2 us)
2894 * Valid Range: 10-65535
2895 * Default Value: 45000(90ms)
2896 */
2897#define INT_MOD_DEFAULT_CNT 100 /* 200us */
2898#define INT_MOD_MAX_CNT 65000
2899#define INT_MOD_MIN_CNT 50
2900ATL2_PARAM(IntModTimer, "Interrupt Moderator Timer");
2901
2902/*
2903 * FlashVendor
2904 * Valid Range: 0-2
2905 * 0 - Atmel
2906 * 1 - SST
2907 * 2 - ST
2908 */
2909ATL2_PARAM(FlashVendor, "SPI Flash Vendor");
2910
2911#define AUTONEG_ADV_DEFAULT 0x2F
2912#define AUTONEG_ADV_MASK 0x2F
2913#define FLOW_CONTROL_DEFAULT FLOW_CONTROL_FULL
2914
2915#define FLASH_VENDOR_DEFAULT 0
2916#define FLASH_VENDOR_MIN 0
2917#define FLASH_VENDOR_MAX 2
2918
2919struct atl2_option {
2920 enum { enable_option, range_option, list_option } type;
2921 char *name;
2922 char *err;
2923 int def;
2924 union {
2925 struct { /* range_option info */
2926 int min;
2927 int max;
2928 } r;
2929 struct { /* list_option info */
2930 int nr;
2931 struct atl2_opt_list { int i; char *str; } *p;
2932 } l;
2933 } arg;
2934};
2935
2936static int __devinit atl2_validate_option(int *value, struct atl2_option *opt)
2937{
2938 int i;
2939 struct atl2_opt_list *ent;
2940
2941 if (*value == OPTION_UNSET) {
2942 *value = opt->def;
2943 return 0;
2944 }
2945
2946 switch (opt->type) {
2947 case enable_option:
2948 switch (*value) {
2949 case OPTION_ENABLED:
2950 printk(KERN_INFO "%s Enabled\n", opt->name);
2951 return 0;
2952 break;
2953 case OPTION_DISABLED:
2954 printk(KERN_INFO "%s Disabled\n", opt->name);
2955 return 0;
2956 break;
2957 }
2958 break;
2959 case range_option:
2960 if (*value >= opt->arg.r.min && *value <= opt->arg.r.max) {
2961 printk(KERN_INFO "%s set to %i\n", opt->name, *value);
2962 return 0;
2963 }
2964 break;
2965 case list_option:
2966 for (i = 0; i < opt->arg.l.nr; i++) {
2967 ent = &opt->arg.l.p[i];
2968 if (*value == ent->i) {
2969 if (ent->str[0] != '\0')
2970 printk(KERN_INFO "%s\n", ent->str);
2971 return 0;
2972 }
2973 }
2974 break;
2975 default:
2976 BUG();
2977 }
2978
2979 printk(KERN_INFO "Invalid %s specified (%i) %s\n",
2980 opt->name, *value, opt->err);
2981 *value = opt->def;
2982 return -1;
2983}
2984
2985/*
2986 * atl2_check_options - Range Checking for Command Line Parameters
2987 * @adapter: board private structure
2988 *
2989 * This routine checks all command line parameters for valid user
2990 * input. If an invalid value is given, or if no user specified
2991 * value exists, a default value is used. The final value is stored
2992 * in a variable in the adapter structure.
2993 */
2994static void __devinit atl2_check_options(struct atl2_adapter *adapter)
2995{
2996 int val;
2997 struct atl2_option opt;
2998 int bd = adapter->bd_number;
2999 if (bd >= ATL2_MAX_NIC) {
3000 printk(KERN_NOTICE "Warning: no configuration for board #%i\n",
3001 bd);
3002 printk(KERN_NOTICE "Using defaults for all values\n");
3003#ifndef module_param_array
3004 bd = ATL2_MAX_NIC;
3005#endif
3006 }
3007
3008 /* Bytes of Transmit Memory */
3009 opt.type = range_option;
3010 opt.name = "Bytes of Transmit Memory";
3011 opt.err = "using default of " __MODULE_STRING(ATL2_DEFAULT_TX_MEMSIZE);
3012 opt.def = ATL2_DEFAULT_TX_MEMSIZE;
3013 opt.arg.r.min = ATL2_MIN_TX_MEMSIZE;
3014 opt.arg.r.max = ATL2_MAX_TX_MEMSIZE;
3015#ifdef module_param_array
3016 if (num_TxMemSize > bd) {
3017#endif
3018 val = TxMemSize[bd];
3019 atl2_validate_option(&val, &opt);
3020 adapter->txd_ring_size = ((u32) val) * 1024;
3021#ifdef module_param_array
3022 } else
3023 adapter->txd_ring_size = ((u32)opt.def) * 1024;
3024#endif
3025 /* txs ring size: */
3026 adapter->txs_ring_size = adapter->txd_ring_size / 128;
3027 if (adapter->txs_ring_size > 160)
3028 adapter->txs_ring_size = 160;
3029
3030 /* Receive Memory Block Count */
3031 opt.type = range_option;
3032 opt.name = "Number of receive memory block";
3033 opt.err = "using default of " __MODULE_STRING(ATL2_DEFAULT_RXD_COUNT);
3034 opt.def = ATL2_DEFAULT_RXD_COUNT;
3035 opt.arg.r.min = ATL2_MIN_RXD_COUNT;
3036 opt.arg.r.max = ATL2_MAX_RXD_COUNT;
3037#ifdef module_param_array
3038 if (num_RxMemBlock > bd) {
3039#endif
3040 val = RxMemBlock[bd];
3041 atl2_validate_option(&val, &opt);
3042 adapter->rxd_ring_size = (u32)val;
3043 /* FIXME */
3044 /* ((u16)val)&~1; */ /* even number */
3045#ifdef module_param_array
3046 } else
3047 adapter->rxd_ring_size = (u32)opt.def;
3048#endif
3049 /* init RXD Flow control value */
3050 adapter->hw.fc_rxd_hi = (adapter->rxd_ring_size / 8) * 7;
3051 adapter->hw.fc_rxd_lo = (ATL2_MIN_RXD_COUNT / 8) >
3052 (adapter->rxd_ring_size / 12) ? (ATL2_MIN_RXD_COUNT / 8) :
3053 (adapter->rxd_ring_size / 12);
3054
3055 /* Interrupt Moderate Timer */
3056 opt.type = range_option;
3057 opt.name = "Interrupt Moderate Timer";
3058 opt.err = "using default of " __MODULE_STRING(INT_MOD_DEFAULT_CNT);
3059 opt.def = INT_MOD_DEFAULT_CNT;
3060 opt.arg.r.min = INT_MOD_MIN_CNT;
3061 opt.arg.r.max = INT_MOD_MAX_CNT;
3062#ifdef module_param_array
3063 if (num_IntModTimer > bd) {
3064#endif
3065 val = IntModTimer[bd];
3066 atl2_validate_option(&val, &opt);
3067 adapter->imt = (u16) val;
3068#ifdef module_param_array
3069 } else
3070 adapter->imt = (u16)(opt.def);
3071#endif
3072 /* Flash Vendor */
3073 opt.type = range_option;
3074 opt.name = "SPI Flash Vendor";
3075 opt.err = "using default of " __MODULE_STRING(FLASH_VENDOR_DEFAULT);
3076 opt.def = FLASH_VENDOR_DEFAULT;
3077 opt.arg.r.min = FLASH_VENDOR_MIN;
3078 opt.arg.r.max = FLASH_VENDOR_MAX;
3079#ifdef module_param_array
3080 if (num_FlashVendor > bd) {
3081#endif
3082 val = FlashVendor[bd];
3083 atl2_validate_option(&val, &opt);
3084 adapter->hw.flash_vendor = (u8) val;
3085#ifdef module_param_array
3086 } else
3087 adapter->hw.flash_vendor = (u8)(opt.def);
3088#endif
3089 /* MediaType */
3090 opt.type = range_option;
3091 opt.name = "Speed/Duplex Selection";
3092 opt.err = "using default of " __MODULE_STRING(MEDIA_TYPE_AUTO_SENSOR);
3093 opt.def = MEDIA_TYPE_AUTO_SENSOR;
3094 opt.arg.r.min = MEDIA_TYPE_AUTO_SENSOR;
3095 opt.arg.r.max = MEDIA_TYPE_10M_HALF;
3096#ifdef module_param_array
3097 if (num_MediaType > bd) {
3098#endif
3099 val = MediaType[bd];
3100 atl2_validate_option(&val, &opt);
3101 adapter->hw.MediaType = (u16) val;
3102#ifdef module_param_array
3103 } else
3104 adapter->hw.MediaType = (u16)(opt.def);
3105#endif
3106}
Linux kernel - Deliverables
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