Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * | |
3 | * Alchemy Au1x00 ethernet driver | |
4 | * | |
89be0501 | 5 | * Copyright 2001-2003, 2006 MontaVista Software Inc. |
1da177e4 LT |
6 | * Copyright 2002 TimeSys Corp. |
7 | * Added ethtool/mii-tool support, | |
8 | * Copyright 2004 Matt Porter <mporter@kernel.crashing.org> | |
6aa20a22 JG |
9 | * Update: 2004 Bjoern Riemer, riemer@fokus.fraunhofer.de |
10 | * or riemer@riemer-nt.de: fixed the link beat detection with | |
1da177e4 | 11 | * ioctls (SIOCGMIIPHY) |
0638dec0 HVR |
12 | * Copyright 2006 Herbert Valerio Riedel <hvr@gnu.org> |
13 | * converted to use linux-2.6.x's PHY framework | |
14 | * | |
1da177e4 LT |
15 | * Author: MontaVista Software, Inc. |
16 | * ppopov@mvista.com or source@mvista.com | |
17 | * | |
18 | * ######################################################################## | |
19 | * | |
20 | * This program is free software; you can distribute it and/or modify it | |
21 | * under the terms of the GNU General Public License (Version 2) as | |
22 | * published by the Free Software Foundation. | |
23 | * | |
24 | * This program is distributed in the hope it will be useful, but WITHOUT | |
25 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
26 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
27 | * for more details. | |
28 | * | |
29 | * You should have received a copy of the GNU General Public License along | |
30 | * with this program; if not, write to the Free Software Foundation, Inc., | |
31 | * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. | |
32 | * | |
33 | * ######################################################################## | |
34 | * | |
6aa20a22 | 35 | * |
1da177e4 | 36 | */ |
bc36b428 | 37 | #include <linux/capability.h> |
d791c2bd | 38 | #include <linux/dma-mapping.h> |
1da177e4 LT |
39 | #include <linux/module.h> |
40 | #include <linux/kernel.h> | |
1da177e4 LT |
41 | #include <linux/string.h> |
42 | #include <linux/timer.h> | |
43 | #include <linux/errno.h> | |
44 | #include <linux/in.h> | |
45 | #include <linux/ioport.h> | |
46 | #include <linux/bitops.h> | |
47 | #include <linux/slab.h> | |
48 | #include <linux/interrupt.h> | |
1da177e4 LT |
49 | #include <linux/init.h> |
50 | #include <linux/netdevice.h> | |
51 | #include <linux/etherdevice.h> | |
52 | #include <linux/ethtool.h> | |
53 | #include <linux/mii.h> | |
54 | #include <linux/skbuff.h> | |
55 | #include <linux/delay.h> | |
8cd35da0 | 56 | #include <linux/crc32.h> |
0638dec0 | 57 | #include <linux/phy.h> |
bd2302c2 | 58 | #include <linux/platform_device.h> |
25b31cb1 YY |
59 | |
60 | #include <asm/cpu.h> | |
1da177e4 LT |
61 | #include <asm/mipsregs.h> |
62 | #include <asm/irq.h> | |
63 | #include <asm/io.h> | |
64 | #include <asm/processor.h> | |
65 | ||
25b31cb1 | 66 | #include <au1000.h> |
bd2302c2 | 67 | #include <au1xxx_eth.h> |
25b31cb1 YY |
68 | #include <prom.h> |
69 | ||
1da177e4 LT |
70 | #include "au1000_eth.h" |
71 | ||
72 | #ifdef AU1000_ETH_DEBUG | |
73 | static int au1000_debug = 5; | |
74 | #else | |
75 | static int au1000_debug = 3; | |
76 | #endif | |
77 | ||
7cd2e6e3 FF |
78 | #define AU1000_DEF_MSG_ENABLE (NETIF_MSG_DRV | \ |
79 | NETIF_MSG_PROBE | \ | |
80 | NETIF_MSG_LINK) | |
81 | ||
89be0501 | 82 | #define DRV_NAME "au1000_eth" |
8020eb82 | 83 | #define DRV_VERSION "1.7" |
1da177e4 LT |
84 | #define DRV_AUTHOR "Pete Popov <ppopov@embeddedalley.com>" |
85 | #define DRV_DESC "Au1xxx on-chip Ethernet driver" | |
86 | ||
87 | MODULE_AUTHOR(DRV_AUTHOR); | |
88 | MODULE_DESCRIPTION(DRV_DESC); | |
89 | MODULE_LICENSE("GPL"); | |
13130c7a | 90 | MODULE_VERSION(DRV_VERSION); |
1da177e4 | 91 | |
1da177e4 LT |
92 | /* |
93 | * Theory of operation | |
94 | * | |
6aa20a22 JG |
95 | * The Au1000 MACs use a simple rx and tx descriptor ring scheme. |
96 | * There are four receive and four transmit descriptors. These | |
97 | * descriptors are not in memory; rather, they are just a set of | |
1da177e4 LT |
98 | * hardware registers. |
99 | * | |
100 | * Since the Au1000 has a coherent data cache, the receive and | |
6aa20a22 | 101 | * transmit buffers are allocated from the KSEG0 segment. The |
1da177e4 LT |
102 | * hardware registers, however, are still mapped at KSEG1 to |
103 | * make sure there's no out-of-order writes, and that all writes | |
104 | * complete immediately. | |
105 | */ | |
106 | ||
107 | /* These addresses are only used if yamon doesn't tell us what | |
108 | * the mac address is, and the mac address is not passed on the | |
109 | * command line. | |
110 | */ | |
6aa20a22 | 111 | static unsigned char au1000_mac_addr[6] __devinitdata = { |
1da177e4 LT |
112 | 0x00, 0x50, 0xc2, 0x0c, 0x30, 0x00 |
113 | }; | |
114 | ||
1da177e4 LT |
115 | struct au1000_private *au_macs[NUM_ETH_INTERFACES]; |
116 | ||
0638dec0 HVR |
117 | /* |
118 | * board-specific configurations | |
119 | * | |
120 | * PHY detection algorithm | |
121 | * | |
bd2302c2 | 122 | * If phy_static_config is undefined, the PHY setup is |
0638dec0 HVR |
123 | * autodetected: |
124 | * | |
125 | * mii_probe() first searches the current MAC's MII bus for a PHY, | |
bd2302c2 | 126 | * selecting the first (or last, if phy_search_highest_addr is |
0638dec0 HVR |
127 | * defined) PHY address not already claimed by another netdev. |
128 | * | |
129 | * If nothing was found that way when searching for the 2nd ethernet | |
bd2302c2 | 130 | * controller's PHY and phy1_search_mac0 is defined, then |
0638dec0 HVR |
131 | * the first MII bus is searched as well for an unclaimed PHY; this is |
132 | * needed in case of a dual-PHY accessible only through the MAC0's MII | |
133 | * bus. | |
134 | * | |
135 | * Finally, if no PHY is found, then the corresponding ethernet | |
136 | * controller is not registered to the network subsystem. | |
1da177e4 LT |
137 | */ |
138 | ||
bd2302c2 | 139 | /* autodetection defaults: phy1_search_mac0 */ |
1da177e4 | 140 | |
0638dec0 HVR |
141 | /* static PHY setup |
142 | * | |
143 | * most boards PHY setup should be detectable properly with the | |
144 | * autodetection algorithm in mii_probe(), but in some cases (e.g. if | |
145 | * you have a switch attached, or want to use the PHY's interrupt | |
146 | * notification capabilities) you can provide a static PHY | |
147 | * configuration here | |
148 | * | |
149 | * IRQs may only be set, if a PHY address was configured | |
150 | * If a PHY address is given, also a bus id is required to be set | |
151 | * | |
152 | * ps: make sure the used irqs are configured properly in the board | |
153 | * specific irq-map | |
154 | */ | |
1da177e4 | 155 | |
eb049630 | 156 | static void au1000_enable_mac(struct net_device *dev, int force_reset) |
5ef3041e FF |
157 | { |
158 | unsigned long flags; | |
159 | struct au1000_private *aup = netdev_priv(dev); | |
160 | ||
161 | spin_lock_irqsave(&aup->lock, flags); | |
162 | ||
163 | if(force_reset || (!aup->mac_enabled)) { | |
164 | *aup->enable = MAC_EN_CLOCK_ENABLE; | |
165 | au_sync_delay(2); | |
166 | *aup->enable = (MAC_EN_RESET0 | MAC_EN_RESET1 | MAC_EN_RESET2 | |
167 | | MAC_EN_CLOCK_ENABLE); | |
168 | au_sync_delay(2); | |
169 | ||
170 | aup->mac_enabled = 1; | |
171 | } | |
172 | ||
173 | spin_unlock_irqrestore(&aup->lock, flags); | |
174 | } | |
175 | ||
0638dec0 HVR |
176 | /* |
177 | * MII operations | |
178 | */ | |
1210dde7 | 179 | static int au1000_mdio_read(struct net_device *dev, int phy_addr, int reg) |
1da177e4 | 180 | { |
454d7c9b | 181 | struct au1000_private *aup = netdev_priv(dev); |
0638dec0 HVR |
182 | volatile u32 *const mii_control_reg = &aup->mac->mii_control; |
183 | volatile u32 *const mii_data_reg = &aup->mac->mii_data; | |
1da177e4 LT |
184 | u32 timedout = 20; |
185 | u32 mii_control; | |
186 | ||
1da177e4 LT |
187 | while (*mii_control_reg & MAC_MII_BUSY) { |
188 | mdelay(1); | |
189 | if (--timedout == 0) { | |
5368c726 | 190 | netdev_err(dev, "read_MII busy timeout!!\n"); |
1da177e4 LT |
191 | return -1; |
192 | } | |
193 | } | |
194 | ||
6aa20a22 | 195 | mii_control = MAC_SET_MII_SELECT_REG(reg) | |
0638dec0 | 196 | MAC_SET_MII_SELECT_PHY(phy_addr) | MAC_MII_READ; |
1da177e4 LT |
197 | |
198 | *mii_control_reg = mii_control; | |
199 | ||
200 | timedout = 20; | |
201 | while (*mii_control_reg & MAC_MII_BUSY) { | |
202 | mdelay(1); | |
203 | if (--timedout == 0) { | |
5368c726 | 204 | netdev_err(dev, "mdio_read busy timeout!!\n"); |
1da177e4 LT |
205 | return -1; |
206 | } | |
207 | } | |
208 | return (int)*mii_data_reg; | |
209 | } | |
210 | ||
1210dde7 AB |
211 | static void au1000_mdio_write(struct net_device *dev, int phy_addr, |
212 | int reg, u16 value) | |
1da177e4 | 213 | { |
454d7c9b | 214 | struct au1000_private *aup = netdev_priv(dev); |
0638dec0 HVR |
215 | volatile u32 *const mii_control_reg = &aup->mac->mii_control; |
216 | volatile u32 *const mii_data_reg = &aup->mac->mii_data; | |
1da177e4 LT |
217 | u32 timedout = 20; |
218 | u32 mii_control; | |
219 | ||
1da177e4 LT |
220 | while (*mii_control_reg & MAC_MII_BUSY) { |
221 | mdelay(1); | |
222 | if (--timedout == 0) { | |
5368c726 | 223 | netdev_err(dev, "mdio_write busy timeout!!\n"); |
1da177e4 LT |
224 | return; |
225 | } | |
226 | } | |
227 | ||
6aa20a22 | 228 | mii_control = MAC_SET_MII_SELECT_REG(reg) | |
0638dec0 | 229 | MAC_SET_MII_SELECT_PHY(phy_addr) | MAC_MII_WRITE; |
1da177e4 LT |
230 | |
231 | *mii_data_reg = value; | |
232 | *mii_control_reg = mii_control; | |
233 | } | |
234 | ||
1210dde7 | 235 | static int au1000_mdiobus_read(struct mii_bus *bus, int phy_addr, int regnum) |
0638dec0 HVR |
236 | { |
237 | /* WARNING: bus->phy_map[phy_addr].attached_dev == dev does | |
238 | * _NOT_ hold (e.g. when PHY is accessed through other MAC's MII bus) */ | |
239 | struct net_device *const dev = bus->priv; | |
240 | ||
eb049630 | 241 | au1000_enable_mac(dev, 0); /* make sure the MAC associated with this |
0638dec0 | 242 | * mii_bus is enabled */ |
1210dde7 | 243 | return au1000_mdio_read(dev, phy_addr, regnum); |
0638dec0 | 244 | } |
1da177e4 | 245 | |
1210dde7 AB |
246 | static int au1000_mdiobus_write(struct mii_bus *bus, int phy_addr, int regnum, |
247 | u16 value) | |
1da177e4 | 248 | { |
0638dec0 | 249 | struct net_device *const dev = bus->priv; |
1da177e4 | 250 | |
eb049630 | 251 | au1000_enable_mac(dev, 0); /* make sure the MAC associated with this |
0638dec0 | 252 | * mii_bus is enabled */ |
1210dde7 | 253 | au1000_mdio_write(dev, phy_addr, regnum, value); |
0638dec0 | 254 | return 0; |
1da177e4 LT |
255 | } |
256 | ||
1210dde7 | 257 | static int au1000_mdiobus_reset(struct mii_bus *bus) |
1da177e4 | 258 | { |
0638dec0 | 259 | struct net_device *const dev = bus->priv; |
1da177e4 | 260 | |
eb049630 | 261 | au1000_enable_mac(dev, 0); /* make sure the MAC associated with this |
0638dec0 HVR |
262 | * mii_bus is enabled */ |
263 | return 0; | |
264 | } | |
1da177e4 | 265 | |
eb049630 | 266 | static void au1000_hard_stop(struct net_device *dev) |
5ef3041e FF |
267 | { |
268 | struct au1000_private *aup = netdev_priv(dev); | |
269 | ||
5368c726 | 270 | netif_dbg(aup, drv, dev, "hard stop\n"); |
5ef3041e FF |
271 | |
272 | aup->mac->control &= ~(MAC_RX_ENABLE | MAC_TX_ENABLE); | |
273 | au_sync_delay(10); | |
274 | } | |
275 | ||
eb049630 | 276 | static void au1000_enable_rx_tx(struct net_device *dev) |
5ef3041e FF |
277 | { |
278 | struct au1000_private *aup = netdev_priv(dev); | |
279 | ||
5368c726 | 280 | netif_dbg(aup, hw, dev, "enable_rx_tx\n"); |
5ef3041e FF |
281 | |
282 | aup->mac->control |= (MAC_RX_ENABLE | MAC_TX_ENABLE); | |
283 | au_sync_delay(10); | |
284 | } | |
285 | ||
286 | static void | |
287 | au1000_adjust_link(struct net_device *dev) | |
288 | { | |
289 | struct au1000_private *aup = netdev_priv(dev); | |
290 | struct phy_device *phydev = aup->phy_dev; | |
291 | unsigned long flags; | |
292 | ||
293 | int status_change = 0; | |
294 | ||
295 | BUG_ON(!aup->phy_dev); | |
296 | ||
297 | spin_lock_irqsave(&aup->lock, flags); | |
298 | ||
299 | if (phydev->link && (aup->old_speed != phydev->speed)) { | |
2cc3c6b1 | 300 | /* speed changed */ |
5ef3041e | 301 | |
2cc3c6b1 | 302 | switch (phydev->speed) { |
5ef3041e FF |
303 | case SPEED_10: |
304 | case SPEED_100: | |
305 | break; | |
306 | default: | |
5368c726 FF |
307 | netdev_warn(dev, "Speed (%d) is not 10/100 ???\n", |
308 | phydev->speed); | |
5ef3041e FF |
309 | break; |
310 | } | |
311 | ||
312 | aup->old_speed = phydev->speed; | |
313 | ||
314 | status_change = 1; | |
315 | } | |
316 | ||
317 | if (phydev->link && (aup->old_duplex != phydev->duplex)) { | |
2cc3c6b1 | 318 | /* duplex mode changed */ |
5ef3041e FF |
319 | |
320 | /* switching duplex mode requires to disable rx and tx! */ | |
eb049630 | 321 | au1000_hard_stop(dev); |
5ef3041e FF |
322 | |
323 | if (DUPLEX_FULL == phydev->duplex) | |
324 | aup->mac->control = ((aup->mac->control | |
325 | | MAC_FULL_DUPLEX) | |
326 | & ~MAC_DISABLE_RX_OWN); | |
327 | else | |
328 | aup->mac->control = ((aup->mac->control | |
329 | & ~MAC_FULL_DUPLEX) | |
330 | | MAC_DISABLE_RX_OWN); | |
331 | au_sync_delay(1); | |
332 | ||
eb049630 | 333 | au1000_enable_rx_tx(dev); |
5ef3041e FF |
334 | aup->old_duplex = phydev->duplex; |
335 | ||
336 | status_change = 1; | |
337 | } | |
338 | ||
2cc3c6b1 FF |
339 | if (phydev->link != aup->old_link) { |
340 | /* link state changed */ | |
5ef3041e FF |
341 | |
342 | if (!phydev->link) { | |
343 | /* link went down */ | |
344 | aup->old_speed = 0; | |
345 | aup->old_duplex = -1; | |
346 | } | |
347 | ||
348 | aup->old_link = phydev->link; | |
349 | status_change = 1; | |
350 | } | |
351 | ||
352 | spin_unlock_irqrestore(&aup->lock, flags); | |
353 | ||
354 | if (status_change) { | |
355 | if (phydev->link) | |
5368c726 FF |
356 | netdev_info(dev, "link up (%d/%s)\n", |
357 | phydev->speed, | |
5ef3041e FF |
358 | DUPLEX_FULL == phydev->duplex ? "Full" : "Half"); |
359 | else | |
5368c726 | 360 | netdev_info(dev, "link down\n"); |
5ef3041e FF |
361 | } |
362 | } | |
363 | ||
eb049630 | 364 | static int au1000_mii_probe (struct net_device *dev) |
0638dec0 | 365 | { |
454d7c9b | 366 | struct au1000_private *const aup = netdev_priv(dev); |
0638dec0 HVR |
367 | struct phy_device *phydev = NULL; |
368 | ||
bd2302c2 FF |
369 | if (aup->phy_static_config) { |
370 | BUG_ON(aup->mac_id < 0 || aup->mac_id > 1); | |
0638dec0 | 371 | |
bd2302c2 FF |
372 | if (aup->phy_addr) |
373 | phydev = aup->mii_bus->phy_map[aup->phy_addr]; | |
374 | else | |
5368c726 | 375 | netdev_info(dev, "using PHY-less setup\n"); |
0638dec0 | 376 | return 0; |
bd2302c2 FF |
377 | } else { |
378 | int phy_addr; | |
379 | ||
380 | /* find the first (lowest address) PHY on the current MAC's MII bus */ | |
381 | for (phy_addr = 0; phy_addr < PHY_MAX_ADDR; phy_addr++) | |
382 | if (aup->mii_bus->phy_map[phy_addr]) { | |
383 | phydev = aup->mii_bus->phy_map[phy_addr]; | |
384 | if (!aup->phy_search_highest_addr) | |
385 | break; /* break out with first one found */ | |
386 | } | |
1da177e4 | 387 | |
bd2302c2 FF |
388 | if (aup->phy1_search_mac0) { |
389 | /* try harder to find a PHY */ | |
390 | if (!phydev && (aup->mac_id == 1)) { | |
391 | /* no PHY found, maybe we have a dual PHY? */ | |
5368c726 | 392 | dev_info(&dev->dev, ": no PHY found on MAC1, " |
bd2302c2 | 393 | "let's see if it's attached to MAC0...\n"); |
0638dec0 | 394 | |
bd2302c2 FF |
395 | /* find the first (lowest address) non-attached PHY on |
396 | * the MAC0 MII bus */ | |
397 | for (phy_addr = 0; phy_addr < PHY_MAX_ADDR; phy_addr++) { | |
398 | struct phy_device *const tmp_phydev = | |
399 | aup->mii_bus->phy_map[phy_addr]; | |
0638dec0 | 400 | |
bd2302c2 FF |
401 | if (aup->mac_id == 1) |
402 | break; | |
0638dec0 | 403 | |
bd2302c2 FF |
404 | if (!tmp_phydev) |
405 | continue; /* no PHY here... */ | |
0638dec0 | 406 | |
bd2302c2 FF |
407 | if (tmp_phydev->attached_dev) |
408 | continue; /* already claimed by MAC0 */ | |
0638dec0 | 409 | |
bd2302c2 FF |
410 | phydev = tmp_phydev; |
411 | break; /* found it */ | |
412 | } | |
413 | } | |
1da177e4 LT |
414 | } |
415 | } | |
1da177e4 | 416 | |
0638dec0 | 417 | if (!phydev) { |
5368c726 | 418 | netdev_err(dev, "no PHY found\n"); |
1da177e4 LT |
419 | return -1; |
420 | } | |
421 | ||
0638dec0 | 422 | /* now we are supposed to have a proper phydev, to attach to... */ |
0638dec0 HVR |
423 | BUG_ON(phydev->attached_dev); |
424 | ||
db1d7bf7 KS |
425 | phydev = phy_connect(dev, dev_name(&phydev->dev), &au1000_adjust_link, |
426 | 0, PHY_INTERFACE_MODE_MII); | |
0638dec0 HVR |
427 | |
428 | if (IS_ERR(phydev)) { | |
5368c726 | 429 | netdev_err(dev, "Could not attach to PHY\n"); |
0638dec0 HVR |
430 | return PTR_ERR(phydev); |
431 | } | |
432 | ||
433 | /* mask with MAC supported features */ | |
434 | phydev->supported &= (SUPPORTED_10baseT_Half | |
435 | | SUPPORTED_10baseT_Full | |
436 | | SUPPORTED_100baseT_Half | |
437 | | SUPPORTED_100baseT_Full | |
438 | | SUPPORTED_Autoneg | |
439 | /* | SUPPORTED_Pause | SUPPORTED_Asym_Pause */ | |
440 | | SUPPORTED_MII | |
441 | | SUPPORTED_TP); | |
442 | ||
443 | phydev->advertising = phydev->supported; | |
444 | ||
445 | aup->old_link = 0; | |
446 | aup->old_speed = 0; | |
447 | aup->old_duplex = -1; | |
448 | aup->phy_dev = phydev; | |
449 | ||
5368c726 FF |
450 | netdev_info(dev, "attached PHY driver [%s] " |
451 | "(mii_bus:phy_addr=%s, irq=%d)\n", | |
db1d7bf7 | 452 | phydev->drv->name, dev_name(&phydev->dev), phydev->irq); |
1da177e4 LT |
453 | |
454 | return 0; | |
455 | } | |
456 | ||
457 | ||
458 | /* | |
459 | * Buffer allocation/deallocation routines. The buffer descriptor returned | |
6aa20a22 | 460 | * has the virtual and dma address of a buffer suitable for |
1da177e4 LT |
461 | * both, receive and transmit operations. |
462 | */ | |
eb049630 | 463 | static db_dest_t *au1000_GetFreeDB(struct au1000_private *aup) |
1da177e4 LT |
464 | { |
465 | db_dest_t *pDB; | |
466 | pDB = aup->pDBfree; | |
467 | ||
468 | if (pDB) { | |
469 | aup->pDBfree = pDB->pnext; | |
470 | } | |
471 | return pDB; | |
472 | } | |
473 | ||
eb049630 | 474 | void au1000_ReleaseDB(struct au1000_private *aup, db_dest_t *pDB) |
1da177e4 LT |
475 | { |
476 | db_dest_t *pDBfree = aup->pDBfree; | |
477 | if (pDBfree) | |
478 | pDBfree->pnext = pDB; | |
479 | aup->pDBfree = pDB; | |
480 | } | |
481 | ||
eb049630 | 482 | static void au1000_reset_mac_unlocked(struct net_device *dev) |
0638dec0 | 483 | { |
454d7c9b | 484 | struct au1000_private *const aup = netdev_priv(dev); |
0638dec0 HVR |
485 | int i; |
486 | ||
eb049630 | 487 | au1000_hard_stop(dev); |
0638dec0 HVR |
488 | |
489 | *aup->enable = MAC_EN_CLOCK_ENABLE; | |
490 | au_sync_delay(2); | |
491 | *aup->enable = 0; | |
492 | au_sync_delay(2); | |
493 | ||
1da177e4 LT |
494 | aup->tx_full = 0; |
495 | for (i = 0; i < NUM_RX_DMA; i++) { | |
496 | /* reset control bits */ | |
497 | aup->rx_dma_ring[i]->buff_stat &= ~0xf; | |
498 | } | |
499 | for (i = 0; i < NUM_TX_DMA; i++) { | |
500 | /* reset control bits */ | |
501 | aup->tx_dma_ring[i]->buff_stat &= ~0xf; | |
502 | } | |
0638dec0 HVR |
503 | |
504 | aup->mac_enabled = 0; | |
505 | ||
1da177e4 LT |
506 | } |
507 | ||
eb049630 | 508 | static void au1000_reset_mac(struct net_device *dev) |
0638dec0 | 509 | { |
454d7c9b | 510 | struct au1000_private *const aup = netdev_priv(dev); |
0638dec0 HVR |
511 | unsigned long flags; |
512 | ||
5368c726 FF |
513 | netif_dbg(aup, hw, dev, "reset mac, aup %x\n", |
514 | (unsigned)aup); | |
0638dec0 HVR |
515 | |
516 | spin_lock_irqsave(&aup->lock, flags); | |
517 | ||
eb049630 | 518 | au1000_reset_mac_unlocked (dev); |
0638dec0 HVR |
519 | |
520 | spin_unlock_irqrestore(&aup->lock, flags); | |
521 | } | |
1da177e4 | 522 | |
6aa20a22 | 523 | /* |
1da177e4 LT |
524 | * Setup the receive and transmit "rings". These pointers are the addresses |
525 | * of the rx and tx MAC DMA registers so they are fixed by the hardware -- | |
526 | * these are not descriptors sitting in memory. | |
527 | */ | |
6aa20a22 | 528 | static void |
eb049630 | 529 | au1000_setup_hw_rings(struct au1000_private *aup, u32 rx_base, u32 tx_base) |
1da177e4 LT |
530 | { |
531 | int i; | |
532 | ||
533 | for (i = 0; i < NUM_RX_DMA; i++) { | |
6aa20a22 | 534 | aup->rx_dma_ring[i] = |
1da177e4 LT |
535 | (volatile rx_dma_t *) (rx_base + sizeof(rx_dma_t)*i); |
536 | } | |
537 | for (i = 0; i < NUM_TX_DMA; i++) { | |
6aa20a22 | 538 | aup->tx_dma_ring[i] = |
1da177e4 LT |
539 | (volatile tx_dma_t *) (tx_base + sizeof(tx_dma_t)*i); |
540 | } | |
541 | } | |
542 | ||
0638dec0 HVR |
543 | /* |
544 | * ethtool operations | |
545 | */ | |
1da177e4 | 546 | |
0638dec0 | 547 | static int au1000_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) |
1da177e4 | 548 | { |
454d7c9b | 549 | struct au1000_private *aup = netdev_priv(dev); |
1da177e4 | 550 | |
0638dec0 HVR |
551 | if (aup->phy_dev) |
552 | return phy_ethtool_gset(aup->phy_dev, cmd); | |
1da177e4 | 553 | |
0638dec0 | 554 | return -EINVAL; |
1da177e4 LT |
555 | } |
556 | ||
0638dec0 | 557 | static int au1000_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) |
1da177e4 | 558 | { |
454d7c9b | 559 | struct au1000_private *aup = netdev_priv(dev); |
1da177e4 | 560 | |
0638dec0 HVR |
561 | if (!capable(CAP_NET_ADMIN)) |
562 | return -EPERM; | |
1da177e4 | 563 | |
0638dec0 HVR |
564 | if (aup->phy_dev) |
565 | return phy_ethtool_sset(aup->phy_dev, cmd); | |
1da177e4 | 566 | |
0638dec0 | 567 | return -EINVAL; |
1da177e4 LT |
568 | } |
569 | ||
570 | static void | |
571 | au1000_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info) | |
572 | { | |
454d7c9b | 573 | struct au1000_private *aup = netdev_priv(dev); |
1da177e4 LT |
574 | |
575 | strcpy(info->driver, DRV_NAME); | |
576 | strcpy(info->version, DRV_VERSION); | |
577 | info->fw_version[0] = '\0'; | |
578 | sprintf(info->bus_info, "%s %d", DRV_NAME, aup->mac_id); | |
579 | info->regdump_len = 0; | |
580 | } | |
581 | ||
7cd2e6e3 FF |
582 | static void au1000_set_msglevel(struct net_device *dev, u32 value) |
583 | { | |
584 | struct au1000_private *aup = netdev_priv(dev); | |
585 | aup->msg_enable = value; | |
586 | } | |
587 | ||
588 | static u32 au1000_get_msglevel(struct net_device *dev) | |
589 | { | |
590 | struct au1000_private *aup = netdev_priv(dev); | |
591 | return aup->msg_enable; | |
592 | } | |
593 | ||
7282d491 | 594 | static const struct ethtool_ops au1000_ethtool_ops = { |
1da177e4 LT |
595 | .get_settings = au1000_get_settings, |
596 | .set_settings = au1000_set_settings, | |
597 | .get_drvinfo = au1000_get_drvinfo, | |
0638dec0 | 598 | .get_link = ethtool_op_get_link, |
7cd2e6e3 FF |
599 | .get_msglevel = au1000_get_msglevel, |
600 | .set_msglevel = au1000_set_msglevel, | |
1da177e4 LT |
601 | }; |
602 | ||
5ef3041e FF |
603 | |
604 | /* | |
605 | * Initialize the interface. | |
606 | * | |
607 | * When the device powers up, the clocks are disabled and the | |
608 | * mac is in reset state. When the interface is closed, we | |
609 | * do the same -- reset the device and disable the clocks to | |
610 | * conserve power. Thus, whenever au1000_init() is called, | |
611 | * the device should already be in reset state. | |
612 | */ | |
613 | static int au1000_init(struct net_device *dev) | |
1da177e4 | 614 | { |
5ef3041e FF |
615 | struct au1000_private *aup = netdev_priv(dev); |
616 | unsigned long flags; | |
617 | int i; | |
618 | u32 control; | |
89be0501 | 619 | |
5368c726 | 620 | netif_dbg(aup, hw, dev, "au1000_init\n"); |
1da177e4 | 621 | |
5ef3041e | 622 | /* bring the device out of reset */ |
eb049630 | 623 | au1000_enable_mac(dev, 1); |
89be0501 | 624 | |
5ef3041e | 625 | spin_lock_irqsave(&aup->lock, flags); |
1da177e4 | 626 | |
5ef3041e FF |
627 | aup->mac->control = 0; |
628 | aup->tx_head = (aup->tx_dma_ring[0]->buff_stat & 0xC) >> 2; | |
629 | aup->tx_tail = aup->tx_head; | |
630 | aup->rx_head = (aup->rx_dma_ring[0]->buff_stat & 0xC) >> 2; | |
1da177e4 | 631 | |
5ef3041e FF |
632 | aup->mac->mac_addr_high = dev->dev_addr[5]<<8 | dev->dev_addr[4]; |
633 | aup->mac->mac_addr_low = dev->dev_addr[3]<<24 | dev->dev_addr[2]<<16 | | |
634 | dev->dev_addr[1]<<8 | dev->dev_addr[0]; | |
635 | ||
636 | for (i = 0; i < NUM_RX_DMA; i++) { | |
637 | aup->rx_dma_ring[i]->buff_stat |= RX_DMA_ENABLE; | |
1da177e4 | 638 | } |
5ef3041e | 639 | au_sync(); |
1da177e4 | 640 | |
5ef3041e FF |
641 | control = MAC_RX_ENABLE | MAC_TX_ENABLE; |
642 | #ifndef CONFIG_CPU_LITTLE_ENDIAN | |
643 | control |= MAC_BIG_ENDIAN; | |
644 | #endif | |
645 | if (aup->phy_dev) { | |
646 | if (aup->phy_dev->link && (DUPLEX_FULL == aup->phy_dev->duplex)) | |
647 | control |= MAC_FULL_DUPLEX; | |
648 | else | |
649 | control |= MAC_DISABLE_RX_OWN; | |
650 | } else { /* PHY-less op, assume full-duplex */ | |
651 | control |= MAC_FULL_DUPLEX; | |
1da177e4 LT |
652 | } |
653 | ||
5ef3041e FF |
654 | aup->mac->control = control; |
655 | aup->mac->vlan1_tag = 0x8100; /* activate vlan support */ | |
656 | au_sync(); | |
1da177e4 | 657 | |
5ef3041e FF |
658 | spin_unlock_irqrestore(&aup->lock, flags); |
659 | return 0; | |
660 | } | |
1da177e4 | 661 | |
eb049630 | 662 | static inline void au1000_update_rx_stats(struct net_device *dev, u32 status) |
5ef3041e | 663 | { |
5ef3041e | 664 | struct net_device_stats *ps = &dev->stats; |
1da177e4 | 665 | |
5ef3041e FF |
666 | ps->rx_packets++; |
667 | if (status & RX_MCAST_FRAME) | |
668 | ps->multicast++; | |
1da177e4 | 669 | |
5ef3041e FF |
670 | if (status & RX_ERROR) { |
671 | ps->rx_errors++; | |
672 | if (status & RX_MISSED_FRAME) | |
673 | ps->rx_missed_errors++; | |
4989ccb2 | 674 | if (status & (RX_OVERLEN | RX_RUNT | RX_LEN_ERROR)) |
5ef3041e FF |
675 | ps->rx_length_errors++; |
676 | if (status & RX_CRC_ERROR) | |
677 | ps->rx_crc_errors++; | |
678 | if (status & RX_COLL) | |
679 | ps->collisions++; | |
2cc3c6b1 | 680 | } else |
5ef3041e | 681 | ps->rx_bytes += status & RX_FRAME_LEN_MASK; |
298cf9be | 682 | |
1da177e4 LT |
683 | } |
684 | ||
6aa20a22 | 685 | /* |
5ef3041e | 686 | * Au1000 receive routine. |
1da177e4 | 687 | */ |
5ef3041e | 688 | static int au1000_rx(struct net_device *dev) |
1da177e4 | 689 | { |
454d7c9b | 690 | struct au1000_private *aup = netdev_priv(dev); |
5ef3041e FF |
691 | struct sk_buff *skb; |
692 | volatile rx_dma_t *prxd; | |
693 | u32 buff_stat, status; | |
694 | db_dest_t *pDB; | |
695 | u32 frmlen; | |
1da177e4 | 696 | |
5368c726 | 697 | netif_dbg(aup, rx_status, dev, "au1000_rx head %d\n", aup->rx_head); |
1da177e4 | 698 | |
5ef3041e FF |
699 | prxd = aup->rx_dma_ring[aup->rx_head]; |
700 | buff_stat = prxd->buff_stat; | |
701 | while (buff_stat & RX_T_DONE) { | |
702 | status = prxd->status; | |
703 | pDB = aup->rx_db_inuse[aup->rx_head]; | |
eb049630 | 704 | au1000_update_rx_stats(dev, status); |
5ef3041e | 705 | if (!(status & RX_ERROR)) { |
1da177e4 | 706 | |
5ef3041e FF |
707 | /* good frame */ |
708 | frmlen = (status & RX_FRAME_LEN_MASK); | |
709 | frmlen -= 4; /* Remove FCS */ | |
710 | skb = dev_alloc_skb(frmlen + 2); | |
711 | if (skb == NULL) { | |
5368c726 | 712 | netdev_err(dev, "Memory squeeze, dropping packet.\n"); |
5ef3041e FF |
713 | dev->stats.rx_dropped++; |
714 | continue; | |
715 | } | |
716 | skb_reserve(skb, 2); /* 16 byte IP header align */ | |
717 | skb_copy_to_linear_data(skb, | |
718 | (unsigned char *)pDB->vaddr, frmlen); | |
719 | skb_put(skb, frmlen); | |
720 | skb->protocol = eth_type_trans(skb, dev); | |
721 | netif_rx(skb); /* pass the packet to upper layers */ | |
2cc3c6b1 | 722 | } else { |
5ef3041e FF |
723 | if (au1000_debug > 4) { |
724 | if (status & RX_MISSED_FRAME) | |
725 | printk("rx miss\n"); | |
726 | if (status & RX_WDOG_TIMER) | |
727 | printk("rx wdog\n"); | |
728 | if (status & RX_RUNT) | |
729 | printk("rx runt\n"); | |
730 | if (status & RX_OVERLEN) | |
731 | printk("rx overlen\n"); | |
732 | if (status & RX_COLL) | |
733 | printk("rx coll\n"); | |
734 | if (status & RX_MII_ERROR) | |
735 | printk("rx mii error\n"); | |
736 | if (status & RX_CRC_ERROR) | |
737 | printk("rx crc error\n"); | |
738 | if (status & RX_LEN_ERROR) | |
739 | printk("rx len error\n"); | |
740 | if (status & RX_U_CNTRL_FRAME) | |
741 | printk("rx u control frame\n"); | |
5ef3041e FF |
742 | } |
743 | } | |
744 | prxd->buff_stat = (u32)(pDB->dma_addr | RX_DMA_ENABLE); | |
745 | aup->rx_head = (aup->rx_head + 1) & (NUM_RX_DMA - 1); | |
746 | au_sync(); | |
1da177e4 | 747 | |
5ef3041e FF |
748 | /* next descriptor */ |
749 | prxd = aup->rx_dma_ring[aup->rx_head]; | |
750 | buff_stat = prxd->buff_stat; | |
1da177e4 | 751 | } |
1da177e4 LT |
752 | return 0; |
753 | } | |
754 | ||
eb049630 | 755 | static void au1000_update_tx_stats(struct net_device *dev, u32 status) |
1da177e4 | 756 | { |
454d7c9b | 757 | struct au1000_private *aup = netdev_priv(dev); |
5ef3041e | 758 | struct net_device_stats *ps = &dev->stats; |
0638dec0 | 759 | |
5ef3041e FF |
760 | if (status & TX_FRAME_ABORTED) { |
761 | if (!aup->phy_dev || (DUPLEX_FULL == aup->phy_dev->duplex)) { | |
762 | if (status & (TX_JAB_TIMEOUT | TX_UNDERRUN)) { | |
763 | /* any other tx errors are only valid | |
764 | * in half duplex mode */ | |
765 | ps->tx_errors++; | |
766 | ps->tx_aborted_errors++; | |
767 | } | |
2cc3c6b1 | 768 | } else { |
5ef3041e FF |
769 | ps->tx_errors++; |
770 | ps->tx_aborted_errors++; | |
771 | if (status & (TX_NO_CARRIER | TX_LOSS_CARRIER)) | |
772 | ps->tx_carrier_errors++; | |
773 | } | |
774 | } | |
775 | } | |
0638dec0 | 776 | |
5ef3041e FF |
777 | /* |
778 | * Called from the interrupt service routine to acknowledge | |
779 | * the TX DONE bits. This is a must if the irq is setup as | |
780 | * edge triggered. | |
781 | */ | |
782 | static void au1000_tx_ack(struct net_device *dev) | |
783 | { | |
784 | struct au1000_private *aup = netdev_priv(dev); | |
785 | volatile tx_dma_t *ptxd; | |
0638dec0 | 786 | |
5ef3041e | 787 | ptxd = aup->tx_dma_ring[aup->tx_tail]; |
0638dec0 | 788 | |
5ef3041e | 789 | while (ptxd->buff_stat & TX_T_DONE) { |
eb049630 | 790 | au1000_update_tx_stats(dev, ptxd->status); |
5ef3041e FF |
791 | ptxd->buff_stat &= ~TX_T_DONE; |
792 | ptxd->len = 0; | |
793 | au_sync(); | |
0638dec0 | 794 | |
5ef3041e FF |
795 | aup->tx_tail = (aup->tx_tail + 1) & (NUM_TX_DMA - 1); |
796 | ptxd = aup->tx_dma_ring[aup->tx_tail]; | |
0638dec0 | 797 | |
5ef3041e FF |
798 | if (aup->tx_full) { |
799 | aup->tx_full = 0; | |
800 | netif_wake_queue(dev); | |
801 | } | |
1da177e4 | 802 | } |
5ef3041e | 803 | } |
1da177e4 | 804 | |
5ef3041e FF |
805 | /* |
806 | * Au1000 interrupt service routine. | |
807 | */ | |
808 | static irqreturn_t au1000_interrupt(int irq, void *dev_id) | |
809 | { | |
810 | struct net_device *dev = dev_id; | |
1da177e4 | 811 | |
5ef3041e FF |
812 | /* Handle RX interrupts first to minimize chance of overrun */ |
813 | ||
814 | au1000_rx(dev); | |
815 | au1000_tx_ack(dev); | |
816 | return IRQ_RETVAL(1); | |
1da177e4 LT |
817 | } |
818 | ||
819 | static int au1000_open(struct net_device *dev) | |
820 | { | |
821 | int retval; | |
454d7c9b | 822 | struct au1000_private *aup = netdev_priv(dev); |
1da177e4 | 823 | |
5368c726 | 824 | netif_dbg(aup, drv, dev, "open: dev=%p\n", dev); |
1da177e4 | 825 | |
2cc3c6b1 FF |
826 | retval = request_irq(dev->irq, au1000_interrupt, 0, |
827 | dev->name, dev); | |
828 | if (retval) { | |
5368c726 | 829 | netdev_err(dev, "unable to get IRQ %d\n", dev->irq); |
0638dec0 HVR |
830 | return retval; |
831 | } | |
832 | ||
2cc3c6b1 FF |
833 | retval = au1000_init(dev); |
834 | if (retval) { | |
5368c726 | 835 | netdev_err(dev, "error in au1000_init\n"); |
1da177e4 LT |
836 | free_irq(dev->irq, dev); |
837 | return retval; | |
838 | } | |
1da177e4 | 839 | |
0638dec0 HVR |
840 | if (aup->phy_dev) { |
841 | /* cause the PHY state machine to schedule a link state check */ | |
842 | aup->phy_dev->state = PHY_CHANGELINK; | |
843 | phy_start(aup->phy_dev); | |
1da177e4 LT |
844 | } |
845 | ||
0638dec0 | 846 | netif_start_queue(dev); |
1da177e4 | 847 | |
5368c726 | 848 | netif_dbg(aup, drv, dev, "open: Initialization done.\n"); |
1da177e4 LT |
849 | |
850 | return 0; | |
851 | } | |
852 | ||
853 | static int au1000_close(struct net_device *dev) | |
854 | { | |
0638dec0 | 855 | unsigned long flags; |
454d7c9b | 856 | struct au1000_private *const aup = netdev_priv(dev); |
1da177e4 | 857 | |
5368c726 | 858 | netif_dbg(aup, drv, dev, "close: dev=%p\n", dev); |
1da177e4 | 859 | |
0638dec0 HVR |
860 | if (aup->phy_dev) |
861 | phy_stop(aup->phy_dev); | |
1da177e4 LT |
862 | |
863 | spin_lock_irqsave(&aup->lock, flags); | |
0638dec0 | 864 | |
eb049630 | 865 | au1000_reset_mac_unlocked (dev); |
0638dec0 | 866 | |
1da177e4 LT |
867 | /* stop the device */ |
868 | netif_stop_queue(dev); | |
869 | ||
870 | /* disable the interrupt */ | |
871 | free_irq(dev->irq, dev); | |
872 | spin_unlock_irqrestore(&aup->lock, flags); | |
873 | ||
874 | return 0; | |
875 | } | |
876 | ||
1da177e4 LT |
877 | /* |
878 | * Au1000 transmit routine. | |
879 | */ | |
61357325 | 880 | static netdev_tx_t au1000_tx(struct sk_buff *skb, struct net_device *dev) |
1da177e4 | 881 | { |
454d7c9b | 882 | struct au1000_private *aup = netdev_priv(dev); |
09f75cd7 | 883 | struct net_device_stats *ps = &dev->stats; |
1da177e4 LT |
884 | volatile tx_dma_t *ptxd; |
885 | u32 buff_stat; | |
886 | db_dest_t *pDB; | |
887 | int i; | |
888 | ||
5368c726 FF |
889 | netif_dbg(aup, tx_queued, dev, "tx: aup %x len=%d, data=%p, head %d\n", |
890 | (unsigned)aup, skb->len, | |
1da177e4 LT |
891 | skb->data, aup->tx_head); |
892 | ||
893 | ptxd = aup->tx_dma_ring[aup->tx_head]; | |
894 | buff_stat = ptxd->buff_stat; | |
895 | if (buff_stat & TX_DMA_ENABLE) { | |
896 | /* We've wrapped around and the transmitter is still busy */ | |
897 | netif_stop_queue(dev); | |
898 | aup->tx_full = 1; | |
5b548140 | 899 | return NETDEV_TX_BUSY; |
2cc3c6b1 | 900 | } else if (buff_stat & TX_T_DONE) { |
eb049630 | 901 | au1000_update_tx_stats(dev, ptxd->status); |
1da177e4 LT |
902 | ptxd->len = 0; |
903 | } | |
904 | ||
905 | if (aup->tx_full) { | |
906 | aup->tx_full = 0; | |
907 | netif_wake_queue(dev); | |
908 | } | |
909 | ||
910 | pDB = aup->tx_db_inuse[aup->tx_head]; | |
bd2302c2 | 911 | skb_copy_from_linear_data(skb, (void *)pDB->vaddr, skb->len); |
1da177e4 | 912 | if (skb->len < ETH_ZLEN) { |
2cc3c6b1 | 913 | for (i = skb->len; i < ETH_ZLEN; i++) { |
1da177e4 LT |
914 | ((char *)pDB->vaddr)[i] = 0; |
915 | } | |
916 | ptxd->len = ETH_ZLEN; | |
2cc3c6b1 | 917 | } else |
5ef3041e | 918 | ptxd->len = skb->len; |
1da177e4 | 919 | |
5ef3041e FF |
920 | ps->tx_packets++; |
921 | ps->tx_bytes += ptxd->len; | |
1da177e4 | 922 | |
5ef3041e FF |
923 | ptxd->buff_stat = pDB->dma_addr | TX_DMA_ENABLE; |
924 | au_sync(); | |
925 | dev_kfree_skb(skb); | |
926 | aup->tx_head = (aup->tx_head + 1) & (NUM_TX_DMA - 1); | |
6ed10654 | 927 | return NETDEV_TX_OK; |
1da177e4 LT |
928 | } |
929 | ||
1da177e4 LT |
930 | /* |
931 | * The Tx ring has been full longer than the watchdog timeout | |
932 | * value. The transmitter must be hung? | |
933 | */ | |
934 | static void au1000_tx_timeout(struct net_device *dev) | |
935 | { | |
5368c726 | 936 | netdev_err(dev, "au1000_tx_timeout: dev=%p\n", dev); |
eb049630 | 937 | au1000_reset_mac(dev); |
1da177e4 | 938 | au1000_init(dev); |
1ae5dc34 | 939 | dev->trans_start = jiffies; /* prevent tx timeout */ |
1da177e4 LT |
940 | netif_wake_queue(dev); |
941 | } | |
942 | ||
d9a92cee | 943 | static void au1000_multicast_list(struct net_device *dev) |
1da177e4 | 944 | { |
454d7c9b | 945 | struct au1000_private *aup = netdev_priv(dev); |
1da177e4 | 946 | |
5368c726 | 947 | netif_dbg(aup, drv, dev, "au1000_multicast_list: flags=%x\n", dev->flags); |
1da177e4 LT |
948 | |
949 | if (dev->flags & IFF_PROMISC) { /* Set promiscuous. */ | |
950 | aup->mac->control |= MAC_PROMISCUOUS; | |
1da177e4 | 951 | } else if ((dev->flags & IFF_ALLMULTI) || |
4cd24eaf | 952 | netdev_mc_count(dev) > MULTICAST_FILTER_LIMIT) { |
1da177e4 LT |
953 | aup->mac->control |= MAC_PASS_ALL_MULTI; |
954 | aup->mac->control &= ~MAC_PROMISCUOUS; | |
5368c726 | 955 | netdev_info(dev, "Pass all multicast\n"); |
1da177e4 | 956 | } else { |
22bedad3 | 957 | struct netdev_hw_addr *ha; |
1da177e4 LT |
958 | u32 mc_filter[2]; /* Multicast hash filter */ |
959 | ||
960 | mc_filter[1] = mc_filter[0] = 0; | |
22bedad3 JP |
961 | netdev_for_each_mc_addr(ha, dev) |
962 | set_bit(ether_crc(ETH_ALEN, ha->addr)>>26, | |
1da177e4 | 963 | (long *)mc_filter); |
1da177e4 LT |
964 | aup->mac->multi_hash_high = mc_filter[1]; |
965 | aup->mac->multi_hash_low = mc_filter[0]; | |
966 | aup->mac->control &= ~MAC_PROMISCUOUS; | |
967 | aup->mac->control |= MAC_HASH_MODE; | |
968 | } | |
969 | } | |
970 | ||
1da177e4 LT |
971 | static int au1000_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) |
972 | { | |
454d7c9b | 973 | struct au1000_private *aup = netdev_priv(dev); |
1da177e4 | 974 | |
2cc3c6b1 FF |
975 | if (!netif_running(dev)) |
976 | return -EINVAL; | |
1da177e4 | 977 | |
2cc3c6b1 FF |
978 | if (!aup->phy_dev) |
979 | return -EINVAL; /* PHY not controllable */ | |
1da177e4 | 980 | |
28b04113 | 981 | return phy_mii_ioctl(aup->phy_dev, rq, cmd); |
1da177e4 LT |
982 | } |
983 | ||
d9a92cee AB |
984 | static const struct net_device_ops au1000_netdev_ops = { |
985 | .ndo_open = au1000_open, | |
986 | .ndo_stop = au1000_close, | |
987 | .ndo_start_xmit = au1000_tx, | |
988 | .ndo_set_multicast_list = au1000_multicast_list, | |
989 | .ndo_do_ioctl = au1000_ioctl, | |
990 | .ndo_tx_timeout = au1000_tx_timeout, | |
991 | .ndo_set_mac_address = eth_mac_addr, | |
992 | .ndo_validate_addr = eth_validate_addr, | |
993 | .ndo_change_mtu = eth_change_mtu, | |
994 | }; | |
995 | ||
bd2302c2 | 996 | static int __devinit au1000_probe(struct platform_device *pdev) |
5ef3041e | 997 | { |
2cc3c6b1 | 998 | static unsigned version_printed; |
5ef3041e | 999 | struct au1000_private *aup = NULL; |
bd2302c2 | 1000 | struct au1000_eth_platform_data *pd; |
5ef3041e FF |
1001 | struct net_device *dev = NULL; |
1002 | db_dest_t *pDB, *pDBfree; | |
bd2302c2 FF |
1003 | int irq, i, err = 0; |
1004 | struct resource *base, *macen; | |
5ef3041e | 1005 | char ethaddr[6]; |
5ef3041e | 1006 | |
bd2302c2 FF |
1007 | base = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
1008 | if (!base) { | |
5368c726 | 1009 | dev_err(&pdev->dev, "failed to retrieve base register\n"); |
bd2302c2 FF |
1010 | err = -ENODEV; |
1011 | goto out; | |
1012 | } | |
5ef3041e | 1013 | |
bd2302c2 FF |
1014 | macen = platform_get_resource(pdev, IORESOURCE_MEM, 1); |
1015 | if (!macen) { | |
5368c726 | 1016 | dev_err(&pdev->dev, "failed to retrieve MAC Enable register\n"); |
bd2302c2 FF |
1017 | err = -ENODEV; |
1018 | goto out; | |
1019 | } | |
5ef3041e | 1020 | |
bd2302c2 FF |
1021 | irq = platform_get_irq(pdev, 0); |
1022 | if (irq < 0) { | |
5368c726 | 1023 | dev_err(&pdev->dev, "failed to retrieve IRQ\n"); |
bd2302c2 FF |
1024 | err = -ENODEV; |
1025 | goto out; | |
1026 | } | |
5ef3041e | 1027 | |
bd2302c2 | 1028 | if (!request_mem_region(base->start, resource_size(base), pdev->name)) { |
5368c726 | 1029 | dev_err(&pdev->dev, "failed to request memory region for base registers\n"); |
bd2302c2 FF |
1030 | err = -ENXIO; |
1031 | goto out; | |
1032 | } | |
1033 | ||
1034 | if (!request_mem_region(macen->start, resource_size(macen), pdev->name)) { | |
5368c726 | 1035 | dev_err(&pdev->dev, "failed to request memory region for MAC enable register\n"); |
bd2302c2 FF |
1036 | err = -ENXIO; |
1037 | goto err_request; | |
1038 | } | |
5ef3041e FF |
1039 | |
1040 | dev = alloc_etherdev(sizeof(struct au1000_private)); | |
1041 | if (!dev) { | |
5368c726 | 1042 | dev_err(&pdev->dev, "alloc_etherdev failed\n"); |
bd2302c2 FF |
1043 | err = -ENOMEM; |
1044 | goto err_alloc; | |
5ef3041e FF |
1045 | } |
1046 | ||
bd2302c2 FF |
1047 | SET_NETDEV_DEV(dev, &pdev->dev); |
1048 | platform_set_drvdata(pdev, dev); | |
5ef3041e FF |
1049 | aup = netdev_priv(dev); |
1050 | ||
1051 | spin_lock_init(&aup->lock); | |
7cd2e6e3 | 1052 | aup->msg_enable = (au1000_debug < 4 ? AU1000_DEF_MSG_ENABLE : au1000_debug); |
5ef3041e FF |
1053 | |
1054 | /* Allocate the data buffers */ | |
1055 | /* Snooping works fine with eth on all au1xxx */ | |
1056 | aup->vaddr = (u32)dma_alloc_noncoherent(NULL, MAX_BUF_SIZE * | |
1057 | (NUM_TX_BUFFS + NUM_RX_BUFFS), | |
1058 | &aup->dma_addr, 0); | |
1059 | if (!aup->vaddr) { | |
5368c726 | 1060 | dev_err(&pdev->dev, "failed to allocate data buffers\n"); |
bd2302c2 FF |
1061 | err = -ENOMEM; |
1062 | goto err_vaddr; | |
5ef3041e FF |
1063 | } |
1064 | ||
1065 | /* aup->mac is the base address of the MAC's registers */ | |
bd2302c2 FF |
1066 | aup->mac = (volatile mac_reg_t *)ioremap_nocache(base->start, resource_size(base)); |
1067 | if (!aup->mac) { | |
5368c726 | 1068 | dev_err(&pdev->dev, "failed to ioremap MAC registers\n"); |
bd2302c2 FF |
1069 | err = -ENXIO; |
1070 | goto err_remap1; | |
1071 | } | |
5ef3041e | 1072 | |
bd2302c2 FF |
1073 | /* Setup some variables for quick register address access */ |
1074 | aup->enable = (volatile u32 *)ioremap_nocache(macen->start, resource_size(macen)); | |
1075 | if (!aup->enable) { | |
5368c726 | 1076 | dev_err(&pdev->dev, "failed to ioremap MAC enable register\n"); |
bd2302c2 FF |
1077 | err = -ENXIO; |
1078 | goto err_remap2; | |
1079 | } | |
1080 | aup->mac_id = pdev->id; | |
5ef3041e | 1081 | |
bd2302c2 | 1082 | if (pdev->id == 0) { |
5ef3041e FF |
1083 | if (prom_get_ethernet_addr(ethaddr) == 0) |
1084 | memcpy(au1000_mac_addr, ethaddr, sizeof(au1000_mac_addr)); | |
1085 | else { | |
5368c726 | 1086 | netdev_info(dev, "No MAC address found\n"); |
5ef3041e FF |
1087 | /* Use the hard coded MAC addresses */ |
1088 | } | |
1089 | ||
eb049630 | 1090 | au1000_setup_hw_rings(aup, MAC0_RX_DMA_ADDR, MAC0_TX_DMA_ADDR); |
bd2302c2 | 1091 | } else if (pdev->id == 1) |
eb049630 | 1092 | au1000_setup_hw_rings(aup, MAC1_RX_DMA_ADDR, MAC1_TX_DMA_ADDR); |
5ef3041e FF |
1093 | |
1094 | /* | |
1095 | * Assign to the Ethernet ports two consecutive MAC addresses | |
1096 | * to match those that are printed on their stickers | |
1097 | */ | |
1098 | memcpy(dev->dev_addr, au1000_mac_addr, sizeof(au1000_mac_addr)); | |
bd2302c2 | 1099 | dev->dev_addr[5] += pdev->id; |
5ef3041e FF |
1100 | |
1101 | *aup->enable = 0; | |
1102 | aup->mac_enabled = 0; | |
1103 | ||
bd2302c2 FF |
1104 | pd = pdev->dev.platform_data; |
1105 | if (!pd) { | |
5368c726 | 1106 | dev_info(&pdev->dev, "no platform_data passed, PHY search on MAC0\n"); |
bd2302c2 FF |
1107 | aup->phy1_search_mac0 = 1; |
1108 | } else { | |
1109 | aup->phy_static_config = pd->phy_static_config; | |
1110 | aup->phy_search_highest_addr = pd->phy_search_highest_addr; | |
1111 | aup->phy1_search_mac0 = pd->phy1_search_mac0; | |
1112 | aup->phy_addr = pd->phy_addr; | |
1113 | aup->phy_busid = pd->phy_busid; | |
1114 | aup->phy_irq = pd->phy_irq; | |
1115 | } | |
1116 | ||
1117 | if (aup->phy_busid && aup->phy_busid > 0) { | |
5368c726 | 1118 | dev_err(&pdev->dev, "MAC0-associated PHY attached 2nd MACs MII" |
bd2302c2 FF |
1119 | "bus not supported yet\n"); |
1120 | err = -ENODEV; | |
1121 | goto err_mdiobus_alloc; | |
1122 | } | |
1123 | ||
5ef3041e | 1124 | aup->mii_bus = mdiobus_alloc(); |
bd2302c2 | 1125 | if (aup->mii_bus == NULL) { |
5368c726 | 1126 | dev_err(&pdev->dev, "failed to allocate mdiobus structure\n"); |
bd2302c2 FF |
1127 | err = -ENOMEM; |
1128 | goto err_mdiobus_alloc; | |
1129 | } | |
5ef3041e FF |
1130 | |
1131 | aup->mii_bus->priv = dev; | |
1132 | aup->mii_bus->read = au1000_mdiobus_read; | |
1133 | aup->mii_bus->write = au1000_mdiobus_write; | |
1134 | aup->mii_bus->reset = au1000_mdiobus_reset; | |
1135 | aup->mii_bus->name = "au1000_eth_mii"; | |
1136 | snprintf(aup->mii_bus->id, MII_BUS_ID_SIZE, "%x", aup->mac_id); | |
1137 | aup->mii_bus->irq = kmalloc(sizeof(int)*PHY_MAX_ADDR, GFP_KERNEL); | |
dcbfef82 | 1138 | if (aup->mii_bus->irq == NULL) |
1139 | goto err_out; | |
1140 | ||
2cc3c6b1 | 1141 | for (i = 0; i < PHY_MAX_ADDR; ++i) |
5ef3041e | 1142 | aup->mii_bus->irq[i] = PHY_POLL; |
5ef3041e | 1143 | /* if known, set corresponding PHY IRQs */ |
bd2302c2 FF |
1144 | if (aup->phy_static_config) |
1145 | if (aup->phy_irq && aup->phy_busid == aup->mac_id) | |
1146 | aup->mii_bus->irq[aup->phy_addr] = aup->phy_irq; | |
1147 | ||
1148 | err = mdiobus_register(aup->mii_bus); | |
1149 | if (err) { | |
5368c726 | 1150 | dev_err(&pdev->dev, "failed to register MDIO bus\n"); |
bd2302c2 FF |
1151 | goto err_mdiobus_reg; |
1152 | } | |
5ef3041e | 1153 | |
eb049630 | 1154 | if (au1000_mii_probe(dev) != 0) |
5ef3041e | 1155 | goto err_out; |
5ef3041e FF |
1156 | |
1157 | pDBfree = NULL; | |
1158 | /* setup the data buffer descriptors and attach a buffer to each one */ | |
1159 | pDB = aup->db; | |
1160 | for (i = 0; i < (NUM_TX_BUFFS+NUM_RX_BUFFS); i++) { | |
1161 | pDB->pnext = pDBfree; | |
1162 | pDBfree = pDB; | |
1163 | pDB->vaddr = (u32 *)((unsigned)aup->vaddr + MAX_BUF_SIZE*i); | |
1164 | pDB->dma_addr = (dma_addr_t)virt_to_bus(pDB->vaddr); | |
1165 | pDB++; | |
1166 | } | |
1167 | aup->pDBfree = pDBfree; | |
1168 | ||
1169 | for (i = 0; i < NUM_RX_DMA; i++) { | |
eb049630 | 1170 | pDB = au1000_GetFreeDB(aup); |
5ef3041e FF |
1171 | if (!pDB) { |
1172 | goto err_out; | |
1173 | } | |
1174 | aup->rx_dma_ring[i]->buff_stat = (unsigned)pDB->dma_addr; | |
1175 | aup->rx_db_inuse[i] = pDB; | |
1176 | } | |
1177 | for (i = 0; i < NUM_TX_DMA; i++) { | |
eb049630 | 1178 | pDB = au1000_GetFreeDB(aup); |
5ef3041e FF |
1179 | if (!pDB) { |
1180 | goto err_out; | |
1181 | } | |
1182 | aup->tx_dma_ring[i]->buff_stat = (unsigned)pDB->dma_addr; | |
1183 | aup->tx_dma_ring[i]->len = 0; | |
1184 | aup->tx_db_inuse[i] = pDB; | |
1185 | } | |
1186 | ||
bd2302c2 FF |
1187 | dev->base_addr = base->start; |
1188 | dev->irq = irq; | |
1189 | dev->netdev_ops = &au1000_netdev_ops; | |
1190 | SET_ETHTOOL_OPS(dev, &au1000_ethtool_ops); | |
1191 | dev->watchdog_timeo = ETH_TX_TIMEOUT; | |
1192 | ||
5ef3041e FF |
1193 | /* |
1194 | * The boot code uses the ethernet controller, so reset it to start | |
1195 | * fresh. au1000_init() expects that the device is in reset state. | |
1196 | */ | |
eb049630 | 1197 | au1000_reset_mac(dev); |
5ef3041e | 1198 | |
bd2302c2 FF |
1199 | err = register_netdev(dev); |
1200 | if (err) { | |
5368c726 | 1201 | netdev_err(dev, "Cannot register net device, aborting.\n"); |
bd2302c2 FF |
1202 | goto err_out; |
1203 | } | |
1204 | ||
5368c726 FF |
1205 | netdev_info(dev, "Au1xx0 Ethernet found at 0x%lx, irq %d\n", |
1206 | (unsigned long)base->start, irq); | |
bd2302c2 FF |
1207 | if (version_printed++ == 0) |
1208 | printk("%s version %s %s\n", DRV_NAME, DRV_VERSION, DRV_AUTHOR); | |
1209 | ||
1210 | return 0; | |
5ef3041e FF |
1211 | |
1212 | err_out: | |
bd2302c2 | 1213 | if (aup->mii_bus != NULL) |
5ef3041e | 1214 | mdiobus_unregister(aup->mii_bus); |
5ef3041e FF |
1215 | |
1216 | /* here we should have a valid dev plus aup-> register addresses | |
1217 | * so we can reset the mac properly.*/ | |
eb049630 | 1218 | au1000_reset_mac(dev); |
5ef3041e FF |
1219 | |
1220 | for (i = 0; i < NUM_RX_DMA; i++) { | |
1221 | if (aup->rx_db_inuse[i]) | |
eb049630 | 1222 | au1000_ReleaseDB(aup, aup->rx_db_inuse[i]); |
5ef3041e FF |
1223 | } |
1224 | for (i = 0; i < NUM_TX_DMA; i++) { | |
1225 | if (aup->tx_db_inuse[i]) | |
eb049630 | 1226 | au1000_ReleaseDB(aup, aup->tx_db_inuse[i]); |
5ef3041e | 1227 | } |
bd2302c2 FF |
1228 | err_mdiobus_reg: |
1229 | mdiobus_free(aup->mii_bus); | |
1230 | err_mdiobus_alloc: | |
1231 | iounmap(aup->enable); | |
1232 | err_remap2: | |
1233 | iounmap(aup->mac); | |
1234 | err_remap1: | |
5ef3041e FF |
1235 | dma_free_noncoherent(NULL, MAX_BUF_SIZE * (NUM_TX_BUFFS + NUM_RX_BUFFS), |
1236 | (void *)aup->vaddr, aup->dma_addr); | |
bd2302c2 | 1237 | err_vaddr: |
5ef3041e | 1238 | free_netdev(dev); |
bd2302c2 FF |
1239 | err_alloc: |
1240 | release_mem_region(macen->start, resource_size(macen)); | |
1241 | err_request: | |
1242 | release_mem_region(base->start, resource_size(base)); | |
1243 | out: | |
1244 | return err; | |
5ef3041e FF |
1245 | } |
1246 | ||
bd2302c2 | 1247 | static int __devexit au1000_remove(struct platform_device *pdev) |
5ef3041e | 1248 | { |
bd2302c2 FF |
1249 | struct net_device *dev = platform_get_drvdata(pdev); |
1250 | struct au1000_private *aup = netdev_priv(dev); | |
1251 | int i; | |
1252 | struct resource *base, *macen; | |
5ef3041e | 1253 | |
bd2302c2 FF |
1254 | platform_set_drvdata(pdev, NULL); |
1255 | ||
1256 | unregister_netdev(dev); | |
1257 | mdiobus_unregister(aup->mii_bus); | |
1258 | mdiobus_free(aup->mii_bus); | |
1259 | ||
1260 | for (i = 0; i < NUM_RX_DMA; i++) | |
1261 | if (aup->rx_db_inuse[i]) | |
eb049630 | 1262 | au1000_ReleaseDB(aup, aup->rx_db_inuse[i]); |
bd2302c2 FF |
1263 | |
1264 | for (i = 0; i < NUM_TX_DMA; i++) | |
1265 | if (aup->tx_db_inuse[i]) | |
eb049630 | 1266 | au1000_ReleaseDB(aup, aup->tx_db_inuse[i]); |
bd2302c2 FF |
1267 | |
1268 | dma_free_noncoherent(NULL, MAX_BUF_SIZE * | |
1269 | (NUM_TX_BUFFS + NUM_RX_BUFFS), | |
1270 | (void *)aup->vaddr, aup->dma_addr); | |
1271 | ||
1272 | iounmap(aup->mac); | |
1273 | iounmap(aup->enable); | |
1274 | ||
1275 | base = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1276 | release_mem_region(base->start, resource_size(base)); | |
1277 | ||
1278 | macen = platform_get_resource(pdev, IORESOURCE_MEM, 1); | |
1279 | release_mem_region(macen->start, resource_size(macen)); | |
1280 | ||
1281 | free_netdev(dev); | |
5ef3041e | 1282 | |
5ef3041e FF |
1283 | return 0; |
1284 | } | |
1285 | ||
bd2302c2 FF |
1286 | static struct platform_driver au1000_eth_driver = { |
1287 | .probe = au1000_probe, | |
1288 | .remove = __devexit_p(au1000_remove), | |
1289 | .driver = { | |
1290 | .name = "au1000-eth", | |
1291 | .owner = THIS_MODULE, | |
1292 | }, | |
1293 | }; | |
1294 | MODULE_ALIAS("platform:au1000-eth"); | |
1295 | ||
1296 | ||
1297 | static int __init au1000_init_module(void) | |
1298 | { | |
1299 | return platform_driver_register(&au1000_eth_driver); | |
1300 | } | |
1301 | ||
1302 | static void __exit au1000_exit_module(void) | |
5ef3041e | 1303 | { |
bd2302c2 | 1304 | platform_driver_unregister(&au1000_eth_driver); |
5ef3041e FF |
1305 | } |
1306 | ||
1da177e4 | 1307 | module_init(au1000_init_module); |
bd2302c2 | 1308 | module_exit(au1000_exit_module); |