projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
[PATCH] PHY: Add support for configuring the PHY connection interface
[deliverable/linux.git] / drivers / net / au1000_eth.c
CommitLineData
1da177e4
LT		 1/*
2 *
3 * Alchemy Au1x00 ethernet driver
4 *
89be0501 5 * Copyright 2001-2003, 2006 MontaVista Software Inc.
1da177e4
LT		 6 * Copyright 2002 TimeSys Corp.
7 * Added ethtool/mii-tool support,
8 * Copyright 2004 Matt Porter <mporter@kernel.crashing.org>
6aa20a22
JG		 9 * Update: 2004 Bjoern Riemer, riemer@fokus.fraunhofer.de
10 * or riemer@riemer-nt.de: fixed the link beat detection with
1da177e4 11 * ioctls (SIOCGMIIPHY)
0638dec0
HVR		 12 * Copyright 2006 Herbert Valerio Riedel <hvr@gnu.org>
13 * converted to use linux-2.6.x's PHY framework
14 *
1da177e4
LT		 15 * Author: MontaVista Software, Inc.
16 * ppopov@mvista.com or source@mvista.com
17 *
18 * ########################################################################
19 *
20 * This program is free software; you can distribute it and/or modify it
21 * under the terms of the GNU General Public License (Version 2) as
22 * published by the Free Software Foundation.
23 *
24 * This program is distributed in the hope it will be useful, but WITHOUT
25 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
26 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
27 * for more details.
28 *
29 * You should have received a copy of the GNU General Public License along
30 * with this program; if not, write to the Free Software Foundation, Inc.,
31 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
32 *
33 * ########################################################################
34 *
6aa20a22 35 *
1da177e4
LT		 36 */
37
38#include <linux/module.h>
39#include <linux/kernel.h>
40#include <linux/sched.h>
41#include <linux/string.h>
42#include <linux/timer.h>
43#include <linux/errno.h>
44#include <linux/in.h>
45#include <linux/ioport.h>
46#include <linux/bitops.h>
47#include <linux/slab.h>
48#include <linux/interrupt.h>
49#include <linux/pci.h>
50#include <linux/init.h>
51#include <linux/netdevice.h>
52#include <linux/etherdevice.h>
53#include <linux/ethtool.h>
54#include <linux/mii.h>
55#include <linux/skbuff.h>
56#include <linux/delay.h>
8cd35da0 57#include <linux/crc32.h>
0638dec0 58#include <linux/phy.h>
1da177e4
LT		 59#include <asm/mipsregs.h>
60#include <asm/irq.h>
61#include <asm/io.h>
62#include <asm/processor.h>
63
64#include <asm/mach-au1x00/au1000.h>
65#include <asm/cpu.h>
66#include "au1000_eth.h"
67
68#ifdef AU1000_ETH_DEBUG
69static int au1000_debug = 5;
70#else
71static int au1000_debug = 3;
72#endif
73
89be0501 74#define DRV_NAME "au1000_eth"
d5b20697 75#define DRV_VERSION "1.6"
1da177e4
LT		 76#define DRV_AUTHOR "Pete Popov <ppopov@embeddedalley.com>"
77#define DRV_DESC "Au1xxx on-chip Ethernet driver"
78
79MODULE_AUTHOR(DRV_AUTHOR);
80MODULE_DESCRIPTION(DRV_DESC);
81MODULE_LICENSE("GPL");
82
83// prototypes
84static void hard_stop(struct net_device *);
85static void enable_rx_tx(struct net_device *dev);
89be0501 86static struct net_device * au1000_probe(int port_num);
1da177e4
LT		 87static int au1000_init(struct net_device *);
88static int au1000_open(struct net_device *);
89static int au1000_close(struct net_device *);
90static int au1000_tx(struct sk_buff *, struct net_device *);
91static int au1000_rx(struct net_device *);
7d12e780 92static irqreturn_t au1000_interrupt(int, void *);
1da177e4 93static void au1000_tx_timeout(struct net_device *);
1da177e4
LT		 94static void set_rx_mode(struct net_device *);
95static struct net_device_stats *au1000_get_stats(struct net_device *);
1da177e4
LT		 96static int au1000_ioctl(struct net_device *, struct ifreq *, int);
97static int mdio_read(struct net_device *, int, int);
98static void mdio_write(struct net_device *, int, int, u16);
0638dec0
HVR		 99static void au1000_adjust_link(struct net_device *);
100static void enable_mac(struct net_device *, int);
1da177e4
LT		 101
102// externs
1da177e4
LT		 103extern int get_ethernet_addr(char *ethernet_addr);
104extern void str2eaddr(unsigned char *ea, unsigned char *str);
c21e6d65 105extern char * prom_getcmdline(void);
1da177e4
LT		 106
107/*
108 * Theory of operation
109 *
6aa20a22
JG		 110 * The Au1000 MACs use a simple rx and tx descriptor ring scheme.
111 * There are four receive and four transmit descriptors. These
112 * descriptors are not in memory; rather, they are just a set of
1da177e4
LT		 113 * hardware registers.
114 *
115 * Since the Au1000 has a coherent data cache, the receive and
6aa20a22 116 * transmit buffers are allocated from the KSEG0 segment. The
1da177e4
LT		 117 * hardware registers, however, are still mapped at KSEG1 to
118 * make sure there's no out-of-order writes, and that all writes
119 * complete immediately.
120 */
121
122/* These addresses are only used if yamon doesn't tell us what
123 * the mac address is, and the mac address is not passed on the
124 * command line.
125 */
6aa20a22 126static unsigned char au1000_mac_addr[6] __devinitdata = {
1da177e4
LT		 127 0x00, 0x50, 0xc2, 0x0c, 0x30, 0x00
128};
129
1da177e4
LT		 130struct au1000_private *au_macs[NUM_ETH_INTERFACES];
131
0638dec0
HVR		 132/*
133 * board-specific configurations
134 *
135 * PHY detection algorithm
136 *
137 * If AU1XXX_PHY_STATIC_CONFIG is undefined, the PHY setup is
138 * autodetected:
139 *
140 * mii_probe() first searches the current MAC's MII bus for a PHY,
141 * selecting the first (or last, if AU1XXX_PHY_SEARCH_HIGHEST_ADDR is
142 * defined) PHY address not already claimed by another netdev.
143 *
144 * If nothing was found that way when searching for the 2nd ethernet
145 * controller's PHY and AU1XXX_PHY1_SEARCH_ON_MAC0 is defined, then
146 * the first MII bus is searched as well for an unclaimed PHY; this is
147 * needed in case of a dual-PHY accessible only through the MAC0's MII
148 * bus.
149 *
150 * Finally, if no PHY is found, then the corresponding ethernet
151 * controller is not registered to the network subsystem.
1da177e4
LT		 152 */
153
0638dec0
HVR		 154/* autodetection defaults */
155#undef AU1XXX_PHY_SEARCH_HIGHEST_ADDR
156#define AU1XXX_PHY1_SEARCH_ON_MAC0
1da177e4 157
0638dec0
HVR		 158/* static PHY setup
159 *
160 * most boards PHY setup should be detectable properly with the
161 * autodetection algorithm in mii_probe(), but in some cases (e.g. if
162 * you have a switch attached, or want to use the PHY's interrupt
163 * notification capabilities) you can provide a static PHY
164 * configuration here
165 *
166 * IRQs may only be set, if a PHY address was configured
167 * If a PHY address is given, also a bus id is required to be set
168 *
169 * ps: make sure the used irqs are configured properly in the board
170 * specific irq-map
171 */
1da177e4 172
0638dec0
HVR		 173#if defined(CONFIG_MIPS_BOSPORUS)
174/*
175 * Micrel/Kendin 5 port switch attached to MAC0,
176 * MAC0 is associated with PHY address 5 (== WAN port)
177 * MAC1 is not associated with any PHY, since it's connected directly
178 * to the switch.
179 * no interrupts are used
180 */
181# define AU1XXX_PHY_STATIC_CONFIG
1da177e4 182
0638dec0
HVR		 183# define AU1XXX_PHY0_ADDR 5
184# define AU1XXX_PHY0_BUSID 0
185# undef AU1XXX_PHY0_IRQ
1da177e4 186
0638dec0
HVR		 187# undef AU1XXX_PHY1_ADDR
188# undef AU1XXX_PHY1_BUSID
189# undef AU1XXX_PHY1_IRQ
1da177e4
LT		 190#endif
191
0638dec0
HVR		 192#if defined(AU1XXX_PHY0_BUSID) && (AU1XXX_PHY0_BUSID > 0)
193# error MAC0-associated PHY attached 2nd MACs MII bus not supported yet
1da177e4 194#endif
1da177e4 195
0638dec0
HVR		 196/*
197 * MII operations
198 */
199static int mdio_read(struct net_device *dev, int phy_addr, int reg)
1da177e4
LT		 200{
201 struct au1000_private *aup = (struct au1000_private *) dev->priv;
0638dec0
HVR		 202 volatile u32 *const mii_control_reg = &aup->mac->mii_control;
203 volatile u32 *const mii_data_reg = &aup->mac->mii_data;
1da177e4
LT		 204 u32 timedout = 20;
205 u32 mii_control;
206
1da177e4
LT		 207 while (*mii_control_reg & MAC_MII_BUSY) {
208 mdelay(1);
209 if (--timedout == 0) {
6aa20a22 210 printk(KERN_ERR "%s: read_MII busy timeout!!\n",
1da177e4
LT		 211 dev->name);
212 return -1;
213 }
214 }
215
6aa20a22 216 mii_control = MAC_SET_MII_SELECT_REG(reg) |
0638dec0 217 MAC_SET_MII_SELECT_PHY(phy_addr) | MAC_MII_READ;
1da177e4
LT		 218
219 *mii_control_reg = mii_control;
220
221 timedout = 20;
222 while (*mii_control_reg & MAC_MII_BUSY) {
223 mdelay(1);
224 if (--timedout == 0) {
6aa20a22 225 printk(KERN_ERR "%s: mdio_read busy timeout!!\n",
1da177e4
LT		 226 dev->name);
227 return -1;
228 }
229 }
230 return (int)*mii_data_reg;
231}
232
0638dec0 233static void mdio_write(struct net_device *dev, int phy_addr, int reg, u16 value)
1da177e4
LT		 234{
235 struct au1000_private *aup = (struct au1000_private *) dev->priv;
0638dec0
HVR		 236 volatile u32 *const mii_control_reg = &aup->mac->mii_control;
237 volatile u32 *const mii_data_reg = &aup->mac->mii_data;
1da177e4
LT		 238 u32 timedout = 20;
239 u32 mii_control;
240
1da177e4
LT		 241 while (*mii_control_reg & MAC_MII_BUSY) {
242 mdelay(1);
243 if (--timedout == 0) {
6aa20a22 244 printk(KERN_ERR "%s: mdio_write busy timeout!!\n",
1da177e4
LT		 245 dev->name);
246 return;
247 }
248 }
249
6aa20a22 250 mii_control = MAC_SET_MII_SELECT_REG(reg) |
0638dec0 251 MAC_SET_MII_SELECT_PHY(phy_addr) | MAC_MII_WRITE;
1da177e4
LT		 252
253 *mii_data_reg = value;
254 *mii_control_reg = mii_control;
255}
256
0638dec0
HVR		 257static int mdiobus_read(struct mii_bus *bus, int phy_addr, int regnum)
258{
259 /* WARNING: bus->phy_map[phy_addr].attached_dev == dev does
260 * _NOT_ hold (e.g. when PHY is accessed through other MAC's MII bus) */
261 struct net_device *const dev = bus->priv;
262
263 enable_mac(dev, 0); /* make sure the MAC associated with this
264 * mii_bus is enabled */
265 return mdio_read(dev, phy_addr, regnum);
266}
1da177e4 267
0638dec0
HVR		 268static int mdiobus_write(struct mii_bus *bus, int phy_addr, int regnum,
269 u16 value)
1da177e4 270{
0638dec0 271 struct net_device *const dev = bus->priv;
1da177e4 272
0638dec0
HVR		 273 enable_mac(dev, 0); /* make sure the MAC associated with this
274 * mii_bus is enabled */
275 mdio_write(dev, phy_addr, regnum, value);
276 return 0;
1da177e4
LT		 277}
278
0638dec0 279static int mdiobus_reset(struct mii_bus *bus)
1da177e4 280{
0638dec0 281 struct net_device *const dev = bus->priv;
1da177e4 282
0638dec0
HVR		 283 enable_mac(dev, 0); /* make sure the MAC associated with this
284 * mii_bus is enabled */
285 return 0;
286}
1da177e4 287
0638dec0
HVR		 288static int mii_probe (struct net_device *dev)
289{
290 struct au1000_private *const aup = (struct au1000_private *) dev->priv;
291 struct phy_device *phydev = NULL;
292
293#if defined(AU1XXX_PHY_STATIC_CONFIG)
294 BUG_ON(aup->mac_id < 0 || aup->mac_id > 1);
295
296 if(aup->mac_id == 0) { /* get PHY0 */
297# if defined(AU1XXX_PHY0_ADDR)
298 phydev = au_macs[AU1XXX_PHY0_BUSID]->mii_bus.phy_map[AU1XXX_PHY0_ADDR];
299# else
300 printk (KERN_INFO DRV_NAME ":%s: using PHY-less setup\n",
301 dev->name);
302 return 0;
303# endif /* defined(AU1XXX_PHY0_ADDR) */
304 } else if (aup->mac_id == 1) { /* get PHY1 */
305# if defined(AU1XXX_PHY1_ADDR)
306 phydev = au_macs[AU1XXX_PHY1_BUSID]->mii_bus.phy_map[AU1XXX_PHY1_ADDR];
307# else
308 printk (KERN_INFO DRV_NAME ":%s: using PHY-less setup\n",
309 dev->name);
310 return 0;
311# endif /* defined(AU1XXX_PHY1_ADDR) */
312 }
313
314#else /* defined(AU1XXX_PHY_STATIC_CONFIG) */
315 int phy_addr;
316
317 /* find the first (lowest address) PHY on the current MAC's MII bus */
318 for (phy_addr = 0; phy_addr < PHY_MAX_ADDR; phy_addr++)
319 if (aup->mii_bus.phy_map[phy_addr]) {
320 phydev = aup->mii_bus.phy_map[phy_addr];
321# if !defined(AU1XXX_PHY_SEARCH_HIGHEST_ADDR)
322 break; /* break out with first one found */
323# endif
1da177e4 324 }
1da177e4 325
0638dec0
HVR		 326# if defined(AU1XXX_PHY1_SEARCH_ON_MAC0)
327 /* try harder to find a PHY */
328 if (!phydev && (aup->mac_id == 1)) {
329 /* no PHY found, maybe we have a dual PHY? */
330 printk (KERN_INFO DRV_NAME ": no PHY found on MAC1, "
331 "let's see if it's attached to MAC0...\n");
332
333 BUG_ON(!au_macs[0]);
334
335 /* find the first (lowest address) non-attached PHY on
336 * the MAC0 MII bus */
337 for (phy_addr = 0; phy_addr < PHY_MAX_ADDR; phy_addr++) {
338 struct phy_device *const tmp_phydev =
339 au_macs[0]->mii_bus.phy_map[phy_addr];
340
341 if (!tmp_phydev)
342 continue; /* no PHY here... */
343
344 if (tmp_phydev->attached_dev)
345 continue; /* already claimed by MAC0 */
346
347 phydev = tmp_phydev;
348 break; /* found it */
1da177e4
LT		 349 }
350 }
0638dec0 351# endif /* defined(AU1XXX_PHY1_SEARCH_OTHER_BUS) */
1da177e4 352
0638dec0
HVR		 353#endif /* defined(AU1XXX_PHY_STATIC_CONFIG) */
354 if (!phydev) {
355 printk (KERN_ERR DRV_NAME ":%s: no PHY found\n", dev->name);
1da177e4
LT		 356 return -1;
357 }
358
0638dec0
HVR		 359 /* now we are supposed to have a proper phydev, to attach to... */
360 BUG_ON(!phydev);
361 BUG_ON(phydev->attached_dev);
362
e8a2b6a4
AF		 363 phydev = phy_connect(dev, phydev->dev.bus_id, &au1000_adjust_link, 0,
364 PHY_INTERFACE_MODE_MII);
0638dec0
HVR		 365
366 if (IS_ERR(phydev)) {
367 printk(KERN_ERR "%s: Could not attach to PHY\n", dev->name);
368 return PTR_ERR(phydev);
369 }
370
371 /* mask with MAC supported features */
372 phydev->supported &= (SUPPORTED_10baseT_Half
373 | SUPPORTED_10baseT_Full
374 | SUPPORTED_100baseT_Half
375 | SUPPORTED_100baseT_Full
376 | SUPPORTED_Autoneg
377 /* | SUPPORTED_Pause | SUPPORTED_Asym_Pause */
378 | SUPPORTED_MII
379 | SUPPORTED_TP);
380
381 phydev->advertising = phydev->supported;
382
383 aup->old_link = 0;
384 aup->old_speed = 0;
385 aup->old_duplex = -1;
386 aup->phy_dev = phydev;
387
388 printk(KERN_INFO "%s: attached PHY driver [%s] "
389 "(mii_bus:phy_addr=%s, irq=%d)\n",
390 dev->name, phydev->drv->name, phydev->dev.bus_id, phydev->irq);
1da177e4
LT		 391
392 return 0;
393}
394
395
396/*
397 * Buffer allocation/deallocation routines. The buffer descriptor returned
6aa20a22 398 * has the virtual and dma address of a buffer suitable for
1da177e4
LT		 399 * both, receive and transmit operations.
400 */
401static db_dest_t *GetFreeDB(struct au1000_private *aup)
402{
403 db_dest_t *pDB;
404 pDB = aup->pDBfree;
405
406 if (pDB) {
407 aup->pDBfree = pDB->pnext;
408 }
409 return pDB;
410}
411
412void ReleaseDB(struct au1000_private *aup, db_dest_t *pDB)
413{
414 db_dest_t *pDBfree = aup->pDBfree;
415 if (pDBfree)
416 pDBfree->pnext = pDB;
417 aup->pDBfree = pDB;
418}
419
420static void enable_rx_tx(struct net_device *dev)
421{
422 struct au1000_private *aup = (struct au1000_private *) dev->priv;
423
424 if (au1000_debug > 4)
425 printk(KERN_INFO "%s: enable_rx_tx\n", dev->name);
426
427 aup->mac->control |= (MAC_RX_ENABLE | MAC_TX_ENABLE);
428 au_sync_delay(10);
429}
430
431static void hard_stop(struct net_device *dev)
432{
433 struct au1000_private *aup = (struct au1000_private *) dev->priv;
434
435 if (au1000_debug > 4)
436 printk(KERN_INFO "%s: hard stop\n", dev->name);
437
438 aup->mac->control &= ~(MAC_RX_ENABLE | MAC_TX_ENABLE);
439 au_sync_delay(10);
440}
441
0638dec0 442static void enable_mac(struct net_device *dev, int force_reset)
1da177e4 443{
0638dec0 444 unsigned long flags;
1da177e4
LT		 445 struct au1000_private *aup = (struct au1000_private *) dev->priv;
446
1da177e4 447 spin_lock_irqsave(&aup->lock, flags);
1da177e4 448
0638dec0 449 if(force_reset || (!aup->mac_enabled)) {
1da177e4
LT		 450 *aup->enable = MAC_EN_CLOCK_ENABLE;
451 au_sync_delay(2);
0638dec0
HVR		 452 *aup->enable = (MAC_EN_RESET0 | MAC_EN_RESET1 | MAC_EN_RESET2
453 | MAC_EN_CLOCK_ENABLE);
1da177e4 454 au_sync_delay(2);
0638dec0
HVR		 455
456 aup->mac_enabled = 1;
1da177e4 457 }
0638dec0
HVR		 458
459 spin_unlock_irqrestore(&aup->lock, flags);
460}
461
462static void reset_mac_unlocked(struct net_device *dev)
463{
464 struct au1000_private *const aup = (struct au1000_private *) dev->priv;
465 int i;
466
467 hard_stop(dev);
468
469 *aup->enable = MAC_EN_CLOCK_ENABLE;
470 au_sync_delay(2);
471 *aup->enable = 0;
472 au_sync_delay(2);
473
1da177e4
LT		 474 aup->tx_full = 0;
475 for (i = 0; i < NUM_RX_DMA; i++) {
476 /* reset control bits */
477 aup->rx_dma_ring[i]->buff_stat &= ~0xf;
478 }
479 for (i = 0; i < NUM_TX_DMA; i++) {
480 /* reset control bits */
481 aup->tx_dma_ring[i]->buff_stat &= ~0xf;
482 }
0638dec0
HVR		 483
484 aup->mac_enabled = 0;
485
1da177e4
LT		 486}
487
0638dec0
HVR		 488static void reset_mac(struct net_device *dev)
489{
490 struct au1000_private *const aup = (struct au1000_private *) dev->priv;
491 unsigned long flags;
492
493 if (au1000_debug > 4)
494 printk(KERN_INFO "%s: reset mac, aup %x\n",
495 dev->name, (unsigned)aup);
496
497 spin_lock_irqsave(&aup->lock, flags);
498
499 reset_mac_unlocked (dev);
500
501 spin_unlock_irqrestore(&aup->lock, flags);
502}
1da177e4 503
6aa20a22 504/*
1da177e4
LT		 505 * Setup the receive and transmit "rings". These pointers are the addresses
506 * of the rx and tx MAC DMA registers so they are fixed by the hardware --
507 * these are not descriptors sitting in memory.
508 */
6aa20a22 509static void
1da177e4
LT		 510setup_hw_rings(struct au1000_private *aup, u32 rx_base, u32 tx_base)
511{
512 int i;
513
514 for (i = 0; i < NUM_RX_DMA; i++) {
6aa20a22 515 aup->rx_dma_ring[i] =
1da177e4
LT		 516 (volatile rx_dma_t *) (rx_base + sizeof(rx_dma_t)*i);
517 }
518 for (i = 0; i < NUM_TX_DMA; i++) {
6aa20a22 519 aup->tx_dma_ring[i] =
1da177e4
LT		 520 (volatile tx_dma_t *) (tx_base + sizeof(tx_dma_t)*i);
521 }
522}
523
524static struct {
1da177e4
LT		 525 u32 base_addr;
526 u32 macen_addr;
527 int irq;
528 struct net_device *dev;
89be0501
SS		 529} iflist[2] = {
530#ifdef CONFIG_SOC_AU1000
531 {AU1000_ETH0_BASE, AU1000_MAC0_ENABLE, AU1000_MAC0_DMA_INT},
532 {AU1000_ETH1_BASE, AU1000_MAC1_ENABLE, AU1000_MAC1_DMA_INT}
533#endif
534#ifdef CONFIG_SOC_AU1100
535 {AU1100_ETH0_BASE, AU1100_MAC0_ENABLE, AU1100_MAC0_DMA_INT}
536#endif
537#ifdef CONFIG_SOC_AU1500
538 {AU1500_ETH0_BASE, AU1500_MAC0_ENABLE, AU1500_MAC0_DMA_INT},
539 {AU1500_ETH1_BASE, AU1500_MAC1_ENABLE, AU1500_MAC1_DMA_INT}
540#endif
541#ifdef CONFIG_SOC_AU1550
542 {AU1550_ETH0_BASE, AU1550_MAC0_ENABLE, AU1550_MAC0_DMA_INT},
543 {AU1550_ETH1_BASE, AU1550_MAC1_ENABLE, AU1550_MAC1_DMA_INT}
544#endif
545};
1da177e4
LT		 546
547static int num_ifs;
548
549/*
550 * Setup the base address and interupt of the Au1xxx ethernet macs
551 * based on cpu type and whether the interface is enabled in sys_pinfunc
552 * register. The last interface is enabled if SYS_PF_NI2 (bit 4) is 0.
553 */
554static int __init au1000_init_module(void)
555{
1da177e4
LT		 556 int ni = (int)((au_readl(SYS_PINFUNC) & (u32)(SYS_PF_NI2)) >> 4);
557 struct net_device *dev;
558 int i, found_one = 0;
559
89be0501
SS		 560 num_ifs = NUM_ETH_INTERFACES - ni;
561
1da177e4 562 for(i = 0; i < num_ifs; i++) {
89be0501 563 dev = au1000_probe(i);
1da177e4
LT		 564 iflist[i].dev = dev;
565 if (dev)
566 found_one++;
567 }
568 if (!found_one)
569 return -ENODEV;
570 return 0;
571}
572
0638dec0
HVR		 573/*
574 * ethtool operations
575 */
1da177e4 576
0638dec0 577static int au1000_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1da177e4
LT		 578{
579 struct au1000_private *aup = (struct au1000_private *)dev->priv;
1da177e4 580
0638dec0
HVR		 581 if (aup->phy_dev)
582 return phy_ethtool_gset(aup->phy_dev, cmd);
1da177e4 583
0638dec0 584 return -EINVAL;
1da177e4
LT		 585}
586
0638dec0 587static int au1000_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1da177e4
LT		 588{
589 struct au1000_private *aup = (struct au1000_private *)dev->priv;
1da177e4 590
0638dec0
HVR		 591 if (!capable(CAP_NET_ADMIN))
592 return -EPERM;
1da177e4 593
0638dec0
HVR		 594 if (aup->phy_dev)
595 return phy_ethtool_sset(aup->phy_dev, cmd);
1da177e4 596
0638dec0 597 return -EINVAL;
1da177e4
LT		 598}
599
600static void
601au1000_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
602{
603 struct au1000_private *aup = (struct au1000_private *)dev->priv;
604
605 strcpy(info->driver, DRV_NAME);
606 strcpy(info->version, DRV_VERSION);
607 info->fw_version[0] = '\0';
608 sprintf(info->bus_info, "%s %d", DRV_NAME, aup->mac_id);
609 info->regdump_len = 0;
610}
611
7282d491 612static const struct ethtool_ops au1000_ethtool_ops = {
1da177e4
LT		 613 .get_settings = au1000_get_settings,
614 .set_settings = au1000_set_settings,
615 .get_drvinfo = au1000_get_drvinfo,
0638dec0 616 .get_link = ethtool_op_get_link,
1da177e4
LT		 617};
618
89be0501 619static struct net_device * au1000_probe(int port_num)
1da177e4
LT		 620{
621 static unsigned version_printed = 0;
622 struct au1000_private *aup = NULL;
623 struct net_device *dev = NULL;
624 db_dest_t *pDB, *pDBfree;
625 char *pmac, *argptr;
626 char ethaddr[6];
89be0501
SS		 627 int irq, i, err;
628 u32 base, macen;
629
630 if (port_num >= NUM_ETH_INTERFACES)
631 return NULL;
1da177e4 632
89be0501
SS		 633 base = CPHYSADDR(iflist[port_num].base_addr );
634 macen = CPHYSADDR(iflist[port_num].macen_addr);
635 irq = iflist[port_num].irq;
636
637 if (!request_mem_region( base, MAC_IOSIZE, "Au1x00 ENET") ||
638 !request_mem_region(macen, 4, "Au1x00 ENET"))
1da177e4
LT		 639 return NULL;
640
89be0501 641 if (version_printed++ == 0)
1da177e4
LT		 642 printk("%s version %s %s\n", DRV_NAME, DRV_VERSION, DRV_AUTHOR);
643
644 dev = alloc_etherdev(sizeof(struct au1000_private));
645 if (!dev) {
89be0501 646 printk(KERN_ERR "%s: alloc_etherdev failed\n", DRV_NAME);
1da177e4
LT		 647 return NULL;
648 }
649
89be0501
SS		 650 if ((err = register_netdev(dev)) != 0) {
651 printk(KERN_ERR "%s: Cannot register net device, error %d\n",
652 DRV_NAME, err);
1da177e4
LT		 653 free_netdev(dev);
654 return NULL;
655 }
656
89be0501
SS		 657 printk("%s: Au1xx0 Ethernet found at 0x%x, irq %d\n",
658 dev->name, base, irq);
1da177e4
LT		 659
660 aup = dev->priv;
661
662 /* Allocate the data buffers */
663 /* Snooping works fine with eth on all au1xxx */
89be0501
SS		 664 aup->vaddr = (u32)dma_alloc_noncoherent(NULL, MAX_BUF_SIZE *
665 (NUM_TX_BUFFS + NUM_RX_BUFFS),
666 &aup->dma_addr, 0);
1da177e4
LT		 667 if (!aup->vaddr) {
668 free_netdev(dev);
89be0501
SS		 669 release_mem_region( base, MAC_IOSIZE);
670 release_mem_region(macen, 4);
1da177e4
LT		 671 return NULL;
672 }
673
674 /* aup->mac is the base address of the MAC's registers */
89be0501
SS		 675 aup->mac = (volatile mac_reg_t *)iflist[port_num].base_addr;
676
1da177e4 677 /* Setup some variables for quick register address access */
89be0501
SS		 678 aup->enable = (volatile u32 *)iflist[port_num].macen_addr;
679 aup->mac_id = port_num;
680 au_macs[port_num] = aup;
681
682 if (port_num == 0) {
683 /* Check the environment variables first */
684 if (get_ethernet_addr(ethaddr) == 0)
1da177e4 685 memcpy(au1000_mac_addr, ethaddr, sizeof(au1000_mac_addr));
89be0501 686 else {
1da177e4
LT		 687 /* Check command line */
688 argptr = prom_getcmdline();
89be0501
SS		 689 if ((pmac = strstr(argptr, "ethaddr=")) == NULL)
690 printk(KERN_INFO "%s: No MAC address found\n",
691 dev->name);
692 /* Use the hard coded MAC addresses */
693 else {
1da177e4 694 str2eaddr(ethaddr, pmac + strlen("ethaddr="));
6aa20a22 695 memcpy(au1000_mac_addr, ethaddr,
89be0501 696 sizeof(au1000_mac_addr));
1da177e4
LT		 697 }
698 }
89be0501 699
1da177e4 700 setup_hw_rings(aup, MAC0_RX_DMA_ADDR, MAC0_TX_DMA_ADDR);
89be0501 701 } else if (port_num == 1)
1da177e4 702 setup_hw_rings(aup, MAC1_RX_DMA_ADDR, MAC1_TX_DMA_ADDR);
1da177e4 703
89be0501
SS		 704 /*
705 * Assign to the Ethernet ports two consecutive MAC addresses
706 * to match those that are printed on their stickers
707 */
708 memcpy(dev->dev_addr, au1000_mac_addr, sizeof(au1000_mac_addr));
709 dev->dev_addr[5] += port_num;
710
0638dec0
HVR		 711 *aup->enable = 0;
712 aup->mac_enabled = 0;
713
714 aup->mii_bus.priv = dev;
715 aup->mii_bus.read = mdiobus_read;
716 aup->mii_bus.write = mdiobus_write;
717 aup->mii_bus.reset = mdiobus_reset;
718 aup->mii_bus.name = "au1000_eth_mii";
719 aup->mii_bus.id = aup->mac_id;
720 aup->mii_bus.irq = kmalloc(sizeof(int)*PHY_MAX_ADDR, GFP_KERNEL);
721 for(i = 0; i < PHY_MAX_ADDR; ++i)
722 aup->mii_bus.irq[i] = PHY_POLL;
723
724 /* if known, set corresponding PHY IRQs */
725#if defined(AU1XXX_PHY_STATIC_CONFIG)
726# if defined(AU1XXX_PHY0_IRQ)
727 if (AU1XXX_PHY0_BUSID == aup->mii_bus.id)
728 aup->mii_bus.irq[AU1XXX_PHY0_ADDR] = AU1XXX_PHY0_IRQ;
729# endif
730# if defined(AU1XXX_PHY1_IRQ)
731 if (AU1XXX_PHY1_BUSID == aup->mii_bus.id)
732 aup->mii_bus.irq[AU1XXX_PHY1_ADDR] = AU1XXX_PHY1_IRQ;
733# endif
734#endif
735 mdiobus_register(&aup->mii_bus);
1da177e4
LT		 736
737 if (mii_probe(dev) != 0) {
738 goto err_out;
739 }
740
741 pDBfree = NULL;
742 /* setup the data buffer descriptors and attach a buffer to each one */
743 pDB = aup->db;
744 for (i = 0; i < (NUM_TX_BUFFS+NUM_RX_BUFFS); i++) {
745 pDB->pnext = pDBfree;
746 pDBfree = pDB;
747 pDB->vaddr = (u32 *)((unsigned)aup->vaddr + MAX_BUF_SIZE*i);
748 pDB->dma_addr = (dma_addr_t)virt_to_bus(pDB->vaddr);
749 pDB++;
750 }
751 aup->pDBfree = pDBfree;
752
753 for (i = 0; i < NUM_RX_DMA; i++) {
754 pDB = GetFreeDB(aup);
755 if (!pDB) {
756 goto err_out;
757 }
758 aup->rx_dma_ring[i]->buff_stat = (unsigned)pDB->dma_addr;
759 aup->rx_db_inuse[i] = pDB;
760 }
761 for (i = 0; i < NUM_TX_DMA; i++) {
762 pDB = GetFreeDB(aup);
763 if (!pDB) {
764 goto err_out;
765 }
766 aup->tx_dma_ring[i]->buff_stat = (unsigned)pDB->dma_addr;
767 aup->tx_dma_ring[i]->len = 0;
768 aup->tx_db_inuse[i] = pDB;
769 }
770
771 spin_lock_init(&aup->lock);
89be0501 772 dev->base_addr = base;
1da177e4
LT		 773 dev->irq = irq;
774 dev->open = au1000_open;
775 dev->hard_start_xmit = au1000_tx;
776 dev->stop = au1000_close;
777 dev->get_stats = au1000_get_stats;
778 dev->set_multicast_list = &set_rx_mode;
779 dev->do_ioctl = &au1000_ioctl;
780 SET_ETHTOOL_OPS(dev, &au1000_ethtool_ops);
1da177e4
LT		 781 dev->tx_timeout = au1000_tx_timeout;
782 dev->watchdog_timeo = ETH_TX_TIMEOUT;
783
6aa20a22
JG		 784 /*
785 * The boot code uses the ethernet controller, so reset it to start
1da177e4
LT		 786 * fresh. au1000_init() expects that the device is in reset state.
787 */
788 reset_mac(dev);
789
790 return dev;
791
792err_out:
793 /* here we should have a valid dev plus aup-> register addresses
794 * so we can reset the mac properly.*/
795 reset_mac(dev);
0638dec0 796
1da177e4
LT		 797 for (i = 0; i < NUM_RX_DMA; i++) {
798 if (aup->rx_db_inuse[i])
799 ReleaseDB(aup, aup->rx_db_inuse[i]);
800 }
801 for (i = 0; i < NUM_TX_DMA; i++) {
802 if (aup->tx_db_inuse[i])
803 ReleaseDB(aup, aup->tx_db_inuse[i]);
804 }
89be0501
SS		 805 dma_free_noncoherent(NULL, MAX_BUF_SIZE * (NUM_TX_BUFFS + NUM_RX_BUFFS),
806 (void *)aup->vaddr, aup->dma_addr);
1da177e4
LT		 807 unregister_netdev(dev);
808 free_netdev(dev);
89be0501
SS		 809 release_mem_region( base, MAC_IOSIZE);
810 release_mem_region(macen, 4);
1da177e4
LT		 811 return NULL;
812}
813
6aa20a22 814/*
1da177e4
LT		 815 * Initialize the interface.
816 *
817 * When the device powers up, the clocks are disabled and the
818 * mac is in reset state. When the interface is closed, we
819 * do the same -- reset the device and disable the clocks to
820 * conserve power. Thus, whenever au1000_init() is called,
821 * the device should already be in reset state.
822 */
823static int au1000_init(struct net_device *dev)
824{
825 struct au1000_private *aup = (struct au1000_private *) dev->priv;
826 u32 flags;
827 int i;
828 u32 control;
1da177e4 829
6aa20a22 830 if (au1000_debug > 4)
1da177e4
LT		 831 printk("%s: au1000_init\n", dev->name);
832
1da177e4 833 /* bring the device out of reset */
0638dec0
HVR		 834 enable_mac(dev, 1);
835
836 spin_lock_irqsave(&aup->lock, flags);
1da177e4
LT		 837
838 aup->mac->control = 0;
839 aup->tx_head = (aup->tx_dma_ring[0]->buff_stat & 0xC) >> 2;
840 aup->tx_tail = aup->tx_head;
841 aup->rx_head = (aup->rx_dma_ring[0]->buff_stat & 0xC) >> 2;
842
843 aup->mac->mac_addr_high = dev->dev_addr[5]<<8 | dev->dev_addr[4];
844 aup->mac->mac_addr_low = dev->dev_addr[3]<<24 | dev->dev_addr[2]<<16 |
845 dev->dev_addr[1]<<8 | dev->dev_addr[0];
846
847 for (i = 0; i < NUM_RX_DMA; i++) {
848 aup->rx_dma_ring[i]->buff_stat |= RX_DMA_ENABLE;
849 }
850 au_sync();
851
0638dec0 852 control = MAC_RX_ENABLE | MAC_TX_ENABLE;
1da177e4
LT		 853#ifndef CONFIG_CPU_LITTLE_ENDIAN
854 control |= MAC_BIG_ENDIAN;
855#endif
0638dec0
HVR		 856 if (aup->phy_dev) {
857 if (aup->phy_dev->link && (DUPLEX_FULL == aup->phy_dev->duplex))
858 control |= MAC_FULL_DUPLEX;
859 else
860 control |= MAC_DISABLE_RX_OWN;
861 } else { /* PHY-less op, assume full-duplex */
1da177e4
LT		 862 control |= MAC_FULL_DUPLEX;
863 }
864
1da177e4
LT		 865 aup->mac->control = control;
866 aup->mac->vlan1_tag = 0x8100; /* activate vlan support */
867 au_sync();
868
869 spin_unlock_irqrestore(&aup->lock, flags);
870 return 0;
871}
872
0638dec0
HVR		 873static void
874au1000_adjust_link(struct net_device *dev)
1da177e4 875{
1da177e4 876 struct au1000_private *aup = (struct au1000_private *) dev->priv;
0638dec0
HVR		 877 struct phy_device *phydev = aup->phy_dev;
878 unsigned long flags;
1da177e4 879
0638dec0 880 int status_change = 0;
1da177e4 881
0638dec0
HVR		 882 BUG_ON(!aup->phy_dev);
883
884 spin_lock_irqsave(&aup->lock, flags);
885
886 if (phydev->link && (aup->old_speed != phydev->speed)) {
887 // speed changed
888
889 switch(phydev->speed) {
890 case SPEED_10:
891 case SPEED_100:
892 break;
893 default:
894 printk(KERN_WARNING
895 "%s: Speed (%d) is not 10/100 ???\n",
896 dev->name, phydev->speed);
897 break;
1da177e4 898 }
0638dec0
HVR		 899
900 aup->old_speed = phydev->speed;
901
902 status_change = 1;
1da177e4
LT		 903 }
904
0638dec0
HVR		 905 if (phydev->link && (aup->old_duplex != phydev->duplex)) {
906 // duplex mode changed
907
908 /* switching duplex mode requires to disable rx and tx! */
1da177e4 909 hard_stop(dev);
0638dec0
HVR		 910
911 if (DUPLEX_FULL == phydev->duplex)
912 aup->mac->control = ((aup->mac->control
913 | MAC_FULL_DUPLEX)
914 & ~MAC_DISABLE_RX_OWN);
915 else
916 aup->mac->control = ((aup->mac->control
917 & ~MAC_FULL_DUPLEX)
918 | MAC_DISABLE_RX_OWN);
919 au_sync_delay(1);
920
1da177e4 921 enable_rx_tx(dev);
0638dec0
HVR		 922 aup->old_duplex = phydev->duplex;
923
924 status_change = 1;
925 }
926
927 if(phydev->link != aup->old_link) {
928 // link state changed
929
930 if (phydev->link) // link went up
931 netif_schedule(dev);
932 else { // link went down
933 aup->old_speed = 0;
934 aup->old_duplex = -1;
935 }
936
937 aup->old_link = phydev->link;
938 status_change = 1;
1da177e4
LT		 939 }
940
0638dec0 941 spin_unlock_irqrestore(&aup->lock, flags);
1da177e4 942
0638dec0
HVR		 943 if (status_change) {
944 if (phydev->link)
945 printk(KERN_INFO "%s: link up (%d/%s)\n",
946 dev->name, phydev->speed,
947 DUPLEX_FULL == phydev->duplex ? "Full" : "Half");
948 else
949 printk(KERN_INFO "%s: link down\n", dev->name);
950 }
1da177e4
LT		 951}
952
953static int au1000_open(struct net_device *dev)
954{
955 int retval;
956 struct au1000_private *aup = (struct au1000_private *) dev->priv;
957
958 if (au1000_debug > 4)
959 printk("%s: open: dev=%p\n", dev->name, dev);
960
0638dec0
HVR		 961 if ((retval = request_irq(dev->irq, &au1000_interrupt, 0,
962 dev->name, dev))) {
963 printk(KERN_ERR "%s: unable to get IRQ %d\n",
964 dev->name, dev->irq);
965 return retval;
966 }
967
1da177e4
LT		 968 if ((retval = au1000_init(dev))) {
969 printk(KERN_ERR "%s: error in au1000_init\n", dev->name);
970 free_irq(dev->irq, dev);
971 return retval;
972 }
1da177e4 973
0638dec0
HVR		 974 if (aup->phy_dev) {
975 /* cause the PHY state machine to schedule a link state check */
976 aup->phy_dev->state = PHY_CHANGELINK;
977 phy_start(aup->phy_dev);
1da177e4
LT		 978 }
979
0638dec0 980 netif_start_queue(dev);
1da177e4
LT		 981
982 if (au1000_debug > 4)
983 printk("%s: open: Initialization done.\n", dev->name);
984
985 return 0;
986}
987
988static int au1000_close(struct net_device *dev)
989{
0638dec0
HVR		 990 unsigned long flags;
991 struct au1000_private *const aup = (struct au1000_private *) dev->priv;
1da177e4
LT		 992
993 if (au1000_debug > 4)
994 printk("%s: close: dev=%p\n", dev->name, dev);
995
0638dec0
HVR		 996 if (aup->phy_dev)
997 phy_stop(aup->phy_dev);
1da177e4
LT		 998
999 spin_lock_irqsave(&aup->lock, flags);
0638dec0
HVR		 1000
1001 reset_mac_unlocked (dev);
1002
1da177e4
LT		 1003 /* stop the device */
1004 netif_stop_queue(dev);
1005
1006 /* disable the interrupt */
1007 free_irq(dev->irq, dev);
1008 spin_unlock_irqrestore(&aup->lock, flags);
1009
1010 return 0;
1011}
1012
1013static void __exit au1000_cleanup_module(void)
1014{
1015 int i, j;
1016 struct net_device *dev;
1017 struct au1000_private *aup;
1018
1019 for (i = 0; i < num_ifs; i++) {
1020 dev = iflist[i].dev;
1021 if (dev) {
1022 aup = (struct au1000_private *) dev->priv;
1023 unregister_netdev(dev);
89be0501 1024 for (j = 0; j < NUM_RX_DMA; j++)
1da177e4
LT		 1025 if (aup->rx_db_inuse[j])
1026 ReleaseDB(aup, aup->rx_db_inuse[j]);
89be0501 1027 for (j = 0; j < NUM_TX_DMA; j++)
1da177e4
LT		 1028 if (aup->tx_db_inuse[j])
1029 ReleaseDB(aup, aup->tx_db_inuse[j]);
89be0501
SS		 1030 dma_free_noncoherent(NULL, MAX_BUF_SIZE *
1031 (NUM_TX_BUFFS + NUM_RX_BUFFS),
1032 (void *)aup->vaddr, aup->dma_addr);
1033 release_mem_region(dev->base_addr, MAC_IOSIZE);
1034 release_mem_region(CPHYSADDR(iflist[i].macen_addr), 4);
1da177e4 1035 free_netdev(dev);
1da177e4
LT		 1036 }
1037 }
1038}
1039
c2d3d4b9 1040static void update_tx_stats(struct net_device *dev, u32 status)
1da177e4
LT		 1041{
1042 struct au1000_private *aup = (struct au1000_private *) dev->priv;
1043 struct net_device_stats *ps = &aup->stats;
1044
1da177e4 1045 if (status & TX_FRAME_ABORTED) {
0638dec0 1046 if (!aup->phy_dev || (DUPLEX_FULL == aup->phy_dev->duplex)) {
1da177e4
LT		 1047 if (status & (TX_JAB_TIMEOUT | TX_UNDERRUN)) {
1048 /* any other tx errors are only valid
1049 * in half duplex mode */
1050 ps->tx_errors++;
1051 ps->tx_aborted_errors++;
1052 }
1053 }
1054 else {
1055 ps->tx_errors++;
1056 ps->tx_aborted_errors++;
1057 if (status & (TX_NO_CARRIER | TX_LOSS_CARRIER))
1058 ps->tx_carrier_errors++;
1059 }
1060 }
1061}
1062
1063
1064/*
1065 * Called from the interrupt service routine to acknowledge
1066 * the TX DONE bits. This is a must if the irq is setup as
1067 * edge triggered.
1068 */
1069static void au1000_tx_ack(struct net_device *dev)
1070{
1071 struct au1000_private *aup = (struct au1000_private *) dev->priv;
1072 volatile tx_dma_t *ptxd;
1073
1074 ptxd = aup->tx_dma_ring[aup->tx_tail];
1075
1076 while (ptxd->buff_stat & TX_T_DONE) {
c2d3d4b9 1077 update_tx_stats(dev, ptxd->status);
1da177e4
LT		 1078 ptxd->buff_stat &= ~TX_T_DONE;
1079 ptxd->len = 0;
1080 au_sync();
1081
1082 aup->tx_tail = (aup->tx_tail + 1) & (NUM_TX_DMA - 1);
1083 ptxd = aup->tx_dma_ring[aup->tx_tail];
1084
1085 if (aup->tx_full) {
1086 aup->tx_full = 0;
1087 netif_wake_queue(dev);
1088 }
1089 }
1090}
1091
1092
1093/*
1094 * Au1000 transmit routine.
1095 */
1096static int au1000_tx(struct sk_buff *skb, struct net_device *dev)
1097{
1098 struct au1000_private *aup = (struct au1000_private *) dev->priv;
c2d3d4b9 1099 struct net_device_stats *ps = &aup->stats;
1da177e4
LT		 1100 volatile tx_dma_t *ptxd;
1101 u32 buff_stat;
1102 db_dest_t *pDB;
1103 int i;
1104
1105 if (au1000_debug > 5)
6aa20a22
JG		 1106 printk("%s: tx: aup %x len=%d, data=%p, head %d\n",
1107 dev->name, (unsigned)aup, skb->len,
1da177e4
LT		 1108 skb->data, aup->tx_head);
1109
1110 ptxd = aup->tx_dma_ring[aup->tx_head];
1111 buff_stat = ptxd->buff_stat;
1112 if (buff_stat & TX_DMA_ENABLE) {
1113 /* We've wrapped around and the transmitter is still busy */
1114 netif_stop_queue(dev);
1115 aup->tx_full = 1;
1116 return 1;
1117 }
1118 else if (buff_stat & TX_T_DONE) {
c2d3d4b9 1119 update_tx_stats(dev, ptxd->status);
1da177e4
LT		 1120 ptxd->len = 0;
1121 }
1122
1123 if (aup->tx_full) {
1124 aup->tx_full = 0;
1125 netif_wake_queue(dev);
1126 }
1127
1128 pDB = aup->tx_db_inuse[aup->tx_head];
1129 memcpy((void *)pDB->vaddr, skb->data, skb->len);
1130 if (skb->len < ETH_ZLEN) {
6aa20a22 1131 for (i=skb->len; i<ETH_ZLEN; i++) {
1da177e4
LT		 1132 ((char *)pDB->vaddr)[i] = 0;
1133 }
1134 ptxd->len = ETH_ZLEN;
1135 }
1136 else
1137 ptxd->len = skb->len;
1138
c2d3d4b9
SS		 1139 ps->tx_packets++;
1140 ps->tx_bytes += ptxd->len;
1141
1da177e4
LT		 1142 ptxd->buff_stat = pDB->dma_addr | TX_DMA_ENABLE;
1143 au_sync();
1144 dev_kfree_skb(skb);
1145 aup->tx_head = (aup->tx_head + 1) & (NUM_TX_DMA - 1);
1146 dev->trans_start = jiffies;
1147 return 0;
1148}
1149
1da177e4
LT		 1150static inline void update_rx_stats(struct net_device *dev, u32 status)
1151{
1152 struct au1000_private *aup = (struct au1000_private *) dev->priv;
1153 struct net_device_stats *ps = &aup->stats;
1154
1155 ps->rx_packets++;
1156 if (status & RX_MCAST_FRAME)
1157 ps->multicast++;
1158
1159 if (status & RX_ERROR) {
1160 ps->rx_errors++;
1161 if (status & RX_MISSED_FRAME)
1162 ps->rx_missed_errors++;
1163 if (status & (RX_OVERLEN | RX_OVERLEN | RX_LEN_ERROR))
1164 ps->rx_length_errors++;
1165 if (status & RX_CRC_ERROR)
1166 ps->rx_crc_errors++;
1167 if (status & RX_COLL)
1168 ps->collisions++;
1169 }
6aa20a22 1170 else
1da177e4
LT		 1171 ps->rx_bytes += status & RX_FRAME_LEN_MASK;
1172
1173}
1174
1175/*
1176 * Au1000 receive routine.
1177 */
1178static int au1000_rx(struct net_device *dev)
1179{
1180 struct au1000_private *aup = (struct au1000_private *) dev->priv;
1181 struct sk_buff *skb;
1182 volatile rx_dma_t *prxd;
1183 u32 buff_stat, status;
1184 db_dest_t *pDB;
1185 u32 frmlen;
1186
1187 if (au1000_debug > 5)
1188 printk("%s: au1000_rx head %d\n", dev->name, aup->rx_head);
1189
1190 prxd = aup->rx_dma_ring[aup->rx_head];
1191 buff_stat = prxd->buff_stat;
1192 while (buff_stat & RX_T_DONE) {
1193 status = prxd->status;
1194 pDB = aup->rx_db_inuse[aup->rx_head];
1195 update_rx_stats(dev, status);
1196 if (!(status & RX_ERROR)) {
1197
1198 /* good frame */
1199 frmlen = (status & RX_FRAME_LEN_MASK);
1200 frmlen -= 4; /* Remove FCS */
1201 skb = dev_alloc_skb(frmlen + 2);
1202 if (skb == NULL) {
1203 printk(KERN_ERR
1204 "%s: Memory squeeze, dropping packet.\n",
1205 dev->name);
1206 aup->stats.rx_dropped++;
1207 continue;
1208 }
1209 skb->dev = dev;
1210 skb_reserve(skb, 2); /* 16 byte IP header align */
1211 eth_copy_and_sum(skb,
1212 (unsigned char *)pDB->vaddr, frmlen, 0);
1213 skb_put(skb, frmlen);
1214 skb->protocol = eth_type_trans(skb, dev);
1215 netif_rx(skb); /* pass the packet to upper layers */
1216 }
1217 else {
1218 if (au1000_debug > 4) {
6aa20a22 1219 if (status & RX_MISSED_FRAME)
1da177e4 1220 printk("rx miss\n");
6aa20a22 1221 if (status & RX_WDOG_TIMER)
1da177e4 1222 printk("rx wdog\n");
6aa20a22 1223 if (status & RX_RUNT)
1da177e4 1224 printk("rx runt\n");
6aa20a22 1225 if (status & RX_OVERLEN)
1da177e4
LT		 1226 printk("rx overlen\n");
1227 if (status & RX_COLL)
1228 printk("rx coll\n");
1229 if (status & RX_MII_ERROR)
1230 printk("rx mii error\n");
1231 if (status & RX_CRC_ERROR)
1232 printk("rx crc error\n");
1233 if (status & RX_LEN_ERROR)
1234 printk("rx len error\n");
1235 if (status & RX_U_CNTRL_FRAME)
1236 printk("rx u control frame\n");
1237 if (status & RX_MISSED_FRAME)
1238 printk("rx miss\n");
1239 }
1240 }
1241 prxd->buff_stat = (u32)(pDB->dma_addr | RX_DMA_ENABLE);
1242 aup->rx_head = (aup->rx_head + 1) & (NUM_RX_DMA - 1);
1243 au_sync();
1244
1245 /* next descriptor */
1246 prxd = aup->rx_dma_ring[aup->rx_head];
1247 buff_stat = prxd->buff_stat;
1248 dev->last_rx = jiffies;
1249 }
1250 return 0;
1251}
1252
1253
1254/*
1255 * Au1000 interrupt service routine.
1256 */
7d12e780 1257static irqreturn_t au1000_interrupt(int irq, void *dev_id)
1da177e4
LT		 1258{
1259 struct net_device *dev = (struct net_device *) dev_id;
1260
1261 if (dev == NULL) {
1262 printk(KERN_ERR "%s: isr: null dev ptr\n", dev->name);
1263 return IRQ_RETVAL(1);
1264 }
1265
1266 /* Handle RX interrupts first to minimize chance of overrun */
1267
1268 au1000_rx(dev);
1269 au1000_tx_ack(dev);
1270 return IRQ_RETVAL(1);
1271}
1272
1273
1274/*
1275 * The Tx ring has been full longer than the watchdog timeout
1276 * value. The transmitter must be hung?
1277 */
1278static void au1000_tx_timeout(struct net_device *dev)
1279{
1280 printk(KERN_ERR "%s: au1000_tx_timeout: dev=%p\n", dev->name, dev);
1281 reset_mac(dev);
1282 au1000_init(dev);
1283 dev->trans_start = jiffies;
1284 netif_wake_queue(dev);
1285}
1286
1da177e4
LT		 1287static void set_rx_mode(struct net_device *dev)
1288{
1289 struct au1000_private *aup = (struct au1000_private *) dev->priv;
1290
6aa20a22 1291 if (au1000_debug > 4)
1da177e4
LT		 1292 printk("%s: set_rx_mode: flags=%x\n", dev->name, dev->flags);
1293
1294 if (dev->flags & IFF_PROMISC) { /* Set promiscuous. */
1295 aup->mac->control |= MAC_PROMISCUOUS;
1da177e4
LT		 1296 } else if ((dev->flags & IFF_ALLMULTI) ||
1297 dev->mc_count > MULTICAST_FILTER_LIMIT) {
1298 aup->mac->control |= MAC_PASS_ALL_MULTI;
1299 aup->mac->control &= ~MAC_PROMISCUOUS;
1300 printk(KERN_INFO "%s: Pass all multicast\n", dev->name);
1301 } else {
1302 int i;
1303 struct dev_mc_list *mclist;
1304 u32 mc_filter[2]; /* Multicast hash filter */
1305
1306 mc_filter[1] = mc_filter[0] = 0;
1307 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
1308 i++, mclist = mclist->next) {
6aa20a22 1309 set_bit(ether_crc(ETH_ALEN, mclist->dmi_addr)>>26,
1da177e4
LT		 1310 (long *)mc_filter);
1311 }
1312 aup->mac->multi_hash_high = mc_filter[1];
1313 aup->mac->multi_hash_low = mc_filter[0];
1314 aup->mac->control &= ~MAC_PROMISCUOUS;
1315 aup->mac->control |= MAC_HASH_MODE;
1316 }
1317}
1318
1da177e4
LT		 1319static int au1000_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1320{
1321 struct au1000_private *aup = (struct au1000_private *)dev->priv;
1da177e4 1322
0638dec0 1323 if (!netif_running(dev)) return -EINVAL;
1da177e4 1324
0638dec0 1325 if (!aup->phy_dev) return -EINVAL; // PHY not controllable
1da177e4 1326
0638dec0 1327 return phy_mii_ioctl(aup->phy_dev, if_mii(rq), cmd);
1da177e4
LT		 1328}
1329
1330static struct net_device_stats *au1000_get_stats(struct net_device *dev)
1331{
1332 struct au1000_private *aup = (struct au1000_private *) dev->priv;
1333
1334 if (au1000_debug > 4)
1335 printk("%s: au1000_get_stats: dev=%p\n", dev->name, dev);
1336
1337 if (netif_device_present(dev)) {
1338 return &aup->stats;
1339 }
1340 return 0;
1341}
1342
1343module_init(au1000_init_module);
1344module_exit(au1000_cleanup_module);
Linux kernel - Deliverables
This page took 0.246756 seconds and 5 git commands to generate.