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Merge branch 'r8169-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/romieu...
[deliverable/linux.git] / drivers / net / b44.c
CommitLineData
753f4920 1/* b44.c: Broadcom 44xx/47xx Fast Ethernet device driver.
1da177e4
LT		 2 *
3 * Copyright (C) 2002 David S. Miller (davem@redhat.com)
753f4920
MB		 4 * Copyright (C) 2004 Pekka Pietikainen (pp@ee.oulu.fi)
5 * Copyright (C) 2004 Florian Schirmer (jolt@tuxbox.org)
6 * Copyright (C) 2006 Felix Fietkau (nbd@openwrt.org)
8056bfaf 7 * Copyright (C) 2006 Broadcom Corporation.
753f4920 8 * Copyright (C) 2007 Michael Buesch <mb@bu3sch.de>
1da177e4
LT		 9 *
10 * Distribute under GPL.
11 */
12
13#include <linux/kernel.h>
14#include <linux/module.h>
15#include <linux/moduleparam.h>
16#include <linux/types.h>
17#include <linux/netdevice.h>
18#include <linux/ethtool.h>
19#include <linux/mii.h>
20#include <linux/if_ether.h>
72f4861e 21#include <linux/if_vlan.h>
1da177e4
LT		 22#include <linux/etherdevice.h>
23#include <linux/pci.h>
24#include <linux/delay.h>
25#include <linux/init.h>
89358f90 26#include <linux/dma-mapping.h>
753f4920 27#include <linux/ssb/ssb.h>
1da177e4
LT		 28
29#include <asm/uaccess.h>
30#include <asm/io.h>
31#include <asm/irq.h>
32
753f4920 33
1da177e4
LT		 34#include "b44.h"
35
36#define DRV_MODULE_NAME "b44"
37#define PFX DRV_MODULE_NAME ": "
753f4920 38#define DRV_MODULE_VERSION "2.0"
1da177e4
LT		 39
40#define B44_DEF_MSG_ENABLE \
41 (NETIF_MSG_DRV | \
42 NETIF_MSG_PROBE | \
43 NETIF_MSG_LINK | \
44 NETIF_MSG_TIMER | \
45 NETIF_MSG_IFDOWN | \
46 NETIF_MSG_IFUP | \
47 NETIF_MSG_RX_ERR | \
48 NETIF_MSG_TX_ERR)
49
50/* length of time before we decide the hardware is borked,
51 * and dev->tx_timeout() should be called to fix the problem
52 */
53#define B44_TX_TIMEOUT (5 * HZ)
54
55/* hardware minimum and maximum for a single frame's data payload */
56#define B44_MIN_MTU 60
57#define B44_MAX_MTU 1500
58
59#define B44_RX_RING_SIZE 512
60#define B44_DEF_RX_RING_PENDING 200
61#define B44_RX_RING_BYTES (sizeof(struct dma_desc) * \
62 B44_RX_RING_SIZE)
63#define B44_TX_RING_SIZE 512
64#define B44_DEF_TX_RING_PENDING (B44_TX_RING_SIZE - 1)
65#define B44_TX_RING_BYTES (sizeof(struct dma_desc) * \
66 B44_TX_RING_SIZE)
1da177e4
LT		 67
68#define TX_RING_GAP(BP) \
69 (B44_TX_RING_SIZE - (BP)->tx_pending)
70#define TX_BUFFS_AVAIL(BP) \
71 (((BP)->tx_cons <= (BP)->tx_prod) ? \
72 (BP)->tx_cons + (BP)->tx_pending - (BP)->tx_prod : \
73 (BP)->tx_cons - (BP)->tx_prod - TX_RING_GAP(BP))
74#define NEXT_TX(N) (((N) + 1) & (B44_TX_RING_SIZE - 1))
75
72f4861e
SH		 76#define RX_PKT_OFFSET 30
77#define RX_PKT_BUF_SZ (1536 + RX_PKT_OFFSET + 64)
1da177e4
LT		 78
79/* minimum number of free TX descriptors required to wake up TX process */
80#define B44_TX_WAKEUP_THRESH (B44_TX_RING_SIZE / 4)
81
725ad800
GZ		 82/* b44 internal pattern match filter info */
83#define B44_PATTERN_BASE 0x400
84#define B44_PATTERN_SIZE 0x80
85#define B44_PMASK_BASE 0x600
86#define B44_PMASK_SIZE 0x10
87#define B44_MAX_PATTERNS 16
88#define B44_ETHIPV6UDP_HLEN 62
89#define B44_ETHIPV4UDP_HLEN 42
90
1da177e4 91static char version[] __devinitdata =
753f4920 92 DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION "\n";
1da177e4 93
753f4920
MB		 94MODULE_AUTHOR("Felix Fietkau, Florian Schirmer, Pekka Pietikainen, David S. Miller");
95MODULE_DESCRIPTION("Broadcom 44xx/47xx 10/100 PCI ethernet driver");
1da177e4
LT		 96MODULE_LICENSE("GPL");
97MODULE_VERSION(DRV_MODULE_VERSION);
98
99static int b44_debug = -1; /* -1 == use B44_DEF_MSG_ENABLE as value */
100module_param(b44_debug, int, 0);
101MODULE_PARM_DESC(b44_debug, "B44 bitmapped debugging message enable value");
102
1da177e4 103
753f4920
MB		 104#ifdef CONFIG_B44_PCI
105static const struct pci_device_id b44_pci_tbl[] = {
106 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_BCM4401) },
107 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_BCM4401B0) },
108 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_BCM4401B1) },
109 { 0 } /* terminate list with empty entry */
110};
1da177e4
LT		 111MODULE_DEVICE_TABLE(pci, b44_pci_tbl);
112
753f4920
MB		 113static struct pci_driver b44_pci_driver = {
114 .name = DRV_MODULE_NAME,
115 .id_table = b44_pci_tbl,
116};
117#endif /* CONFIG_B44_PCI */
118
119static const struct ssb_device_id b44_ssb_tbl[] = {
120 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_ETHERNET, SSB_ANY_REV),
121 SSB_DEVTABLE_END
122};
123MODULE_DEVICE_TABLE(ssb, b44_ssb_tbl);
124
1da177e4
LT		 125static void b44_halt(struct b44 *);
126static void b44_init_rings(struct b44 *);
5fc7d61a
MC		 127
128#define B44_FULL_RESET 1
129#define B44_FULL_RESET_SKIP_PHY 2
130#define B44_PARTIAL_RESET 3
fedb0eef
MB		 131#define B44_CHIP_RESET_FULL 4
132#define B44_CHIP_RESET_PARTIAL 5
5fc7d61a 133
00e8b3aa 134static void b44_init_hw(struct b44 *, int);
1da177e4 135
9f38c636
JL		 136static int dma_desc_align_mask;
137static int dma_desc_sync_size;
753f4920 138static int instance;
9f38c636 139
3353930d
FR		 140static const char b44_gstrings[][ETH_GSTRING_LEN] = {
141#define _B44(x...) # x,
142B44_STAT_REG_DECLARE
143#undef _B44
144};
145
753f4920
MB		 146static inline void b44_sync_dma_desc_for_device(struct ssb_device *sdev,
147 dma_addr_t dma_base,
148 unsigned long offset,
149 enum dma_data_direction dir)
9f38c636 150{
f225763a
MB		 151 ssb_dma_sync_single_range_for_device(sdev, dma_base,
152 offset & dma_desc_align_mask,
153 dma_desc_sync_size, dir);
9f38c636
JL		 154}
155
753f4920
MB		 156static inline void b44_sync_dma_desc_for_cpu(struct ssb_device *sdev,
157 dma_addr_t dma_base,
158 unsigned long offset,
159 enum dma_data_direction dir)
9f38c636 160{
f225763a
MB		 161 ssb_dma_sync_single_range_for_cpu(sdev, dma_base,
162 offset & dma_desc_align_mask,
163 dma_desc_sync_size, dir);
9f38c636
JL		 164}
165
1da177e4
LT		 166static inline unsigned long br32(const struct b44 *bp, unsigned long reg)
167{
753f4920 168 return ssb_read32(bp->sdev, reg);
1da177e4
LT		 169}
170
10badc21 171static inline void bw32(const struct b44 *bp,
1da177e4
LT		 172 unsigned long reg, unsigned long val)
173{
753f4920 174 ssb_write32(bp->sdev, reg, val);
1da177e4
LT		 175}
176
177static int b44_wait_bit(struct b44 *bp, unsigned long reg,
178 u32 bit, unsigned long timeout, const int clear)
179{
180 unsigned long i;
181
182 for (i = 0; i < timeout; i++) {
183 u32 val = br32(bp, reg);
184
185 if (clear && !(val & bit))
186 break;
187 if (!clear && (val & bit))
188 break;
189 udelay(10);
190 }
191 if (i == timeout) {
192 printk(KERN_ERR PFX "%s: BUG! Timeout waiting for bit %08x of register "
193 "%lx to %s.\n",
194 bp->dev->name,
195 bit, reg,
196 (clear ? "clear" : "set"));
197 return -ENODEV;
198 }
199 return 0;
200}
201
753f4920 202static inline void __b44_cam_read(struct b44 *bp, unsigned char *data, int index)
1da177e4
LT		 203{
204 u32 val;
205
753f4920
MB		 206 bw32(bp, B44_CAM_CTRL, (CAM_CTRL_READ |
207 (index << CAM_CTRL_INDEX_SHIFT)));
1da177e4 208
753f4920 209 b44_wait_bit(bp, B44_CAM_CTRL, CAM_CTRL_BUSY, 100, 1);
1da177e4 210
753f4920 211 val = br32(bp, B44_CAM_DATA_LO);
1da177e4 212
753f4920
MB		 213 data[2] = (val >> 24) & 0xFF;
214 data[3] = (val >> 16) & 0xFF;
215 data[4] = (val >> 8) & 0xFF;
216 data[5] = (val >> 0) & 0xFF;
1da177e4 217
753f4920 218 val = br32(bp, B44_CAM_DATA_HI);
1da177e4 219
753f4920
MB		 220 data[0] = (val >> 8) & 0xFF;
221 data[1] = (val >> 0) & 0xFF;
1da177e4
LT		 222}
223
753f4920 224static inline void __b44_cam_write(struct b44 *bp, unsigned char *data, int index)
1da177e4
LT		 225{
226 u32 val;
227
228 val = ((u32) data[2]) << 24;
229 val |= ((u32) data[3]) << 16;
230 val |= ((u32) data[4]) << 8;
231 val |= ((u32) data[5]) << 0;
232 bw32(bp, B44_CAM_DATA_LO, val);
10badc21 233 val = (CAM_DATA_HI_VALID |
1da177e4
LT		 234 (((u32) data[0]) << 8) |
235 (((u32) data[1]) << 0));
236 bw32(bp, B44_CAM_DATA_HI, val);
237 bw32(bp, B44_CAM_CTRL, (CAM_CTRL_WRITE |
238 (index << CAM_CTRL_INDEX_SHIFT)));
10badc21 239 b44_wait_bit(bp, B44_CAM_CTRL, CAM_CTRL_BUSY, 100, 1);
1da177e4
LT		 240}
241
242static inline void __b44_disable_ints(struct b44 *bp)
243{
244 bw32(bp, B44_IMASK, 0);
245}
246
247static void b44_disable_ints(struct b44 *bp)
248{
249 __b44_disable_ints(bp);
250
251 /* Flush posted writes. */
252 br32(bp, B44_IMASK);
253}
254
255static void b44_enable_ints(struct b44 *bp)
256{
257 bw32(bp, B44_IMASK, bp->imask);
258}
259
753f4920 260static int __b44_readphy(struct b44 *bp, int phy_addr, int reg, u32 *val)
1da177e4
LT		 261{
262 int err;
263
264 bw32(bp, B44_EMAC_ISTAT, EMAC_INT_MII);
265 bw32(bp, B44_MDIO_DATA, (MDIO_DATA_SB_START |
266 (MDIO_OP_READ << MDIO_DATA_OP_SHIFT) |
753f4920 267 (phy_addr << MDIO_DATA_PMD_SHIFT) |
1da177e4
LT		 268 (reg << MDIO_DATA_RA_SHIFT) |
269 (MDIO_TA_VALID << MDIO_DATA_TA_SHIFT)));
270 err = b44_wait_bit(bp, B44_EMAC_ISTAT, EMAC_INT_MII, 100, 0);
271 *val = br32(bp, B44_MDIO_DATA) & MDIO_DATA_DATA;
272
273 return err;
274}
275
753f4920 276static int __b44_writephy(struct b44 *bp, int phy_addr, int reg, u32 val)
1da177e4
LT		 277{
278 bw32(bp, B44_EMAC_ISTAT, EMAC_INT_MII);
279 bw32(bp, B44_MDIO_DATA, (MDIO_DATA_SB_START |
280 (MDIO_OP_WRITE << MDIO_DATA_OP_SHIFT) |
753f4920 281 (phy_addr << MDIO_DATA_PMD_SHIFT) |
1da177e4
LT		 282 (reg << MDIO_DATA_RA_SHIFT) |
283 (MDIO_TA_VALID << MDIO_DATA_TA_SHIFT) |
284 (val & MDIO_DATA_DATA)));
285 return b44_wait_bit(bp, B44_EMAC_ISTAT, EMAC_INT_MII, 100, 0);
286}
287
753f4920
MB		 288static inline int b44_readphy(struct b44 *bp, int reg, u32 *val)
289{
290 if (bp->phy_addr == B44_PHY_ADDR_NO_PHY)
291 return 0;
292
293 return __b44_readphy(bp, bp->phy_addr, reg, val);
294}
295
296static inline int b44_writephy(struct b44 *bp, int reg, u32 val)
297{
298 if (bp->phy_addr == B44_PHY_ADDR_NO_PHY)
299 return 0;
300
301 return __b44_writephy(bp, bp->phy_addr, reg, val);
302}
303
1da177e4 304/* miilib interface */
1da177e4
LT		 305static int b44_mii_read(struct net_device *dev, int phy_id, int location)
306{
307 u32 val;
308 struct b44 *bp = netdev_priv(dev);
753f4920 309 int rc = __b44_readphy(bp, phy_id, location, &val);
1da177e4
LT		 310 if (rc)
311 return 0xffffffff;
312 return val;
313}
314
315static void b44_mii_write(struct net_device *dev, int phy_id, int location,
316 int val)
317{
318 struct b44 *bp = netdev_priv(dev);
753f4920 319 __b44_writephy(bp, phy_id, location, val);
1da177e4
LT		 320}
321
322static int b44_phy_reset(struct b44 *bp)
323{
324 u32 val;
325 int err;
326
753f4920
MB		 327 if (bp->phy_addr == B44_PHY_ADDR_NO_PHY)
328 return 0;
1da177e4
LT		 329 err = b44_writephy(bp, MII_BMCR, BMCR_RESET);
330 if (err)
331 return err;
332 udelay(100);
333 err = b44_readphy(bp, MII_BMCR, &val);
334 if (!err) {
335 if (val & BMCR_RESET) {
336 printk(KERN_ERR PFX "%s: PHY Reset would not complete.\n",
337 bp->dev->name);
338 err = -ENODEV;
339 }
340 }
341
342 return 0;
343}
344
345static void __b44_set_flow_ctrl(struct b44 *bp, u32 pause_flags)
346{
347 u32 val;
348
349 bp->flags &= ~(B44_FLAG_TX_PAUSE | B44_FLAG_RX_PAUSE);
350 bp->flags |= pause_flags;
351
352 val = br32(bp, B44_RXCONFIG);
353 if (pause_flags & B44_FLAG_RX_PAUSE)
354 val |= RXCONFIG_FLOW;
355 else
356 val &= ~RXCONFIG_FLOW;
357 bw32(bp, B44_RXCONFIG, val);
358
359 val = br32(bp, B44_MAC_FLOW);
360 if (pause_flags & B44_FLAG_TX_PAUSE)
361 val |= (MAC_FLOW_PAUSE_ENAB |
362 (0xc0 & MAC_FLOW_RX_HI_WATER));
363 else
364 val &= ~MAC_FLOW_PAUSE_ENAB;
365 bw32(bp, B44_MAC_FLOW, val);
366}
367
368static void b44_set_flow_ctrl(struct b44 *bp, u32 local, u32 remote)
369{
10badc21 370 u32 pause_enab = 0;
2b474cf5
GZ		 371
372 /* The driver supports only rx pause by default because
10badc21
JG		 373 the b44 mac tx pause mechanism generates excessive
374 pause frames.
2b474cf5
GZ		 375 Use ethtool to turn on b44 tx pause if necessary.
376 */
377 if ((local & ADVERTISE_PAUSE_CAP) &&
10badc21 378 (local & ADVERTISE_PAUSE_ASYM)){
2b474cf5
GZ		 379 if ((remote & LPA_PAUSE_ASYM) &&
380 !(remote & LPA_PAUSE_CAP))
381 pause_enab |= B44_FLAG_RX_PAUSE;
1da177e4
LT		 382 }
383
384 __b44_set_flow_ctrl(bp, pause_enab);
385}
386
753f4920
MB		 387#ifdef SSB_DRIVER_MIPS
388extern char *nvram_get(char *name);
389static void b44_wap54g10_workaround(struct b44 *bp)
390{
391 const char *str;
392 u32 val;
393 int err;
394
395 /*
396 * workaround for bad hardware design in Linksys WAP54G v1.0
397 * see https://dev.openwrt.org/ticket/146
398 * check and reset bit "isolate"
399 */
400 str = nvram_get("boardnum");
401 if (!str)
402 return;
403 if (simple_strtoul(str, NULL, 0) == 2) {
404 err = __b44_readphy(bp, 0, MII_BMCR, &val);
405 if (err)
406 goto error;
407 if (!(val & BMCR_ISOLATE))
408 return;
409 val &= ~BMCR_ISOLATE;
410 err = __b44_writephy(bp, 0, MII_BMCR, val);
411 if (err)
412 goto error;
413 }
414 return;
415error:
416 printk(KERN_WARNING PFX "PHY: cannot reset MII transceiver isolate bit.\n");
417}
418#else
419static inline void b44_wap54g10_workaround(struct b44 *bp)
420{
421}
422#endif
423
1da177e4
LT		 424static int b44_setup_phy(struct b44 *bp)
425{
426 u32 val;
427 int err;
428
753f4920
MB		 429 b44_wap54g10_workaround(bp);
430
431 if (bp->phy_addr == B44_PHY_ADDR_NO_PHY)
432 return 0;
1da177e4
LT		 433 if ((err = b44_readphy(bp, B44_MII_ALEDCTRL, &val)) != 0)
434 goto out;
435 if ((err = b44_writephy(bp, B44_MII_ALEDCTRL,
436 val & MII_ALEDCTRL_ALLMSK)) != 0)
437 goto out;
438 if ((err = b44_readphy(bp, B44_MII_TLEDCTRL, &val)) != 0)
439 goto out;
440 if ((err = b44_writephy(bp, B44_MII_TLEDCTRL,
441 val | MII_TLEDCTRL_ENABLE)) != 0)
442 goto out;
443
444 if (!(bp->flags & B44_FLAG_FORCE_LINK)) {
445 u32 adv = ADVERTISE_CSMA;
446
447 if (bp->flags & B44_FLAG_ADV_10HALF)
448 adv |= ADVERTISE_10HALF;
449 if (bp->flags & B44_FLAG_ADV_10FULL)
450 adv |= ADVERTISE_10FULL;
451 if (bp->flags & B44_FLAG_ADV_100HALF)
452 adv |= ADVERTISE_100HALF;
453 if (bp->flags & B44_FLAG_ADV_100FULL)
454 adv |= ADVERTISE_100FULL;
455
456 if (bp->flags & B44_FLAG_PAUSE_AUTO)
457 adv |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
458
459 if ((err = b44_writephy(bp, MII_ADVERTISE, adv)) != 0)
460 goto out;
461 if ((err = b44_writephy(bp, MII_BMCR, (BMCR_ANENABLE |
462 BMCR_ANRESTART))) != 0)
463 goto out;
464 } else {
465 u32 bmcr;
466
467 if ((err = b44_readphy(bp, MII_BMCR, &bmcr)) != 0)
468 goto out;
469 bmcr &= ~(BMCR_FULLDPLX | BMCR_ANENABLE | BMCR_SPEED100);
470 if (bp->flags & B44_FLAG_100_BASE_T)
471 bmcr |= BMCR_SPEED100;
472 if (bp->flags & B44_FLAG_FULL_DUPLEX)
473 bmcr |= BMCR_FULLDPLX;
474 if ((err = b44_writephy(bp, MII_BMCR, bmcr)) != 0)
475 goto out;
476
477 /* Since we will not be negotiating there is no safe way
478 * to determine if the link partner supports flow control
479 * or not. So just disable it completely in this case.
480 */
481 b44_set_flow_ctrl(bp, 0, 0);
482 }
483
484out:
485 return err;
486}
487
488static void b44_stats_update(struct b44 *bp)
489{
490 unsigned long reg;
491 u32 *val;
492
493 val = &bp->hw_stats.tx_good_octets;
494 for (reg = B44_TX_GOOD_O; reg <= B44_TX_PAUSE; reg += 4UL) {
495 *val++ += br32(bp, reg);
496 }
3353930d
FR		 497
498 /* Pad */
499 reg += 8*4UL;
500
1da177e4
LT		 501 for (reg = B44_RX_GOOD_O; reg <= B44_RX_NPAUSE; reg += 4UL) {
502 *val++ += br32(bp, reg);
503 }
504}
505
506static void b44_link_report(struct b44 *bp)
507{
508 if (!netif_carrier_ok(bp->dev)) {
509 printk(KERN_INFO PFX "%s: Link is down.\n", bp->dev->name);
510 } else {
511 printk(KERN_INFO PFX "%s: Link is up at %d Mbps, %s duplex.\n",
512 bp->dev->name,
513 (bp->flags & B44_FLAG_100_BASE_T) ? 100 : 10,
514 (bp->flags & B44_FLAG_FULL_DUPLEX) ? "full" : "half");
515
516 printk(KERN_INFO PFX "%s: Flow control is %s for TX and "
517 "%s for RX.\n",
518 bp->dev->name,
519 (bp->flags & B44_FLAG_TX_PAUSE) ? "on" : "off",
520 (bp->flags & B44_FLAG_RX_PAUSE) ? "on" : "off");
521 }
522}
523
524static void b44_check_phy(struct b44 *bp)
525{
526 u32 bmsr, aux;
527
753f4920
MB		 528 if (bp->phy_addr == B44_PHY_ADDR_NO_PHY) {
529 bp->flags |= B44_FLAG_100_BASE_T;
530 bp->flags |= B44_FLAG_FULL_DUPLEX;
531 if (!netif_carrier_ok(bp->dev)) {
532 u32 val = br32(bp, B44_TX_CTRL);
533 val |= TX_CTRL_DUPLEX;
534 bw32(bp, B44_TX_CTRL, val);
535 netif_carrier_on(bp->dev);
536 b44_link_report(bp);
537 }
538 return;
539 }
540
1da177e4
LT		 541 if (!b44_readphy(bp, MII_BMSR, &bmsr) &&
542 !b44_readphy(bp, B44_MII_AUXCTRL, &aux) &&
543 (bmsr != 0xffff)) {
544 if (aux & MII_AUXCTRL_SPEED)
545 bp->flags |= B44_FLAG_100_BASE_T;
546 else
547 bp->flags &= ~B44_FLAG_100_BASE_T;
548 if (aux & MII_AUXCTRL_DUPLEX)
549 bp->flags |= B44_FLAG_FULL_DUPLEX;
550 else
551 bp->flags &= ~B44_FLAG_FULL_DUPLEX;
552
553 if (!netif_carrier_ok(bp->dev) &&
554 (bmsr & BMSR_LSTATUS)) {
555 u32 val = br32(bp, B44_TX_CTRL);
556 u32 local_adv, remote_adv;
557
558 if (bp->flags & B44_FLAG_FULL_DUPLEX)
559 val |= TX_CTRL_DUPLEX;
560 else
561 val &= ~TX_CTRL_DUPLEX;
562 bw32(bp, B44_TX_CTRL, val);
563
564 if (!(bp->flags & B44_FLAG_FORCE_LINK) &&
565 !b44_readphy(bp, MII_ADVERTISE, &local_adv) &&
566 !b44_readphy(bp, MII_LPA, &remote_adv))
567 b44_set_flow_ctrl(bp, local_adv, remote_adv);
568
569 /* Link now up */
570 netif_carrier_on(bp->dev);
571 b44_link_report(bp);
572 } else if (netif_carrier_ok(bp->dev) && !(bmsr & BMSR_LSTATUS)) {
573 /* Link now down */
574 netif_carrier_off(bp->dev);
575 b44_link_report(bp);
576 }
577
578 if (bmsr & BMSR_RFAULT)
579 printk(KERN_WARNING PFX "%s: Remote fault detected in PHY\n",
580 bp->dev->name);
581 if (bmsr & BMSR_JCD)
582 printk(KERN_WARNING PFX "%s: Jabber detected in PHY\n",
583 bp->dev->name);
584 }
585}
586
587static void b44_timer(unsigned long __opaque)
588{
589 struct b44 *bp = (struct b44 *) __opaque;
590
591 spin_lock_irq(&bp->lock);
592
593 b44_check_phy(bp);
594
595 b44_stats_update(bp);
596
597 spin_unlock_irq(&bp->lock);
598
a72a8179 599 mod_timer(&bp->timer, round_jiffies(jiffies + HZ));
1da177e4
LT		 600}
601
602static void b44_tx(struct b44 *bp)
603{
604 u32 cur, cons;
605
606 cur = br32(bp, B44_DMATX_STAT) & DMATX_STAT_CDMASK;
607 cur /= sizeof(struct dma_desc);
608
609 /* XXX needs updating when NETIF_F_SG is supported */
610 for (cons = bp->tx_cons; cons != cur; cons = NEXT_TX(cons)) {
611 struct ring_info *rp = &bp->tx_buffers[cons];
612 struct sk_buff *skb = rp->skb;
613
5d9428de 614 BUG_ON(skb == NULL);
1da177e4 615
f225763a
MB		 616 ssb_dma_unmap_single(bp->sdev,
617 rp->mapping,
618 skb->len,
619 DMA_TO_DEVICE);
1da177e4
LT		 620 rp->skb = NULL;
621 dev_kfree_skb_irq(skb);
622 }
623
624 bp->tx_cons = cons;
625 if (netif_queue_stopped(bp->dev) &&
626 TX_BUFFS_AVAIL(bp) > B44_TX_WAKEUP_THRESH)
627 netif_wake_queue(bp->dev);
628
629 bw32(bp, B44_GPTIMER, 0);
630}
631
632/* Works like this. This chip writes a 'struct rx_header" 30 bytes
633 * before the DMA address you give it. So we allocate 30 more bytes
634 * for the RX buffer, DMA map all of it, skb_reserve the 30 bytes, then
635 * point the chip at 30 bytes past where the rx_header will go.
636 */
637static int b44_alloc_rx_skb(struct b44 *bp, int src_idx, u32 dest_idx_unmasked)
638{
639 struct dma_desc *dp;
640 struct ring_info *src_map, *map;
641 struct rx_header *rh;
642 struct sk_buff *skb;
643 dma_addr_t mapping;
644 int dest_idx;
645 u32 ctrl;
646
647 src_map = NULL;
648 if (src_idx >= 0)
649 src_map = &bp->rx_buffers[src_idx];
650 dest_idx = dest_idx_unmasked & (B44_RX_RING_SIZE - 1);
651 map = &bp->rx_buffers[dest_idx];
bf0dcbd9 652 skb = netdev_alloc_skb(bp->dev, RX_PKT_BUF_SZ);
1da177e4
LT		 653 if (skb == NULL)
654 return -ENOMEM;
655
f225763a
MB		 656 mapping = ssb_dma_map_single(bp->sdev, skb->data,
657 RX_PKT_BUF_SZ,
658 DMA_FROM_DEVICE);
1da177e4
LT		 659
660 /* Hardware bug work-around, the chip is unable to do PCI DMA
661 to/from anything above 1GB :-( */
f225763a 662 if (ssb_dma_mapping_error(bp->sdev, mapping) ||
97db9ee7 663 mapping + RX_PKT_BUF_SZ > DMA_30BIT_MASK) {
1da177e4 664 /* Sigh... */
f225763a
MB		 665 if (!ssb_dma_mapping_error(bp->sdev, mapping))
666 ssb_dma_unmap_single(bp->sdev, mapping,
667 RX_PKT_BUF_SZ, DMA_FROM_DEVICE);
1da177e4 668 dev_kfree_skb_any(skb);
bf0dcbd9 669 skb = __netdev_alloc_skb(bp->dev, RX_PKT_BUF_SZ, GFP_ATOMIC|GFP_DMA);
1da177e4
LT		 670 if (skb == NULL)
671 return -ENOMEM;
f225763a
MB		 672 mapping = ssb_dma_map_single(bp->sdev, skb->data,
673 RX_PKT_BUF_SZ,
674 DMA_FROM_DEVICE);
675 if (ssb_dma_mapping_error(bp->sdev, mapping) ||
97db9ee7 676 mapping + RX_PKT_BUF_SZ > DMA_30BIT_MASK) {
f225763a
MB		 677 if (!ssb_dma_mapping_error(bp->sdev, mapping))
678 ssb_dma_unmap_single(bp->sdev, mapping, RX_PKT_BUF_SZ,DMA_FROM_DEVICE);
1da177e4
LT		 679 dev_kfree_skb_any(skb);
680 return -ENOMEM;
681 }
682 }
683
72f4861e
SH		 684 rh = (struct rx_header *) skb->data;
685 skb_reserve(skb, RX_PKT_OFFSET);
1da177e4 686
1da177e4
LT		 687 rh->len = 0;
688 rh->flags = 0;
689
690 map->skb = skb;
753f4920 691 map->mapping = mapping;
1da177e4
LT		 692
693 if (src_map != NULL)
694 src_map->skb = NULL;
695
72f4861e 696 ctrl = (DESC_CTRL_LEN & (RX_PKT_BUF_SZ - RX_PKT_OFFSET));
1da177e4
LT		 697 if (dest_idx == (B44_RX_RING_SIZE - 1))
698 ctrl |= DESC_CTRL_EOT;
699
700 dp = &bp->rx_ring[dest_idx];
701 dp->ctrl = cpu_to_le32(ctrl);
72f4861e 702 dp->addr = cpu_to_le32((u32) mapping + RX_PKT_OFFSET + bp->dma_offset);
1da177e4 703
9f38c636 704 if (bp->flags & B44_FLAG_RX_RING_HACK)
753f4920
MB		 705 b44_sync_dma_desc_for_device(bp->sdev, bp->rx_ring_dma,
706 dest_idx * sizeof(dp),
707 DMA_BIDIRECTIONAL);
9f38c636 708
1da177e4
LT		 709 return RX_PKT_BUF_SZ;
710}
711
712static void b44_recycle_rx(struct b44 *bp, int src_idx, u32 dest_idx_unmasked)
713{
714 struct dma_desc *src_desc, *dest_desc;
715 struct ring_info *src_map, *dest_map;
716 struct rx_header *rh;
717 int dest_idx;
a7bed27d 718 __le32 ctrl;
1da177e4
LT		 719
720 dest_idx = dest_idx_unmasked & (B44_RX_RING_SIZE - 1);
721 dest_desc = &bp->rx_ring[dest_idx];
722 dest_map = &bp->rx_buffers[dest_idx];
723 src_desc = &bp->rx_ring[src_idx];
724 src_map = &bp->rx_buffers[src_idx];
725
726 dest_map->skb = src_map->skb;
727 rh = (struct rx_header *) src_map->skb->data;
728 rh->len = 0;
729 rh->flags = 0;
753f4920 730 dest_map->mapping = src_map->mapping;
1da177e4 731
9f38c636 732 if (bp->flags & B44_FLAG_RX_RING_HACK)
753f4920
MB		 733 b44_sync_dma_desc_for_cpu(bp->sdev, bp->rx_ring_dma,
734 src_idx * sizeof(src_desc),
735 DMA_BIDIRECTIONAL);
9f38c636 736
1da177e4
LT		 737 ctrl = src_desc->ctrl;
738 if (dest_idx == (B44_RX_RING_SIZE - 1))
739 ctrl |= cpu_to_le32(DESC_CTRL_EOT);
740 else
741 ctrl &= cpu_to_le32(~DESC_CTRL_EOT);
742
743 dest_desc->ctrl = ctrl;
744 dest_desc->addr = src_desc->addr;
9f38c636 745
1da177e4
LT		 746 src_map->skb = NULL;
747
9f38c636 748 if (bp->flags & B44_FLAG_RX_RING_HACK)
753f4920
MB		 749 b44_sync_dma_desc_for_device(bp->sdev, bp->rx_ring_dma,
750 dest_idx * sizeof(dest_desc),
751 DMA_BIDIRECTIONAL);
9f38c636 752
f225763a
MB		 753 ssb_dma_sync_single_for_device(bp->sdev, le32_to_cpu(src_desc->addr),
754 RX_PKT_BUF_SZ,
755 DMA_FROM_DEVICE);
1da177e4
LT		 756}
757
758static int b44_rx(struct b44 *bp, int budget)
759{
760 int received;
761 u32 cons, prod;
762
763 received = 0;
764 prod = br32(bp, B44_DMARX_STAT) & DMARX_STAT_CDMASK;
765 prod /= sizeof(struct dma_desc);
766 cons = bp->rx_cons;
767
768 while (cons != prod && budget > 0) {
769 struct ring_info *rp = &bp->rx_buffers[cons];
770 struct sk_buff *skb = rp->skb;
753f4920 771 dma_addr_t map = rp->mapping;
1da177e4
LT		 772 struct rx_header *rh;
773 u16 len;
774
f225763a 775 ssb_dma_sync_single_for_cpu(bp->sdev, map,
1da177e4 776 RX_PKT_BUF_SZ,
753f4920 777 DMA_FROM_DEVICE);
1da177e4 778 rh = (struct rx_header *) skb->data;
a7bed27d 779 len = le16_to_cpu(rh->len);
72f4861e 780 if ((len > (RX_PKT_BUF_SZ - RX_PKT_OFFSET)) ||
1da177e4
LT		 781 (rh->flags & cpu_to_le16(RX_FLAG_ERRORS))) {
782 drop_it:
783 b44_recycle_rx(bp, cons, bp->rx_prod);
784 drop_it_no_recycle:
785 bp->stats.rx_dropped++;
786 goto next_pkt;
787 }
788
789 if (len == 0) {
790 int i = 0;
791
792 do {
793 udelay(2);
794 barrier();
a7bed27d 795 len = le16_to_cpu(rh->len);
1da177e4
LT		 796 } while (len == 0 && i++ < 5);
797 if (len == 0)
798 goto drop_it;
799 }
800
801 /* Omit CRC. */
802 len -= 4;
803
804 if (len > RX_COPY_THRESHOLD) {
805 int skb_size;
806 skb_size = b44_alloc_rx_skb(bp, cons, bp->rx_prod);
807 if (skb_size < 0)
808 goto drop_it;
f225763a
MB		 809 ssb_dma_unmap_single(bp->sdev, map,
810 skb_size, DMA_FROM_DEVICE);
1da177e4 811 /* Leave out rx_header */
72f4861e
SH		 812 skb_put(skb, len + RX_PKT_OFFSET);
813 skb_pull(skb, RX_PKT_OFFSET);
1da177e4
LT		 814 } else {
815 struct sk_buff *copy_skb;
816
817 b44_recycle_rx(bp, cons, bp->rx_prod);
818 copy_skb = dev_alloc_skb(len + 2);
819 if (copy_skb == NULL)
820 goto drop_it_no_recycle;
821
1da177e4
LT		 822 skb_reserve(copy_skb, 2);
823 skb_put(copy_skb, len);
824 /* DMA sync done above, copy just the actual packet */
72f4861e 825 skb_copy_from_linear_data_offset(skb, RX_PKT_OFFSET,
d626f62b 826 copy_skb->data, len);
1da177e4
LT		 827 skb = copy_skb;
828 }
829 skb->ip_summed = CHECKSUM_NONE;
830 skb->protocol = eth_type_trans(skb, bp->dev);
831 netif_receive_skb(skb);
832 bp->dev->last_rx = jiffies;
833 received++;
834 budget--;
835 next_pkt:
836 bp->rx_prod = (bp->rx_prod + 1) &
837 (B44_RX_RING_SIZE - 1);
838 cons = (cons + 1) & (B44_RX_RING_SIZE - 1);
839 }
840
841 bp->rx_cons = cons;
842 bw32(bp, B44_DMARX_PTR, cons * sizeof(struct dma_desc));
843
844 return received;
845}
846
bea3348e 847static int b44_poll(struct napi_struct *napi, int budget)
1da177e4 848{
bea3348e
SH		 849 struct b44 *bp = container_of(napi, struct b44, napi);
850 struct net_device *netdev = bp->dev;
851 int work_done;
1da177e4
LT		 852
853 spin_lock_irq(&bp->lock);
854
855 if (bp->istat & (ISTAT_TX | ISTAT_TO)) {
856 /* spin_lock(&bp->tx_lock); */
857 b44_tx(bp);
858 /* spin_unlock(&bp->tx_lock); */
859 }
860 spin_unlock_irq(&bp->lock);
861
bea3348e
SH		 862 work_done = 0;
863 if (bp->istat & ISTAT_RX)
864 work_done += b44_rx(bp, budget);
1da177e4
LT		 865
866 if (bp->istat & ISTAT_ERRORS) {
d15e9c4d
FR		 867 unsigned long flags;
868
869 spin_lock_irqsave(&bp->lock, flags);
1da177e4
LT		 870 b44_halt(bp);
871 b44_init_rings(bp);
5fc7d61a 872 b44_init_hw(bp, B44_FULL_RESET_SKIP_PHY);
1da177e4 873 netif_wake_queue(bp->dev);
d15e9c4d 874 spin_unlock_irqrestore(&bp->lock, flags);
bea3348e 875 work_done = 0;
1da177e4
LT		 876 }
877
bea3348e
SH		 878 if (work_done < budget) {
879 netif_rx_complete(netdev, napi);
1da177e4
LT		 880 b44_enable_ints(bp);
881 }
882
bea3348e 883 return work_done;
1da177e4
LT		 884}
885
7d12e780 886static irqreturn_t b44_interrupt(int irq, void *dev_id)
1da177e4
LT		 887{
888 struct net_device *dev = dev_id;
889 struct b44 *bp = netdev_priv(dev);
1da177e4
LT		 890 u32 istat, imask;
891 int handled = 0;
892
65b984f2 893 spin_lock(&bp->lock);
1da177e4
LT		 894
895 istat = br32(bp, B44_ISTAT);
896 imask = br32(bp, B44_IMASK);
897
e78181fe
JB		 898 /* The interrupt mask register controls which interrupt bits
899 * will actually raise an interrupt to the CPU when set by hw/firmware,
900 * but doesn't mask off the bits.
1da177e4
LT		 901 */
902 istat &= imask;
903 if (istat) {
904 handled = 1;
ba5eec9c
FR		 905
906 if (unlikely(!netif_running(dev))) {
907 printk(KERN_INFO "%s: late interrupt.\n", dev->name);
908 goto irq_ack;
909 }
910
bea3348e 911 if (netif_rx_schedule_prep(dev, &bp->napi)) {
1da177e4
LT		 912 /* NOTE: These writes are posted by the readback of
913 * the ISTAT register below.
914 */
915 bp->istat = istat;
916 __b44_disable_ints(bp);
bea3348e 917 __netif_rx_schedule(dev, &bp->napi);
1da177e4
LT		 918 } else {
919 printk(KERN_ERR PFX "%s: Error, poll already scheduled\n",
920 dev->name);
921 }
922
ba5eec9c 923irq_ack:
1da177e4
LT		 924 bw32(bp, B44_ISTAT, istat);
925 br32(bp, B44_ISTAT);
926 }
65b984f2 927 spin_unlock(&bp->lock);
1da177e4
LT		 928 return IRQ_RETVAL(handled);
929}
930
931static void b44_tx_timeout(struct net_device *dev)
932{
933 struct b44 *bp = netdev_priv(dev);
934
935 printk(KERN_ERR PFX "%s: transmit timed out, resetting\n",
936 dev->name);
937
938 spin_lock_irq(&bp->lock);
939
940 b44_halt(bp);
941 b44_init_rings(bp);
5fc7d61a 942 b44_init_hw(bp, B44_FULL_RESET);
1da177e4
LT		 943
944 spin_unlock_irq(&bp->lock);
945
946 b44_enable_ints(bp);
947
948 netif_wake_queue(dev);
949}
950
951static int b44_start_xmit(struct sk_buff *skb, struct net_device *dev)
952{
953 struct b44 *bp = netdev_priv(dev);
c7193693 954 int rc = NETDEV_TX_OK;
1da177e4
LT		 955 dma_addr_t mapping;
956 u32 len, entry, ctrl;
957
958 len = skb->len;
959 spin_lock_irq(&bp->lock);
960
961 /* This is a hard error, log it. */
962 if (unlikely(TX_BUFFS_AVAIL(bp) < 1)) {
963 netif_stop_queue(dev);
1da177e4
LT		 964 printk(KERN_ERR PFX "%s: BUG! Tx Ring full when queue awake!\n",
965 dev->name);
c7193693 966 goto err_out;
1da177e4
LT		 967 }
968
f225763a
MB		 969 mapping = ssb_dma_map_single(bp->sdev, skb->data, len, DMA_TO_DEVICE);
970 if (ssb_dma_mapping_error(bp->sdev, mapping) || mapping + len > DMA_30BIT_MASK) {
f65a7177
SH		 971 struct sk_buff *bounce_skb;
972
1da177e4 973 /* Chip can't handle DMA to/from >1GB, use bounce buffer */
f225763a
MB		 974 if (!ssb_dma_mapping_error(bp->sdev, mapping))
975 ssb_dma_unmap_single(bp->sdev, mapping, len,
976 DMA_TO_DEVICE);
1da177e4 977
f65a7177 978 bounce_skb = __dev_alloc_skb(len, GFP_ATOMIC | GFP_DMA);
1da177e4 979 if (!bounce_skb)
c7193693 980 goto err_out;
1da177e4 981
f225763a
MB		 982 mapping = ssb_dma_map_single(bp->sdev, bounce_skb->data,
983 len, DMA_TO_DEVICE);
984 if (ssb_dma_mapping_error(bp->sdev, mapping) || mapping + len > DMA_30BIT_MASK) {
985 if (!ssb_dma_mapping_error(bp->sdev, mapping))
986 ssb_dma_unmap_single(bp->sdev, mapping,
987 len, DMA_TO_DEVICE);
1da177e4 988 dev_kfree_skb_any(bounce_skb);
c7193693 989 goto err_out;
1da177e4
LT		 990 }
991
f65a7177 992 skb_copy_from_linear_data(skb, skb_put(bounce_skb, len), len);
1da177e4
LT		 993 dev_kfree_skb_any(skb);
994 skb = bounce_skb;
995 }
996
997 entry = bp->tx_prod;
998 bp->tx_buffers[entry].skb = skb;
753f4920 999 bp->tx_buffers[entry].mapping = mapping;
1da177e4
LT		 1000
1001 ctrl = (len & DESC_CTRL_LEN);
1002 ctrl |= DESC_CTRL_IOC | DESC_CTRL_SOF | DESC_CTRL_EOF;
1003 if (entry == (B44_TX_RING_SIZE - 1))
1004 ctrl |= DESC_CTRL_EOT;
1005
1006 bp->tx_ring[entry].ctrl = cpu_to_le32(ctrl);
1007 bp->tx_ring[entry].addr = cpu_to_le32((u32) mapping+bp->dma_offset);
1008
9f38c636 1009 if (bp->flags & B44_FLAG_TX_RING_HACK)
753f4920
MB		 1010 b44_sync_dma_desc_for_device(bp->sdev, bp->tx_ring_dma,
1011 entry * sizeof(bp->tx_ring[0]),
1012 DMA_TO_DEVICE);
9f38c636 1013
1da177e4
LT		 1014 entry = NEXT_TX(entry);
1015
1016 bp->tx_prod = entry;
1017
1018 wmb();
1019
1020 bw32(bp, B44_DMATX_PTR, entry * sizeof(struct dma_desc));
1021 if (bp->flags & B44_FLAG_BUGGY_TXPTR)
1022 bw32(bp, B44_DMATX_PTR, entry * sizeof(struct dma_desc));
1023 if (bp->flags & B44_FLAG_REORDER_BUG)
1024 br32(bp, B44_DMATX_PTR);
1025
1026 if (TX_BUFFS_AVAIL(bp) < 1)
1027 netif_stop_queue(dev);
1028
c7193693
FR		 1029 dev->trans_start = jiffies;
1030
1031out_unlock:
1da177e4
LT		 1032 spin_unlock_irq(&bp->lock);
1033
c7193693 1034 return rc;
1da177e4 1035
c7193693
FR		 1036err_out:
1037 rc = NETDEV_TX_BUSY;
1038 goto out_unlock;
1da177e4
LT		 1039}
1040
1041static int b44_change_mtu(struct net_device *dev, int new_mtu)
1042{
1043 struct b44 *bp = netdev_priv(dev);
1044
1045 if (new_mtu < B44_MIN_MTU || new_mtu > B44_MAX_MTU)
1046 return -EINVAL;
1047
1048 if (!netif_running(dev)) {
1049 /* We'll just catch it later when the
1050 * device is up'd.
1051 */
1052 dev->mtu = new_mtu;
1053 return 0;
1054 }
1055
1056 spin_lock_irq(&bp->lock);
1057 b44_halt(bp);
1058 dev->mtu = new_mtu;
1059 b44_init_rings(bp);
5fc7d61a 1060 b44_init_hw(bp, B44_FULL_RESET);
1da177e4
LT		 1061 spin_unlock_irq(&bp->lock);
1062
1063 b44_enable_ints(bp);
10badc21 1064
1da177e4
LT		 1065 return 0;
1066}
1067
1068/* Free up pending packets in all rx/tx rings.
1069 *
1070 * The chip has been shut down and the driver detached from
1071 * the networking, so no interrupts or new tx packets will
1072 * end up in the driver. bp->lock is not held and we are not
1073 * in an interrupt context and thus may sleep.
1074 */
1075static void b44_free_rings(struct b44 *bp)
1076{
1077 struct ring_info *rp;
1078 int i;
1079
1080 for (i = 0; i < B44_RX_RING_SIZE; i++) {
1081 rp = &bp->rx_buffers[i];
1082
1083 if (rp->skb == NULL)
1084 continue;
f225763a
MB		 1085 ssb_dma_unmap_single(bp->sdev, rp->mapping, RX_PKT_BUF_SZ,
1086 DMA_FROM_DEVICE);
1da177e4
LT		 1087 dev_kfree_skb_any(rp->skb);
1088 rp->skb = NULL;
1089 }
1090
1091 /* XXX needs changes once NETIF_F_SG is set... */
1092 for (i = 0; i < B44_TX_RING_SIZE; i++) {
1093 rp = &bp->tx_buffers[i];
1094
1095 if (rp->skb == NULL)
1096 continue;
f225763a
MB		 1097 ssb_dma_unmap_single(bp->sdev, rp->mapping, rp->skb->len,
1098 DMA_TO_DEVICE);
1da177e4
LT		 1099 dev_kfree_skb_any(rp->skb);
1100 rp->skb = NULL;
1101 }
1102}
1103
1104/* Initialize tx/rx rings for packet processing.
1105 *
1106 * The chip has been shut down and the driver detached from
1107 * the networking, so no interrupts or new tx packets will
874a6214 1108 * end up in the driver.
1da177e4
LT		 1109 */
1110static void b44_init_rings(struct b44 *bp)
1111{
1112 int i;
1113
1114 b44_free_rings(bp);
1115
1116 memset(bp->rx_ring, 0, B44_RX_RING_BYTES);
1117 memset(bp->tx_ring, 0, B44_TX_RING_BYTES);
1118
9f38c636 1119 if (bp->flags & B44_FLAG_RX_RING_HACK)
f225763a
MB		 1120 ssb_dma_sync_single_for_device(bp->sdev, bp->rx_ring_dma,
1121 DMA_TABLE_BYTES,
1122 DMA_BIDIRECTIONAL);
9f38c636
JL		 1123
1124 if (bp->flags & B44_FLAG_TX_RING_HACK)
f225763a
MB		 1125 ssb_dma_sync_single_for_device(bp->sdev, bp->tx_ring_dma,
1126 DMA_TABLE_BYTES,
1127 DMA_TO_DEVICE);
9f38c636 1128
1da177e4
LT		 1129 for (i = 0; i < bp->rx_pending; i++) {
1130 if (b44_alloc_rx_skb(bp, -1, i) < 0)
1131 break;
1132 }
1133}
1134
1135/*
1136 * Must not be invoked with interrupt sources disabled and
1137 * the hardware shutdown down.
1138 */
1139static void b44_free_consistent(struct b44 *bp)
1140{
b4558ea9
JJ		 1141 kfree(bp->rx_buffers);
1142 bp->rx_buffers = NULL;
1143 kfree(bp->tx_buffers);
1144 bp->tx_buffers = NULL;
1da177e4 1145 if (bp->rx_ring) {
9f38c636 1146 if (bp->flags & B44_FLAG_RX_RING_HACK) {
f225763a
MB		 1147 ssb_dma_unmap_single(bp->sdev, bp->rx_ring_dma,
1148 DMA_TABLE_BYTES,
1149 DMA_BIDIRECTIONAL);
9f38c636
JL		 1150 kfree(bp->rx_ring);
1151 } else
f225763a
MB		 1152 ssb_dma_free_consistent(bp->sdev, DMA_TABLE_BYTES,
1153 bp->rx_ring, bp->rx_ring_dma,
1154 GFP_KERNEL);
1da177e4 1155 bp->rx_ring = NULL;
9f38c636 1156 bp->flags &= ~B44_FLAG_RX_RING_HACK;
1da177e4
LT		 1157 }
1158 if (bp->tx_ring) {
9f38c636 1159 if (bp->flags & B44_FLAG_TX_RING_HACK) {
f225763a
MB		 1160 ssb_dma_unmap_single(bp->sdev, bp->tx_ring_dma,
1161 DMA_TABLE_BYTES,
1162 DMA_TO_DEVICE);
9f38c636
JL		 1163 kfree(bp->tx_ring);
1164 } else
f225763a
MB		 1165 ssb_dma_free_consistent(bp->sdev, DMA_TABLE_BYTES,
1166 bp->tx_ring, bp->tx_ring_dma,
1167 GFP_KERNEL);
1da177e4 1168 bp->tx_ring = NULL;
9f38c636 1169 bp->flags &= ~B44_FLAG_TX_RING_HACK;
1da177e4
LT		 1170 }
1171}
1172
1173/*
1174 * Must not be invoked with interrupt sources disabled and
1175 * the hardware shutdown down. Can sleep.
1176 */
753f4920 1177static int b44_alloc_consistent(struct b44 *bp, gfp_t gfp)
1da177e4
LT		 1178{
1179 int size;
1180
1181 size = B44_RX_RING_SIZE * sizeof(struct ring_info);
753f4920 1182 bp->rx_buffers = kzalloc(size, gfp);
1da177e4
LT		 1183 if (!bp->rx_buffers)
1184 goto out_err;
1da177e4
LT		 1185
1186 size = B44_TX_RING_SIZE * sizeof(struct ring_info);
753f4920 1187 bp->tx_buffers = kzalloc(size, gfp);
1da177e4
LT		 1188 if (!bp->tx_buffers)
1189 goto out_err;
1da177e4
LT		 1190
1191 size = DMA_TABLE_BYTES;
f225763a 1192 bp->rx_ring = ssb_dma_alloc_consistent(bp->sdev, size, &bp->rx_ring_dma, gfp);
9f38c636
JL		 1193 if (!bp->rx_ring) {
1194 /* Allocation may have failed due to pci_alloc_consistent
1195 insisting on use of GFP_DMA, which is more restrictive
1196 than necessary... */
1197 struct dma_desc *rx_ring;
1198 dma_addr_t rx_ring_dma;
1199
753f4920 1200 rx_ring = kzalloc(size, gfp);
874a6214 1201 if (!rx_ring)
9f38c636
JL		 1202 goto out_err;
1203
f225763a
MB		 1204 rx_ring_dma = ssb_dma_map_single(bp->sdev, rx_ring,
1205 DMA_TABLE_BYTES,
1206 DMA_BIDIRECTIONAL);
9f38c636 1207
f225763a 1208 if (ssb_dma_mapping_error(bp->sdev, rx_ring_dma) ||
97db9ee7 1209 rx_ring_dma + size > DMA_30BIT_MASK) {
9f38c636
JL		 1210 kfree(rx_ring);
1211 goto out_err;
1212 }
1213
1214 bp->rx_ring = rx_ring;
1215 bp->rx_ring_dma = rx_ring_dma;
1216 bp->flags |= B44_FLAG_RX_RING_HACK;
1217 }
1da177e4 1218
f225763a 1219 bp->tx_ring = ssb_dma_alloc_consistent(bp->sdev, size, &bp->tx_ring_dma, gfp);
9f38c636 1220 if (!bp->tx_ring) {
f225763a 1221 /* Allocation may have failed due to ssb_dma_alloc_consistent
9f38c636
JL		 1222 insisting on use of GFP_DMA, which is more restrictive
1223 than necessary... */
1224 struct dma_desc *tx_ring;
1225 dma_addr_t tx_ring_dma;
1226
753f4920 1227 tx_ring = kzalloc(size, gfp);
874a6214 1228 if (!tx_ring)
9f38c636
JL		 1229 goto out_err;
1230
f225763a 1231 tx_ring_dma = ssb_dma_map_single(bp->sdev, tx_ring,
753f4920
MB		 1232 DMA_TABLE_BYTES,
1233 DMA_TO_DEVICE);
9f38c636 1234
f225763a 1235 if (ssb_dma_mapping_error(bp->sdev, tx_ring_dma) ||
97db9ee7 1236 tx_ring_dma + size > DMA_30BIT_MASK) {
9f38c636
JL		 1237 kfree(tx_ring);
1238 goto out_err;
1239 }
1240
1241 bp->tx_ring = tx_ring;
1242 bp->tx_ring_dma = tx_ring_dma;
1243 bp->flags |= B44_FLAG_TX_RING_HACK;
1244 }
1da177e4
LT		 1245
1246 return 0;
1247
1248out_err:
1249 b44_free_consistent(bp);
1250 return -ENOMEM;
1251}
1252
1253/* bp->lock is held. */
1254static void b44_clear_stats(struct b44 *bp)
1255{
1256 unsigned long reg;
1257
1258 bw32(bp, B44_MIB_CTRL, MIB_CTRL_CLR_ON_READ);
1259 for (reg = B44_TX_GOOD_O; reg <= B44_TX_PAUSE; reg += 4UL)
1260 br32(bp, reg);
1261 for (reg = B44_RX_GOOD_O; reg <= B44_RX_NPAUSE; reg += 4UL)
1262 br32(bp, reg);
1263}
1264
1265/* bp->lock is held. */
fedb0eef 1266static void b44_chip_reset(struct b44 *bp, int reset_kind)
1da177e4 1267{
753f4920
MB		 1268 struct ssb_device *sdev = bp->sdev;
1269
1270 if (ssb_device_is_enabled(bp->sdev)) {
1da177e4
LT		 1271 bw32(bp, B44_RCV_LAZY, 0);
1272 bw32(bp, B44_ENET_CTRL, ENET_CTRL_DISABLE);
40ee8c76 1273 b44_wait_bit(bp, B44_ENET_CTRL, ENET_CTRL_DISABLE, 200, 1);
1da177e4
LT		 1274 bw32(bp, B44_DMATX_CTRL, 0);
1275 bp->tx_prod = bp->tx_cons = 0;
1276 if (br32(bp, B44_DMARX_STAT) & DMARX_STAT_EMASK) {
1277 b44_wait_bit(bp, B44_DMARX_STAT, DMARX_STAT_SIDLE,
1278 100, 0);
1279 }
1280 bw32(bp, B44_DMARX_CTRL, 0);
1281 bp->rx_prod = bp->rx_cons = 0;
753f4920
MB		 1282 } else
1283 ssb_pcicore_dev_irqvecs_enable(&sdev->bus->pcicore, sdev);
1da177e4 1284
753f4920 1285 ssb_device_enable(bp->sdev, 0);
1da177e4
LT		 1286 b44_clear_stats(bp);
1287
fedb0eef
MB		 1288 /*
1289 * Don't enable PHY if we are doing a partial reset
1290 * we are probably going to power down
1291 */
1292 if (reset_kind == B44_CHIP_RESET_PARTIAL)
1293 return;
1294
753f4920
MB		 1295 switch (sdev->bus->bustype) {
1296 case SSB_BUSTYPE_SSB:
1297 bw32(bp, B44_MDIO_CTRL, (MDIO_CTRL_PREAMBLE |
1298 (((ssb_clockspeed(sdev->bus) + (B44_MDC_RATIO / 2)) / B44_MDC_RATIO)
1299 & MDIO_CTRL_MAXF_MASK)));
1300 break;
1301 case SSB_BUSTYPE_PCI:
1302 case SSB_BUSTYPE_PCMCIA:
1303 bw32(bp, B44_MDIO_CTRL, (MDIO_CTRL_PREAMBLE |
1304 (0x0d & MDIO_CTRL_MAXF_MASK)));
1305 break;
1306 }
1307
1da177e4
LT		 1308 br32(bp, B44_MDIO_CTRL);
1309
1310 if (!(br32(bp, B44_DEVCTRL) & DEVCTRL_IPP)) {
1311 bw32(bp, B44_ENET_CTRL, ENET_CTRL_EPSEL);
1312 br32(bp, B44_ENET_CTRL);
1313 bp->flags &= ~B44_FLAG_INTERNAL_PHY;
1314 } else {
1315 u32 val = br32(bp, B44_DEVCTRL);
1316
1317 if (val & DEVCTRL_EPR) {
1318 bw32(bp, B44_DEVCTRL, (val & ~DEVCTRL_EPR));
1319 br32(bp, B44_DEVCTRL);
1320 udelay(100);
1321 }
1322 bp->flags |= B44_FLAG_INTERNAL_PHY;
1323 }
1324}
1325
1326/* bp->lock is held. */
1327static void b44_halt(struct b44 *bp)
1328{
1329 b44_disable_ints(bp);
fedb0eef
MB		 1330 /* reset PHY */
1331 b44_phy_reset(bp);
1332 /* power down PHY */
1333 printk(KERN_INFO PFX "%s: powering down PHY\n", bp->dev->name);
1334 bw32(bp, B44_MAC_CTRL, MAC_CTRL_PHY_PDOWN);
1335 /* now reset the chip, but without enabling the MAC&PHY
1336 * part of it. This has to be done _after_ we shut down the PHY */
1337 b44_chip_reset(bp, B44_CHIP_RESET_PARTIAL);
1da177e4
LT		 1338}
1339
1340/* bp->lock is held. */
1341static void __b44_set_mac_addr(struct b44 *bp)
1342{
1343 bw32(bp, B44_CAM_CTRL, 0);
1344 if (!(bp->dev->flags & IFF_PROMISC)) {
1345 u32 val;
1346
1347 __b44_cam_write(bp, bp->dev->dev_addr, 0);
1348 val = br32(bp, B44_CAM_CTRL);
1349 bw32(bp, B44_CAM_CTRL, val | CAM_CTRL_ENABLE);
1350 }
1351}
1352
1353static int b44_set_mac_addr(struct net_device *dev, void *p)
1354{
1355 struct b44 *bp = netdev_priv(dev);
1356 struct sockaddr *addr = p;
753f4920 1357 u32 val;
1da177e4
LT		 1358
1359 if (netif_running(dev))
1360 return -EBUSY;
1361
391fc09a
GZ		 1362 if (!is_valid_ether_addr(addr->sa_data))
1363 return -EINVAL;
1364
1da177e4
LT		 1365 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
1366
1367 spin_lock_irq(&bp->lock);
753f4920
MB		 1368
1369 val = br32(bp, B44_RXCONFIG);
1370 if (!(val & RXCONFIG_CAM_ABSENT))
1371 __b44_set_mac_addr(bp);
1372
1da177e4
LT		 1373 spin_unlock_irq(&bp->lock);
1374
1375 return 0;
1376}
1377
1378/* Called at device open time to get the chip ready for
1379 * packet processing. Invoked with bp->lock held.
1380 */
1381static void __b44_set_rx_mode(struct net_device *);
5fc7d61a 1382static void b44_init_hw(struct b44 *bp, int reset_kind)
1da177e4
LT		 1383{
1384 u32 val;
1385
fedb0eef 1386 b44_chip_reset(bp, B44_CHIP_RESET_FULL);
5fc7d61a 1387 if (reset_kind == B44_FULL_RESET) {
00e8b3aa
GZ		 1388 b44_phy_reset(bp);
1389 b44_setup_phy(bp);
1390 }
1da177e4
LT		 1391
1392 /* Enable CRC32, set proper LED modes and power on PHY */
1393 bw32(bp, B44_MAC_CTRL, MAC_CTRL_CRC32_ENAB | MAC_CTRL_PHY_LEDCTRL);
1394 bw32(bp, B44_RCV_LAZY, (1 << RCV_LAZY_FC_SHIFT));
1395
1396 /* This sets the MAC address too. */
1397 __b44_set_rx_mode(bp->dev);
1398
1399 /* MTU + eth header + possible VLAN tag + struct rx_header */
1400 bw32(bp, B44_RXMAXLEN, bp->dev->mtu + ETH_HLEN + 8 + RX_HEADER_LEN);
1401 bw32(bp, B44_TXMAXLEN, bp->dev->mtu + ETH_HLEN + 8 + RX_HEADER_LEN);
1402
1403 bw32(bp, B44_TX_WMARK, 56); /* XXX magic */
5fc7d61a
MC		 1404 if (reset_kind == B44_PARTIAL_RESET) {
1405 bw32(bp, B44_DMARX_CTRL, (DMARX_CTRL_ENABLE |
72f4861e 1406 (RX_PKT_OFFSET << DMARX_CTRL_ROSHIFT)));
5fc7d61a 1407 } else {
00e8b3aa
GZ		 1408 bw32(bp, B44_DMATX_CTRL, DMATX_CTRL_ENABLE);
1409 bw32(bp, B44_DMATX_ADDR, bp->tx_ring_dma + bp->dma_offset);
1410 bw32(bp, B44_DMARX_CTRL, (DMARX_CTRL_ENABLE |
72f4861e 1411 (RX_PKT_OFFSET << DMARX_CTRL_ROSHIFT)));
00e8b3aa 1412 bw32(bp, B44_DMARX_ADDR, bp->rx_ring_dma + bp->dma_offset);
1da177e4 1413
00e8b3aa
GZ		 1414 bw32(bp, B44_DMARX_PTR, bp->rx_pending);
1415 bp->rx_prod = bp->rx_pending;
1da177e4 1416
00e8b3aa 1417 bw32(bp, B44_MIB_CTRL, MIB_CTRL_CLR_ON_READ);
00e8b3aa 1418 }
1da177e4
LT		 1419
1420 val = br32(bp, B44_ENET_CTRL);
1421 bw32(bp, B44_ENET_CTRL, (val | ENET_CTRL_ENABLE));
1422}
1423
1424static int b44_open(struct net_device *dev)
1425{
1426 struct b44 *bp = netdev_priv(dev);
1427 int err;
1428
753f4920 1429 err = b44_alloc_consistent(bp, GFP_KERNEL);
1da177e4 1430 if (err)
6c2f4267 1431 goto out;
1da177e4 1432
bea3348e
SH		 1433 napi_enable(&bp->napi);
1434
1da177e4 1435 b44_init_rings(bp);
5fc7d61a 1436 b44_init_hw(bp, B44_FULL_RESET);
1da177e4 1437
e254e9bf
JL		 1438 b44_check_phy(bp);
1439
1fb9df5d 1440 err = request_irq(dev->irq, b44_interrupt, IRQF_SHARED, dev->name, dev);
6c2f4267 1441 if (unlikely(err < 0)) {
bea3348e 1442 napi_disable(&bp->napi);
fedb0eef 1443 b44_chip_reset(bp, B44_CHIP_RESET_PARTIAL);
6c2f4267
FR		 1444 b44_free_rings(bp);
1445 b44_free_consistent(bp);
1446 goto out;
1447 }
1da177e4
LT		 1448
1449 init_timer(&bp->timer);
1450 bp->timer.expires = jiffies + HZ;
1451 bp->timer.data = (unsigned long) bp;
1452 bp->timer.function = b44_timer;
1453 add_timer(&bp->timer);
1454
1455 b44_enable_ints(bp);
d9e2d185 1456 netif_start_queue(dev);
6c2f4267 1457out:
1da177e4
LT		 1458 return err;
1459}
1460
1da177e4
LT		 1461#ifdef CONFIG_NET_POLL_CONTROLLER
1462/*
1463 * Polling receive - used by netconsole and other diagnostic tools
1464 * to allow network i/o with interrupts disabled.
1465 */
1466static void b44_poll_controller(struct net_device *dev)
1467{
1468 disable_irq(dev->irq);
7d12e780 1469 b44_interrupt(dev->irq, dev);
1da177e4
LT		 1470 enable_irq(dev->irq);
1471}
1472#endif
1473
725ad800
GZ		 1474static void bwfilter_table(struct b44 *bp, u8 *pp, u32 bytes, u32 table_offset)
1475{
1476 u32 i;
1477 u32 *pattern = (u32 *) pp;
1478
1479 for (i = 0; i < bytes; i += sizeof(u32)) {
1480 bw32(bp, B44_FILT_ADDR, table_offset + i);
1481 bw32(bp, B44_FILT_DATA, pattern[i / sizeof(u32)]);
1482 }
1483}
1484
1485static int b44_magic_pattern(u8 *macaddr, u8 *ppattern, u8 *pmask, int offset)
1486{
1487 int magicsync = 6;
1488 int k, j, len = offset;
1489 int ethaddr_bytes = ETH_ALEN;
1490
1491 memset(ppattern + offset, 0xff, magicsync);
1492 for (j = 0; j < magicsync; j++)
1493 set_bit(len++, (unsigned long *) pmask);
1494
1495 for (j = 0; j < B44_MAX_PATTERNS; j++) {
1496 if ((B44_PATTERN_SIZE - len) >= ETH_ALEN)
1497 ethaddr_bytes = ETH_ALEN;
1498 else
1499 ethaddr_bytes = B44_PATTERN_SIZE - len;
1500 if (ethaddr_bytes <=0)
1501 break;
1502 for (k = 0; k< ethaddr_bytes; k++) {
1503 ppattern[offset + magicsync +
1504 (j * ETH_ALEN) + k] = macaddr[k];
1505 len++;
1506 set_bit(len, (unsigned long *) pmask);
1507 }
1508 }
1509 return len - 1;
1510}
1511
1512/* Setup magic packet patterns in the b44 WOL
1513 * pattern matching filter.
1514 */
1515static void b44_setup_pseudo_magicp(struct b44 *bp)
1516{
1517
1518 u32 val;
1519 int plen0, plen1, plen2;
1520 u8 *pwol_pattern;
1521 u8 pwol_mask[B44_PMASK_SIZE];
1522
dd00cc48 1523 pwol_pattern = kzalloc(B44_PATTERN_SIZE, GFP_KERNEL);
725ad800
GZ		 1524 if (!pwol_pattern) {
1525 printk(KERN_ERR PFX "Memory not available for WOL\n");
1526 return;
1527 }
1528
1529 /* Ipv4 magic packet pattern - pattern 0.*/
725ad800
GZ		 1530 memset(pwol_mask, 0, B44_PMASK_SIZE);
1531 plen0 = b44_magic_pattern(bp->dev->dev_addr, pwol_pattern, pwol_mask,
1532 B44_ETHIPV4UDP_HLEN);
1533
1534 bwfilter_table(bp, pwol_pattern, B44_PATTERN_SIZE, B44_PATTERN_BASE);
1535 bwfilter_table(bp, pwol_mask, B44_PMASK_SIZE, B44_PMASK_BASE);
1536
1537 /* Raw ethernet II magic packet pattern - pattern 1 */
1538 memset(pwol_pattern, 0, B44_PATTERN_SIZE);
1539 memset(pwol_mask, 0, B44_PMASK_SIZE);
1540 plen1 = b44_magic_pattern(bp->dev->dev_addr, pwol_pattern, pwol_mask,
1541 ETH_HLEN);
1542
1543 bwfilter_table(bp, pwol_pattern, B44_PATTERN_SIZE,
1544 B44_PATTERN_BASE + B44_PATTERN_SIZE);
1545 bwfilter_table(bp, pwol_mask, B44_PMASK_SIZE,
1546 B44_PMASK_BASE + B44_PMASK_SIZE);
1547
1548 /* Ipv6 magic packet pattern - pattern 2 */
1549 memset(pwol_pattern, 0, B44_PATTERN_SIZE);
1550 memset(pwol_mask, 0, B44_PMASK_SIZE);
1551 plen2 = b44_magic_pattern(bp->dev->dev_addr, pwol_pattern, pwol_mask,
1552 B44_ETHIPV6UDP_HLEN);
1553
1554 bwfilter_table(bp, pwol_pattern, B44_PATTERN_SIZE,
1555 B44_PATTERN_BASE + B44_PATTERN_SIZE + B44_PATTERN_SIZE);
1556 bwfilter_table(bp, pwol_mask, B44_PMASK_SIZE,
1557 B44_PMASK_BASE + B44_PMASK_SIZE + B44_PMASK_SIZE);
1558
1559 kfree(pwol_pattern);
1560
1561 /* set these pattern's lengths: one less than each real length */
1562 val = plen0 | (plen1 << 8) | (plen2 << 16) | WKUP_LEN_ENABLE_THREE;
1563 bw32(bp, B44_WKUP_LEN, val);
1564
1565 /* enable wakeup pattern matching */
1566 val = br32(bp, B44_DEVCTRL);
1567 bw32(bp, B44_DEVCTRL, val | DEVCTRL_PFE);
1568
1569}
52cafd96 1570
753f4920
MB		 1571#ifdef CONFIG_B44_PCI
1572static void b44_setup_wol_pci(struct b44 *bp)
1573{
1574 u16 val;
1575
1576 if (bp->sdev->bus->bustype != SSB_BUSTYPE_SSB) {
1577 bw32(bp, SSB_TMSLOW, br32(bp, SSB_TMSLOW) | SSB_TMSLOW_PE);
1578 pci_read_config_word(bp->sdev->bus->host_pci, SSB_PMCSR, &val);
1579 pci_write_config_word(bp->sdev->bus->host_pci, SSB_PMCSR, val | SSB_PE);
1580 }
1581}
1582#else
1583static inline void b44_setup_wol_pci(struct b44 *bp) { }
1584#endif /* CONFIG_B44_PCI */
1585
52cafd96
GZ		 1586static void b44_setup_wol(struct b44 *bp)
1587{
1588 u32 val;
52cafd96
GZ		 1589
1590 bw32(bp, B44_RXCONFIG, RXCONFIG_ALLMULTI);
1591
1592 if (bp->flags & B44_FLAG_B0_ANDLATER) {
1593
1594 bw32(bp, B44_WKUP_LEN, WKUP_LEN_DISABLE);
1595
1596 val = bp->dev->dev_addr[2] << 24 |
1597 bp->dev->dev_addr[3] << 16 |
1598 bp->dev->dev_addr[4] << 8 |
1599 bp->dev->dev_addr[5];
1600 bw32(bp, B44_ADDR_LO, val);
1601
1602 val = bp->dev->dev_addr[0] << 8 |
1603 bp->dev->dev_addr[1];
1604 bw32(bp, B44_ADDR_HI, val);
1605
1606 val = br32(bp, B44_DEVCTRL);
1607 bw32(bp, B44_DEVCTRL, val | DEVCTRL_MPM | DEVCTRL_PFE);
1608
725ad800
GZ		 1609 } else {
1610 b44_setup_pseudo_magicp(bp);
1611 }
753f4920 1612 b44_setup_wol_pci(bp);
52cafd96
GZ		 1613}
1614
1da177e4
LT		 1615static int b44_close(struct net_device *dev)
1616{
1617 struct b44 *bp = netdev_priv(dev);
1618
1619 netif_stop_queue(dev);
1620
bea3348e 1621 napi_disable(&bp->napi);
ba5eec9c 1622
1da177e4
LT		 1623 del_timer_sync(&bp->timer);
1624
1625 spin_lock_irq(&bp->lock);
1626
1da177e4
LT		 1627 b44_halt(bp);
1628 b44_free_rings(bp);
c35ca399 1629 netif_carrier_off(dev);
1da177e4
LT		 1630
1631 spin_unlock_irq(&bp->lock);
1632
1633 free_irq(dev->irq, dev);
1634
52cafd96 1635 if (bp->flags & B44_FLAG_WOL_ENABLE) {
5fc7d61a 1636 b44_init_hw(bp, B44_PARTIAL_RESET);
52cafd96
GZ		 1637 b44_setup_wol(bp);
1638 }
1639
1da177e4
LT		 1640 b44_free_consistent(bp);
1641
1642 return 0;
1643}
1644
1645static struct net_device_stats *b44_get_stats(struct net_device *dev)
1646{
1647 struct b44 *bp = netdev_priv(dev);
1648 struct net_device_stats *nstat = &bp->stats;
1649 struct b44_hw_stats *hwstat = &bp->hw_stats;
1650
1651 /* Convert HW stats into netdevice stats. */
1652 nstat->rx_packets = hwstat->rx_pkts;
1653 nstat->tx_packets = hwstat->tx_pkts;
1654 nstat->rx_bytes = hwstat->rx_octets;
1655 nstat->tx_bytes = hwstat->tx_octets;
1656 nstat->tx_errors = (hwstat->tx_jabber_pkts +
1657 hwstat->tx_oversize_pkts +
1658 hwstat->tx_underruns +
1659 hwstat->tx_excessive_cols +
1660 hwstat->tx_late_cols);
1661 nstat->multicast = hwstat->tx_multicast_pkts;
1662 nstat->collisions = hwstat->tx_total_cols;
1663
1664 nstat->rx_length_errors = (hwstat->rx_oversize_pkts +
1665 hwstat->rx_undersize);
1666 nstat->rx_over_errors = hwstat->rx_missed_pkts;
1667 nstat->rx_frame_errors = hwstat->rx_align_errs;
1668 nstat->rx_crc_errors = hwstat->rx_crc_errs;
1669 nstat->rx_errors = (hwstat->rx_jabber_pkts +
1670 hwstat->rx_oversize_pkts +
1671 hwstat->rx_missed_pkts +
1672 hwstat->rx_crc_align_errs +
1673 hwstat->rx_undersize +
1674 hwstat->rx_crc_errs +
1675 hwstat->rx_align_errs +
1676 hwstat->rx_symbol_errs);
1677
1678 nstat->tx_aborted_errors = hwstat->tx_underruns;
1679#if 0
1680 /* Carrier lost counter seems to be broken for some devices */
1681 nstat->tx_carrier_errors = hwstat->tx_carrier_lost;
1682#endif
1683
1684 return nstat;
1685}
1686
1687static int __b44_load_mcast(struct b44 *bp, struct net_device *dev)
1688{
1689 struct dev_mc_list *mclist;
1690 int i, num_ents;
1691
1692 num_ents = min_t(int, dev->mc_count, B44_MCAST_TABLE_SIZE);
1693 mclist = dev->mc_list;
1694 for (i = 0; mclist && i < num_ents; i++, mclist = mclist->next) {
1695 __b44_cam_write(bp, mclist->dmi_addr, i + 1);
1696 }
1697 return i+1;
1698}
1699
1700static void __b44_set_rx_mode(struct net_device *dev)
1701{
1702 struct b44 *bp = netdev_priv(dev);
1703 u32 val;
1da177e4
LT		 1704
1705 val = br32(bp, B44_RXCONFIG);
1706 val &= ~(RXCONFIG_PROMISC | RXCONFIG_ALLMULTI);
753f4920 1707 if ((dev->flags & IFF_PROMISC) || (val & RXCONFIG_CAM_ABSENT)) {
1da177e4
LT		 1708 val |= RXCONFIG_PROMISC;
1709 bw32(bp, B44_RXCONFIG, val);
1710 } else {
874a6214 1711 unsigned char zero[6] = {0, 0, 0, 0, 0, 0};
cda22aa9 1712 int i = 1;
874a6214 1713
1da177e4
LT		 1714 __b44_set_mac_addr(bp);
1715
2f614fe0
JG		 1716 if ((dev->flags & IFF_ALLMULTI) ||
1717 (dev->mc_count > B44_MCAST_TABLE_SIZE))
1da177e4
LT		 1718 val |= RXCONFIG_ALLMULTI;
1719 else
874a6214 1720 i = __b44_load_mcast(bp, dev);
10badc21 1721
2f614fe0 1722 for (; i < 64; i++)
10badc21 1723 __b44_cam_write(bp, zero, i);
2f614fe0 1724
1da177e4
LT		 1725 bw32(bp, B44_RXCONFIG, val);
1726 val = br32(bp, B44_CAM_CTRL);
1727 bw32(bp, B44_CAM_CTRL, val | CAM_CTRL_ENABLE);
1728 }
1729}
1730
1731static void b44_set_rx_mode(struct net_device *dev)
1732{
1733 struct b44 *bp = netdev_priv(dev);
1734
1735 spin_lock_irq(&bp->lock);
1736 __b44_set_rx_mode(dev);
1737 spin_unlock_irq(&bp->lock);
1738}
1739
1740static u32 b44_get_msglevel(struct net_device *dev)
1741{
1742 struct b44 *bp = netdev_priv(dev);
1743 return bp->msg_enable;
1744}
1745
1746static void b44_set_msglevel(struct net_device *dev, u32 value)
1747{
1748 struct b44 *bp = netdev_priv(dev);
1749 bp->msg_enable = value;
1750}
1751
1752static void b44_get_drvinfo (struct net_device *dev, struct ethtool_drvinfo *info)
1753{
1754 struct b44 *bp = netdev_priv(dev);
753f4920 1755 struct ssb_bus *bus = bp->sdev->bus;
1da177e4 1756
753f4920
MB		 1757 strncpy(info->driver, DRV_MODULE_NAME, sizeof(info->driver));
1758 strncpy(info->version, DRV_MODULE_VERSION, sizeof(info->driver));
1759 switch (bus->bustype) {
1760 case SSB_BUSTYPE_PCI:
1761 strncpy(info->bus_info, pci_name(bus->host_pci), sizeof(info->bus_info));
1762 break;
1763 case SSB_BUSTYPE_PCMCIA:
1764 case SSB_BUSTYPE_SSB:
1765 strncpy(info->bus_info, "SSB", sizeof(info->bus_info));
1766 break;
1767 }
1da177e4
LT		 1768}
1769
1770static int b44_nway_reset(struct net_device *dev)
1771{
1772 struct b44 *bp = netdev_priv(dev);
1773 u32 bmcr;
1774 int r;
1775
1776 spin_lock_irq(&bp->lock);
1777 b44_readphy(bp, MII_BMCR, &bmcr);
1778 b44_readphy(bp, MII_BMCR, &bmcr);
1779 r = -EINVAL;
1780 if (bmcr & BMCR_ANENABLE) {
1781 b44_writephy(bp, MII_BMCR,
1782 bmcr | BMCR_ANRESTART);
1783 r = 0;
1784 }
1785 spin_unlock_irq(&bp->lock);
1786
1787 return r;
1788}
1789
1790static int b44_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1791{
1792 struct b44 *bp = netdev_priv(dev);
1793
1da177e4
LT		 1794 cmd->supported = (SUPPORTED_Autoneg);
1795 cmd->supported |= (SUPPORTED_100baseT_Half |
1796 SUPPORTED_100baseT_Full |
1797 SUPPORTED_10baseT_Half |
1798 SUPPORTED_10baseT_Full |
1799 SUPPORTED_MII);
1800
1801 cmd->advertising = 0;
1802 if (bp->flags & B44_FLAG_ADV_10HALF)
adf6e000 1803 cmd->advertising |= ADVERTISED_10baseT_Half;
1da177e4 1804 if (bp->flags & B44_FLAG_ADV_10FULL)
adf6e000 1805 cmd->advertising |= ADVERTISED_10baseT_Full;
1da177e4 1806 if (bp->flags & B44_FLAG_ADV_100HALF)
adf6e000 1807 cmd->advertising |= ADVERTISED_100baseT_Half;
1da177e4 1808 if (bp->flags & B44_FLAG_ADV_100FULL)
adf6e000
MW		 1809 cmd->advertising |= ADVERTISED_100baseT_Full;
1810 cmd->advertising |= ADVERTISED_Pause | ADVERTISED_Asym_Pause;
1da177e4
LT		 1811 cmd->speed = (bp->flags & B44_FLAG_100_BASE_T) ?
1812 SPEED_100 : SPEED_10;
1813 cmd->duplex = (bp->flags & B44_FLAG_FULL_DUPLEX) ?
1814 DUPLEX_FULL : DUPLEX_HALF;
1815 cmd->port = 0;
1816 cmd->phy_address = bp->phy_addr;
1817 cmd->transceiver = (bp->flags & B44_FLAG_INTERNAL_PHY) ?
1818 XCVR_INTERNAL : XCVR_EXTERNAL;
1819 cmd->autoneg = (bp->flags & B44_FLAG_FORCE_LINK) ?
1820 AUTONEG_DISABLE : AUTONEG_ENABLE;
47b9c3b1
GZ		 1821 if (cmd->autoneg == AUTONEG_ENABLE)
1822 cmd->advertising |= ADVERTISED_Autoneg;
1823 if (!netif_running(dev)){
1824 cmd->speed = 0;
1825 cmd->duplex = 0xff;
1826 }
1da177e4
LT		 1827 cmd->maxtxpkt = 0;
1828 cmd->maxrxpkt = 0;
1829 return 0;
1830}
1831
1832static int b44_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1833{
1834 struct b44 *bp = netdev_priv(dev);
1835
1da177e4
LT		 1836 /* We do not support gigabit. */
1837 if (cmd->autoneg == AUTONEG_ENABLE) {
1838 if (cmd->advertising &
1839 (ADVERTISED_1000baseT_Half |
1840 ADVERTISED_1000baseT_Full))
1841 return -EINVAL;
1842 } else if ((cmd->speed != SPEED_100 &&
1843 cmd->speed != SPEED_10) ||
1844 (cmd->duplex != DUPLEX_HALF &&
1845 cmd->duplex != DUPLEX_FULL)) {
1846 return -EINVAL;
1847 }
1848
1849 spin_lock_irq(&bp->lock);
1850
1851 if (cmd->autoneg == AUTONEG_ENABLE) {
47b9c3b1
GZ		 1852 bp->flags &= ~(B44_FLAG_FORCE_LINK |
1853 B44_FLAG_100_BASE_T |
1854 B44_FLAG_FULL_DUPLEX |
1855 B44_FLAG_ADV_10HALF |
1da177e4
LT		 1856 B44_FLAG_ADV_10FULL |
1857 B44_FLAG_ADV_100HALF |
1858 B44_FLAG_ADV_100FULL);
47b9c3b1
GZ		 1859 if (cmd->advertising == 0) {
1860 bp->flags |= (B44_FLAG_ADV_10HALF |
1861 B44_FLAG_ADV_10FULL |
1862 B44_FLAG_ADV_100HALF |
1863 B44_FLAG_ADV_100FULL);
1864 } else {
1865 if (cmd->advertising & ADVERTISED_10baseT_Half)
1866 bp->flags |= B44_FLAG_ADV_10HALF;
1867 if (cmd->advertising & ADVERTISED_10baseT_Full)
1868 bp->flags |= B44_FLAG_ADV_10FULL;
1869 if (cmd->advertising & ADVERTISED_100baseT_Half)
1870 bp->flags |= B44_FLAG_ADV_100HALF;
1871 if (cmd->advertising & ADVERTISED_100baseT_Full)
1872 bp->flags |= B44_FLAG_ADV_100FULL;
1873 }
1da177e4
LT		 1874 } else {
1875 bp->flags |= B44_FLAG_FORCE_LINK;
47b9c3b1 1876 bp->flags &= ~(B44_FLAG_100_BASE_T | B44_FLAG_FULL_DUPLEX);
1da177e4
LT		 1877 if (cmd->speed == SPEED_100)
1878 bp->flags |= B44_FLAG_100_BASE_T;
1879 if (cmd->duplex == DUPLEX_FULL)
1880 bp->flags |= B44_FLAG_FULL_DUPLEX;
1881 }
1882
47b9c3b1
GZ		 1883 if (netif_running(dev))
1884 b44_setup_phy(bp);
1da177e4
LT		 1885
1886 spin_unlock_irq(&bp->lock);
1887
1888 return 0;
1889}
1890
1891static void b44_get_ringparam(struct net_device *dev,
1892 struct ethtool_ringparam *ering)
1893{
1894 struct b44 *bp = netdev_priv(dev);
1895
1896 ering->rx_max_pending = B44_RX_RING_SIZE - 1;
1897 ering->rx_pending = bp->rx_pending;
1898
1899 /* XXX ethtool lacks a tx_max_pending, oops... */
1900}
1901
1902static int b44_set_ringparam(struct net_device *dev,
1903 struct ethtool_ringparam *ering)
1904{
1905 struct b44 *bp = netdev_priv(dev);
1906
1907 if ((ering->rx_pending > B44_RX_RING_SIZE - 1) ||
1908 (ering->rx_mini_pending != 0) ||
1909 (ering->rx_jumbo_pending != 0) ||
1910 (ering->tx_pending > B44_TX_RING_SIZE - 1))
1911 return -EINVAL;
1912
1913 spin_lock_irq(&bp->lock);
1914
1915 bp->rx_pending = ering->rx_pending;
1916 bp->tx_pending = ering->tx_pending;
1917
1918 b44_halt(bp);
1919 b44_init_rings(bp);
5fc7d61a 1920 b44_init_hw(bp, B44_FULL_RESET);
1da177e4
LT		 1921 netif_wake_queue(bp->dev);
1922 spin_unlock_irq(&bp->lock);
1923
1924 b44_enable_ints(bp);
10badc21 1925
1da177e4
LT		 1926 return 0;
1927}
1928
1929static void b44_get_pauseparam(struct net_device *dev,
1930 struct ethtool_pauseparam *epause)
1931{
1932 struct b44 *bp = netdev_priv(dev);
1933
1934 epause->autoneg =
1935 (bp->flags & B44_FLAG_PAUSE_AUTO) != 0;
1936 epause->rx_pause =
1937 (bp->flags & B44_FLAG_RX_PAUSE) != 0;
1938 epause->tx_pause =
1939 (bp->flags & B44_FLAG_TX_PAUSE) != 0;
1940}
1941
1942static int b44_set_pauseparam(struct net_device *dev,
1943 struct ethtool_pauseparam *epause)
1944{
1945 struct b44 *bp = netdev_priv(dev);
1946
1947 spin_lock_irq(&bp->lock);
1948 if (epause->autoneg)
1949 bp->flags |= B44_FLAG_PAUSE_AUTO;
1950 else
1951 bp->flags &= ~B44_FLAG_PAUSE_AUTO;
1952 if (epause->rx_pause)
1953 bp->flags |= B44_FLAG_RX_PAUSE;
1954 else
1955 bp->flags &= ~B44_FLAG_RX_PAUSE;
1956 if (epause->tx_pause)
1957 bp->flags |= B44_FLAG_TX_PAUSE;
1958 else
1959 bp->flags &= ~B44_FLAG_TX_PAUSE;
1960 if (bp->flags & B44_FLAG_PAUSE_AUTO) {
1961 b44_halt(bp);
1962 b44_init_rings(bp);
5fc7d61a 1963 b44_init_hw(bp, B44_FULL_RESET);
1da177e4
LT		 1964 } else {
1965 __b44_set_flow_ctrl(bp, bp->flags);
1966 }
1967 spin_unlock_irq(&bp->lock);
1968
1969 b44_enable_ints(bp);
10badc21 1970
1da177e4
LT		 1971 return 0;
1972}
1973
3353930d
FR		 1974static void b44_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1975{
1976 switch(stringset) {
1977 case ETH_SS_STATS:
1978 memcpy(data, *b44_gstrings, sizeof(b44_gstrings));
1979 break;
1980 }
1981}
1982
b9f2c044 1983static int b44_get_sset_count(struct net_device *dev, int sset)
3353930d 1984{
b9f2c044
JG		 1985 switch (sset) {
1986 case ETH_SS_STATS:
1987 return ARRAY_SIZE(b44_gstrings);
1988 default:
1989 return -EOPNOTSUPP;
1990 }
3353930d
FR		 1991}
1992
1993static void b44_get_ethtool_stats(struct net_device *dev,
1994 struct ethtool_stats *stats, u64 *data)
1995{
1996 struct b44 *bp = netdev_priv(dev);
1997 u32 *val = &bp->hw_stats.tx_good_octets;
1998 u32 i;
1999
2000 spin_lock_irq(&bp->lock);
2001
2002 b44_stats_update(bp);
2003
2004 for (i = 0; i < ARRAY_SIZE(b44_gstrings); i++)
2005 *data++ = *val++;
2006
2007 spin_unlock_irq(&bp->lock);
2008}
2009
52cafd96
GZ		 2010static void b44_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2011{
2012 struct b44 *bp = netdev_priv(dev);
2013
2014 wol->supported = WAKE_MAGIC;
2015 if (bp->flags & B44_FLAG_WOL_ENABLE)
2016 wol->wolopts = WAKE_MAGIC;
2017 else
2018 wol->wolopts = 0;
2019 memset(&wol->sopass, 0, sizeof(wol->sopass));
2020}
2021
2022static int b44_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2023{
2024 struct b44 *bp = netdev_priv(dev);
2025
2026 spin_lock_irq(&bp->lock);
2027 if (wol->wolopts & WAKE_MAGIC)
2028 bp->flags |= B44_FLAG_WOL_ENABLE;
2029 else
2030 bp->flags &= ~B44_FLAG_WOL_ENABLE;
2031 spin_unlock_irq(&bp->lock);
2032
2033 return 0;
2034}
2035
7282d491 2036static const struct ethtool_ops b44_ethtool_ops = {
1da177e4
LT		 2037 .get_drvinfo = b44_get_drvinfo,
2038 .get_settings = b44_get_settings,
2039 .set_settings = b44_set_settings,
2040 .nway_reset = b44_nway_reset,
2041 .get_link = ethtool_op_get_link,
52cafd96
GZ		 2042 .get_wol = b44_get_wol,
2043 .set_wol = b44_set_wol,
1da177e4
LT		 2044 .get_ringparam = b44_get_ringparam,
2045 .set_ringparam = b44_set_ringparam,
2046 .get_pauseparam = b44_get_pauseparam,
2047 .set_pauseparam = b44_set_pauseparam,
2048 .get_msglevel = b44_get_msglevel,
2049 .set_msglevel = b44_set_msglevel,
3353930d 2050 .get_strings = b44_get_strings,
b9f2c044 2051 .get_sset_count = b44_get_sset_count,
3353930d 2052 .get_ethtool_stats = b44_get_ethtool_stats,
1da177e4
LT		 2053};
2054
2055static int b44_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2056{
2057 struct mii_ioctl_data *data = if_mii(ifr);
2058 struct b44 *bp = netdev_priv(dev);
3410572d
FR		 2059 int err = -EINVAL;
2060
2061 if (!netif_running(dev))
2062 goto out;
1da177e4
LT		 2063
2064 spin_lock_irq(&bp->lock);
2065 err = generic_mii_ioctl(&bp->mii_if, data, cmd, NULL);
2066 spin_unlock_irq(&bp->lock);
3410572d 2067out:
1da177e4
LT		 2068 return err;
2069}
2070
1da177e4
LT		 2071static int __devinit b44_get_invariants(struct b44 *bp)
2072{
753f4920
MB		 2073 struct ssb_device *sdev = bp->sdev;
2074 int err = 0;
2075 u8 *addr;
1da177e4 2076
753f4920 2077 bp->dma_offset = ssb_dma_translation(sdev);
1da177e4 2078
753f4920
MB		 2079 if (sdev->bus->bustype == SSB_BUSTYPE_SSB &&
2080 instance > 1) {
458414b2
LF		 2081 addr = sdev->bus->sprom.et1mac;
2082 bp->phy_addr = sdev->bus->sprom.et1phyaddr;
753f4920 2083 } else {
458414b2
LF		 2084 addr = sdev->bus->sprom.et0mac;
2085 bp->phy_addr = sdev->bus->sprom.et0phyaddr;
753f4920 2086 }
5ea79631
MB		 2087 /* Some ROMs have buggy PHY addresses with the high
2088 * bits set (sign extension?). Truncate them to a
2089 * valid PHY address. */
2090 bp->phy_addr &= 0x1F;
2091
753f4920 2092 memcpy(bp->dev->dev_addr, addr, 6);
391fc09a
GZ		 2093
2094 if (!is_valid_ether_addr(&bp->dev->dev_addr[0])){
2095 printk(KERN_ERR PFX "Invalid MAC address found in EEPROM\n");
2096 return -EINVAL;
2097 }
2098
2160de53 2099 memcpy(bp->dev->perm_addr, bp->dev->dev_addr, bp->dev->addr_len);
1da177e4 2100
1da177e4
LT		 2101 bp->imask = IMASK_DEF;
2102
10badc21 2103 /* XXX - really required?
1da177e4 2104 bp->flags |= B44_FLAG_BUGGY_TXPTR;
753f4920 2105 */
52cafd96 2106
753f4920
MB		 2107 if (bp->sdev->id.revision >= 7)
2108 bp->flags |= B44_FLAG_B0_ANDLATER;
52cafd96 2109
1da177e4
LT		 2110 return err;
2111}
2112
753f4920
MB		 2113static int __devinit b44_init_one(struct ssb_device *sdev,
2114 const struct ssb_device_id *ent)
1da177e4
LT		 2115{
2116 static int b44_version_printed = 0;
1da177e4
LT		 2117 struct net_device *dev;
2118 struct b44 *bp;
0795af57
JP		 2119 int err;
2120 DECLARE_MAC_BUF(mac);
1da177e4 2121
753f4920
MB		 2122 instance++;
2123
1da177e4
LT		 2124 if (b44_version_printed++ == 0)
2125 printk(KERN_INFO "%s", version);
2126
1da177e4
LT		 2127
2128 dev = alloc_etherdev(sizeof(*bp));
2129 if (!dev) {
753f4920 2130 dev_err(sdev->dev, "Etherdev alloc failed, aborting.\n");
1da177e4 2131 err = -ENOMEM;
753f4920 2132 goto out;
1da177e4
LT		 2133 }
2134
753f4920 2135 SET_NETDEV_DEV(dev, sdev->dev);
1da177e4
LT		 2136
2137 /* No interesting netdevice features in this card... */
2138 dev->features |= 0;
2139
2140 bp = netdev_priv(dev);
753f4920 2141 bp->sdev = sdev;
1da177e4 2142 bp->dev = dev;
874a6214
FR		 2143
2144 bp->msg_enable = netif_msg_init(b44_debug, B44_DEF_MSG_ENABLE);
1da177e4
LT		 2145
2146 spin_lock_init(&bp->lock);
2147
1da177e4
LT		 2148 bp->rx_pending = B44_DEF_RX_RING_PENDING;
2149 bp->tx_pending = B44_DEF_TX_RING_PENDING;
2150
2151 dev->open = b44_open;
2152 dev->stop = b44_close;
2153 dev->hard_start_xmit = b44_start_xmit;
2154 dev->get_stats = b44_get_stats;
2155 dev->set_multicast_list = b44_set_rx_mode;
2156 dev->set_mac_address = b44_set_mac_addr;
2157 dev->do_ioctl = b44_ioctl;
2158 dev->tx_timeout = b44_tx_timeout;
bea3348e 2159 netif_napi_add(dev, &bp->napi, b44_poll, 64);
1da177e4
LT		 2160 dev->watchdog_timeo = B44_TX_TIMEOUT;
2161#ifdef CONFIG_NET_POLL_CONTROLLER
2162 dev->poll_controller = b44_poll_controller;
2163#endif
2164 dev->change_mtu = b44_change_mtu;
753f4920 2165 dev->irq = sdev->irq;
1da177e4
LT		 2166 SET_ETHTOOL_OPS(dev, &b44_ethtool_ops);
2167
c35ca399
SH		 2168 netif_carrier_off(dev);
2169
753f4920
MB		 2170 err = ssb_bus_powerup(sdev->bus, 0);
2171 if (err) {
2172 dev_err(sdev->dev,
2173 "Failed to powerup the bus\n");
2174 goto err_out_free_dev;
2175 }
2176 err = ssb_dma_set_mask(sdev, DMA_30BIT_MASK);
2177 if (err) {
2178 dev_err(sdev->dev,
2179 "Required 30BIT DMA mask unsupported by the system.\n");
2180 goto err_out_powerdown;
2181 }
1da177e4
LT		 2182 err = b44_get_invariants(bp);
2183 if (err) {
753f4920 2184 dev_err(sdev->dev,
2e8a538d 2185 "Problem fetching invariants of chip, aborting.\n");
753f4920 2186 goto err_out_powerdown;
1da177e4
LT		 2187 }
2188
2189 bp->mii_if.dev = dev;
2190 bp->mii_if.mdio_read = b44_mii_read;
2191 bp->mii_if.mdio_write = b44_mii_write;
2192 bp->mii_if.phy_id = bp->phy_addr;
2193 bp->mii_if.phy_id_mask = 0x1f;
2194 bp->mii_if.reg_num_mask = 0x1f;
2195
2196 /* By default, advertise all speed/duplex settings. */
2197 bp->flags |= (B44_FLAG_ADV_10HALF | B44_FLAG_ADV_10FULL |
2198 B44_FLAG_ADV_100HALF | B44_FLAG_ADV_100FULL);
2199
2200 /* By default, auto-negotiate PAUSE. */
2201 bp->flags |= B44_FLAG_PAUSE_AUTO;
2202
2203 err = register_netdev(dev);
2204 if (err) {
753f4920
MB		 2205 dev_err(sdev->dev, "Cannot register net device, aborting.\n");
2206 goto err_out_powerdown;
1da177e4
LT		 2207 }
2208
753f4920 2209 ssb_set_drvdata(sdev, dev);
1da177e4 2210
10badc21 2211 /* Chip reset provides power to the b44 MAC & PCI cores, which
5c513129 2212 * is necessary for MAC register access.
10badc21 2213 */
fedb0eef 2214 b44_chip_reset(bp, B44_CHIP_RESET_FULL);
5c513129 2215
753f4920 2216 printk(KERN_INFO "%s: Broadcom 44xx/47xx 10/100BaseT Ethernet %s\n",
0795af57 2217 dev->name, print_mac(mac, dev->dev_addr));
1da177e4
LT		 2218
2219 return 0;
2220
753f4920
MB		 2221err_out_powerdown:
2222 ssb_bus_may_powerdown(sdev->bus);
1da177e4
LT		 2223
2224err_out_free_dev:
2225 free_netdev(dev);
2226
753f4920 2227out:
1da177e4
LT		 2228 return err;
2229}
2230
753f4920 2231static void __devexit b44_remove_one(struct ssb_device *sdev)
1da177e4 2232{
753f4920 2233 struct net_device *dev = ssb_get_drvdata(sdev);
1da177e4 2234
874a6214 2235 unregister_netdev(dev);
753f4920 2236 ssb_bus_may_powerdown(sdev->bus);
874a6214 2237 free_netdev(dev);
fedb0eef 2238 ssb_pcihost_set_power_state(sdev, PCI_D3hot);
753f4920 2239 ssb_set_drvdata(sdev, NULL);
1da177e4
LT		 2240}
2241
753f4920 2242static int b44_suspend(struct ssb_device *sdev, pm_message_t state)
1da177e4 2243{
753f4920 2244 struct net_device *dev = ssb_get_drvdata(sdev);
1da177e4
LT		 2245 struct b44 *bp = netdev_priv(dev);
2246
753f4920
MB		 2247 if (!netif_running(dev))
2248 return 0;
1da177e4
LT		 2249
2250 del_timer_sync(&bp->timer);
2251
10badc21 2252 spin_lock_irq(&bp->lock);
1da177e4
LT		 2253
2254 b44_halt(bp);
10badc21 2255 netif_carrier_off(bp->dev);
1da177e4
LT		 2256 netif_device_detach(bp->dev);
2257 b44_free_rings(bp);
2258
2259 spin_unlock_irq(&bp->lock);
46e17853
PM		 2260
2261 free_irq(dev->irq, dev);
52cafd96 2262 if (bp->flags & B44_FLAG_WOL_ENABLE) {
5fc7d61a 2263 b44_init_hw(bp, B44_PARTIAL_RESET);
52cafd96
GZ		 2264 b44_setup_wol(bp);
2265 }
753f4920 2266
fedb0eef 2267 ssb_pcihost_set_power_state(sdev, PCI_D3hot);
1da177e4
LT		 2268 return 0;
2269}
2270
753f4920 2271static int b44_resume(struct ssb_device *sdev)
1da177e4 2272{
753f4920 2273 struct net_device *dev = ssb_get_drvdata(sdev);
1da177e4 2274 struct b44 *bp = netdev_priv(dev);
90afd0e5 2275 int rc = 0;
1da177e4 2276
753f4920 2277 rc = ssb_bus_powerup(sdev->bus, 0);
90afd0e5 2278 if (rc) {
753f4920
MB		 2279 dev_err(sdev->dev,
2280 "Failed to powerup the bus\n");
90afd0e5
DM		 2281 return rc;
2282 }
2283
1da177e4
LT		 2284 if (!netif_running(dev))
2285 return 0;
2286
90afd0e5
DM		 2287 rc = request_irq(dev->irq, b44_interrupt, IRQF_SHARED, dev->name, dev);
2288 if (rc) {
46e17853 2289 printk(KERN_ERR PFX "%s: request_irq failed\n", dev->name);
90afd0e5
DM		 2290 return rc;
2291 }
46e17853 2292
1da177e4
LT		 2293 spin_lock_irq(&bp->lock);
2294
2295 b44_init_rings(bp);
5fc7d61a 2296 b44_init_hw(bp, B44_FULL_RESET);
1da177e4
LT		 2297 netif_device_attach(bp->dev);
2298 spin_unlock_irq(&bp->lock);
2299
1da177e4 2300 b44_enable_ints(bp);
d9e2d185 2301 netif_wake_queue(dev);
a72a8179
SH		 2302
2303 mod_timer(&bp->timer, jiffies + 1);
2304
1da177e4
LT		 2305 return 0;
2306}
2307
753f4920 2308static struct ssb_driver b44_ssb_driver = {
1da177e4 2309 .name = DRV_MODULE_NAME,
753f4920 2310 .id_table = b44_ssb_tbl,
1da177e4
LT		 2311 .probe = b44_init_one,
2312 .remove = __devexit_p(b44_remove_one),
753f4920
MB		 2313 .suspend = b44_suspend,
2314 .resume = b44_resume,
1da177e4
LT		 2315};
2316
753f4920
MB		 2317static inline int b44_pci_init(void)
2318{
2319 int err = 0;
2320#ifdef CONFIG_B44_PCI
2321 err = ssb_pcihost_register(&b44_pci_driver);
2322#endif
2323 return err;
2324}
2325
2326static inline void b44_pci_exit(void)
2327{
2328#ifdef CONFIG_B44_PCI
2329 ssb_pcihost_unregister(&b44_pci_driver);
2330#endif
2331}
2332
1da177e4
LT		 2333static int __init b44_init(void)
2334{
9f38c636 2335 unsigned int dma_desc_align_size = dma_get_cache_alignment();
753f4920 2336 int err;
9f38c636
JL		 2337
2338 /* Setup paramaters for syncing RX/TX DMA descriptors */
2339 dma_desc_align_mask = ~(dma_desc_align_size - 1);
22d4d771 2340 dma_desc_sync_size = max_t(unsigned int, dma_desc_align_size, sizeof(struct dma_desc));
9f38c636 2341
753f4920
MB		 2342 err = b44_pci_init();
2343 if (err)
2344 return err;
2345 err = ssb_driver_register(&b44_ssb_driver);
2346 if (err)
2347 b44_pci_exit();
2348 return err;
1da177e4
LT		 2349}
2350
2351static void __exit b44_cleanup(void)
2352{
753f4920
MB		 2353 ssb_driver_unregister(&b44_ssb_driver);
2354 b44_pci_exit();
1da177e4
LT		 2355}
2356
2357module_init(b44_init);
2358module_exit(b44_cleanup);
2359
Linux kernel - Deliverables
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