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9b1fc55a MB |
1 | /* |
2 | * Driver for BCM963xx builtin Ethernet mac | |
3 | * | |
4 | * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr> | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License as published by | |
8 | * the Free Software Foundation; either version 2 of the License, or | |
9 | * (at your option) any later version. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License | |
17 | * along with this program; if not, write to the Free Software | |
18 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
19 | */ | |
20 | #include <linux/init.h> | |
21 | #include <linux/module.h> | |
22 | #include <linux/clk.h> | |
23 | #include <linux/etherdevice.h> | |
24 | #include <linux/delay.h> | |
25 | #include <linux/ethtool.h> | |
26 | #include <linux/crc32.h> | |
27 | #include <linux/err.h> | |
28 | #include <linux/dma-mapping.h> | |
29 | #include <linux/platform_device.h> | |
30 | #include <linux/if_vlan.h> | |
31 | ||
32 | #include <bcm63xx_dev_enet.h> | |
33 | #include "bcm63xx_enet.h" | |
34 | ||
35 | static char bcm_enet_driver_name[] = "bcm63xx_enet"; | |
36 | static char bcm_enet_driver_version[] = "1.0"; | |
37 | ||
38 | static int copybreak __read_mostly = 128; | |
39 | module_param(copybreak, int, 0); | |
40 | MODULE_PARM_DESC(copybreak, "Receive copy threshold"); | |
41 | ||
42 | /* io memory shared between all devices */ | |
43 | static void __iomem *bcm_enet_shared_base; | |
44 | ||
45 | /* | |
46 | * io helpers to access mac registers | |
47 | */ | |
48 | static inline u32 enet_readl(struct bcm_enet_priv *priv, u32 off) | |
49 | { | |
50 | return bcm_readl(priv->base + off); | |
51 | } | |
52 | ||
53 | static inline void enet_writel(struct bcm_enet_priv *priv, | |
54 | u32 val, u32 off) | |
55 | { | |
56 | bcm_writel(val, priv->base + off); | |
57 | } | |
58 | ||
59 | /* | |
60 | * io helpers to access shared registers | |
61 | */ | |
62 | static inline u32 enet_dma_readl(struct bcm_enet_priv *priv, u32 off) | |
63 | { | |
64 | return bcm_readl(bcm_enet_shared_base + off); | |
65 | } | |
66 | ||
67 | static inline void enet_dma_writel(struct bcm_enet_priv *priv, | |
68 | u32 val, u32 off) | |
69 | { | |
70 | bcm_writel(val, bcm_enet_shared_base + off); | |
71 | } | |
72 | ||
73 | /* | |
74 | * write given data into mii register and wait for transfer to end | |
75 | * with timeout (average measured transfer time is 25us) | |
76 | */ | |
77 | static int do_mdio_op(struct bcm_enet_priv *priv, unsigned int data) | |
78 | { | |
79 | int limit; | |
80 | ||
81 | /* make sure mii interrupt status is cleared */ | |
82 | enet_writel(priv, ENET_IR_MII, ENET_IR_REG); | |
83 | ||
84 | enet_writel(priv, data, ENET_MIIDATA_REG); | |
85 | wmb(); | |
86 | ||
87 | /* busy wait on mii interrupt bit, with timeout */ | |
88 | limit = 1000; | |
89 | do { | |
90 | if (enet_readl(priv, ENET_IR_REG) & ENET_IR_MII) | |
91 | break; | |
92 | udelay(1); | |
ec1652af | 93 | } while (limit-- > 0); |
9b1fc55a MB |
94 | |
95 | return (limit < 0) ? 1 : 0; | |
96 | } | |
97 | ||
98 | /* | |
99 | * MII internal read callback | |
100 | */ | |
101 | static int bcm_enet_mdio_read(struct bcm_enet_priv *priv, int mii_id, | |
102 | int regnum) | |
103 | { | |
104 | u32 tmp, val; | |
105 | ||
106 | tmp = regnum << ENET_MIIDATA_REG_SHIFT; | |
107 | tmp |= 0x2 << ENET_MIIDATA_TA_SHIFT; | |
108 | tmp |= mii_id << ENET_MIIDATA_PHYID_SHIFT; | |
109 | tmp |= ENET_MIIDATA_OP_READ_MASK; | |
110 | ||
111 | if (do_mdio_op(priv, tmp)) | |
112 | return -1; | |
113 | ||
114 | val = enet_readl(priv, ENET_MIIDATA_REG); | |
115 | val &= 0xffff; | |
116 | return val; | |
117 | } | |
118 | ||
119 | /* | |
120 | * MII internal write callback | |
121 | */ | |
122 | static int bcm_enet_mdio_write(struct bcm_enet_priv *priv, int mii_id, | |
123 | int regnum, u16 value) | |
124 | { | |
125 | u32 tmp; | |
126 | ||
127 | tmp = (value & 0xffff) << ENET_MIIDATA_DATA_SHIFT; | |
128 | tmp |= 0x2 << ENET_MIIDATA_TA_SHIFT; | |
129 | tmp |= regnum << ENET_MIIDATA_REG_SHIFT; | |
130 | tmp |= mii_id << ENET_MIIDATA_PHYID_SHIFT; | |
131 | tmp |= ENET_MIIDATA_OP_WRITE_MASK; | |
132 | ||
133 | (void)do_mdio_op(priv, tmp); | |
134 | return 0; | |
135 | } | |
136 | ||
137 | /* | |
138 | * MII read callback from phylib | |
139 | */ | |
140 | static int bcm_enet_mdio_read_phylib(struct mii_bus *bus, int mii_id, | |
141 | int regnum) | |
142 | { | |
143 | return bcm_enet_mdio_read(bus->priv, mii_id, regnum); | |
144 | } | |
145 | ||
146 | /* | |
147 | * MII write callback from phylib | |
148 | */ | |
149 | static int bcm_enet_mdio_write_phylib(struct mii_bus *bus, int mii_id, | |
150 | int regnum, u16 value) | |
151 | { | |
152 | return bcm_enet_mdio_write(bus->priv, mii_id, regnum, value); | |
153 | } | |
154 | ||
155 | /* | |
156 | * MII read callback from mii core | |
157 | */ | |
158 | static int bcm_enet_mdio_read_mii(struct net_device *dev, int mii_id, | |
159 | int regnum) | |
160 | { | |
161 | return bcm_enet_mdio_read(netdev_priv(dev), mii_id, regnum); | |
162 | } | |
163 | ||
164 | /* | |
165 | * MII write callback from mii core | |
166 | */ | |
167 | static void bcm_enet_mdio_write_mii(struct net_device *dev, int mii_id, | |
168 | int regnum, int value) | |
169 | { | |
170 | bcm_enet_mdio_write(netdev_priv(dev), mii_id, regnum, value); | |
171 | } | |
172 | ||
173 | /* | |
174 | * refill rx queue | |
175 | */ | |
176 | static int bcm_enet_refill_rx(struct net_device *dev) | |
177 | { | |
178 | struct bcm_enet_priv *priv; | |
179 | ||
180 | priv = netdev_priv(dev); | |
181 | ||
182 | while (priv->rx_desc_count < priv->rx_ring_size) { | |
183 | struct bcm_enet_desc *desc; | |
184 | struct sk_buff *skb; | |
185 | dma_addr_t p; | |
186 | int desc_idx; | |
187 | u32 len_stat; | |
188 | ||
189 | desc_idx = priv->rx_dirty_desc; | |
190 | desc = &priv->rx_desc_cpu[desc_idx]; | |
191 | ||
192 | if (!priv->rx_skb[desc_idx]) { | |
193 | skb = netdev_alloc_skb(dev, priv->rx_skb_size); | |
194 | if (!skb) | |
195 | break; | |
196 | priv->rx_skb[desc_idx] = skb; | |
197 | ||
198 | p = dma_map_single(&priv->pdev->dev, skb->data, | |
199 | priv->rx_skb_size, | |
200 | DMA_FROM_DEVICE); | |
201 | desc->address = p; | |
202 | } | |
203 | ||
204 | len_stat = priv->rx_skb_size << DMADESC_LENGTH_SHIFT; | |
205 | len_stat |= DMADESC_OWNER_MASK; | |
206 | if (priv->rx_dirty_desc == priv->rx_ring_size - 1) { | |
207 | len_stat |= DMADESC_WRAP_MASK; | |
208 | priv->rx_dirty_desc = 0; | |
209 | } else { | |
210 | priv->rx_dirty_desc++; | |
211 | } | |
212 | wmb(); | |
213 | desc->len_stat = len_stat; | |
214 | ||
215 | priv->rx_desc_count++; | |
216 | ||
217 | /* tell dma engine we allocated one buffer */ | |
218 | enet_dma_writel(priv, 1, ENETDMA_BUFALLOC_REG(priv->rx_chan)); | |
219 | } | |
220 | ||
221 | /* If rx ring is still empty, set a timer to try allocating | |
222 | * again at a later time. */ | |
223 | if (priv->rx_desc_count == 0 && netif_running(dev)) { | |
224 | dev_warn(&priv->pdev->dev, "unable to refill rx ring\n"); | |
225 | priv->rx_timeout.expires = jiffies + HZ; | |
226 | add_timer(&priv->rx_timeout); | |
227 | } | |
228 | ||
229 | return 0; | |
230 | } | |
231 | ||
232 | /* | |
233 | * timer callback to defer refill rx queue in case we're OOM | |
234 | */ | |
235 | static void bcm_enet_refill_rx_timer(unsigned long data) | |
236 | { | |
237 | struct net_device *dev; | |
238 | struct bcm_enet_priv *priv; | |
239 | ||
240 | dev = (struct net_device *)data; | |
241 | priv = netdev_priv(dev); | |
242 | ||
243 | spin_lock(&priv->rx_lock); | |
244 | bcm_enet_refill_rx((struct net_device *)data); | |
245 | spin_unlock(&priv->rx_lock); | |
246 | } | |
247 | ||
248 | /* | |
249 | * extract packet from rx queue | |
250 | */ | |
251 | static int bcm_enet_receive_queue(struct net_device *dev, int budget) | |
252 | { | |
253 | struct bcm_enet_priv *priv; | |
254 | struct device *kdev; | |
255 | int processed; | |
256 | ||
257 | priv = netdev_priv(dev); | |
258 | kdev = &priv->pdev->dev; | |
259 | processed = 0; | |
260 | ||
261 | /* don't scan ring further than number of refilled | |
262 | * descriptor */ | |
263 | if (budget > priv->rx_desc_count) | |
264 | budget = priv->rx_desc_count; | |
265 | ||
266 | do { | |
267 | struct bcm_enet_desc *desc; | |
268 | struct sk_buff *skb; | |
269 | int desc_idx; | |
270 | u32 len_stat; | |
271 | unsigned int len; | |
272 | ||
273 | desc_idx = priv->rx_curr_desc; | |
274 | desc = &priv->rx_desc_cpu[desc_idx]; | |
275 | ||
276 | /* make sure we actually read the descriptor status at | |
277 | * each loop */ | |
278 | rmb(); | |
279 | ||
280 | len_stat = desc->len_stat; | |
281 | ||
282 | /* break if dma ownership belongs to hw */ | |
283 | if (len_stat & DMADESC_OWNER_MASK) | |
284 | break; | |
285 | ||
286 | processed++; | |
287 | priv->rx_curr_desc++; | |
288 | if (priv->rx_curr_desc == priv->rx_ring_size) | |
289 | priv->rx_curr_desc = 0; | |
290 | priv->rx_desc_count--; | |
291 | ||
292 | /* if the packet does not have start of packet _and_ | |
293 | * end of packet flag set, then just recycle it */ | |
294 | if ((len_stat & DMADESC_ESOP_MASK) != DMADESC_ESOP_MASK) { | |
295 | priv->stats.rx_dropped++; | |
296 | continue; | |
297 | } | |
298 | ||
299 | /* recycle packet if it's marked as bad */ | |
300 | if (unlikely(len_stat & DMADESC_ERR_MASK)) { | |
301 | priv->stats.rx_errors++; | |
302 | ||
303 | if (len_stat & DMADESC_OVSIZE_MASK) | |
304 | priv->stats.rx_length_errors++; | |
305 | if (len_stat & DMADESC_CRC_MASK) | |
306 | priv->stats.rx_crc_errors++; | |
307 | if (len_stat & DMADESC_UNDER_MASK) | |
308 | priv->stats.rx_frame_errors++; | |
309 | if (len_stat & DMADESC_OV_MASK) | |
310 | priv->stats.rx_fifo_errors++; | |
311 | continue; | |
312 | } | |
313 | ||
314 | /* valid packet */ | |
315 | skb = priv->rx_skb[desc_idx]; | |
316 | len = (len_stat & DMADESC_LENGTH_MASK) >> DMADESC_LENGTH_SHIFT; | |
317 | /* don't include FCS */ | |
318 | len -= 4; | |
319 | ||
320 | if (len < copybreak) { | |
321 | struct sk_buff *nskb; | |
322 | ||
89d71a66 | 323 | nskb = netdev_alloc_skb_ip_align(dev, len); |
9b1fc55a MB |
324 | if (!nskb) { |
325 | /* forget packet, just rearm desc */ | |
326 | priv->stats.rx_dropped++; | |
327 | continue; | |
328 | } | |
329 | ||
9b1fc55a MB |
330 | dma_sync_single_for_cpu(kdev, desc->address, |
331 | len, DMA_FROM_DEVICE); | |
332 | memcpy(nskb->data, skb->data, len); | |
333 | dma_sync_single_for_device(kdev, desc->address, | |
334 | len, DMA_FROM_DEVICE); | |
335 | skb = nskb; | |
336 | } else { | |
337 | dma_unmap_single(&priv->pdev->dev, desc->address, | |
338 | priv->rx_skb_size, DMA_FROM_DEVICE); | |
339 | priv->rx_skb[desc_idx] = NULL; | |
340 | } | |
341 | ||
342 | skb_put(skb, len); | |
343 | skb->dev = dev; | |
344 | skb->protocol = eth_type_trans(skb, dev); | |
345 | priv->stats.rx_packets++; | |
346 | priv->stats.rx_bytes += len; | |
347 | dev->last_rx = jiffies; | |
348 | netif_receive_skb(skb); | |
349 | ||
350 | } while (--budget > 0); | |
351 | ||
352 | if (processed || !priv->rx_desc_count) { | |
353 | bcm_enet_refill_rx(dev); | |
354 | ||
355 | /* kick rx dma */ | |
356 | enet_dma_writel(priv, ENETDMA_CHANCFG_EN_MASK, | |
357 | ENETDMA_CHANCFG_REG(priv->rx_chan)); | |
358 | } | |
359 | ||
360 | return processed; | |
361 | } | |
362 | ||
363 | ||
364 | /* | |
365 | * try to or force reclaim of transmitted buffers | |
366 | */ | |
367 | static int bcm_enet_tx_reclaim(struct net_device *dev, int force) | |
368 | { | |
369 | struct bcm_enet_priv *priv; | |
370 | int released; | |
371 | ||
372 | priv = netdev_priv(dev); | |
373 | released = 0; | |
374 | ||
375 | while (priv->tx_desc_count < priv->tx_ring_size) { | |
376 | struct bcm_enet_desc *desc; | |
377 | struct sk_buff *skb; | |
378 | ||
379 | /* We run in a bh and fight against start_xmit, which | |
380 | * is called with bh disabled */ | |
381 | spin_lock(&priv->tx_lock); | |
382 | ||
383 | desc = &priv->tx_desc_cpu[priv->tx_dirty_desc]; | |
384 | ||
385 | if (!force && (desc->len_stat & DMADESC_OWNER_MASK)) { | |
386 | spin_unlock(&priv->tx_lock); | |
387 | break; | |
388 | } | |
389 | ||
390 | /* ensure other field of the descriptor were not read | |
391 | * before we checked ownership */ | |
392 | rmb(); | |
393 | ||
394 | skb = priv->tx_skb[priv->tx_dirty_desc]; | |
395 | priv->tx_skb[priv->tx_dirty_desc] = NULL; | |
396 | dma_unmap_single(&priv->pdev->dev, desc->address, skb->len, | |
397 | DMA_TO_DEVICE); | |
398 | ||
399 | priv->tx_dirty_desc++; | |
400 | if (priv->tx_dirty_desc == priv->tx_ring_size) | |
401 | priv->tx_dirty_desc = 0; | |
402 | priv->tx_desc_count++; | |
403 | ||
404 | spin_unlock(&priv->tx_lock); | |
405 | ||
406 | if (desc->len_stat & DMADESC_UNDER_MASK) | |
407 | priv->stats.tx_errors++; | |
408 | ||
409 | dev_kfree_skb(skb); | |
410 | released++; | |
411 | } | |
412 | ||
413 | if (netif_queue_stopped(dev) && released) | |
414 | netif_wake_queue(dev); | |
415 | ||
416 | return released; | |
417 | } | |
418 | ||
419 | /* | |
420 | * poll func, called by network core | |
421 | */ | |
422 | static int bcm_enet_poll(struct napi_struct *napi, int budget) | |
423 | { | |
424 | struct bcm_enet_priv *priv; | |
425 | struct net_device *dev; | |
426 | int tx_work_done, rx_work_done; | |
427 | ||
428 | priv = container_of(napi, struct bcm_enet_priv, napi); | |
429 | dev = priv->net_dev; | |
430 | ||
431 | /* ack interrupts */ | |
432 | enet_dma_writel(priv, ENETDMA_IR_PKTDONE_MASK, | |
433 | ENETDMA_IR_REG(priv->rx_chan)); | |
434 | enet_dma_writel(priv, ENETDMA_IR_PKTDONE_MASK, | |
435 | ENETDMA_IR_REG(priv->tx_chan)); | |
436 | ||
437 | /* reclaim sent skb */ | |
438 | tx_work_done = bcm_enet_tx_reclaim(dev, 0); | |
439 | ||
440 | spin_lock(&priv->rx_lock); | |
441 | rx_work_done = bcm_enet_receive_queue(dev, budget); | |
442 | spin_unlock(&priv->rx_lock); | |
443 | ||
444 | if (rx_work_done >= budget || tx_work_done > 0) { | |
445 | /* rx/tx queue is not yet empty/clean */ | |
446 | return rx_work_done; | |
447 | } | |
448 | ||
449 | /* no more packet in rx/tx queue, remove device from poll | |
450 | * queue */ | |
451 | napi_complete(napi); | |
452 | ||
453 | /* restore rx/tx interrupt */ | |
454 | enet_dma_writel(priv, ENETDMA_IR_PKTDONE_MASK, | |
455 | ENETDMA_IRMASK_REG(priv->rx_chan)); | |
456 | enet_dma_writel(priv, ENETDMA_IR_PKTDONE_MASK, | |
457 | ENETDMA_IRMASK_REG(priv->tx_chan)); | |
458 | ||
459 | return rx_work_done; | |
460 | } | |
461 | ||
462 | /* | |
463 | * mac interrupt handler | |
464 | */ | |
465 | static irqreturn_t bcm_enet_isr_mac(int irq, void *dev_id) | |
466 | { | |
467 | struct net_device *dev; | |
468 | struct bcm_enet_priv *priv; | |
469 | u32 stat; | |
470 | ||
471 | dev = dev_id; | |
472 | priv = netdev_priv(dev); | |
473 | ||
474 | stat = enet_readl(priv, ENET_IR_REG); | |
475 | if (!(stat & ENET_IR_MIB)) | |
476 | return IRQ_NONE; | |
477 | ||
478 | /* clear & mask interrupt */ | |
479 | enet_writel(priv, ENET_IR_MIB, ENET_IR_REG); | |
480 | enet_writel(priv, 0, ENET_IRMASK_REG); | |
481 | ||
482 | /* read mib registers in workqueue */ | |
483 | schedule_work(&priv->mib_update_task); | |
484 | ||
485 | return IRQ_HANDLED; | |
486 | } | |
487 | ||
488 | /* | |
489 | * rx/tx dma interrupt handler | |
490 | */ | |
491 | static irqreturn_t bcm_enet_isr_dma(int irq, void *dev_id) | |
492 | { | |
493 | struct net_device *dev; | |
494 | struct bcm_enet_priv *priv; | |
495 | ||
496 | dev = dev_id; | |
497 | priv = netdev_priv(dev); | |
498 | ||
499 | /* mask rx/tx interrupts */ | |
500 | enet_dma_writel(priv, 0, ENETDMA_IRMASK_REG(priv->rx_chan)); | |
501 | enet_dma_writel(priv, 0, ENETDMA_IRMASK_REG(priv->tx_chan)); | |
502 | ||
503 | napi_schedule(&priv->napi); | |
504 | ||
505 | return IRQ_HANDLED; | |
506 | } | |
507 | ||
508 | /* | |
509 | * tx request callback | |
510 | */ | |
511 | static int bcm_enet_start_xmit(struct sk_buff *skb, struct net_device *dev) | |
512 | { | |
513 | struct bcm_enet_priv *priv; | |
514 | struct bcm_enet_desc *desc; | |
515 | u32 len_stat; | |
516 | int ret; | |
517 | ||
518 | priv = netdev_priv(dev); | |
519 | ||
520 | /* lock against tx reclaim */ | |
521 | spin_lock(&priv->tx_lock); | |
522 | ||
523 | /* make sure the tx hw queue is not full, should not happen | |
524 | * since we stop queue before it's the case */ | |
525 | if (unlikely(!priv->tx_desc_count)) { | |
526 | netif_stop_queue(dev); | |
527 | dev_err(&priv->pdev->dev, "xmit called with no tx desc " | |
528 | "available?\n"); | |
529 | ret = NETDEV_TX_BUSY; | |
530 | goto out_unlock; | |
531 | } | |
532 | ||
533 | /* point to the next available desc */ | |
534 | desc = &priv->tx_desc_cpu[priv->tx_curr_desc]; | |
535 | priv->tx_skb[priv->tx_curr_desc] = skb; | |
536 | ||
537 | /* fill descriptor */ | |
538 | desc->address = dma_map_single(&priv->pdev->dev, skb->data, skb->len, | |
539 | DMA_TO_DEVICE); | |
540 | ||
541 | len_stat = (skb->len << DMADESC_LENGTH_SHIFT) & DMADESC_LENGTH_MASK; | |
542 | len_stat |= DMADESC_ESOP_MASK | | |
543 | DMADESC_APPEND_CRC | | |
544 | DMADESC_OWNER_MASK; | |
545 | ||
546 | priv->tx_curr_desc++; | |
547 | if (priv->tx_curr_desc == priv->tx_ring_size) { | |
548 | priv->tx_curr_desc = 0; | |
549 | len_stat |= DMADESC_WRAP_MASK; | |
550 | } | |
551 | priv->tx_desc_count--; | |
552 | ||
553 | /* dma might be already polling, make sure we update desc | |
554 | * fields in correct order */ | |
555 | wmb(); | |
556 | desc->len_stat = len_stat; | |
557 | wmb(); | |
558 | ||
559 | /* kick tx dma */ | |
560 | enet_dma_writel(priv, ENETDMA_CHANCFG_EN_MASK, | |
561 | ENETDMA_CHANCFG_REG(priv->tx_chan)); | |
562 | ||
563 | /* stop queue if no more desc available */ | |
564 | if (!priv->tx_desc_count) | |
565 | netif_stop_queue(dev); | |
566 | ||
567 | priv->stats.tx_bytes += skb->len; | |
568 | priv->stats.tx_packets++; | |
569 | dev->trans_start = jiffies; | |
570 | ret = NETDEV_TX_OK; | |
571 | ||
572 | out_unlock: | |
573 | spin_unlock(&priv->tx_lock); | |
574 | return ret; | |
575 | } | |
576 | ||
577 | /* | |
578 | * Change the interface's mac address. | |
579 | */ | |
580 | static int bcm_enet_set_mac_address(struct net_device *dev, void *p) | |
581 | { | |
582 | struct bcm_enet_priv *priv; | |
583 | struct sockaddr *addr = p; | |
584 | u32 val; | |
585 | ||
586 | priv = netdev_priv(dev); | |
587 | memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN); | |
588 | ||
589 | /* use perfect match register 0 to store my mac address */ | |
590 | val = (dev->dev_addr[2] << 24) | (dev->dev_addr[3] << 16) | | |
591 | (dev->dev_addr[4] << 8) | dev->dev_addr[5]; | |
592 | enet_writel(priv, val, ENET_PML_REG(0)); | |
593 | ||
594 | val = (dev->dev_addr[0] << 8 | dev->dev_addr[1]); | |
595 | val |= ENET_PMH_DATAVALID_MASK; | |
596 | enet_writel(priv, val, ENET_PMH_REG(0)); | |
597 | ||
598 | return 0; | |
599 | } | |
600 | ||
601 | /* | |
602 | * Change rx mode (promiscous/allmulti) and update multicast list | |
603 | */ | |
604 | static void bcm_enet_set_multicast_list(struct net_device *dev) | |
605 | { | |
606 | struct bcm_enet_priv *priv; | |
607 | struct dev_mc_list *mc_list; | |
608 | u32 val; | |
609 | int i; | |
610 | ||
611 | priv = netdev_priv(dev); | |
612 | ||
613 | val = enet_readl(priv, ENET_RXCFG_REG); | |
614 | ||
615 | if (dev->flags & IFF_PROMISC) | |
616 | val |= ENET_RXCFG_PROMISC_MASK; | |
617 | else | |
618 | val &= ~ENET_RXCFG_PROMISC_MASK; | |
619 | ||
620 | /* only 3 perfect match registers left, first one is used for | |
621 | * own mac address */ | |
4cd24eaf | 622 | if ((dev->flags & IFF_ALLMULTI) || netdev_mc_count(dev) > 3) |
9b1fc55a MB |
623 | val |= ENET_RXCFG_ALLMCAST_MASK; |
624 | else | |
625 | val &= ~ENET_RXCFG_ALLMCAST_MASK; | |
626 | ||
627 | /* no need to set perfect match registers if we catch all | |
628 | * multicast */ | |
629 | if (val & ENET_RXCFG_ALLMCAST_MASK) { | |
630 | enet_writel(priv, val, ENET_RXCFG_REG); | |
631 | return; | |
632 | } | |
633 | ||
0ddf477b JP |
634 | i = 0; |
635 | netdev_for_each_mc_addr(mc_list, dev) { | |
9b1fc55a MB |
636 | u8 *dmi_addr; |
637 | u32 tmp; | |
638 | ||
0ddf477b JP |
639 | if (i == 3) |
640 | break; | |
9b1fc55a MB |
641 | /* update perfect match registers */ |
642 | dmi_addr = mc_list->dmi_addr; | |
643 | tmp = (dmi_addr[2] << 24) | (dmi_addr[3] << 16) | | |
644 | (dmi_addr[4] << 8) | dmi_addr[5]; | |
645 | enet_writel(priv, tmp, ENET_PML_REG(i + 1)); | |
646 | ||
647 | tmp = (dmi_addr[0] << 8 | dmi_addr[1]); | |
648 | tmp |= ENET_PMH_DATAVALID_MASK; | |
0ddf477b | 649 | enet_writel(priv, tmp, ENET_PMH_REG(i++ + 1)); |
9b1fc55a MB |
650 | } |
651 | ||
652 | for (; i < 3; i++) { | |
653 | enet_writel(priv, 0, ENET_PML_REG(i + 1)); | |
654 | enet_writel(priv, 0, ENET_PMH_REG(i + 1)); | |
655 | } | |
656 | ||
657 | enet_writel(priv, val, ENET_RXCFG_REG); | |
658 | } | |
659 | ||
660 | /* | |
661 | * set mac duplex parameters | |
662 | */ | |
663 | static void bcm_enet_set_duplex(struct bcm_enet_priv *priv, int fullduplex) | |
664 | { | |
665 | u32 val; | |
666 | ||
667 | val = enet_readl(priv, ENET_TXCTL_REG); | |
668 | if (fullduplex) | |
669 | val |= ENET_TXCTL_FD_MASK; | |
670 | else | |
671 | val &= ~ENET_TXCTL_FD_MASK; | |
672 | enet_writel(priv, val, ENET_TXCTL_REG); | |
673 | } | |
674 | ||
675 | /* | |
676 | * set mac flow control parameters | |
677 | */ | |
678 | static void bcm_enet_set_flow(struct bcm_enet_priv *priv, int rx_en, int tx_en) | |
679 | { | |
680 | u32 val; | |
681 | ||
682 | /* rx flow control (pause frame handling) */ | |
683 | val = enet_readl(priv, ENET_RXCFG_REG); | |
684 | if (rx_en) | |
685 | val |= ENET_RXCFG_ENFLOW_MASK; | |
686 | else | |
687 | val &= ~ENET_RXCFG_ENFLOW_MASK; | |
688 | enet_writel(priv, val, ENET_RXCFG_REG); | |
689 | ||
690 | /* tx flow control (pause frame generation) */ | |
691 | val = enet_dma_readl(priv, ENETDMA_CFG_REG); | |
692 | if (tx_en) | |
693 | val |= ENETDMA_CFG_FLOWCH_MASK(priv->rx_chan); | |
694 | else | |
695 | val &= ~ENETDMA_CFG_FLOWCH_MASK(priv->rx_chan); | |
696 | enet_dma_writel(priv, val, ENETDMA_CFG_REG); | |
697 | } | |
698 | ||
699 | /* | |
700 | * link changed callback (from phylib) | |
701 | */ | |
702 | static void bcm_enet_adjust_phy_link(struct net_device *dev) | |
703 | { | |
704 | struct bcm_enet_priv *priv; | |
705 | struct phy_device *phydev; | |
706 | int status_changed; | |
707 | ||
708 | priv = netdev_priv(dev); | |
709 | phydev = priv->phydev; | |
710 | status_changed = 0; | |
711 | ||
712 | if (priv->old_link != phydev->link) { | |
713 | status_changed = 1; | |
714 | priv->old_link = phydev->link; | |
715 | } | |
716 | ||
717 | /* reflect duplex change in mac configuration */ | |
718 | if (phydev->link && phydev->duplex != priv->old_duplex) { | |
719 | bcm_enet_set_duplex(priv, | |
720 | (phydev->duplex == DUPLEX_FULL) ? 1 : 0); | |
721 | status_changed = 1; | |
722 | priv->old_duplex = phydev->duplex; | |
723 | } | |
724 | ||
725 | /* enable flow control if remote advertise it (trust phylib to | |
726 | * check that duplex is full */ | |
727 | if (phydev->link && phydev->pause != priv->old_pause) { | |
728 | int rx_pause_en, tx_pause_en; | |
729 | ||
730 | if (phydev->pause) { | |
731 | /* pause was advertised by lpa and us */ | |
732 | rx_pause_en = 1; | |
733 | tx_pause_en = 1; | |
734 | } else if (!priv->pause_auto) { | |
735 | /* pause setting overrided by user */ | |
736 | rx_pause_en = priv->pause_rx; | |
737 | tx_pause_en = priv->pause_tx; | |
738 | } else { | |
739 | rx_pause_en = 0; | |
740 | tx_pause_en = 0; | |
741 | } | |
742 | ||
743 | bcm_enet_set_flow(priv, rx_pause_en, tx_pause_en); | |
744 | status_changed = 1; | |
745 | priv->old_pause = phydev->pause; | |
746 | } | |
747 | ||
748 | if (status_changed) { | |
749 | pr_info("%s: link %s", dev->name, phydev->link ? | |
750 | "UP" : "DOWN"); | |
751 | if (phydev->link) | |
752 | pr_cont(" - %d/%s - flow control %s", phydev->speed, | |
753 | DUPLEX_FULL == phydev->duplex ? "full" : "half", | |
754 | phydev->pause == 1 ? "rx&tx" : "off"); | |
755 | ||
756 | pr_cont("\n"); | |
757 | } | |
758 | } | |
759 | ||
760 | /* | |
761 | * link changed callback (if phylib is not used) | |
762 | */ | |
763 | static void bcm_enet_adjust_link(struct net_device *dev) | |
764 | { | |
765 | struct bcm_enet_priv *priv; | |
766 | ||
767 | priv = netdev_priv(dev); | |
768 | bcm_enet_set_duplex(priv, priv->force_duplex_full); | |
769 | bcm_enet_set_flow(priv, priv->pause_rx, priv->pause_tx); | |
770 | netif_carrier_on(dev); | |
771 | ||
772 | pr_info("%s: link forced UP - %d/%s - flow control %s/%s\n", | |
773 | dev->name, | |
774 | priv->force_speed_100 ? 100 : 10, | |
775 | priv->force_duplex_full ? "full" : "half", | |
776 | priv->pause_rx ? "rx" : "off", | |
777 | priv->pause_tx ? "tx" : "off"); | |
778 | } | |
779 | ||
780 | /* | |
781 | * open callback, allocate dma rings & buffers and start rx operation | |
782 | */ | |
783 | static int bcm_enet_open(struct net_device *dev) | |
784 | { | |
785 | struct bcm_enet_priv *priv; | |
786 | struct sockaddr addr; | |
787 | struct device *kdev; | |
788 | struct phy_device *phydev; | |
789 | int i, ret; | |
790 | unsigned int size; | |
791 | char phy_id[MII_BUS_ID_SIZE + 3]; | |
792 | void *p; | |
793 | u32 val; | |
794 | ||
795 | priv = netdev_priv(dev); | |
796 | kdev = &priv->pdev->dev; | |
797 | ||
798 | if (priv->has_phy) { | |
799 | /* connect to PHY */ | |
800 | snprintf(phy_id, sizeof(phy_id), PHY_ID_FMT, | |
801 | priv->mac_id ? "1" : "0", priv->phy_id); | |
802 | ||
803 | phydev = phy_connect(dev, phy_id, &bcm_enet_adjust_phy_link, 0, | |
804 | PHY_INTERFACE_MODE_MII); | |
805 | ||
806 | if (IS_ERR(phydev)) { | |
807 | dev_err(kdev, "could not attach to PHY\n"); | |
808 | return PTR_ERR(phydev); | |
809 | } | |
810 | ||
811 | /* mask with MAC supported features */ | |
812 | phydev->supported &= (SUPPORTED_10baseT_Half | | |
813 | SUPPORTED_10baseT_Full | | |
814 | SUPPORTED_100baseT_Half | | |
815 | SUPPORTED_100baseT_Full | | |
816 | SUPPORTED_Autoneg | | |
817 | SUPPORTED_Pause | | |
818 | SUPPORTED_MII); | |
819 | phydev->advertising = phydev->supported; | |
820 | ||
821 | if (priv->pause_auto && priv->pause_rx && priv->pause_tx) | |
822 | phydev->advertising |= SUPPORTED_Pause; | |
823 | else | |
824 | phydev->advertising &= ~SUPPORTED_Pause; | |
825 | ||
826 | dev_info(kdev, "attached PHY at address %d [%s]\n", | |
827 | phydev->addr, phydev->drv->name); | |
828 | ||
829 | priv->old_link = 0; | |
830 | priv->old_duplex = -1; | |
831 | priv->old_pause = -1; | |
832 | priv->phydev = phydev; | |
833 | } | |
834 | ||
835 | /* mask all interrupts and request them */ | |
836 | enet_writel(priv, 0, ENET_IRMASK_REG); | |
837 | enet_dma_writel(priv, 0, ENETDMA_IRMASK_REG(priv->rx_chan)); | |
838 | enet_dma_writel(priv, 0, ENETDMA_IRMASK_REG(priv->tx_chan)); | |
839 | ||
840 | ret = request_irq(dev->irq, bcm_enet_isr_mac, 0, dev->name, dev); | |
841 | if (ret) | |
842 | goto out_phy_disconnect; | |
843 | ||
844 | ret = request_irq(priv->irq_rx, bcm_enet_isr_dma, | |
845 | IRQF_SAMPLE_RANDOM | IRQF_DISABLED, dev->name, dev); | |
846 | if (ret) | |
847 | goto out_freeirq; | |
848 | ||
849 | ret = request_irq(priv->irq_tx, bcm_enet_isr_dma, | |
850 | IRQF_DISABLED, dev->name, dev); | |
851 | if (ret) | |
852 | goto out_freeirq_rx; | |
853 | ||
854 | /* initialize perfect match registers */ | |
855 | for (i = 0; i < 4; i++) { | |
856 | enet_writel(priv, 0, ENET_PML_REG(i)); | |
857 | enet_writel(priv, 0, ENET_PMH_REG(i)); | |
858 | } | |
859 | ||
860 | /* write device mac address */ | |
861 | memcpy(addr.sa_data, dev->dev_addr, ETH_ALEN); | |
862 | bcm_enet_set_mac_address(dev, &addr); | |
863 | ||
864 | /* allocate rx dma ring */ | |
865 | size = priv->rx_ring_size * sizeof(struct bcm_enet_desc); | |
866 | p = dma_alloc_coherent(kdev, size, &priv->rx_desc_dma, GFP_KERNEL); | |
867 | if (!p) { | |
868 | dev_err(kdev, "cannot allocate rx ring %u\n", size); | |
869 | ret = -ENOMEM; | |
870 | goto out_freeirq_tx; | |
871 | } | |
872 | ||
873 | memset(p, 0, size); | |
874 | priv->rx_desc_alloc_size = size; | |
875 | priv->rx_desc_cpu = p; | |
876 | ||
877 | /* allocate tx dma ring */ | |
878 | size = priv->tx_ring_size * sizeof(struct bcm_enet_desc); | |
879 | p = dma_alloc_coherent(kdev, size, &priv->tx_desc_dma, GFP_KERNEL); | |
880 | if (!p) { | |
881 | dev_err(kdev, "cannot allocate tx ring\n"); | |
882 | ret = -ENOMEM; | |
883 | goto out_free_rx_ring; | |
884 | } | |
885 | ||
886 | memset(p, 0, size); | |
887 | priv->tx_desc_alloc_size = size; | |
888 | priv->tx_desc_cpu = p; | |
889 | ||
890 | priv->tx_skb = kzalloc(sizeof(struct sk_buff *) * priv->tx_ring_size, | |
891 | GFP_KERNEL); | |
892 | if (!priv->tx_skb) { | |
893 | dev_err(kdev, "cannot allocate rx skb queue\n"); | |
894 | ret = -ENOMEM; | |
895 | goto out_free_tx_ring; | |
896 | } | |
897 | ||
898 | priv->tx_desc_count = priv->tx_ring_size; | |
899 | priv->tx_dirty_desc = 0; | |
900 | priv->tx_curr_desc = 0; | |
901 | spin_lock_init(&priv->tx_lock); | |
902 | ||
903 | /* init & fill rx ring with skbs */ | |
904 | priv->rx_skb = kzalloc(sizeof(struct sk_buff *) * priv->rx_ring_size, | |
905 | GFP_KERNEL); | |
906 | if (!priv->rx_skb) { | |
907 | dev_err(kdev, "cannot allocate rx skb queue\n"); | |
908 | ret = -ENOMEM; | |
909 | goto out_free_tx_skb; | |
910 | } | |
911 | ||
912 | priv->rx_desc_count = 0; | |
913 | priv->rx_dirty_desc = 0; | |
914 | priv->rx_curr_desc = 0; | |
915 | ||
916 | /* initialize flow control buffer allocation */ | |
917 | enet_dma_writel(priv, ENETDMA_BUFALLOC_FORCE_MASK | 0, | |
918 | ENETDMA_BUFALLOC_REG(priv->rx_chan)); | |
919 | ||
920 | if (bcm_enet_refill_rx(dev)) { | |
921 | dev_err(kdev, "cannot allocate rx skb queue\n"); | |
922 | ret = -ENOMEM; | |
923 | goto out; | |
924 | } | |
925 | ||
926 | /* write rx & tx ring addresses */ | |
927 | enet_dma_writel(priv, priv->rx_desc_dma, | |
928 | ENETDMA_RSTART_REG(priv->rx_chan)); | |
929 | enet_dma_writel(priv, priv->tx_desc_dma, | |
930 | ENETDMA_RSTART_REG(priv->tx_chan)); | |
931 | ||
932 | /* clear remaining state ram for rx & tx channel */ | |
933 | enet_dma_writel(priv, 0, ENETDMA_SRAM2_REG(priv->rx_chan)); | |
934 | enet_dma_writel(priv, 0, ENETDMA_SRAM2_REG(priv->tx_chan)); | |
935 | enet_dma_writel(priv, 0, ENETDMA_SRAM3_REG(priv->rx_chan)); | |
936 | enet_dma_writel(priv, 0, ENETDMA_SRAM3_REG(priv->tx_chan)); | |
937 | enet_dma_writel(priv, 0, ENETDMA_SRAM4_REG(priv->rx_chan)); | |
938 | enet_dma_writel(priv, 0, ENETDMA_SRAM4_REG(priv->tx_chan)); | |
939 | ||
940 | /* set max rx/tx length */ | |
941 | enet_writel(priv, priv->hw_mtu, ENET_RXMAXLEN_REG); | |
942 | enet_writel(priv, priv->hw_mtu, ENET_TXMAXLEN_REG); | |
943 | ||
944 | /* set dma maximum burst len */ | |
945 | enet_dma_writel(priv, BCMENET_DMA_MAXBURST, | |
946 | ENETDMA_MAXBURST_REG(priv->rx_chan)); | |
947 | enet_dma_writel(priv, BCMENET_DMA_MAXBURST, | |
948 | ENETDMA_MAXBURST_REG(priv->tx_chan)); | |
949 | ||
950 | /* set correct transmit fifo watermark */ | |
951 | enet_writel(priv, BCMENET_TX_FIFO_TRESH, ENET_TXWMARK_REG); | |
952 | ||
953 | /* set flow control low/high threshold to 1/3 / 2/3 */ | |
954 | val = priv->rx_ring_size / 3; | |
955 | enet_dma_writel(priv, val, ENETDMA_FLOWCL_REG(priv->rx_chan)); | |
956 | val = (priv->rx_ring_size * 2) / 3; | |
957 | enet_dma_writel(priv, val, ENETDMA_FLOWCH_REG(priv->rx_chan)); | |
958 | ||
959 | /* all set, enable mac and interrupts, start dma engine and | |
960 | * kick rx dma channel */ | |
961 | wmb(); | |
962 | enet_writel(priv, ENET_CTL_ENABLE_MASK, ENET_CTL_REG); | |
963 | enet_dma_writel(priv, ENETDMA_CFG_EN_MASK, ENETDMA_CFG_REG); | |
964 | enet_dma_writel(priv, ENETDMA_CHANCFG_EN_MASK, | |
965 | ENETDMA_CHANCFG_REG(priv->rx_chan)); | |
966 | ||
967 | /* watch "mib counters about to overflow" interrupt */ | |
968 | enet_writel(priv, ENET_IR_MIB, ENET_IR_REG); | |
969 | enet_writel(priv, ENET_IR_MIB, ENET_IRMASK_REG); | |
970 | ||
971 | /* watch "packet transferred" interrupt in rx and tx */ | |
972 | enet_dma_writel(priv, ENETDMA_IR_PKTDONE_MASK, | |
973 | ENETDMA_IR_REG(priv->rx_chan)); | |
974 | enet_dma_writel(priv, ENETDMA_IR_PKTDONE_MASK, | |
975 | ENETDMA_IR_REG(priv->tx_chan)); | |
976 | ||
977 | /* make sure we enable napi before rx interrupt */ | |
978 | napi_enable(&priv->napi); | |
979 | ||
980 | enet_dma_writel(priv, ENETDMA_IR_PKTDONE_MASK, | |
981 | ENETDMA_IRMASK_REG(priv->rx_chan)); | |
982 | enet_dma_writel(priv, ENETDMA_IR_PKTDONE_MASK, | |
983 | ENETDMA_IRMASK_REG(priv->tx_chan)); | |
984 | ||
985 | if (priv->has_phy) | |
986 | phy_start(priv->phydev); | |
987 | else | |
988 | bcm_enet_adjust_link(dev); | |
989 | ||
990 | netif_start_queue(dev); | |
991 | return 0; | |
992 | ||
993 | out: | |
994 | for (i = 0; i < priv->rx_ring_size; i++) { | |
995 | struct bcm_enet_desc *desc; | |
996 | ||
997 | if (!priv->rx_skb[i]) | |
998 | continue; | |
999 | ||
1000 | desc = &priv->rx_desc_cpu[i]; | |
1001 | dma_unmap_single(kdev, desc->address, priv->rx_skb_size, | |
1002 | DMA_FROM_DEVICE); | |
1003 | kfree_skb(priv->rx_skb[i]); | |
1004 | } | |
1005 | kfree(priv->rx_skb); | |
1006 | ||
1007 | out_free_tx_skb: | |
1008 | kfree(priv->tx_skb); | |
1009 | ||
1010 | out_free_tx_ring: | |
1011 | dma_free_coherent(kdev, priv->tx_desc_alloc_size, | |
1012 | priv->tx_desc_cpu, priv->tx_desc_dma); | |
1013 | ||
1014 | out_free_rx_ring: | |
1015 | dma_free_coherent(kdev, priv->rx_desc_alloc_size, | |
1016 | priv->rx_desc_cpu, priv->rx_desc_dma); | |
1017 | ||
1018 | out_freeirq_tx: | |
1019 | free_irq(priv->irq_tx, dev); | |
1020 | ||
1021 | out_freeirq_rx: | |
1022 | free_irq(priv->irq_rx, dev); | |
1023 | ||
1024 | out_freeirq: | |
1025 | free_irq(dev->irq, dev); | |
1026 | ||
1027 | out_phy_disconnect: | |
1028 | phy_disconnect(priv->phydev); | |
1029 | ||
1030 | return ret; | |
1031 | } | |
1032 | ||
1033 | /* | |
1034 | * disable mac | |
1035 | */ | |
1036 | static void bcm_enet_disable_mac(struct bcm_enet_priv *priv) | |
1037 | { | |
1038 | int limit; | |
1039 | u32 val; | |
1040 | ||
1041 | val = enet_readl(priv, ENET_CTL_REG); | |
1042 | val |= ENET_CTL_DISABLE_MASK; | |
1043 | enet_writel(priv, val, ENET_CTL_REG); | |
1044 | ||
1045 | limit = 1000; | |
1046 | do { | |
1047 | u32 val; | |
1048 | ||
1049 | val = enet_readl(priv, ENET_CTL_REG); | |
1050 | if (!(val & ENET_CTL_DISABLE_MASK)) | |
1051 | break; | |
1052 | udelay(1); | |
1053 | } while (limit--); | |
1054 | } | |
1055 | ||
1056 | /* | |
1057 | * disable dma in given channel | |
1058 | */ | |
1059 | static void bcm_enet_disable_dma(struct bcm_enet_priv *priv, int chan) | |
1060 | { | |
1061 | int limit; | |
1062 | ||
1063 | enet_dma_writel(priv, 0, ENETDMA_CHANCFG_REG(chan)); | |
1064 | ||
1065 | limit = 1000; | |
1066 | do { | |
1067 | u32 val; | |
1068 | ||
1069 | val = enet_dma_readl(priv, ENETDMA_CHANCFG_REG(chan)); | |
1070 | if (!(val & ENETDMA_CHANCFG_EN_MASK)) | |
1071 | break; | |
1072 | udelay(1); | |
1073 | } while (limit--); | |
1074 | } | |
1075 | ||
1076 | /* | |
1077 | * stop callback | |
1078 | */ | |
1079 | static int bcm_enet_stop(struct net_device *dev) | |
1080 | { | |
1081 | struct bcm_enet_priv *priv; | |
1082 | struct device *kdev; | |
1083 | int i; | |
1084 | ||
1085 | priv = netdev_priv(dev); | |
1086 | kdev = &priv->pdev->dev; | |
1087 | ||
1088 | netif_stop_queue(dev); | |
1089 | napi_disable(&priv->napi); | |
1090 | if (priv->has_phy) | |
1091 | phy_stop(priv->phydev); | |
1092 | del_timer_sync(&priv->rx_timeout); | |
1093 | ||
1094 | /* mask all interrupts */ | |
1095 | enet_writel(priv, 0, ENET_IRMASK_REG); | |
1096 | enet_dma_writel(priv, 0, ENETDMA_IRMASK_REG(priv->rx_chan)); | |
1097 | enet_dma_writel(priv, 0, ENETDMA_IRMASK_REG(priv->tx_chan)); | |
1098 | ||
1099 | /* make sure no mib update is scheduled */ | |
1100 | flush_scheduled_work(); | |
1101 | ||
1102 | /* disable dma & mac */ | |
1103 | bcm_enet_disable_dma(priv, priv->tx_chan); | |
1104 | bcm_enet_disable_dma(priv, priv->rx_chan); | |
1105 | bcm_enet_disable_mac(priv); | |
1106 | ||
1107 | /* force reclaim of all tx buffers */ | |
1108 | bcm_enet_tx_reclaim(dev, 1); | |
1109 | ||
1110 | /* free the rx skb ring */ | |
1111 | for (i = 0; i < priv->rx_ring_size; i++) { | |
1112 | struct bcm_enet_desc *desc; | |
1113 | ||
1114 | if (!priv->rx_skb[i]) | |
1115 | continue; | |
1116 | ||
1117 | desc = &priv->rx_desc_cpu[i]; | |
1118 | dma_unmap_single(kdev, desc->address, priv->rx_skb_size, | |
1119 | DMA_FROM_DEVICE); | |
1120 | kfree_skb(priv->rx_skb[i]); | |
1121 | } | |
1122 | ||
1123 | /* free remaining allocated memory */ | |
1124 | kfree(priv->rx_skb); | |
1125 | kfree(priv->tx_skb); | |
1126 | dma_free_coherent(kdev, priv->rx_desc_alloc_size, | |
1127 | priv->rx_desc_cpu, priv->rx_desc_dma); | |
1128 | dma_free_coherent(kdev, priv->tx_desc_alloc_size, | |
1129 | priv->tx_desc_cpu, priv->tx_desc_dma); | |
1130 | free_irq(priv->irq_tx, dev); | |
1131 | free_irq(priv->irq_rx, dev); | |
1132 | free_irq(dev->irq, dev); | |
1133 | ||
1134 | /* release phy */ | |
1135 | if (priv->has_phy) { | |
1136 | phy_disconnect(priv->phydev); | |
1137 | priv->phydev = NULL; | |
1138 | } | |
1139 | ||
1140 | return 0; | |
1141 | } | |
1142 | ||
1143 | /* | |
1144 | * core request to return device rx/tx stats | |
1145 | */ | |
1146 | static struct net_device_stats *bcm_enet_get_stats(struct net_device *dev) | |
1147 | { | |
1148 | struct bcm_enet_priv *priv; | |
1149 | ||
1150 | priv = netdev_priv(dev); | |
1151 | return &priv->stats; | |
1152 | } | |
1153 | ||
1154 | /* | |
1155 | * ethtool callbacks | |
1156 | */ | |
1157 | struct bcm_enet_stats { | |
1158 | char stat_string[ETH_GSTRING_LEN]; | |
1159 | int sizeof_stat; | |
1160 | int stat_offset; | |
1161 | int mib_reg; | |
1162 | }; | |
1163 | ||
1164 | #define GEN_STAT(m) sizeof(((struct bcm_enet_priv *)0)->m), \ | |
1165 | offsetof(struct bcm_enet_priv, m) | |
1166 | ||
1167 | static const struct bcm_enet_stats bcm_enet_gstrings_stats[] = { | |
1168 | { "rx_packets", GEN_STAT(stats.rx_packets), -1 }, | |
1169 | { "tx_packets", GEN_STAT(stats.tx_packets), -1 }, | |
1170 | { "rx_bytes", GEN_STAT(stats.rx_bytes), -1 }, | |
1171 | { "tx_bytes", GEN_STAT(stats.tx_bytes), -1 }, | |
1172 | { "rx_errors", GEN_STAT(stats.rx_errors), -1 }, | |
1173 | { "tx_errors", GEN_STAT(stats.tx_errors), -1 }, | |
1174 | { "rx_dropped", GEN_STAT(stats.rx_dropped), -1 }, | |
1175 | { "tx_dropped", GEN_STAT(stats.tx_dropped), -1 }, | |
1176 | ||
1177 | { "rx_good_octets", GEN_STAT(mib.rx_gd_octets), ETH_MIB_RX_GD_OCTETS}, | |
1178 | { "rx_good_pkts", GEN_STAT(mib.rx_gd_pkts), ETH_MIB_RX_GD_PKTS }, | |
1179 | { "rx_broadcast", GEN_STAT(mib.rx_brdcast), ETH_MIB_RX_BRDCAST }, | |
1180 | { "rx_multicast", GEN_STAT(mib.rx_mult), ETH_MIB_RX_MULT }, | |
1181 | { "rx_64_octets", GEN_STAT(mib.rx_64), ETH_MIB_RX_64 }, | |
1182 | { "rx_65_127_oct", GEN_STAT(mib.rx_65_127), ETH_MIB_RX_65_127 }, | |
1183 | { "rx_128_255_oct", GEN_STAT(mib.rx_128_255), ETH_MIB_RX_128_255 }, | |
1184 | { "rx_256_511_oct", GEN_STAT(mib.rx_256_511), ETH_MIB_RX_256_511 }, | |
1185 | { "rx_512_1023_oct", GEN_STAT(mib.rx_512_1023), ETH_MIB_RX_512_1023 }, | |
1186 | { "rx_1024_max_oct", GEN_STAT(mib.rx_1024_max), ETH_MIB_RX_1024_MAX }, | |
1187 | { "rx_jabber", GEN_STAT(mib.rx_jab), ETH_MIB_RX_JAB }, | |
1188 | { "rx_oversize", GEN_STAT(mib.rx_ovr), ETH_MIB_RX_OVR }, | |
1189 | { "rx_fragment", GEN_STAT(mib.rx_frag), ETH_MIB_RX_FRAG }, | |
1190 | { "rx_dropped", GEN_STAT(mib.rx_drop), ETH_MIB_RX_DROP }, | |
1191 | { "rx_crc_align", GEN_STAT(mib.rx_crc_align), ETH_MIB_RX_CRC_ALIGN }, | |
1192 | { "rx_undersize", GEN_STAT(mib.rx_und), ETH_MIB_RX_UND }, | |
1193 | { "rx_crc", GEN_STAT(mib.rx_crc), ETH_MIB_RX_CRC }, | |
1194 | { "rx_align", GEN_STAT(mib.rx_align), ETH_MIB_RX_ALIGN }, | |
1195 | { "rx_symbol_error", GEN_STAT(mib.rx_sym), ETH_MIB_RX_SYM }, | |
1196 | { "rx_pause", GEN_STAT(mib.rx_pause), ETH_MIB_RX_PAUSE }, | |
1197 | { "rx_control", GEN_STAT(mib.rx_cntrl), ETH_MIB_RX_CNTRL }, | |
1198 | ||
1199 | { "tx_good_octets", GEN_STAT(mib.tx_gd_octets), ETH_MIB_TX_GD_OCTETS }, | |
1200 | { "tx_good_pkts", GEN_STAT(mib.tx_gd_pkts), ETH_MIB_TX_GD_PKTS }, | |
1201 | { "tx_broadcast", GEN_STAT(mib.tx_brdcast), ETH_MIB_TX_BRDCAST }, | |
1202 | { "tx_multicast", GEN_STAT(mib.tx_mult), ETH_MIB_TX_MULT }, | |
1203 | { "tx_64_oct", GEN_STAT(mib.tx_64), ETH_MIB_TX_64 }, | |
1204 | { "tx_65_127_oct", GEN_STAT(mib.tx_65_127), ETH_MIB_TX_65_127 }, | |
1205 | { "tx_128_255_oct", GEN_STAT(mib.tx_128_255), ETH_MIB_TX_128_255 }, | |
1206 | { "tx_256_511_oct", GEN_STAT(mib.tx_256_511), ETH_MIB_TX_256_511 }, | |
1207 | { "tx_512_1023_oct", GEN_STAT(mib.tx_512_1023), ETH_MIB_TX_512_1023}, | |
1208 | { "tx_1024_max_oct", GEN_STAT(mib.tx_1024_max), ETH_MIB_TX_1024_MAX }, | |
1209 | { "tx_jabber", GEN_STAT(mib.tx_jab), ETH_MIB_TX_JAB }, | |
1210 | { "tx_oversize", GEN_STAT(mib.tx_ovr), ETH_MIB_TX_OVR }, | |
1211 | { "tx_fragment", GEN_STAT(mib.tx_frag), ETH_MIB_TX_FRAG }, | |
1212 | { "tx_underrun", GEN_STAT(mib.tx_underrun), ETH_MIB_TX_UNDERRUN }, | |
1213 | { "tx_collisions", GEN_STAT(mib.tx_col), ETH_MIB_TX_COL }, | |
1214 | { "tx_single_collision", GEN_STAT(mib.tx_1_col), ETH_MIB_TX_1_COL }, | |
1215 | { "tx_multiple_collision", GEN_STAT(mib.tx_m_col), ETH_MIB_TX_M_COL }, | |
1216 | { "tx_excess_collision", GEN_STAT(mib.tx_ex_col), ETH_MIB_TX_EX_COL }, | |
1217 | { "tx_late_collision", GEN_STAT(mib.tx_late), ETH_MIB_TX_LATE }, | |
1218 | { "tx_deferred", GEN_STAT(mib.tx_def), ETH_MIB_TX_DEF }, | |
1219 | { "tx_carrier_sense", GEN_STAT(mib.tx_crs), ETH_MIB_TX_CRS }, | |
1220 | { "tx_pause", GEN_STAT(mib.tx_pause), ETH_MIB_TX_PAUSE }, | |
1221 | ||
1222 | }; | |
1223 | ||
1224 | #define BCM_ENET_STATS_LEN \ | |
1225 | (sizeof(bcm_enet_gstrings_stats) / sizeof(struct bcm_enet_stats)) | |
1226 | ||
1227 | static const u32 unused_mib_regs[] = { | |
1228 | ETH_MIB_TX_ALL_OCTETS, | |
1229 | ETH_MIB_TX_ALL_PKTS, | |
1230 | ETH_MIB_RX_ALL_OCTETS, | |
1231 | ETH_MIB_RX_ALL_PKTS, | |
1232 | }; | |
1233 | ||
1234 | ||
1235 | static void bcm_enet_get_drvinfo(struct net_device *netdev, | |
1236 | struct ethtool_drvinfo *drvinfo) | |
1237 | { | |
1238 | strncpy(drvinfo->driver, bcm_enet_driver_name, 32); | |
1239 | strncpy(drvinfo->version, bcm_enet_driver_version, 32); | |
1240 | strncpy(drvinfo->fw_version, "N/A", 32); | |
1241 | strncpy(drvinfo->bus_info, "bcm63xx", 32); | |
1242 | drvinfo->n_stats = BCM_ENET_STATS_LEN; | |
1243 | } | |
1244 | ||
a3f92eea FF |
1245 | static int bcm_enet_get_sset_count(struct net_device *netdev, |
1246 | int string_set) | |
9b1fc55a | 1247 | { |
a3f92eea FF |
1248 | switch (string_set) { |
1249 | case ETH_SS_STATS: | |
1250 | return BCM_ENET_STATS_LEN; | |
1251 | default: | |
1252 | return -EINVAL; | |
1253 | } | |
9b1fc55a MB |
1254 | } |
1255 | ||
1256 | static void bcm_enet_get_strings(struct net_device *netdev, | |
1257 | u32 stringset, u8 *data) | |
1258 | { | |
1259 | int i; | |
1260 | ||
1261 | switch (stringset) { | |
1262 | case ETH_SS_STATS: | |
1263 | for (i = 0; i < BCM_ENET_STATS_LEN; i++) { | |
1264 | memcpy(data + i * ETH_GSTRING_LEN, | |
1265 | bcm_enet_gstrings_stats[i].stat_string, | |
1266 | ETH_GSTRING_LEN); | |
1267 | } | |
1268 | break; | |
1269 | } | |
1270 | } | |
1271 | ||
1272 | static void update_mib_counters(struct bcm_enet_priv *priv) | |
1273 | { | |
1274 | int i; | |
1275 | ||
1276 | for (i = 0; i < BCM_ENET_STATS_LEN; i++) { | |
1277 | const struct bcm_enet_stats *s; | |
1278 | u32 val; | |
1279 | char *p; | |
1280 | ||
1281 | s = &bcm_enet_gstrings_stats[i]; | |
1282 | if (s->mib_reg == -1) | |
1283 | continue; | |
1284 | ||
1285 | val = enet_readl(priv, ENET_MIB_REG(s->mib_reg)); | |
1286 | p = (char *)priv + s->stat_offset; | |
1287 | ||
1288 | if (s->sizeof_stat == sizeof(u64)) | |
1289 | *(u64 *)p += val; | |
1290 | else | |
1291 | *(u32 *)p += val; | |
1292 | } | |
1293 | ||
1294 | /* also empty unused mib counters to make sure mib counter | |
1295 | * overflow interrupt is cleared */ | |
1296 | for (i = 0; i < ARRAY_SIZE(unused_mib_regs); i++) | |
1297 | (void)enet_readl(priv, ENET_MIB_REG(unused_mib_regs[i])); | |
1298 | } | |
1299 | ||
1300 | static void bcm_enet_update_mib_counters_defer(struct work_struct *t) | |
1301 | { | |
1302 | struct bcm_enet_priv *priv; | |
1303 | ||
1304 | priv = container_of(t, struct bcm_enet_priv, mib_update_task); | |
1305 | mutex_lock(&priv->mib_update_lock); | |
1306 | update_mib_counters(priv); | |
1307 | mutex_unlock(&priv->mib_update_lock); | |
1308 | ||
1309 | /* reenable mib interrupt */ | |
1310 | if (netif_running(priv->net_dev)) | |
1311 | enet_writel(priv, ENET_IR_MIB, ENET_IRMASK_REG); | |
1312 | } | |
1313 | ||
1314 | static void bcm_enet_get_ethtool_stats(struct net_device *netdev, | |
1315 | struct ethtool_stats *stats, | |
1316 | u64 *data) | |
1317 | { | |
1318 | struct bcm_enet_priv *priv; | |
1319 | int i; | |
1320 | ||
1321 | priv = netdev_priv(netdev); | |
1322 | ||
1323 | mutex_lock(&priv->mib_update_lock); | |
1324 | update_mib_counters(priv); | |
1325 | ||
1326 | for (i = 0; i < BCM_ENET_STATS_LEN; i++) { | |
1327 | const struct bcm_enet_stats *s; | |
1328 | char *p; | |
1329 | ||
1330 | s = &bcm_enet_gstrings_stats[i]; | |
1331 | p = (char *)priv + s->stat_offset; | |
1332 | data[i] = (s->sizeof_stat == sizeof(u64)) ? | |
1333 | *(u64 *)p : *(u32 *)p; | |
1334 | } | |
1335 | mutex_unlock(&priv->mib_update_lock); | |
1336 | } | |
1337 | ||
1338 | static int bcm_enet_get_settings(struct net_device *dev, | |
1339 | struct ethtool_cmd *cmd) | |
1340 | { | |
1341 | struct bcm_enet_priv *priv; | |
1342 | ||
1343 | priv = netdev_priv(dev); | |
1344 | ||
1345 | cmd->maxrxpkt = 0; | |
1346 | cmd->maxtxpkt = 0; | |
1347 | ||
1348 | if (priv->has_phy) { | |
1349 | if (!priv->phydev) | |
1350 | return -ENODEV; | |
1351 | return phy_ethtool_gset(priv->phydev, cmd); | |
1352 | } else { | |
1353 | cmd->autoneg = 0; | |
1354 | cmd->speed = (priv->force_speed_100) ? SPEED_100 : SPEED_10; | |
1355 | cmd->duplex = (priv->force_duplex_full) ? | |
1356 | DUPLEX_FULL : DUPLEX_HALF; | |
1357 | cmd->supported = ADVERTISED_10baseT_Half | | |
1358 | ADVERTISED_10baseT_Full | | |
1359 | ADVERTISED_100baseT_Half | | |
1360 | ADVERTISED_100baseT_Full; | |
1361 | cmd->advertising = 0; | |
1362 | cmd->port = PORT_MII; | |
1363 | cmd->transceiver = XCVR_EXTERNAL; | |
1364 | } | |
1365 | return 0; | |
1366 | } | |
1367 | ||
1368 | static int bcm_enet_set_settings(struct net_device *dev, | |
1369 | struct ethtool_cmd *cmd) | |
1370 | { | |
1371 | struct bcm_enet_priv *priv; | |
1372 | ||
1373 | priv = netdev_priv(dev); | |
1374 | if (priv->has_phy) { | |
1375 | if (!priv->phydev) | |
1376 | return -ENODEV; | |
1377 | return phy_ethtool_sset(priv->phydev, cmd); | |
1378 | } else { | |
1379 | ||
1380 | if (cmd->autoneg || | |
1381 | (cmd->speed != SPEED_100 && cmd->speed != SPEED_10) || | |
1382 | cmd->port != PORT_MII) | |
1383 | return -EINVAL; | |
1384 | ||
1385 | priv->force_speed_100 = (cmd->speed == SPEED_100) ? 1 : 0; | |
1386 | priv->force_duplex_full = (cmd->duplex == DUPLEX_FULL) ? 1 : 0; | |
1387 | ||
1388 | if (netif_running(dev)) | |
1389 | bcm_enet_adjust_link(dev); | |
1390 | return 0; | |
1391 | } | |
1392 | } | |
1393 | ||
1394 | static void bcm_enet_get_ringparam(struct net_device *dev, | |
1395 | struct ethtool_ringparam *ering) | |
1396 | { | |
1397 | struct bcm_enet_priv *priv; | |
1398 | ||
1399 | priv = netdev_priv(dev); | |
1400 | ||
1401 | /* rx/tx ring is actually only limited by memory */ | |
1402 | ering->rx_max_pending = 8192; | |
1403 | ering->tx_max_pending = 8192; | |
1404 | ering->rx_mini_max_pending = 0; | |
1405 | ering->rx_jumbo_max_pending = 0; | |
1406 | ering->rx_pending = priv->rx_ring_size; | |
1407 | ering->tx_pending = priv->tx_ring_size; | |
1408 | } | |
1409 | ||
1410 | static int bcm_enet_set_ringparam(struct net_device *dev, | |
1411 | struct ethtool_ringparam *ering) | |
1412 | { | |
1413 | struct bcm_enet_priv *priv; | |
1414 | int was_running; | |
1415 | ||
1416 | priv = netdev_priv(dev); | |
1417 | ||
1418 | was_running = 0; | |
1419 | if (netif_running(dev)) { | |
1420 | bcm_enet_stop(dev); | |
1421 | was_running = 1; | |
1422 | } | |
1423 | ||
1424 | priv->rx_ring_size = ering->rx_pending; | |
1425 | priv->tx_ring_size = ering->tx_pending; | |
1426 | ||
1427 | if (was_running) { | |
1428 | int err; | |
1429 | ||
1430 | err = bcm_enet_open(dev); | |
1431 | if (err) | |
1432 | dev_close(dev); | |
1433 | else | |
1434 | bcm_enet_set_multicast_list(dev); | |
1435 | } | |
1436 | return 0; | |
1437 | } | |
1438 | ||
1439 | static void bcm_enet_get_pauseparam(struct net_device *dev, | |
1440 | struct ethtool_pauseparam *ecmd) | |
1441 | { | |
1442 | struct bcm_enet_priv *priv; | |
1443 | ||
1444 | priv = netdev_priv(dev); | |
1445 | ecmd->autoneg = priv->pause_auto; | |
1446 | ecmd->rx_pause = priv->pause_rx; | |
1447 | ecmd->tx_pause = priv->pause_tx; | |
1448 | } | |
1449 | ||
1450 | static int bcm_enet_set_pauseparam(struct net_device *dev, | |
1451 | struct ethtool_pauseparam *ecmd) | |
1452 | { | |
1453 | struct bcm_enet_priv *priv; | |
1454 | ||
1455 | priv = netdev_priv(dev); | |
1456 | ||
1457 | if (priv->has_phy) { | |
1458 | if (ecmd->autoneg && (ecmd->rx_pause != ecmd->tx_pause)) { | |
1459 | /* asymetric pause mode not supported, | |
1460 | * actually possible but integrated PHY has RO | |
1461 | * asym_pause bit */ | |
1462 | return -EINVAL; | |
1463 | } | |
1464 | } else { | |
1465 | /* no pause autoneg on direct mii connection */ | |
1466 | if (ecmd->autoneg) | |
1467 | return -EINVAL; | |
1468 | } | |
1469 | ||
1470 | priv->pause_auto = ecmd->autoneg; | |
1471 | priv->pause_rx = ecmd->rx_pause; | |
1472 | priv->pause_tx = ecmd->tx_pause; | |
1473 | ||
1474 | return 0; | |
1475 | } | |
1476 | ||
1477 | static struct ethtool_ops bcm_enet_ethtool_ops = { | |
1478 | .get_strings = bcm_enet_get_strings, | |
a3f92eea | 1479 | .get_sset_count = bcm_enet_get_sset_count, |
9b1fc55a MB |
1480 | .get_ethtool_stats = bcm_enet_get_ethtool_stats, |
1481 | .get_settings = bcm_enet_get_settings, | |
1482 | .set_settings = bcm_enet_set_settings, | |
1483 | .get_drvinfo = bcm_enet_get_drvinfo, | |
1484 | .get_link = ethtool_op_get_link, | |
1485 | .get_ringparam = bcm_enet_get_ringparam, | |
1486 | .set_ringparam = bcm_enet_set_ringparam, | |
1487 | .get_pauseparam = bcm_enet_get_pauseparam, | |
1488 | .set_pauseparam = bcm_enet_set_pauseparam, | |
1489 | }; | |
1490 | ||
1491 | static int bcm_enet_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) | |
1492 | { | |
1493 | struct bcm_enet_priv *priv; | |
1494 | ||
1495 | priv = netdev_priv(dev); | |
1496 | if (priv->has_phy) { | |
1497 | if (!priv->phydev) | |
1498 | return -ENODEV; | |
1499 | return phy_mii_ioctl(priv->phydev, if_mii(rq), cmd); | |
1500 | } else { | |
1501 | struct mii_if_info mii; | |
1502 | ||
1503 | mii.dev = dev; | |
1504 | mii.mdio_read = bcm_enet_mdio_read_mii; | |
1505 | mii.mdio_write = bcm_enet_mdio_write_mii; | |
1506 | mii.phy_id = 0; | |
1507 | mii.phy_id_mask = 0x3f; | |
1508 | mii.reg_num_mask = 0x1f; | |
1509 | return generic_mii_ioctl(&mii, if_mii(rq), cmd, NULL); | |
1510 | } | |
1511 | } | |
1512 | ||
1513 | /* | |
1514 | * calculate actual hardware mtu | |
1515 | */ | |
1516 | static int compute_hw_mtu(struct bcm_enet_priv *priv, int mtu) | |
1517 | { | |
1518 | int actual_mtu; | |
1519 | ||
1520 | actual_mtu = mtu; | |
1521 | ||
1522 | /* add ethernet header + vlan tag size */ | |
1523 | actual_mtu += VLAN_ETH_HLEN; | |
1524 | ||
1525 | if (actual_mtu < 64 || actual_mtu > BCMENET_MAX_MTU) | |
1526 | return -EINVAL; | |
1527 | ||
1528 | /* | |
1529 | * setup maximum size before we get overflow mark in | |
1530 | * descriptor, note that this will not prevent reception of | |
1531 | * big frames, they will be split into multiple buffers | |
1532 | * anyway | |
1533 | */ | |
1534 | priv->hw_mtu = actual_mtu; | |
1535 | ||
1536 | /* | |
1537 | * align rx buffer size to dma burst len, account FCS since | |
1538 | * it's appended | |
1539 | */ | |
1540 | priv->rx_skb_size = ALIGN(actual_mtu + ETH_FCS_LEN, | |
1541 | BCMENET_DMA_MAXBURST * 4); | |
1542 | return 0; | |
1543 | } | |
1544 | ||
1545 | /* | |
1546 | * adjust mtu, can't be called while device is running | |
1547 | */ | |
1548 | static int bcm_enet_change_mtu(struct net_device *dev, int new_mtu) | |
1549 | { | |
1550 | int ret; | |
1551 | ||
1552 | if (netif_running(dev)) | |
1553 | return -EBUSY; | |
1554 | ||
1555 | ret = compute_hw_mtu(netdev_priv(dev), new_mtu); | |
1556 | if (ret) | |
1557 | return ret; | |
1558 | dev->mtu = new_mtu; | |
1559 | return 0; | |
1560 | } | |
1561 | ||
1562 | /* | |
1563 | * preinit hardware to allow mii operation while device is down | |
1564 | */ | |
1565 | static void bcm_enet_hw_preinit(struct bcm_enet_priv *priv) | |
1566 | { | |
1567 | u32 val; | |
1568 | int limit; | |
1569 | ||
1570 | /* make sure mac is disabled */ | |
1571 | bcm_enet_disable_mac(priv); | |
1572 | ||
1573 | /* soft reset mac */ | |
1574 | val = ENET_CTL_SRESET_MASK; | |
1575 | enet_writel(priv, val, ENET_CTL_REG); | |
1576 | wmb(); | |
1577 | ||
1578 | limit = 1000; | |
1579 | do { | |
1580 | val = enet_readl(priv, ENET_CTL_REG); | |
1581 | if (!(val & ENET_CTL_SRESET_MASK)) | |
1582 | break; | |
1583 | udelay(1); | |
1584 | } while (limit--); | |
1585 | ||
1586 | /* select correct mii interface */ | |
1587 | val = enet_readl(priv, ENET_CTL_REG); | |
1588 | if (priv->use_external_mii) | |
1589 | val |= ENET_CTL_EPHYSEL_MASK; | |
1590 | else | |
1591 | val &= ~ENET_CTL_EPHYSEL_MASK; | |
1592 | enet_writel(priv, val, ENET_CTL_REG); | |
1593 | ||
1594 | /* turn on mdc clock */ | |
1595 | enet_writel(priv, (0x1f << ENET_MIISC_MDCFREQDIV_SHIFT) | | |
1596 | ENET_MIISC_PREAMBLEEN_MASK, ENET_MIISC_REG); | |
1597 | ||
1598 | /* set mib counters to self-clear when read */ | |
1599 | val = enet_readl(priv, ENET_MIBCTL_REG); | |
1600 | val |= ENET_MIBCTL_RDCLEAR_MASK; | |
1601 | enet_writel(priv, val, ENET_MIBCTL_REG); | |
1602 | } | |
1603 | ||
1604 | static const struct net_device_ops bcm_enet_ops = { | |
1605 | .ndo_open = bcm_enet_open, | |
1606 | .ndo_stop = bcm_enet_stop, | |
1607 | .ndo_start_xmit = bcm_enet_start_xmit, | |
1608 | .ndo_get_stats = bcm_enet_get_stats, | |
1609 | .ndo_set_mac_address = bcm_enet_set_mac_address, | |
1610 | .ndo_set_multicast_list = bcm_enet_set_multicast_list, | |
1611 | .ndo_do_ioctl = bcm_enet_ioctl, | |
1612 | .ndo_change_mtu = bcm_enet_change_mtu, | |
1613 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
1614 | .ndo_poll_controller = bcm_enet_netpoll, | |
1615 | #endif | |
1616 | }; | |
1617 | ||
1618 | /* | |
1619 | * allocate netdevice, request register memory and register device. | |
1620 | */ | |
1621 | static int __devinit bcm_enet_probe(struct platform_device *pdev) | |
1622 | { | |
1623 | struct bcm_enet_priv *priv; | |
1624 | struct net_device *dev; | |
1625 | struct bcm63xx_enet_platform_data *pd; | |
1626 | struct resource *res_mem, *res_irq, *res_irq_rx, *res_irq_tx; | |
1627 | struct mii_bus *bus; | |
1628 | const char *clk_name; | |
1629 | unsigned int iomem_size; | |
1630 | int i, ret; | |
1631 | ||
1632 | /* stop if shared driver failed, assume driver->probe will be | |
1633 | * called in the same order we register devices (correct ?) */ | |
1634 | if (!bcm_enet_shared_base) | |
1635 | return -ENODEV; | |
1636 | ||
1637 | res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1638 | res_irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0); | |
1639 | res_irq_rx = platform_get_resource(pdev, IORESOURCE_IRQ, 1); | |
1640 | res_irq_tx = platform_get_resource(pdev, IORESOURCE_IRQ, 2); | |
1641 | if (!res_mem || !res_irq || !res_irq_rx || !res_irq_tx) | |
1642 | return -ENODEV; | |
1643 | ||
1644 | ret = 0; | |
1645 | dev = alloc_etherdev(sizeof(*priv)); | |
1646 | if (!dev) | |
1647 | return -ENOMEM; | |
1648 | priv = netdev_priv(dev); | |
1649 | memset(priv, 0, sizeof(*priv)); | |
1650 | ||
1651 | ret = compute_hw_mtu(priv, dev->mtu); | |
1652 | if (ret) | |
1653 | goto out; | |
1654 | ||
1655 | iomem_size = res_mem->end - res_mem->start + 1; | |
1656 | if (!request_mem_region(res_mem->start, iomem_size, "bcm63xx_enet")) { | |
1657 | ret = -EBUSY; | |
1658 | goto out; | |
1659 | } | |
1660 | ||
1661 | priv->base = ioremap(res_mem->start, iomem_size); | |
1662 | if (priv->base == NULL) { | |
1663 | ret = -ENOMEM; | |
1664 | goto out_release_mem; | |
1665 | } | |
1666 | dev->irq = priv->irq = res_irq->start; | |
1667 | priv->irq_rx = res_irq_rx->start; | |
1668 | priv->irq_tx = res_irq_tx->start; | |
1669 | priv->mac_id = pdev->id; | |
1670 | ||
1671 | /* get rx & tx dma channel id for this mac */ | |
1672 | if (priv->mac_id == 0) { | |
1673 | priv->rx_chan = 0; | |
1674 | priv->tx_chan = 1; | |
1675 | clk_name = "enet0"; | |
1676 | } else { | |
1677 | priv->rx_chan = 2; | |
1678 | priv->tx_chan = 3; | |
1679 | clk_name = "enet1"; | |
1680 | } | |
1681 | ||
1682 | priv->mac_clk = clk_get(&pdev->dev, clk_name); | |
1683 | if (IS_ERR(priv->mac_clk)) { | |
1684 | ret = PTR_ERR(priv->mac_clk); | |
1685 | goto out_unmap; | |
1686 | } | |
1687 | clk_enable(priv->mac_clk); | |
1688 | ||
1689 | /* initialize default and fetch platform data */ | |
1690 | priv->rx_ring_size = BCMENET_DEF_RX_DESC; | |
1691 | priv->tx_ring_size = BCMENET_DEF_TX_DESC; | |
1692 | ||
1693 | pd = pdev->dev.platform_data; | |
1694 | if (pd) { | |
1695 | memcpy(dev->dev_addr, pd->mac_addr, ETH_ALEN); | |
1696 | priv->has_phy = pd->has_phy; | |
1697 | priv->phy_id = pd->phy_id; | |
1698 | priv->has_phy_interrupt = pd->has_phy_interrupt; | |
1699 | priv->phy_interrupt = pd->phy_interrupt; | |
1700 | priv->use_external_mii = !pd->use_internal_phy; | |
1701 | priv->pause_auto = pd->pause_auto; | |
1702 | priv->pause_rx = pd->pause_rx; | |
1703 | priv->pause_tx = pd->pause_tx; | |
1704 | priv->force_duplex_full = pd->force_duplex_full; | |
1705 | priv->force_speed_100 = pd->force_speed_100; | |
1706 | } | |
1707 | ||
1708 | if (priv->mac_id == 0 && priv->has_phy && !priv->use_external_mii) { | |
1709 | /* using internal PHY, enable clock */ | |
1710 | priv->phy_clk = clk_get(&pdev->dev, "ephy"); | |
1711 | if (IS_ERR(priv->phy_clk)) { | |
1712 | ret = PTR_ERR(priv->phy_clk); | |
1713 | priv->phy_clk = NULL; | |
1714 | goto out_put_clk_mac; | |
1715 | } | |
1716 | clk_enable(priv->phy_clk); | |
1717 | } | |
1718 | ||
1719 | /* do minimal hardware init to be able to probe mii bus */ | |
1720 | bcm_enet_hw_preinit(priv); | |
1721 | ||
1722 | /* MII bus registration */ | |
1723 | if (priv->has_phy) { | |
1724 | ||
1725 | priv->mii_bus = mdiobus_alloc(); | |
1726 | if (!priv->mii_bus) { | |
1727 | ret = -ENOMEM; | |
1728 | goto out_uninit_hw; | |
1729 | } | |
1730 | ||
1731 | bus = priv->mii_bus; | |
1732 | bus->name = "bcm63xx_enet MII bus"; | |
1733 | bus->parent = &pdev->dev; | |
1734 | bus->priv = priv; | |
1735 | bus->read = bcm_enet_mdio_read_phylib; | |
1736 | bus->write = bcm_enet_mdio_write_phylib; | |
1737 | sprintf(bus->id, "%d", priv->mac_id); | |
1738 | ||
1739 | /* only probe bus where we think the PHY is, because | |
1740 | * the mdio read operation return 0 instead of 0xffff | |
1741 | * if a slave is not present on hw */ | |
1742 | bus->phy_mask = ~(1 << priv->phy_id); | |
1743 | ||
1744 | bus->irq = kmalloc(sizeof(int) * PHY_MAX_ADDR, GFP_KERNEL); | |
1745 | if (!bus->irq) { | |
1746 | ret = -ENOMEM; | |
1747 | goto out_free_mdio; | |
1748 | } | |
1749 | ||
1750 | if (priv->has_phy_interrupt) | |
1751 | bus->irq[priv->phy_id] = priv->phy_interrupt; | |
1752 | else | |
1753 | bus->irq[priv->phy_id] = PHY_POLL; | |
1754 | ||
1755 | ret = mdiobus_register(bus); | |
1756 | if (ret) { | |
1757 | dev_err(&pdev->dev, "unable to register mdio bus\n"); | |
1758 | goto out_free_mdio; | |
1759 | } | |
1760 | } else { | |
1761 | ||
1762 | /* run platform code to initialize PHY device */ | |
1763 | if (pd->mii_config && | |
1764 | pd->mii_config(dev, 1, bcm_enet_mdio_read_mii, | |
1765 | bcm_enet_mdio_write_mii)) { | |
1766 | dev_err(&pdev->dev, "unable to configure mdio bus\n"); | |
1767 | goto out_uninit_hw; | |
1768 | } | |
1769 | } | |
1770 | ||
1771 | spin_lock_init(&priv->rx_lock); | |
1772 | ||
1773 | /* init rx timeout (used for oom) */ | |
1774 | init_timer(&priv->rx_timeout); | |
1775 | priv->rx_timeout.function = bcm_enet_refill_rx_timer; | |
1776 | priv->rx_timeout.data = (unsigned long)dev; | |
1777 | ||
1778 | /* init the mib update lock&work */ | |
1779 | mutex_init(&priv->mib_update_lock); | |
1780 | INIT_WORK(&priv->mib_update_task, bcm_enet_update_mib_counters_defer); | |
1781 | ||
1782 | /* zero mib counters */ | |
1783 | for (i = 0; i < ENET_MIB_REG_COUNT; i++) | |
1784 | enet_writel(priv, 0, ENET_MIB_REG(i)); | |
1785 | ||
1786 | /* register netdevice */ | |
1787 | dev->netdev_ops = &bcm_enet_ops; | |
1788 | netif_napi_add(dev, &priv->napi, bcm_enet_poll, 16); | |
1789 | ||
1790 | SET_ETHTOOL_OPS(dev, &bcm_enet_ethtool_ops); | |
1791 | SET_NETDEV_DEV(dev, &pdev->dev); | |
1792 | ||
1793 | ret = register_netdev(dev); | |
1794 | if (ret) | |
1795 | goto out_unregister_mdio; | |
1796 | ||
1797 | netif_carrier_off(dev); | |
1798 | platform_set_drvdata(pdev, dev); | |
1799 | priv->pdev = pdev; | |
1800 | priv->net_dev = dev; | |
1801 | ||
1802 | return 0; | |
1803 | ||
1804 | out_unregister_mdio: | |
1805 | if (priv->mii_bus) { | |
1806 | mdiobus_unregister(priv->mii_bus); | |
1807 | kfree(priv->mii_bus->irq); | |
1808 | } | |
1809 | ||
1810 | out_free_mdio: | |
1811 | if (priv->mii_bus) | |
1812 | mdiobus_free(priv->mii_bus); | |
1813 | ||
1814 | out_uninit_hw: | |
1815 | /* turn off mdc clock */ | |
1816 | enet_writel(priv, 0, ENET_MIISC_REG); | |
1817 | if (priv->phy_clk) { | |
1818 | clk_disable(priv->phy_clk); | |
1819 | clk_put(priv->phy_clk); | |
1820 | } | |
1821 | ||
1822 | out_put_clk_mac: | |
1823 | clk_disable(priv->mac_clk); | |
1824 | clk_put(priv->mac_clk); | |
1825 | ||
1826 | out_unmap: | |
1827 | iounmap(priv->base); | |
1828 | ||
1829 | out_release_mem: | |
1830 | release_mem_region(res_mem->start, iomem_size); | |
1831 | out: | |
1832 | free_netdev(dev); | |
1833 | return ret; | |
1834 | } | |
1835 | ||
1836 | ||
1837 | /* | |
1838 | * exit func, stops hardware and unregisters netdevice | |
1839 | */ | |
1840 | static int __devexit bcm_enet_remove(struct platform_device *pdev) | |
1841 | { | |
1842 | struct bcm_enet_priv *priv; | |
1843 | struct net_device *dev; | |
1844 | struct resource *res; | |
1845 | ||
1846 | /* stop netdevice */ | |
1847 | dev = platform_get_drvdata(pdev); | |
1848 | priv = netdev_priv(dev); | |
1849 | unregister_netdev(dev); | |
1850 | ||
1851 | /* turn off mdc clock */ | |
1852 | enet_writel(priv, 0, ENET_MIISC_REG); | |
1853 | ||
1854 | if (priv->has_phy) { | |
1855 | mdiobus_unregister(priv->mii_bus); | |
1856 | kfree(priv->mii_bus->irq); | |
1857 | mdiobus_free(priv->mii_bus); | |
1858 | } else { | |
1859 | struct bcm63xx_enet_platform_data *pd; | |
1860 | ||
1861 | pd = pdev->dev.platform_data; | |
1862 | if (pd && pd->mii_config) | |
1863 | pd->mii_config(dev, 0, bcm_enet_mdio_read_mii, | |
1864 | bcm_enet_mdio_write_mii); | |
1865 | } | |
1866 | ||
1867 | /* release device resources */ | |
1868 | iounmap(priv->base); | |
1869 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1870 | release_mem_region(res->start, res->end - res->start + 1); | |
1871 | ||
1872 | /* disable hw block clocks */ | |
1873 | if (priv->phy_clk) { | |
1874 | clk_disable(priv->phy_clk); | |
1875 | clk_put(priv->phy_clk); | |
1876 | } | |
1877 | clk_disable(priv->mac_clk); | |
1878 | clk_put(priv->mac_clk); | |
1879 | ||
1880 | platform_set_drvdata(pdev, NULL); | |
1881 | free_netdev(dev); | |
1882 | return 0; | |
1883 | } | |
1884 | ||
1885 | struct platform_driver bcm63xx_enet_driver = { | |
1886 | .probe = bcm_enet_probe, | |
1887 | .remove = __devexit_p(bcm_enet_remove), | |
1888 | .driver = { | |
1889 | .name = "bcm63xx_enet", | |
1890 | .owner = THIS_MODULE, | |
1891 | }, | |
1892 | }; | |
1893 | ||
1894 | /* | |
1895 | * reserve & remap memory space shared between all macs | |
1896 | */ | |
1897 | static int __devinit bcm_enet_shared_probe(struct platform_device *pdev) | |
1898 | { | |
1899 | struct resource *res; | |
1900 | unsigned int iomem_size; | |
1901 | ||
1902 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1903 | if (!res) | |
1904 | return -ENODEV; | |
1905 | ||
1906 | iomem_size = res->end - res->start + 1; | |
1907 | if (!request_mem_region(res->start, iomem_size, "bcm63xx_enet_dma")) | |
1908 | return -EBUSY; | |
1909 | ||
1910 | bcm_enet_shared_base = ioremap(res->start, iomem_size); | |
1911 | if (!bcm_enet_shared_base) { | |
1912 | release_mem_region(res->start, iomem_size); | |
1913 | return -ENOMEM; | |
1914 | } | |
1915 | return 0; | |
1916 | } | |
1917 | ||
1918 | static int __devexit bcm_enet_shared_remove(struct platform_device *pdev) | |
1919 | { | |
1920 | struct resource *res; | |
1921 | ||
1922 | iounmap(bcm_enet_shared_base); | |
1923 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1924 | release_mem_region(res->start, res->end - res->start + 1); | |
1925 | return 0; | |
1926 | } | |
1927 | ||
1928 | /* | |
1929 | * this "shared" driver is needed because both macs share a single | |
1930 | * address space | |
1931 | */ | |
1932 | struct platform_driver bcm63xx_enet_shared_driver = { | |
1933 | .probe = bcm_enet_shared_probe, | |
1934 | .remove = __devexit_p(bcm_enet_shared_remove), | |
1935 | .driver = { | |
1936 | .name = "bcm63xx_enet_shared", | |
1937 | .owner = THIS_MODULE, | |
1938 | }, | |
1939 | }; | |
1940 | ||
1941 | /* | |
1942 | * entry point | |
1943 | */ | |
1944 | static int __init bcm_enet_init(void) | |
1945 | { | |
1946 | int ret; | |
1947 | ||
1948 | ret = platform_driver_register(&bcm63xx_enet_shared_driver); | |
1949 | if (ret) | |
1950 | return ret; | |
1951 | ||
1952 | ret = platform_driver_register(&bcm63xx_enet_driver); | |
1953 | if (ret) | |
1954 | platform_driver_unregister(&bcm63xx_enet_shared_driver); | |
1955 | ||
1956 | return ret; | |
1957 | } | |
1958 | ||
1959 | static void __exit bcm_enet_exit(void) | |
1960 | { | |
1961 | platform_driver_unregister(&bcm63xx_enet_driver); | |
1962 | platform_driver_unregister(&bcm63xx_enet_shared_driver); | |
1963 | } | |
1964 | ||
1965 | ||
1966 | module_init(bcm_enet_init); | |
1967 | module_exit(bcm_enet_exit); | |
1968 | ||
1969 | MODULE_DESCRIPTION("BCM63xx internal ethernet mac driver"); | |
1970 | MODULE_AUTHOR("Maxime Bizon <mbizon@freebox.fr>"); | |
1971 | MODULE_LICENSE("GPL"); |