Commit | Line | Data |
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6b7c5b94 | 1 | /* |
d2145cde | 2 | * Copyright (C) 2005 - 2011 Emulex |
6b7c5b94 SP |
3 | * All rights reserved. |
4 | * | |
5 | * This program is free software; you can redistribute it and/or | |
6 | * modify it under the terms of the GNU General Public License version 2 | |
7 | * as published by the Free Software Foundation. The full GNU General | |
8 | * Public License is included in this distribution in the file called COPYING. | |
9 | * | |
10 | * Contact Information: | |
d2145cde | 11 | * linux-drivers@emulex.com |
6b7c5b94 | 12 | * |
d2145cde AK |
13 | * Emulex |
14 | * 3333 Susan Street | |
15 | * Costa Mesa, CA 92626 | |
6b7c5b94 SP |
16 | */ |
17 | ||
18 | #ifndef BE_H | |
19 | #define BE_H | |
20 | ||
21 | #include <linux/pci.h> | |
22 | #include <linux/etherdevice.h> | |
23 | #include <linux/version.h> | |
24 | #include <linux/delay.h> | |
25 | #include <net/tcp.h> | |
26 | #include <net/ip.h> | |
27 | #include <net/ipv6.h> | |
28 | #include <linux/if_vlan.h> | |
29 | #include <linux/workqueue.h> | |
30 | #include <linux/interrupt.h> | |
84517482 | 31 | #include <linux/firmware.h> |
5a0e3ad6 | 32 | #include <linux/slab.h> |
6b7c5b94 SP |
33 | |
34 | #include "be_hw.h" | |
35 | ||
c888385a | 36 | #define DRV_VER "4.0.100u" |
6b7c5b94 SP |
37 | #define DRV_NAME "be2net" |
38 | #define BE_NAME "ServerEngines BladeEngine2 10Gbps NIC" | |
12d7ea2c | 39 | #define BE3_NAME "ServerEngines BladeEngine3 10Gbps NIC" |
c4ca2374 | 40 | #define OC_NAME "Emulex OneConnect 10Gbps NIC" |
fe6d2a38 SP |
41 | #define OC_NAME_BE OC_NAME "(be3)" |
42 | #define OC_NAME_LANCER OC_NAME "(Lancer)" | |
35ecf03c | 43 | #define DRV_DESC "ServerEngines BladeEngine 10Gbps NIC Driver" |
6b7c5b94 | 44 | |
c4ca2374 | 45 | #define BE_VENDOR_ID 0x19a2 |
fe6d2a38 | 46 | #define EMULEX_VENDOR_ID 0x10df |
c4ca2374 | 47 | #define BE_DEVICE_ID1 0x211 |
12d7ea2c | 48 | #define BE_DEVICE_ID2 0x221 |
fe6d2a38 SP |
49 | #define OC_DEVICE_ID1 0x700 /* Device Id for BE2 cards */ |
50 | #define OC_DEVICE_ID2 0x710 /* Device Id for BE3 cards */ | |
51 | #define OC_DEVICE_ID3 0xe220 /* Device id for Lancer cards */ | |
c4ca2374 AK |
52 | |
53 | static inline char *nic_name(struct pci_dev *pdev) | |
54 | { | |
12d7ea2c AK |
55 | switch (pdev->device) { |
56 | case OC_DEVICE_ID1: | |
c4ca2374 | 57 | return OC_NAME; |
e254f6ec | 58 | case OC_DEVICE_ID2: |
fe6d2a38 SP |
59 | return OC_NAME_BE; |
60 | case OC_DEVICE_ID3: | |
61 | return OC_NAME_LANCER; | |
12d7ea2c AK |
62 | case BE_DEVICE_ID2: |
63 | return BE3_NAME; | |
64 | default: | |
c4ca2374 | 65 | return BE_NAME; |
12d7ea2c | 66 | } |
c4ca2374 AK |
67 | } |
68 | ||
6b7c5b94 | 69 | /* Number of bytes of an RX frame that are copied to skb->data */ |
2e588f84 | 70 | #define BE_HDR_LEN ((u16) 64) |
6b7c5b94 SP |
71 | #define BE_MAX_JUMBO_FRAME_SIZE 9018 |
72 | #define BE_MIN_MTU 256 | |
73 | ||
74 | #define BE_NUM_VLANS_SUPPORTED 64 | |
75 | #define BE_MAX_EQD 96 | |
76 | #define BE_MAX_TX_FRAG_COUNT 30 | |
77 | ||
78 | #define EVNT_Q_LEN 1024 | |
79 | #define TX_Q_LEN 2048 | |
80 | #define TX_CQ_LEN 1024 | |
81 | #define RX_Q_LEN 1024 /* Does not support any other value */ | |
82 | #define RX_CQ_LEN 1024 | |
5fb379ee | 83 | #define MCC_Q_LEN 128 /* total size not to exceed 8 pages */ |
6b7c5b94 SP |
84 | #define MCC_CQ_LEN 256 |
85 | ||
3abcdeda | 86 | #define MAX_RSS_QS 4 /* BE limit is 4 queues/port */ |
ac6a0c4a SP |
87 | #define MAX_RX_QS (MAX_RSS_QS + 1) /* RSS qs + 1 def Rx */ |
88 | #define BE_MAX_MSIX_VECTORS (MAX_RX_QS + 1)/* RX + TX */ | |
6b7c5b94 SP |
89 | #define BE_NAPI_WEIGHT 64 |
90 | #define MAX_RX_POST BE_NAPI_WEIGHT /* Frags posted at a time */ | |
91 | #define RX_FRAGS_REFILL_WM (RX_Q_LEN - MAX_RX_POST) | |
92 | ||
8788fdc2 SP |
93 | #define FW_VER_LEN 32 |
94 | ||
ba343c77 SB |
95 | #define BE_MAX_VF 32 |
96 | ||
6b7c5b94 SP |
97 | struct be_dma_mem { |
98 | void *va; | |
99 | dma_addr_t dma; | |
100 | u32 size; | |
101 | }; | |
102 | ||
103 | struct be_queue_info { | |
104 | struct be_dma_mem dma_mem; | |
105 | u16 len; | |
106 | u16 entry_size; /* Size of an element in the queue */ | |
107 | u16 id; | |
108 | u16 tail, head; | |
109 | bool created; | |
110 | atomic_t used; /* Number of valid elements in the queue */ | |
111 | }; | |
112 | ||
5fb379ee SP |
113 | static inline u32 MODULO(u16 val, u16 limit) |
114 | { | |
115 | BUG_ON(limit & (limit - 1)); | |
116 | return val & (limit - 1); | |
117 | } | |
118 | ||
119 | static inline void index_adv(u16 *index, u16 val, u16 limit) | |
120 | { | |
121 | *index = MODULO((*index + val), limit); | |
122 | } | |
123 | ||
124 | static inline void index_inc(u16 *index, u16 limit) | |
125 | { | |
126 | *index = MODULO((*index + 1), limit); | |
127 | } | |
128 | ||
129 | static inline void *queue_head_node(struct be_queue_info *q) | |
130 | { | |
131 | return q->dma_mem.va + q->head * q->entry_size; | |
132 | } | |
133 | ||
134 | static inline void *queue_tail_node(struct be_queue_info *q) | |
135 | { | |
136 | return q->dma_mem.va + q->tail * q->entry_size; | |
137 | } | |
138 | ||
139 | static inline void queue_head_inc(struct be_queue_info *q) | |
140 | { | |
141 | index_inc(&q->head, q->len); | |
142 | } | |
143 | ||
144 | static inline void queue_tail_inc(struct be_queue_info *q) | |
145 | { | |
146 | index_inc(&q->tail, q->len); | |
147 | } | |
148 | ||
5fb379ee SP |
149 | struct be_eq_obj { |
150 | struct be_queue_info q; | |
151 | char desc[32]; | |
152 | ||
153 | /* Adaptive interrupt coalescing (AIC) info */ | |
154 | bool enable_aic; | |
155 | u16 min_eqd; /* in usecs */ | |
156 | u16 max_eqd; /* in usecs */ | |
157 | u16 cur_eqd; /* in usecs */ | |
fe6d2a38 | 158 | u8 msix_vec_idx; |
5fb379ee SP |
159 | |
160 | struct napi_struct napi; | |
161 | }; | |
162 | ||
163 | struct be_mcc_obj { | |
164 | struct be_queue_info q; | |
165 | struct be_queue_info cq; | |
7a1e9b20 | 166 | bool rearm_cq; |
5fb379ee SP |
167 | }; |
168 | ||
3abcdeda | 169 | struct be_tx_stats { |
6b7c5b94 SP |
170 | u32 be_tx_reqs; /* number of TX requests initiated */ |
171 | u32 be_tx_stops; /* number of times TX Q was stopped */ | |
6b7c5b94 SP |
172 | u32 be_tx_wrbs; /* number of tx WRBs used */ |
173 | u32 be_tx_events; /* number of tx completion events */ | |
174 | u32 be_tx_compl; /* number of tx completion entries processed */ | |
4097f663 SP |
175 | ulong be_tx_jiffies; |
176 | u64 be_tx_bytes; | |
177 | u64 be_tx_bytes_prev; | |
91992e44 | 178 | u64 be_tx_pkts; |
6b7c5b94 | 179 | u32 be_tx_rate; |
6b7c5b94 SP |
180 | }; |
181 | ||
6b7c5b94 SP |
182 | struct be_tx_obj { |
183 | struct be_queue_info q; | |
184 | struct be_queue_info cq; | |
185 | /* Remember the skbs that were transmitted */ | |
186 | struct sk_buff *sent_skb_list[TX_Q_LEN]; | |
187 | }; | |
188 | ||
189 | /* Struct to remember the pages posted for rx frags */ | |
190 | struct be_rx_page_info { | |
191 | struct page *page; | |
fac6da5b | 192 | DEFINE_DMA_UNMAP_ADDR(bus); |
6b7c5b94 SP |
193 | u16 page_offset; |
194 | bool last_page_user; | |
195 | }; | |
196 | ||
3abcdeda SP |
197 | struct be_rx_stats { |
198 | u32 rx_post_fail;/* number of ethrx buffer alloc failures */ | |
199 | u32 rx_polls; /* number of times NAPI called poll function */ | |
200 | u32 rx_events; /* number of ucast rx completion events */ | |
201 | u32 rx_compl; /* number of rx completion entries processed */ | |
202 | ulong rx_jiffies; | |
203 | u64 rx_bytes; | |
204 | u64 rx_bytes_prev; | |
205 | u64 rx_pkts; | |
206 | u32 rx_rate; | |
207 | u32 rx_mcast_pkts; | |
208 | u32 rxcp_err; /* Num rx completion entries w/ err set. */ | |
209 | ulong rx_fps_jiffies; /* jiffies at last FPS calc */ | |
210 | u32 rx_frags; | |
211 | u32 prev_rx_frags; | |
212 | u32 rx_fps; /* Rx frags per second */ | |
213 | }; | |
214 | ||
2e588f84 SP |
215 | struct be_rx_compl_info { |
216 | u32 rss_hash; | |
217 | u16 vid; | |
218 | u16 pkt_size; | |
219 | u16 rxq_idx; | |
220 | u16 mac_id; | |
221 | u8 vlanf; | |
222 | u8 num_rcvd; | |
223 | u8 err; | |
224 | u8 ipf; | |
225 | u8 tcpf; | |
226 | u8 udpf; | |
227 | u8 ip_csum; | |
228 | u8 l4_csum; | |
229 | u8 ipv6; | |
230 | u8 vtm; | |
231 | u8 pkt_type; | |
232 | }; | |
233 | ||
6b7c5b94 | 234 | struct be_rx_obj { |
3abcdeda | 235 | struct be_adapter *adapter; |
6b7c5b94 SP |
236 | struct be_queue_info q; |
237 | struct be_queue_info cq; | |
2e588f84 | 238 | struct be_rx_compl_info rxcp; |
6b7c5b94 | 239 | struct be_rx_page_info page_info_tbl[RX_Q_LEN]; |
3abcdeda SP |
240 | struct be_eq_obj rx_eq; |
241 | struct be_rx_stats stats; | |
242 | u8 rss_id; | |
243 | bool rx_post_starved; /* Zero rx frags have been posted to BE */ | |
e80d9da6 | 244 | u32 cache_line_barrier[16]; |
6b7c5b94 SP |
245 | }; |
246 | ||
609ff3bb AK |
247 | struct be_drv_stats { |
248 | u8 be_on_die_temperature; | |
249 | }; | |
250 | ||
64600ea5 AK |
251 | struct be_vf_cfg { |
252 | unsigned char vf_mac_addr[ETH_ALEN]; | |
253 | u32 vf_if_handle; | |
254 | u32 vf_pmac_id; | |
1da87b7f | 255 | u16 vf_vlan_tag; |
e1d18735 | 256 | u32 vf_tx_rate; |
64600ea5 AK |
257 | }; |
258 | ||
9cd9000b | 259 | #define BE_INVALID_PMAC_ID 0xffffffff |
609ff3bb | 260 | |
6b7c5b94 SP |
261 | struct be_adapter { |
262 | struct pci_dev *pdev; | |
263 | struct net_device *netdev; | |
264 | ||
8788fdc2 SP |
265 | u8 __iomem *csr; |
266 | u8 __iomem *db; /* Door Bell */ | |
267 | u8 __iomem *pcicfg; /* PCI config space */ | |
8788fdc2 | 268 | |
2984961c | 269 | struct mutex mbox_lock; /* For serializing mbox cmds to BE card */ |
8788fdc2 SP |
270 | struct be_dma_mem mbox_mem; |
271 | /* Mbox mem is adjusted to align to 16 bytes. The allocated addr | |
272 | * is stored for freeing purpose */ | |
273 | struct be_dma_mem mbox_mem_alloced; | |
274 | ||
275 | struct be_mcc_obj mcc_obj; | |
276 | spinlock_t mcc_lock; /* For serializing mcc cmds to BE card */ | |
277 | spinlock_t mcc_cq_lock; | |
6b7c5b94 | 278 | |
3abcdeda | 279 | struct msix_entry msix_entries[BE_MAX_MSIX_VECTORS]; |
ac6a0c4a | 280 | u32 num_msix_vec; |
6b7c5b94 SP |
281 | bool isr_registered; |
282 | ||
283 | /* TX Rings */ | |
284 | struct be_eq_obj tx_eq; | |
285 | struct be_tx_obj tx_obj; | |
3abcdeda | 286 | struct be_tx_stats tx_stats; |
6b7c5b94 SP |
287 | |
288 | u32 cache_line_break[8]; | |
289 | ||
290 | /* Rx rings */ | |
ac6a0c4a | 291 | struct be_rx_obj rx_obj[MAX_RX_QS]; |
3abcdeda | 292 | u32 num_rx_qs; |
6b7c5b94 SP |
293 | u32 big_page_size; /* Compounded page size shared by rx wrbs */ |
294 | ||
fe6d2a38 | 295 | u8 msix_vec_next_idx; |
609ff3bb | 296 | struct be_drv_stats drv_stats; |
fe6d2a38 | 297 | |
6b7c5b94 | 298 | struct vlan_group *vlan_grp; |
82903e4b AK |
299 | u16 vlans_added; |
300 | u16 max_vlans; /* Number of vlans supported */ | |
b738127d | 301 | u8 vlan_tag[VLAN_N_VID]; |
cc4ce020 SK |
302 | u8 vlan_prio_bmap; /* Available Priority BitMap */ |
303 | u16 recommended_prio; /* Recommended Priority */ | |
e7b909a6 | 304 | struct be_dma_mem mc_cmd_mem; |
6b7c5b94 | 305 | |
3abcdeda | 306 | struct be_dma_mem stats_cmd; |
6b7c5b94 SP |
307 | /* Work queue used to perform periodic tasks like getting statistics */ |
308 | struct delayed_work work; | |
609ff3bb | 309 | u16 work_counter; |
6b7c5b94 SP |
310 | |
311 | /* Ethtool knobs and info */ | |
312 | bool rx_csum; /* BE card must perform rx-checksumming */ | |
6b7c5b94 SP |
313 | char fw_ver[FW_VER_LEN]; |
314 | u32 if_handle; /* Used to configure filtering */ | |
315 | u32 pmac_id; /* MAC addr handle used by BE card */ | |
316 | ||
cf588477 | 317 | bool eeh_err; |
a8f447bd | 318 | bool link_up; |
6b7c5b94 | 319 | u32 port_num; |
24307eef | 320 | bool promiscuous; |
71d8d1b5 | 321 | bool wol; |
3486be29 | 322 | u32 function_mode; |
3abcdeda | 323 | u32 function_caps; |
9e90c961 AK |
324 | u32 rx_fc; /* Rx flow control */ |
325 | u32 tx_fc; /* Tx flow control */ | |
7c185276 | 326 | bool ue_detected; |
b2aebe6d | 327 | bool stats_cmd_sent; |
0dffc83e AK |
328 | int link_speed; |
329 | u8 port_type; | |
16c02145 | 330 | u8 transceiver; |
ee3cb629 | 331 | u8 autoneg; |
7b139c83 | 332 | u8 generation; /* BladeEngine ASIC generation */ |
dd131e76 SB |
333 | u32 flash_status; |
334 | struct completion flash_compl; | |
ba343c77 | 335 | |
2e588f84 | 336 | bool be3_native; |
ba343c77 | 337 | bool sriov_enabled; |
64600ea5 | 338 | struct be_vf_cfg vf_cfg[BE_MAX_VF]; |
344dbf10 | 339 | u8 is_virtfn; |
fe6d2a38 | 340 | u32 sli_family; |
9e1453c5 | 341 | u8 hba_port_num; |
3968fa1e | 342 | u16 pvid; |
6b7c5b94 SP |
343 | }; |
344 | ||
344dbf10 | 345 | #define be_physfn(adapter) (!adapter->is_virtfn) |
ba343c77 | 346 | |
7b139c83 AK |
347 | /* BladeEngine Generation numbers */ |
348 | #define BE_GEN2 2 | |
349 | #define BE_GEN3 3 | |
350 | ||
fe6d2a38 SP |
351 | #define lancer_chip(adapter) (adapter->pdev->device == OC_DEVICE_ID3) |
352 | ||
0fc0b732 | 353 | extern const struct ethtool_ops be_ethtool_ops; |
6b7c5b94 | 354 | |
ac6a0c4a | 355 | #define msix_enabled(adapter) (adapter->num_msix_vec > 0) |
3abcdeda SP |
356 | #define tx_stats(adapter) (&adapter->tx_stats) |
357 | #define rx_stats(rxo) (&rxo->stats) | |
6b7c5b94 SP |
358 | |
359 | #define BE_SET_NETDEV_OPS(netdev, ops) (netdev->netdev_ops = ops) | |
360 | ||
3abcdeda SP |
361 | #define for_all_rx_queues(adapter, rxo, i) \ |
362 | for (i = 0, rxo = &adapter->rx_obj[i]; i < adapter->num_rx_qs; \ | |
363 | i++, rxo++) | |
364 | ||
365 | /* Just skip the first default non-rss queue */ | |
366 | #define for_all_rss_queues(adapter, rxo, i) \ | |
367 | for (i = 0, rxo = &adapter->rx_obj[i+1]; i < (adapter->num_rx_qs - 1);\ | |
368 | i++, rxo++) | |
369 | ||
6b7c5b94 SP |
370 | #define PAGE_SHIFT_4K 12 |
371 | #define PAGE_SIZE_4K (1 << PAGE_SHIFT_4K) | |
372 | ||
373 | /* Returns number of pages spanned by the data starting at the given addr */ | |
374 | #define PAGES_4K_SPANNED(_address, size) \ | |
375 | ((u32)((((size_t)(_address) & (PAGE_SIZE_4K - 1)) + \ | |
376 | (size) + (PAGE_SIZE_4K - 1)) >> PAGE_SHIFT_4K)) | |
377 | ||
378 | /* Byte offset into the page corresponding to given address */ | |
379 | #define OFFSET_IN_PAGE(addr) \ | |
380 | ((size_t)(addr) & (PAGE_SIZE_4K-1)) | |
381 | ||
382 | /* Returns bit offset within a DWORD of a bitfield */ | |
383 | #define AMAP_BIT_OFFSET(_struct, field) \ | |
384 | (((size_t)&(((_struct *)0)->field))%32) | |
385 | ||
386 | /* Returns the bit mask of the field that is NOT shifted into location. */ | |
387 | static inline u32 amap_mask(u32 bitsize) | |
388 | { | |
389 | return (bitsize == 32 ? 0xFFFFFFFF : (1 << bitsize) - 1); | |
390 | } | |
391 | ||
392 | static inline void | |
393 | amap_set(void *ptr, u32 dw_offset, u32 mask, u32 offset, u32 value) | |
394 | { | |
395 | u32 *dw = (u32 *) ptr + dw_offset; | |
396 | *dw &= ~(mask << offset); | |
397 | *dw |= (mask & value) << offset; | |
398 | } | |
399 | ||
400 | #define AMAP_SET_BITS(_struct, field, ptr, val) \ | |
401 | amap_set(ptr, \ | |
402 | offsetof(_struct, field)/32, \ | |
403 | amap_mask(sizeof(((_struct *)0)->field)), \ | |
404 | AMAP_BIT_OFFSET(_struct, field), \ | |
405 | val) | |
406 | ||
407 | static inline u32 amap_get(void *ptr, u32 dw_offset, u32 mask, u32 offset) | |
408 | { | |
409 | u32 *dw = (u32 *) ptr; | |
410 | return mask & (*(dw + dw_offset) >> offset); | |
411 | } | |
412 | ||
413 | #define AMAP_GET_BITS(_struct, field, ptr) \ | |
414 | amap_get(ptr, \ | |
415 | offsetof(_struct, field)/32, \ | |
416 | amap_mask(sizeof(((_struct *)0)->field)), \ | |
417 | AMAP_BIT_OFFSET(_struct, field)) | |
418 | ||
419 | #define be_dws_cpu_to_le(wrb, len) swap_dws(wrb, len) | |
420 | #define be_dws_le_to_cpu(wrb, len) swap_dws(wrb, len) | |
421 | static inline void swap_dws(void *wrb, int len) | |
422 | { | |
423 | #ifdef __BIG_ENDIAN | |
424 | u32 *dw = wrb; | |
425 | BUG_ON(len % 4); | |
426 | do { | |
427 | *dw = cpu_to_le32(*dw); | |
428 | dw++; | |
429 | len -= 4; | |
430 | } while (len); | |
431 | #endif /* __BIG_ENDIAN */ | |
432 | } | |
433 | ||
434 | static inline u8 is_tcp_pkt(struct sk_buff *skb) | |
435 | { | |
436 | u8 val = 0; | |
437 | ||
438 | if (ip_hdr(skb)->version == 4) | |
439 | val = (ip_hdr(skb)->protocol == IPPROTO_TCP); | |
440 | else if (ip_hdr(skb)->version == 6) | |
441 | val = (ipv6_hdr(skb)->nexthdr == NEXTHDR_TCP); | |
442 | ||
443 | return val; | |
444 | } | |
445 | ||
446 | static inline u8 is_udp_pkt(struct sk_buff *skb) | |
447 | { | |
448 | u8 val = 0; | |
449 | ||
450 | if (ip_hdr(skb)->version == 4) | |
451 | val = (ip_hdr(skb)->protocol == IPPROTO_UDP); | |
452 | else if (ip_hdr(skb)->version == 6) | |
453 | val = (ipv6_hdr(skb)->nexthdr == NEXTHDR_UDP); | |
454 | ||
455 | return val; | |
456 | } | |
457 | ||
344dbf10 SB |
458 | static inline void be_check_sriov_fn_type(struct be_adapter *adapter) |
459 | { | |
460 | u8 data; | |
fe6d2a38 SP |
461 | u32 sli_intf; |
462 | ||
463 | if (lancer_chip(adapter)) { | |
464 | pci_read_config_dword(adapter->pdev, SLI_INTF_REG_OFFSET, | |
465 | &sli_intf); | |
466 | adapter->is_virtfn = (sli_intf & SLI_INTF_FT_MASK) ? 1 : 0; | |
467 | } else { | |
468 | pci_write_config_byte(adapter->pdev, 0xFE, 0xAA); | |
469 | pci_read_config_byte(adapter->pdev, 0xFE, &data); | |
470 | adapter->is_virtfn = (data != 0xAA); | |
471 | } | |
344dbf10 SB |
472 | } |
473 | ||
6d87f5c3 AK |
474 | static inline void be_vf_eth_addr_generate(struct be_adapter *adapter, u8 *mac) |
475 | { | |
476 | u32 addr; | |
477 | ||
478 | addr = jhash(adapter->netdev->dev_addr, ETH_ALEN, 0); | |
479 | ||
480 | mac[5] = (u8)(addr & 0xFF); | |
481 | mac[4] = (u8)((addr >> 8) & 0xFF); | |
482 | mac[3] = (u8)((addr >> 16) & 0xFF); | |
7a2414a5 AK |
483 | /* Use the OUI from the current MAC address */ |
484 | memcpy(mac, adapter->netdev->dev_addr, 3); | |
6d87f5c3 AK |
485 | } |
486 | ||
8788fdc2 | 487 | extern void be_cq_notify(struct be_adapter *adapter, u16 qid, bool arm, |
5fb379ee | 488 | u16 num_popped); |
8788fdc2 | 489 | extern void be_link_status_update(struct be_adapter *adapter, bool link_up); |
b31c50a7 | 490 | extern void netdev_stats_update(struct be_adapter *adapter); |
84517482 | 491 | extern int be_load_fw(struct be_adapter *adapter, u8 *func); |
6b7c5b94 | 492 | #endif /* BE_H */ |