[deliverable/linux.git] / drivers / net / benet / be.h

/*
 * Copyright (C) 2005 - 2009 ServerEngines
 * All rights reserved.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License version 2
 * as published by the Free Software Foundation.  The full GNU General
 * Public License is included in this distribution in the file called COPYING.
 *
 * Contact Information:
 * linux-drivers@serverengines.com
 *
 * ServerEngines
 * 209 N. Fair Oaks Ave
 * Sunnyvale, CA 94085
 */

#ifndef BE_H
#define BE_H

#include <linux/pci.h>
#include <linux/etherdevice.h>
#include <linux/version.h>
#include <linux/delay.h>
#include <net/tcp.h>
#include <net/ip.h>
#include <net/ipv6.h>
#include <linux/if_vlan.h>
#include <linux/workqueue.h>
#include <linux/interrupt.h>
#include <linux/inet_lro.h>

#include "be_hw.h"

#define DRV_VER			"2.0.348"
#define DRV_NAME		"be2net"
#define BE_NAME			"ServerEngines BladeEngine2 10Gbps NIC"
#define OC_NAME			"Emulex OneConnect 10Gbps NIC"
#define DRV_DESC		BE_NAME "Driver"

#define BE_VENDOR_ID 		0x19a2
#define BE_DEVICE_ID1		0x211
#define OC_DEVICE_ID1		0x700
#define OC_DEVICE_ID2		0x701

static inline char *nic_name(struct pci_dev *pdev)
{
	if (pdev->device == OC_DEVICE_ID1 || pdev->device == OC_DEVICE_ID2)
		return OC_NAME;
	else
		return BE_NAME;
}

/* Number of bytes of an RX frame that are copied to skb->data */
#define BE_HDR_LEN 		64
#define BE_MAX_JUMBO_FRAME_SIZE	9018
#define BE_MIN_MTU		256

#define BE_NUM_VLANS_SUPPORTED	64
#define BE_MAX_EQD		96
#define	BE_MAX_TX_FRAG_COUNT	30

#define EVNT_Q_LEN		1024
#define TX_Q_LEN		2048
#define TX_CQ_LEN		1024
#define RX_Q_LEN		1024	/* Does not support any other value */
#define RX_CQ_LEN		1024
#define MCC_Q_LEN		128	/* total size not to exceed 8 pages */
#define MCC_CQ_LEN		256

#define BE_NAPI_WEIGHT		64
#define MAX_RX_POST 		BE_NAPI_WEIGHT /* Frags posted at a time */
#define RX_FRAGS_REFILL_WM	(RX_Q_LEN - MAX_RX_POST)

#define BE_MAX_LRO_DESCRIPTORS  16
#define BE_MAX_FRAGS_PER_FRAME  16

struct be_dma_mem {
	void *va;
	dma_addr_t dma;
	u32 size;
};

struct be_queue_info {
	struct be_dma_mem dma_mem;
	u16 len;
	u16 entry_size;	/* Size of an element in the queue */
	u16 id;
	u16 tail, head;
	bool created;
	atomic_t used;	/* Number of valid elements in the queue */
};

static inline u32 MODULO(u16 val, u16 limit)
{
	BUG_ON(limit & (limit - 1));
	return val & (limit - 1);
}

static inline void index_adv(u16 *index, u16 val, u16 limit)
{
	*index = MODULO((*index + val), limit);
}

static inline void index_inc(u16 *index, u16 limit)
{
	*index = MODULO((*index + 1), limit);
}

static inline void *queue_head_node(struct be_queue_info *q)
{
	return q->dma_mem.va + q->head * q->entry_size;
}

static inline void *queue_tail_node(struct be_queue_info *q)
{
	return q->dma_mem.va + q->tail * q->entry_size;
}

static inline void queue_head_inc(struct be_queue_info *q)
{
	index_inc(&q->head, q->len);
}

static inline void queue_tail_inc(struct be_queue_info *q)
{
	index_inc(&q->tail, q->len);
}


struct be_eq_obj {
	struct be_queue_info q;
	char desc[32];

	/* Adaptive interrupt coalescing (AIC) info */
	bool enable_aic;
	u16 min_eqd;		/* in usecs */
	u16 max_eqd;		/* in usecs */
	u16 cur_eqd;		/* in usecs */

	struct napi_struct napi;
};

struct be_mcc_obj {
	struct be_queue_info q;
	struct be_queue_info cq;
};

struct be_ctrl_info {
	u8 __iomem *csr;
	u8 __iomem *db;		/* Door Bell */
	u8 __iomem *pcicfg;	/* PCI config space */
	int pci_func;

	/* Mbox used for cmd request/response */
	spinlock_t mbox_lock;	/* For serializing mbox cmds to BE card */
	struct be_dma_mem mbox_mem;
	/* Mbox mem is adjusted to align to 16 bytes. The allocated addr
	 * is stored for freeing purpose */
	struct be_dma_mem mbox_mem_alloced;

	/* MCC Rings */
	struct be_mcc_obj mcc_obj;
	spinlock_t mcc_lock;	/* For serializing mcc cmds to BE card */
	spinlock_t mcc_cq_lock;
};

#include "be_cmds.h"

struct be_drvr_stats {
	u32 be_tx_reqs;		/* number of TX requests initiated */
	u32 be_tx_stops;	/* number of times TX Q was stopped */
	u32 be_fwd_reqs;	/* number of send reqs through forwarding i/f */
	u32 be_tx_wrbs;		/* number of tx WRBs used */
	u32 be_tx_events;	/* number of tx completion events  */
	u32 be_tx_compl;	/* number of tx completion entries processed */
	ulong be_tx_jiffies;
	u64 be_tx_bytes;
	u64 be_tx_bytes_prev;
	u32 be_tx_rate;

	u32 cache_barrier[16];

	u32 be_ethrx_post_fail;/* number of ethrx buffer alloc failures */
	u32 be_polls;		/* number of times NAPI called poll function */
	u32 be_rx_events;	/* number of ucast rx completion events  */
	u32 be_rx_compl;	/* number of rx completion entries processed */
	u32 be_lro_hgram_data[8];	/* histogram of LRO data packets */
	u32 be_lro_hgram_ack[8];	/* histogram of LRO ACKs */
	ulong be_rx_jiffies;
	u64 be_rx_bytes;
	u64 be_rx_bytes_prev;
	u32 be_rx_rate;
	/* number of non ether type II frames dropped where
	 * frame len > length field of Mac Hdr */
	u32 be_802_3_dropped_frames;
	/* number of non ether type II frames malformed where
	 * in frame len < length field of Mac Hdr */
	u32 be_802_3_malformed_frames;
	u32 be_rxcp_err;	/* Num rx completion entries w/ err set. */
	ulong rx_fps_jiffies;	/* jiffies at last FPS calc */
	u32 be_rx_frags;
	u32 be_prev_rx_frags;
	u32 be_rx_fps;		/* Rx frags per second */
};

struct be_stats_obj {
	struct be_drvr_stats drvr_stats;
	struct net_device_stats net_stats;
	struct be_dma_mem cmd;
};

struct be_tx_obj {
	struct be_queue_info q;
	struct be_queue_info cq;
	/* Remember the skbs that were transmitted */
	struct sk_buff *sent_skb_list[TX_Q_LEN];
};

/* Struct to remember the pages posted for rx frags */
struct be_rx_page_info {
	struct page *page;
	dma_addr_t bus;
	u16 page_offset;
	bool last_page_user;
};

struct be_rx_obj {
	struct be_queue_info q;
	struct be_queue_info cq;
	struct be_rx_page_info page_info_tbl[RX_Q_LEN];
	struct net_lro_mgr lro_mgr;
	struct net_lro_desc lro_desc[BE_MAX_LRO_DESCRIPTORS];
};

#define BE_NUM_MSIX_VECTORS		2	/* 1 each for Tx and Rx */
struct be_adapter {
	struct pci_dev *pdev;
	struct net_device *netdev;

	/* Mbox, pci config, csr address information */
	struct be_ctrl_info ctrl;

	struct msix_entry msix_entries[BE_NUM_MSIX_VECTORS];
	bool msix_enabled;
	bool isr_registered;

	/* TX Rings */
	struct be_eq_obj tx_eq;
	struct be_tx_obj tx_obj;

	u32 cache_line_break[8];

	/* Rx rings */
	struct be_eq_obj rx_eq;
	struct be_rx_obj rx_obj;
	u32 big_page_size;	/* Compounded page size shared by rx wrbs */
	bool rx_post_starved;	/* Zero rx frags have been posted to BE */

	struct vlan_group *vlan_grp;
	u16 num_vlans;
	u8 vlan_tag[VLAN_GROUP_ARRAY_LEN];

	struct be_stats_obj stats;
	/* Work queue used to perform periodic tasks like getting statistics */
	struct delayed_work work;

	/* Ethtool knobs and info */
	bool rx_csum; 		/* BE card must perform rx-checksumming */
	u32 max_rx_coal;
	char fw_ver[FW_VER_LEN];
	u32 if_handle;		/* Used to configure filtering */
	u32 pmac_id;		/* MAC addr handle used by BE card */

	struct be_link_info link;
	u32 port_num;
	bool promiscuous;
};

extern struct ethtool_ops be_ethtool_ops;

#define drvr_stats(adapter)		(&adapter->stats.drvr_stats)

#define BE_SET_NETDEV_OPS(netdev, ops)	(netdev->netdev_ops = ops)

#define PAGE_SHIFT_4K		12
#define PAGE_SIZE_4K		(1 << PAGE_SHIFT_4K)

/* Returns number of pages spanned by the data starting at the given addr */
#define PAGES_4K_SPANNED(_address, size) 				\
		((u32)((((size_t)(_address) & (PAGE_SIZE_4K - 1)) + 	\
			(size) + (PAGE_SIZE_4K - 1)) >> PAGE_SHIFT_4K))

/* Byte offset into the page corresponding to given address */
#define OFFSET_IN_PAGE(addr)						\
		 ((size_t)(addr) & (PAGE_SIZE_4K-1))

/* Returns bit offset within a DWORD of a bitfield */
#define AMAP_BIT_OFFSET(_struct, field)  				\
		(((size_t)&(((_struct *)0)->field))%32)

/* Returns the bit mask of the field that is NOT shifted into location. */
static inline u32 amap_mask(u32 bitsize)
{
	return (bitsize == 32 ? 0xFFFFFFFF : (1 << bitsize) - 1);
}

static inline void
amap_set(void *ptr, u32 dw_offset, u32 mask, u32 offset, u32 value)
{
	u32 *dw = (u32 *) ptr + dw_offset;
	*dw &= ~(mask << offset);
	*dw |= (mask & value) << offset;
}

#define AMAP_SET_BITS(_struct, field, ptr, val)				\
		amap_set(ptr,						\
			offsetof(_struct, field)/32,			\
			amap_mask(sizeof(((_struct *)0)->field)),	\
			AMAP_BIT_OFFSET(_struct, field),		\
			val)

static inline u32 amap_get(void *ptr, u32 dw_offset, u32 mask, u32 offset)
{
	u32 *dw = (u32 *) ptr;
	return mask & (*(dw + dw_offset) >> offset);
}

#define AMAP_GET_BITS(_struct, field, ptr)				\
		amap_get(ptr,						\
			offsetof(_struct, field)/32,			\
			amap_mask(sizeof(((_struct *)0)->field)),	\
			AMAP_BIT_OFFSET(_struct, field))

#define be_dws_cpu_to_le(wrb, len)	swap_dws(wrb, len)
#define be_dws_le_to_cpu(wrb, len)	swap_dws(wrb, len)
static inline void swap_dws(void *wrb, int len)
{
#ifdef __BIG_ENDIAN
	u32 *dw = wrb;
	BUG_ON(len % 4);
	do {
		*dw = cpu_to_le32(*dw);
		dw++;
		len -= 4;
	} while (len);
#endif				/* __BIG_ENDIAN */
}

static inline u8 is_tcp_pkt(struct sk_buff *skb)
{
	u8 val = 0;

	if (ip_hdr(skb)->version == 4)
		val = (ip_hdr(skb)->protocol == IPPROTO_TCP);
	else if (ip_hdr(skb)->version == 6)
		val = (ipv6_hdr(skb)->nexthdr == NEXTHDR_TCP);

	return val;
}

static inline u8 is_udp_pkt(struct sk_buff *skb)
{
	u8 val = 0;

	if (ip_hdr(skb)->version == 4)
		val = (ip_hdr(skb)->protocol == IPPROTO_UDP);
	else if (ip_hdr(skb)->version == 6)
		val = (ipv6_hdr(skb)->nexthdr == NEXTHDR_UDP);

	return val;
}

extern void be_cq_notify(struct be_ctrl_info *ctrl, u16 qid, bool arm,
		u16 num_popped);
#endif				/* BE_H */
Commit	Line	Data
6b7c5b94 SP	1	/*
	2	* Copyright (C) 2005 - 2009 ServerEngines
	3	* All rights reserved.
	4	*
	5	* This program is free software; you can redistribute it and/or
	6	* modify it under the terms of the GNU General Public License version 2
	7	* as published by the Free Software Foundation. The full GNU General
	8	* Public License is included in this distribution in the file called COPYING.
	9	*
	10	* Contact Information:
	11	* linux-drivers@serverengines.com
	12	*
	13	* ServerEngines
	14	* 209 N. Fair Oaks Ave
	15	* Sunnyvale, CA 94085
	16	*/
	17
	18	#ifndef BE_H
	19	#define BE_H
	20
	21	#include <linux/pci.h>
	22	#include <linux/etherdevice.h>
	23	#include <linux/version.h>
	24	#include <linux/delay.h>
	25	#include <net/tcp.h>
	26	#include <net/ip.h>
	27	#include <net/ipv6.h>
	28	#include <linux/if_vlan.h>
	29	#include <linux/workqueue.h>
	30	#include <linux/interrupt.h>
	31	#include <linux/inet_lro.h>
	32
	33	#include "be_hw.h"
	34
	35	#define DRV_VER "2.0.348"
	36	#define DRV_NAME "be2net"
	37	#define BE_NAME "ServerEngines BladeEngine2 10Gbps NIC"
c4ca2374	38	#define OC_NAME "Emulex OneConnect 10Gbps NIC"
6b7c5b94 SP	39	#define DRV_DESC BE_NAME "Driver"
6b7c5b94 SP	40
c4ca2374 AK	41	#define BE_VENDOR_ID 0x19a2
	42	#define BE_DEVICE_ID1 0x211
	43	#define OC_DEVICE_ID1 0x700
	44	#define OC_DEVICE_ID2 0x701
	45
	46	static inline char nic_name(struct pci_dev pdev)
	47	{
	48	if (pdev->device == OC_DEVICE_ID1 \|\| pdev->device == OC_DEVICE_ID2)
	49	return OC_NAME;
	50	else
	51	return BE_NAME;
	52	}
	53
6b7c5b94 SP	54	/* Number of bytes of an RX frame that are copied to skb->data */
	55	#define BE_HDR_LEN 64
	56	#define BE_MAX_JUMBO_FRAME_SIZE 9018
	57	#define BE_MIN_MTU 256
	58
	59	#define BE_NUM_VLANS_SUPPORTED 64
	60	#define BE_MAX_EQD 96
	61	#define BE_MAX_TX_FRAG_COUNT 30
	62
	63	#define EVNT_Q_LEN 1024
	64	#define TX_Q_LEN 2048
	65	#define TX_CQ_LEN 1024
	66	#define RX_Q_LEN 1024 /* Does not support any other value */
	67	#define RX_CQ_LEN 1024
5fb379ee	68	#define MCC_Q_LEN 128 /* total size not to exceed 8 pages */
6b7c5b94 SP	69	#define MCC_CQ_LEN 256
	70
	71	#define BE_NAPI_WEIGHT 64
	72	#define MAX_RX_POST BE_NAPI_WEIGHT /* Frags posted at a time */
	73	#define RX_FRAGS_REFILL_WM (RX_Q_LEN - MAX_RX_POST)
	74
	75	#define BE_MAX_LRO_DESCRIPTORS 16
	76	#define BE_MAX_FRAGS_PER_FRAME 16
	77
	78	struct be_dma_mem {
	79	void *va;
	80	dma_addr_t dma;
	81	u32 size;
	82	};
	83
	84	struct be_queue_info {
	85	struct be_dma_mem dma_mem;
	86	u16 len;
	87	u16 entry_size; /* Size of an element in the queue */
	88	u16 id;
	89	u16 tail, head;
	90	bool created;
	91	atomic_t used; /* Number of valid elements in the queue */
	92	};
	93
5fb379ee SP	94	static inline u32 MODULO(u16 val, u16 limit)
	95	{
	96	BUG_ON(limit & (limit - 1));
	97	return val & (limit - 1);
	98	}
	99
	100	static inline void index_adv(u16 *index, u16 val, u16 limit)
	101	{
	102	index = MODULO((index + val), limit);
	103	}
	104
	105	static inline void index_inc(u16 *index, u16 limit)
	106	{
	107	index = MODULO((index + 1), limit);
	108	}
	109
	110	static inline void queue_head_node(struct be_queue_info q)
	111	{
	112	return q->dma_mem.va + q->head * q->entry_size;
	113	}
	114
	115	static inline void queue_tail_node(struct be_queue_info q)
	116	{
	117	return q->dma_mem.va + q->tail * q->entry_size;
	118	}
	119
	120	static inline void queue_head_inc(struct be_queue_info *q)
	121	{
	122	index_inc(&q->head, q->len);
	123	}
	124
	125	static inline void queue_tail_inc(struct be_queue_info *q)
	126	{
	127	index_inc(&q->tail, q->len);
	128	}
	129
	130
	131	struct be_eq_obj {
	132	struct be_queue_info q;
	133	char desc[32];
	134
	135	/* Adaptive interrupt coalescing (AIC) info */
	136	bool enable_aic;
	137	u16 min_eqd; /* in usecs */
	138	u16 max_eqd; /* in usecs */
	139	u16 cur_eqd; /* in usecs */
	140
	141	struct napi_struct napi;
	142	};
	143
	144	struct be_mcc_obj {
	145	struct be_queue_info q;
	146	struct be_queue_info cq;
	147	};
	148
6b7c5b94 SP	149	struct be_ctrl_info {
	150	u8 __iomem *csr;
	151	u8 __iomem db; / Door Bell */
	152	u8 __iomem pcicfg; / PCI config space */
	153	int pci_func;
	154
	155	/* Mbox used for cmd request/response */
5fb379ee	156	spinlock_t mbox_lock; /* For serializing mbox cmds to BE card */
6b7c5b94 SP	157	struct be_dma_mem mbox_mem;
	158	/* Mbox mem is adjusted to align to 16 bytes. The allocated addr
	159	* is stored for freeing purpose */
	160	struct be_dma_mem mbox_mem_alloced;
5fb379ee SP	161
	162	/* MCC Rings */
	163	struct be_mcc_obj mcc_obj;
	164	spinlock_t mcc_lock; /* For serializing mcc cmds to BE card */
	165	spinlock_t mcc_cq_lock;
6b7c5b94 SP	166	};
	167
	168	#include "be_cmds.h"
	169
	170	struct be_drvr_stats {
	171	u32 be_tx_reqs; /* number of TX requests initiated */
	172	u32 be_tx_stops; /* number of times TX Q was stopped */
	173	u32 be_fwd_reqs; /* number of send reqs through forwarding i/f */
	174	u32 be_tx_wrbs; /* number of tx WRBs used */
	175	u32 be_tx_events; /* number of tx completion events */
	176	u32 be_tx_compl; /* number of tx completion entries processed */
4097f663 SP	177	ulong be_tx_jiffies;
	178	u64 be_tx_bytes;
	179	u64 be_tx_bytes_prev;
6b7c5b94 SP	180	u32 be_tx_rate;
	181
	182	u32 cache_barrier[16];
	183
	184	u32 be_ethrx_post_fail;/* number of ethrx buffer alloc failures */
	185	u32 be_polls; /* number of times NAPI called poll function */
	186	u32 be_rx_events; /* number of ucast rx completion events */
	187	u32 be_rx_compl; /* number of rx completion entries processed */
	188	u32 be_lro_hgram_data[8]; /* histogram of LRO data packets */
	189	u32 be_lro_hgram_ack[8]; /* histogram of LRO ACKs */
4097f663 SP	190	ulong be_rx_jiffies;
	191	u64 be_rx_bytes;
	192	u64 be_rx_bytes_prev;
6b7c5b94 SP	193	u32 be_rx_rate;
	194	/* number of non ether type II frames dropped where
	195	* frame len > length field of Mac Hdr */
	196	u32 be_802_3_dropped_frames;
	197	/* number of non ether type II frames malformed where
	198	* in frame len < length field of Mac Hdr */
	199	u32 be_802_3_malformed_frames;
	200	u32 be_rxcp_err; /* Num rx completion entries w/ err set. */
	201	ulong rx_fps_jiffies; /* jiffies at last FPS calc */
	202	u32 be_rx_frags;
	203	u32 be_prev_rx_frags;
	204	u32 be_rx_fps; /* Rx frags per second */
	205	};
	206
	207	struct be_stats_obj {
	208	struct be_drvr_stats drvr_stats;
	209	struct net_device_stats net_stats;
	210	struct be_dma_mem cmd;
	211	};
	212
6b7c5b94 SP	213	struct be_tx_obj {
	214	struct be_queue_info q;
	215	struct be_queue_info cq;
	216	/* Remember the skbs that were transmitted */
	217	struct sk_buff *sent_skb_list[TX_Q_LEN];
	218	};
	219
	220	/* Struct to remember the pages posted for rx frags */
	221	struct be_rx_page_info {
	222	struct page *page;
	223	dma_addr_t bus;
	224	u16 page_offset;
	225	bool last_page_user;
	226	};
	227
	228	struct be_rx_obj {
	229	struct be_queue_info q;
	230	struct be_queue_info cq;
	231	struct be_rx_page_info page_info_tbl[RX_Q_LEN];
	232	struct net_lro_mgr lro_mgr;
	233	struct net_lro_desc lro_desc[BE_MAX_LRO_DESCRIPTORS];
	234	};
	235
	236	#define BE_NUM_MSIX_VECTORS 2 /* 1 each for Tx and Rx */
	237	struct be_adapter {
	238	struct pci_dev *pdev;
	239	struct net_device *netdev;
	240
	241	/* Mbox, pci config, csr address information */
	242	struct be_ctrl_info ctrl;
	243
	244	struct msix_entry msix_entries[BE_NUM_MSIX_VECTORS];
	245	bool msix_enabled;
	246	bool isr_registered;
	247
	248	/* TX Rings */
	249	struct be_eq_obj tx_eq;
	250	struct be_tx_obj tx_obj;
	251
	252	u32 cache_line_break[8];
	253
	254	/* Rx rings */
	255	struct be_eq_obj rx_eq;
	256	struct be_rx_obj rx_obj;
	257	u32 big_page_size; /* Compounded page size shared by rx wrbs */
ea1dae11	258	bool rx_post_starved; /* Zero rx frags have been posted to BE */
6b7c5b94 SP	259
	260	struct vlan_group *vlan_grp;
	261	u16 num_vlans;
	262	u8 vlan_tag[VLAN_GROUP_ARRAY_LEN];
	263
	264	struct be_stats_obj stats;
	265	/* Work queue used to perform periodic tasks like getting statistics */
	266	struct delayed_work work;
	267
	268	/* Ethtool knobs and info */
	269	bool rx_csum; /* BE card must perform rx-checksumming */
	270	u32 max_rx_coal;
	271	char fw_ver[FW_VER_LEN];
	272	u32 if_handle; /* Used to configure filtering */
	273	u32 pmac_id; /* MAC addr handle used by BE card */
	274
	275	struct be_link_info link;
	276	u32 port_num;
24307eef	277	bool promiscuous;
6b7c5b94 SP	278	};
	279
	280	extern struct ethtool_ops be_ethtool_ops;
	281
	282	#define drvr_stats(adapter) (&adapter->stats.drvr_stats)
	283
	284	#define BE_SET_NETDEV_OPS(netdev, ops) (netdev->netdev_ops = ops)
	285
6b7c5b94 SP	286	#define PAGE_SHIFT_4K 12
	287	#define PAGE_SIZE_4K (1 << PAGE_SHIFT_4K)
	288
	289	/* Returns number of pages spanned by the data starting at the given addr */
	290	#define PAGES_4K_SPANNED(_address, size) \
	291	((u32)((((size_t)(_address) & (PAGE_SIZE_4K - 1)) + \
	292	(size) + (PAGE_SIZE_4K - 1)) >> PAGE_SHIFT_4K))
	293
	294	/* Byte offset into the page corresponding to given address */
	295	#define OFFSET_IN_PAGE(addr) \
	296	((size_t)(addr) & (PAGE_SIZE_4K-1))
	297
	298	/* Returns bit offset within a DWORD of a bitfield */
	299	#define AMAP_BIT_OFFSET(_struct, field) \
	300	(((size_t)&(((_struct *)0)->field))%32)
	301
	302	/* Returns the bit mask of the field that is NOT shifted into location. */
	303	static inline u32 amap_mask(u32 bitsize)
	304	{
	305	return (bitsize == 32 ? 0xFFFFFFFF : (1 << bitsize) - 1);
	306	}
	307
	308	static inline void
	309	amap_set(void *ptr, u32 dw_offset, u32 mask, u32 offset, u32 value)
	310	{
	311	u32 dw = (u32 ) ptr + dw_offset;
	312	*dw &= ~(mask << offset);
	313	*dw \|= (mask & value) << offset;
	314	}
	315
	316	#define AMAP_SET_BITS(_struct, field, ptr, val) \
	317	amap_set(ptr, \
	318	offsetof(_struct, field)/32, \
	319	amap_mask(sizeof(((_struct *)0)->field)), \
	320	AMAP_BIT_OFFSET(_struct, field), \
	321	val)
	322
	323	static inline u32 amap_get(void *ptr, u32 dw_offset, u32 mask, u32 offset)
	324	{
	325	u32 dw = (u32 ) ptr;
	326	return mask & (*(dw + dw_offset) >> offset);
	327	}
	328
	329	#define AMAP_GET_BITS(_struct, field, ptr) \
	330	amap_get(ptr, \
	331	offsetof(_struct, field)/32, \
	332	amap_mask(sizeof(((_struct *)0)->field)), \
	333	AMAP_BIT_OFFSET(_struct, field))
	334
	335	#define be_dws_cpu_to_le(wrb, len) swap_dws(wrb, len)
	336	#define be_dws_le_to_cpu(wrb, len) swap_dws(wrb, len)
	337	static inline void swap_dws(void *wrb, int len)
	338	{
	339	#ifdef __BIG_ENDIAN
	340	u32 *dw = wrb;
	341	BUG_ON(len % 4);
	342	do {
	343	dw = cpu_to_le32(dw);
	344	dw++;
	345	len -= 4;
	346	} while (len);
	347	#endif /* __BIG_ENDIAN */
	348	}
	349
350	static inline u8 is_tcp_pkt(struct sk_buff *skb)
351	{
352	u8 val = 0;
353
354	if (ip_hdr(skb)->version == 4)
355	val = (ip_hdr(skb)->protocol == IPPROTO_TCP);
356	else if (ip_hdr(skb)->version == 6)
357	val = (ipv6_hdr(skb)->nexthdr == NEXTHDR_TCP);
358
359	return val;
360	}
361
362	static inline u8 is_udp_pkt(struct sk_buff *skb)
363	{
364	u8 val = 0;
365
366	if (ip_hdr(skb)->version == 4)
367	val = (ip_hdr(skb)->protocol == IPPROTO_UDP);
368	else if (ip_hdr(skb)->version == 6)
369	val = (ipv6_hdr(skb)->nexthdr == NEXTHDR_UDP);
370
371	return val;
372	}
373
5fb379ee SP	374	extern void be_cq_notify(struct be_ctrl_info *ctrl, u16 qid, bool arm,
5fb379ee SP	375	u16 num_popped);
6b7c5b94	376	#endif /* BE_H */