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Merge branch 'master' of master.kernel.org:/pub/scm/linux/kernel/git/davem/net-2.6
[deliverable/linux.git] / drivers / net / benet / be_cmds.h
CommitLineData
6b7c5b94 1/*
294aedcf 2 * Copyright (C) 2005 - 2010 ServerEngines
6b7c5b94
SP		 3 * All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License version 2
7 * as published by the Free Software Foundation. The full GNU General
8 * Public License is included in this distribution in the file called COPYING.
9 *
10 * Contact Information:
11 * linux-drivers@serverengines.com
12 *
13 * ServerEngines
14 * 209 N. Fair Oaks Ave
15 * Sunnyvale, CA 94085
16 */
17
18/*
19 * The driver sends configuration and managements command requests to the
20 * firmware in the BE. These requests are communicated to the processor
21 * using Work Request Blocks (WRBs) submitted to the MCC-WRB ring or via one
22 * WRB inside a MAILBOX.
23 * The commands are serviced by the ARM processor in the BladeEngine's MPU.
24 */
25
26struct be_sge {
27 u32 pa_lo;
28 u32 pa_hi;
29 u32 len;
30};
31
32#define MCC_WRB_EMBEDDED_MASK 1 /* bit 0 of dword 0*/
33#define MCC_WRB_SGE_CNT_SHIFT 3 /* bits 3 - 7 of dword 0 */
34#define MCC_WRB_SGE_CNT_MASK 0x1F /* bits 3 - 7 of dword 0 */
35struct be_mcc_wrb {
36 u32 embedded; /* dword 0 */
37 u32 payload_length; /* dword 1 */
38 u32 tag0; /* dword 2 */
39 u32 tag1; /* dword 3 */
40 u32 rsvd; /* dword 4 */
41 union {
42 u8 embedded_payload[236]; /* used by embedded cmds */
43 struct be_sge sgl[19]; /* used by non-embedded cmds */
44 } payload;
45};
46
47#define CQE_FLAGS_VALID_MASK (1 << 31)
48#define CQE_FLAGS_ASYNC_MASK (1 << 30)
49#define CQE_FLAGS_COMPLETED_MASK (1 << 28)
50#define CQE_FLAGS_CONSUMED_MASK (1 << 27)
51
52/* Completion Status */
53enum {
54 MCC_STATUS_SUCCESS = 0x0,
55/* The client does not have sufficient privileges to execute the command */
56 MCC_STATUS_INSUFFICIENT_PRIVILEGES = 0x1,
57/* A parameter in the command was invalid. */
58 MCC_STATUS_INVALID_PARAMETER = 0x2,
59/* There are insufficient chip resources to execute the command */
60 MCC_STATUS_INSUFFICIENT_RESOURCES = 0x3,
61/* The command is completing because the queue was getting flushed */
62 MCC_STATUS_QUEUE_FLUSHING = 0x4,
63/* The command is completing with a DMA error */
b31c50a7 64 MCC_STATUS_DMA_FAILED = 0x5,
49643848 65 MCC_STATUS_NOT_SUPPORTED = 66
6b7c5b94
SP		 66};
67
68#define CQE_STATUS_COMPL_MASK 0xFFFF
69#define CQE_STATUS_COMPL_SHIFT 0 /* bits 0 - 15 */
70#define CQE_STATUS_EXTD_MASK 0xFFFF
f5209b44 71#define CQE_STATUS_EXTD_SHIFT 16 /* bits 16 - 31 */
6b7c5b94 72
efd2e40a 73struct be_mcc_compl {
6b7c5b94
SP		 74 u32 status; /* dword 0 */
75 u32 tag0; /* dword 1 */
76 u32 tag1; /* dword 2 */
77 u32 flags; /* dword 3 */
78};
79
a8f447bd
SP		 80/* When the async bit of mcc_compl is set, the last 4 bytes of
81 * mcc_compl is interpreted as follows:
82 */
83#define ASYNC_TRAILER_EVENT_CODE_SHIFT 8 /* bits 8 - 15 */
84#define ASYNC_TRAILER_EVENT_CODE_MASK 0xFF
85#define ASYNC_EVENT_CODE_LINK_STATE 0x1
86struct be_async_event_trailer {
87 u32 code;
88};
89
90enum {
91 ASYNC_EVENT_LINK_DOWN = 0x0,
92 ASYNC_EVENT_LINK_UP = 0x1
93};
94
95/* When the event code of an async trailer is link-state, the mcc_compl
96 * must be interpreted as follows
97 */
98struct be_async_event_link_state {
99 u8 physical_port;
100 u8 port_link_status;
101 u8 port_duplex;
102 u8 port_speed;
103 u8 port_fault;
104 u8 rsvd0[7];
105 struct be_async_event_trailer trailer;
106} __packed;
107
6b7c5b94
SP		 108struct be_mcc_mailbox {
109 struct be_mcc_wrb wrb;
efd2e40a 110 struct be_mcc_compl compl;
6b7c5b94
SP		 111};
112
113#define CMD_SUBSYSTEM_COMMON 0x1
114#define CMD_SUBSYSTEM_ETH 0x3
ff33a6e2 115#define CMD_SUBSYSTEM_LOWLEVEL 0xb
6b7c5b94
SP		 116
117#define OPCODE_COMMON_NTWK_MAC_QUERY 1
118#define OPCODE_COMMON_NTWK_MAC_SET 2
119#define OPCODE_COMMON_NTWK_MULTICAST_SET 3
120#define OPCODE_COMMON_NTWK_VLAN_CONFIG 4
121#define OPCODE_COMMON_NTWK_LINK_STATUS_QUERY 5
fa9a6fed 122#define OPCODE_COMMON_READ_FLASHROM 6
84517482 123#define OPCODE_COMMON_WRITE_FLASHROM 7
6b7c5b94
SP		 124#define OPCODE_COMMON_CQ_CREATE 12
125#define OPCODE_COMMON_EQ_CREATE 13
126#define OPCODE_COMMON_MCC_CREATE 21
368c0ca2 127#define OPCODE_COMMON_SEEPROM_READ 30
6b7c5b94
SP		 128#define OPCODE_COMMON_NTWK_RX_FILTER 34
129#define OPCODE_COMMON_GET_FW_VERSION 35
130#define OPCODE_COMMON_SET_FLOW_CONTROL 36
131#define OPCODE_COMMON_GET_FLOW_CONTROL 37
132#define OPCODE_COMMON_SET_FRAME_SIZE 39
133#define OPCODE_COMMON_MODIFY_EQ_DELAY 41
134#define OPCODE_COMMON_FIRMWARE_CONFIG 42
135#define OPCODE_COMMON_NTWK_INTERFACE_CREATE 50
136#define OPCODE_COMMON_NTWK_INTERFACE_DESTROY 51
5fb379ee 137#define OPCODE_COMMON_MCC_DESTROY 53
6b7c5b94
SP		 138#define OPCODE_COMMON_CQ_DESTROY 54
139#define OPCODE_COMMON_EQ_DESTROY 55
140#define OPCODE_COMMON_QUERY_FIRMWARE_CONFIG 58
141#define OPCODE_COMMON_NTWK_PMAC_ADD 59
142#define OPCODE_COMMON_NTWK_PMAC_DEL 60
14074eab 143#define OPCODE_COMMON_FUNCTION_RESET 61
fad9ab2c
SB		 144#define OPCODE_COMMON_ENABLE_DISABLE_BEACON 69
145#define OPCODE_COMMON_GET_BEACON_STATE 70
0388f251 146#define OPCODE_COMMON_READ_TRANSRECV_DATA 73
ee3cb629 147#define OPCODE_COMMON_GET_PHY_DETAILS 102
6b7c5b94
SP		 148
149#define OPCODE_ETH_ACPI_CONFIG 2
150#define OPCODE_ETH_PROMISCUOUS 3
151#define OPCODE_ETH_GET_STATISTICS 4
152#define OPCODE_ETH_TX_CREATE 7
153#define OPCODE_ETH_RX_CREATE 8
154#define OPCODE_ETH_TX_DESTROY 9
155#define OPCODE_ETH_RX_DESTROY 10
71d8d1b5 156#define OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG 12
6b7c5b94 157
ff33a6e2
S		 158#define OPCODE_LOWLEVEL_HOST_DDR_DMA 17
159#define OPCODE_LOWLEVEL_LOOPBACK_TEST 18
fced9999 160#define OPCODE_LOWLEVEL_SET_LOOPBACK_MODE 19
ff33a6e2 161
6b7c5b94
SP		 162struct be_cmd_req_hdr {
163 u8 opcode; /* dword 0 */
164 u8 subsystem; /* dword 0 */
165 u8 port_number; /* dword 0 */
166 u8 domain; /* dword 0 */
167 u32 timeout; /* dword 1 */
168 u32 request_length; /* dword 2 */
7b139c83
AK		 169 u8 version; /* dword 3 */
170 u8 rsvd[3]; /* dword 3 */
6b7c5b94
SP		 171};
172
173#define RESP_HDR_INFO_OPCODE_SHIFT 0 /* bits 0 - 7 */
174#define RESP_HDR_INFO_SUBSYS_SHIFT 8 /* bits 8 - 15 */
175struct be_cmd_resp_hdr {
176 u32 info; /* dword 0 */
177 u32 status; /* dword 1 */
178 u32 response_length; /* dword 2 */
179 u32 actual_resp_len; /* dword 3 */
180};
181
182struct phys_addr {
183 u32 lo;
184 u32 hi;
185};
186
187/**************************
188 * BE Command definitions *
189 **************************/
190
191/* Pseudo amap definition in which each bit of the actual structure is defined
192 * as a byte: used to calculate offset/shift/mask of each field */
193struct amap_eq_context {
194 u8 cidx[13]; /* dword 0*/
195 u8 rsvd0[3]; /* dword 0*/
196 u8 epidx[13]; /* dword 0*/
197 u8 valid; /* dword 0*/
198 u8 rsvd1; /* dword 0*/
199 u8 size; /* dword 0*/
200 u8 pidx[13]; /* dword 1*/
201 u8 rsvd2[3]; /* dword 1*/
202 u8 pd[10]; /* dword 1*/
203 u8 count[3]; /* dword 1*/
204 u8 solevent; /* dword 1*/
205 u8 stalled; /* dword 1*/
206 u8 armed; /* dword 1*/
207 u8 rsvd3[4]; /* dword 2*/
208 u8 func[8]; /* dword 2*/
209 u8 rsvd4; /* dword 2*/
210 u8 delaymult[10]; /* dword 2*/
211 u8 rsvd5[2]; /* dword 2*/
212 u8 phase[2]; /* dword 2*/
213 u8 nodelay; /* dword 2*/
214 u8 rsvd6[4]; /* dword 2*/
215 u8 rsvd7[32]; /* dword 3*/
216} __packed;
217
218struct be_cmd_req_eq_create {
219 struct be_cmd_req_hdr hdr;
220 u16 num_pages; /* sword */
221 u16 rsvd0; /* sword */
222 u8 context[sizeof(struct amap_eq_context) / 8];
223 struct phys_addr pages[8];
224} __packed;
225
226struct be_cmd_resp_eq_create {
227 struct be_cmd_resp_hdr resp_hdr;
228 u16 eq_id; /* sword */
229 u16 rsvd0; /* sword */
230} __packed;
231
232/******************** Mac query ***************************/
233enum {
234 MAC_ADDRESS_TYPE_STORAGE = 0x0,
235 MAC_ADDRESS_TYPE_NETWORK = 0x1,
236 MAC_ADDRESS_TYPE_PD = 0x2,
237 MAC_ADDRESS_TYPE_MANAGEMENT = 0x3
238};
239
240struct mac_addr {
241 u16 size_of_struct;
242 u8 addr[ETH_ALEN];
243} __packed;
244
245struct be_cmd_req_mac_query {
246 struct be_cmd_req_hdr hdr;
247 u8 type;
248 u8 permanent;
249 u16 if_id;
250} __packed;
251
252struct be_cmd_resp_mac_query {
253 struct be_cmd_resp_hdr hdr;
254 struct mac_addr mac;
255};
256
257/******************** PMac Add ***************************/
258struct be_cmd_req_pmac_add {
259 struct be_cmd_req_hdr hdr;
260 u32 if_id;
261 u8 mac_address[ETH_ALEN];
262 u8 rsvd0[2];
263} __packed;
264
265struct be_cmd_resp_pmac_add {
266 struct be_cmd_resp_hdr hdr;
267 u32 pmac_id;
268};
269
270/******************** PMac Del ***************************/
271struct be_cmd_req_pmac_del {
272 struct be_cmd_req_hdr hdr;
273 u32 if_id;
274 u32 pmac_id;
275};
276
277/******************** Create CQ ***************************/
278/* Pseudo amap definition in which each bit of the actual structure is defined
279 * as a byte: used to calculate offset/shift/mask of each field */
280struct amap_cq_context {
281 u8 cidx[11]; /* dword 0*/
282 u8 rsvd0; /* dword 0*/
283 u8 coalescwm[2]; /* dword 0*/
284 u8 nodelay; /* dword 0*/
285 u8 epidx[11]; /* dword 0*/
286 u8 rsvd1; /* dword 0*/
287 u8 count[2]; /* dword 0*/
288 u8 valid; /* dword 0*/
289 u8 solevent; /* dword 0*/
290 u8 eventable; /* dword 0*/
291 u8 pidx[11]; /* dword 1*/
292 u8 rsvd2; /* dword 1*/
293 u8 pd[10]; /* dword 1*/
294 u8 eqid[8]; /* dword 1*/
295 u8 stalled; /* dword 1*/
296 u8 armed; /* dword 1*/
297 u8 rsvd3[4]; /* dword 2*/
298 u8 func[8]; /* dword 2*/
299 u8 rsvd4[20]; /* dword 2*/
300 u8 rsvd5[32]; /* dword 3*/
301} __packed;
302
303struct be_cmd_req_cq_create {
304 struct be_cmd_req_hdr hdr;
305 u16 num_pages;
306 u16 rsvd0;
307 u8 context[sizeof(struct amap_cq_context) / 8];
308 struct phys_addr pages[8];
309} __packed;
310
311struct be_cmd_resp_cq_create {
312 struct be_cmd_resp_hdr hdr;
313 u16 cq_id;
314 u16 rsvd0;
315} __packed;
316
5fb379ee
SP		 317/******************** Create MCCQ ***************************/
318/* Pseudo amap definition in which each bit of the actual structure is defined
319 * as a byte: used to calculate offset/shift/mask of each field */
320struct amap_mcc_context {
321 u8 con_index[14];
322 u8 rsvd0[2];
323 u8 ring_size[4];
324 u8 fetch_wrb;
325 u8 fetch_r2t;
326 u8 cq_id[10];
327 u8 prod_index[14];
328 u8 fid[8];
329 u8 pdid[9];
330 u8 valid;
331 u8 rsvd1[32];
332 u8 rsvd2[32];
333} __packed;
334
335struct be_cmd_req_mcc_create {
336 struct be_cmd_req_hdr hdr;
337 u16 num_pages;
338 u16 rsvd0;
339 u8 context[sizeof(struct amap_mcc_context) / 8];
340 struct phys_addr pages[8];
341} __packed;
342
343struct be_cmd_resp_mcc_create {
344 struct be_cmd_resp_hdr hdr;
345 u16 id;
346 u16 rsvd0;
347} __packed;
348
6b7c5b94
SP		 349/******************** Create TxQ ***************************/
350#define BE_ETH_TX_RING_TYPE_STANDARD 2
351#define BE_ULP1_NUM 1
352
353/* Pseudo amap definition in which each bit of the actual structure is defined
354 * as a byte: used to calculate offset/shift/mask of each field */
355struct amap_tx_context {
356 u8 rsvd0[16]; /* dword 0 */
357 u8 tx_ring_size[4]; /* dword 0 */
358 u8 rsvd1[26]; /* dword 0 */
359 u8 pci_func_id[8]; /* dword 1 */
360 u8 rsvd2[9]; /* dword 1 */
361 u8 ctx_valid; /* dword 1 */
362 u8 cq_id_send[16]; /* dword 2 */
363 u8 rsvd3[16]; /* dword 2 */
364 u8 rsvd4[32]; /* dword 3 */
365 u8 rsvd5[32]; /* dword 4 */
366 u8 rsvd6[32]; /* dword 5 */
367 u8 rsvd7[32]; /* dword 6 */
368 u8 rsvd8[32]; /* dword 7 */
369 u8 rsvd9[32]; /* dword 8 */
370 u8 rsvd10[32]; /* dword 9 */
371 u8 rsvd11[32]; /* dword 10 */
372 u8 rsvd12[32]; /* dword 11 */
373 u8 rsvd13[32]; /* dword 12 */
374 u8 rsvd14[32]; /* dword 13 */
375 u8 rsvd15[32]; /* dword 14 */
376 u8 rsvd16[32]; /* dword 15 */
377} __packed;
378
379struct be_cmd_req_eth_tx_create {
380 struct be_cmd_req_hdr hdr;
381 u8 num_pages;
382 u8 ulp_num;
383 u8 type;
384 u8 bound_port;
385 u8 context[sizeof(struct amap_tx_context) / 8];
386 struct phys_addr pages[8];
387} __packed;
388
389struct be_cmd_resp_eth_tx_create {
390 struct be_cmd_resp_hdr hdr;
391 u16 cid;
392 u16 rsvd0;
393} __packed;
394
395/******************** Create RxQ ***************************/
396struct be_cmd_req_eth_rx_create {
397 struct be_cmd_req_hdr hdr;
398 u16 cq_id;
399 u8 frag_size;
400 u8 num_pages;
401 struct phys_addr pages[2];
402 u32 interface_id;
403 u16 max_frame_size;
404 u16 rsvd0;
405 u32 rss_queue;
406} __packed;
407
408struct be_cmd_resp_eth_rx_create {
409 struct be_cmd_resp_hdr hdr;
410 u16 id;
411 u8 cpu_id;
412 u8 rsvd0;
413} __packed;
414
415/******************** Q Destroy ***************************/
416/* Type of Queue to be destroyed */
417enum {
418 QTYPE_EQ = 1,
419 QTYPE_CQ,
420 QTYPE_TXQ,
5fb379ee
SP		 421 QTYPE_RXQ,
422 QTYPE_MCCQ
6b7c5b94
SP		 423};
424
425struct be_cmd_req_q_destroy {
426 struct be_cmd_req_hdr hdr;
427 u16 id;
428 u16 bypass_flush; /* valid only for rx q destroy */
429} __packed;
430
431/************ I/f Create (it's actually I/f Config Create)**********/
432
433/* Capability flags for the i/f */
434enum be_if_flags {
435 BE_IF_FLAGS_RSS = 0x4,
436 BE_IF_FLAGS_PROMISCUOUS = 0x8,
437 BE_IF_FLAGS_BROADCAST = 0x10,
438 BE_IF_FLAGS_UNTAGGED = 0x20,
439 BE_IF_FLAGS_ULP = 0x40,
440 BE_IF_FLAGS_VLAN_PROMISCUOUS = 0x80,
441 BE_IF_FLAGS_VLAN = 0x100,
442 BE_IF_FLAGS_MCAST_PROMISCUOUS = 0x200,
443 BE_IF_FLAGS_PASS_L2_ERRORS = 0x400,
444 BE_IF_FLAGS_PASS_L3L4_ERRORS = 0x800
445};
446
447/* An RX interface is an object with one or more MAC addresses and
448 * filtering capabilities. */
449struct be_cmd_req_if_create {
450 struct be_cmd_req_hdr hdr;
af901ca1 451 u32 version; /* ignore currently */
6b7c5b94
SP		 452 u32 capability_flags;
453 u32 enable_flags;
454 u8 mac_addr[ETH_ALEN];
455 u8 rsvd0;
456 u8 pmac_invalid; /* if set, don't attach the mac addr to the i/f */
457 u32 vlan_tag; /* not used currently */
458} __packed;
459
460struct be_cmd_resp_if_create {
461 struct be_cmd_resp_hdr hdr;
462 u32 interface_id;
463 u32 pmac_id;
464};
465
466/****** I/f Destroy(it's actually I/f Config Destroy )**********/
467struct be_cmd_req_if_destroy {
468 struct be_cmd_req_hdr hdr;
469 u32 interface_id;
470};
471
472/*************** HW Stats Get **********************************/
473struct be_port_rxf_stats {
474 u32 rx_bytes_lsd; /* dword 0*/
475 u32 rx_bytes_msd; /* dword 1*/
476 u32 rx_total_frames; /* dword 2*/
477 u32 rx_unicast_frames; /* dword 3*/
478 u32 rx_multicast_frames; /* dword 4*/
479 u32 rx_broadcast_frames; /* dword 5*/
480 u32 rx_crc_errors; /* dword 6*/
481 u32 rx_alignment_symbol_errors; /* dword 7*/
482 u32 rx_pause_frames; /* dword 8*/
483 u32 rx_control_frames; /* dword 9*/
484 u32 rx_in_range_errors; /* dword 10*/
485 u32 rx_out_range_errors; /* dword 11*/
486 u32 rx_frame_too_long; /* dword 12*/
487 u32 rx_address_match_errors; /* dword 13*/
488 u32 rx_vlan_mismatch; /* dword 14*/
489 u32 rx_dropped_too_small; /* dword 15*/
490 u32 rx_dropped_too_short; /* dword 16*/
491 u32 rx_dropped_header_too_small; /* dword 17*/
492 u32 rx_dropped_tcp_length; /* dword 18*/
493 u32 rx_dropped_runt; /* dword 19*/
494 u32 rx_64_byte_packets; /* dword 20*/
495 u32 rx_65_127_byte_packets; /* dword 21*/
496 u32 rx_128_256_byte_packets; /* dword 22*/
497 u32 rx_256_511_byte_packets; /* dword 23*/
498 u32 rx_512_1023_byte_packets; /* dword 24*/
499 u32 rx_1024_1518_byte_packets; /* dword 25*/
500 u32 rx_1519_2047_byte_packets; /* dword 26*/
501 u32 rx_2048_4095_byte_packets; /* dword 27*/
502 u32 rx_4096_8191_byte_packets; /* dword 28*/
503 u32 rx_8192_9216_byte_packets; /* dword 29*/
504 u32 rx_ip_checksum_errs; /* dword 30*/
505 u32 rx_tcp_checksum_errs; /* dword 31*/
506 u32 rx_udp_checksum_errs; /* dword 32*/
507 u32 rx_non_rss_packets; /* dword 33*/
508 u32 rx_ipv4_packets; /* dword 34*/
509 u32 rx_ipv6_packets; /* dword 35*/
510 u32 rx_ipv4_bytes_lsd; /* dword 36*/
511 u32 rx_ipv4_bytes_msd; /* dword 37*/
512 u32 rx_ipv6_bytes_lsd; /* dword 38*/
513 u32 rx_ipv6_bytes_msd; /* dword 39*/
514 u32 rx_chute1_packets; /* dword 40*/
515 u32 rx_chute2_packets; /* dword 41*/
516 u32 rx_chute3_packets; /* dword 42*/
517 u32 rx_management_packets; /* dword 43*/
518 u32 rx_switched_unicast_packets; /* dword 44*/
519 u32 rx_switched_multicast_packets; /* dword 45*/
520 u32 rx_switched_broadcast_packets; /* dword 46*/
521 u32 tx_bytes_lsd; /* dword 47*/
522 u32 tx_bytes_msd; /* dword 48*/
523 u32 tx_unicastframes; /* dword 49*/
524 u32 tx_multicastframes; /* dword 50*/
525 u32 tx_broadcastframes; /* dword 51*/
526 u32 tx_pauseframes; /* dword 52*/
527 u32 tx_controlframes; /* dword 53*/
528 u32 tx_64_byte_packets; /* dword 54*/
529 u32 tx_65_127_byte_packets; /* dword 55*/
530 u32 tx_128_256_byte_packets; /* dword 56*/
531 u32 tx_256_511_byte_packets; /* dword 57*/
532 u32 tx_512_1023_byte_packets; /* dword 58*/
533 u32 tx_1024_1518_byte_packets; /* dword 59*/
534 u32 tx_1519_2047_byte_packets; /* dword 60*/
535 u32 tx_2048_4095_byte_packets; /* dword 61*/
536 u32 tx_4096_8191_byte_packets; /* dword 62*/
537 u32 tx_8192_9216_byte_packets; /* dword 63*/
538 u32 rx_fifo_overflow; /* dword 64*/
539 u32 rx_input_fifo_overflow; /* dword 65*/
540};
541
542struct be_rxf_stats {
543 struct be_port_rxf_stats port[2];
544 u32 rx_drops_no_pbuf; /* dword 132*/
545 u32 rx_drops_no_txpb; /* dword 133*/
546 u32 rx_drops_no_erx_descr; /* dword 134*/
547 u32 rx_drops_no_tpre_descr; /* dword 135*/
548 u32 management_rx_port_packets; /* dword 136*/
549 u32 management_rx_port_bytes; /* dword 137*/
550 u32 management_rx_port_pause_frames; /* dword 138*/
551 u32 management_rx_port_errors; /* dword 139*/
552 u32 management_tx_port_packets; /* dword 140*/
553 u32 management_tx_port_bytes; /* dword 141*/
554 u32 management_tx_port_pause; /* dword 142*/
555 u32 management_rx_port_rxfifo_overflow; /* dword 143*/
556 u32 rx_drops_too_many_frags; /* dword 144*/
557 u32 rx_drops_invalid_ring; /* dword 145*/
558 u32 forwarded_packets; /* dword 146*/
559 u32 rx_drops_mtu; /* dword 147*/
560 u32 rsvd0[15];
561};
562
563struct be_erx_stats {
564 u32 rx_drops_no_fragments[44]; /* dwordS 0 to 43*/
565 u32 debug_wdma_sent_hold; /* dword 44*/
566 u32 debug_wdma_pbfree_sent_hold; /* dword 45*/
567 u32 debug_wdma_zerobyte_pbfree_sent_hold; /* dword 46*/
568 u32 debug_pmem_pbuf_dealloc; /* dword 47*/
569};
570
571struct be_hw_stats {
572 struct be_rxf_stats rxf;
573 u32 rsvd[48];
574 struct be_erx_stats erx;
575};
576
577struct be_cmd_req_get_stats {
578 struct be_cmd_req_hdr hdr;
579 u8 rsvd[sizeof(struct be_hw_stats)];
580};
581
582struct be_cmd_resp_get_stats {
583 struct be_cmd_resp_hdr hdr;
584 struct be_hw_stats hw_stats;
585};
586
587struct be_cmd_req_vlan_config {
588 struct be_cmd_req_hdr hdr;
589 u8 interface_id;
590 u8 promiscuous;
591 u8 untagged;
592 u8 num_vlan;
593 u16 normal_vlan[64];
594} __packed;
595
596struct be_cmd_req_promiscuous_config {
597 struct be_cmd_req_hdr hdr;
598 u8 port0_promiscuous;
599 u8 port1_promiscuous;
600 u16 rsvd0;
601} __packed;
602
e7b909a6
SP		 603/******************** Multicast MAC Config *******************/
604#define BE_MAX_MC 64 /* set mcast promisc if > 64 */
6b7c5b94
SP		 605struct macaddr {
606 u8 byte[ETH_ALEN];
607};
608
609struct be_cmd_req_mcast_mac_config {
610 struct be_cmd_req_hdr hdr;
611 u16 num_mac;
612 u8 promiscuous;
613 u8 interface_id;
e7b909a6 614 struct macaddr mac[BE_MAX_MC];
6b7c5b94
SP		 615} __packed;
616
617static inline struct be_hw_stats *
618hw_stats_from_cmd(struct be_cmd_resp_get_stats *cmd)
619{
620 return &cmd->hw_stats;
621}
622
623/******************** Link Status Query *******************/
624struct be_cmd_req_link_status {
625 struct be_cmd_req_hdr hdr;
626 u32 rsvd;
627};
628
6b7c5b94
SP		 629enum {
630 PHY_LINK_DUPLEX_NONE = 0x0,
631 PHY_LINK_DUPLEX_HALF = 0x1,
632 PHY_LINK_DUPLEX_FULL = 0x2
633};
634
635enum {
636 PHY_LINK_SPEED_ZERO = 0x0, /* => No link */
637 PHY_LINK_SPEED_10MBPS = 0x1,
638 PHY_LINK_SPEED_100MBPS = 0x2,
639 PHY_LINK_SPEED_1GBPS = 0x3,
640 PHY_LINK_SPEED_10GBPS = 0x4
641};
642
643struct be_cmd_resp_link_status {
644 struct be_cmd_resp_hdr hdr;
645 u8 physical_port;
646 u8 mac_duplex;
647 u8 mac_speed;
648 u8 mac_fault;
649 u8 mgmt_mac_duplex;
650 u8 mgmt_mac_speed;
0388f251
SB		 651 u16 link_speed;
652 u32 rsvd0;
6b7c5b94
SP		 653} __packed;
654
0388f251
SB		 655/******************** Port Identification ***************************/
656/* Identifies the type of port attached to NIC */
657struct be_cmd_req_port_type {
658 struct be_cmd_req_hdr hdr;
659 u32 page_num;
660 u32 port;
661};
662
663enum {
664 TR_PAGE_A0 = 0xa0,
665 TR_PAGE_A2 = 0xa2
666};
667
668struct be_cmd_resp_port_type {
669 struct be_cmd_resp_hdr hdr;
670 u32 page_num;
671 u32 port;
672 struct data {
673 u8 identifier;
674 u8 identifier_ext;
675 u8 connector;
676 u8 transceiver[8];
677 u8 rsvd0[3];
678 u8 length_km;
679 u8 length_hm;
680 u8 length_om1;
681 u8 length_om2;
682 u8 length_cu;
683 u8 length_cu_m;
684 u8 vendor_name[16];
685 u8 rsvd;
686 u8 vendor_oui[3];
687 u8 vendor_pn[16];
688 u8 vendor_rev[4];
689 } data;
690};
691
6b7c5b94 692/******************** Get FW Version *******************/
6b7c5b94
SP		 693struct be_cmd_req_get_fw_version {
694 struct be_cmd_req_hdr hdr;
695 u8 rsvd0[FW_VER_LEN];
696 u8 rsvd1[FW_VER_LEN];
697} __packed;
698
699struct be_cmd_resp_get_fw_version {
700 struct be_cmd_resp_hdr hdr;
701 u8 firmware_version_string[FW_VER_LEN];
702 u8 fw_on_flash_version_string[FW_VER_LEN];
703} __packed;
704
705/******************** Set Flow Contrl *******************/
706struct be_cmd_req_set_flow_control {
707 struct be_cmd_req_hdr hdr;
708 u16 tx_flow_control;
709 u16 rx_flow_control;
710} __packed;
711
712/******************** Get Flow Contrl *******************/
713struct be_cmd_req_get_flow_control {
714 struct be_cmd_req_hdr hdr;
715 u32 rsvd;
716};
717
718struct be_cmd_resp_get_flow_control {
719 struct be_cmd_resp_hdr hdr;
720 u16 tx_flow_control;
721 u16 rx_flow_control;
722} __packed;
723
724/******************** Modify EQ Delay *******************/
725struct be_cmd_req_modify_eq_delay {
726 struct be_cmd_req_hdr hdr;
727 u32 num_eq;
728 struct {
729 u32 eq_id;
730 u32 phase;
731 u32 delay_multiplier;
732 } delay[8];
733} __packed;
734
735struct be_cmd_resp_modify_eq_delay {
736 struct be_cmd_resp_hdr hdr;
737 u32 rsvd0;
738} __packed;
739
740/******************** Get FW Config *******************/
741struct be_cmd_req_query_fw_cfg {
742 struct be_cmd_req_hdr hdr;
743 u32 rsvd[30];
744};
745
746struct be_cmd_resp_query_fw_cfg {
747 struct be_cmd_resp_hdr hdr;
748 u32 be_config_number;
749 u32 asic_revision;
750 u32 phys_port;
84517482 751 u32 function_cap;
6b7c5b94
SP		 752 u32 rsvd[26];
753};
754
fad9ab2c
SB		 755/******************** Port Beacon ***************************/
756
757#define BEACON_STATE_ENABLED 0x1
758#define BEACON_STATE_DISABLED 0x0
759
760struct be_cmd_req_enable_disable_beacon {
761 struct be_cmd_req_hdr hdr;
762 u8 port_num;
763 u8 beacon_state;
764 u8 beacon_duration;
765 u8 status_duration;
766} __packed;
767
768struct be_cmd_resp_enable_disable_beacon {
769 struct be_cmd_resp_hdr resp_hdr;
770 u32 rsvd0;
771} __packed;
772
773struct be_cmd_req_get_beacon_state {
774 struct be_cmd_req_hdr hdr;
775 u8 port_num;
776 u8 rsvd0;
777 u16 rsvd1;
778} __packed;
779
780struct be_cmd_resp_get_beacon_state {
781 struct be_cmd_resp_hdr resp_hdr;
782 u8 beacon_state;
783 u8 rsvd0[3];
784} __packed;
785
84517482
AK		 786/****************** Firmware Flash ******************/
787struct flashrom_params {
788 u32 op_code;
789 u32 op_type;
790 u32 data_buf_size;
791 u32 offset;
792 u8 data_buf[4];
793};
794
795struct be_cmd_write_flashrom {
796 struct be_cmd_req_hdr hdr;
797 struct flashrom_params params;
798};
799
71d8d1b5
AK		 800/************************ WOL *******************************/
801struct be_cmd_req_acpi_wol_magic_config{
802 struct be_cmd_req_hdr hdr;
803 u32 rsvd0[145];
804 u8 magic_mac[6];
805 u8 rsvd2[2];
806} __packed;
807
ff33a6e2
S		 808/********************** LoopBack test *********************/
809struct be_cmd_req_loopback_test {
810 struct be_cmd_req_hdr hdr;
811 u32 loopback_type;
812 u32 num_pkts;
813 u64 pattern;
814 u32 src_port;
815 u32 dest_port;
816 u32 pkt_size;
817};
818
819struct be_cmd_resp_loopback_test {
820 struct be_cmd_resp_hdr resp_hdr;
821 u32 status;
822 u32 num_txfer;
823 u32 num_rx;
824 u32 miscomp_off;
825 u32 ticks_compl;
826};
827
fced9999
SB		 828struct be_cmd_req_set_lmode {
829 struct be_cmd_req_hdr hdr;
830 u8 src_port;
831 u8 dest_port;
832 u8 loopback_type;
833 u8 loopback_state;
834};
835
836struct be_cmd_resp_set_lmode {
837 struct be_cmd_resp_hdr resp_hdr;
838 u8 rsvd0[4];
839};
840
ff33a6e2
S		 841/********************** DDR DMA test *********************/
842struct be_cmd_req_ddrdma_test {
843 struct be_cmd_req_hdr hdr;
844 u64 pattern;
845 u32 byte_count;
846 u32 rsvd0;
847 u8 snd_buff[4096];
848 u8 rsvd1[4096];
849};
850
851struct be_cmd_resp_ddrdma_test {
852 struct be_cmd_resp_hdr hdr;
853 u64 pattern;
854 u32 byte_cnt;
855 u32 snd_err;
856 u8 rsvd0[4096];
857 u8 rcv_buff[4096];
858};
859
368c0ca2
SB		 860/*********************** SEEPROM Read ***********************/
861
862#define BE_READ_SEEPROM_LEN 1024
863struct be_cmd_req_seeprom_read {
864 struct be_cmd_req_hdr hdr;
865 u8 rsvd0[BE_READ_SEEPROM_LEN];
866};
867
868struct be_cmd_resp_seeprom_read {
869 struct be_cmd_req_hdr hdr;
870 u8 seeprom_data[BE_READ_SEEPROM_LEN];
871};
872
ee3cb629
AK		 873enum {
874 PHY_TYPE_CX4_10GB = 0,
875 PHY_TYPE_XFP_10GB,
876 PHY_TYPE_SFP_1GB,
877 PHY_TYPE_SFP_PLUS_10GB,
878 PHY_TYPE_KR_10GB,
879 PHY_TYPE_KX4_10GB,
880 PHY_TYPE_BASET_10GB,
881 PHY_TYPE_BASET_1GB,
882 PHY_TYPE_DISABLED = 255
883};
884
885struct be_cmd_req_get_phy_info {
886 struct be_cmd_req_hdr hdr;
887 u8 rsvd0[24];
888};
889struct be_cmd_resp_get_phy_info {
890 struct be_cmd_req_hdr hdr;
891 u16 phy_type;
892 u16 interface_type;
893 u32 misc_params;
894 u32 future_use[4];
895};
896
8788fdc2
SP		 897extern int be_pci_fnum_get(struct be_adapter *adapter);
898extern int be_cmd_POST(struct be_adapter *adapter);
899extern int be_cmd_mac_addr_query(struct be_adapter *adapter, u8 *mac_addr,
6b7c5b94 900 u8 type, bool permanent, u32 if_handle);
8788fdc2 901extern int be_cmd_pmac_add(struct be_adapter *adapter, u8 *mac_addr,
6b7c5b94 902 u32 if_id, u32 *pmac_id);
8788fdc2 903extern int be_cmd_pmac_del(struct be_adapter *adapter, u32 if_id, u32 pmac_id);
73d540f2
SP		 904extern int be_cmd_if_create(struct be_adapter *adapter, u32 cap_flags,
905 u32 en_flags, u8 *mac, bool pmac_invalid,
ba343c77 906 u32 *if_handle, u32 *pmac_id, u32 domain);
8788fdc2
SP		 907extern int be_cmd_if_destroy(struct be_adapter *adapter, u32 if_handle);
908extern int be_cmd_eq_create(struct be_adapter *adapter,
6b7c5b94 909 struct be_queue_info *eq, int eq_delay);
8788fdc2 910extern int be_cmd_cq_create(struct be_adapter *adapter,
6b7c5b94
SP		 911 struct be_queue_info *cq, struct be_queue_info *eq,
912 bool sol_evts, bool no_delay,
913 int num_cqe_dma_coalesce);
8788fdc2 914extern int be_cmd_mccq_create(struct be_adapter *adapter,
5fb379ee
SP		 915 struct be_queue_info *mccq,
916 struct be_queue_info *cq);
8788fdc2 917extern int be_cmd_txq_create(struct be_adapter *adapter,
6b7c5b94
SP		 918 struct be_queue_info *txq,
919 struct be_queue_info *cq);
8788fdc2 920extern int be_cmd_rxq_create(struct be_adapter *adapter,
6b7c5b94
SP		 921 struct be_queue_info *rxq, u16 cq_id,
922 u16 frag_size, u16 max_frame_size, u32 if_id,
923 u32 rss);
8788fdc2 924extern int be_cmd_q_destroy(struct be_adapter *adapter, struct be_queue_info *q,
6b7c5b94 925 int type);
8788fdc2 926extern int be_cmd_link_status_query(struct be_adapter *adapter,
0388f251 927 bool *link_up, u8 *mac_speed, u16 *link_speed);
8788fdc2
SP		 928extern int be_cmd_reset(struct be_adapter *adapter);
929extern int be_cmd_get_stats(struct be_adapter *adapter,
6b7c5b94 930 struct be_dma_mem *nonemb_cmd);
8788fdc2 931extern int be_cmd_get_fw_ver(struct be_adapter *adapter, char *fw_ver);
6b7c5b94 932
8788fdc2
SP		 933extern int be_cmd_modify_eqd(struct be_adapter *adapter, u32 eq_id, u32 eqd);
934extern int be_cmd_vlan_config(struct be_adapter *adapter, u32 if_id,
6b7c5b94
SP		 935 u16 *vtag_array, u32 num, bool untagged,
936 bool promiscuous);
8788fdc2 937extern int be_cmd_promiscuous_config(struct be_adapter *adapter,
6b7c5b94 938 u8 port_num, bool en);
8788fdc2 939extern int be_cmd_multicast_set(struct be_adapter *adapter, u32 if_id,
0ddf477b 940 struct net_device *netdev, struct be_dma_mem *mem);
8788fdc2 941extern int be_cmd_set_flow_control(struct be_adapter *adapter,
6b7c5b94 942 u32 tx_fc, u32 rx_fc);
8788fdc2 943extern int be_cmd_get_flow_control(struct be_adapter *adapter,
6b7c5b94 944 u32 *tx_fc, u32 *rx_fc);
dcb9b564
AK		 945extern int be_cmd_query_fw_cfg(struct be_adapter *adapter,
946 u32 *port_num, u32 *cap);
14074eab 947extern int be_cmd_reset_function(struct be_adapter *adapter);
f31e50a8 948extern int be_process_mcc(struct be_adapter *adapter, int *status);
fad9ab2c
SB		 949extern int be_cmd_set_beacon_state(struct be_adapter *adapter,
950 u8 port_num, u8 beacon, u8 status, u8 state);
951extern int be_cmd_get_beacon_state(struct be_adapter *adapter,
952 u8 port_num, u32 *state);
0388f251
SB		 953extern int be_cmd_read_port_type(struct be_adapter *adapter, u32 port,
954 u8 *connector);
84517482
AK		 955extern int be_cmd_write_flashrom(struct be_adapter *adapter,
956 struct be_dma_mem *cmd, u32 flash_oper,
957 u32 flash_opcode, u32 buf_size);
3f0d4560
AK		 958int be_cmd_get_flash_crc(struct be_adapter *adapter, u8 *flashed_crc,
959 int offset);
71d8d1b5
AK		 960extern int be_cmd_enable_magic_wol(struct be_adapter *adapter, u8 *mac,
961 struct be_dma_mem *nonemb_cmd);
2243e2e9
SP		 962extern int be_cmd_fw_init(struct be_adapter *adapter);
963extern int be_cmd_fw_clean(struct be_adapter *adapter);
7a1e9b20
SP		 964extern void be_async_mcc_enable(struct be_adapter *adapter);
965extern void be_async_mcc_disable(struct be_adapter *adapter);
ff33a6e2
S		 966extern int be_cmd_loopback_test(struct be_adapter *adapter, u32 port_num,
967 u32 loopback_type, u32 pkt_size,
968 u32 num_pkts, u64 pattern);
969extern int be_cmd_ddr_dma_test(struct be_adapter *adapter, u64 pattern,
970 u32 byte_cnt, struct be_dma_mem *cmd);
368c0ca2
SB		 971extern int be_cmd_get_seeprom_data(struct be_adapter *adapter,
972 struct be_dma_mem *nonemb_cmd);
fced9999
SB		 973extern int be_cmd_set_loopback(struct be_adapter *adapter, u8 port_num,
974 u8 loopback_type, u8 enable);
ee3cb629
AK		 975extern int be_cmd_get_phy_info(struct be_adapter *adapter,
976 struct be_dma_mem *cmd);
d4a66e75 977
Linux kernel - Deliverables
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