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ext3: Flush disk caches on fsync when needed
[deliverable/linux.git] / drivers / net / benet / be_cmds.h
CommitLineData
6b7c5b94
SP		 1/*
2 * Copyright (C) 2005 - 2009 ServerEngines
3 * All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License version 2
7 * as published by the Free Software Foundation. The full GNU General
8 * Public License is included in this distribution in the file called COPYING.
9 *
10 * Contact Information:
11 * linux-drivers@serverengines.com
12 *
13 * ServerEngines
14 * 209 N. Fair Oaks Ave
15 * Sunnyvale, CA 94085
16 */
17
18/*
19 * The driver sends configuration and managements command requests to the
20 * firmware in the BE. These requests are communicated to the processor
21 * using Work Request Blocks (WRBs) submitted to the MCC-WRB ring or via one
22 * WRB inside a MAILBOX.
23 * The commands are serviced by the ARM processor in the BladeEngine's MPU.
24 */
25
26struct be_sge {
27 u32 pa_lo;
28 u32 pa_hi;
29 u32 len;
30};
31
32#define MCC_WRB_EMBEDDED_MASK 1 /* bit 0 of dword 0*/
33#define MCC_WRB_SGE_CNT_SHIFT 3 /* bits 3 - 7 of dword 0 */
34#define MCC_WRB_SGE_CNT_MASK 0x1F /* bits 3 - 7 of dword 0 */
35struct be_mcc_wrb {
36 u32 embedded; /* dword 0 */
37 u32 payload_length; /* dword 1 */
38 u32 tag0; /* dword 2 */
39 u32 tag1; /* dword 3 */
40 u32 rsvd; /* dword 4 */
41 union {
42 u8 embedded_payload[236]; /* used by embedded cmds */
43 struct be_sge sgl[19]; /* used by non-embedded cmds */
44 } payload;
45};
46
47#define CQE_FLAGS_VALID_MASK (1 << 31)
48#define CQE_FLAGS_ASYNC_MASK (1 << 30)
49#define CQE_FLAGS_COMPLETED_MASK (1 << 28)
50#define CQE_FLAGS_CONSUMED_MASK (1 << 27)
51
52/* Completion Status */
53enum {
54 MCC_STATUS_SUCCESS = 0x0,
55/* The client does not have sufficient privileges to execute the command */
56 MCC_STATUS_INSUFFICIENT_PRIVILEGES = 0x1,
57/* A parameter in the command was invalid. */
58 MCC_STATUS_INVALID_PARAMETER = 0x2,
59/* There are insufficient chip resources to execute the command */
60 MCC_STATUS_INSUFFICIENT_RESOURCES = 0x3,
61/* The command is completing because the queue was getting flushed */
62 MCC_STATUS_QUEUE_FLUSHING = 0x4,
63/* The command is completing with a DMA error */
64 MCC_STATUS_DMA_FAILED = 0x5
65};
66
67#define CQE_STATUS_COMPL_MASK 0xFFFF
68#define CQE_STATUS_COMPL_SHIFT 0 /* bits 0 - 15 */
69#define CQE_STATUS_EXTD_MASK 0xFFFF
70#define CQE_STATUS_EXTD_SHIFT 0 /* bits 0 - 15 */
71
efd2e40a 72struct be_mcc_compl {
6b7c5b94
SP		 73 u32 status; /* dword 0 */
74 u32 tag0; /* dword 1 */
75 u32 tag1; /* dword 2 */
76 u32 flags; /* dword 3 */
77};
78
a8f447bd
SP		 79/* When the async bit of mcc_compl is set, the last 4 bytes of
80 * mcc_compl is interpreted as follows:
81 */
82#define ASYNC_TRAILER_EVENT_CODE_SHIFT 8 /* bits 8 - 15 */
83#define ASYNC_TRAILER_EVENT_CODE_MASK 0xFF
84#define ASYNC_EVENT_CODE_LINK_STATE 0x1
85struct be_async_event_trailer {
86 u32 code;
87};
88
89enum {
90 ASYNC_EVENT_LINK_DOWN = 0x0,
91 ASYNC_EVENT_LINK_UP = 0x1
92};
93
94/* When the event code of an async trailer is link-state, the mcc_compl
95 * must be interpreted as follows
96 */
97struct be_async_event_link_state {
98 u8 physical_port;
99 u8 port_link_status;
100 u8 port_duplex;
101 u8 port_speed;
102 u8 port_fault;
103 u8 rsvd0[7];
104 struct be_async_event_trailer trailer;
105} __packed;
106
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SP		 107struct be_mcc_mailbox {
108 struct be_mcc_wrb wrb;
efd2e40a 109 struct be_mcc_compl compl;
6b7c5b94
SP		 110};
111
112#define CMD_SUBSYSTEM_COMMON 0x1
113#define CMD_SUBSYSTEM_ETH 0x3
114
115#define OPCODE_COMMON_NTWK_MAC_QUERY 1
116#define OPCODE_COMMON_NTWK_MAC_SET 2
117#define OPCODE_COMMON_NTWK_MULTICAST_SET 3
118#define OPCODE_COMMON_NTWK_VLAN_CONFIG 4
119#define OPCODE_COMMON_NTWK_LINK_STATUS_QUERY 5
84517482 120#define OPCODE_COMMON_WRITE_FLASHROM 7
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SP		 121#define OPCODE_COMMON_CQ_CREATE 12
122#define OPCODE_COMMON_EQ_CREATE 13
123#define OPCODE_COMMON_MCC_CREATE 21
124#define OPCODE_COMMON_NTWK_RX_FILTER 34
125#define OPCODE_COMMON_GET_FW_VERSION 35
126#define OPCODE_COMMON_SET_FLOW_CONTROL 36
127#define OPCODE_COMMON_GET_FLOW_CONTROL 37
128#define OPCODE_COMMON_SET_FRAME_SIZE 39
129#define OPCODE_COMMON_MODIFY_EQ_DELAY 41
130#define OPCODE_COMMON_FIRMWARE_CONFIG 42
131#define OPCODE_COMMON_NTWK_INTERFACE_CREATE 50
132#define OPCODE_COMMON_NTWK_INTERFACE_DESTROY 51
5fb379ee 133#define OPCODE_COMMON_MCC_DESTROY 53
6b7c5b94
SP		 134#define OPCODE_COMMON_CQ_DESTROY 54
135#define OPCODE_COMMON_EQ_DESTROY 55
136#define OPCODE_COMMON_QUERY_FIRMWARE_CONFIG 58
137#define OPCODE_COMMON_NTWK_PMAC_ADD 59
138#define OPCODE_COMMON_NTWK_PMAC_DEL 60
14074eab 139#define OPCODE_COMMON_FUNCTION_RESET 61
6b7c5b94
SP		 140
141#define OPCODE_ETH_ACPI_CONFIG 2
142#define OPCODE_ETH_PROMISCUOUS 3
143#define OPCODE_ETH_GET_STATISTICS 4
144#define OPCODE_ETH_TX_CREATE 7
145#define OPCODE_ETH_RX_CREATE 8
146#define OPCODE_ETH_TX_DESTROY 9
147#define OPCODE_ETH_RX_DESTROY 10
148
149struct be_cmd_req_hdr {
150 u8 opcode; /* dword 0 */
151 u8 subsystem; /* dword 0 */
152 u8 port_number; /* dword 0 */
153 u8 domain; /* dword 0 */
154 u32 timeout; /* dword 1 */
155 u32 request_length; /* dword 2 */
156 u32 rsvd; /* dword 3 */
157};
158
159#define RESP_HDR_INFO_OPCODE_SHIFT 0 /* bits 0 - 7 */
160#define RESP_HDR_INFO_SUBSYS_SHIFT 8 /* bits 8 - 15 */
161struct be_cmd_resp_hdr {
162 u32 info; /* dword 0 */
163 u32 status; /* dword 1 */
164 u32 response_length; /* dword 2 */
165 u32 actual_resp_len; /* dword 3 */
166};
167
168struct phys_addr {
169 u32 lo;
170 u32 hi;
171};
172
173/**************************
174 * BE Command definitions *
175 **************************/
176
177/* Pseudo amap definition in which each bit of the actual structure is defined
178 * as a byte: used to calculate offset/shift/mask of each field */
179struct amap_eq_context {
180 u8 cidx[13]; /* dword 0*/
181 u8 rsvd0[3]; /* dword 0*/
182 u8 epidx[13]; /* dword 0*/
183 u8 valid; /* dword 0*/
184 u8 rsvd1; /* dword 0*/
185 u8 size; /* dword 0*/
186 u8 pidx[13]; /* dword 1*/
187 u8 rsvd2[3]; /* dword 1*/
188 u8 pd[10]; /* dword 1*/
189 u8 count[3]; /* dword 1*/
190 u8 solevent; /* dword 1*/
191 u8 stalled; /* dword 1*/
192 u8 armed; /* dword 1*/
193 u8 rsvd3[4]; /* dword 2*/
194 u8 func[8]; /* dword 2*/
195 u8 rsvd4; /* dword 2*/
196 u8 delaymult[10]; /* dword 2*/
197 u8 rsvd5[2]; /* dword 2*/
198 u8 phase[2]; /* dword 2*/
199 u8 nodelay; /* dword 2*/
200 u8 rsvd6[4]; /* dword 2*/
201 u8 rsvd7[32]; /* dword 3*/
202} __packed;
203
204struct be_cmd_req_eq_create {
205 struct be_cmd_req_hdr hdr;
206 u16 num_pages; /* sword */
207 u16 rsvd0; /* sword */
208 u8 context[sizeof(struct amap_eq_context) / 8];
209 struct phys_addr pages[8];
210} __packed;
211
212struct be_cmd_resp_eq_create {
213 struct be_cmd_resp_hdr resp_hdr;
214 u16 eq_id; /* sword */
215 u16 rsvd0; /* sword */
216} __packed;
217
218/******************** Mac query ***************************/
219enum {
220 MAC_ADDRESS_TYPE_STORAGE = 0x0,
221 MAC_ADDRESS_TYPE_NETWORK = 0x1,
222 MAC_ADDRESS_TYPE_PD = 0x2,
223 MAC_ADDRESS_TYPE_MANAGEMENT = 0x3
224};
225
226struct mac_addr {
227 u16 size_of_struct;
228 u8 addr[ETH_ALEN];
229} __packed;
230
231struct be_cmd_req_mac_query {
232 struct be_cmd_req_hdr hdr;
233 u8 type;
234 u8 permanent;
235 u16 if_id;
236} __packed;
237
238struct be_cmd_resp_mac_query {
239 struct be_cmd_resp_hdr hdr;
240 struct mac_addr mac;
241};
242
243/******************** PMac Add ***************************/
244struct be_cmd_req_pmac_add {
245 struct be_cmd_req_hdr hdr;
246 u32 if_id;
247 u8 mac_address[ETH_ALEN];
248 u8 rsvd0[2];
249} __packed;
250
251struct be_cmd_resp_pmac_add {
252 struct be_cmd_resp_hdr hdr;
253 u32 pmac_id;
254};
255
256/******************** PMac Del ***************************/
257struct be_cmd_req_pmac_del {
258 struct be_cmd_req_hdr hdr;
259 u32 if_id;
260 u32 pmac_id;
261};
262
263/******************** Create CQ ***************************/
264/* Pseudo amap definition in which each bit of the actual structure is defined
265 * as a byte: used to calculate offset/shift/mask of each field */
266struct amap_cq_context {
267 u8 cidx[11]; /* dword 0*/
268 u8 rsvd0; /* dword 0*/
269 u8 coalescwm[2]; /* dword 0*/
270 u8 nodelay; /* dword 0*/
271 u8 epidx[11]; /* dword 0*/
272 u8 rsvd1; /* dword 0*/
273 u8 count[2]; /* dword 0*/
274 u8 valid; /* dword 0*/
275 u8 solevent; /* dword 0*/
276 u8 eventable; /* dword 0*/
277 u8 pidx[11]; /* dword 1*/
278 u8 rsvd2; /* dword 1*/
279 u8 pd[10]; /* dword 1*/
280 u8 eqid[8]; /* dword 1*/
281 u8 stalled; /* dword 1*/
282 u8 armed; /* dword 1*/
283 u8 rsvd3[4]; /* dword 2*/
284 u8 func[8]; /* dword 2*/
285 u8 rsvd4[20]; /* dword 2*/
286 u8 rsvd5[32]; /* dword 3*/
287} __packed;
288
289struct be_cmd_req_cq_create {
290 struct be_cmd_req_hdr hdr;
291 u16 num_pages;
292 u16 rsvd0;
293 u8 context[sizeof(struct amap_cq_context) / 8];
294 struct phys_addr pages[8];
295} __packed;
296
297struct be_cmd_resp_cq_create {
298 struct be_cmd_resp_hdr hdr;
299 u16 cq_id;
300 u16 rsvd0;
301} __packed;
302
5fb379ee
SP		 303/******************** Create MCCQ ***************************/
304/* Pseudo amap definition in which each bit of the actual structure is defined
305 * as a byte: used to calculate offset/shift/mask of each field */
306struct amap_mcc_context {
307 u8 con_index[14];
308 u8 rsvd0[2];
309 u8 ring_size[4];
310 u8 fetch_wrb;
311 u8 fetch_r2t;
312 u8 cq_id[10];
313 u8 prod_index[14];
314 u8 fid[8];
315 u8 pdid[9];
316 u8 valid;
317 u8 rsvd1[32];
318 u8 rsvd2[32];
319} __packed;
320
321struct be_cmd_req_mcc_create {
322 struct be_cmd_req_hdr hdr;
323 u16 num_pages;
324 u16 rsvd0;
325 u8 context[sizeof(struct amap_mcc_context) / 8];
326 struct phys_addr pages[8];
327} __packed;
328
329struct be_cmd_resp_mcc_create {
330 struct be_cmd_resp_hdr hdr;
331 u16 id;
332 u16 rsvd0;
333} __packed;
334
6b7c5b94
SP		 335/******************** Create TxQ ***************************/
336#define BE_ETH_TX_RING_TYPE_STANDARD 2
337#define BE_ULP1_NUM 1
338
339/* Pseudo amap definition in which each bit of the actual structure is defined
340 * as a byte: used to calculate offset/shift/mask of each field */
341struct amap_tx_context {
342 u8 rsvd0[16]; /* dword 0 */
343 u8 tx_ring_size[4]; /* dword 0 */
344 u8 rsvd1[26]; /* dword 0 */
345 u8 pci_func_id[8]; /* dword 1 */
346 u8 rsvd2[9]; /* dword 1 */
347 u8 ctx_valid; /* dword 1 */
348 u8 cq_id_send[16]; /* dword 2 */
349 u8 rsvd3[16]; /* dword 2 */
350 u8 rsvd4[32]; /* dword 3 */
351 u8 rsvd5[32]; /* dword 4 */
352 u8 rsvd6[32]; /* dword 5 */
353 u8 rsvd7[32]; /* dword 6 */
354 u8 rsvd8[32]; /* dword 7 */
355 u8 rsvd9[32]; /* dword 8 */
356 u8 rsvd10[32]; /* dword 9 */
357 u8 rsvd11[32]; /* dword 10 */
358 u8 rsvd12[32]; /* dword 11 */
359 u8 rsvd13[32]; /* dword 12 */
360 u8 rsvd14[32]; /* dword 13 */
361 u8 rsvd15[32]; /* dword 14 */
362 u8 rsvd16[32]; /* dword 15 */
363} __packed;
364
365struct be_cmd_req_eth_tx_create {
366 struct be_cmd_req_hdr hdr;
367 u8 num_pages;
368 u8 ulp_num;
369 u8 type;
370 u8 bound_port;
371 u8 context[sizeof(struct amap_tx_context) / 8];
372 struct phys_addr pages[8];
373} __packed;
374
375struct be_cmd_resp_eth_tx_create {
376 struct be_cmd_resp_hdr hdr;
377 u16 cid;
378 u16 rsvd0;
379} __packed;
380
381/******************** Create RxQ ***************************/
382struct be_cmd_req_eth_rx_create {
383 struct be_cmd_req_hdr hdr;
384 u16 cq_id;
385 u8 frag_size;
386 u8 num_pages;
387 struct phys_addr pages[2];
388 u32 interface_id;
389 u16 max_frame_size;
390 u16 rsvd0;
391 u32 rss_queue;
392} __packed;
393
394struct be_cmd_resp_eth_rx_create {
395 struct be_cmd_resp_hdr hdr;
396 u16 id;
397 u8 cpu_id;
398 u8 rsvd0;
399} __packed;
400
401/******************** Q Destroy ***************************/
402/* Type of Queue to be destroyed */
403enum {
404 QTYPE_EQ = 1,
405 QTYPE_CQ,
406 QTYPE_TXQ,
5fb379ee
SP		 407 QTYPE_RXQ,
408 QTYPE_MCCQ
6b7c5b94
SP		 409};
410
411struct be_cmd_req_q_destroy {
412 struct be_cmd_req_hdr hdr;
413 u16 id;
414 u16 bypass_flush; /* valid only for rx q destroy */
415} __packed;
416
417/************ I/f Create (it's actually I/f Config Create)**********/
418
419/* Capability flags for the i/f */
420enum be_if_flags {
421 BE_IF_FLAGS_RSS = 0x4,
422 BE_IF_FLAGS_PROMISCUOUS = 0x8,
423 BE_IF_FLAGS_BROADCAST = 0x10,
424 BE_IF_FLAGS_UNTAGGED = 0x20,
425 BE_IF_FLAGS_ULP = 0x40,
426 BE_IF_FLAGS_VLAN_PROMISCUOUS = 0x80,
427 BE_IF_FLAGS_VLAN = 0x100,
428 BE_IF_FLAGS_MCAST_PROMISCUOUS = 0x200,
429 BE_IF_FLAGS_PASS_L2_ERRORS = 0x400,
430 BE_IF_FLAGS_PASS_L3L4_ERRORS = 0x800
431};
432
433/* An RX interface is an object with one or more MAC addresses and
434 * filtering capabilities. */
435struct be_cmd_req_if_create {
436 struct be_cmd_req_hdr hdr;
437 u32 version; /* ignore currntly */
438 u32 capability_flags;
439 u32 enable_flags;
440 u8 mac_addr[ETH_ALEN];
441 u8 rsvd0;
442 u8 pmac_invalid; /* if set, don't attach the mac addr to the i/f */
443 u32 vlan_tag; /* not used currently */
444} __packed;
445
446struct be_cmd_resp_if_create {
447 struct be_cmd_resp_hdr hdr;
448 u32 interface_id;
449 u32 pmac_id;
450};
451
452/****** I/f Destroy(it's actually I/f Config Destroy )**********/
453struct be_cmd_req_if_destroy {
454 struct be_cmd_req_hdr hdr;
455 u32 interface_id;
456};
457
458/*************** HW Stats Get **********************************/
459struct be_port_rxf_stats {
460 u32 rx_bytes_lsd; /* dword 0*/
461 u32 rx_bytes_msd; /* dword 1*/
462 u32 rx_total_frames; /* dword 2*/
463 u32 rx_unicast_frames; /* dword 3*/
464 u32 rx_multicast_frames; /* dword 4*/
465 u32 rx_broadcast_frames; /* dword 5*/
466 u32 rx_crc_errors; /* dword 6*/
467 u32 rx_alignment_symbol_errors; /* dword 7*/
468 u32 rx_pause_frames; /* dword 8*/
469 u32 rx_control_frames; /* dword 9*/
470 u32 rx_in_range_errors; /* dword 10*/
471 u32 rx_out_range_errors; /* dword 11*/
472 u32 rx_frame_too_long; /* dword 12*/
473 u32 rx_address_match_errors; /* dword 13*/
474 u32 rx_vlan_mismatch; /* dword 14*/
475 u32 rx_dropped_too_small; /* dword 15*/
476 u32 rx_dropped_too_short; /* dword 16*/
477 u32 rx_dropped_header_too_small; /* dword 17*/
478 u32 rx_dropped_tcp_length; /* dword 18*/
479 u32 rx_dropped_runt; /* dword 19*/
480 u32 rx_64_byte_packets; /* dword 20*/
481 u32 rx_65_127_byte_packets; /* dword 21*/
482 u32 rx_128_256_byte_packets; /* dword 22*/
483 u32 rx_256_511_byte_packets; /* dword 23*/
484 u32 rx_512_1023_byte_packets; /* dword 24*/
485 u32 rx_1024_1518_byte_packets; /* dword 25*/
486 u32 rx_1519_2047_byte_packets; /* dword 26*/
487 u32 rx_2048_4095_byte_packets; /* dword 27*/
488 u32 rx_4096_8191_byte_packets; /* dword 28*/
489 u32 rx_8192_9216_byte_packets; /* dword 29*/
490 u32 rx_ip_checksum_errs; /* dword 30*/
491 u32 rx_tcp_checksum_errs; /* dword 31*/
492 u32 rx_udp_checksum_errs; /* dword 32*/
493 u32 rx_non_rss_packets; /* dword 33*/
494 u32 rx_ipv4_packets; /* dword 34*/
495 u32 rx_ipv6_packets; /* dword 35*/
496 u32 rx_ipv4_bytes_lsd; /* dword 36*/
497 u32 rx_ipv4_bytes_msd; /* dword 37*/
498 u32 rx_ipv6_bytes_lsd; /* dword 38*/
499 u32 rx_ipv6_bytes_msd; /* dword 39*/
500 u32 rx_chute1_packets; /* dword 40*/
501 u32 rx_chute2_packets; /* dword 41*/
502 u32 rx_chute3_packets; /* dword 42*/
503 u32 rx_management_packets; /* dword 43*/
504 u32 rx_switched_unicast_packets; /* dword 44*/
505 u32 rx_switched_multicast_packets; /* dword 45*/
506 u32 rx_switched_broadcast_packets; /* dword 46*/
507 u32 tx_bytes_lsd; /* dword 47*/
508 u32 tx_bytes_msd; /* dword 48*/
509 u32 tx_unicastframes; /* dword 49*/
510 u32 tx_multicastframes; /* dword 50*/
511 u32 tx_broadcastframes; /* dword 51*/
512 u32 tx_pauseframes; /* dword 52*/
513 u32 tx_controlframes; /* dword 53*/
514 u32 tx_64_byte_packets; /* dword 54*/
515 u32 tx_65_127_byte_packets; /* dword 55*/
516 u32 tx_128_256_byte_packets; /* dword 56*/
517 u32 tx_256_511_byte_packets; /* dword 57*/
518 u32 tx_512_1023_byte_packets; /* dword 58*/
519 u32 tx_1024_1518_byte_packets; /* dword 59*/
520 u32 tx_1519_2047_byte_packets; /* dword 60*/
521 u32 tx_2048_4095_byte_packets; /* dword 61*/
522 u32 tx_4096_8191_byte_packets; /* dword 62*/
523 u32 tx_8192_9216_byte_packets; /* dword 63*/
524 u32 rx_fifo_overflow; /* dword 64*/
525 u32 rx_input_fifo_overflow; /* dword 65*/
526};
527
528struct be_rxf_stats {
529 struct be_port_rxf_stats port[2];
530 u32 rx_drops_no_pbuf; /* dword 132*/
531 u32 rx_drops_no_txpb; /* dword 133*/
532 u32 rx_drops_no_erx_descr; /* dword 134*/
533 u32 rx_drops_no_tpre_descr; /* dword 135*/
534 u32 management_rx_port_packets; /* dword 136*/
535 u32 management_rx_port_bytes; /* dword 137*/
536 u32 management_rx_port_pause_frames; /* dword 138*/
537 u32 management_rx_port_errors; /* dword 139*/
538 u32 management_tx_port_packets; /* dword 140*/
539 u32 management_tx_port_bytes; /* dword 141*/
540 u32 management_tx_port_pause; /* dword 142*/
541 u32 management_rx_port_rxfifo_overflow; /* dword 143*/
542 u32 rx_drops_too_many_frags; /* dword 144*/
543 u32 rx_drops_invalid_ring; /* dword 145*/
544 u32 forwarded_packets; /* dword 146*/
545 u32 rx_drops_mtu; /* dword 147*/
546 u32 rsvd0[15];
547};
548
549struct be_erx_stats {
550 u32 rx_drops_no_fragments[44]; /* dwordS 0 to 43*/
551 u32 debug_wdma_sent_hold; /* dword 44*/
552 u32 debug_wdma_pbfree_sent_hold; /* dword 45*/
553 u32 debug_wdma_zerobyte_pbfree_sent_hold; /* dword 46*/
554 u32 debug_pmem_pbuf_dealloc; /* dword 47*/
555};
556
557struct be_hw_stats {
558 struct be_rxf_stats rxf;
559 u32 rsvd[48];
560 struct be_erx_stats erx;
561};
562
563struct be_cmd_req_get_stats {
564 struct be_cmd_req_hdr hdr;
565 u8 rsvd[sizeof(struct be_hw_stats)];
566};
567
568struct be_cmd_resp_get_stats {
569 struct be_cmd_resp_hdr hdr;
570 struct be_hw_stats hw_stats;
571};
572
573struct be_cmd_req_vlan_config {
574 struct be_cmd_req_hdr hdr;
575 u8 interface_id;
576 u8 promiscuous;
577 u8 untagged;
578 u8 num_vlan;
579 u16 normal_vlan[64];
580} __packed;
581
582struct be_cmd_req_promiscuous_config {
583 struct be_cmd_req_hdr hdr;
584 u8 port0_promiscuous;
585 u8 port1_promiscuous;
586 u16 rsvd0;
587} __packed;
588
589struct macaddr {
590 u8 byte[ETH_ALEN];
591};
592
593struct be_cmd_req_mcast_mac_config {
594 struct be_cmd_req_hdr hdr;
595 u16 num_mac;
596 u8 promiscuous;
597 u8 interface_id;
598 struct macaddr mac[32];
599} __packed;
600
601static inline struct be_hw_stats *
602hw_stats_from_cmd(struct be_cmd_resp_get_stats *cmd)
603{
604 return &cmd->hw_stats;
605}
606
607/******************** Link Status Query *******************/
608struct be_cmd_req_link_status {
609 struct be_cmd_req_hdr hdr;
610 u32 rsvd;
611};
612
6b7c5b94
SP		 613enum {
614 PHY_LINK_DUPLEX_NONE = 0x0,
615 PHY_LINK_DUPLEX_HALF = 0x1,
616 PHY_LINK_DUPLEX_FULL = 0x2
617};
618
619enum {
620 PHY_LINK_SPEED_ZERO = 0x0, /* => No link */
621 PHY_LINK_SPEED_10MBPS = 0x1,
622 PHY_LINK_SPEED_100MBPS = 0x2,
623 PHY_LINK_SPEED_1GBPS = 0x3,
624 PHY_LINK_SPEED_10GBPS = 0x4
625};
626
627struct be_cmd_resp_link_status {
628 struct be_cmd_resp_hdr hdr;
629 u8 physical_port;
630 u8 mac_duplex;
631 u8 mac_speed;
632 u8 mac_fault;
633 u8 mgmt_mac_duplex;
634 u8 mgmt_mac_speed;
635 u16 rsvd0;
636} __packed;
637
638/******************** Get FW Version *******************/
6b7c5b94
SP		 639struct be_cmd_req_get_fw_version {
640 struct be_cmd_req_hdr hdr;
641 u8 rsvd0[FW_VER_LEN];
642 u8 rsvd1[FW_VER_LEN];
643} __packed;
644
645struct be_cmd_resp_get_fw_version {
646 struct be_cmd_resp_hdr hdr;
647 u8 firmware_version_string[FW_VER_LEN];
648 u8 fw_on_flash_version_string[FW_VER_LEN];
649} __packed;
650
651/******************** Set Flow Contrl *******************/
652struct be_cmd_req_set_flow_control {
653 struct be_cmd_req_hdr hdr;
654 u16 tx_flow_control;
655 u16 rx_flow_control;
656} __packed;
657
658/******************** Get Flow Contrl *******************/
659struct be_cmd_req_get_flow_control {
660 struct be_cmd_req_hdr hdr;
661 u32 rsvd;
662};
663
664struct be_cmd_resp_get_flow_control {
665 struct be_cmd_resp_hdr hdr;
666 u16 tx_flow_control;
667 u16 rx_flow_control;
668} __packed;
669
670/******************** Modify EQ Delay *******************/
671struct be_cmd_req_modify_eq_delay {
672 struct be_cmd_req_hdr hdr;
673 u32 num_eq;
674 struct {
675 u32 eq_id;
676 u32 phase;
677 u32 delay_multiplier;
678 } delay[8];
679} __packed;
680
681struct be_cmd_resp_modify_eq_delay {
682 struct be_cmd_resp_hdr hdr;
683 u32 rsvd0;
684} __packed;
685
686/******************** Get FW Config *******************/
687struct be_cmd_req_query_fw_cfg {
688 struct be_cmd_req_hdr hdr;
689 u32 rsvd[30];
690};
691
692struct be_cmd_resp_query_fw_cfg {
693 struct be_cmd_resp_hdr hdr;
694 u32 be_config_number;
695 u32 asic_revision;
696 u32 phys_port;
84517482 697 u32 function_cap;
6b7c5b94
SP		 698 u32 rsvd[26];
699};
700
84517482
AK		 701/****************** Firmware Flash ******************/
702struct flashrom_params {
703 u32 op_code;
704 u32 op_type;
705 u32 data_buf_size;
706 u32 offset;
707 u8 data_buf[4];
708};
709
710struct be_cmd_write_flashrom {
711 struct be_cmd_req_hdr hdr;
712 struct flashrom_params params;
713};
714
8788fdc2
SP		 715extern int be_pci_fnum_get(struct be_adapter *adapter);
716extern int be_cmd_POST(struct be_adapter *adapter);
717extern int be_cmd_mac_addr_query(struct be_adapter *adapter, u8 *mac_addr,
6b7c5b94 718 u8 type, bool permanent, u32 if_handle);
8788fdc2 719extern int be_cmd_pmac_add(struct be_adapter *adapter, u8 *mac_addr,
6b7c5b94 720 u32 if_id, u32 *pmac_id);
8788fdc2
SP		 721extern int be_cmd_pmac_del(struct be_adapter *adapter, u32 if_id, u32 pmac_id);
722extern int be_cmd_if_create(struct be_adapter *adapter, u32 if_flags, u8 *mac,
6b7c5b94 723 bool pmac_invalid, u32 *if_handle, u32 *pmac_id);
8788fdc2
SP		 724extern int be_cmd_if_destroy(struct be_adapter *adapter, u32 if_handle);
725extern int be_cmd_eq_create(struct be_adapter *adapter,
6b7c5b94 726 struct be_queue_info *eq, int eq_delay);
8788fdc2 727extern int be_cmd_cq_create(struct be_adapter *adapter,
6b7c5b94
SP		 728 struct be_queue_info *cq, struct be_queue_info *eq,
729 bool sol_evts, bool no_delay,
730 int num_cqe_dma_coalesce);
8788fdc2 731extern int be_cmd_mccq_create(struct be_adapter *adapter,
5fb379ee
SP		 732 struct be_queue_info *mccq,
733 struct be_queue_info *cq);
8788fdc2 734extern int be_cmd_txq_create(struct be_adapter *adapter,
6b7c5b94
SP		 735 struct be_queue_info *txq,
736 struct be_queue_info *cq);
8788fdc2 737extern int be_cmd_rxq_create(struct be_adapter *adapter,
6b7c5b94
SP		 738 struct be_queue_info *rxq, u16 cq_id,
739 u16 frag_size, u16 max_frame_size, u32 if_id,
740 u32 rss);
8788fdc2 741extern int be_cmd_q_destroy(struct be_adapter *adapter, struct be_queue_info *q,
6b7c5b94 742 int type);
8788fdc2 743extern int be_cmd_link_status_query(struct be_adapter *adapter,
a8f447bd 744 bool *link_up);
8788fdc2
SP		 745extern int be_cmd_reset(struct be_adapter *adapter);
746extern int be_cmd_get_stats(struct be_adapter *adapter,
6b7c5b94 747 struct be_dma_mem *nonemb_cmd);
8788fdc2 748extern int be_cmd_get_fw_ver(struct be_adapter *adapter, char *fw_ver);
6b7c5b94 749
8788fdc2
SP		 750extern int be_cmd_modify_eqd(struct be_adapter *adapter, u32 eq_id, u32 eqd);
751extern int be_cmd_vlan_config(struct be_adapter *adapter, u32 if_id,
6b7c5b94
SP		 752 u16 *vtag_array, u32 num, bool untagged,
753 bool promiscuous);
8788fdc2 754extern int be_cmd_promiscuous_config(struct be_adapter *adapter,
6b7c5b94 755 u8 port_num, bool en);
8788fdc2 756extern int be_cmd_multicast_set(struct be_adapter *adapter, u32 if_id,
24307eef 757 struct dev_mc_list *mc_list, u32 mc_count);
8788fdc2 758extern int be_cmd_set_flow_control(struct be_adapter *adapter,
6b7c5b94 759 u32 tx_fc, u32 rx_fc);
8788fdc2 760extern int be_cmd_get_flow_control(struct be_adapter *adapter,
6b7c5b94 761 u32 *tx_fc, u32 *rx_fc);
8788fdc2 762extern int be_cmd_query_fw_cfg(struct be_adapter *adapter, u32 *port_num);
14074eab 763extern int be_cmd_reset_function(struct be_adapter *adapter);
8788fdc2 764extern void be_process_mcc(struct be_adapter *adapter);
84517482
AK		 765extern int be_cmd_write_flashrom(struct be_adapter *adapter,
766 struct be_dma_mem *cmd, u32 flash_oper,
767 u32 flash_opcode, u32 buf_size);
Linux kernel - Deliverables
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