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be2net: variable name changes
[deliverable/linux.git] / drivers / net / benet / be_cmds.h
CommitLineData
6b7c5b94 1/*
294aedcf 2 * Copyright (C) 2005 - 2010 ServerEngines
6b7c5b94
SP		 3 * All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License version 2
7 * as published by the Free Software Foundation. The full GNU General
8 * Public License is included in this distribution in the file called COPYING.
9 *
10 * Contact Information:
11 * linux-drivers@serverengines.com
12 *
13 * ServerEngines
14 * 209 N. Fair Oaks Ave
15 * Sunnyvale, CA 94085
16 */
17
18/*
19 * The driver sends configuration and managements command requests to the
20 * firmware in the BE. These requests are communicated to the processor
21 * using Work Request Blocks (WRBs) submitted to the MCC-WRB ring or via one
22 * WRB inside a MAILBOX.
23 * The commands are serviced by the ARM processor in the BladeEngine's MPU.
24 */
25
26struct be_sge {
27 u32 pa_lo;
28 u32 pa_hi;
29 u32 len;
30};
31
32#define MCC_WRB_EMBEDDED_MASK 1 /* bit 0 of dword 0*/
33#define MCC_WRB_SGE_CNT_SHIFT 3 /* bits 3 - 7 of dword 0 */
34#define MCC_WRB_SGE_CNT_MASK 0x1F /* bits 3 - 7 of dword 0 */
35struct be_mcc_wrb {
36 u32 embedded; /* dword 0 */
37 u32 payload_length; /* dword 1 */
38 u32 tag0; /* dword 2 */
39 u32 tag1; /* dword 3 */
40 u32 rsvd; /* dword 4 */
41 union {
42 u8 embedded_payload[236]; /* used by embedded cmds */
43 struct be_sge sgl[19]; /* used by non-embedded cmds */
44 } payload;
45};
46
47#define CQE_FLAGS_VALID_MASK (1 << 31)
48#define CQE_FLAGS_ASYNC_MASK (1 << 30)
49#define CQE_FLAGS_COMPLETED_MASK (1 << 28)
50#define CQE_FLAGS_CONSUMED_MASK (1 << 27)
51
52/* Completion Status */
53enum {
54 MCC_STATUS_SUCCESS = 0x0,
55/* The client does not have sufficient privileges to execute the command */
56 MCC_STATUS_INSUFFICIENT_PRIVILEGES = 0x1,
57/* A parameter in the command was invalid. */
58 MCC_STATUS_INVALID_PARAMETER = 0x2,
59/* There are insufficient chip resources to execute the command */
60 MCC_STATUS_INSUFFICIENT_RESOURCES = 0x3,
61/* The command is completing because the queue was getting flushed */
62 MCC_STATUS_QUEUE_FLUSHING = 0x4,
63/* The command is completing with a DMA error */
b31c50a7 64 MCC_STATUS_DMA_FAILED = 0x5,
49643848 65 MCC_STATUS_NOT_SUPPORTED = 66
6b7c5b94
SP		 66};
67
68#define CQE_STATUS_COMPL_MASK 0xFFFF
69#define CQE_STATUS_COMPL_SHIFT 0 /* bits 0 - 15 */
70#define CQE_STATUS_EXTD_MASK 0xFFFF
f5209b44 71#define CQE_STATUS_EXTD_SHIFT 16 /* bits 16 - 31 */
6b7c5b94 72
efd2e40a 73struct be_mcc_compl {
6b7c5b94
SP		 74 u32 status; /* dword 0 */
75 u32 tag0; /* dword 1 */
76 u32 tag1; /* dword 2 */
77 u32 flags; /* dword 3 */
78};
79
a8f447bd
SP		 80/* When the async bit of mcc_compl is set, the last 4 bytes of
81 * mcc_compl is interpreted as follows:
82 */
83#define ASYNC_TRAILER_EVENT_CODE_SHIFT 8 /* bits 8 - 15 */
84#define ASYNC_TRAILER_EVENT_CODE_MASK 0xFF
85#define ASYNC_EVENT_CODE_LINK_STATE 0x1
86struct be_async_event_trailer {
87 u32 code;
88};
89
90enum {
91 ASYNC_EVENT_LINK_DOWN = 0x0,
92 ASYNC_EVENT_LINK_UP = 0x1
93};
94
95/* When the event code of an async trailer is link-state, the mcc_compl
96 * must be interpreted as follows
97 */
98struct be_async_event_link_state {
99 u8 physical_port;
100 u8 port_link_status;
101 u8 port_duplex;
102 u8 port_speed;
103 u8 port_fault;
104 u8 rsvd0[7];
105 struct be_async_event_trailer trailer;
106} __packed;
107
6b7c5b94
SP		 108struct be_mcc_mailbox {
109 struct be_mcc_wrb wrb;
efd2e40a 110 struct be_mcc_compl compl;
6b7c5b94
SP		 111};
112
113#define CMD_SUBSYSTEM_COMMON 0x1
114#define CMD_SUBSYSTEM_ETH 0x3
ff33a6e2 115#define CMD_SUBSYSTEM_LOWLEVEL 0xb
6b7c5b94
SP		 116
117#define OPCODE_COMMON_NTWK_MAC_QUERY 1
118#define OPCODE_COMMON_NTWK_MAC_SET 2
119#define OPCODE_COMMON_NTWK_MULTICAST_SET 3
120#define OPCODE_COMMON_NTWK_VLAN_CONFIG 4
121#define OPCODE_COMMON_NTWK_LINK_STATUS_QUERY 5
fa9a6fed 122#define OPCODE_COMMON_READ_FLASHROM 6
84517482 123#define OPCODE_COMMON_WRITE_FLASHROM 7
6b7c5b94
SP		 124#define OPCODE_COMMON_CQ_CREATE 12
125#define OPCODE_COMMON_EQ_CREATE 13
126#define OPCODE_COMMON_MCC_CREATE 21
e1d18735 127#define OPCODE_COMMON_SET_QOS 28
368c0ca2 128#define OPCODE_COMMON_SEEPROM_READ 30
6b7c5b94
SP		 129#define OPCODE_COMMON_NTWK_RX_FILTER 34
130#define OPCODE_COMMON_GET_FW_VERSION 35
131#define OPCODE_COMMON_SET_FLOW_CONTROL 36
132#define OPCODE_COMMON_GET_FLOW_CONTROL 37
133#define OPCODE_COMMON_SET_FRAME_SIZE 39
134#define OPCODE_COMMON_MODIFY_EQ_DELAY 41
135#define OPCODE_COMMON_FIRMWARE_CONFIG 42
136#define OPCODE_COMMON_NTWK_INTERFACE_CREATE 50
137#define OPCODE_COMMON_NTWK_INTERFACE_DESTROY 51
5fb379ee 138#define OPCODE_COMMON_MCC_DESTROY 53
6b7c5b94
SP		 139#define OPCODE_COMMON_CQ_DESTROY 54
140#define OPCODE_COMMON_EQ_DESTROY 55
141#define OPCODE_COMMON_QUERY_FIRMWARE_CONFIG 58
142#define OPCODE_COMMON_NTWK_PMAC_ADD 59
143#define OPCODE_COMMON_NTWK_PMAC_DEL 60
14074eab 144#define OPCODE_COMMON_FUNCTION_RESET 61
fad9ab2c
SB		 145#define OPCODE_COMMON_ENABLE_DISABLE_BEACON 69
146#define OPCODE_COMMON_GET_BEACON_STATE 70
0388f251 147#define OPCODE_COMMON_READ_TRANSRECV_DATA 73
ee3cb629 148#define OPCODE_COMMON_GET_PHY_DETAILS 102
6b7c5b94
SP		 149
150#define OPCODE_ETH_ACPI_CONFIG 2
151#define OPCODE_ETH_PROMISCUOUS 3
152#define OPCODE_ETH_GET_STATISTICS 4
153#define OPCODE_ETH_TX_CREATE 7
154#define OPCODE_ETH_RX_CREATE 8
155#define OPCODE_ETH_TX_DESTROY 9
156#define OPCODE_ETH_RX_DESTROY 10
71d8d1b5 157#define OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG 12
6b7c5b94 158
ff33a6e2
S		 159#define OPCODE_LOWLEVEL_HOST_DDR_DMA 17
160#define OPCODE_LOWLEVEL_LOOPBACK_TEST 18
fced9999 161#define OPCODE_LOWLEVEL_SET_LOOPBACK_MODE 19
ff33a6e2 162
6b7c5b94
SP		 163struct be_cmd_req_hdr {
164 u8 opcode; /* dword 0 */
165 u8 subsystem; /* dword 0 */
166 u8 port_number; /* dword 0 */
167 u8 domain; /* dword 0 */
168 u32 timeout; /* dword 1 */
169 u32 request_length; /* dword 2 */
7b139c83
AK		 170 u8 version; /* dword 3 */
171 u8 rsvd[3]; /* dword 3 */
6b7c5b94
SP		 172};
173
174#define RESP_HDR_INFO_OPCODE_SHIFT 0 /* bits 0 - 7 */
175#define RESP_HDR_INFO_SUBSYS_SHIFT 8 /* bits 8 - 15 */
176struct be_cmd_resp_hdr {
177 u32 info; /* dword 0 */
178 u32 status; /* dword 1 */
179 u32 response_length; /* dword 2 */
180 u32 actual_resp_len; /* dword 3 */
181};
182
183struct phys_addr {
184 u32 lo;
185 u32 hi;
186};
187
188/**************************
189 * BE Command definitions *
190 **************************/
191
192/* Pseudo amap definition in which each bit of the actual structure is defined
193 * as a byte: used to calculate offset/shift/mask of each field */
194struct amap_eq_context {
195 u8 cidx[13]; /* dword 0*/
196 u8 rsvd0[3]; /* dword 0*/
197 u8 epidx[13]; /* dword 0*/
198 u8 valid; /* dword 0*/
199 u8 rsvd1; /* dword 0*/
200 u8 size; /* dword 0*/
201 u8 pidx[13]; /* dword 1*/
202 u8 rsvd2[3]; /* dword 1*/
203 u8 pd[10]; /* dword 1*/
204 u8 count[3]; /* dword 1*/
205 u8 solevent; /* dword 1*/
206 u8 stalled; /* dword 1*/
207 u8 armed; /* dword 1*/
208 u8 rsvd3[4]; /* dword 2*/
209 u8 func[8]; /* dword 2*/
210 u8 rsvd4; /* dword 2*/
211 u8 delaymult[10]; /* dword 2*/
212 u8 rsvd5[2]; /* dword 2*/
213 u8 phase[2]; /* dword 2*/
214 u8 nodelay; /* dword 2*/
215 u8 rsvd6[4]; /* dword 2*/
216 u8 rsvd7[32]; /* dword 3*/
217} __packed;
218
219struct be_cmd_req_eq_create {
220 struct be_cmd_req_hdr hdr;
221 u16 num_pages; /* sword */
222 u16 rsvd0; /* sword */
223 u8 context[sizeof(struct amap_eq_context) / 8];
224 struct phys_addr pages[8];
225} __packed;
226
227struct be_cmd_resp_eq_create {
228 struct be_cmd_resp_hdr resp_hdr;
229 u16 eq_id; /* sword */
230 u16 rsvd0; /* sword */
231} __packed;
232
233/******************** Mac query ***************************/
234enum {
235 MAC_ADDRESS_TYPE_STORAGE = 0x0,
236 MAC_ADDRESS_TYPE_NETWORK = 0x1,
237 MAC_ADDRESS_TYPE_PD = 0x2,
238 MAC_ADDRESS_TYPE_MANAGEMENT = 0x3
239};
240
241struct mac_addr {
242 u16 size_of_struct;
243 u8 addr[ETH_ALEN];
244} __packed;
245
246struct be_cmd_req_mac_query {
247 struct be_cmd_req_hdr hdr;
248 u8 type;
249 u8 permanent;
250 u16 if_id;
251} __packed;
252
253struct be_cmd_resp_mac_query {
254 struct be_cmd_resp_hdr hdr;
255 struct mac_addr mac;
256};
257
258/******************** PMac Add ***************************/
259struct be_cmd_req_pmac_add {
260 struct be_cmd_req_hdr hdr;
261 u32 if_id;
262 u8 mac_address[ETH_ALEN];
263 u8 rsvd0[2];
264} __packed;
265
266struct be_cmd_resp_pmac_add {
267 struct be_cmd_resp_hdr hdr;
268 u32 pmac_id;
269};
270
271/******************** PMac Del ***************************/
272struct be_cmd_req_pmac_del {
273 struct be_cmd_req_hdr hdr;
274 u32 if_id;
275 u32 pmac_id;
276};
277
278/******************** Create CQ ***************************/
279/* Pseudo amap definition in which each bit of the actual structure is defined
280 * as a byte: used to calculate offset/shift/mask of each field */
281struct amap_cq_context {
282 u8 cidx[11]; /* dword 0*/
283 u8 rsvd0; /* dword 0*/
284 u8 coalescwm[2]; /* dword 0*/
285 u8 nodelay; /* dword 0*/
286 u8 epidx[11]; /* dword 0*/
287 u8 rsvd1; /* dword 0*/
288 u8 count[2]; /* dword 0*/
289 u8 valid; /* dword 0*/
290 u8 solevent; /* dword 0*/
291 u8 eventable; /* dword 0*/
292 u8 pidx[11]; /* dword 1*/
293 u8 rsvd2; /* dword 1*/
294 u8 pd[10]; /* dword 1*/
295 u8 eqid[8]; /* dword 1*/
296 u8 stalled; /* dword 1*/
297 u8 armed; /* dword 1*/
298 u8 rsvd3[4]; /* dword 2*/
299 u8 func[8]; /* dword 2*/
300 u8 rsvd4[20]; /* dword 2*/
301 u8 rsvd5[32]; /* dword 3*/
302} __packed;
303
304struct be_cmd_req_cq_create {
305 struct be_cmd_req_hdr hdr;
306 u16 num_pages;
307 u16 rsvd0;
308 u8 context[sizeof(struct amap_cq_context) / 8];
309 struct phys_addr pages[8];
310} __packed;
311
312struct be_cmd_resp_cq_create {
313 struct be_cmd_resp_hdr hdr;
314 u16 cq_id;
315 u16 rsvd0;
316} __packed;
317
5fb379ee
SP		 318/******************** Create MCCQ ***************************/
319/* Pseudo amap definition in which each bit of the actual structure is defined
320 * as a byte: used to calculate offset/shift/mask of each field */
321struct amap_mcc_context {
322 u8 con_index[14];
323 u8 rsvd0[2];
324 u8 ring_size[4];
325 u8 fetch_wrb;
326 u8 fetch_r2t;
327 u8 cq_id[10];
328 u8 prod_index[14];
329 u8 fid[8];
330 u8 pdid[9];
331 u8 valid;
332 u8 rsvd1[32];
333 u8 rsvd2[32];
334} __packed;
335
336struct be_cmd_req_mcc_create {
337 struct be_cmd_req_hdr hdr;
338 u16 num_pages;
339 u16 rsvd0;
340 u8 context[sizeof(struct amap_mcc_context) / 8];
341 struct phys_addr pages[8];
342} __packed;
343
344struct be_cmd_resp_mcc_create {
345 struct be_cmd_resp_hdr hdr;
346 u16 id;
347 u16 rsvd0;
348} __packed;
349
6b7c5b94
SP		 350/******************** Create TxQ ***************************/
351#define BE_ETH_TX_RING_TYPE_STANDARD 2
352#define BE_ULP1_NUM 1
353
354/* Pseudo amap definition in which each bit of the actual structure is defined
355 * as a byte: used to calculate offset/shift/mask of each field */
356struct amap_tx_context {
357 u8 rsvd0[16]; /* dword 0 */
358 u8 tx_ring_size[4]; /* dword 0 */
359 u8 rsvd1[26]; /* dword 0 */
360 u8 pci_func_id[8]; /* dword 1 */
361 u8 rsvd2[9]; /* dword 1 */
362 u8 ctx_valid; /* dword 1 */
363 u8 cq_id_send[16]; /* dword 2 */
364 u8 rsvd3[16]; /* dword 2 */
365 u8 rsvd4[32]; /* dword 3 */
366 u8 rsvd5[32]; /* dword 4 */
367 u8 rsvd6[32]; /* dword 5 */
368 u8 rsvd7[32]; /* dword 6 */
369 u8 rsvd8[32]; /* dword 7 */
370 u8 rsvd9[32]; /* dword 8 */
371 u8 rsvd10[32]; /* dword 9 */
372 u8 rsvd11[32]; /* dword 10 */
373 u8 rsvd12[32]; /* dword 11 */
374 u8 rsvd13[32]; /* dword 12 */
375 u8 rsvd14[32]; /* dword 13 */
376 u8 rsvd15[32]; /* dword 14 */
377 u8 rsvd16[32]; /* dword 15 */
378} __packed;
379
380struct be_cmd_req_eth_tx_create {
381 struct be_cmd_req_hdr hdr;
382 u8 num_pages;
383 u8 ulp_num;
384 u8 type;
385 u8 bound_port;
386 u8 context[sizeof(struct amap_tx_context) / 8];
387 struct phys_addr pages[8];
388} __packed;
389
390struct be_cmd_resp_eth_tx_create {
391 struct be_cmd_resp_hdr hdr;
392 u16 cid;
393 u16 rsvd0;
394} __packed;
395
396/******************** Create RxQ ***************************/
397struct be_cmd_req_eth_rx_create {
398 struct be_cmd_req_hdr hdr;
399 u16 cq_id;
400 u8 frag_size;
401 u8 num_pages;
402 struct phys_addr pages[2];
403 u32 interface_id;
404 u16 max_frame_size;
405 u16 rsvd0;
406 u32 rss_queue;
407} __packed;
408
409struct be_cmd_resp_eth_rx_create {
410 struct be_cmd_resp_hdr hdr;
411 u16 id;
412 u8 cpu_id;
413 u8 rsvd0;
414} __packed;
415
416/******************** Q Destroy ***************************/
417/* Type of Queue to be destroyed */
418enum {
419 QTYPE_EQ = 1,
420 QTYPE_CQ,
421 QTYPE_TXQ,
5fb379ee
SP		 422 QTYPE_RXQ,
423 QTYPE_MCCQ
6b7c5b94
SP		 424};
425
426struct be_cmd_req_q_destroy {
427 struct be_cmd_req_hdr hdr;
428 u16 id;
429 u16 bypass_flush; /* valid only for rx q destroy */
430} __packed;
431
432/************ I/f Create (it's actually I/f Config Create)**********/
433
434/* Capability flags for the i/f */
435enum be_if_flags {
436 BE_IF_FLAGS_RSS = 0x4,
437 BE_IF_FLAGS_PROMISCUOUS = 0x8,
438 BE_IF_FLAGS_BROADCAST = 0x10,
439 BE_IF_FLAGS_UNTAGGED = 0x20,
440 BE_IF_FLAGS_ULP = 0x40,
441 BE_IF_FLAGS_VLAN_PROMISCUOUS = 0x80,
442 BE_IF_FLAGS_VLAN = 0x100,
443 BE_IF_FLAGS_MCAST_PROMISCUOUS = 0x200,
444 BE_IF_FLAGS_PASS_L2_ERRORS = 0x400,
445 BE_IF_FLAGS_PASS_L3L4_ERRORS = 0x800
446};
447
448/* An RX interface is an object with one or more MAC addresses and
449 * filtering capabilities. */
450struct be_cmd_req_if_create {
451 struct be_cmd_req_hdr hdr;
af901ca1 452 u32 version; /* ignore currently */
6b7c5b94
SP		 453 u32 capability_flags;
454 u32 enable_flags;
455 u8 mac_addr[ETH_ALEN];
456 u8 rsvd0;
457 u8 pmac_invalid; /* if set, don't attach the mac addr to the i/f */
458 u32 vlan_tag; /* not used currently */
459} __packed;
460
461struct be_cmd_resp_if_create {
462 struct be_cmd_resp_hdr hdr;
463 u32 interface_id;
464 u32 pmac_id;
465};
466
467/****** I/f Destroy(it's actually I/f Config Destroy )**********/
468struct be_cmd_req_if_destroy {
469 struct be_cmd_req_hdr hdr;
470 u32 interface_id;
471};
472
473/*************** HW Stats Get **********************************/
474struct be_port_rxf_stats {
475 u32 rx_bytes_lsd; /* dword 0*/
476 u32 rx_bytes_msd; /* dword 1*/
477 u32 rx_total_frames; /* dword 2*/
478 u32 rx_unicast_frames; /* dword 3*/
479 u32 rx_multicast_frames; /* dword 4*/
480 u32 rx_broadcast_frames; /* dword 5*/
481 u32 rx_crc_errors; /* dword 6*/
482 u32 rx_alignment_symbol_errors; /* dword 7*/
483 u32 rx_pause_frames; /* dword 8*/
484 u32 rx_control_frames; /* dword 9*/
485 u32 rx_in_range_errors; /* dword 10*/
486 u32 rx_out_range_errors; /* dword 11*/
487 u32 rx_frame_too_long; /* dword 12*/
488 u32 rx_address_match_errors; /* dword 13*/
489 u32 rx_vlan_mismatch; /* dword 14*/
490 u32 rx_dropped_too_small; /* dword 15*/
491 u32 rx_dropped_too_short; /* dword 16*/
492 u32 rx_dropped_header_too_small; /* dword 17*/
493 u32 rx_dropped_tcp_length; /* dword 18*/
494 u32 rx_dropped_runt; /* dword 19*/
495 u32 rx_64_byte_packets; /* dword 20*/
496 u32 rx_65_127_byte_packets; /* dword 21*/
497 u32 rx_128_256_byte_packets; /* dword 22*/
498 u32 rx_256_511_byte_packets; /* dword 23*/
499 u32 rx_512_1023_byte_packets; /* dword 24*/
500 u32 rx_1024_1518_byte_packets; /* dword 25*/
501 u32 rx_1519_2047_byte_packets; /* dword 26*/
502 u32 rx_2048_4095_byte_packets; /* dword 27*/
503 u32 rx_4096_8191_byte_packets; /* dword 28*/
504 u32 rx_8192_9216_byte_packets; /* dword 29*/
505 u32 rx_ip_checksum_errs; /* dword 30*/
506 u32 rx_tcp_checksum_errs; /* dword 31*/
507 u32 rx_udp_checksum_errs; /* dword 32*/
508 u32 rx_non_rss_packets; /* dword 33*/
509 u32 rx_ipv4_packets; /* dword 34*/
510 u32 rx_ipv6_packets; /* dword 35*/
511 u32 rx_ipv4_bytes_lsd; /* dword 36*/
512 u32 rx_ipv4_bytes_msd; /* dword 37*/
513 u32 rx_ipv6_bytes_lsd; /* dword 38*/
514 u32 rx_ipv6_bytes_msd; /* dword 39*/
515 u32 rx_chute1_packets; /* dword 40*/
516 u32 rx_chute2_packets; /* dword 41*/
517 u32 rx_chute3_packets; /* dword 42*/
518 u32 rx_management_packets; /* dword 43*/
519 u32 rx_switched_unicast_packets; /* dword 44*/
520 u32 rx_switched_multicast_packets; /* dword 45*/
521 u32 rx_switched_broadcast_packets; /* dword 46*/
522 u32 tx_bytes_lsd; /* dword 47*/
523 u32 tx_bytes_msd; /* dword 48*/
524 u32 tx_unicastframes; /* dword 49*/
525 u32 tx_multicastframes; /* dword 50*/
526 u32 tx_broadcastframes; /* dword 51*/
527 u32 tx_pauseframes; /* dword 52*/
528 u32 tx_controlframes; /* dword 53*/
529 u32 tx_64_byte_packets; /* dword 54*/
530 u32 tx_65_127_byte_packets; /* dword 55*/
531 u32 tx_128_256_byte_packets; /* dword 56*/
532 u32 tx_256_511_byte_packets; /* dword 57*/
533 u32 tx_512_1023_byte_packets; /* dword 58*/
534 u32 tx_1024_1518_byte_packets; /* dword 59*/
535 u32 tx_1519_2047_byte_packets; /* dword 60*/
536 u32 tx_2048_4095_byte_packets; /* dword 61*/
537 u32 tx_4096_8191_byte_packets; /* dword 62*/
538 u32 tx_8192_9216_byte_packets; /* dword 63*/
539 u32 rx_fifo_overflow; /* dword 64*/
540 u32 rx_input_fifo_overflow; /* dword 65*/
541};
542
543struct be_rxf_stats {
544 struct be_port_rxf_stats port[2];
545 u32 rx_drops_no_pbuf; /* dword 132*/
546 u32 rx_drops_no_txpb; /* dword 133*/
547 u32 rx_drops_no_erx_descr; /* dword 134*/
548 u32 rx_drops_no_tpre_descr; /* dword 135*/
549 u32 management_rx_port_packets; /* dword 136*/
550 u32 management_rx_port_bytes; /* dword 137*/
551 u32 management_rx_port_pause_frames; /* dword 138*/
552 u32 management_rx_port_errors; /* dword 139*/
553 u32 management_tx_port_packets; /* dword 140*/
554 u32 management_tx_port_bytes; /* dword 141*/
555 u32 management_tx_port_pause; /* dword 142*/
556 u32 management_rx_port_rxfifo_overflow; /* dword 143*/
557 u32 rx_drops_too_many_frags; /* dword 144*/
558 u32 rx_drops_invalid_ring; /* dword 145*/
559 u32 forwarded_packets; /* dword 146*/
560 u32 rx_drops_mtu; /* dword 147*/
561 u32 rsvd0[15];
562};
563
564struct be_erx_stats {
565 u32 rx_drops_no_fragments[44]; /* dwordS 0 to 43*/
566 u32 debug_wdma_sent_hold; /* dword 44*/
567 u32 debug_wdma_pbfree_sent_hold; /* dword 45*/
568 u32 debug_wdma_zerobyte_pbfree_sent_hold; /* dword 46*/
569 u32 debug_pmem_pbuf_dealloc; /* dword 47*/
570};
571
572struct be_hw_stats {
573 struct be_rxf_stats rxf;
574 u32 rsvd[48];
575 struct be_erx_stats erx;
576};
577
578struct be_cmd_req_get_stats {
579 struct be_cmd_req_hdr hdr;
580 u8 rsvd[sizeof(struct be_hw_stats)];
581};
582
583struct be_cmd_resp_get_stats {
584 struct be_cmd_resp_hdr hdr;
585 struct be_hw_stats hw_stats;
586};
587
588struct be_cmd_req_vlan_config {
589 struct be_cmd_req_hdr hdr;
590 u8 interface_id;
591 u8 promiscuous;
592 u8 untagged;
593 u8 num_vlan;
594 u16 normal_vlan[64];
595} __packed;
596
597struct be_cmd_req_promiscuous_config {
598 struct be_cmd_req_hdr hdr;
599 u8 port0_promiscuous;
600 u8 port1_promiscuous;
601 u16 rsvd0;
602} __packed;
603
e7b909a6
SP		 604/******************** Multicast MAC Config *******************/
605#define BE_MAX_MC 64 /* set mcast promisc if > 64 */
6b7c5b94
SP		 606struct macaddr {
607 u8 byte[ETH_ALEN];
608};
609
610struct be_cmd_req_mcast_mac_config {
611 struct be_cmd_req_hdr hdr;
612 u16 num_mac;
613 u8 promiscuous;
614 u8 interface_id;
e7b909a6 615 struct macaddr mac[BE_MAX_MC];
6b7c5b94
SP		 616} __packed;
617
618static inline struct be_hw_stats *
619hw_stats_from_cmd(struct be_cmd_resp_get_stats *cmd)
620{
621 return &cmd->hw_stats;
622}
623
624/******************** Link Status Query *******************/
625struct be_cmd_req_link_status {
626 struct be_cmd_req_hdr hdr;
627 u32 rsvd;
628};
629
6b7c5b94
SP		 630enum {
631 PHY_LINK_DUPLEX_NONE = 0x0,
632 PHY_LINK_DUPLEX_HALF = 0x1,
633 PHY_LINK_DUPLEX_FULL = 0x2
634};
635
636enum {
637 PHY_LINK_SPEED_ZERO = 0x0, /* => No link */
638 PHY_LINK_SPEED_10MBPS = 0x1,
639 PHY_LINK_SPEED_100MBPS = 0x2,
640 PHY_LINK_SPEED_1GBPS = 0x3,
641 PHY_LINK_SPEED_10GBPS = 0x4
642};
643
644struct be_cmd_resp_link_status {
645 struct be_cmd_resp_hdr hdr;
646 u8 physical_port;
647 u8 mac_duplex;
648 u8 mac_speed;
649 u8 mac_fault;
650 u8 mgmt_mac_duplex;
651 u8 mgmt_mac_speed;
0388f251
SB		 652 u16 link_speed;
653 u32 rsvd0;
6b7c5b94
SP		 654} __packed;
655
0388f251
SB		 656/******************** Port Identification ***************************/
657/* Identifies the type of port attached to NIC */
658struct be_cmd_req_port_type {
659 struct be_cmd_req_hdr hdr;
660 u32 page_num;
661 u32 port;
662};
663
664enum {
665 TR_PAGE_A0 = 0xa0,
666 TR_PAGE_A2 = 0xa2
667};
668
669struct be_cmd_resp_port_type {
670 struct be_cmd_resp_hdr hdr;
671 u32 page_num;
672 u32 port;
673 struct data {
674 u8 identifier;
675 u8 identifier_ext;
676 u8 connector;
677 u8 transceiver[8];
678 u8 rsvd0[3];
679 u8 length_km;
680 u8 length_hm;
681 u8 length_om1;
682 u8 length_om2;
683 u8 length_cu;
684 u8 length_cu_m;
685 u8 vendor_name[16];
686 u8 rsvd;
687 u8 vendor_oui[3];
688 u8 vendor_pn[16];
689 u8 vendor_rev[4];
690 } data;
691};
692
6b7c5b94 693/******************** Get FW Version *******************/
6b7c5b94
SP		 694struct be_cmd_req_get_fw_version {
695 struct be_cmd_req_hdr hdr;
696 u8 rsvd0[FW_VER_LEN];
697 u8 rsvd1[FW_VER_LEN];
698} __packed;
699
700struct be_cmd_resp_get_fw_version {
701 struct be_cmd_resp_hdr hdr;
702 u8 firmware_version_string[FW_VER_LEN];
703 u8 fw_on_flash_version_string[FW_VER_LEN];
704} __packed;
705
706/******************** Set Flow Contrl *******************/
707struct be_cmd_req_set_flow_control {
708 struct be_cmd_req_hdr hdr;
709 u16 tx_flow_control;
710 u16 rx_flow_control;
711} __packed;
712
713/******************** Get Flow Contrl *******************/
714struct be_cmd_req_get_flow_control {
715 struct be_cmd_req_hdr hdr;
716 u32 rsvd;
717};
718
719struct be_cmd_resp_get_flow_control {
720 struct be_cmd_resp_hdr hdr;
721 u16 tx_flow_control;
722 u16 rx_flow_control;
723} __packed;
724
725/******************** Modify EQ Delay *******************/
726struct be_cmd_req_modify_eq_delay {
727 struct be_cmd_req_hdr hdr;
728 u32 num_eq;
729 struct {
730 u32 eq_id;
731 u32 phase;
732 u32 delay_multiplier;
733 } delay[8];
734} __packed;
735
736struct be_cmd_resp_modify_eq_delay {
737 struct be_cmd_resp_hdr hdr;
738 u32 rsvd0;
739} __packed;
740
741/******************** Get FW Config *******************/
742struct be_cmd_req_query_fw_cfg {
743 struct be_cmd_req_hdr hdr;
744 u32 rsvd[30];
745};
746
747struct be_cmd_resp_query_fw_cfg {
748 struct be_cmd_resp_hdr hdr;
749 u32 be_config_number;
750 u32 asic_revision;
751 u32 phys_port;
3486be29 752 u32 function_mode;
6b7c5b94
SP		 753 u32 rsvd[26];
754};
755
fad9ab2c
SB		 756/******************** Port Beacon ***************************/
757
758#define BEACON_STATE_ENABLED 0x1
759#define BEACON_STATE_DISABLED 0x0
760
761struct be_cmd_req_enable_disable_beacon {
762 struct be_cmd_req_hdr hdr;
763 u8 port_num;
764 u8 beacon_state;
765 u8 beacon_duration;
766 u8 status_duration;
767} __packed;
768
769struct be_cmd_resp_enable_disable_beacon {
770 struct be_cmd_resp_hdr resp_hdr;
771 u32 rsvd0;
772} __packed;
773
774struct be_cmd_req_get_beacon_state {
775 struct be_cmd_req_hdr hdr;
776 u8 port_num;
777 u8 rsvd0;
778 u16 rsvd1;
779} __packed;
780
781struct be_cmd_resp_get_beacon_state {
782 struct be_cmd_resp_hdr resp_hdr;
783 u8 beacon_state;
784 u8 rsvd0[3];
785} __packed;
786
84517482
AK		 787/****************** Firmware Flash ******************/
788struct flashrom_params {
789 u32 op_code;
790 u32 op_type;
791 u32 data_buf_size;
792 u32 offset;
793 u8 data_buf[4];
794};
795
796struct be_cmd_write_flashrom {
797 struct be_cmd_req_hdr hdr;
798 struct flashrom_params params;
799};
800
71d8d1b5
AK		 801/************************ WOL *******************************/
802struct be_cmd_req_acpi_wol_magic_config{
803 struct be_cmd_req_hdr hdr;
804 u32 rsvd0[145];
805 u8 magic_mac[6];
806 u8 rsvd2[2];
807} __packed;
808
ff33a6e2
S		 809/********************** LoopBack test *********************/
810struct be_cmd_req_loopback_test {
811 struct be_cmd_req_hdr hdr;
812 u32 loopback_type;
813 u32 num_pkts;
814 u64 pattern;
815 u32 src_port;
816 u32 dest_port;
817 u32 pkt_size;
818};
819
820struct be_cmd_resp_loopback_test {
821 struct be_cmd_resp_hdr resp_hdr;
822 u32 status;
823 u32 num_txfer;
824 u32 num_rx;
825 u32 miscomp_off;
826 u32 ticks_compl;
827};
828
fced9999
SB		 829struct be_cmd_req_set_lmode {
830 struct be_cmd_req_hdr hdr;
831 u8 src_port;
832 u8 dest_port;
833 u8 loopback_type;
834 u8 loopback_state;
835};
836
837struct be_cmd_resp_set_lmode {
838 struct be_cmd_resp_hdr resp_hdr;
839 u8 rsvd0[4];
840};
841
ff33a6e2
S		 842/********************** DDR DMA test *********************/
843struct be_cmd_req_ddrdma_test {
844 struct be_cmd_req_hdr hdr;
845 u64 pattern;
846 u32 byte_count;
847 u32 rsvd0;
848 u8 snd_buff[4096];
849 u8 rsvd1[4096];
850};
851
852struct be_cmd_resp_ddrdma_test {
853 struct be_cmd_resp_hdr hdr;
854 u64 pattern;
855 u32 byte_cnt;
856 u32 snd_err;
857 u8 rsvd0[4096];
858 u8 rcv_buff[4096];
859};
860
368c0ca2
SB		 861/*********************** SEEPROM Read ***********************/
862
863#define BE_READ_SEEPROM_LEN 1024
864struct be_cmd_req_seeprom_read {
865 struct be_cmd_req_hdr hdr;
866 u8 rsvd0[BE_READ_SEEPROM_LEN];
867};
868
869struct be_cmd_resp_seeprom_read {
870 struct be_cmd_req_hdr hdr;
871 u8 seeprom_data[BE_READ_SEEPROM_LEN];
872};
873
ee3cb629
AK		 874enum {
875 PHY_TYPE_CX4_10GB = 0,
876 PHY_TYPE_XFP_10GB,
877 PHY_TYPE_SFP_1GB,
878 PHY_TYPE_SFP_PLUS_10GB,
879 PHY_TYPE_KR_10GB,
880 PHY_TYPE_KX4_10GB,
881 PHY_TYPE_BASET_10GB,
882 PHY_TYPE_BASET_1GB,
883 PHY_TYPE_DISABLED = 255
884};
885
886struct be_cmd_req_get_phy_info {
887 struct be_cmd_req_hdr hdr;
888 u8 rsvd0[24];
889};
890struct be_cmd_resp_get_phy_info {
891 struct be_cmd_req_hdr hdr;
892 u16 phy_type;
893 u16 interface_type;
894 u32 misc_params;
895 u32 future_use[4];
896};
897
e1d18735
AK		 898/*********************** Set QOS ***********************/
899
900#define BE_QOS_BITS_NIC 1
901
902struct be_cmd_req_set_qos {
903 struct be_cmd_req_hdr hdr;
904 u32 valid_bits;
905 u32 max_bps_nic;
906 u32 rsvd[7];
907};
908
909struct be_cmd_resp_set_qos {
910 struct be_cmd_resp_hdr hdr;
911 u32 rsvd;
912};
913
8788fdc2
SP		 914extern int be_pci_fnum_get(struct be_adapter *adapter);
915extern int be_cmd_POST(struct be_adapter *adapter);
916extern int be_cmd_mac_addr_query(struct be_adapter *adapter, u8 *mac_addr,
6b7c5b94 917 u8 type, bool permanent, u32 if_handle);
8788fdc2 918extern int be_cmd_pmac_add(struct be_adapter *adapter, u8 *mac_addr,
6b7c5b94 919 u32 if_id, u32 *pmac_id);
8788fdc2 920extern int be_cmd_pmac_del(struct be_adapter *adapter, u32 if_id, u32 pmac_id);
73d540f2
SP		 921extern int be_cmd_if_create(struct be_adapter *adapter, u32 cap_flags,
922 u32 en_flags, u8 *mac, bool pmac_invalid,
ba343c77 923 u32 *if_handle, u32 *pmac_id, u32 domain);
8788fdc2
SP		 924extern int be_cmd_if_destroy(struct be_adapter *adapter, u32 if_handle);
925extern int be_cmd_eq_create(struct be_adapter *adapter,
6b7c5b94 926 struct be_queue_info *eq, int eq_delay);
8788fdc2 927extern int be_cmd_cq_create(struct be_adapter *adapter,
6b7c5b94
SP		 928 struct be_queue_info *cq, struct be_queue_info *eq,
929 bool sol_evts, bool no_delay,
930 int num_cqe_dma_coalesce);
8788fdc2 931extern int be_cmd_mccq_create(struct be_adapter *adapter,
5fb379ee
SP		 932 struct be_queue_info *mccq,
933 struct be_queue_info *cq);
8788fdc2 934extern int be_cmd_txq_create(struct be_adapter *adapter,
6b7c5b94
SP		 935 struct be_queue_info *txq,
936 struct be_queue_info *cq);
8788fdc2 937extern int be_cmd_rxq_create(struct be_adapter *adapter,
6b7c5b94
SP		 938 struct be_queue_info *rxq, u16 cq_id,
939 u16 frag_size, u16 max_frame_size, u32 if_id,
940 u32 rss);
8788fdc2 941extern int be_cmd_q_destroy(struct be_adapter *adapter, struct be_queue_info *q,
6b7c5b94 942 int type);
8788fdc2 943extern int be_cmd_link_status_query(struct be_adapter *adapter,
0388f251 944 bool *link_up, u8 *mac_speed, u16 *link_speed);
8788fdc2
SP		 945extern int be_cmd_reset(struct be_adapter *adapter);
946extern int be_cmd_get_stats(struct be_adapter *adapter,
6b7c5b94 947 struct be_dma_mem *nonemb_cmd);
8788fdc2 948extern int be_cmd_get_fw_ver(struct be_adapter *adapter, char *fw_ver);
6b7c5b94 949
8788fdc2
SP		 950extern int be_cmd_modify_eqd(struct be_adapter *adapter, u32 eq_id, u32 eqd);
951extern int be_cmd_vlan_config(struct be_adapter *adapter, u32 if_id,
6b7c5b94
SP		 952 u16 *vtag_array, u32 num, bool untagged,
953 bool promiscuous);
8788fdc2 954extern int be_cmd_promiscuous_config(struct be_adapter *adapter,
6b7c5b94 955 u8 port_num, bool en);
8788fdc2 956extern int be_cmd_multicast_set(struct be_adapter *adapter, u32 if_id,
0ddf477b 957 struct net_device *netdev, struct be_dma_mem *mem);
8788fdc2 958extern int be_cmd_set_flow_control(struct be_adapter *adapter,
6b7c5b94 959 u32 tx_fc, u32 rx_fc);
8788fdc2 960extern int be_cmd_get_flow_control(struct be_adapter *adapter,
6b7c5b94 961 u32 *tx_fc, u32 *rx_fc);
dcb9b564
AK		 962extern int be_cmd_query_fw_cfg(struct be_adapter *adapter,
963 u32 *port_num, u32 *cap);
14074eab 964extern int be_cmd_reset_function(struct be_adapter *adapter);
f31e50a8 965extern int be_process_mcc(struct be_adapter *adapter, int *status);
fad9ab2c
SB		 966extern int be_cmd_set_beacon_state(struct be_adapter *adapter,
967 u8 port_num, u8 beacon, u8 status, u8 state);
968extern int be_cmd_get_beacon_state(struct be_adapter *adapter,
969 u8 port_num, u32 *state);
0388f251
SB		 970extern int be_cmd_read_port_type(struct be_adapter *adapter, u32 port,
971 u8 *connector);
84517482
AK		 972extern int be_cmd_write_flashrom(struct be_adapter *adapter,
973 struct be_dma_mem *cmd, u32 flash_oper,
974 u32 flash_opcode, u32 buf_size);
3f0d4560
AK		 975int be_cmd_get_flash_crc(struct be_adapter *adapter, u8 *flashed_crc,
976 int offset);
71d8d1b5
AK		 977extern int be_cmd_enable_magic_wol(struct be_adapter *adapter, u8 *mac,
978 struct be_dma_mem *nonemb_cmd);
2243e2e9
SP		 979extern int be_cmd_fw_init(struct be_adapter *adapter);
980extern int be_cmd_fw_clean(struct be_adapter *adapter);
7a1e9b20
SP		 981extern void be_async_mcc_enable(struct be_adapter *adapter);
982extern void be_async_mcc_disable(struct be_adapter *adapter);
ff33a6e2
S		 983extern int be_cmd_loopback_test(struct be_adapter *adapter, u32 port_num,
984 u32 loopback_type, u32 pkt_size,
985 u32 num_pkts, u64 pattern);
986extern int be_cmd_ddr_dma_test(struct be_adapter *adapter, u64 pattern,
987 u32 byte_cnt, struct be_dma_mem *cmd);
368c0ca2
SB		 988extern int be_cmd_get_seeprom_data(struct be_adapter *adapter,
989 struct be_dma_mem *nonemb_cmd);
fced9999
SB		 990extern int be_cmd_set_loopback(struct be_adapter *adapter, u8 port_num,
991 u8 loopback_type, u8 enable);
ee3cb629
AK		 992extern int be_cmd_get_phy_info(struct be_adapter *adapter,
993 struct be_dma_mem *cmd);
e1d18735 994extern int be_cmd_set_qos(struct be_adapter *adapter, u32 bps, u32 domain);
d4a66e75 995
Linux kernel - Deliverables
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