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be2net: Add error recovery during load for Lancer
[deliverable/linux.git] / drivers / net / benet / be_cmds.h
CommitLineData
6b7c5b94 1/*
294aedcf 2 * Copyright (C) 2005 - 2010 ServerEngines
6b7c5b94
SP		 3 * All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License version 2
7 * as published by the Free Software Foundation. The full GNU General
8 * Public License is included in this distribution in the file called COPYING.
9 *
10 * Contact Information:
11 * linux-drivers@serverengines.com
12 *
13 * ServerEngines
14 * 209 N. Fair Oaks Ave
15 * Sunnyvale, CA 94085
16 */
17
18/*
19 * The driver sends configuration and managements command requests to the
20 * firmware in the BE. These requests are communicated to the processor
21 * using Work Request Blocks (WRBs) submitted to the MCC-WRB ring or via one
22 * WRB inside a MAILBOX.
23 * The commands are serviced by the ARM processor in the BladeEngine's MPU.
24 */
25
26struct be_sge {
27 u32 pa_lo;
28 u32 pa_hi;
29 u32 len;
30};
31
32#define MCC_WRB_EMBEDDED_MASK 1 /* bit 0 of dword 0*/
33#define MCC_WRB_SGE_CNT_SHIFT 3 /* bits 3 - 7 of dword 0 */
34#define MCC_WRB_SGE_CNT_MASK 0x1F /* bits 3 - 7 of dword 0 */
35struct be_mcc_wrb {
36 u32 embedded; /* dword 0 */
37 u32 payload_length; /* dword 1 */
38 u32 tag0; /* dword 2 */
39 u32 tag1; /* dword 3 */
40 u32 rsvd; /* dword 4 */
41 union {
42 u8 embedded_payload[236]; /* used by embedded cmds */
43 struct be_sge sgl[19]; /* used by non-embedded cmds */
44 } payload;
45};
46
47#define CQE_FLAGS_VALID_MASK (1 << 31)
48#define CQE_FLAGS_ASYNC_MASK (1 << 30)
49#define CQE_FLAGS_COMPLETED_MASK (1 << 28)
50#define CQE_FLAGS_CONSUMED_MASK (1 << 27)
51
52/* Completion Status */
53enum {
54 MCC_STATUS_SUCCESS = 0x0,
55/* The client does not have sufficient privileges to execute the command */
56 MCC_STATUS_INSUFFICIENT_PRIVILEGES = 0x1,
57/* A parameter in the command was invalid. */
58 MCC_STATUS_INVALID_PARAMETER = 0x2,
59/* There are insufficient chip resources to execute the command */
60 MCC_STATUS_INSUFFICIENT_RESOURCES = 0x3,
61/* The command is completing because the queue was getting flushed */
62 MCC_STATUS_QUEUE_FLUSHING = 0x4,
63/* The command is completing with a DMA error */
b31c50a7 64 MCC_STATUS_DMA_FAILED = 0x5,
49643848 65 MCC_STATUS_NOT_SUPPORTED = 66
6b7c5b94
SP		 66};
67
68#define CQE_STATUS_COMPL_MASK 0xFFFF
69#define CQE_STATUS_COMPL_SHIFT 0 /* bits 0 - 15 */
70#define CQE_STATUS_EXTD_MASK 0xFFFF
f5209b44 71#define CQE_STATUS_EXTD_SHIFT 16 /* bits 16 - 31 */
6b7c5b94 72
efd2e40a 73struct be_mcc_compl {
6b7c5b94
SP		 74 u32 status; /* dword 0 */
75 u32 tag0; /* dword 1 */
76 u32 tag1; /* dword 2 */
77 u32 flags; /* dword 3 */
78};
79
a8f447bd
SP		 80/* When the async bit of mcc_compl is set, the last 4 bytes of
81 * mcc_compl is interpreted as follows:
82 */
83#define ASYNC_TRAILER_EVENT_CODE_SHIFT 8 /* bits 8 - 15 */
84#define ASYNC_TRAILER_EVENT_CODE_MASK 0xFF
cc4ce020
SK		 85#define ASYNC_TRAILER_EVENT_TYPE_SHIFT 16
86#define ASYNC_TRAILER_EVENT_TYPE_MASK 0xFF
a8f447bd 87#define ASYNC_EVENT_CODE_LINK_STATE 0x1
cc4ce020
SK		 88#define ASYNC_EVENT_CODE_GRP_5 0x5
89#define ASYNC_EVENT_QOS_SPEED 0x1
90#define ASYNC_EVENT_COS_PRIORITY 0x2
3968fa1e 91#define ASYNC_EVENT_PVID_STATE 0x3
a8f447bd
SP		 92struct be_async_event_trailer {
93 u32 code;
94};
95
96enum {
97 ASYNC_EVENT_LINK_DOWN = 0x0,
98 ASYNC_EVENT_LINK_UP = 0x1
99};
100
101/* When the event code of an async trailer is link-state, the mcc_compl
102 * must be interpreted as follows
103 */
104struct be_async_event_link_state {
105 u8 physical_port;
106 u8 port_link_status;
107 u8 port_duplex;
108 u8 port_speed;
109 u8 port_fault;
110 u8 rsvd0[7];
111 struct be_async_event_trailer trailer;
112} __packed;
113
cc4ce020
SK		 114/* When the event code of an async trailer is GRP-5 and event_type is QOS_SPEED
115 * the mcc_compl must be interpreted as follows
116 */
117struct be_async_event_grp5_qos_link_speed {
118 u8 physical_port;
119 u8 rsvd[5];
120 u16 qos_link_speed;
121 u32 event_tag;
122 struct be_async_event_trailer trailer;
123} __packed;
124
125/* When the event code of an async trailer is GRP5 and event type is
126 * CoS-Priority, the mcc_compl must be interpreted as follows
127 */
128struct be_async_event_grp5_cos_priority {
129 u8 physical_port;
130 u8 available_priority_bmap;
131 u8 reco_default_priority;
132 u8 valid;
133 u8 rsvd0;
134 u8 event_tag;
135 struct be_async_event_trailer trailer;
136} __packed;
137
3968fa1e
AK		 138/* When the event code of an async trailer is GRP5 and event type is
139 * PVID state, the mcc_compl must be interpreted as follows
140 */
141struct be_async_event_grp5_pvid_state {
142 u8 enabled;
143 u8 rsvd0;
144 u16 tag;
145 u32 event_tag;
146 u32 rsvd1;
147 struct be_async_event_trailer trailer;
148} __packed;
149
6b7c5b94
SP		 150struct be_mcc_mailbox {
151 struct be_mcc_wrb wrb;
efd2e40a 152 struct be_mcc_compl compl;
6b7c5b94
SP		 153};
154
155#define CMD_SUBSYSTEM_COMMON 0x1
156#define CMD_SUBSYSTEM_ETH 0x3
ff33a6e2 157#define CMD_SUBSYSTEM_LOWLEVEL 0xb
6b7c5b94
SP		 158
159#define OPCODE_COMMON_NTWK_MAC_QUERY 1
160#define OPCODE_COMMON_NTWK_MAC_SET 2
161#define OPCODE_COMMON_NTWK_MULTICAST_SET 3
162#define OPCODE_COMMON_NTWK_VLAN_CONFIG 4
163#define OPCODE_COMMON_NTWK_LINK_STATUS_QUERY 5
fa9a6fed 164#define OPCODE_COMMON_READ_FLASHROM 6
84517482 165#define OPCODE_COMMON_WRITE_FLASHROM 7
6b7c5b94
SP		 166#define OPCODE_COMMON_CQ_CREATE 12
167#define OPCODE_COMMON_EQ_CREATE 13
cc4ce020 168#define OPCODE_COMMON_MCC_CREATE 21
e1d18735 169#define OPCODE_COMMON_SET_QOS 28
cc4ce020 170#define OPCODE_COMMON_MCC_CREATE_EXT 90
368c0ca2 171#define OPCODE_COMMON_SEEPROM_READ 30
9e1453c5 172#define OPCODE_COMMON_GET_CNTL_ATTRIBUTES 32
6b7c5b94
SP		 173#define OPCODE_COMMON_NTWK_RX_FILTER 34
174#define OPCODE_COMMON_GET_FW_VERSION 35
175#define OPCODE_COMMON_SET_FLOW_CONTROL 36
176#define OPCODE_COMMON_GET_FLOW_CONTROL 37
177#define OPCODE_COMMON_SET_FRAME_SIZE 39
178#define OPCODE_COMMON_MODIFY_EQ_DELAY 41
179#define OPCODE_COMMON_FIRMWARE_CONFIG 42
180#define OPCODE_COMMON_NTWK_INTERFACE_CREATE 50
181#define OPCODE_COMMON_NTWK_INTERFACE_DESTROY 51
5fb379ee 182#define OPCODE_COMMON_MCC_DESTROY 53
6b7c5b94
SP		 183#define OPCODE_COMMON_CQ_DESTROY 54
184#define OPCODE_COMMON_EQ_DESTROY 55
185#define OPCODE_COMMON_QUERY_FIRMWARE_CONFIG 58
186#define OPCODE_COMMON_NTWK_PMAC_ADD 59
187#define OPCODE_COMMON_NTWK_PMAC_DEL 60
14074eab 188#define OPCODE_COMMON_FUNCTION_RESET 61
fad9ab2c
SB		 189#define OPCODE_COMMON_ENABLE_DISABLE_BEACON 69
190#define OPCODE_COMMON_GET_BEACON_STATE 70
0388f251 191#define OPCODE_COMMON_READ_TRANSRECV_DATA 73
ee3cb629 192#define OPCODE_COMMON_GET_PHY_DETAILS 102
609ff3bb 193#define OPCODE_COMMON_GET_CNTL_ADDITIONAL_ATTRIBUTES 121
6b7c5b94 194
3abcdeda 195#define OPCODE_ETH_RSS_CONFIG 1
6b7c5b94
SP		 196#define OPCODE_ETH_ACPI_CONFIG 2
197#define OPCODE_ETH_PROMISCUOUS 3
198#define OPCODE_ETH_GET_STATISTICS 4
199#define OPCODE_ETH_TX_CREATE 7
200#define OPCODE_ETH_RX_CREATE 8
201#define OPCODE_ETH_TX_DESTROY 9
202#define OPCODE_ETH_RX_DESTROY 10
71d8d1b5 203#define OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG 12
6b7c5b94 204
ff33a6e2
S		 205#define OPCODE_LOWLEVEL_HOST_DDR_DMA 17
206#define OPCODE_LOWLEVEL_LOOPBACK_TEST 18
fced9999 207#define OPCODE_LOWLEVEL_SET_LOOPBACK_MODE 19
ff33a6e2 208
6b7c5b94
SP		 209struct be_cmd_req_hdr {
210 u8 opcode; /* dword 0 */
211 u8 subsystem; /* dword 0 */
212 u8 port_number; /* dword 0 */
213 u8 domain; /* dword 0 */
214 u32 timeout; /* dword 1 */
215 u32 request_length; /* dword 2 */
7b139c83
AK		 216 u8 version; /* dword 3 */
217 u8 rsvd[3]; /* dword 3 */
6b7c5b94
SP		 218};
219
220#define RESP_HDR_INFO_OPCODE_SHIFT 0 /* bits 0 - 7 */
221#define RESP_HDR_INFO_SUBSYS_SHIFT 8 /* bits 8 - 15 */
222struct be_cmd_resp_hdr {
223 u32 info; /* dword 0 */
224 u32 status; /* dword 1 */
225 u32 response_length; /* dword 2 */
226 u32 actual_resp_len; /* dword 3 */
227};
228
229struct phys_addr {
230 u32 lo;
231 u32 hi;
232};
233
234/**************************
235 * BE Command definitions *
236 **************************/
237
238/* Pseudo amap definition in which each bit of the actual structure is defined
239 * as a byte: used to calculate offset/shift/mask of each field */
240struct amap_eq_context {
241 u8 cidx[13]; /* dword 0*/
242 u8 rsvd0[3]; /* dword 0*/
243 u8 epidx[13]; /* dword 0*/
244 u8 valid; /* dword 0*/
245 u8 rsvd1; /* dword 0*/
246 u8 size; /* dword 0*/
247 u8 pidx[13]; /* dword 1*/
248 u8 rsvd2[3]; /* dword 1*/
249 u8 pd[10]; /* dword 1*/
250 u8 count[3]; /* dword 1*/
251 u8 solevent; /* dword 1*/
252 u8 stalled; /* dword 1*/
253 u8 armed; /* dword 1*/
254 u8 rsvd3[4]; /* dword 2*/
255 u8 func[8]; /* dword 2*/
256 u8 rsvd4; /* dword 2*/
257 u8 delaymult[10]; /* dword 2*/
258 u8 rsvd5[2]; /* dword 2*/
259 u8 phase[2]; /* dword 2*/
260 u8 nodelay; /* dword 2*/
261 u8 rsvd6[4]; /* dword 2*/
262 u8 rsvd7[32]; /* dword 3*/
263} __packed;
264
265struct be_cmd_req_eq_create {
266 struct be_cmd_req_hdr hdr;
267 u16 num_pages; /* sword */
268 u16 rsvd0; /* sword */
269 u8 context[sizeof(struct amap_eq_context) / 8];
270 struct phys_addr pages[8];
271} __packed;
272
273struct be_cmd_resp_eq_create {
274 struct be_cmd_resp_hdr resp_hdr;
275 u16 eq_id; /* sword */
276 u16 rsvd0; /* sword */
277} __packed;
278
279/******************** Mac query ***************************/
280enum {
281 MAC_ADDRESS_TYPE_STORAGE = 0x0,
282 MAC_ADDRESS_TYPE_NETWORK = 0x1,
283 MAC_ADDRESS_TYPE_PD = 0x2,
284 MAC_ADDRESS_TYPE_MANAGEMENT = 0x3
285};
286
287struct mac_addr {
288 u16 size_of_struct;
289 u8 addr[ETH_ALEN];
290} __packed;
291
292struct be_cmd_req_mac_query {
293 struct be_cmd_req_hdr hdr;
294 u8 type;
295 u8 permanent;
296 u16 if_id;
297} __packed;
298
299struct be_cmd_resp_mac_query {
300 struct be_cmd_resp_hdr hdr;
301 struct mac_addr mac;
302};
303
304/******************** PMac Add ***************************/
305struct be_cmd_req_pmac_add {
306 struct be_cmd_req_hdr hdr;
307 u32 if_id;
308 u8 mac_address[ETH_ALEN];
309 u8 rsvd0[2];
310} __packed;
311
312struct be_cmd_resp_pmac_add {
313 struct be_cmd_resp_hdr hdr;
314 u32 pmac_id;
315};
316
317/******************** PMac Del ***************************/
318struct be_cmd_req_pmac_del {
319 struct be_cmd_req_hdr hdr;
320 u32 if_id;
321 u32 pmac_id;
322};
323
324/******************** Create CQ ***************************/
325/* Pseudo amap definition in which each bit of the actual structure is defined
326 * as a byte: used to calculate offset/shift/mask of each field */
fe6d2a38 327struct amap_cq_context_be {
6b7c5b94
SP		 328 u8 cidx[11]; /* dword 0*/
329 u8 rsvd0; /* dword 0*/
330 u8 coalescwm[2]; /* dword 0*/
331 u8 nodelay; /* dword 0*/
332 u8 epidx[11]; /* dword 0*/
333 u8 rsvd1; /* dword 0*/
334 u8 count[2]; /* dword 0*/
335 u8 valid; /* dword 0*/
336 u8 solevent; /* dword 0*/
337 u8 eventable; /* dword 0*/
338 u8 pidx[11]; /* dword 1*/
339 u8 rsvd2; /* dword 1*/
340 u8 pd[10]; /* dword 1*/
341 u8 eqid[8]; /* dword 1*/
342 u8 stalled; /* dword 1*/
343 u8 armed; /* dword 1*/
344 u8 rsvd3[4]; /* dword 2*/
345 u8 func[8]; /* dword 2*/
346 u8 rsvd4[20]; /* dword 2*/
347 u8 rsvd5[32]; /* dword 3*/
348} __packed;
349
fe6d2a38
SP		 350struct amap_cq_context_lancer {
351 u8 rsvd0[12]; /* dword 0*/
352 u8 coalescwm[2]; /* dword 0*/
353 u8 nodelay; /* dword 0*/
354 u8 rsvd1[12]; /* dword 0*/
355 u8 count[2]; /* dword 0*/
356 u8 valid; /* dword 0*/
357 u8 rsvd2; /* dword 0*/
358 u8 eventable; /* dword 0*/
359 u8 eqid[16]; /* dword 1*/
360 u8 rsvd3[15]; /* dword 1*/
361 u8 armed; /* dword 1*/
362 u8 rsvd4[32]; /* dword 2*/
363 u8 rsvd5[32]; /* dword 3*/
364} __packed;
365
6b7c5b94
SP		 366struct be_cmd_req_cq_create {
367 struct be_cmd_req_hdr hdr;
368 u16 num_pages;
fe6d2a38
SP		 369 u8 page_size;
370 u8 rsvd0;
371 u8 context[sizeof(struct amap_cq_context_be) / 8];
6b7c5b94
SP		 372 struct phys_addr pages[8];
373} __packed;
374
fe6d2a38 375
6b7c5b94
SP		 376struct be_cmd_resp_cq_create {
377 struct be_cmd_resp_hdr hdr;
378 u16 cq_id;
379 u16 rsvd0;
380} __packed;
381
5fb379ee
SP		 382/******************** Create MCCQ ***************************/
383/* Pseudo amap definition in which each bit of the actual structure is defined
384 * as a byte: used to calculate offset/shift/mask of each field */
fe6d2a38 385struct amap_mcc_context_be {
5fb379ee
SP		 386 u8 con_index[14];
387 u8 rsvd0[2];
388 u8 ring_size[4];
389 u8 fetch_wrb;
390 u8 fetch_r2t;
391 u8 cq_id[10];
392 u8 prod_index[14];
393 u8 fid[8];
394 u8 pdid[9];
395 u8 valid;
396 u8 rsvd1[32];
397 u8 rsvd2[32];
398} __packed;
399
fe6d2a38
SP		 400struct amap_mcc_context_lancer {
401 u8 async_cq_id[16];
402 u8 ring_size[4];
403 u8 rsvd0[12];
404 u8 rsvd1[31];
405 u8 valid;
406 u8 async_cq_valid[1];
407 u8 rsvd2[31];
408 u8 rsvd3[32];
409} __packed;
410
5fb379ee
SP		 411struct be_cmd_req_mcc_create {
412 struct be_cmd_req_hdr hdr;
413 u16 num_pages;
fe6d2a38 414 u16 cq_id;
cc4ce020 415 u32 async_event_bitmap[1];
fe6d2a38 416 u8 context[sizeof(struct amap_mcc_context_be) / 8];
5fb379ee
SP		 417 struct phys_addr pages[8];
418} __packed;
419
420struct be_cmd_resp_mcc_create {
421 struct be_cmd_resp_hdr hdr;
422 u16 id;
423 u16 rsvd0;
424} __packed;
425
6b7c5b94
SP		 426/******************** Create TxQ ***************************/
427#define BE_ETH_TX_RING_TYPE_STANDARD 2
428#define BE_ULP1_NUM 1
429
430/* Pseudo amap definition in which each bit of the actual structure is defined
431 * as a byte: used to calculate offset/shift/mask of each field */
432struct amap_tx_context {
433 u8 rsvd0[16]; /* dword 0 */
434 u8 tx_ring_size[4]; /* dword 0 */
435 u8 rsvd1[26]; /* dword 0 */
436 u8 pci_func_id[8]; /* dword 1 */
437 u8 rsvd2[9]; /* dword 1 */
438 u8 ctx_valid; /* dword 1 */
439 u8 cq_id_send[16]; /* dword 2 */
440 u8 rsvd3[16]; /* dword 2 */
441 u8 rsvd4[32]; /* dword 3 */
442 u8 rsvd5[32]; /* dword 4 */
443 u8 rsvd6[32]; /* dword 5 */
444 u8 rsvd7[32]; /* dword 6 */
445 u8 rsvd8[32]; /* dword 7 */
446 u8 rsvd9[32]; /* dword 8 */
447 u8 rsvd10[32]; /* dword 9 */
448 u8 rsvd11[32]; /* dword 10 */
449 u8 rsvd12[32]; /* dword 11 */
450 u8 rsvd13[32]; /* dword 12 */
451 u8 rsvd14[32]; /* dword 13 */
452 u8 rsvd15[32]; /* dword 14 */
453 u8 rsvd16[32]; /* dword 15 */
454} __packed;
455
456struct be_cmd_req_eth_tx_create {
457 struct be_cmd_req_hdr hdr;
458 u8 num_pages;
459 u8 ulp_num;
460 u8 type;
461 u8 bound_port;
462 u8 context[sizeof(struct amap_tx_context) / 8];
463 struct phys_addr pages[8];
464} __packed;
465
466struct be_cmd_resp_eth_tx_create {
467 struct be_cmd_resp_hdr hdr;
468 u16 cid;
469 u16 rsvd0;
470} __packed;
471
472/******************** Create RxQ ***************************/
473struct be_cmd_req_eth_rx_create {
474 struct be_cmd_req_hdr hdr;
475 u16 cq_id;
476 u8 frag_size;
477 u8 num_pages;
478 struct phys_addr pages[2];
479 u32 interface_id;
480 u16 max_frame_size;
481 u16 rsvd0;
482 u32 rss_queue;
483} __packed;
484
485struct be_cmd_resp_eth_rx_create {
486 struct be_cmd_resp_hdr hdr;
487 u16 id;
3abcdeda 488 u8 rss_id;
6b7c5b94
SP		 489 u8 rsvd0;
490} __packed;
491
492/******************** Q Destroy ***************************/
493/* Type of Queue to be destroyed */
494enum {
495 QTYPE_EQ = 1,
496 QTYPE_CQ,
497 QTYPE_TXQ,
5fb379ee
SP		 498 QTYPE_RXQ,
499 QTYPE_MCCQ
6b7c5b94
SP		 500};
501
502struct be_cmd_req_q_destroy {
503 struct be_cmd_req_hdr hdr;
504 u16 id;
505 u16 bypass_flush; /* valid only for rx q destroy */
506} __packed;
507
508/************ I/f Create (it's actually I/f Config Create)**********/
509
510/* Capability flags for the i/f */
511enum be_if_flags {
512 BE_IF_FLAGS_RSS = 0x4,
513 BE_IF_FLAGS_PROMISCUOUS = 0x8,
514 BE_IF_FLAGS_BROADCAST = 0x10,
515 BE_IF_FLAGS_UNTAGGED = 0x20,
516 BE_IF_FLAGS_ULP = 0x40,
517 BE_IF_FLAGS_VLAN_PROMISCUOUS = 0x80,
518 BE_IF_FLAGS_VLAN = 0x100,
519 BE_IF_FLAGS_MCAST_PROMISCUOUS = 0x200,
520 BE_IF_FLAGS_PASS_L2_ERRORS = 0x400,
521 BE_IF_FLAGS_PASS_L3L4_ERRORS = 0x800
522};
523
524/* An RX interface is an object with one or more MAC addresses and
525 * filtering capabilities. */
526struct be_cmd_req_if_create {
527 struct be_cmd_req_hdr hdr;
af901ca1 528 u32 version; /* ignore currently */
6b7c5b94
SP		 529 u32 capability_flags;
530 u32 enable_flags;
531 u8 mac_addr[ETH_ALEN];
532 u8 rsvd0;
533 u8 pmac_invalid; /* if set, don't attach the mac addr to the i/f */
534 u32 vlan_tag; /* not used currently */
535} __packed;
536
537struct be_cmd_resp_if_create {
538 struct be_cmd_resp_hdr hdr;
539 u32 interface_id;
540 u32 pmac_id;
541};
542
543/****** I/f Destroy(it's actually I/f Config Destroy )**********/
544struct be_cmd_req_if_destroy {
545 struct be_cmd_req_hdr hdr;
546 u32 interface_id;
547};
548
549/*************** HW Stats Get **********************************/
550struct be_port_rxf_stats {
551 u32 rx_bytes_lsd; /* dword 0*/
552 u32 rx_bytes_msd; /* dword 1*/
553 u32 rx_total_frames; /* dword 2*/
554 u32 rx_unicast_frames; /* dword 3*/
555 u32 rx_multicast_frames; /* dword 4*/
556 u32 rx_broadcast_frames; /* dword 5*/
557 u32 rx_crc_errors; /* dword 6*/
558 u32 rx_alignment_symbol_errors; /* dword 7*/
559 u32 rx_pause_frames; /* dword 8*/
560 u32 rx_control_frames; /* dword 9*/
561 u32 rx_in_range_errors; /* dword 10*/
562 u32 rx_out_range_errors; /* dword 11*/
563 u32 rx_frame_too_long; /* dword 12*/
564 u32 rx_address_match_errors; /* dword 13*/
565 u32 rx_vlan_mismatch; /* dword 14*/
566 u32 rx_dropped_too_small; /* dword 15*/
567 u32 rx_dropped_too_short; /* dword 16*/
568 u32 rx_dropped_header_too_small; /* dword 17*/
569 u32 rx_dropped_tcp_length; /* dword 18*/
570 u32 rx_dropped_runt; /* dword 19*/
571 u32 rx_64_byte_packets; /* dword 20*/
572 u32 rx_65_127_byte_packets; /* dword 21*/
573 u32 rx_128_256_byte_packets; /* dword 22*/
574 u32 rx_256_511_byte_packets; /* dword 23*/
575 u32 rx_512_1023_byte_packets; /* dword 24*/
576 u32 rx_1024_1518_byte_packets; /* dword 25*/
577 u32 rx_1519_2047_byte_packets; /* dword 26*/
578 u32 rx_2048_4095_byte_packets; /* dword 27*/
579 u32 rx_4096_8191_byte_packets; /* dword 28*/
580 u32 rx_8192_9216_byte_packets; /* dword 29*/
581 u32 rx_ip_checksum_errs; /* dword 30*/
582 u32 rx_tcp_checksum_errs; /* dword 31*/
583 u32 rx_udp_checksum_errs; /* dword 32*/
584 u32 rx_non_rss_packets; /* dword 33*/
585 u32 rx_ipv4_packets; /* dword 34*/
586 u32 rx_ipv6_packets; /* dword 35*/
587 u32 rx_ipv4_bytes_lsd; /* dword 36*/
588 u32 rx_ipv4_bytes_msd; /* dword 37*/
589 u32 rx_ipv6_bytes_lsd; /* dword 38*/
590 u32 rx_ipv6_bytes_msd; /* dword 39*/
591 u32 rx_chute1_packets; /* dword 40*/
592 u32 rx_chute2_packets; /* dword 41*/
593 u32 rx_chute3_packets; /* dword 42*/
594 u32 rx_management_packets; /* dword 43*/
595 u32 rx_switched_unicast_packets; /* dword 44*/
596 u32 rx_switched_multicast_packets; /* dword 45*/
597 u32 rx_switched_broadcast_packets; /* dword 46*/
598 u32 tx_bytes_lsd; /* dword 47*/
599 u32 tx_bytes_msd; /* dword 48*/
600 u32 tx_unicastframes; /* dword 49*/
601 u32 tx_multicastframes; /* dword 50*/
602 u32 tx_broadcastframes; /* dword 51*/
603 u32 tx_pauseframes; /* dword 52*/
604 u32 tx_controlframes; /* dword 53*/
605 u32 tx_64_byte_packets; /* dword 54*/
606 u32 tx_65_127_byte_packets; /* dword 55*/
607 u32 tx_128_256_byte_packets; /* dword 56*/
608 u32 tx_256_511_byte_packets; /* dword 57*/
609 u32 tx_512_1023_byte_packets; /* dword 58*/
610 u32 tx_1024_1518_byte_packets; /* dword 59*/
611 u32 tx_1519_2047_byte_packets; /* dword 60*/
612 u32 tx_2048_4095_byte_packets; /* dword 61*/
613 u32 tx_4096_8191_byte_packets; /* dword 62*/
614 u32 tx_8192_9216_byte_packets; /* dword 63*/
615 u32 rx_fifo_overflow; /* dword 64*/
616 u32 rx_input_fifo_overflow; /* dword 65*/
617};
618
619struct be_rxf_stats {
620 struct be_port_rxf_stats port[2];
621 u32 rx_drops_no_pbuf; /* dword 132*/
622 u32 rx_drops_no_txpb; /* dword 133*/
623 u32 rx_drops_no_erx_descr; /* dword 134*/
624 u32 rx_drops_no_tpre_descr; /* dword 135*/
625 u32 management_rx_port_packets; /* dword 136*/
626 u32 management_rx_port_bytes; /* dword 137*/
627 u32 management_rx_port_pause_frames; /* dword 138*/
628 u32 management_rx_port_errors; /* dword 139*/
629 u32 management_tx_port_packets; /* dword 140*/
630 u32 management_tx_port_bytes; /* dword 141*/
631 u32 management_tx_port_pause; /* dword 142*/
632 u32 management_rx_port_rxfifo_overflow; /* dword 143*/
633 u32 rx_drops_too_many_frags; /* dword 144*/
634 u32 rx_drops_invalid_ring; /* dword 145*/
635 u32 forwarded_packets; /* dword 146*/
636 u32 rx_drops_mtu; /* dword 147*/
f6c4bf3e
AK		 637 u32 rsvd0[7];
638 u32 port0_jabber_events;
639 u32 port1_jabber_events;
640 u32 rsvd1[6];
6b7c5b94
SP		 641};
642
643struct be_erx_stats {
644 u32 rx_drops_no_fragments[44]; /* dwordS 0 to 43*/
645 u32 debug_wdma_sent_hold; /* dword 44*/
646 u32 debug_wdma_pbfree_sent_hold; /* dword 45*/
647 u32 debug_wdma_zerobyte_pbfree_sent_hold; /* dword 46*/
648 u32 debug_pmem_pbuf_dealloc; /* dword 47*/
649};
650
f6c4bf3e
AK		 651struct be_pmem_stats {
652 u32 eth_red_drops;
653 u32 rsvd[4];
654};
655
6b7c5b94
SP		 656struct be_hw_stats {
657 struct be_rxf_stats rxf;
658 u32 rsvd[48];
659 struct be_erx_stats erx;
f6c4bf3e 660 struct be_pmem_stats pmem;
6b7c5b94
SP		 661};
662
663struct be_cmd_req_get_stats {
664 struct be_cmd_req_hdr hdr;
665 u8 rsvd[sizeof(struct be_hw_stats)];
666};
667
668struct be_cmd_resp_get_stats {
669 struct be_cmd_resp_hdr hdr;
670 struct be_hw_stats hw_stats;
671};
672
609ff3bb
AK		 673struct be_cmd_req_get_cntl_addnl_attribs {
674 struct be_cmd_req_hdr hdr;
675 u8 rsvd[8];
676};
677
678struct be_cmd_resp_get_cntl_addnl_attribs {
679 struct be_cmd_resp_hdr hdr;
680 u16 ipl_file_number;
681 u8 ipl_file_version;
682 u8 rsvd0;
683 u8 on_die_temperature; /* in degrees centigrade*/
684 u8 rsvd1[3];
685};
686
6b7c5b94
SP		 687struct be_cmd_req_vlan_config {
688 struct be_cmd_req_hdr hdr;
689 u8 interface_id;
690 u8 promiscuous;
691 u8 untagged;
692 u8 num_vlan;
693 u16 normal_vlan[64];
694} __packed;
695
696struct be_cmd_req_promiscuous_config {
697 struct be_cmd_req_hdr hdr;
698 u8 port0_promiscuous;
699 u8 port1_promiscuous;
700 u16 rsvd0;
701} __packed;
702
e7b909a6
SP		 703/******************** Multicast MAC Config *******************/
704#define BE_MAX_MC 64 /* set mcast promisc if > 64 */
6b7c5b94
SP		 705struct macaddr {
706 u8 byte[ETH_ALEN];
707};
708
709struct be_cmd_req_mcast_mac_config {
710 struct be_cmd_req_hdr hdr;
711 u16 num_mac;
712 u8 promiscuous;
713 u8 interface_id;
e7b909a6 714 struct macaddr mac[BE_MAX_MC];
6b7c5b94
SP		 715} __packed;
716
717static inline struct be_hw_stats *
718hw_stats_from_cmd(struct be_cmd_resp_get_stats *cmd)
719{
720 return &cmd->hw_stats;
721}
722
723/******************** Link Status Query *******************/
724struct be_cmd_req_link_status {
725 struct be_cmd_req_hdr hdr;
726 u32 rsvd;
727};
728
6b7c5b94
SP		 729enum {
730 PHY_LINK_DUPLEX_NONE = 0x0,
731 PHY_LINK_DUPLEX_HALF = 0x1,
732 PHY_LINK_DUPLEX_FULL = 0x2
733};
734
735enum {
736 PHY_LINK_SPEED_ZERO = 0x0, /* => No link */
737 PHY_LINK_SPEED_10MBPS = 0x1,
738 PHY_LINK_SPEED_100MBPS = 0x2,
739 PHY_LINK_SPEED_1GBPS = 0x3,
740 PHY_LINK_SPEED_10GBPS = 0x4
741};
742
743struct be_cmd_resp_link_status {
744 struct be_cmd_resp_hdr hdr;
745 u8 physical_port;
746 u8 mac_duplex;
747 u8 mac_speed;
748 u8 mac_fault;
749 u8 mgmt_mac_duplex;
750 u8 mgmt_mac_speed;
0388f251
SB		 751 u16 link_speed;
752 u32 rsvd0;
6b7c5b94
SP		 753} __packed;
754
0388f251
SB		 755/******************** Port Identification ***************************/
756/* Identifies the type of port attached to NIC */
757struct be_cmd_req_port_type {
758 struct be_cmd_req_hdr hdr;
759 u32 page_num;
760 u32 port;
761};
762
763enum {
764 TR_PAGE_A0 = 0xa0,
765 TR_PAGE_A2 = 0xa2
766};
767
768struct be_cmd_resp_port_type {
769 struct be_cmd_resp_hdr hdr;
770 u32 page_num;
771 u32 port;
772 struct data {
773 u8 identifier;
774 u8 identifier_ext;
775 u8 connector;
776 u8 transceiver[8];
777 u8 rsvd0[3];
778 u8 length_km;
779 u8 length_hm;
780 u8 length_om1;
781 u8 length_om2;
782 u8 length_cu;
783 u8 length_cu_m;
784 u8 vendor_name[16];
785 u8 rsvd;
786 u8 vendor_oui[3];
787 u8 vendor_pn[16];
788 u8 vendor_rev[4];
789 } data;
790};
791
6b7c5b94 792/******************** Get FW Version *******************/
6b7c5b94
SP		 793struct be_cmd_req_get_fw_version {
794 struct be_cmd_req_hdr hdr;
795 u8 rsvd0[FW_VER_LEN];
796 u8 rsvd1[FW_VER_LEN];
797} __packed;
798
799struct be_cmd_resp_get_fw_version {
800 struct be_cmd_resp_hdr hdr;
801 u8 firmware_version_string[FW_VER_LEN];
802 u8 fw_on_flash_version_string[FW_VER_LEN];
803} __packed;
804
805/******************** Set Flow Contrl *******************/
806struct be_cmd_req_set_flow_control {
807 struct be_cmd_req_hdr hdr;
808 u16 tx_flow_control;
809 u16 rx_flow_control;
810} __packed;
811
812/******************** Get Flow Contrl *******************/
813struct be_cmd_req_get_flow_control {
814 struct be_cmd_req_hdr hdr;
815 u32 rsvd;
816};
817
818struct be_cmd_resp_get_flow_control {
819 struct be_cmd_resp_hdr hdr;
820 u16 tx_flow_control;
821 u16 rx_flow_control;
822} __packed;
823
824/******************** Modify EQ Delay *******************/
825struct be_cmd_req_modify_eq_delay {
826 struct be_cmd_req_hdr hdr;
827 u32 num_eq;
828 struct {
829 u32 eq_id;
830 u32 phase;
831 u32 delay_multiplier;
832 } delay[8];
833} __packed;
834
835struct be_cmd_resp_modify_eq_delay {
836 struct be_cmd_resp_hdr hdr;
837 u32 rsvd0;
838} __packed;
839
840/******************** Get FW Config *******************/
3abcdeda 841#define BE_FUNCTION_CAPS_RSS 0x2
6b7c5b94
SP		 842struct be_cmd_req_query_fw_cfg {
843 struct be_cmd_req_hdr hdr;
3abcdeda 844 u32 rsvd[31];
6b7c5b94
SP		 845};
846
847struct be_cmd_resp_query_fw_cfg {
848 struct be_cmd_resp_hdr hdr;
849 u32 be_config_number;
850 u32 asic_revision;
851 u32 phys_port;
3486be29 852 u32 function_mode;
6b7c5b94 853 u32 rsvd[26];
3abcdeda
SP		 854 u32 function_caps;
855};
856
857/******************** RSS Config *******************/
858/* RSS types */
859#define RSS_ENABLE_NONE 0x0
860#define RSS_ENABLE_IPV4 0x1
861#define RSS_ENABLE_TCP_IPV4 0x2
862#define RSS_ENABLE_IPV6 0x4
863#define RSS_ENABLE_TCP_IPV6 0x8
864
865struct be_cmd_req_rss_config {
866 struct be_cmd_req_hdr hdr;
867 u32 if_id;
868 u16 enable_rss;
869 u16 cpu_table_size_log2;
870 u32 hash[10];
871 u8 cpu_table[128];
872 u8 flush;
873 u8 rsvd0[3];
6b7c5b94
SP		 874};
875
fad9ab2c
SB		 876/******************** Port Beacon ***************************/
877
878#define BEACON_STATE_ENABLED 0x1
879#define BEACON_STATE_DISABLED 0x0
880
881struct be_cmd_req_enable_disable_beacon {
882 struct be_cmd_req_hdr hdr;
883 u8 port_num;
884 u8 beacon_state;
885 u8 beacon_duration;
886 u8 status_duration;
887} __packed;
888
889struct be_cmd_resp_enable_disable_beacon {
890 struct be_cmd_resp_hdr resp_hdr;
891 u32 rsvd0;
892} __packed;
893
894struct be_cmd_req_get_beacon_state {
895 struct be_cmd_req_hdr hdr;
896 u8 port_num;
897 u8 rsvd0;
898 u16 rsvd1;
899} __packed;
900
901struct be_cmd_resp_get_beacon_state {
902 struct be_cmd_resp_hdr resp_hdr;
903 u8 beacon_state;
904 u8 rsvd0[3];
905} __packed;
906
84517482
AK		 907/****************** Firmware Flash ******************/
908struct flashrom_params {
909 u32 op_code;
910 u32 op_type;
911 u32 data_buf_size;
912 u32 offset;
913 u8 data_buf[4];
914};
915
916struct be_cmd_write_flashrom {
917 struct be_cmd_req_hdr hdr;
918 struct flashrom_params params;
919};
920
71d8d1b5
AK		 921/************************ WOL *******************************/
922struct be_cmd_req_acpi_wol_magic_config{
923 struct be_cmd_req_hdr hdr;
924 u32 rsvd0[145];
925 u8 magic_mac[6];
926 u8 rsvd2[2];
927} __packed;
928
ff33a6e2
S		 929/********************** LoopBack test *********************/
930struct be_cmd_req_loopback_test {
931 struct be_cmd_req_hdr hdr;
932 u32 loopback_type;
933 u32 num_pkts;
934 u64 pattern;
935 u32 src_port;
936 u32 dest_port;
937 u32 pkt_size;
938};
939
940struct be_cmd_resp_loopback_test {
941 struct be_cmd_resp_hdr resp_hdr;
942 u32 status;
943 u32 num_txfer;
944 u32 num_rx;
945 u32 miscomp_off;
946 u32 ticks_compl;
947};
948
fced9999
SB		 949struct be_cmd_req_set_lmode {
950 struct be_cmd_req_hdr hdr;
951 u8 src_port;
952 u8 dest_port;
953 u8 loopback_type;
954 u8 loopback_state;
955};
956
957struct be_cmd_resp_set_lmode {
958 struct be_cmd_resp_hdr resp_hdr;
959 u8 rsvd0[4];
960};
961
ff33a6e2
S		 962/********************** DDR DMA test *********************/
963struct be_cmd_req_ddrdma_test {
964 struct be_cmd_req_hdr hdr;
965 u64 pattern;
966 u32 byte_count;
967 u32 rsvd0;
968 u8 snd_buff[4096];
969 u8 rsvd1[4096];
970};
971
972struct be_cmd_resp_ddrdma_test {
973 struct be_cmd_resp_hdr hdr;
974 u64 pattern;
975 u32 byte_cnt;
976 u32 snd_err;
977 u8 rsvd0[4096];
978 u8 rcv_buff[4096];
979};
980
368c0ca2
SB		 981/*********************** SEEPROM Read ***********************/
982
983#define BE_READ_SEEPROM_LEN 1024
984struct be_cmd_req_seeprom_read {
985 struct be_cmd_req_hdr hdr;
986 u8 rsvd0[BE_READ_SEEPROM_LEN];
987};
988
989struct be_cmd_resp_seeprom_read {
990 struct be_cmd_req_hdr hdr;
991 u8 seeprom_data[BE_READ_SEEPROM_LEN];
992};
993
ee3cb629
AK		 994enum {
995 PHY_TYPE_CX4_10GB = 0,
996 PHY_TYPE_XFP_10GB,
997 PHY_TYPE_SFP_1GB,
998 PHY_TYPE_SFP_PLUS_10GB,
999 PHY_TYPE_KR_10GB,
1000 PHY_TYPE_KX4_10GB,
1001 PHY_TYPE_BASET_10GB,
1002 PHY_TYPE_BASET_1GB,
1003 PHY_TYPE_DISABLED = 255
1004};
1005
1006struct be_cmd_req_get_phy_info {
1007 struct be_cmd_req_hdr hdr;
1008 u8 rsvd0[24];
1009};
1010struct be_cmd_resp_get_phy_info {
1011 struct be_cmd_req_hdr hdr;
1012 u16 phy_type;
1013 u16 interface_type;
1014 u32 misc_params;
1015 u32 future_use[4];
1016};
1017
e1d18735
AK		 1018/*********************** Set QOS ***********************/
1019
1020#define BE_QOS_BITS_NIC 1
1021
1022struct be_cmd_req_set_qos {
1023 struct be_cmd_req_hdr hdr;
1024 u32 valid_bits;
1025 u32 max_bps_nic;
1026 u32 rsvd[7];
1027};
1028
1029struct be_cmd_resp_set_qos {
1030 struct be_cmd_resp_hdr hdr;
1031 u32 rsvd;
1032};
1033
9e1453c5
AK		 1034/*********************** Controller Attributes ***********************/
1035struct be_cmd_req_cntl_attribs {
1036 struct be_cmd_req_hdr hdr;
1037};
1038
1039struct be_cmd_resp_cntl_attribs {
1040 struct be_cmd_resp_hdr hdr;
1041 struct mgmt_controller_attrib attribs;
1042};
1043
8788fdc2
SP		 1044extern int be_pci_fnum_get(struct be_adapter *adapter);
1045extern int be_cmd_POST(struct be_adapter *adapter);
1046extern int be_cmd_mac_addr_query(struct be_adapter *adapter, u8 *mac_addr,
6b7c5b94 1047 u8 type, bool permanent, u32 if_handle);
8788fdc2 1048extern int be_cmd_pmac_add(struct be_adapter *adapter, u8 *mac_addr,
f8617e08
AK		 1049 u32 if_id, u32 *pmac_id, u32 domain);
1050extern int be_cmd_pmac_del(struct be_adapter *adapter, u32 if_id,
1051 u32 pmac_id, u32 domain);
73d540f2
SP		 1052extern int be_cmd_if_create(struct be_adapter *adapter, u32 cap_flags,
1053 u32 en_flags, u8 *mac, bool pmac_invalid,
ba343c77 1054 u32 *if_handle, u32 *pmac_id, u32 domain);
658681f7
AK		 1055extern int be_cmd_if_destroy(struct be_adapter *adapter, u32 if_handle,
1056 u32 domain);
8788fdc2 1057extern int be_cmd_eq_create(struct be_adapter *adapter,
6b7c5b94 1058 struct be_queue_info *eq, int eq_delay);
8788fdc2 1059extern int be_cmd_cq_create(struct be_adapter *adapter,
6b7c5b94
SP		 1060 struct be_queue_info *cq, struct be_queue_info *eq,
1061 bool sol_evts, bool no_delay,
1062 int num_cqe_dma_coalesce);
8788fdc2 1063extern int be_cmd_mccq_create(struct be_adapter *adapter,
5fb379ee
SP		 1064 struct be_queue_info *mccq,
1065 struct be_queue_info *cq);
8788fdc2 1066extern int be_cmd_txq_create(struct be_adapter *adapter,
6b7c5b94
SP		 1067 struct be_queue_info *txq,
1068 struct be_queue_info *cq);
8788fdc2 1069extern int be_cmd_rxq_create(struct be_adapter *adapter,
6b7c5b94
SP		 1070 struct be_queue_info *rxq, u16 cq_id,
1071 u16 frag_size, u16 max_frame_size, u32 if_id,
3abcdeda 1072 u32 rss, u8 *rss_id);
8788fdc2 1073extern int be_cmd_q_destroy(struct be_adapter *adapter, struct be_queue_info *q,
6b7c5b94 1074 int type);
8788fdc2 1075extern int be_cmd_link_status_query(struct be_adapter *adapter,
0388f251 1076 bool *link_up, u8 *mac_speed, u16 *link_speed);
8788fdc2
SP		 1077extern int be_cmd_reset(struct be_adapter *adapter);
1078extern int be_cmd_get_stats(struct be_adapter *adapter,
6b7c5b94 1079 struct be_dma_mem *nonemb_cmd);
8788fdc2 1080extern int be_cmd_get_fw_ver(struct be_adapter *adapter, char *fw_ver);
6b7c5b94 1081
8788fdc2
SP		 1082extern int be_cmd_modify_eqd(struct be_adapter *adapter, u32 eq_id, u32 eqd);
1083extern int be_cmd_vlan_config(struct be_adapter *adapter, u32 if_id,
6b7c5b94
SP		 1084 u16 *vtag_array, u32 num, bool untagged,
1085 bool promiscuous);
8788fdc2 1086extern int be_cmd_promiscuous_config(struct be_adapter *adapter,
6b7c5b94 1087 u8 port_num, bool en);
8788fdc2 1088extern int be_cmd_multicast_set(struct be_adapter *adapter, u32 if_id,
0ddf477b 1089 struct net_device *netdev, struct be_dma_mem *mem);
8788fdc2 1090extern int be_cmd_set_flow_control(struct be_adapter *adapter,
6b7c5b94 1091 u32 tx_fc, u32 rx_fc);
8788fdc2 1092extern int be_cmd_get_flow_control(struct be_adapter *adapter,
6b7c5b94 1093 u32 *tx_fc, u32 *rx_fc);
dcb9b564 1094extern int be_cmd_query_fw_cfg(struct be_adapter *adapter,
3abcdeda 1095 u32 *port_num, u32 *function_mode, u32 *function_caps);
14074eab 1096extern int be_cmd_reset_function(struct be_adapter *adapter);
3abcdeda
SP		 1097extern int be_cmd_rss_config(struct be_adapter *adapter, u8 *rsstable,
1098 u16 table_size);
f31e50a8 1099extern int be_process_mcc(struct be_adapter *adapter, int *status);
fad9ab2c
SB		 1100extern int be_cmd_set_beacon_state(struct be_adapter *adapter,
1101 u8 port_num, u8 beacon, u8 status, u8 state);
1102extern int be_cmd_get_beacon_state(struct be_adapter *adapter,
1103 u8 port_num, u32 *state);
84517482
AK		 1104extern int be_cmd_write_flashrom(struct be_adapter *adapter,
1105 struct be_dma_mem *cmd, u32 flash_oper,
1106 u32 flash_opcode, u32 buf_size);
3f0d4560
AK		 1107int be_cmd_get_flash_crc(struct be_adapter *adapter, u8 *flashed_crc,
1108 int offset);
71d8d1b5
AK		 1109extern int be_cmd_enable_magic_wol(struct be_adapter *adapter, u8 *mac,
1110 struct be_dma_mem *nonemb_cmd);
2243e2e9
SP		 1111extern int be_cmd_fw_init(struct be_adapter *adapter);
1112extern int be_cmd_fw_clean(struct be_adapter *adapter);
7a1e9b20
SP		 1113extern void be_async_mcc_enable(struct be_adapter *adapter);
1114extern void be_async_mcc_disable(struct be_adapter *adapter);
ff33a6e2
S		 1115extern int be_cmd_loopback_test(struct be_adapter *adapter, u32 port_num,
1116 u32 loopback_type, u32 pkt_size,
1117 u32 num_pkts, u64 pattern);
1118extern int be_cmd_ddr_dma_test(struct be_adapter *adapter, u64 pattern,
1119 u32 byte_cnt, struct be_dma_mem *cmd);
368c0ca2
SB		 1120extern int be_cmd_get_seeprom_data(struct be_adapter *adapter,
1121 struct be_dma_mem *nonemb_cmd);
fced9999
SB		 1122extern int be_cmd_set_loopback(struct be_adapter *adapter, u8 port_num,
1123 u8 loopback_type, u8 enable);
ee3cb629
AK		 1124extern int be_cmd_get_phy_info(struct be_adapter *adapter,
1125 struct be_dma_mem *cmd);
e1d18735 1126extern int be_cmd_set_qos(struct be_adapter *adapter, u32 bps, u32 domain);
d053de91 1127extern void be_detect_dump_ue(struct be_adapter *adapter);
609ff3bb 1128extern int be_cmd_get_die_temperature(struct be_adapter *adapter);
9e1453c5 1129extern int be_cmd_get_cntl_attributes(struct be_adapter *adapter);
d4a66e75 1130
Linux kernel - Deliverables
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