Commit | Line | Data |
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6b7c5b94 | 1 | /* |
294aedcf | 2 | * Copyright (C) 2005 - 2010 ServerEngines |
6b7c5b94 SP |
3 | * All rights reserved. |
4 | * | |
5 | * This program is free software; you can redistribute it and/or | |
6 | * modify it under the terms of the GNU General Public License version 2 | |
7 | * as published by the Free Software Foundation. The full GNU General | |
8 | * Public License is included in this distribution in the file called COPYING. | |
9 | * | |
10 | * Contact Information: | |
11 | * linux-drivers@serverengines.com | |
12 | * | |
13 | * ServerEngines | |
14 | * 209 N. Fair Oaks Ave | |
15 | * Sunnyvale, CA 94085 | |
16 | */ | |
17 | ||
18 | /********* Mailbox door bell *************/ | |
19 | /* Used for driver communication with the FW. | |
20 | * The software must write this register twice to post any command. First, | |
21 | * it writes the register with hi=1 and the upper bits of the physical address | |
22 | * for the MAILBOX structure. Software must poll the ready bit until this | |
23 | * is acknowledged. Then, sotware writes the register with hi=0 with the lower | |
24 | * bits in the address. It must poll the ready bit until the command is | |
25 | * complete. Upon completion, the MAILBOX will contain a valid completion | |
26 | * queue entry. | |
27 | */ | |
28 | #define MPU_MAILBOX_DB_OFFSET 0x160 | |
29 | #define MPU_MAILBOX_DB_RDY_MASK 0x1 /* bit 0 */ | |
30 | #define MPU_MAILBOX_DB_HI_MASK 0x2 /* bit 1 */ | |
31 | ||
32 | #define MPU_EP_CONTROL 0 | |
33 | ||
34 | /********** MPU semphore ******************/ | |
fe6d2a38 SP |
35 | #define MPU_EP_SEMAPHORE_OFFSET 0xac |
36 | #define MPU_EP_SEMAPHORE_IF_TYPE2_OFFSET 0x400 | |
37 | #define EP_SEMAPHORE_POST_STAGE_MASK 0x0000FFFF | |
38 | #define EP_SEMAPHORE_POST_ERR_MASK 0x1 | |
39 | #define EP_SEMAPHORE_POST_ERR_SHIFT 31 | |
40 | ||
6b7c5b94 SP |
41 | /* MPU semphore POST stage values */ |
42 | #define POST_STAGE_AWAITING_HOST_RDY 0x1 /* FW awaiting goahead from host */ | |
43 | #define POST_STAGE_HOST_RDY 0x2 /* Host has given go-ahed to FW */ | |
44 | #define POST_STAGE_BE_RESET 0x3 /* Host wants to reset chip */ | |
45 | #define POST_STAGE_ARMFW_RDY 0xc000 /* FW is done with POST */ | |
46 | ||
47 | /********* Memory BAR register ************/ | |
48 | #define PCICFG_MEMBAR_CTRL_INT_CTRL_OFFSET 0xfc | |
49 | /* Host Interrupt Enable, if set interrupts are enabled although "PCI Interrupt | |
50 | * Disable" may still globally block interrupts in addition to individual | |
51 | * interrupt masks; a mechanism for the device driver to block all interrupts | |
52 | * atomically without having to arbitrate for the PCI Interrupt Disable bit | |
53 | * with the OS. | |
54 | */ | |
55 | #define MEMBAR_CTRL_INT_CTRL_HOSTINTR_MASK (1 << 29) /* bit 29 */ | |
6b7c5b94 | 56 | |
65155b37 | 57 | /********* Power management (WOL) **********/ |
71d8d1b5 AK |
58 | #define PCICFG_PM_CONTROL_OFFSET 0x44 |
59 | #define PCICFG_PM_CONTROL_MASK 0x108 /* bits 3 & 8 */ | |
60 | ||
7c185276 AK |
61 | /********* Online Control Registers *******/ |
62 | #define PCICFG_ONLINE0 0xB0 | |
63 | #define PCICFG_ONLINE1 0xB4 | |
64 | ||
65 | /********* UE Status and Mask Registers ***/ | |
66 | #define PCICFG_UE_STATUS_LOW 0xA0 | |
67 | #define PCICFG_UE_STATUS_HIGH 0xA4 | |
68 | #define PCICFG_UE_STATUS_LOW_MASK 0xA8 | |
69 | #define PCICFG_UE_STATUS_HI_MASK 0xAC | |
70 | ||
fe6d2a38 SP |
71 | /******** SLI_INTF ***********************/ |
72 | #define SLI_INTF_REG_OFFSET 0x58 | |
73 | #define SLI_INTF_VALID_MASK 0xE0000000 | |
74 | #define SLI_INTF_VALID 0xC0000000 | |
75 | #define SLI_INTF_HINT2_MASK 0x1F000000 | |
76 | #define SLI_INTF_HINT2_SHIFT 24 | |
77 | #define SLI_INTF_HINT1_MASK 0x00FF0000 | |
78 | #define SLI_INTF_HINT1_SHIFT 16 | |
79 | #define SLI_INTF_FAMILY_MASK 0x00000F00 | |
80 | #define SLI_INTF_FAMILY_SHIFT 8 | |
81 | #define SLI_INTF_IF_TYPE_MASK 0x0000F000 | |
82 | #define SLI_INTF_IF_TYPE_SHIFT 12 | |
83 | #define SLI_INTF_REV_MASK 0x000000F0 | |
84 | #define SLI_INTF_REV_SHIFT 4 | |
85 | #define SLI_INTF_FT_MASK 0x00000001 | |
86 | ||
87 | ||
88 | /* SLI family */ | |
89 | #define BE_SLI_FAMILY 0x0 | |
90 | #define LANCER_A0_SLI_FAMILY 0xA | |
91 | ||
92 | ||
c001c213 SP |
93 | /********* ISR0 Register offset **********/ |
94 | #define CEV_ISR0_OFFSET 0xC18 | |
95 | #define CEV_ISR_SIZE 4 | |
96 | ||
6b7c5b94 SP |
97 | /********* Event Q door bell *************/ |
98 | #define DB_EQ_OFFSET DB_CQ_OFFSET | |
99 | #define DB_EQ_RING_ID_MASK 0x1FF /* bits 0 - 8 */ | |
fe6d2a38 SP |
100 | #define DB_EQ_RING_ID_EXT_MASK 0x3e00 /* bits 9-13 */ |
101 | #define DB_EQ_RING_ID_EXT_MASK_SHIFT (2) /* qid bits 9-13 placing at 11-15 */ | |
102 | ||
6b7c5b94 SP |
103 | /* Clear the interrupt for this eq */ |
104 | #define DB_EQ_CLR_SHIFT (9) /* bit 9 */ | |
105 | /* Must be 1 */ | |
5fb379ee | 106 | #define DB_EQ_EVNT_SHIFT (10) /* bit 10 */ |
6b7c5b94 SP |
107 | /* Number of event entries processed */ |
108 | #define DB_EQ_NUM_POPPED_SHIFT (16) /* bits 16 - 28 */ | |
109 | /* Rearm bit */ | |
110 | #define DB_EQ_REARM_SHIFT (29) /* bit 29 */ | |
111 | ||
112 | /********* Compl Q door bell *************/ | |
113 | #define DB_CQ_OFFSET 0x120 | |
114 | #define DB_CQ_RING_ID_MASK 0x3FF /* bits 0 - 9 */ | |
fe6d2a38 SP |
115 | #define DB_CQ_RING_ID_EXT_MASK 0x7C00 /* bits 10-14 */ |
116 | #define DB_CQ_RING_ID_EXT_MASK_SHIFT (1) /* qid bits 10-14 | |
117 | placing at 11-15 */ | |
118 | ||
6b7c5b94 SP |
119 | /* Number of event entries processed */ |
120 | #define DB_CQ_NUM_POPPED_SHIFT (16) /* bits 16 - 28 */ | |
121 | /* Rearm bit */ | |
122 | #define DB_CQ_REARM_SHIFT (29) /* bit 29 */ | |
123 | ||
124 | /********** TX ULP door bell *************/ | |
125 | #define DB_TXULP1_OFFSET 0x60 | |
126 | #define DB_TXULP_RING_ID_MASK 0x7FF /* bits 0 - 10 */ | |
127 | /* Number of tx entries posted */ | |
128 | #define DB_TXULP_NUM_POSTED_SHIFT (16) /* bits 16 - 29 */ | |
129 | #define DB_TXULP_NUM_POSTED_MASK 0x3FFF /* bits 16 - 29 */ | |
130 | ||
131 | /********** RQ(erx) door bell ************/ | |
132 | #define DB_RQ_OFFSET 0x100 | |
133 | #define DB_RQ_RING_ID_MASK 0x3FF /* bits 0 - 9 */ | |
134 | /* Number of rx frags posted */ | |
135 | #define DB_RQ_NUM_POSTED_SHIFT (24) /* bits 24 - 31 */ | |
136 | ||
5fb379ee SP |
137 | /********** MCC door bell ************/ |
138 | #define DB_MCCQ_OFFSET 0x140 | |
139 | #define DB_MCCQ_RING_ID_MASK 0x7FF /* bits 0 - 10 */ | |
140 | /* Number of entries posted */ | |
141 | #define DB_MCCQ_NUM_POSTED_SHIFT (16) /* bits 16 - 29 */ | |
142 | ||
ba343c77 SB |
143 | /********** SRIOV VF PCICFG OFFSET ********/ |
144 | #define SRIOV_VF_PCICFG_OFFSET (4096) | |
145 | ||
3f0d4560 AK |
146 | /* Flashrom related descriptors */ |
147 | #define IMAGE_TYPE_FIRMWARE 160 | |
148 | #define IMAGE_TYPE_BOOTCODE 224 | |
149 | #define IMAGE_TYPE_OPTIONROM 32 | |
150 | ||
151 | #define NUM_FLASHDIR_ENTRIES 32 | |
152 | ||
153 | #define IMG_TYPE_ISCSI_ACTIVE 0 | |
154 | #define IMG_TYPE_REDBOOT 1 | |
155 | #define IMG_TYPE_BIOS 2 | |
156 | #define IMG_TYPE_PXE_BIOS 3 | |
157 | #define IMG_TYPE_FCOE_BIOS 8 | |
158 | #define IMG_TYPE_ISCSI_BACKUP 9 | |
159 | #define IMG_TYPE_FCOE_FW_ACTIVE 10 | |
160 | #define IMG_TYPE_FCOE_FW_BACKUP 11 | |
9fe96934 | 161 | #define IMG_TYPE_NCSI_FW 13 |
3f0d4560 AK |
162 | |
163 | #define FLASHROM_OPER_FLASH 1 | |
164 | #define FLASHROM_OPER_SAVE 2 | |
165 | #define FLASHROM_OPER_REPORT 4 | |
166 | ||
167 | #define FLASH_IMAGE_MAX_SIZE_g2 (1310720) /* Max firmware image sz */ | |
168 | #define FLASH_BIOS_IMAGE_MAX_SIZE_g2 (262144) /* Max OPTION ROM img sz */ | |
169 | #define FLASH_REDBOOT_IMAGE_MAX_SIZE_g2 (262144) /* Max Redboot image sz */ | |
170 | #define FLASH_IMAGE_MAX_SIZE_g3 (2097152) /* Max fw image size */ | |
171 | #define FLASH_BIOS_IMAGE_MAX_SIZE_g3 (524288) /* Max OPTION ROM img sz */ | |
172 | #define FLASH_REDBOOT_IMAGE_MAX_SIZE_g3 (1048576) /* Max Redboot image sz */ | |
9fe96934 | 173 | #define FLASH_NCSI_IMAGE_MAX_SIZE_g3 (262144) /* Max NSCI image sz */ |
3f0d4560 AK |
174 | |
175 | #define FLASH_NCSI_MAGIC (0x16032009) | |
176 | #define FLASH_NCSI_DISABLED (0) | |
177 | #define FLASH_NCSI_ENABLED (1) | |
178 | ||
179 | #define FLASH_NCSI_BITFILE_HDR_OFFSET (0x600000) | |
180 | ||
181 | /* Offsets for components on Flash. */ | |
182 | #define FLASH_iSCSI_PRIMARY_IMAGE_START_g2 (1048576) | |
183 | #define FLASH_iSCSI_BACKUP_IMAGE_START_g2 (2359296) | |
184 | #define FLASH_FCoE_PRIMARY_IMAGE_START_g2 (3670016) | |
185 | #define FLASH_FCoE_BACKUP_IMAGE_START_g2 (4980736) | |
186 | #define FLASH_iSCSI_BIOS_START_g2 (7340032) | |
187 | #define FLASH_PXE_BIOS_START_g2 (7864320) | |
188 | #define FLASH_FCoE_BIOS_START_g2 (524288) | |
189 | #define FLASH_REDBOOT_START_g2 (0) | |
190 | ||
9fe96934 | 191 | #define FLASH_NCSI_START_g3 (15990784) |
3f0d4560 AK |
192 | #define FLASH_iSCSI_PRIMARY_IMAGE_START_g3 (2097152) |
193 | #define FLASH_iSCSI_BACKUP_IMAGE_START_g3 (4194304) | |
194 | #define FLASH_FCoE_PRIMARY_IMAGE_START_g3 (6291456) | |
195 | #define FLASH_FCoE_BACKUP_IMAGE_START_g3 (8388608) | |
196 | #define FLASH_iSCSI_BIOS_START_g3 (12582912) | |
197 | #define FLASH_PXE_BIOS_START_g3 (13107200) | |
198 | #define FLASH_FCoE_BIOS_START_g3 (13631488) | |
199 | #define FLASH_REDBOOT_START_g3 (262144) | |
200 | ||
1ef78abe AK |
201 | /************* Rx Packet Type Encoding **************/ |
202 | #define BE_UNICAST_PACKET 0 | |
203 | #define BE_MULTICAST_PACKET 1 | |
204 | #define BE_BROADCAST_PACKET 2 | |
205 | #define BE_RSVD_PACKET 3 | |
3f0d4560 | 206 | |
6b7c5b94 SP |
207 | /* |
208 | * BE descriptors: host memory data structures whose formats | |
209 | * are hardwired in BE silicon. | |
210 | */ | |
211 | /* Event Queue Descriptor */ | |
212 | #define EQ_ENTRY_VALID_MASK 0x1 /* bit 0 */ | |
213 | #define EQ_ENTRY_RES_ID_MASK 0xFFFF /* bits 16 - 31 */ | |
214 | #define EQ_ENTRY_RES_ID_SHIFT 16 | |
3f0d4560 | 215 | |
6b7c5b94 SP |
216 | struct be_eq_entry { |
217 | u32 evt; | |
218 | }; | |
219 | ||
220 | /* TX Queue Descriptor */ | |
221 | #define ETH_WRB_FRAG_LEN_MASK 0xFFFF | |
222 | struct be_eth_wrb { | |
223 | u32 frag_pa_hi; /* dword 0 */ | |
224 | u32 frag_pa_lo; /* dword 1 */ | |
225 | u32 rsvd0; /* dword 2 */ | |
226 | u32 frag_len; /* dword 3: bits 0 - 15 */ | |
227 | } __packed; | |
228 | ||
229 | /* Pseudo amap definition for eth_hdr_wrb in which each bit of the | |
230 | * actual structure is defined as a byte : used to calculate | |
231 | * offset/shift/mask of each field */ | |
232 | struct amap_eth_hdr_wrb { | |
233 | u8 rsvd0[32]; /* dword 0 */ | |
234 | u8 rsvd1[32]; /* dword 1 */ | |
235 | u8 complete; /* dword 2 */ | |
236 | u8 event; | |
237 | u8 crc; | |
238 | u8 forward; | |
49e4b847 | 239 | u8 lso6; |
6b7c5b94 SP |
240 | u8 mgmt; |
241 | u8 ipcs; | |
242 | u8 udpcs; | |
243 | u8 tcpcs; | |
244 | u8 lso; | |
245 | u8 vlan; | |
246 | u8 gso[2]; | |
247 | u8 num_wrb[5]; | |
248 | u8 lso_mss[14]; | |
249 | u8 len[16]; /* dword 3 */ | |
250 | u8 vlan_tag[16]; | |
251 | } __packed; | |
252 | ||
253 | struct be_eth_hdr_wrb { | |
254 | u32 dw[4]; | |
255 | }; | |
256 | ||
257 | /* TX Compl Queue Descriptor */ | |
258 | ||
259 | /* Pseudo amap definition for eth_tx_compl in which each bit of the | |
260 | * actual structure is defined as a byte: used to calculate | |
261 | * offset/shift/mask of each field */ | |
262 | struct amap_eth_tx_compl { | |
263 | u8 wrb_index[16]; /* dword 0 */ | |
264 | u8 ct[2]; /* dword 0 */ | |
265 | u8 port[2]; /* dword 0 */ | |
266 | u8 rsvd0[8]; /* dword 0 */ | |
267 | u8 status[4]; /* dword 0 */ | |
268 | u8 user_bytes[16]; /* dword 1 */ | |
269 | u8 nwh_bytes[8]; /* dword 1 */ | |
270 | u8 lso; /* dword 1 */ | |
271 | u8 cast_enc[2]; /* dword 1 */ | |
272 | u8 rsvd1[5]; /* dword 1 */ | |
273 | u8 rsvd2[32]; /* dword 2 */ | |
274 | u8 pkts[16]; /* dword 3 */ | |
275 | u8 ringid[11]; /* dword 3 */ | |
276 | u8 hash_val[4]; /* dword 3 */ | |
277 | u8 valid; /* dword 3 */ | |
278 | } __packed; | |
279 | ||
280 | struct be_eth_tx_compl { | |
281 | u32 dw[4]; | |
282 | }; | |
283 | ||
284 | /* RX Queue Descriptor */ | |
285 | struct be_eth_rx_d { | |
286 | u32 fragpa_hi; | |
287 | u32 fragpa_lo; | |
288 | }; | |
289 | ||
290 | /* RX Compl Queue Descriptor */ | |
291 | ||
292 | /* Pseudo amap definition for eth_rx_compl in which each bit of the | |
293 | * actual structure is defined as a byte: used to calculate | |
294 | * offset/shift/mask of each field */ | |
295 | struct amap_eth_rx_compl { | |
296 | u8 vlan_tag[16]; /* dword 0 */ | |
297 | u8 pktsize[14]; /* dword 0 */ | |
298 | u8 port; /* dword 0 */ | |
299 | u8 ip_opt; /* dword 0 */ | |
300 | u8 err; /* dword 1 */ | |
301 | u8 rsshp; /* dword 1 */ | |
302 | u8 ipf; /* dword 1 */ | |
303 | u8 tcpf; /* dword 1 */ | |
304 | u8 udpf; /* dword 1 */ | |
305 | u8 ipcksm; /* dword 1 */ | |
306 | u8 l4_cksm; /* dword 1 */ | |
307 | u8 ip_version; /* dword 1 */ | |
308 | u8 macdst[6]; /* dword 1 */ | |
309 | u8 vtp; /* dword 1 */ | |
310 | u8 rsvd0; /* dword 1 */ | |
311 | u8 fragndx[10]; /* dword 1 */ | |
312 | u8 ct[2]; /* dword 1 */ | |
313 | u8 sw; /* dword 1 */ | |
314 | u8 numfrags[3]; /* dword 1 */ | |
315 | u8 rss_flush; /* dword 2 */ | |
316 | u8 cast_enc[2]; /* dword 2 */ | |
84517482 | 317 | u8 vtm; /* dword 2 */ |
6b7c5b94 SP |
318 | u8 rss_bank; /* dword 2 */ |
319 | u8 rsvd1[23]; /* dword 2 */ | |
320 | u8 lro_pkt; /* dword 2 */ | |
321 | u8 rsvd2[2]; /* dword 2 */ | |
322 | u8 valid; /* dword 2 */ | |
323 | u8 rsshash[32]; /* dword 3 */ | |
324 | } __packed; | |
325 | ||
326 | struct be_eth_rx_compl { | |
327 | u32 dw[4]; | |
328 | }; | |
84517482 | 329 | |
9e1453c5 AK |
330 | struct mgmt_hba_attribs { |
331 | u8 flashrom_version_string[32]; | |
332 | u8 manufacturer_name[32]; | |
333 | u32 supported_modes; | |
334 | u32 rsvd0[3]; | |
335 | u8 ncsi_ver_string[12]; | |
336 | u32 default_extended_timeout; | |
337 | u8 controller_model_number[32]; | |
338 | u8 controller_description[64]; | |
339 | u8 controller_serial_number[32]; | |
340 | u8 ip_version_string[32]; | |
341 | u8 firmware_version_string[32]; | |
342 | u8 bios_version_string[32]; | |
343 | u8 redboot_version_string[32]; | |
344 | u8 driver_version_string[32]; | |
345 | u8 fw_on_flash_version_string[32]; | |
346 | u32 functionalities_supported; | |
347 | u16 max_cdblength; | |
348 | u8 asic_revision; | |
349 | u8 generational_guid[16]; | |
350 | u8 hba_port_count; | |
351 | u16 default_link_down_timeout; | |
352 | u8 iscsi_ver_min_max; | |
353 | u8 multifunction_device; | |
354 | u8 cache_valid; | |
355 | u8 hba_status; | |
356 | u8 max_domains_supported; | |
357 | u8 phy_port; | |
358 | u32 firmware_post_status; | |
359 | u32 hba_mtu[8]; | |
360 | u32 rsvd1[4]; | |
361 | }; | |
362 | ||
363 | struct mgmt_controller_attrib { | |
364 | struct mgmt_hba_attribs hba_attribs; | |
365 | u16 pci_vendor_id; | |
366 | u16 pci_device_id; | |
367 | u16 pci_sub_vendor_id; | |
368 | u16 pci_sub_system_id; | |
369 | u8 pci_bus_number; | |
370 | u8 pci_device_number; | |
371 | u8 pci_function_number; | |
372 | u8 interface_type; | |
373 | u64 unique_identifier; | |
374 | u32 rsvd0[5]; | |
375 | }; | |
376 | ||
84517482 AK |
377 | struct controller_id { |
378 | u32 vendor; | |
379 | u32 device; | |
380 | u32 subvendor; | |
381 | u32 subdevice; | |
382 | }; | |
383 | ||
3f0d4560 AK |
384 | struct flash_comp { |
385 | unsigned long offset; | |
386 | int optype; | |
387 | int size; | |
388 | }; | |
389 | ||
390 | struct image_hdr { | |
391 | u32 imageid; | |
392 | u32 imageoffset; | |
393 | u32 imagelength; | |
394 | u32 image_checksum; | |
395 | u8 image_version[32]; | |
396 | }; | |
397 | struct flash_file_hdr_g2 { | |
84517482 AK |
398 | u8 sign[32]; |
399 | u32 cksum; | |
400 | u32 antidote; | |
401 | struct controller_id cont_id; | |
402 | u32 file_len; | |
403 | u32 chunk_num; | |
404 | u32 total_chunks; | |
405 | u32 num_imgs; | |
406 | u8 build[24]; | |
407 | }; | |
408 | ||
3f0d4560 AK |
409 | struct flash_file_hdr_g3 { |
410 | u8 sign[52]; | |
411 | u8 ufi_version[4]; | |
412 | u32 file_len; | |
413 | u32 cksum; | |
414 | u32 antidote; | |
415 | u32 num_imgs; | |
416 | u8 build[24]; | |
417 | u8 rsvd[32]; | |
418 | }; | |
419 | ||
84517482 AK |
420 | struct flash_section_hdr { |
421 | u32 format_rev; | |
422 | u32 cksum; | |
423 | u32 antidote; | |
424 | u32 build_no; | |
425 | u8 id_string[64]; | |
426 | u32 active_entry_mask; | |
427 | u32 valid_entry_mask; | |
428 | u32 org_content_mask; | |
429 | u32 rsvd0; | |
430 | u32 rsvd1; | |
431 | u32 rsvd2; | |
432 | u32 rsvd3; | |
433 | u32 rsvd4; | |
434 | }; | |
435 | ||
436 | struct flash_section_entry { | |
437 | u32 type; | |
438 | u32 offset; | |
439 | u32 pad_size; | |
440 | u32 image_size; | |
441 | u32 cksum; | |
442 | u32 entry_point; | |
443 | u32 rsvd0; | |
444 | u32 rsvd1; | |
445 | u8 ver_data[32]; | |
446 | }; | |
447 | ||
448 | struct flash_section_info { | |
449 | u8 cookie[32]; | |
450 | struct flash_section_hdr fsec_hdr; | |
451 | struct flash_section_entry fsec_entry[32]; | |
452 | }; |