projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
be2net: parse vid and vtm fields of rx-compl only if vlanf bit is set
[deliverable/linux.git] / drivers / net / benet / be_main.c
CommitLineData
6b7c5b94 1/*
d2145cde 2 * Copyright (C) 2005 - 2011 Emulex
6b7c5b94
SP		 3 * All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License version 2
7 * as published by the Free Software Foundation. The full GNU General
8 * Public License is included in this distribution in the file called COPYING.
9 *
10 * Contact Information:
d2145cde 11 * linux-drivers@emulex.com
6b7c5b94 12 *
d2145cde
AK		 13 * Emulex
14 * 3333 Susan Street
15 * Costa Mesa, CA 92626
6b7c5b94
SP		 16 */
17
18#include "be.h"
8788fdc2 19#include "be_cmds.h"
65f71b8b 20#include <asm/div64.h>
6b7c5b94
SP		 21
22MODULE_VERSION(DRV_VER);
23MODULE_DEVICE_TABLE(pci, be_dev_ids);
24MODULE_DESCRIPTION(DRV_DESC " " DRV_VER);
25MODULE_AUTHOR("ServerEngines Corporation");
26MODULE_LICENSE("GPL");
27
2e588f84 28static ushort rx_frag_size = 2048;
ba343c77 29static unsigned int num_vfs;
2e588f84 30module_param(rx_frag_size, ushort, S_IRUGO);
ba343c77 31module_param(num_vfs, uint, S_IRUGO);
6b7c5b94 32MODULE_PARM_DESC(rx_frag_size, "Size of a fragment that holds rcvd data.");
ba343c77 33MODULE_PARM_DESC(num_vfs, "Number of PCI VFs to initialize");
6b7c5b94 34
3abcdeda
SP		 35static bool multi_rxq = true;
36module_param(multi_rxq, bool, S_IRUGO | S_IWUSR);
37MODULE_PARM_DESC(multi_rxq, "Multi Rx Queue support. Enabled by default");
38
6b7c5b94 39static DEFINE_PCI_DEVICE_TABLE(be_dev_ids) = {
c4ca2374 40 { PCI_DEVICE(BE_VENDOR_ID, BE_DEVICE_ID1) },
59fd5d87 41 { PCI_DEVICE(BE_VENDOR_ID, BE_DEVICE_ID2) },
c4ca2374
AK		 42 { PCI_DEVICE(BE_VENDOR_ID, OC_DEVICE_ID1) },
43 { PCI_DEVICE(BE_VENDOR_ID, OC_DEVICE_ID2) },
fe6d2a38 44 { PCI_DEVICE(EMULEX_VENDOR_ID, OC_DEVICE_ID3)},
6b7c5b94
SP		 45 { 0 }
46};
47MODULE_DEVICE_TABLE(pci, be_dev_ids);
7c185276
AK		 48/* UE Status Low CSR */
49static char *ue_status_low_desc[] = {
50 "CEV",
51 "CTX",
52 "DBUF",
53 "ERX",
54 "Host",
55 "MPU",
56 "NDMA",
57 "PTC ",
58 "RDMA ",
59 "RXF ",
60 "RXIPS ",
61 "RXULP0 ",
62 "RXULP1 ",
63 "RXULP2 ",
64 "TIM ",
65 "TPOST ",
66 "TPRE ",
67 "TXIPS ",
68 "TXULP0 ",
69 "TXULP1 ",
70 "UC ",
71 "WDMA ",
72 "TXULP2 ",
73 "HOST1 ",
74 "P0_OB_LINK ",
75 "P1_OB_LINK ",
76 "HOST_GPIO ",
77 "MBOX ",
78 "AXGMAC0",
79 "AXGMAC1",
80 "JTAG",
81 "MPU_INTPEND"
82};
83/* UE Status High CSR */
84static char *ue_status_hi_desc[] = {
85 "LPCMEMHOST",
86 "MGMT_MAC",
87 "PCS0ONLINE",
88 "MPU_IRAM",
89 "PCS1ONLINE",
90 "PCTL0",
91 "PCTL1",
92 "PMEM",
93 "RR",
94 "TXPB",
95 "RXPP",
96 "XAUI",
97 "TXP",
98 "ARM",
99 "IPC",
100 "HOST2",
101 "HOST3",
102 "HOST4",
103 "HOST5",
104 "HOST6",
105 "HOST7",
106 "HOST8",
107 "HOST9",
108 "NETC"
109 "Unknown",
110 "Unknown",
111 "Unknown",
112 "Unknown",
113 "Unknown",
114 "Unknown",
115 "Unknown",
116 "Unknown"
117};
6b7c5b94 118
3abcdeda
SP		 119static inline bool be_multi_rxq(struct be_adapter *adapter)
120{
121 return (adapter->num_rx_qs > 1);
122}
123
6b7c5b94
SP		 124static void be_queue_free(struct be_adapter *adapter, struct be_queue_info *q)
125{
126 struct be_dma_mem *mem = &q->dma_mem;
127 if (mem->va)
2b7bcebf
IV		 128 dma_free_coherent(&adapter->pdev->dev, mem->size, mem->va,
129 mem->dma);
6b7c5b94
SP		 130}
131
132static int be_queue_alloc(struct be_adapter *adapter, struct be_queue_info *q,
133 u16 len, u16 entry_size)
134{
135 struct be_dma_mem *mem = &q->dma_mem;
136
137 memset(q, 0, sizeof(*q));
138 q->len = len;
139 q->entry_size = entry_size;
140 mem->size = len * entry_size;
2b7bcebf
IV		 141 mem->va = dma_alloc_coherent(&adapter->pdev->dev, mem->size, &mem->dma,
142 GFP_KERNEL);
6b7c5b94
SP		 143 if (!mem->va)
144 return -1;
145 memset(mem->va, 0, mem->size);
146 return 0;
147}
148
8788fdc2 149static void be_intr_set(struct be_adapter *adapter, bool enable)
6b7c5b94 150{
8788fdc2 151 u8 __iomem *addr = adapter->pcicfg + PCICFG_MEMBAR_CTRL_INT_CTRL_OFFSET;
6b7c5b94
SP		 152 u32 reg = ioread32(addr);
153 u32 enabled = reg & MEMBAR_CTRL_INT_CTRL_HOSTINTR_MASK;
5f0b849e 154
cf588477
SP		 155 if (adapter->eeh_err)
156 return;
157
5f0b849e 158 if (!enabled && enable)
6b7c5b94 159 reg |= MEMBAR_CTRL_INT_CTRL_HOSTINTR_MASK;
5f0b849e 160 else if (enabled && !enable)
6b7c5b94 161 reg &= ~MEMBAR_CTRL_INT_CTRL_HOSTINTR_MASK;
5f0b849e 162 else
6b7c5b94 163 return;
5f0b849e 164
6b7c5b94
SP		 165 iowrite32(reg, addr);
166}
167
8788fdc2 168static void be_rxq_notify(struct be_adapter *adapter, u16 qid, u16 posted)
6b7c5b94
SP		 169{
170 u32 val = 0;
171 val |= qid & DB_RQ_RING_ID_MASK;
172 val |= posted << DB_RQ_NUM_POSTED_SHIFT;
f3eb62d2
SP		 173
174 wmb();
8788fdc2 175 iowrite32(val, adapter->db + DB_RQ_OFFSET);
6b7c5b94
SP		 176}
177
8788fdc2 178static void be_txq_notify(struct be_adapter *adapter, u16 qid, u16 posted)
6b7c5b94
SP		 179{
180 u32 val = 0;
181 val |= qid & DB_TXULP_RING_ID_MASK;
182 val |= (posted & DB_TXULP_NUM_POSTED_MASK) << DB_TXULP_NUM_POSTED_SHIFT;
f3eb62d2
SP		 183
184 wmb();
8788fdc2 185 iowrite32(val, adapter->db + DB_TXULP1_OFFSET);
6b7c5b94
SP		 186}
187
8788fdc2 188static void be_eq_notify(struct be_adapter *adapter, u16 qid,
6b7c5b94
SP		 189 bool arm, bool clear_int, u16 num_popped)
190{
191 u32 val = 0;
192 val |= qid & DB_EQ_RING_ID_MASK;
fe6d2a38
SP		 193 val |= ((qid & DB_EQ_RING_ID_EXT_MASK) <<
194 DB_EQ_RING_ID_EXT_MASK_SHIFT);
cf588477
SP		 195
196 if (adapter->eeh_err)
197 return;
198
6b7c5b94
SP		 199 if (arm)
200 val |= 1 << DB_EQ_REARM_SHIFT;
201 if (clear_int)
202 val |= 1 << DB_EQ_CLR_SHIFT;
203 val |= 1 << DB_EQ_EVNT_SHIFT;
204 val |= num_popped << DB_EQ_NUM_POPPED_SHIFT;
8788fdc2 205 iowrite32(val, adapter->db + DB_EQ_OFFSET);
6b7c5b94
SP		 206}
207
8788fdc2 208void be_cq_notify(struct be_adapter *adapter, u16 qid, bool arm, u16 num_popped)
6b7c5b94
SP		 209{
210 u32 val = 0;
211 val |= qid & DB_CQ_RING_ID_MASK;
fe6d2a38
SP		 212 val |= ((qid & DB_CQ_RING_ID_EXT_MASK) <<
213 DB_CQ_RING_ID_EXT_MASK_SHIFT);
cf588477
SP		 214
215 if (adapter->eeh_err)
216 return;
217
6b7c5b94
SP		 218 if (arm)
219 val |= 1 << DB_CQ_REARM_SHIFT;
220 val |= num_popped << DB_CQ_NUM_POPPED_SHIFT;
8788fdc2 221 iowrite32(val, adapter->db + DB_CQ_OFFSET);
6b7c5b94
SP		 222}
223
6b7c5b94
SP		 224static int be_mac_addr_set(struct net_device *netdev, void *p)
225{
226 struct be_adapter *adapter = netdev_priv(netdev);
227 struct sockaddr *addr = p;
228 int status = 0;
229
ca9e4988
AK		 230 if (!is_valid_ether_addr(addr->sa_data))
231 return -EADDRNOTAVAIL;
232
ba343c77
SB		 233 /* MAC addr configuration will be done in hardware for VFs
234 * by their corresponding PFs. Just copy to netdev addr here
235 */
236 if (!be_physfn(adapter))
237 goto netdev_addr;
238
f8617e08
AK		 239 status = be_cmd_pmac_del(adapter, adapter->if_handle,
240 adapter->pmac_id, 0);
a65027e4
SP		 241 if (status)
242 return status;
6b7c5b94 243
a65027e4 244 status = be_cmd_pmac_add(adapter, (u8 *)addr->sa_data,
f8617e08 245 adapter->if_handle, &adapter->pmac_id, 0);
ba343c77 246netdev_addr:
6b7c5b94
SP		 247 if (!status)
248 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
249
250 return status;
251}
252
b31c50a7 253void netdev_stats_update(struct be_adapter *adapter)
6b7c5b94 254{
3abcdeda 255 struct be_hw_stats *hw_stats = hw_stats_from_cmd(adapter->stats_cmd.va);
6b7c5b94
SP		 256 struct be_rxf_stats *rxf_stats = &hw_stats->rxf;
257 struct be_port_rxf_stats *port_stats =
258 &rxf_stats->port[adapter->port_num];
78122a52 259 struct net_device_stats *dev_stats = &adapter->netdev->stats;
68110868 260 struct be_erx_stats *erx_stats = &hw_stats->erx;
3abcdeda
SP		 261 struct be_rx_obj *rxo;
262 int i;
6b7c5b94 263
3abcdeda
SP		 264 memset(dev_stats, 0, sizeof(*dev_stats));
265 for_all_rx_queues(adapter, rxo, i) {
266 dev_stats->rx_packets += rx_stats(rxo)->rx_pkts;
267 dev_stats->rx_bytes += rx_stats(rxo)->rx_bytes;
268 dev_stats->multicast += rx_stats(rxo)->rx_mcast_pkts;
269 /* no space in linux buffers: best possible approximation */
270 dev_stats->rx_dropped +=
271 erx_stats->rx_drops_no_fragments[rxo->q.id];
272 }
273
274 dev_stats->tx_packets = tx_stats(adapter)->be_tx_pkts;
275 dev_stats->tx_bytes = tx_stats(adapter)->be_tx_bytes;
6b7c5b94
SP		 276
277 /* bad pkts received */
278 dev_stats->rx_errors = port_stats->rx_crc_errors +
279 port_stats->rx_alignment_symbol_errors +
280 port_stats->rx_in_range_errors +
68110868
SP		 281 port_stats->rx_out_range_errors +
282 port_stats->rx_frame_too_long +
283 port_stats->rx_dropped_too_small +
284 port_stats->rx_dropped_too_short +
285 port_stats->rx_dropped_header_too_small +
286 port_stats->rx_dropped_tcp_length +
287 port_stats->rx_dropped_runt +
288 port_stats->rx_tcp_checksum_errs +
289 port_stats->rx_ip_checksum_errs +
290 port_stats->rx_udp_checksum_errs;
291
6b7c5b94
SP		 292 /* detailed rx errors */
293 dev_stats->rx_length_errors = port_stats->rx_in_range_errors +
68110868
SP		 294 port_stats->rx_out_range_errors +
295 port_stats->rx_frame_too_long;
296
6b7c5b94
SP		 297 dev_stats->rx_crc_errors = port_stats->rx_crc_errors;
298
299 /* frame alignment errors */
300 dev_stats->rx_frame_errors = port_stats->rx_alignment_symbol_errors;
68110868 301
6b7c5b94
SP		 302 /* receiver fifo overrun */
303 /* drops_no_pbuf is no per i/f, it's per BE card */
304 dev_stats->rx_fifo_errors = port_stats->rx_fifo_overflow +
305 port_stats->rx_input_fifo_overflow +
306 rxf_stats->rx_drops_no_pbuf;
6b7c5b94
SP		 307}
308
8788fdc2 309void be_link_status_update(struct be_adapter *adapter, bool link_up)
6b7c5b94 310{
6b7c5b94
SP		 311 struct net_device *netdev = adapter->netdev;
312
6b7c5b94 313 /* If link came up or went down */
a8f447bd 314 if (adapter->link_up != link_up) {
0dffc83e 315 adapter->link_speed = -1;
a8f447bd 316 if (link_up) {
6b7c5b94
SP		 317 netif_carrier_on(netdev);
318 printk(KERN_INFO "%s: Link up\n", netdev->name);
a8f447bd 319 } else {
a8f447bd
SP		 320 netif_carrier_off(netdev);
321 printk(KERN_INFO "%s: Link down\n", netdev->name);
6b7c5b94 322 }
a8f447bd 323 adapter->link_up = link_up;
6b7c5b94 324 }
6b7c5b94
SP		 325}
326
327/* Update the EQ delay n BE based on the RX frags consumed / sec */
3abcdeda 328static void be_rx_eqd_update(struct be_adapter *adapter, struct be_rx_obj *rxo)
6b7c5b94 329{
3abcdeda
SP		 330 struct be_eq_obj *rx_eq = &rxo->rx_eq;
331 struct be_rx_stats *stats = &rxo->stats;
4097f663
SP		 332 ulong now = jiffies;
333 u32 eqd;
334
335 if (!rx_eq->enable_aic)
336 return;
337
338 /* Wrapped around */
339 if (time_before(now, stats->rx_fps_jiffies)) {
340 stats->rx_fps_jiffies = now;
341 return;
342 }
6b7c5b94
SP		 343
344 /* Update once a second */
4097f663 345 if ((now - stats->rx_fps_jiffies) < HZ)
6b7c5b94
SP		 346 return;
347
3abcdeda 348 stats->rx_fps = (stats->rx_frags - stats->prev_rx_frags) /
4097f663 349 ((now - stats->rx_fps_jiffies) / HZ);
6b7c5b94 350
4097f663 351 stats->rx_fps_jiffies = now;
3abcdeda
SP		 352 stats->prev_rx_frags = stats->rx_frags;
353 eqd = stats->rx_fps / 110000;
6b7c5b94
SP		 354 eqd = eqd << 3;
355 if (eqd > rx_eq->max_eqd)
356 eqd = rx_eq->max_eqd;
357 if (eqd < rx_eq->min_eqd)
358 eqd = rx_eq->min_eqd;
359 if (eqd < 10)
360 eqd = 0;
361 if (eqd != rx_eq->cur_eqd)
8788fdc2 362 be_cmd_modify_eqd(adapter, rx_eq->q.id, eqd);
6b7c5b94
SP		 363
364 rx_eq->cur_eqd = eqd;
365}
366
65f71b8b
SH		 367static u32 be_calc_rate(u64 bytes, unsigned long ticks)
368{
369 u64 rate = bytes;
370
371 do_div(rate, ticks / HZ);
372 rate <<= 3; /* bytes/sec -> bits/sec */
373 do_div(rate, 1000000ul); /* MB/Sec */
374
375 return rate;
376}
377
4097f663
SP		 378static void be_tx_rate_update(struct be_adapter *adapter)
379{
3abcdeda 380 struct be_tx_stats *stats = tx_stats(adapter);
4097f663
SP		 381 ulong now = jiffies;
382
383 /* Wrapped around? */
384 if (time_before(now, stats->be_tx_jiffies)) {
385 stats->be_tx_jiffies = now;
386 return;
387 }
388
389 /* Update tx rate once in two seconds */
390 if ((now - stats->be_tx_jiffies) > 2 * HZ) {
65f71b8b
SH		 391 stats->be_tx_rate = be_calc_rate(stats->be_tx_bytes
392 - stats->be_tx_bytes_prev,
393 now - stats->be_tx_jiffies);
4097f663
SP		 394 stats->be_tx_jiffies = now;
395 stats->be_tx_bytes_prev = stats->be_tx_bytes;
396 }
397}
398
6b7c5b94 399static void be_tx_stats_update(struct be_adapter *adapter,
91992e44 400 u32 wrb_cnt, u32 copied, u32 gso_segs, bool stopped)
6b7c5b94 401{
3abcdeda 402 struct be_tx_stats *stats = tx_stats(adapter);
6b7c5b94
SP		 403 stats->be_tx_reqs++;
404 stats->be_tx_wrbs += wrb_cnt;
405 stats->be_tx_bytes += copied;
91992e44 406 stats->be_tx_pkts += (gso_segs ? gso_segs : 1);
6b7c5b94
SP		 407 if (stopped)
408 stats->be_tx_stops++;
6b7c5b94
SP		 409}
410
411/* Determine number of WRB entries needed to xmit data in an skb */
fe6d2a38
SP		 412static u32 wrb_cnt_for_skb(struct be_adapter *adapter, struct sk_buff *skb,
413 bool *dummy)
6b7c5b94 414{
ebc8d2ab
DM		 415 int cnt = (skb->len > skb->data_len);
416
417 cnt += skb_shinfo(skb)->nr_frags;
418
6b7c5b94
SP		 419 /* to account for hdr wrb */
420 cnt++;
fe6d2a38
SP		 421 if (lancer_chip(adapter) || !(cnt & 1)) {
422 *dummy = false;
423 } else {
6b7c5b94
SP		 424 /* add a dummy to make it an even num */
425 cnt++;
426 *dummy = true;
fe6d2a38 427 }
6b7c5b94
SP		 428 BUG_ON(cnt > BE_MAX_TX_FRAG_COUNT);
429 return cnt;
430}
431
432static inline void wrb_fill(struct be_eth_wrb *wrb, u64 addr, int len)
433{
434 wrb->frag_pa_hi = upper_32_bits(addr);
435 wrb->frag_pa_lo = addr & 0xFFFFFFFF;
436 wrb->frag_len = len & ETH_WRB_FRAG_LEN_MASK;
437}
438
cc4ce020
SK		 439static void wrb_fill_hdr(struct be_adapter *adapter, struct be_eth_hdr_wrb *hdr,
440 struct sk_buff *skb, u32 wrb_cnt, u32 len)
6b7c5b94 441{
cc4ce020
SK		 442 u8 vlan_prio = 0;
443 u16 vlan_tag = 0;
444
6b7c5b94
SP		 445 memset(hdr, 0, sizeof(*hdr));
446
447 AMAP_SET_BITS(struct amap_eth_hdr_wrb, crc, hdr, 1);
448
49e4b847 449 if (skb_is_gso(skb)) {
6b7c5b94
SP		 450 AMAP_SET_BITS(struct amap_eth_hdr_wrb, lso, hdr, 1);
451 AMAP_SET_BITS(struct amap_eth_hdr_wrb, lso_mss,
452 hdr, skb_shinfo(skb)->gso_size);
fe6d2a38 453 if (skb_is_gso_v6(skb) && !lancer_chip(adapter))
49e4b847 454 AMAP_SET_BITS(struct amap_eth_hdr_wrb, lso6, hdr, 1);
fe6d2a38
SP		 455 if (lancer_chip(adapter) && adapter->sli_family ==
456 LANCER_A0_SLI_FAMILY) {
457 AMAP_SET_BITS(struct amap_eth_hdr_wrb, ipcs, hdr, 1);
458 if (is_tcp_pkt(skb))
459 AMAP_SET_BITS(struct amap_eth_hdr_wrb,
460 tcpcs, hdr, 1);
461 else if (is_udp_pkt(skb))
462 AMAP_SET_BITS(struct amap_eth_hdr_wrb,
463 udpcs, hdr, 1);
464 }
6b7c5b94
SP		 465 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
466 if (is_tcp_pkt(skb))
467 AMAP_SET_BITS(struct amap_eth_hdr_wrb, tcpcs, hdr, 1);
468 else if (is_udp_pkt(skb))
469 AMAP_SET_BITS(struct amap_eth_hdr_wrb, udpcs, hdr, 1);
470 }
471
cc4ce020 472 if (adapter->vlan_grp && vlan_tx_tag_present(skb)) {
6b7c5b94 473 AMAP_SET_BITS(struct amap_eth_hdr_wrb, vlan, hdr, 1);
cc4ce020
SK		 474 vlan_tag = vlan_tx_tag_get(skb);
475 vlan_prio = (vlan_tag & VLAN_PRIO_MASK) >> VLAN_PRIO_SHIFT;
476 /* If vlan priority provided by OS is NOT in available bmap */
477 if (!(adapter->vlan_prio_bmap & (1 << vlan_prio)))
478 vlan_tag = (vlan_tag & ~VLAN_PRIO_MASK) |
479 adapter->recommended_prio;
480 AMAP_SET_BITS(struct amap_eth_hdr_wrb, vlan_tag, hdr, vlan_tag);
6b7c5b94
SP		 481 }
482
483 AMAP_SET_BITS(struct amap_eth_hdr_wrb, event, hdr, 1);
484 AMAP_SET_BITS(struct amap_eth_hdr_wrb, complete, hdr, 1);
485 AMAP_SET_BITS(struct amap_eth_hdr_wrb, num_wrb, hdr, wrb_cnt);
486 AMAP_SET_BITS(struct amap_eth_hdr_wrb, len, hdr, len);
487}
488
2b7bcebf 489static void unmap_tx_frag(struct device *dev, struct be_eth_wrb *wrb,
7101e111
SP		 490 bool unmap_single)
491{
492 dma_addr_t dma;
493
494 be_dws_le_to_cpu(wrb, sizeof(*wrb));
495
496 dma = (u64)wrb->frag_pa_hi << 32 | (u64)wrb->frag_pa_lo;
b681ee77 497 if (wrb->frag_len) {
7101e111 498 if (unmap_single)
2b7bcebf
IV		 499 dma_unmap_single(dev, dma, wrb->frag_len,
500 DMA_TO_DEVICE);
7101e111 501 else
2b7bcebf 502 dma_unmap_page(dev, dma, wrb->frag_len, DMA_TO_DEVICE);
7101e111
SP		 503 }
504}
6b7c5b94
SP		 505
506static int make_tx_wrbs(struct be_adapter *adapter,
507 struct sk_buff *skb, u32 wrb_cnt, bool dummy_wrb)
508{
7101e111
SP		 509 dma_addr_t busaddr;
510 int i, copied = 0;
2b7bcebf 511 struct device *dev = &adapter->pdev->dev;
6b7c5b94
SP		 512 struct sk_buff *first_skb = skb;
513 struct be_queue_info *txq = &adapter->tx_obj.q;
514 struct be_eth_wrb *wrb;
515 struct be_eth_hdr_wrb *hdr;
7101e111
SP		 516 bool map_single = false;
517 u16 map_head;
6b7c5b94 518
6b7c5b94
SP		 519 hdr = queue_head_node(txq);
520 queue_head_inc(txq);
7101e111 521 map_head = txq->head;
6b7c5b94 522
ebc8d2ab 523 if (skb->len > skb->data_len) {
e743d313 524 int len = skb_headlen(skb);
2b7bcebf
IV		 525 busaddr = dma_map_single(dev, skb->data, len, DMA_TO_DEVICE);
526 if (dma_mapping_error(dev, busaddr))
7101e111
SP		 527 goto dma_err;
528 map_single = true;
ebc8d2ab
DM		 529 wrb = queue_head_node(txq);
530 wrb_fill(wrb, busaddr, len);
531 be_dws_cpu_to_le(wrb, sizeof(*wrb));
532 queue_head_inc(txq);
533 copied += len;
534 }
6b7c5b94 535
ebc8d2ab
DM		 536 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
537 struct skb_frag_struct *frag =
538 &skb_shinfo(skb)->frags[i];
2b7bcebf
IV		 539 busaddr = dma_map_page(dev, frag->page, frag->page_offset,
540 frag->size, DMA_TO_DEVICE);
541 if (dma_mapping_error(dev, busaddr))
7101e111 542 goto dma_err;
ebc8d2ab
DM		 543 wrb = queue_head_node(txq);
544 wrb_fill(wrb, busaddr, frag->size);
545 be_dws_cpu_to_le(wrb, sizeof(*wrb));
546 queue_head_inc(txq);
547 copied += frag->size;
6b7c5b94
SP		 548 }
549
550 if (dummy_wrb) {
551 wrb = queue_head_node(txq);
552 wrb_fill(wrb, 0, 0);
553 be_dws_cpu_to_le(wrb, sizeof(*wrb));
554 queue_head_inc(txq);
555 }
556
cc4ce020 557 wrb_fill_hdr(adapter, hdr, first_skb, wrb_cnt, copied);
6b7c5b94
SP		 558 be_dws_cpu_to_le(hdr, sizeof(*hdr));
559
560 return copied;
7101e111
SP		 561dma_err:
562 txq->head = map_head;
563 while (copied) {
564 wrb = queue_head_node(txq);
2b7bcebf 565 unmap_tx_frag(dev, wrb, map_single);
7101e111
SP		 566 map_single = false;
567 copied -= wrb->frag_len;
568 queue_head_inc(txq);
569 }
570 return 0;
6b7c5b94
SP		 571}
572
61357325 573static netdev_tx_t be_xmit(struct sk_buff *skb,
b31c50a7 574 struct net_device *netdev)
6b7c5b94
SP		 575{
576 struct be_adapter *adapter = netdev_priv(netdev);
577 struct be_tx_obj *tx_obj = &adapter->tx_obj;
578 struct be_queue_info *txq = &tx_obj->q;
579 u32 wrb_cnt = 0, copied = 0;
580 u32 start = txq->head;
581 bool dummy_wrb, stopped = false;
582
fe6d2a38 583 wrb_cnt = wrb_cnt_for_skb(adapter, skb, &dummy_wrb);
6b7c5b94
SP		 584
585 copied = make_tx_wrbs(adapter, skb, wrb_cnt, dummy_wrb);
c190e3c8
AK		 586 if (copied) {
587 /* record the sent skb in the sent_skb table */
588 BUG_ON(tx_obj->sent_skb_list[start]);
589 tx_obj->sent_skb_list[start] = skb;
590
591 /* Ensure txq has space for the next skb; Else stop the queue
592 * *BEFORE* ringing the tx doorbell, so that we serialze the
593 * tx compls of the current transmit which'll wake up the queue
594 */
7101e111 595 atomic_add(wrb_cnt, &txq->used);
c190e3c8
AK		 596 if ((BE_MAX_TX_FRAG_COUNT + atomic_read(&txq->used)) >=
597 txq->len) {
598 netif_stop_queue(netdev);
599 stopped = true;
600 }
6b7c5b94 601
c190e3c8 602 be_txq_notify(adapter, txq->id, wrb_cnt);
6b7c5b94 603
91992e44
AK		 604 be_tx_stats_update(adapter, wrb_cnt, copied,
605 skb_shinfo(skb)->gso_segs, stopped);
c190e3c8
AK		 606 } else {
607 txq->head = start;
608 dev_kfree_skb_any(skb);
6b7c5b94 609 }
6b7c5b94
SP		 610 return NETDEV_TX_OK;
611}
612
613static int be_change_mtu(struct net_device *netdev, int new_mtu)
614{
615 struct be_adapter *adapter = netdev_priv(netdev);
616 if (new_mtu < BE_MIN_MTU ||
34a89b8c
AK		 617 new_mtu > (BE_MAX_JUMBO_FRAME_SIZE -
618 (ETH_HLEN + ETH_FCS_LEN))) {
6b7c5b94
SP		 619 dev_info(&adapter->pdev->dev,
620 "MTU must be between %d and %d bytes\n",
34a89b8c
AK		 621 BE_MIN_MTU,
622 (BE_MAX_JUMBO_FRAME_SIZE - (ETH_HLEN + ETH_FCS_LEN)));
6b7c5b94
SP		 623 return -EINVAL;
624 }
625 dev_info(&adapter->pdev->dev, "MTU changed from %d to %d bytes\n",
626 netdev->mtu, new_mtu);
627 netdev->mtu = new_mtu;
628 return 0;
629}
630
631/*
82903e4b
AK		 632 * A max of 64 (BE_NUM_VLANS_SUPPORTED) vlans can be configured in BE.
633 * If the user configures more, place BE in vlan promiscuous mode.
6b7c5b94 634 */
1da87b7f 635static int be_vid_config(struct be_adapter *adapter, bool vf, u32 vf_num)
6b7c5b94 636{
6b7c5b94
SP		 637 u16 vtag[BE_NUM_VLANS_SUPPORTED];
638 u16 ntags = 0, i;
82903e4b 639 int status = 0;
1da87b7f
AK		 640 u32 if_handle;
641
642 if (vf) {
643 if_handle = adapter->vf_cfg[vf_num].vf_if_handle;
644 vtag[0] = cpu_to_le16(adapter->vf_cfg[vf_num].vf_vlan_tag);
645 status = be_cmd_vlan_config(adapter, if_handle, vtag, 1, 1, 0);
646 }
6b7c5b94 647
82903e4b 648 if (adapter->vlans_added <= adapter->max_vlans) {
6b7c5b94 649 /* Construct VLAN Table to give to HW */
b738127d 650 for (i = 0; i < VLAN_N_VID; i++) {
6b7c5b94
SP		 651 if (adapter->vlan_tag[i]) {
652 vtag[ntags] = cpu_to_le16(i);
653 ntags++;
654 }
655 }
b31c50a7
SP		 656 status = be_cmd_vlan_config(adapter, adapter->if_handle,
657 vtag, ntags, 1, 0);
6b7c5b94 658 } else {
b31c50a7
SP		 659 status = be_cmd_vlan_config(adapter, adapter->if_handle,
660 NULL, 0, 1, 1);
6b7c5b94 661 }
1da87b7f 662
b31c50a7 663 return status;
6b7c5b94
SP		 664}
665
666static void be_vlan_register(struct net_device *netdev, struct vlan_group *grp)
667{
668 struct be_adapter *adapter = netdev_priv(netdev);
6b7c5b94 669
6b7c5b94 670 adapter->vlan_grp = grp;
6b7c5b94
SP		 671}
672
673static void be_vlan_add_vid(struct net_device *netdev, u16 vid)
674{
675 struct be_adapter *adapter = netdev_priv(netdev);
676
1da87b7f 677 adapter->vlans_added++;
ba343c77
SB		 678 if (!be_physfn(adapter))
679 return;
680
6b7c5b94 681 adapter->vlan_tag[vid] = 1;
82903e4b 682 if (adapter->vlans_added <= (adapter->max_vlans + 1))
1da87b7f 683 be_vid_config(adapter, false, 0);
6b7c5b94
SP		 684}
685
686static void be_vlan_rem_vid(struct net_device *netdev, u16 vid)
687{
688 struct be_adapter *adapter = netdev_priv(netdev);
689
1da87b7f
AK		 690 adapter->vlans_added--;
691 vlan_group_set_device(adapter->vlan_grp, vid, NULL);
692
ba343c77
SB		 693 if (!be_physfn(adapter))
694 return;
695
6b7c5b94 696 adapter->vlan_tag[vid] = 0;
82903e4b 697 if (adapter->vlans_added <= adapter->max_vlans)
1da87b7f 698 be_vid_config(adapter, false, 0);
6b7c5b94
SP		 699}
700
24307eef 701static void be_set_multicast_list(struct net_device *netdev)
6b7c5b94
SP		 702{
703 struct be_adapter *adapter = netdev_priv(netdev);
6b7c5b94 704
24307eef 705 if (netdev->flags & IFF_PROMISC) {
8788fdc2 706 be_cmd_promiscuous_config(adapter, adapter->port_num, 1);
24307eef
SP		 707 adapter->promiscuous = true;
708 goto done;
6b7c5b94
SP		 709 }
710
24307eef
SP		 711 /* BE was previously in promiscous mode; disable it */
712 if (adapter->promiscuous) {
713 adapter->promiscuous = false;
8788fdc2 714 be_cmd_promiscuous_config(adapter, adapter->port_num, 0);
6b7c5b94
SP		 715 }
716
e7b909a6 717 /* Enable multicast promisc if num configured exceeds what we support */
4cd24eaf
JP		 718 if (netdev->flags & IFF_ALLMULTI ||
719 netdev_mc_count(netdev) > BE_MAX_MC) {
0ddf477b 720 be_cmd_multicast_set(adapter, adapter->if_handle, NULL,
e7b909a6 721 &adapter->mc_cmd_mem);
24307eef 722 goto done;
6b7c5b94 723 }
6b7c5b94 724
0ddf477b 725 be_cmd_multicast_set(adapter, adapter->if_handle, netdev,
f31e50a8 726 &adapter->mc_cmd_mem);
24307eef
SP		 727done:
728 return;
6b7c5b94
SP		 729}
730
ba343c77
SB		 731static int be_set_vf_mac(struct net_device *netdev, int vf, u8 *mac)
732{
733 struct be_adapter *adapter = netdev_priv(netdev);
734 int status;
735
736 if (!adapter->sriov_enabled)
737 return -EPERM;
738
739 if (!is_valid_ether_addr(mac) || (vf >= num_vfs))
740 return -EINVAL;
741
64600ea5
AK		 742 if (adapter->vf_cfg[vf].vf_pmac_id != BE_INVALID_PMAC_ID)
743 status = be_cmd_pmac_del(adapter,
744 adapter->vf_cfg[vf].vf_if_handle,
f8617e08 745 adapter->vf_cfg[vf].vf_pmac_id, vf + 1);
ba343c77 746
64600ea5
AK		 747 status = be_cmd_pmac_add(adapter, mac,
748 adapter->vf_cfg[vf].vf_if_handle,
f8617e08 749 &adapter->vf_cfg[vf].vf_pmac_id, vf + 1);
64600ea5
AK		 750
751 if (status)
ba343c77
SB		 752 dev_err(&adapter->pdev->dev, "MAC %pM set on VF %d Failed\n",
753 mac, vf);
64600ea5
AK		 754 else
755 memcpy(adapter->vf_cfg[vf].vf_mac_addr, mac, ETH_ALEN);
756
ba343c77
SB		 757 return status;
758}
759
64600ea5
AK		 760static int be_get_vf_config(struct net_device *netdev, int vf,
761 struct ifla_vf_info *vi)
762{
763 struct be_adapter *adapter = netdev_priv(netdev);
764
765 if (!adapter->sriov_enabled)
766 return -EPERM;
767
768 if (vf >= num_vfs)
769 return -EINVAL;
770
771 vi->vf = vf;
e1d18735 772 vi->tx_rate = adapter->vf_cfg[vf].vf_tx_rate;
1da87b7f 773 vi->vlan = adapter->vf_cfg[vf].vf_vlan_tag;
64600ea5
AK		 774 vi->qos = 0;
775 memcpy(&vi->mac, adapter->vf_cfg[vf].vf_mac_addr, ETH_ALEN);
776
777 return 0;
778}
779
1da87b7f
AK		 780static int be_set_vf_vlan(struct net_device *netdev,
781 int vf, u16 vlan, u8 qos)
782{
783 struct be_adapter *adapter = netdev_priv(netdev);
784 int status = 0;
785
786 if (!adapter->sriov_enabled)
787 return -EPERM;
788
789 if ((vf >= num_vfs) || (vlan > 4095))
790 return -EINVAL;
791
792 if (vlan) {
793 adapter->vf_cfg[vf].vf_vlan_tag = vlan;
794 adapter->vlans_added++;
795 } else {
796 adapter->vf_cfg[vf].vf_vlan_tag = 0;
797 adapter->vlans_added--;
798 }
799
800 status = be_vid_config(adapter, true, vf);
801
802 if (status)
803 dev_info(&adapter->pdev->dev,
804 "VLAN %d config on VF %d failed\n", vlan, vf);
805 return status;
806}
807
e1d18735
AK		 808static int be_set_vf_tx_rate(struct net_device *netdev,
809 int vf, int rate)
810{
811 struct be_adapter *adapter = netdev_priv(netdev);
812 int status = 0;
813
814 if (!adapter->sriov_enabled)
815 return -EPERM;
816
817 if ((vf >= num_vfs) || (rate < 0))
818 return -EINVAL;
819
820 if (rate > 10000)
821 rate = 10000;
822
823 adapter->vf_cfg[vf].vf_tx_rate = rate;
856c4012 824 status = be_cmd_set_qos(adapter, rate / 10, vf + 1);
e1d18735
AK		 825
826 if (status)
827 dev_info(&adapter->pdev->dev,
828 "tx rate %d on VF %d failed\n", rate, vf);
829 return status;
830}
831
3abcdeda 832static void be_rx_rate_update(struct be_rx_obj *rxo)
6b7c5b94 833{
3abcdeda 834 struct be_rx_stats *stats = &rxo->stats;
4097f663 835 ulong now = jiffies;
6b7c5b94 836
4097f663 837 /* Wrapped around */
3abcdeda
SP		 838 if (time_before(now, stats->rx_jiffies)) {
839 stats->rx_jiffies = now;
4097f663
SP		 840 return;
841 }
6b7c5b94
SP		 842
843 /* Update the rate once in two seconds */
3abcdeda 844 if ((now - stats->rx_jiffies) < 2 * HZ)
6b7c5b94
SP		 845 return;
846
3abcdeda
SP		 847 stats->rx_rate = be_calc_rate(stats->rx_bytes - stats->rx_bytes_prev,
848 now - stats->rx_jiffies);
849 stats->rx_jiffies = now;
850 stats->rx_bytes_prev = stats->rx_bytes;
6b7c5b94
SP		 851}
852
3abcdeda 853static void be_rx_stats_update(struct be_rx_obj *rxo,
2e588f84 854 struct be_rx_compl_info *rxcp)
4097f663 855{
3abcdeda 856 struct be_rx_stats *stats = &rxo->stats;
1ef78abe 857
3abcdeda 858 stats->rx_compl++;
2e588f84
SP		 859 stats->rx_frags += rxcp->num_rcvd;
860 stats->rx_bytes += rxcp->pkt_size;
3abcdeda 861 stats->rx_pkts++;
2e588f84 862 if (rxcp->pkt_type == BE_MULTICAST_PACKET)
3abcdeda 863 stats->rx_mcast_pkts++;
2e588f84
SP		 864 if (rxcp->err)
865 stats->rxcp_err++;
4097f663
SP		 866}
867
2e588f84 868static inline bool csum_passed(struct be_rx_compl_info *rxcp)
728a9972 869{
19fad86f
PR		 870 /* L4 checksum is not reliable for non TCP/UDP packets.
871 * Also ignore ipcksm for ipv6 pkts */
2e588f84
SP		 872 return (rxcp->tcpf || rxcp->udpf) && rxcp->l4_csum &&
873 (rxcp->ip_csum || rxcp->ipv6);
728a9972
AK		 874}
875
6b7c5b94 876static struct be_rx_page_info *
3abcdeda
SP		 877get_rx_page_info(struct be_adapter *adapter,
878 struct be_rx_obj *rxo,
879 u16 frag_idx)
6b7c5b94
SP		 880{
881 struct be_rx_page_info *rx_page_info;
3abcdeda 882 struct be_queue_info *rxq = &rxo->q;
6b7c5b94 883
3abcdeda 884 rx_page_info = &rxo->page_info_tbl[frag_idx];
6b7c5b94
SP		 885 BUG_ON(!rx_page_info->page);
886
205859a2 887 if (rx_page_info->last_page_user) {
2b7bcebf
IV		 888 dma_unmap_page(&adapter->pdev->dev,
889 dma_unmap_addr(rx_page_info, bus),
890 adapter->big_page_size, DMA_FROM_DEVICE);
205859a2
AK		 891 rx_page_info->last_page_user = false;
892 }
6b7c5b94
SP		 893
894 atomic_dec(&rxq->used);
895 return rx_page_info;
896}
897
898/* Throwaway the data in the Rx completion */
899static void be_rx_compl_discard(struct be_adapter *adapter,
3abcdeda 900 struct be_rx_obj *rxo,
2e588f84 901 struct be_rx_compl_info *rxcp)
6b7c5b94 902{
3abcdeda 903 struct be_queue_info *rxq = &rxo->q;
6b7c5b94 904 struct be_rx_page_info *page_info;
2e588f84 905 u16 i, num_rcvd = rxcp->num_rcvd;
6b7c5b94 906
e80d9da6 907 for (i = 0; i < num_rcvd; i++) {
2e588f84 908 page_info = get_rx_page_info(adapter, rxo, rxcp->rxq_idx);
e80d9da6
PR		 909 put_page(page_info->page);
910 memset(page_info, 0, sizeof(*page_info));
2e588f84 911 index_inc(&rxcp->rxq_idx, rxq->len);
6b7c5b94
SP		 912 }
913}
914
915/*
916 * skb_fill_rx_data forms a complete skb for an ether frame
917 * indicated by rxcp.
918 */
3abcdeda 919static void skb_fill_rx_data(struct be_adapter *adapter, struct be_rx_obj *rxo,
2e588f84 920 struct sk_buff *skb, struct be_rx_compl_info *rxcp)
6b7c5b94 921{
3abcdeda 922 struct be_queue_info *rxq = &rxo->q;
6b7c5b94 923 struct be_rx_page_info *page_info;
2e588f84
SP		 924 u16 i, j;
925 u16 hdr_len, curr_frag_len, remaining;
6b7c5b94 926 u8 *start;
6b7c5b94 927
2e588f84 928 page_info = get_rx_page_info(adapter, rxo, rxcp->rxq_idx);
6b7c5b94
SP		 929 start = page_address(page_info->page) + page_info->page_offset;
930 prefetch(start);
931
932 /* Copy data in the first descriptor of this completion */
2e588f84 933 curr_frag_len = min(rxcp->pkt_size, rx_frag_size);
6b7c5b94
SP		 934
935 /* Copy the header portion into skb_data */
2e588f84 936 hdr_len = min(BE_HDR_LEN, curr_frag_len);
6b7c5b94
SP		 937 memcpy(skb->data, start, hdr_len);
938 skb->len = curr_frag_len;
939 if (curr_frag_len <= BE_HDR_LEN) { /* tiny packet */
940 /* Complete packet has now been moved to data */
941 put_page(page_info->page);
942 skb->data_len = 0;
943 skb->tail += curr_frag_len;
944 } else {
945 skb_shinfo(skb)->nr_frags = 1;
946 skb_shinfo(skb)->frags[0].page = page_info->page;
947 skb_shinfo(skb)->frags[0].page_offset =
948 page_info->page_offset + hdr_len;
949 skb_shinfo(skb)->frags[0].size = curr_frag_len - hdr_len;
950 skb->data_len = curr_frag_len - hdr_len;
951 skb->tail += hdr_len;
952 }
205859a2 953 page_info->page = NULL;
6b7c5b94 954
2e588f84
SP		 955 if (rxcp->pkt_size <= rx_frag_size) {
956 BUG_ON(rxcp->num_rcvd != 1);
957 return;
6b7c5b94
SP		 958 }
959
960 /* More frags present for this completion */
2e588f84
SP		 961 index_inc(&rxcp->rxq_idx, rxq->len);
962 remaining = rxcp->pkt_size - curr_frag_len;
963 for (i = 1, j = 0; i < rxcp->num_rcvd; i++) {
964 page_info = get_rx_page_info(adapter, rxo, rxcp->rxq_idx);
965 curr_frag_len = min(remaining, rx_frag_size);
6b7c5b94 966
bd46cb6c
AK		 967 /* Coalesce all frags from the same physical page in one slot */
968 if (page_info->page_offset == 0) {
969 /* Fresh page */
970 j++;
971 skb_shinfo(skb)->frags[j].page = page_info->page;
972 skb_shinfo(skb)->frags[j].page_offset =
973 page_info->page_offset;
974 skb_shinfo(skb)->frags[j].size = 0;
975 skb_shinfo(skb)->nr_frags++;
976 } else {
977 put_page(page_info->page);
978 }
979
980 skb_shinfo(skb)->frags[j].size += curr_frag_len;
6b7c5b94
SP		 981 skb->len += curr_frag_len;
982 skb->data_len += curr_frag_len;
6b7c5b94 983
2e588f84
SP		 984 remaining -= curr_frag_len;
985 index_inc(&rxcp->rxq_idx, rxq->len);
205859a2 986 page_info->page = NULL;
6b7c5b94 987 }
bd46cb6c 988 BUG_ON(j > MAX_SKB_FRAGS);
6b7c5b94
SP		 989}
990
5be93b9a 991/* Process the RX completion indicated by rxcp when GRO is disabled */
6b7c5b94 992static void be_rx_compl_process(struct be_adapter *adapter,
3abcdeda 993 struct be_rx_obj *rxo,
2e588f84 994 struct be_rx_compl_info *rxcp)
6b7c5b94
SP		 995{
996 struct sk_buff *skb;
89420424 997
89d71a66 998 skb = netdev_alloc_skb_ip_align(adapter->netdev, BE_HDR_LEN);
a058a632 999 if (unlikely(!skb)) {
6b7c5b94
SP		 1000 if (net_ratelimit())
1001 dev_warn(&adapter->pdev->dev, "skb alloc failed\n");
3abcdeda 1002 be_rx_compl_discard(adapter, rxo, rxcp);
6b7c5b94
SP		 1003 return;
1004 }
1005
2e588f84 1006 skb_fill_rx_data(adapter, rxo, skb, rxcp);
6b7c5b94 1007
c6ce2f4b 1008 if (likely(adapter->rx_csum && csum_passed(rxcp)))
728a9972 1009 skb->ip_summed = CHECKSUM_UNNECESSARY;
c6ce2f4b
SK		 1010 else
1011 skb_checksum_none_assert(skb);
6b7c5b94
SP		 1012
1013 skb->truesize = skb->len + sizeof(struct sk_buff);
1014 skb->protocol = eth_type_trans(skb, adapter->netdev);
6b7c5b94 1015
2e588f84 1016 if (unlikely(rxcp->vlanf)) {
82903e4b 1017 if (!adapter->vlan_grp || adapter->vlans_added == 0) {
6b7c5b94
SP		 1018 kfree_skb(skb);
1019 return;
1020 }
2e588f84 1021 vlan_hwaccel_receive_skb(skb, adapter->vlan_grp, rxcp->vid);
6b7c5b94
SP		 1022 } else {
1023 netif_receive_skb(skb);
1024 }
6b7c5b94
SP		 1025}
1026
5be93b9a
AK		 1027/* Process the RX completion indicated by rxcp when GRO is enabled */
1028static void be_rx_compl_process_gro(struct be_adapter *adapter,
3abcdeda 1029 struct be_rx_obj *rxo,
2e588f84 1030 struct be_rx_compl_info *rxcp)
6b7c5b94
SP		 1031{
1032 struct be_rx_page_info *page_info;
5be93b9a 1033 struct sk_buff *skb = NULL;
3abcdeda
SP		 1034 struct be_queue_info *rxq = &rxo->q;
1035 struct be_eq_obj *eq_obj = &rxo->rx_eq;
2e588f84
SP		 1036 u16 remaining, curr_frag_len;
1037 u16 i, j;
3968fa1e 1038
5be93b9a
AK		 1039 skb = napi_get_frags(&eq_obj->napi);
1040 if (!skb) {
3abcdeda 1041 be_rx_compl_discard(adapter, rxo, rxcp);
5be93b9a
AK		 1042 return;
1043 }
1044
2e588f84
SP		 1045 remaining = rxcp->pkt_size;
1046 for (i = 0, j = -1; i < rxcp->num_rcvd; i++) {
1047 page_info = get_rx_page_info(adapter, rxo, rxcp->rxq_idx);
6b7c5b94
SP		 1048
1049 curr_frag_len = min(remaining, rx_frag_size);
1050
bd46cb6c
AK		 1051 /* Coalesce all frags from the same physical page in one slot */
1052 if (i == 0 || page_info->page_offset == 0) {
1053 /* First frag or Fresh page */
1054 j++;
5be93b9a
AK		 1055 skb_shinfo(skb)->frags[j].page = page_info->page;
1056 skb_shinfo(skb)->frags[j].page_offset =
1057 page_info->page_offset;
1058 skb_shinfo(skb)->frags[j].size = 0;
bd46cb6c
AK		 1059 } else {
1060 put_page(page_info->page);
1061 }
5be93b9a 1062 skb_shinfo(skb)->frags[j].size += curr_frag_len;
6b7c5b94 1063
bd46cb6c 1064 remaining -= curr_frag_len;
2e588f84 1065 index_inc(&rxcp->rxq_idx, rxq->len);
6b7c5b94
SP		 1066 memset(page_info, 0, sizeof(*page_info));
1067 }
bd46cb6c 1068 BUG_ON(j > MAX_SKB_FRAGS);
6b7c5b94 1069
5be93b9a 1070 skb_shinfo(skb)->nr_frags = j + 1;
2e588f84
SP		 1071 skb->len = rxcp->pkt_size;
1072 skb->data_len = rxcp->pkt_size;
1073 skb->truesize += rxcp->pkt_size;
5be93b9a
AK		 1074 skb->ip_summed = CHECKSUM_UNNECESSARY;
1075
2e588f84 1076 if (likely(!rxcp->vlanf))
5be93b9a 1077 napi_gro_frags(&eq_obj->napi);
2e588f84
SP		 1078 else
1079 vlan_gro_frags(&eq_obj->napi, adapter->vlan_grp, rxcp->vid);
1080}
1081
1082static void be_parse_rx_compl_v1(struct be_adapter *adapter,
1083 struct be_eth_rx_compl *compl,
1084 struct be_rx_compl_info *rxcp)
1085{
1086 rxcp->pkt_size =
1087 AMAP_GET_BITS(struct amap_eth_rx_compl_v1, pktsize, compl);
1088 rxcp->vlanf = AMAP_GET_BITS(struct amap_eth_rx_compl_v1, vtp, compl);
1089 rxcp->err = AMAP_GET_BITS(struct amap_eth_rx_compl_v1, err, compl);
1090 rxcp->tcpf = AMAP_GET_BITS(struct amap_eth_rx_compl_v1, tcpf, compl);
9ecb42fd 1091 rxcp->udpf = AMAP_GET_BITS(struct amap_eth_rx_compl_v1, udpf, compl);
2e588f84
SP		 1092 rxcp->ip_csum =
1093 AMAP_GET_BITS(struct amap_eth_rx_compl_v1, ipcksm, compl);
1094 rxcp->l4_csum =
1095 AMAP_GET_BITS(struct amap_eth_rx_compl_v1, l4_cksm, compl);
1096 rxcp->ipv6 =
1097 AMAP_GET_BITS(struct amap_eth_rx_compl_v1, ip_version, compl);
1098 rxcp->rxq_idx =
1099 AMAP_GET_BITS(struct amap_eth_rx_compl_v1, fragndx, compl);
1100 rxcp->num_rcvd =
1101 AMAP_GET_BITS(struct amap_eth_rx_compl_v1, numfrags, compl);
1102 rxcp->pkt_type =
1103 AMAP_GET_BITS(struct amap_eth_rx_compl_v1, cast_enc, compl);
15d72184
SP		 1104 if (rxcp->vlanf) {
1105 rxcp->vtm = AMAP_GET_BITS(struct amap_eth_rx_compl_v1, vtm,
1106 compl);
1107 rxcp->vid = AMAP_GET_BITS(struct amap_eth_rx_compl_v1, vlan_tag,
1108 compl);
1109 }
2e588f84
SP		 1110}
1111
1112static void be_parse_rx_compl_v0(struct be_adapter *adapter,
1113 struct be_eth_rx_compl *compl,
1114 struct be_rx_compl_info *rxcp)
1115{
1116 rxcp->pkt_size =
1117 AMAP_GET_BITS(struct amap_eth_rx_compl_v0, pktsize, compl);
1118 rxcp->vlanf = AMAP_GET_BITS(struct amap_eth_rx_compl_v0, vtp, compl);
1119 rxcp->err = AMAP_GET_BITS(struct amap_eth_rx_compl_v0, err, compl);
1120 rxcp->tcpf = AMAP_GET_BITS(struct amap_eth_rx_compl_v0, tcpf, compl);
9ecb42fd 1121 rxcp->udpf = AMAP_GET_BITS(struct amap_eth_rx_compl_v0, udpf, compl);
2e588f84
SP		 1122 rxcp->ip_csum =
1123 AMAP_GET_BITS(struct amap_eth_rx_compl_v0, ipcksm, compl);
1124 rxcp->l4_csum =
1125 AMAP_GET_BITS(struct amap_eth_rx_compl_v0, l4_cksm, compl);
1126 rxcp->ipv6 =
1127 AMAP_GET_BITS(struct amap_eth_rx_compl_v0, ip_version, compl);
1128 rxcp->rxq_idx =
1129 AMAP_GET_BITS(struct amap_eth_rx_compl_v0, fragndx, compl);
1130 rxcp->num_rcvd =
1131 AMAP_GET_BITS(struct amap_eth_rx_compl_v0, numfrags, compl);
1132 rxcp->pkt_type =
1133 AMAP_GET_BITS(struct amap_eth_rx_compl_v0, cast_enc, compl);
15d72184
SP		 1134 if (rxcp->vlanf) {
1135 rxcp->vtm = AMAP_GET_BITS(struct amap_eth_rx_compl_v0, vtm,
1136 compl);
1137 rxcp->vid = AMAP_GET_BITS(struct amap_eth_rx_compl_v0, vlan_tag,
1138 compl);
1139 }
2e588f84
SP		 1140}
1141
1142static struct be_rx_compl_info *be_rx_compl_get(struct be_rx_obj *rxo)
1143{
1144 struct be_eth_rx_compl *compl = queue_tail_node(&rxo->cq);
1145 struct be_rx_compl_info *rxcp = &rxo->rxcp;
1146 struct be_adapter *adapter = rxo->adapter;
6b7c5b94 1147
2e588f84
SP		 1148 /* For checking the valid bit it is Ok to use either definition as the
1149 * valid bit is at the same position in both v0 and v1 Rx compl */
1150 if (compl->dw[offsetof(struct amap_eth_rx_compl_v1, valid) / 32] == 0)
1151 return NULL;
6b7c5b94 1152
2e588f84
SP		 1153 rmb();
1154 be_dws_le_to_cpu(compl, sizeof(*compl));
6b7c5b94 1155
2e588f84
SP		 1156 if (adapter->be3_native)
1157 be_parse_rx_compl_v1(adapter, compl, rxcp);
1158 else
1159 be_parse_rx_compl_v0(adapter, compl, rxcp);
6b7c5b94 1160
15d72184
SP		 1161 if (rxcp->vlanf) {
1162 /* vlanf could be wrongly set in some cards.
1163 * ignore if vtm is not set */
1164 if ((adapter->function_mode & 0x400) && !rxcp->vtm)
1165 rxcp->vlanf = 0;
6b7c5b94 1166
15d72184
SP		 1167 if (!lancer_chip(adapter))
1168 rxcp->vid = swab16(rxcp->vid);
6b7c5b94 1169
15d72184
SP		 1170 if ((adapter->pvid == rxcp->vid) &&
1171 !adapter->vlan_tag[rxcp->vid])
1172 rxcp->vlanf = 0;
1173 }
2e588f84
SP		 1174
1175 /* As the compl has been parsed, reset it; we wont touch it again */
1176 compl->dw[offsetof(struct amap_eth_rx_compl_v1, valid) / 32] = 0;
6b7c5b94 1177
3abcdeda 1178 queue_tail_inc(&rxo->cq);
6b7c5b94
SP		 1179 return rxcp;
1180}
1181
1829b086 1182static inline struct page *be_alloc_pages(u32 size, gfp_t gfp)
6b7c5b94 1183{
6b7c5b94 1184 u32 order = get_order(size);
1829b086 1185
6b7c5b94 1186 if (order > 0)
1829b086
ED		 1187 gfp |= __GFP_COMP;
1188 return alloc_pages(gfp, order);
6b7c5b94
SP		 1189}
1190
1191/*
1192 * Allocate a page, split it to fragments of size rx_frag_size and post as
1193 * receive buffers to BE
1194 */
1829b086 1195static void be_post_rx_frags(struct be_rx_obj *rxo, gfp_t gfp)
6b7c5b94 1196{
3abcdeda
SP		 1197 struct be_adapter *adapter = rxo->adapter;
1198 struct be_rx_page_info *page_info_tbl = rxo->page_info_tbl;
26d92f92 1199 struct be_rx_page_info *page_info = NULL, *prev_page_info = NULL;
3abcdeda 1200 struct be_queue_info *rxq = &rxo->q;
6b7c5b94
SP		 1201 struct page *pagep = NULL;
1202 struct be_eth_rx_d *rxd;
1203 u64 page_dmaaddr = 0, frag_dmaaddr;
1204 u32 posted, page_offset = 0;
1205
3abcdeda 1206 page_info = &rxo->page_info_tbl[rxq->head];
6b7c5b94
SP		 1207 for (posted = 0; posted < MAX_RX_POST && !page_info->page; posted++) {
1208 if (!pagep) {
1829b086 1209 pagep = be_alloc_pages(adapter->big_page_size, gfp);
6b7c5b94 1210 if (unlikely(!pagep)) {
3abcdeda 1211 rxo->stats.rx_post_fail++;
6b7c5b94
SP		 1212 break;
1213 }
2b7bcebf
IV		 1214 page_dmaaddr = dma_map_page(&adapter->pdev->dev, pagep,
1215 0, adapter->big_page_size,
1216 DMA_FROM_DEVICE);
6b7c5b94
SP		 1217 page_info->page_offset = 0;
1218 } else {
1219 get_page(pagep);
1220 page_info->page_offset = page_offset + rx_frag_size;
1221 }
1222 page_offset = page_info->page_offset;
1223 page_info->page = pagep;
fac6da5b 1224 dma_unmap_addr_set(page_info, bus, page_dmaaddr);
6b7c5b94
SP		 1225 frag_dmaaddr = page_dmaaddr + page_info->page_offset;
1226
1227 rxd = queue_head_node(rxq);
1228 rxd->fragpa_lo = cpu_to_le32(frag_dmaaddr & 0xFFFFFFFF);
1229 rxd->fragpa_hi = cpu_to_le32(upper_32_bits(frag_dmaaddr));
6b7c5b94
SP		 1230
1231 /* Any space left in the current big page for another frag? */
1232 if ((page_offset + rx_frag_size + rx_frag_size) >
1233 adapter->big_page_size) {
1234 pagep = NULL;
1235 page_info->last_page_user = true;
1236 }
26d92f92
SP		 1237
1238 prev_page_info = page_info;
1239 queue_head_inc(rxq);
6b7c5b94
SP		 1240 page_info = &page_info_tbl[rxq->head];
1241 }
1242 if (pagep)
26d92f92 1243 prev_page_info->last_page_user = true;
6b7c5b94
SP		 1244
1245 if (posted) {
6b7c5b94 1246 atomic_add(posted, &rxq->used);
8788fdc2 1247 be_rxq_notify(adapter, rxq->id, posted);
ea1dae11
SP		 1248 } else if (atomic_read(&rxq->used) == 0) {
1249 /* Let be_worker replenish when memory is available */
3abcdeda 1250 rxo->rx_post_starved = true;
6b7c5b94 1251 }
6b7c5b94
SP		 1252}
1253
5fb379ee 1254static struct be_eth_tx_compl *be_tx_compl_get(struct be_queue_info *tx_cq)
6b7c5b94 1255{
6b7c5b94
SP		 1256 struct be_eth_tx_compl *txcp = queue_tail_node(tx_cq);
1257
1258 if (txcp->dw[offsetof(struct amap_eth_tx_compl, valid) / 32] == 0)
1259 return NULL;
1260
f3eb62d2 1261 rmb();
6b7c5b94
SP		 1262 be_dws_le_to_cpu(txcp, sizeof(*txcp));
1263
1264 txcp->dw[offsetof(struct amap_eth_tx_compl, valid) / 32] = 0;
1265
1266 queue_tail_inc(tx_cq);
1267 return txcp;
1268}
1269
1270static void be_tx_compl_process(struct be_adapter *adapter, u16 last_index)
1271{
1272 struct be_queue_info *txq = &adapter->tx_obj.q;
a73b796e 1273 struct be_eth_wrb *wrb;
6b7c5b94
SP		 1274 struct sk_buff **sent_skbs = adapter->tx_obj.sent_skb_list;
1275 struct sk_buff *sent_skb;
ec43b1a6
SP		 1276 u16 cur_index, num_wrbs = 1; /* account for hdr wrb */
1277 bool unmap_skb_hdr = true;
6b7c5b94 1278
ec43b1a6 1279 sent_skb = sent_skbs[txq->tail];
6b7c5b94 1280 BUG_ON(!sent_skb);
ec43b1a6
SP		 1281 sent_skbs[txq->tail] = NULL;
1282
1283 /* skip header wrb */
a73b796e 1284 queue_tail_inc(txq);
6b7c5b94 1285
ec43b1a6 1286 do {
6b7c5b94 1287 cur_index = txq->tail;
a73b796e 1288 wrb = queue_tail_node(txq);
2b7bcebf
IV		 1289 unmap_tx_frag(&adapter->pdev->dev, wrb,
1290 (unmap_skb_hdr && skb_headlen(sent_skb)));
ec43b1a6
SP		 1291 unmap_skb_hdr = false;
1292
6b7c5b94
SP		 1293 num_wrbs++;
1294 queue_tail_inc(txq);
ec43b1a6 1295 } while (cur_index != last_index);
6b7c5b94
SP		 1296
1297 atomic_sub(num_wrbs, &txq->used);
a73b796e 1298
6b7c5b94
SP		 1299 kfree_skb(sent_skb);
1300}
1301
859b1e4e
SP		 1302static inline struct be_eq_entry *event_get(struct be_eq_obj *eq_obj)
1303{
1304 struct be_eq_entry *eqe = queue_tail_node(&eq_obj->q);
1305
1306 if (!eqe->evt)
1307 return NULL;
1308
f3eb62d2 1309 rmb();
859b1e4e
SP		 1310 eqe->evt = le32_to_cpu(eqe->evt);
1311 queue_tail_inc(&eq_obj->q);
1312 return eqe;
1313}
1314
1315static int event_handle(struct be_adapter *adapter,
1316 struct be_eq_obj *eq_obj)
1317{
1318 struct be_eq_entry *eqe;
1319 u16 num = 0;
1320
1321 while ((eqe = event_get(eq_obj)) != NULL) {
1322 eqe->evt = 0;
1323 num++;
1324 }
1325
1326 /* Deal with any spurious interrupts that come
1327 * without events
1328 */
1329 be_eq_notify(adapter, eq_obj->q.id, true, true, num);
1330 if (num)
1331 napi_schedule(&eq_obj->napi);
1332
1333 return num;
1334}
1335
1336/* Just read and notify events without processing them.
1337 * Used at the time of destroying event queues */
1338static void be_eq_clean(struct be_adapter *adapter,
1339 struct be_eq_obj *eq_obj)
1340{
1341 struct be_eq_entry *eqe;
1342 u16 num = 0;
1343
1344 while ((eqe = event_get(eq_obj)) != NULL) {
1345 eqe->evt = 0;
1346 num++;
1347 }
1348
1349 if (num)
1350 be_eq_notify(adapter, eq_obj->q.id, false, true, num);
1351}
1352
3abcdeda 1353static void be_rx_q_clean(struct be_adapter *adapter, struct be_rx_obj *rxo)
6b7c5b94
SP		 1354{
1355 struct be_rx_page_info *page_info;
3abcdeda
SP		 1356 struct be_queue_info *rxq = &rxo->q;
1357 struct be_queue_info *rx_cq = &rxo->cq;
2e588f84 1358 struct be_rx_compl_info *rxcp;
6b7c5b94
SP		 1359 u16 tail;
1360
1361 /* First cleanup pending rx completions */
3abcdeda
SP		 1362 while ((rxcp = be_rx_compl_get(rxo)) != NULL) {
1363 be_rx_compl_discard(adapter, rxo, rxcp);
64642811 1364 be_cq_notify(adapter, rx_cq->id, false, 1);
6b7c5b94
SP		 1365 }
1366
1367 /* Then free posted rx buffer that were not used */
1368 tail = (rxq->head + rxq->len - atomic_read(&rxq->used)) % rxq->len;
cdab23b7 1369 for (; atomic_read(&rxq->used) > 0; index_inc(&tail, rxq->len)) {
3abcdeda 1370 page_info = get_rx_page_info(adapter, rxo, tail);
6b7c5b94
SP		 1371 put_page(page_info->page);
1372 memset(page_info, 0, sizeof(*page_info));
1373 }
1374 BUG_ON(atomic_read(&rxq->used));
1375}
1376
a8e9179a 1377static void be_tx_compl_clean(struct be_adapter *adapter)
6b7c5b94 1378{
a8e9179a 1379 struct be_queue_info *tx_cq = &adapter->tx_obj.cq;
6b7c5b94 1380 struct be_queue_info *txq = &adapter->tx_obj.q;
a8e9179a
SP		 1381 struct be_eth_tx_compl *txcp;
1382 u16 end_idx, cmpl = 0, timeo = 0;
b03388d6
SP		 1383 struct sk_buff **sent_skbs = adapter->tx_obj.sent_skb_list;
1384 struct sk_buff *sent_skb;
1385 bool dummy_wrb;
a8e9179a
SP		 1386
1387 /* Wait for a max of 200ms for all the tx-completions to arrive. */
1388 do {
1389 while ((txcp = be_tx_compl_get(tx_cq))) {
1390 end_idx = AMAP_GET_BITS(struct amap_eth_tx_compl,
1391 wrb_index, txcp);
1392 be_tx_compl_process(adapter, end_idx);
1393 cmpl++;
1394 }
1395 if (cmpl) {
1396 be_cq_notify(adapter, tx_cq->id, false, cmpl);
1397 cmpl = 0;
1398 }
1399
1400 if (atomic_read(&txq->used) == 0 || ++timeo > 200)
1401 break;
1402
1403 mdelay(1);
1404 } while (true);
1405
1406 if (atomic_read(&txq->used))
1407 dev_err(&adapter->pdev->dev, "%d pending tx-completions\n",
1408 atomic_read(&txq->used));
b03388d6
SP		 1409
1410 /* free posted tx for which compls will never arrive */
1411 while (atomic_read(&txq->used)) {
1412 sent_skb = sent_skbs[txq->tail];
1413 end_idx = txq->tail;
1414 index_adv(&end_idx,
fe6d2a38
SP		 1415 wrb_cnt_for_skb(adapter, sent_skb, &dummy_wrb) - 1,
1416 txq->len);
b03388d6
SP		 1417 be_tx_compl_process(adapter, end_idx);
1418 }
6b7c5b94
SP		 1419}
1420
5fb379ee
SP		 1421static void be_mcc_queues_destroy(struct be_adapter *adapter)
1422{
1423 struct be_queue_info *q;
5fb379ee 1424
8788fdc2 1425 q = &adapter->mcc_obj.q;
5fb379ee 1426 if (q->created)
8788fdc2 1427 be_cmd_q_destroy(adapter, q, QTYPE_MCCQ);
5fb379ee
SP		 1428 be_queue_free(adapter, q);
1429
8788fdc2 1430 q = &adapter->mcc_obj.cq;
5fb379ee 1431 if (q->created)
8788fdc2 1432 be_cmd_q_destroy(adapter, q, QTYPE_CQ);
5fb379ee
SP		 1433 be_queue_free(adapter, q);
1434}
1435
1436/* Must be called only after TX qs are created as MCC shares TX EQ */
1437static int be_mcc_queues_create(struct be_adapter *adapter)
1438{
1439 struct be_queue_info *q, *cq;
5fb379ee
SP		 1440
1441 /* Alloc MCC compl queue */
8788fdc2 1442 cq = &adapter->mcc_obj.cq;
5fb379ee 1443 if (be_queue_alloc(adapter, cq, MCC_CQ_LEN,
efd2e40a 1444 sizeof(struct be_mcc_compl)))
5fb379ee
SP		 1445 goto err;
1446
1447 /* Ask BE to create MCC compl queue; share TX's eq */
8788fdc2 1448 if (be_cmd_cq_create(adapter, cq, &adapter->tx_eq.q, false, true, 0))
5fb379ee
SP		 1449 goto mcc_cq_free;
1450
1451 /* Alloc MCC queue */
8788fdc2 1452 q = &adapter->mcc_obj.q;
5fb379ee
SP		 1453 if (be_queue_alloc(adapter, q, MCC_Q_LEN, sizeof(struct be_mcc_wrb)))
1454 goto mcc_cq_destroy;
1455
1456 /* Ask BE to create MCC queue */
8788fdc2 1457 if (be_cmd_mccq_create(adapter, q, cq))
5fb379ee
SP		 1458 goto mcc_q_free;
1459
1460 return 0;
1461
1462mcc_q_free:
1463 be_queue_free(adapter, q);
1464mcc_cq_destroy:
8788fdc2 1465 be_cmd_q_destroy(adapter, cq, QTYPE_CQ);
5fb379ee
SP		 1466mcc_cq_free:
1467 be_queue_free(adapter, cq);
1468err:
1469 return -1;
1470}
1471
6b7c5b94
SP		 1472static void be_tx_queues_destroy(struct be_adapter *adapter)
1473{
1474 struct be_queue_info *q;
1475
1476 q = &adapter->tx_obj.q;
a8e9179a 1477 if (q->created)
8788fdc2 1478 be_cmd_q_destroy(adapter, q, QTYPE_TXQ);
6b7c5b94
SP		 1479 be_queue_free(adapter, q);
1480
1481 q = &adapter->tx_obj.cq;
1482 if (q->created)
8788fdc2 1483 be_cmd_q_destroy(adapter, q, QTYPE_CQ);
6b7c5b94
SP		 1484 be_queue_free(adapter, q);
1485
859b1e4e
SP		 1486 /* Clear any residual events */
1487 be_eq_clean(adapter, &adapter->tx_eq);
1488
6b7c5b94
SP		 1489 q = &adapter->tx_eq.q;
1490 if (q->created)
8788fdc2 1491 be_cmd_q_destroy(adapter, q, QTYPE_EQ);
6b7c5b94
SP		 1492 be_queue_free(adapter, q);
1493}
1494
1495static int be_tx_queues_create(struct be_adapter *adapter)
1496{
1497 struct be_queue_info *eq, *q, *cq;
1498
1499 adapter->tx_eq.max_eqd = 0;
1500 adapter->tx_eq.min_eqd = 0;
1501 adapter->tx_eq.cur_eqd = 96;
1502 adapter->tx_eq.enable_aic = false;
1503 /* Alloc Tx Event queue */
1504 eq = &adapter->tx_eq.q;
1505 if (be_queue_alloc(adapter, eq, EVNT_Q_LEN, sizeof(struct be_eq_entry)))
1506 return -1;
1507
1508 /* Ask BE to create Tx Event queue */
8788fdc2 1509 if (be_cmd_eq_create(adapter, eq, adapter->tx_eq.cur_eqd))
6b7c5b94 1510 goto tx_eq_free;
fe6d2a38
SP		 1511
1512 adapter->tx_eq.msix_vec_idx = adapter->msix_vec_next_idx++;
1513
ba343c77 1514
6b7c5b94
SP		 1515 /* Alloc TX eth compl queue */
1516 cq = &adapter->tx_obj.cq;
1517 if (be_queue_alloc(adapter, cq, TX_CQ_LEN,
1518 sizeof(struct be_eth_tx_compl)))
1519 goto tx_eq_destroy;
1520
1521 /* Ask BE to create Tx eth compl queue */
8788fdc2 1522 if (be_cmd_cq_create(adapter, cq, eq, false, false, 3))
6b7c5b94
SP		 1523 goto tx_cq_free;
1524
1525 /* Alloc TX eth queue */
1526 q = &adapter->tx_obj.q;
1527 if (be_queue_alloc(adapter, q, TX_Q_LEN, sizeof(struct be_eth_wrb)))
1528 goto tx_cq_destroy;
1529
1530 /* Ask BE to create Tx eth queue */
8788fdc2 1531 if (be_cmd_txq_create(adapter, q, cq))
6b7c5b94
SP		 1532 goto tx_q_free;
1533 return 0;
1534
1535tx_q_free:
1536 be_queue_free(adapter, q);
1537tx_cq_destroy:
8788fdc2 1538 be_cmd_q_destroy(adapter, cq, QTYPE_CQ);
6b7c5b94
SP		 1539tx_cq_free:
1540 be_queue_free(adapter, cq);
1541tx_eq_destroy:
8788fdc2 1542 be_cmd_q_destroy(adapter, eq, QTYPE_EQ);
6b7c5b94
SP		 1543tx_eq_free:
1544 be_queue_free(adapter, eq);
1545 return -1;
1546}
1547
1548static void be_rx_queues_destroy(struct be_adapter *adapter)
1549{
1550 struct be_queue_info *q;
3abcdeda
SP		 1551 struct be_rx_obj *rxo;
1552 int i;
1553
1554 for_all_rx_queues(adapter, rxo, i) {
1555 q = &rxo->q;
1556 if (q->created) {
1557 be_cmd_q_destroy(adapter, q, QTYPE_RXQ);
1558 /* After the rxq is invalidated, wait for a grace time
1559 * of 1ms for all dma to end and the flush compl to
1560 * arrive
1561 */
1562 mdelay(1);
1563 be_rx_q_clean(adapter, rxo);
1564 }
1565 be_queue_free(adapter, q);
1566
1567 q = &rxo->cq;
1568 if (q->created)
1569 be_cmd_q_destroy(adapter, q, QTYPE_CQ);
1570 be_queue_free(adapter, q);
1571
1572 /* Clear any residual events */
1573 q = &rxo->rx_eq.q;
1574 if (q->created) {
1575 be_eq_clean(adapter, &rxo->rx_eq);
1576 be_cmd_q_destroy(adapter, q, QTYPE_EQ);
1577 }
1578 be_queue_free(adapter, q);
6b7c5b94 1579 }
6b7c5b94
SP		 1580}
1581
ac6a0c4a
SP		 1582static u32 be_num_rxqs_want(struct be_adapter *adapter)
1583{
1584 if (multi_rxq && (adapter->function_caps & BE_FUNCTION_CAPS_RSS) &&
1585 !adapter->sriov_enabled && !(adapter->function_mode & 0x400)) {
1586 return 1 + MAX_RSS_QS; /* one default non-RSS queue */
1587 } else {
1588 dev_warn(&adapter->pdev->dev,
1589 "No support for multiple RX queues\n");
1590 return 1;
1591 }
1592}
1593
6b7c5b94
SP		 1594static int be_rx_queues_create(struct be_adapter *adapter)
1595{
1596 struct be_queue_info *eq, *q, *cq;
3abcdeda
SP		 1597 struct be_rx_obj *rxo;
1598 int rc, i;
6b7c5b94 1599
ac6a0c4a
SP		 1600 adapter->num_rx_qs = min(be_num_rxqs_want(adapter),
1601 msix_enabled(adapter) ?
1602 adapter->num_msix_vec - 1 : 1);
1603 if (adapter->num_rx_qs != MAX_RX_QS)
1604 dev_warn(&adapter->pdev->dev,
1605 "Can create only %d RX queues", adapter->num_rx_qs);
1606
6b7c5b94 1607 adapter->big_page_size = (1 << get_order(rx_frag_size)) * PAGE_SIZE;
3abcdeda
SP		 1608 for_all_rx_queues(adapter, rxo, i) {
1609 rxo->adapter = adapter;
1610 rxo->rx_eq.max_eqd = BE_MAX_EQD;
1611 rxo->rx_eq.enable_aic = true;
1612
1613 /* EQ */
1614 eq = &rxo->rx_eq.q;
1615 rc = be_queue_alloc(adapter, eq, EVNT_Q_LEN,
1616 sizeof(struct be_eq_entry));
1617 if (rc)
1618 goto err;
1619
1620 rc = be_cmd_eq_create(adapter, eq, rxo->rx_eq.cur_eqd);
1621 if (rc)
1622 goto err;
1623
fe6d2a38
SP		 1624 rxo->rx_eq.msix_vec_idx = adapter->msix_vec_next_idx++;
1625
3abcdeda
SP		 1626 /* CQ */
1627 cq = &rxo->cq;
1628 rc = be_queue_alloc(adapter, cq, RX_CQ_LEN,
1629 sizeof(struct be_eth_rx_compl));
1630 if (rc)
1631 goto err;
1632
1633 rc = be_cmd_cq_create(adapter, cq, eq, false, false, 3);
1634 if (rc)
1635 goto err;
3abcdeda
SP		 1636 /* Rx Q */
1637 q = &rxo->q;
1638 rc = be_queue_alloc(adapter, q, RX_Q_LEN,
1639 sizeof(struct be_eth_rx_d));
1640 if (rc)
1641 goto err;
1642
1643 rc = be_cmd_rxq_create(adapter, q, cq->id, rx_frag_size,
1644 BE_MAX_JUMBO_FRAME_SIZE, adapter->if_handle,
1645 (i > 0) ? 1 : 0/* rss enable */, &rxo->rss_id);
1646 if (rc)
1647 goto err;
1648 }
1649
1650 if (be_multi_rxq(adapter)) {
1651 u8 rsstable[MAX_RSS_QS];
1652
1653 for_all_rss_queues(adapter, rxo, i)
1654 rsstable[i] = rxo->rss_id;
1655
1656 rc = be_cmd_rss_config(adapter, rsstable,
1657 adapter->num_rx_qs - 1);
1658 if (rc)
1659 goto err;
1660 }
6b7c5b94
SP		 1661
1662 return 0;
3abcdeda
SP		 1663err:
1664 be_rx_queues_destroy(adapter);
1665 return -1;
6b7c5b94 1666}
6b7c5b94 1667
fe6d2a38 1668static bool event_peek(struct be_eq_obj *eq_obj)
b628bde2 1669{
fe6d2a38
SP		 1670 struct be_eq_entry *eqe = queue_tail_node(&eq_obj->q);
1671 if (!eqe->evt)
1672 return false;
1673 else
1674 return true;
b628bde2
SP		 1675}
1676
6b7c5b94
SP		 1677static irqreturn_t be_intx(int irq, void *dev)
1678{
1679 struct be_adapter *adapter = dev;
3abcdeda 1680 struct be_rx_obj *rxo;
fe6d2a38 1681 int isr, i, tx = 0 , rx = 0;
6b7c5b94 1682
fe6d2a38
SP		 1683 if (lancer_chip(adapter)) {
1684 if (event_peek(&adapter->tx_eq))
1685 tx = event_handle(adapter, &adapter->tx_eq);
1686 for_all_rx_queues(adapter, rxo, i) {
1687 if (event_peek(&rxo->rx_eq))
1688 rx |= event_handle(adapter, &rxo->rx_eq);
1689 }
6b7c5b94 1690
fe6d2a38
SP		 1691 if (!(tx || rx))
1692 return IRQ_NONE;
3abcdeda 1693
fe6d2a38
SP		 1694 } else {
1695 isr = ioread32(adapter->csr + CEV_ISR0_OFFSET +
1696 (adapter->tx_eq.q.id / 8) * CEV_ISR_SIZE);
1697 if (!isr)
1698 return IRQ_NONE;
1699
1700 if ((1 << adapter->tx_eq.msix_vec_idx & isr))
1701 event_handle(adapter, &adapter->tx_eq);
1702
1703 for_all_rx_queues(adapter, rxo, i) {
1704 if ((1 << rxo->rx_eq.msix_vec_idx & isr))
1705 event_handle(adapter, &rxo->rx_eq);
1706 }
3abcdeda 1707 }
c001c213 1708
8788fdc2 1709 return IRQ_HANDLED;
6b7c5b94
SP		 1710}
1711
1712static irqreturn_t be_msix_rx(int irq, void *dev)
1713{
3abcdeda
SP		 1714 struct be_rx_obj *rxo = dev;
1715 struct be_adapter *adapter = rxo->adapter;
6b7c5b94 1716
3abcdeda 1717 event_handle(adapter, &rxo->rx_eq);
6b7c5b94
SP		 1718
1719 return IRQ_HANDLED;
1720}
1721
5fb379ee 1722static irqreturn_t be_msix_tx_mcc(int irq, void *dev)
6b7c5b94
SP		 1723{
1724 struct be_adapter *adapter = dev;
1725
8788fdc2 1726 event_handle(adapter, &adapter->tx_eq);
6b7c5b94
SP		 1727
1728 return IRQ_HANDLED;
1729}
1730
2e588f84 1731static inline bool do_gro(struct be_rx_compl_info *rxcp)
6b7c5b94 1732{
2e588f84 1733 return (rxcp->tcpf && !rxcp->err) ? true : false;
6b7c5b94
SP		 1734}
1735
49b05221 1736static int be_poll_rx(struct napi_struct *napi, int budget)
6b7c5b94
SP		 1737{
1738 struct be_eq_obj *rx_eq = container_of(napi, struct be_eq_obj, napi);
3abcdeda
SP		 1739 struct be_rx_obj *rxo = container_of(rx_eq, struct be_rx_obj, rx_eq);
1740 struct be_adapter *adapter = rxo->adapter;
1741 struct be_queue_info *rx_cq = &rxo->cq;
2e588f84 1742 struct be_rx_compl_info *rxcp;
6b7c5b94
SP		 1743 u32 work_done;
1744
3abcdeda 1745 rxo->stats.rx_polls++;
6b7c5b94 1746 for (work_done = 0; work_done < budget; work_done++) {
3abcdeda 1747 rxcp = be_rx_compl_get(rxo);
6b7c5b94
SP		 1748 if (!rxcp)
1749 break;
1750
e80d9da6 1751 /* Ignore flush completions */
2e588f84
SP		 1752 if (rxcp->num_rcvd) {
1753 if (do_gro(rxcp))
64642811
SP		 1754 be_rx_compl_process_gro(adapter, rxo, rxcp);
1755 else
1756 be_rx_compl_process(adapter, rxo, rxcp);
1757 }
2e588f84 1758 be_rx_stats_update(rxo, rxcp);
6b7c5b94
SP		 1759 }
1760
6b7c5b94 1761 /* Refill the queue */
3abcdeda 1762 if (atomic_read(&rxo->q.used) < RX_FRAGS_REFILL_WM)
1829b086 1763 be_post_rx_frags(rxo, GFP_ATOMIC);
6b7c5b94
SP		 1764
1765 /* All consumed */
1766 if (work_done < budget) {
1767 napi_complete(napi);
8788fdc2 1768 be_cq_notify(adapter, rx_cq->id, true, work_done);
6b7c5b94
SP		 1769 } else {
1770 /* More to be consumed; continue with interrupts disabled */
8788fdc2 1771 be_cq_notify(adapter, rx_cq->id, false, work_done);
6b7c5b94
SP		 1772 }
1773 return work_done;
1774}
1775
f31e50a8
SP		 1776/* As TX and MCC share the same EQ check for both TX and MCC completions.
1777 * For TX/MCC we don't honour budget; consume everything
1778 */
1779static int be_poll_tx_mcc(struct napi_struct *napi, int budget)
6b7c5b94 1780{
f31e50a8
SP		 1781 struct be_eq_obj *tx_eq = container_of(napi, struct be_eq_obj, napi);
1782 struct be_adapter *adapter =
1783 container_of(tx_eq, struct be_adapter, tx_eq);
5fb379ee
SP		 1784 struct be_queue_info *txq = &adapter->tx_obj.q;
1785 struct be_queue_info *tx_cq = &adapter->tx_obj.cq;
6b7c5b94 1786 struct be_eth_tx_compl *txcp;
f31e50a8 1787 int tx_compl = 0, mcc_compl, status = 0;
6b7c5b94
SP		 1788 u16 end_idx;
1789
5fb379ee 1790 while ((txcp = be_tx_compl_get(tx_cq))) {
6b7c5b94 1791 end_idx = AMAP_GET_BITS(struct amap_eth_tx_compl,
f31e50a8 1792 wrb_index, txcp);
6b7c5b94 1793 be_tx_compl_process(adapter, end_idx);
f31e50a8 1794 tx_compl++;
6b7c5b94
SP		 1795 }
1796
f31e50a8
SP		 1797 mcc_compl = be_process_mcc(adapter, &status);
1798
1799 napi_complete(napi);
1800
1801 if (mcc_compl) {
1802 struct be_mcc_obj *mcc_obj = &adapter->mcc_obj;
1803 be_cq_notify(adapter, mcc_obj->cq.id, true, mcc_compl);
1804 }
1805
1806 if (tx_compl) {
1807 be_cq_notify(adapter, adapter->tx_obj.cq.id, true, tx_compl);
5fb379ee
SP		 1808
1809 /* As Tx wrbs have been freed up, wake up netdev queue if
1810 * it was stopped due to lack of tx wrbs.
1811 */
1812 if (netif_queue_stopped(adapter->netdev) &&
6b7c5b94 1813 atomic_read(&txq->used) < txq->len / 2) {
5fb379ee
SP		 1814 netif_wake_queue(adapter->netdev);
1815 }
1816
3abcdeda
SP		 1817 tx_stats(adapter)->be_tx_events++;
1818 tx_stats(adapter)->be_tx_compl += tx_compl;
6b7c5b94 1819 }
6b7c5b94
SP		 1820
1821 return 1;
1822}
1823
d053de91 1824void be_detect_dump_ue(struct be_adapter *adapter)
7c185276
AK		 1825{
1826 u32 ue_status_lo, ue_status_hi, ue_status_lo_mask, ue_status_hi_mask;
1827 u32 i;
1828
1829 pci_read_config_dword(adapter->pdev,
1830 PCICFG_UE_STATUS_LOW, &ue_status_lo);
1831 pci_read_config_dword(adapter->pdev,
1832 PCICFG_UE_STATUS_HIGH, &ue_status_hi);
1833 pci_read_config_dword(adapter->pdev,
1834 PCICFG_UE_STATUS_LOW_MASK, &ue_status_lo_mask);
1835 pci_read_config_dword(adapter->pdev,
1836 PCICFG_UE_STATUS_HI_MASK, &ue_status_hi_mask);
1837
1838 ue_status_lo = (ue_status_lo & (~ue_status_lo_mask));
1839 ue_status_hi = (ue_status_hi & (~ue_status_hi_mask));
1840
d053de91
AK		 1841 if (ue_status_lo || ue_status_hi) {
1842 adapter->ue_detected = true;
7acc2087 1843 adapter->eeh_err = true;
d053de91
AK		 1844 dev_err(&adapter->pdev->dev, "UE Detected!!\n");
1845 }
1846
7c185276
AK		 1847 if (ue_status_lo) {
1848 for (i = 0; ue_status_lo; ue_status_lo >>= 1, i++) {
1849 if (ue_status_lo & 1)
1850 dev_err(&adapter->pdev->dev,
1851 "UE: %s bit set\n", ue_status_low_desc[i]);
1852 }
1853 }
1854 if (ue_status_hi) {
1855 for (i = 0; ue_status_hi; ue_status_hi >>= 1, i++) {
1856 if (ue_status_hi & 1)
1857 dev_err(&adapter->pdev->dev,
1858 "UE: %s bit set\n", ue_status_hi_desc[i]);
1859 }
1860 }
1861
1862}
1863
ea1dae11
SP		 1864static void be_worker(struct work_struct *work)
1865{
1866 struct be_adapter *adapter =
1867 container_of(work, struct be_adapter, work.work);
3abcdeda
SP		 1868 struct be_rx_obj *rxo;
1869 int i;
ea1dae11 1870
f203af70
SK		 1871 /* when interrupts are not yet enabled, just reap any pending
1872 * mcc completions */
1873 if (!netif_running(adapter->netdev)) {
1874 int mcc_compl, status = 0;
1875
1876 mcc_compl = be_process_mcc(adapter, &status);
1877
1878 if (mcc_compl) {
1879 struct be_mcc_obj *mcc_obj = &adapter->mcc_obj;
1880 be_cq_notify(adapter, mcc_obj->cq.id, false, mcc_compl);
1881 }
9b037f38
AK		 1882
1883 if (!adapter->ue_detected && !lancer_chip(adapter))
1884 be_detect_dump_ue(adapter);
1885
f203af70
SK		 1886 goto reschedule;
1887 }
1888
b2aebe6d 1889 if (!adapter->stats_cmd_sent)
3abcdeda 1890 be_cmd_get_stats(adapter, &adapter->stats_cmd);
ea1dae11 1891
4097f663 1892 be_tx_rate_update(adapter);
4097f663 1893
3abcdeda
SP		 1894 for_all_rx_queues(adapter, rxo, i) {
1895 be_rx_rate_update(rxo);
1896 be_rx_eqd_update(adapter, rxo);
1897
1898 if (rxo->rx_post_starved) {
1899 rxo->rx_post_starved = false;
1829b086 1900 be_post_rx_frags(rxo, GFP_KERNEL);
3abcdeda 1901 }
ea1dae11 1902 }
fe6d2a38 1903 if (!adapter->ue_detected && !lancer_chip(adapter))
d053de91 1904 be_detect_dump_ue(adapter);
ea1dae11 1905
f203af70 1906reschedule:
ea1dae11
SP		 1907 schedule_delayed_work(&adapter->work, msecs_to_jiffies(1000));
1908}
1909
8d56ff11
SP		 1910static void be_msix_disable(struct be_adapter *adapter)
1911{
ac6a0c4a 1912 if (msix_enabled(adapter)) {
8d56ff11 1913 pci_disable_msix(adapter->pdev);
ac6a0c4a 1914 adapter->num_msix_vec = 0;
3abcdeda
SP		 1915 }
1916}
1917
6b7c5b94
SP		 1918static void be_msix_enable(struct be_adapter *adapter)
1919{
3abcdeda 1920#define BE_MIN_MSIX_VECTORS (1 + 1) /* Rx + Tx */
ac6a0c4a 1921 int i, status, num_vec;
6b7c5b94 1922
ac6a0c4a 1923 num_vec = be_num_rxqs_want(adapter) + 1;
3abcdeda 1924
ac6a0c4a 1925 for (i = 0; i < num_vec; i++)
6b7c5b94
SP		 1926 adapter->msix_entries[i].entry = i;
1927
ac6a0c4a 1928 status = pci_enable_msix(adapter->pdev, adapter->msix_entries, num_vec);
3abcdeda
SP		 1929 if (status == 0) {
1930 goto done;
1931 } else if (status >= BE_MIN_MSIX_VECTORS) {
ac6a0c4a 1932 num_vec = status;
3abcdeda 1933 if (pci_enable_msix(adapter->pdev, adapter->msix_entries,
ac6a0c4a 1934 num_vec) == 0)
3abcdeda 1935 goto done;
3abcdeda
SP		 1936 }
1937 return;
1938done:
ac6a0c4a
SP		 1939 adapter->num_msix_vec = num_vec;
1940 return;
6b7c5b94
SP		 1941}
1942
ba343c77
SB		 1943static void be_sriov_enable(struct be_adapter *adapter)
1944{
344dbf10 1945 be_check_sriov_fn_type(adapter);
6dedec81 1946#ifdef CONFIG_PCI_IOV
ba343c77 1947 if (be_physfn(adapter) && num_vfs) {
6dedec81
AK		 1948 int status;
1949
ba343c77
SB		 1950 status = pci_enable_sriov(adapter->pdev, num_vfs);
1951 adapter->sriov_enabled = status ? false : true;
1952 }
1953#endif
ba343c77
SB		 1954}
1955
1956static void be_sriov_disable(struct be_adapter *adapter)
1957{
1958#ifdef CONFIG_PCI_IOV
1959 if (adapter->sriov_enabled) {
1960 pci_disable_sriov(adapter->pdev);
1961 adapter->sriov_enabled = false;
1962 }
1963#endif
1964}
1965
fe6d2a38
SP		 1966static inline int be_msix_vec_get(struct be_adapter *adapter,
1967 struct be_eq_obj *eq_obj)
6b7c5b94 1968{
fe6d2a38 1969 return adapter->msix_entries[eq_obj->msix_vec_idx].vector;
6b7c5b94
SP		 1970}
1971
b628bde2
SP		 1972static int be_request_irq(struct be_adapter *adapter,
1973 struct be_eq_obj *eq_obj,
3abcdeda 1974 void *handler, char *desc, void *context)
6b7c5b94
SP		 1975{
1976 struct net_device *netdev = adapter->netdev;
b628bde2
SP		 1977 int vec;
1978
1979 sprintf(eq_obj->desc, "%s-%s", netdev->name, desc);
fe6d2a38 1980 vec = be_msix_vec_get(adapter, eq_obj);
3abcdeda 1981 return request_irq(vec, handler, 0, eq_obj->desc, context);
b628bde2
SP		 1982}
1983
3abcdeda
SP		 1984static void be_free_irq(struct be_adapter *adapter, struct be_eq_obj *eq_obj,
1985 void *context)
b628bde2 1986{
fe6d2a38 1987 int vec = be_msix_vec_get(adapter, eq_obj);
3abcdeda 1988 free_irq(vec, context);
b628bde2 1989}
6b7c5b94 1990
b628bde2
SP		 1991static int be_msix_register(struct be_adapter *adapter)
1992{
3abcdeda
SP		 1993 struct be_rx_obj *rxo;
1994 int status, i;
1995 char qname[10];
b628bde2 1996
3abcdeda
SP		 1997 status = be_request_irq(adapter, &adapter->tx_eq, be_msix_tx_mcc, "tx",
1998 adapter);
6b7c5b94
SP		 1999 if (status)
2000 goto err;
2001
3abcdeda
SP		 2002 for_all_rx_queues(adapter, rxo, i) {
2003 sprintf(qname, "rxq%d", i);
2004 status = be_request_irq(adapter, &rxo->rx_eq, be_msix_rx,
2005 qname, rxo);
2006 if (status)
2007 goto err_msix;
2008 }
b628bde2 2009
6b7c5b94 2010 return 0;
b628bde2 2011
3abcdeda
SP		 2012err_msix:
2013 be_free_irq(adapter, &adapter->tx_eq, adapter);
2014
2015 for (i--, rxo = &adapter->rx_obj[i]; i >= 0; i--, rxo--)
2016 be_free_irq(adapter, &rxo->rx_eq, rxo);
2017
6b7c5b94
SP		 2018err:
2019 dev_warn(&adapter->pdev->dev,
2020 "MSIX Request IRQ failed - err %d\n", status);
ac6a0c4a 2021 be_msix_disable(adapter);
6b7c5b94
SP		 2022 return status;
2023}
2024
2025static int be_irq_register(struct be_adapter *adapter)
2026{
2027 struct net_device *netdev = adapter->netdev;
2028 int status;
2029
ac6a0c4a 2030 if (msix_enabled(adapter)) {
6b7c5b94
SP		 2031 status = be_msix_register(adapter);
2032 if (status == 0)
2033 goto done;
ba343c77
SB		 2034 /* INTx is not supported for VF */
2035 if (!be_physfn(adapter))
2036 return status;
6b7c5b94
SP		 2037 }
2038
2039 /* INTx */
2040 netdev->irq = adapter->pdev->irq;
2041 status = request_irq(netdev->irq, be_intx, IRQF_SHARED, netdev->name,
2042 adapter);
2043 if (status) {
2044 dev_err(&adapter->pdev->dev,
2045 "INTx request IRQ failed - err %d\n", status);
2046 return status;
2047 }
2048done:
2049 adapter->isr_registered = true;
2050 return 0;
2051}
2052
2053static void be_irq_unregister(struct be_adapter *adapter)
2054{
2055 struct net_device *netdev = adapter->netdev;
3abcdeda
SP		 2056 struct be_rx_obj *rxo;
2057 int i;
6b7c5b94
SP		 2058
2059 if (!adapter->isr_registered)
2060 return;
2061
2062 /* INTx */
ac6a0c4a 2063 if (!msix_enabled(adapter)) {
6b7c5b94
SP		 2064 free_irq(netdev->irq, adapter);
2065 goto done;
2066 }
2067
2068 /* MSIx */
3abcdeda
SP		 2069 be_free_irq(adapter, &adapter->tx_eq, adapter);
2070
2071 for_all_rx_queues(adapter, rxo, i)
2072 be_free_irq(adapter, &rxo->rx_eq, rxo);
2073
6b7c5b94
SP		 2074done:
2075 adapter->isr_registered = false;
6b7c5b94
SP		 2076}
2077
889cd4b2
SP		 2078static int be_close(struct net_device *netdev)
2079{
2080 struct be_adapter *adapter = netdev_priv(netdev);
3abcdeda 2081 struct be_rx_obj *rxo;
889cd4b2 2082 struct be_eq_obj *tx_eq = &adapter->tx_eq;
3abcdeda 2083 int vec, i;
889cd4b2 2084
889cd4b2
SP		 2085 be_async_mcc_disable(adapter);
2086
889cd4b2
SP		 2087 netif_carrier_off(netdev);
2088 adapter->link_up = false;
2089
fe6d2a38
SP		 2090 if (!lancer_chip(adapter))
2091 be_intr_set(adapter, false);
889cd4b2 2092
63fcb27f
PR		 2093 for_all_rx_queues(adapter, rxo, i)
2094 napi_disable(&rxo->rx_eq.napi);
2095
2096 napi_disable(&tx_eq->napi);
2097
2098 if (lancer_chip(adapter)) {
2099 be_cq_notify(adapter, adapter->tx_obj.cq.id, false, 0);
2100 be_cq_notify(adapter, adapter->mcc_obj.cq.id, false, 0);
2101 for_all_rx_queues(adapter, rxo, i)
2102 be_cq_notify(adapter, rxo->cq.id, false, 0);
2103 }
2104
ac6a0c4a 2105 if (msix_enabled(adapter)) {
fe6d2a38 2106 vec = be_msix_vec_get(adapter, tx_eq);
889cd4b2 2107 synchronize_irq(vec);
3abcdeda
SP		 2108
2109 for_all_rx_queues(adapter, rxo, i) {
fe6d2a38 2110 vec = be_msix_vec_get(adapter, &rxo->rx_eq);
3abcdeda
SP		 2111 synchronize_irq(vec);
2112 }
889cd4b2
SP		 2113 } else {
2114 synchronize_irq(netdev->irq);
2115 }
2116 be_irq_unregister(adapter);
2117
889cd4b2
SP		 2118 /* Wait for all pending tx completions to arrive so that
2119 * all tx skbs are freed.
2120 */
2121 be_tx_compl_clean(adapter);
2122
2123 return 0;
2124}
2125
6b7c5b94
SP		 2126static int be_open(struct net_device *netdev)
2127{
2128 struct be_adapter *adapter = netdev_priv(netdev);
6b7c5b94 2129 struct be_eq_obj *tx_eq = &adapter->tx_eq;
3abcdeda 2130 struct be_rx_obj *rxo;
a8f447bd 2131 bool link_up;
3abcdeda 2132 int status, i;
0388f251
SB		 2133 u8 mac_speed;
2134 u16 link_speed;
5fb379ee 2135
3abcdeda 2136 for_all_rx_queues(adapter, rxo, i) {
1829b086 2137 be_post_rx_frags(rxo, GFP_KERNEL);
3abcdeda
SP		 2138 napi_enable(&rxo->rx_eq.napi);
2139 }
5fb379ee
SP		 2140 napi_enable(&tx_eq->napi);
2141
2142 be_irq_register(adapter);
2143
fe6d2a38
SP		 2144 if (!lancer_chip(adapter))
2145 be_intr_set(adapter, true);
5fb379ee
SP		 2146
2147 /* The evt queues are created in unarmed state; arm them */
3abcdeda
SP		 2148 for_all_rx_queues(adapter, rxo, i) {
2149 be_eq_notify(adapter, rxo->rx_eq.q.id, true, false, 0);
2150 be_cq_notify(adapter, rxo->cq.id, true, 0);
2151 }
8788fdc2 2152 be_eq_notify(adapter, tx_eq->q.id, true, false, 0);
5fb379ee 2153
7a1e9b20
SP		 2154 /* Now that interrupts are on we can process async mcc */
2155 be_async_mcc_enable(adapter);
2156
0388f251
SB		 2157 status = be_cmd_link_status_query(adapter, &link_up, &mac_speed,
2158 &link_speed);
a8f447bd 2159 if (status)
889cd4b2 2160 goto err;
a8f447bd 2161 be_link_status_update(adapter, link_up);
5fb379ee 2162
889cd4b2 2163 if (be_physfn(adapter)) {
1da87b7f 2164 status = be_vid_config(adapter, false, 0);
889cd4b2
SP		 2165 if (status)
2166 goto err;
4f2aa89c 2167
ba343c77
SB		 2168 status = be_cmd_set_flow_control(adapter,
2169 adapter->tx_fc, adapter->rx_fc);
2170 if (status)
889cd4b2 2171 goto err;
ba343c77 2172 }
4f2aa89c 2173
889cd4b2
SP		 2174 return 0;
2175err:
2176 be_close(adapter->netdev);
2177 return -EIO;
5fb379ee
SP		 2178}
2179
71d8d1b5
AK		 2180static int be_setup_wol(struct be_adapter *adapter, bool enable)
2181{
2182 struct be_dma_mem cmd;
2183 int status = 0;
2184 u8 mac[ETH_ALEN];
2185
2186 memset(mac, 0, ETH_ALEN);
2187
2188 cmd.size = sizeof(struct be_cmd_req_acpi_wol_magic_config);
2b7bcebf
IV		 2189 cmd.va = dma_alloc_coherent(&adapter->pdev->dev, cmd.size, &cmd.dma,
2190 GFP_KERNEL);
71d8d1b5
AK		 2191 if (cmd.va == NULL)
2192 return -1;
2193 memset(cmd.va, 0, cmd.size);
2194
2195 if (enable) {
2196 status = pci_write_config_dword(adapter->pdev,
2197 PCICFG_PM_CONTROL_OFFSET, PCICFG_PM_CONTROL_MASK);
2198 if (status) {
2199 dev_err(&adapter->pdev->dev,
2381a55c 2200 "Could not enable Wake-on-lan\n");
2b7bcebf
IV		 2201 dma_free_coherent(&adapter->pdev->dev, cmd.size, cmd.va,
2202 cmd.dma);
71d8d1b5
AK		 2203 return status;
2204 }
2205 status = be_cmd_enable_magic_wol(adapter,
2206 adapter->netdev->dev_addr, &cmd);
2207 pci_enable_wake(adapter->pdev, PCI_D3hot, 1);
2208 pci_enable_wake(adapter->pdev, PCI_D3cold, 1);
2209 } else {
2210 status = be_cmd_enable_magic_wol(adapter, mac, &cmd);
2211 pci_enable_wake(adapter->pdev, PCI_D3hot, 0);
2212 pci_enable_wake(adapter->pdev, PCI_D3cold, 0);
2213 }
2214
2b7bcebf 2215 dma_free_coherent(&adapter->pdev->dev, cmd.size, cmd.va, cmd.dma);
71d8d1b5
AK		 2216 return status;
2217}
2218
6d87f5c3
AK		 2219/*
2220 * Generate a seed MAC address from the PF MAC Address using jhash.
2221 * MAC Address for VFs are assigned incrementally starting from the seed.
2222 * These addresses are programmed in the ASIC by the PF and the VF driver
2223 * queries for the MAC address during its probe.
2224 */
2225static inline int be_vf_eth_addr_config(struct be_adapter *adapter)
2226{
2227 u32 vf = 0;
3abcdeda 2228 int status = 0;
6d87f5c3
AK		 2229 u8 mac[ETH_ALEN];
2230
2231 be_vf_eth_addr_generate(adapter, mac);
2232
2233 for (vf = 0; vf < num_vfs; vf++) {
2234 status = be_cmd_pmac_add(adapter, mac,
2235 adapter->vf_cfg[vf].vf_if_handle,
f8617e08
AK		 2236 &adapter->vf_cfg[vf].vf_pmac_id,
2237 vf + 1);
6d87f5c3
AK		 2238 if (status)
2239 dev_err(&adapter->pdev->dev,
2240 "Mac address add failed for VF %d\n", vf);
2241 else
2242 memcpy(adapter->vf_cfg[vf].vf_mac_addr, mac, ETH_ALEN);
2243
2244 mac[5] += 1;
2245 }
2246 return status;
2247}
2248
2249static inline void be_vf_eth_addr_rem(struct be_adapter *adapter)
2250{
2251 u32 vf;
2252
2253 for (vf = 0; vf < num_vfs; vf++) {
2254 if (adapter->vf_cfg[vf].vf_pmac_id != BE_INVALID_PMAC_ID)
2255 be_cmd_pmac_del(adapter,
2256 adapter->vf_cfg[vf].vf_if_handle,
f8617e08 2257 adapter->vf_cfg[vf].vf_pmac_id, vf + 1);
6d87f5c3
AK		 2258 }
2259}
2260
5fb379ee
SP		 2261static int be_setup(struct be_adapter *adapter)
2262{
5fb379ee 2263 struct net_device *netdev = adapter->netdev;
ba343c77 2264 u32 cap_flags, en_flags, vf = 0;
6b7c5b94 2265 int status;
ba343c77
SB		 2266 u8 mac[ETH_ALEN];
2267
f21b538c
PR		 2268 cap_flags = en_flags = BE_IF_FLAGS_UNTAGGED |
2269 BE_IF_FLAGS_BROADCAST |
2270 BE_IF_FLAGS_MULTICAST;
6b7c5b94 2271
ba343c77
SB		 2272 if (be_physfn(adapter)) {
2273 cap_flags |= BE_IF_FLAGS_MCAST_PROMISCUOUS |
2274 BE_IF_FLAGS_PROMISCUOUS |
2275 BE_IF_FLAGS_PASS_L3L4_ERRORS;
2276 en_flags |= BE_IF_FLAGS_PASS_L3L4_ERRORS;
3abcdeda 2277
ac6a0c4a 2278 if (adapter->function_caps & BE_FUNCTION_CAPS_RSS) {
3abcdeda
SP		 2279 cap_flags |= BE_IF_FLAGS_RSS;
2280 en_flags |= BE_IF_FLAGS_RSS;
2281 }
ba343c77 2282 }
73d540f2
SP		 2283
2284 status = be_cmd_if_create(adapter, cap_flags, en_flags,
2285 netdev->dev_addr, false/* pmac_invalid */,
ba343c77 2286 &adapter->if_handle, &adapter->pmac_id, 0);
6b7c5b94
SP		 2287 if (status != 0)
2288 goto do_none;
2289
ba343c77 2290 if (be_physfn(adapter)) {
c99ac3e7
AK		 2291 if (adapter->sriov_enabled) {
2292 while (vf < num_vfs) {
2293 cap_flags = en_flags = BE_IF_FLAGS_UNTAGGED |
2294 BE_IF_FLAGS_BROADCAST;
2295 status = be_cmd_if_create(adapter, cap_flags,
2296 en_flags, mac, true,
64600ea5 2297 &adapter->vf_cfg[vf].vf_if_handle,
ba343c77 2298 NULL, vf+1);
c99ac3e7
AK		 2299 if (status) {
2300 dev_err(&adapter->pdev->dev,
2301 "Interface Create failed for VF %d\n",
2302 vf);
2303 goto if_destroy;
2304 }
2305 adapter->vf_cfg[vf].vf_pmac_id =
2306 BE_INVALID_PMAC_ID;
2307 vf++;
ba343c77 2308 }
84e5b9f7 2309 }
c99ac3e7 2310 } else {
ba343c77
SB		 2311 status = be_cmd_mac_addr_query(adapter, mac,
2312 MAC_ADDRESS_TYPE_NETWORK, false, adapter->if_handle);
2313 if (!status) {
2314 memcpy(adapter->netdev->dev_addr, mac, ETH_ALEN);
2315 memcpy(adapter->netdev->perm_addr, mac, ETH_ALEN);
2316 }
2317 }
2318
6b7c5b94
SP		 2319 status = be_tx_queues_create(adapter);
2320 if (status != 0)
2321 goto if_destroy;
2322
2323 status = be_rx_queues_create(adapter);
2324 if (status != 0)
2325 goto tx_qs_destroy;
2326
5fb379ee
SP		 2327 status = be_mcc_queues_create(adapter);
2328 if (status != 0)
2329 goto rx_qs_destroy;
6b7c5b94 2330
0dffc83e
AK		 2331 adapter->link_speed = -1;
2332
6b7c5b94
SP		 2333 return 0;
2334
6d87f5c3 2335 be_mcc_queues_destroy(adapter);
5fb379ee
SP		 2336rx_qs_destroy:
2337 be_rx_queues_destroy(adapter);
6b7c5b94
SP		 2338tx_qs_destroy:
2339 be_tx_queues_destroy(adapter);
2340if_destroy:
c99ac3e7
AK		 2341 if (be_physfn(adapter) && adapter->sriov_enabled)
2342 for (vf = 0; vf < num_vfs; vf++)
2343 if (adapter->vf_cfg[vf].vf_if_handle)
2344 be_cmd_if_destroy(adapter,
658681f7
AK		 2345 adapter->vf_cfg[vf].vf_if_handle,
2346 vf + 1);
2347 be_cmd_if_destroy(adapter, adapter->if_handle, 0);
6b7c5b94
SP		 2348do_none:
2349 return status;
2350}
2351
5fb379ee
SP		 2352static int be_clear(struct be_adapter *adapter)
2353{
7ab8b0b4
AK		 2354 int vf;
2355
c99ac3e7 2356 if (be_physfn(adapter) && adapter->sriov_enabled)
6d87f5c3
AK		 2357 be_vf_eth_addr_rem(adapter);
2358
1a8887d8 2359 be_mcc_queues_destroy(adapter);
5fb379ee
SP		 2360 be_rx_queues_destroy(adapter);
2361 be_tx_queues_destroy(adapter);
2362
7ab8b0b4
AK		 2363 if (be_physfn(adapter) && adapter->sriov_enabled)
2364 for (vf = 0; vf < num_vfs; vf++)
2365 if (adapter->vf_cfg[vf].vf_if_handle)
2366 be_cmd_if_destroy(adapter,
2367 adapter->vf_cfg[vf].vf_if_handle,
2368 vf + 1);
2369
658681f7 2370 be_cmd_if_destroy(adapter, adapter->if_handle, 0);
5fb379ee 2371
2243e2e9
SP		 2372 /* tell fw we're done with firing cmds */
2373 be_cmd_fw_clean(adapter);
5fb379ee
SP		 2374 return 0;
2375}
2376
6b7c5b94 2377
84517482 2378#define FW_FILE_HDR_SIGN "ServerEngines Corp. "
fa9a6fed 2379static bool be_flash_redboot(struct be_adapter *adapter,
3f0d4560
AK		 2380 const u8 *p, u32 img_start, int image_size,
2381 int hdr_size)
fa9a6fed
SB		 2382{
2383 u32 crc_offset;
2384 u8 flashed_crc[4];
2385 int status;
3f0d4560
AK		 2386
2387 crc_offset = hdr_size + img_start + image_size - 4;
2388
fa9a6fed 2389 p += crc_offset;
3f0d4560
AK		 2390
2391 status = be_cmd_get_flash_crc(adapter, flashed_crc,
f510fc64 2392 (image_size - 4));
fa9a6fed
SB		 2393 if (status) {
2394 dev_err(&adapter->pdev->dev,
2395 "could not get crc from flash, not flashing redboot\n");
2396 return false;
2397 }
2398
2399 /*update redboot only if crc does not match*/
2400 if (!memcmp(flashed_crc, p, 4))
2401 return false;
2402 else
2403 return true;
fa9a6fed
SB		 2404}
2405
3f0d4560 2406static int be_flash_data(struct be_adapter *adapter,
84517482 2407 const struct firmware *fw,
3f0d4560
AK		 2408 struct be_dma_mem *flash_cmd, int num_of_images)
2409
84517482 2410{
3f0d4560
AK		 2411 int status = 0, i, filehdr_size = 0;
2412 u32 total_bytes = 0, flash_op;
84517482
AK		 2413 int num_bytes;
2414 const u8 *p = fw->data;
2415 struct be_cmd_write_flashrom *req = flash_cmd->va;
215faf9c 2416 const struct flash_comp *pflashcomp;
9fe96934 2417 int num_comp;
3f0d4560 2418
215faf9c 2419 static const struct flash_comp gen3_flash_types[9] = {
3f0d4560
AK		 2420 { FLASH_iSCSI_PRIMARY_IMAGE_START_g3, IMG_TYPE_ISCSI_ACTIVE,
2421 FLASH_IMAGE_MAX_SIZE_g3},
2422 { FLASH_REDBOOT_START_g3, IMG_TYPE_REDBOOT,
2423 FLASH_REDBOOT_IMAGE_MAX_SIZE_g3},
2424 { FLASH_iSCSI_BIOS_START_g3, IMG_TYPE_BIOS,
2425 FLASH_BIOS_IMAGE_MAX_SIZE_g3},
2426 { FLASH_PXE_BIOS_START_g3, IMG_TYPE_PXE_BIOS,
2427 FLASH_BIOS_IMAGE_MAX_SIZE_g3},
2428 { FLASH_FCoE_BIOS_START_g3, IMG_TYPE_FCOE_BIOS,
2429 FLASH_BIOS_IMAGE_MAX_SIZE_g3},
2430 { FLASH_iSCSI_BACKUP_IMAGE_START_g3, IMG_TYPE_ISCSI_BACKUP,
2431 FLASH_IMAGE_MAX_SIZE_g3},
2432 { FLASH_FCoE_PRIMARY_IMAGE_START_g3, IMG_TYPE_FCOE_FW_ACTIVE,
2433 FLASH_IMAGE_MAX_SIZE_g3},
2434 { FLASH_FCoE_BACKUP_IMAGE_START_g3, IMG_TYPE_FCOE_FW_BACKUP,
9fe96934
SB		 2435 FLASH_IMAGE_MAX_SIZE_g3},
2436 { FLASH_NCSI_START_g3, IMG_TYPE_NCSI_FW,
2437 FLASH_NCSI_IMAGE_MAX_SIZE_g3}
3f0d4560 2438 };
215faf9c 2439 static const struct flash_comp gen2_flash_types[8] = {
3f0d4560
AK		 2440 { FLASH_iSCSI_PRIMARY_IMAGE_START_g2, IMG_TYPE_ISCSI_ACTIVE,
2441 FLASH_IMAGE_MAX_SIZE_g2},
2442 { FLASH_REDBOOT_START_g2, IMG_TYPE_REDBOOT,
2443 FLASH_REDBOOT_IMAGE_MAX_SIZE_g2},
2444 { FLASH_iSCSI_BIOS_START_g2, IMG_TYPE_BIOS,
2445 FLASH_BIOS_IMAGE_MAX_SIZE_g2},
2446 { FLASH_PXE_BIOS_START_g2, IMG_TYPE_PXE_BIOS,
2447 FLASH_BIOS_IMAGE_MAX_SIZE_g2},
2448 { FLASH_FCoE_BIOS_START_g2, IMG_TYPE_FCOE_BIOS,
2449 FLASH_BIOS_IMAGE_MAX_SIZE_g2},
2450 { FLASH_iSCSI_BACKUP_IMAGE_START_g2, IMG_TYPE_ISCSI_BACKUP,
2451 FLASH_IMAGE_MAX_SIZE_g2},
2452 { FLASH_FCoE_PRIMARY_IMAGE_START_g2, IMG_TYPE_FCOE_FW_ACTIVE,
2453 FLASH_IMAGE_MAX_SIZE_g2},
2454 { FLASH_FCoE_BACKUP_IMAGE_START_g2, IMG_TYPE_FCOE_FW_BACKUP,
2455 FLASH_IMAGE_MAX_SIZE_g2}
2456 };
2457
2458 if (adapter->generation == BE_GEN3) {
2459 pflashcomp = gen3_flash_types;
2460 filehdr_size = sizeof(struct flash_file_hdr_g3);
215faf9c 2461 num_comp = ARRAY_SIZE(gen3_flash_types);
3f0d4560
AK		 2462 } else {
2463 pflashcomp = gen2_flash_types;
2464 filehdr_size = sizeof(struct flash_file_hdr_g2);
215faf9c 2465 num_comp = ARRAY_SIZE(gen2_flash_types);
84517482 2466 }
9fe96934
SB		 2467 for (i = 0; i < num_comp; i++) {
2468 if ((pflashcomp[i].optype == IMG_TYPE_NCSI_FW) &&
2469 memcmp(adapter->fw_ver, "3.102.148.0", 11) < 0)
2470 continue;
3f0d4560
AK		 2471 if ((pflashcomp[i].optype == IMG_TYPE_REDBOOT) &&
2472 (!be_flash_redboot(adapter, fw->data,
fae21a4d
AK		 2473 pflashcomp[i].offset, pflashcomp[i].size, filehdr_size +
2474 (num_of_images * sizeof(struct image_hdr)))))
3f0d4560
AK		 2475 continue;
2476 p = fw->data;
2477 p += filehdr_size + pflashcomp[i].offset
2478 + (num_of_images * sizeof(struct image_hdr));
2479 if (p + pflashcomp[i].size > fw->data + fw->size)
84517482 2480 return -1;
3f0d4560
AK		 2481 total_bytes = pflashcomp[i].size;
2482 while (total_bytes) {
2483 if (total_bytes > 32*1024)
2484 num_bytes = 32*1024;
2485 else
2486 num_bytes = total_bytes;
2487 total_bytes -= num_bytes;
2488
2489 if (!total_bytes)
2490 flash_op = FLASHROM_OPER_FLASH;
2491 else
2492 flash_op = FLASHROM_OPER_SAVE;
2493 memcpy(req->params.data_buf, p, num_bytes);
2494 p += num_bytes;
2495 status = be_cmd_write_flashrom(adapter, flash_cmd,
2496 pflashcomp[i].optype, flash_op, num_bytes);
2497 if (status) {
2498 dev_err(&adapter->pdev->dev,
2499 "cmd to write to flash rom failed.\n");
2500 return -1;
2501 }
2502 yield();
84517482 2503 }
84517482 2504 }
84517482
AK		 2505 return 0;
2506}
2507
3f0d4560
AK		 2508static int get_ufigen_type(struct flash_file_hdr_g2 *fhdr)
2509{
2510 if (fhdr == NULL)
2511 return 0;
2512 if (fhdr->build[0] == '3')
2513 return BE_GEN3;
2514 else if (fhdr->build[0] == '2')
2515 return BE_GEN2;
2516 else
2517 return 0;
2518}
2519
84517482
AK		 2520int be_load_fw(struct be_adapter *adapter, u8 *func)
2521{
2522 char fw_file[ETHTOOL_FLASH_MAX_FILENAME];
2523 const struct firmware *fw;
3f0d4560
AK		 2524 struct flash_file_hdr_g2 *fhdr;
2525 struct flash_file_hdr_g3 *fhdr3;
2526 struct image_hdr *img_hdr_ptr = NULL;
84517482 2527 struct be_dma_mem flash_cmd;
8b93b710 2528 int status, i = 0, num_imgs = 0;
84517482 2529 const u8 *p;
84517482 2530
d9efd2af
SB		 2531 if (!netif_running(adapter->netdev)) {
2532 dev_err(&adapter->pdev->dev,
2533 "Firmware load not allowed (interface is down)\n");
2534 return -EPERM;
2535 }
2536
84517482
AK		 2537 strcpy(fw_file, func);
2538
2539 status = request_firmware(&fw, fw_file, &adapter->pdev->dev);
2540 if (status)
2541 goto fw_exit;
2542
2543 p = fw->data;
3f0d4560 2544 fhdr = (struct flash_file_hdr_g2 *) p;
84517482
AK		 2545 dev_info(&adapter->pdev->dev, "Flashing firmware file %s\n", fw_file);
2546
84517482 2547 flash_cmd.size = sizeof(struct be_cmd_write_flashrom) + 32*1024;
2b7bcebf
IV		 2548 flash_cmd.va = dma_alloc_coherent(&adapter->pdev->dev, flash_cmd.size,
2549 &flash_cmd.dma, GFP_KERNEL);
84517482
AK		 2550 if (!flash_cmd.va) {
2551 status = -ENOMEM;
2552 dev_err(&adapter->pdev->dev,
2553 "Memory allocation failure while flashing\n");
2554 goto fw_exit;
2555 }
2556
3f0d4560
AK		 2557 if ((adapter->generation == BE_GEN3) &&
2558 (get_ufigen_type(fhdr) == BE_GEN3)) {
2559 fhdr3 = (struct flash_file_hdr_g3 *) fw->data;
8b93b710
AK		 2560 num_imgs = le32_to_cpu(fhdr3->num_imgs);
2561 for (i = 0; i < num_imgs; i++) {
3f0d4560
AK		 2562 img_hdr_ptr = (struct image_hdr *) (fw->data +
2563 (sizeof(struct flash_file_hdr_g3) +
8b93b710
AK		 2564 i * sizeof(struct image_hdr)));
2565 if (le32_to_cpu(img_hdr_ptr->imageid) == 1)
2566 status = be_flash_data(adapter, fw, &flash_cmd,
2567 num_imgs);
3f0d4560
AK		 2568 }
2569 } else if ((adapter->generation == BE_GEN2) &&
2570 (get_ufigen_type(fhdr) == BE_GEN2)) {
2571 status = be_flash_data(adapter, fw, &flash_cmd, 0);
2572 } else {
2573 dev_err(&adapter->pdev->dev,
2574 "UFI and Interface are not compatible for flashing\n");
2575 status = -1;
84517482
AK		 2576 }
2577
2b7bcebf
IV		 2578 dma_free_coherent(&adapter->pdev->dev, flash_cmd.size, flash_cmd.va,
2579 flash_cmd.dma);
84517482
AK		 2580 if (status) {
2581 dev_err(&adapter->pdev->dev, "Firmware load error\n");
2582 goto fw_exit;
2583 }
2584
af901ca1 2585 dev_info(&adapter->pdev->dev, "Firmware flashed successfully\n");
84517482
AK		 2586
2587fw_exit:
2588 release_firmware(fw);
2589 return status;
2590}
2591
6b7c5b94
SP		 2592static struct net_device_ops be_netdev_ops = {
2593 .ndo_open = be_open,
2594 .ndo_stop = be_close,
2595 .ndo_start_xmit = be_xmit,
6b7c5b94
SP		 2596 .ndo_set_rx_mode = be_set_multicast_list,
2597 .ndo_set_mac_address = be_mac_addr_set,
2598 .ndo_change_mtu = be_change_mtu,
2599 .ndo_validate_addr = eth_validate_addr,
2600 .ndo_vlan_rx_register = be_vlan_register,
2601 .ndo_vlan_rx_add_vid = be_vlan_add_vid,
2602 .ndo_vlan_rx_kill_vid = be_vlan_rem_vid,
64600ea5 2603 .ndo_set_vf_mac = be_set_vf_mac,
1da87b7f 2604 .ndo_set_vf_vlan = be_set_vf_vlan,
e1d18735 2605 .ndo_set_vf_tx_rate = be_set_vf_tx_rate,
64600ea5 2606 .ndo_get_vf_config = be_get_vf_config
6b7c5b94
SP		 2607};
2608
2609static void be_netdev_init(struct net_device *netdev)
2610{
2611 struct be_adapter *adapter = netdev_priv(netdev);
3abcdeda
SP		 2612 struct be_rx_obj *rxo;
2613 int i;
6b7c5b94
SP		 2614
2615 netdev->features |= NETIF_F_SG | NETIF_F_HW_VLAN_RX | NETIF_F_TSO |
79032644
MM		 2616 NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_FILTER |
2617 NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
49e4b847 2618 NETIF_F_GRO | NETIF_F_TSO6;
6b7c5b94 2619
79032644
MM		 2620 netdev->vlan_features |= NETIF_F_SG | NETIF_F_TSO |
2621 NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM;
51c59870 2622
fe6d2a38
SP		 2623 if (lancer_chip(adapter))
2624 netdev->vlan_features |= NETIF_F_TSO6;
2625
6b7c5b94
SP		 2626 netdev->flags |= IFF_MULTICAST;
2627
728a9972
AK		 2628 adapter->rx_csum = true;
2629
9e90c961
AK		 2630 /* Default settings for Rx and Tx flow control */
2631 adapter->rx_fc = true;
2632 adapter->tx_fc = true;
2633
c190e3c8
AK		 2634 netif_set_gso_max_size(netdev, 65535);
2635
6b7c5b94
SP		 2636 BE_SET_NETDEV_OPS(netdev, &be_netdev_ops);
2637
2638 SET_ETHTOOL_OPS(netdev, &be_ethtool_ops);
2639
3abcdeda
SP		 2640 for_all_rx_queues(adapter, rxo, i)
2641 netif_napi_add(netdev, &rxo->rx_eq.napi, be_poll_rx,
2642 BE_NAPI_WEIGHT);
2643
5fb379ee 2644 netif_napi_add(netdev, &adapter->tx_eq.napi, be_poll_tx_mcc,
6b7c5b94 2645 BE_NAPI_WEIGHT);
6b7c5b94
SP		 2646}
2647
2648static void be_unmap_pci_bars(struct be_adapter *adapter)
2649{
8788fdc2
SP		 2650 if (adapter->csr)
2651 iounmap(adapter->csr);
2652 if (adapter->db)
2653 iounmap(adapter->db);
ba343c77 2654 if (adapter->pcicfg && be_physfn(adapter))
8788fdc2 2655 iounmap(adapter->pcicfg);
6b7c5b94
SP		 2656}
2657
2658static int be_map_pci_bars(struct be_adapter *adapter)
2659{
2660 u8 __iomem *addr;
ba343c77 2661 int pcicfg_reg, db_reg;
6b7c5b94 2662
fe6d2a38
SP		 2663 if (lancer_chip(adapter)) {
2664 addr = ioremap_nocache(pci_resource_start(adapter->pdev, 0),
2665 pci_resource_len(adapter->pdev, 0));
2666 if (addr == NULL)
2667 return -ENOMEM;
2668 adapter->db = addr;
2669 return 0;
2670 }
2671
ba343c77
SB		 2672 if (be_physfn(adapter)) {
2673 addr = ioremap_nocache(pci_resource_start(adapter->pdev, 2),
2674 pci_resource_len(adapter->pdev, 2));
2675 if (addr == NULL)
2676 return -ENOMEM;
2677 adapter->csr = addr;
2678 }
6b7c5b94 2679
ba343c77 2680 if (adapter->generation == BE_GEN2) {
7b139c83 2681 pcicfg_reg = 1;
ba343c77
SB		 2682 db_reg = 4;
2683 } else {
7b139c83 2684 pcicfg_reg = 0;
ba343c77
SB		 2685 if (be_physfn(adapter))
2686 db_reg = 4;
2687 else
2688 db_reg = 0;
2689 }
2690 addr = ioremap_nocache(pci_resource_start(adapter->pdev, db_reg),
2691 pci_resource_len(adapter->pdev, db_reg));
6b7c5b94
SP		 2692 if (addr == NULL)
2693 goto pci_map_err;
ba343c77
SB		 2694 adapter->db = addr;
2695
2696 if (be_physfn(adapter)) {
2697 addr = ioremap_nocache(
2698 pci_resource_start(adapter->pdev, pcicfg_reg),
2699 pci_resource_len(adapter->pdev, pcicfg_reg));
2700 if (addr == NULL)
2701 goto pci_map_err;
2702 adapter->pcicfg = addr;
2703 } else
2704 adapter->pcicfg = adapter->db + SRIOV_VF_PCICFG_OFFSET;
6b7c5b94
SP		 2705
2706 return 0;
2707pci_map_err:
2708 be_unmap_pci_bars(adapter);
2709 return -ENOMEM;
2710}
2711
2712
2713static void be_ctrl_cleanup(struct be_adapter *adapter)
2714{
8788fdc2 2715 struct be_dma_mem *mem = &adapter->mbox_mem_alloced;
6b7c5b94
SP		 2716
2717 be_unmap_pci_bars(adapter);
2718
2719 if (mem->va)
2b7bcebf
IV		 2720 dma_free_coherent(&adapter->pdev->dev, mem->size, mem->va,
2721 mem->dma);
e7b909a6
SP		 2722
2723 mem = &adapter->mc_cmd_mem;
2724 if (mem->va)
2b7bcebf
IV		 2725 dma_free_coherent(&adapter->pdev->dev, mem->size, mem->va,
2726 mem->dma);
6b7c5b94
SP		 2727}
2728
6b7c5b94
SP		 2729static int be_ctrl_init(struct be_adapter *adapter)
2730{
8788fdc2
SP		 2731 struct be_dma_mem *mbox_mem_alloc = &adapter->mbox_mem_alloced;
2732 struct be_dma_mem *mbox_mem_align = &adapter->mbox_mem;
e7b909a6 2733 struct be_dma_mem *mc_cmd_mem = &adapter->mc_cmd_mem;
6b7c5b94 2734 int status;
6b7c5b94
SP		 2735
2736 status = be_map_pci_bars(adapter);
2737 if (status)
e7b909a6 2738 goto done;
6b7c5b94
SP		 2739
2740 mbox_mem_alloc->size = sizeof(struct be_mcc_mailbox) + 16;
2b7bcebf
IV		 2741 mbox_mem_alloc->va = dma_alloc_coherent(&adapter->pdev->dev,
2742 mbox_mem_alloc->size,
2743 &mbox_mem_alloc->dma,
2744 GFP_KERNEL);
6b7c5b94 2745 if (!mbox_mem_alloc->va) {
e7b909a6
SP		 2746 status = -ENOMEM;
2747 goto unmap_pci_bars;
6b7c5b94 2748 }
e7b909a6 2749
6b7c5b94
SP		 2750 mbox_mem_align->size = sizeof(struct be_mcc_mailbox);
2751 mbox_mem_align->va = PTR_ALIGN(mbox_mem_alloc->va, 16);
2752 mbox_mem_align->dma = PTR_ALIGN(mbox_mem_alloc->dma, 16);
2753 memset(mbox_mem_align->va, 0, sizeof(struct be_mcc_mailbox));
e7b909a6
SP		 2754
2755 mc_cmd_mem->size = sizeof(struct be_cmd_req_mcast_mac_config);
2b7bcebf
IV		 2756 mc_cmd_mem->va = dma_alloc_coherent(&adapter->pdev->dev,
2757 mc_cmd_mem->size, &mc_cmd_mem->dma,
2758 GFP_KERNEL);
e7b909a6
SP		 2759 if (mc_cmd_mem->va == NULL) {
2760 status = -ENOMEM;
2761 goto free_mbox;
2762 }
2763 memset(mc_cmd_mem->va, 0, mc_cmd_mem->size);
2764
2984961c 2765 mutex_init(&adapter->mbox_lock);
8788fdc2
SP		 2766 spin_lock_init(&adapter->mcc_lock);
2767 spin_lock_init(&adapter->mcc_cq_lock);
a8f447bd 2768
dd131e76 2769 init_completion(&adapter->flash_compl);
cf588477 2770 pci_save_state(adapter->pdev);
6b7c5b94 2771 return 0;
e7b909a6
SP		 2772
2773free_mbox:
2b7bcebf
IV		 2774 dma_free_coherent(&adapter->pdev->dev, mbox_mem_alloc->size,
2775 mbox_mem_alloc->va, mbox_mem_alloc->dma);
e7b909a6
SP		 2776
2777unmap_pci_bars:
2778 be_unmap_pci_bars(adapter);
2779
2780done:
2781 return status;
6b7c5b94
SP		 2782}
2783
2784static void be_stats_cleanup(struct be_adapter *adapter)
2785{
3abcdeda 2786 struct be_dma_mem *cmd = &adapter->stats_cmd;
6b7c5b94
SP		 2787
2788 if (cmd->va)
2b7bcebf
IV		 2789 dma_free_coherent(&adapter->pdev->dev, cmd->size,
2790 cmd->va, cmd->dma);
6b7c5b94
SP		 2791}
2792
2793static int be_stats_init(struct be_adapter *adapter)
2794{
3abcdeda 2795 struct be_dma_mem *cmd = &adapter->stats_cmd;
6b7c5b94
SP		 2796
2797 cmd->size = sizeof(struct be_cmd_req_get_stats);
2b7bcebf
IV		 2798 cmd->va = dma_alloc_coherent(&adapter->pdev->dev, cmd->size, &cmd->dma,
2799 GFP_KERNEL);
6b7c5b94
SP		 2800 if (cmd->va == NULL)
2801 return -1;
d291b9af 2802 memset(cmd->va, 0, cmd->size);
6b7c5b94
SP		 2803 return 0;
2804}
2805
2806static void __devexit be_remove(struct pci_dev *pdev)
2807{
2808 struct be_adapter *adapter = pci_get_drvdata(pdev);
8d56ff11 2809
6b7c5b94
SP		 2810 if (!adapter)
2811 return;
2812
f203af70
SK		 2813 cancel_delayed_work_sync(&adapter->work);
2814
6b7c5b94
SP		 2815 unregister_netdev(adapter->netdev);
2816
5fb379ee
SP		 2817 be_clear(adapter);
2818
6b7c5b94
SP		 2819 be_stats_cleanup(adapter);
2820
2821 be_ctrl_cleanup(adapter);
2822
ba343c77
SB		 2823 be_sriov_disable(adapter);
2824
8d56ff11 2825 be_msix_disable(adapter);
6b7c5b94
SP		 2826
2827 pci_set_drvdata(pdev, NULL);
2828 pci_release_regions(pdev);
2829 pci_disable_device(pdev);
2830
2831 free_netdev(adapter->netdev);
2832}
2833
2243e2e9 2834static int be_get_config(struct be_adapter *adapter)
6b7c5b94 2835{
6b7c5b94 2836 int status;
2243e2e9 2837 u8 mac[ETH_ALEN];
6b7c5b94 2838
2243e2e9 2839 status = be_cmd_get_fw_ver(adapter, adapter->fw_ver);
6b7c5b94
SP		 2840 if (status)
2841 return status;
2842
3abcdeda
SP		 2843 status = be_cmd_query_fw_cfg(adapter, &adapter->port_num,
2844 &adapter->function_mode, &adapter->function_caps);
43a04fdc
SP		 2845 if (status)
2846 return status;
2847
2243e2e9 2848 memset(mac, 0, ETH_ALEN);
ba343c77
SB		 2849
2850 if (be_physfn(adapter)) {
2851 status = be_cmd_mac_addr_query(adapter, mac,
2243e2e9 2852 MAC_ADDRESS_TYPE_NETWORK, true /*permanent */, 0);
ca9e4988 2853
ba343c77
SB		 2854 if (status)
2855 return status;
ca9e4988 2856
ba343c77
SB		 2857 if (!is_valid_ether_addr(mac))
2858 return -EADDRNOTAVAIL;
2859
2860 memcpy(adapter->netdev->dev_addr, mac, ETH_ALEN);
2861 memcpy(adapter->netdev->perm_addr, mac, ETH_ALEN);
2862 }
6b7c5b94 2863
3486be29 2864 if (adapter->function_mode & 0x400)
82903e4b
AK		 2865 adapter->max_vlans = BE_NUM_VLANS_SUPPORTED/4;
2866 else
2867 adapter->max_vlans = BE_NUM_VLANS_SUPPORTED;
2868
9e1453c5
AK		 2869 status = be_cmd_get_cntl_attributes(adapter);
2870 if (status)
2871 return status;
2872
2e588f84 2873 be_cmd_check_native_mode(adapter);
2243e2e9 2874 return 0;
6b7c5b94
SP		 2875}
2876
fe6d2a38
SP		 2877static int be_dev_family_check(struct be_adapter *adapter)
2878{
2879 struct pci_dev *pdev = adapter->pdev;
2880 u32 sli_intf = 0, if_type;
2881
2882 switch (pdev->device) {
2883 case BE_DEVICE_ID1:
2884 case OC_DEVICE_ID1:
2885 adapter->generation = BE_GEN2;
2886 break;
2887 case BE_DEVICE_ID2:
2888 case OC_DEVICE_ID2:
2889 adapter->generation = BE_GEN3;
2890 break;
2891 case OC_DEVICE_ID3:
2892 pci_read_config_dword(pdev, SLI_INTF_REG_OFFSET, &sli_intf);
2893 if_type = (sli_intf & SLI_INTF_IF_TYPE_MASK) >>
2894 SLI_INTF_IF_TYPE_SHIFT;
2895
2896 if (((sli_intf & SLI_INTF_VALID_MASK) != SLI_INTF_VALID) ||
2897 if_type != 0x02) {
2898 dev_err(&pdev->dev, "SLI_INTF reg val is not valid\n");
2899 return -EINVAL;
2900 }
2901 if (num_vfs > 0) {
2902 dev_err(&pdev->dev, "VFs not supported\n");
2903 return -EINVAL;
2904 }
2905 adapter->sli_family = ((sli_intf & SLI_INTF_FAMILY_MASK) >>
2906 SLI_INTF_FAMILY_SHIFT);
2907 adapter->generation = BE_GEN3;
2908 break;
2909 default:
2910 adapter->generation = 0;
2911 }
2912 return 0;
2913}
2914
37eed1cb
PR		 2915static int lancer_wait_ready(struct be_adapter *adapter)
2916{
2917#define SLIPORT_READY_TIMEOUT 500
2918 u32 sliport_status;
2919 int status = 0, i;
2920
2921 for (i = 0; i < SLIPORT_READY_TIMEOUT; i++) {
2922 sliport_status = ioread32(adapter->db + SLIPORT_STATUS_OFFSET);
2923 if (sliport_status & SLIPORT_STATUS_RDY_MASK)
2924 break;
2925
2926 msleep(20);
2927 }
2928
2929 if (i == SLIPORT_READY_TIMEOUT)
2930 status = -1;
2931
2932 return status;
2933}
2934
2935static int lancer_test_and_set_rdy_state(struct be_adapter *adapter)
2936{
2937 int status;
2938 u32 sliport_status, err, reset_needed;
2939 status = lancer_wait_ready(adapter);
2940 if (!status) {
2941 sliport_status = ioread32(adapter->db + SLIPORT_STATUS_OFFSET);
2942 err = sliport_status & SLIPORT_STATUS_ERR_MASK;
2943 reset_needed = sliport_status & SLIPORT_STATUS_RN_MASK;
2944 if (err && reset_needed) {
2945 iowrite32(SLI_PORT_CONTROL_IP_MASK,
2946 adapter->db + SLIPORT_CONTROL_OFFSET);
2947
2948 /* check adapter has corrected the error */
2949 status = lancer_wait_ready(adapter);
2950 sliport_status = ioread32(adapter->db +
2951 SLIPORT_STATUS_OFFSET);
2952 sliport_status &= (SLIPORT_STATUS_ERR_MASK |
2953 SLIPORT_STATUS_RN_MASK);
2954 if (status || sliport_status)
2955 status = -1;
2956 } else if (err || reset_needed) {
2957 status = -1;
2958 }
2959 }
2960 return status;
2961}
2962
6b7c5b94
SP		 2963static int __devinit be_probe(struct pci_dev *pdev,
2964 const struct pci_device_id *pdev_id)
2965{
2966 int status = 0;
2967 struct be_adapter *adapter;
2968 struct net_device *netdev;
6b7c5b94
SP		 2969
2970 status = pci_enable_device(pdev);
2971 if (status)
2972 goto do_none;
2973
2974 status = pci_request_regions(pdev, DRV_NAME);
2975 if (status)
2976 goto disable_dev;
2977 pci_set_master(pdev);
2978
2979 netdev = alloc_etherdev(sizeof(struct be_adapter));
2980 if (netdev == NULL) {
2981 status = -ENOMEM;
2982 goto rel_reg;
2983 }
2984 adapter = netdev_priv(netdev);
2985 adapter->pdev = pdev;
2986 pci_set_drvdata(pdev, adapter);
fe6d2a38
SP		 2987
2988 status = be_dev_family_check(adapter);
63657b9c 2989 if (status)
fe6d2a38
SP		 2990 goto free_netdev;
2991
6b7c5b94 2992 adapter->netdev = netdev;
2243e2e9 2993 SET_NETDEV_DEV(netdev, &pdev->dev);
6b7c5b94 2994
2b7bcebf 2995 status = dma_set_mask(&pdev->dev, DMA_BIT_MASK(64));
6b7c5b94
SP		 2996 if (!status) {
2997 netdev->features |= NETIF_F_HIGHDMA;
2998 } else {
2b7bcebf 2999 status = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
6b7c5b94
SP		 3000 if (status) {
3001 dev_err(&pdev->dev, "Could not set PCI DMA Mask\n");
3002 goto free_netdev;
3003 }
3004 }
3005
ba343c77
SB		 3006 be_sriov_enable(adapter);
3007
6b7c5b94
SP		 3008 status = be_ctrl_init(adapter);
3009 if (status)
3010 goto free_netdev;
3011
37eed1cb
PR		 3012 if (lancer_chip(adapter)) {
3013 status = lancer_test_and_set_rdy_state(adapter);
3014 if (status) {
3015 dev_err(&pdev->dev, "Adapter in non recoverable error\n");
3016 goto free_netdev;
3017 }
3018 }
3019
2243e2e9 3020 /* sync up with fw's ready state */
ba343c77
SB		 3021 if (be_physfn(adapter)) {
3022 status = be_cmd_POST(adapter);
3023 if (status)
3024 goto ctrl_clean;
ba343c77 3025 }
6b7c5b94 3026
2243e2e9
SP		 3027 /* tell fw we're ready to fire cmds */
3028 status = be_cmd_fw_init(adapter);
6b7c5b94 3029 if (status)
2243e2e9
SP		 3030 goto ctrl_clean;
3031
a4b4dfab
AK		 3032 status = be_cmd_reset_function(adapter);
3033 if (status)
3034 goto ctrl_clean;
556ae191 3035
2243e2e9
SP		 3036 status = be_stats_init(adapter);
3037 if (status)
3038 goto ctrl_clean;
3039
3040 status = be_get_config(adapter);
6b7c5b94
SP		 3041 if (status)
3042 goto stats_clean;
6b7c5b94 3043
3abcdeda
SP		 3044 be_msix_enable(adapter);
3045
6b7c5b94 3046 INIT_DELAYED_WORK(&adapter->work, be_worker);
6b7c5b94 3047
5fb379ee
SP		 3048 status = be_setup(adapter);
3049 if (status)
3abcdeda 3050 goto msix_disable;
2243e2e9 3051
3abcdeda 3052 be_netdev_init(netdev);
6b7c5b94
SP		 3053 status = register_netdev(netdev);
3054 if (status != 0)
5fb379ee 3055 goto unsetup;
63a76944 3056 netif_carrier_off(netdev);
6b7c5b94 3057
e6319365
AK		 3058 if (be_physfn(adapter) && adapter->sriov_enabled) {
3059 status = be_vf_eth_addr_config(adapter);
3060 if (status)
3061 goto unreg_netdev;
3062 }
3063
c4ca2374 3064 dev_info(&pdev->dev, "%s port %d\n", nic_name(pdev), adapter->port_num);
f203af70 3065 schedule_delayed_work(&adapter->work, msecs_to_jiffies(100));
6b7c5b94
SP		 3066 return 0;
3067
e6319365
AK		 3068unreg_netdev:
3069 unregister_netdev(netdev);
5fb379ee
SP		 3070unsetup:
3071 be_clear(adapter);
3abcdeda
SP		 3072msix_disable:
3073 be_msix_disable(adapter);
6b7c5b94
SP		 3074stats_clean:
3075 be_stats_cleanup(adapter);
3076ctrl_clean:
3077 be_ctrl_cleanup(adapter);
3078free_netdev:
ba343c77 3079 be_sriov_disable(adapter);
fe6d2a38 3080 free_netdev(netdev);
8d56ff11 3081 pci_set_drvdata(pdev, NULL);
6b7c5b94
SP		 3082rel_reg:
3083 pci_release_regions(pdev);
3084disable_dev:
3085 pci_disable_device(pdev);
3086do_none:
c4ca2374 3087 dev_err(&pdev->dev, "%s initialization failed\n", nic_name(pdev));
6b7c5b94
SP		 3088 return status;
3089}
3090
3091static int be_suspend(struct pci_dev *pdev, pm_message_t state)
3092{
3093 struct be_adapter *adapter = pci_get_drvdata(pdev);
3094 struct net_device *netdev = adapter->netdev;
3095
a4ca055f 3096 cancel_delayed_work_sync(&adapter->work);
71d8d1b5
AK		 3097 if (adapter->wol)
3098 be_setup_wol(adapter, true);
3099
6b7c5b94
SP		 3100 netif_device_detach(netdev);
3101 if (netif_running(netdev)) {
3102 rtnl_lock();
3103 be_close(netdev);
3104 rtnl_unlock();
3105 }
9e90c961 3106 be_cmd_get_flow_control(adapter, &adapter->tx_fc, &adapter->rx_fc);
9b0365f1 3107 be_clear(adapter);
6b7c5b94 3108
a4ca055f 3109 be_msix_disable(adapter);
6b7c5b94
SP		 3110 pci_save_state(pdev);
3111 pci_disable_device(pdev);
3112 pci_set_power_state(pdev, pci_choose_state(pdev, state));
3113 return 0;
3114}
3115
3116static int be_resume(struct pci_dev *pdev)
3117{
3118 int status = 0;
3119 struct be_adapter *adapter = pci_get_drvdata(pdev);
3120 struct net_device *netdev = adapter->netdev;
3121
3122 netif_device_detach(netdev);
3123
3124 status = pci_enable_device(pdev);
3125 if (status)
3126 return status;
3127
3128 pci_set_power_state(pdev, 0);
3129 pci_restore_state(pdev);
3130
a4ca055f 3131 be_msix_enable(adapter);
2243e2e9
SP		 3132 /* tell fw we're ready to fire cmds */
3133 status = be_cmd_fw_init(adapter);
3134 if (status)
3135 return status;
3136
9b0365f1 3137 be_setup(adapter);
6b7c5b94
SP		 3138 if (netif_running(netdev)) {
3139 rtnl_lock();
3140 be_open(netdev);
3141 rtnl_unlock();
3142 }
3143 netif_device_attach(netdev);
71d8d1b5
AK		 3144
3145 if (adapter->wol)
3146 be_setup_wol(adapter, false);
a4ca055f
AK		 3147
3148 schedule_delayed_work(&adapter->work, msecs_to_jiffies(100));
6b7c5b94
SP		 3149 return 0;
3150}
3151
82456b03
SP		 3152/*
3153 * An FLR will stop BE from DMAing any data.
3154 */
3155static void be_shutdown(struct pci_dev *pdev)
3156{
3157 struct be_adapter *adapter = pci_get_drvdata(pdev);
3158 struct net_device *netdev = adapter->netdev;
3159
a4ca055f
AK		 3160 if (netif_running(netdev))
3161 cancel_delayed_work_sync(&adapter->work);
3162
82456b03
SP		 3163 netif_device_detach(netdev);
3164
3165 be_cmd_reset_function(adapter);
3166
3167 if (adapter->wol)
3168 be_setup_wol(adapter, true);
3169
3170 pci_disable_device(pdev);
82456b03
SP		 3171}
3172
cf588477
SP		 3173static pci_ers_result_t be_eeh_err_detected(struct pci_dev *pdev,
3174 pci_channel_state_t state)
3175{
3176 struct be_adapter *adapter = pci_get_drvdata(pdev);
3177 struct net_device *netdev = adapter->netdev;
3178
3179 dev_err(&adapter->pdev->dev, "EEH error detected\n");
3180
3181 adapter->eeh_err = true;
3182
3183 netif_device_detach(netdev);
3184
3185 if (netif_running(netdev)) {
3186 rtnl_lock();
3187 be_close(netdev);
3188 rtnl_unlock();
3189 }
3190 be_clear(adapter);
3191
3192 if (state == pci_channel_io_perm_failure)
3193 return PCI_ERS_RESULT_DISCONNECT;
3194
3195 pci_disable_device(pdev);
3196
3197 return PCI_ERS_RESULT_NEED_RESET;
3198}
3199
3200static pci_ers_result_t be_eeh_reset(struct pci_dev *pdev)
3201{
3202 struct be_adapter *adapter = pci_get_drvdata(pdev);
3203 int status;
3204
3205 dev_info(&adapter->pdev->dev, "EEH reset\n");
3206 adapter->eeh_err = false;
3207
3208 status = pci_enable_device(pdev);
3209 if (status)
3210 return PCI_ERS_RESULT_DISCONNECT;
3211
3212 pci_set_master(pdev);
3213 pci_set_power_state(pdev, 0);
3214 pci_restore_state(pdev);
3215
3216 /* Check if card is ok and fw is ready */
3217 status = be_cmd_POST(adapter);
3218 if (status)
3219 return PCI_ERS_RESULT_DISCONNECT;
3220
3221 return PCI_ERS_RESULT_RECOVERED;
3222}
3223
3224static void be_eeh_resume(struct pci_dev *pdev)
3225{
3226 int status = 0;
3227 struct be_adapter *adapter = pci_get_drvdata(pdev);
3228 struct net_device *netdev = adapter->netdev;
3229
3230 dev_info(&adapter->pdev->dev, "EEH resume\n");
3231
3232 pci_save_state(pdev);
3233
3234 /* tell fw we're ready to fire cmds */
3235 status = be_cmd_fw_init(adapter);
3236 if (status)
3237 goto err;
3238
3239 status = be_setup(adapter);
3240 if (status)
3241 goto err;
3242
3243 if (netif_running(netdev)) {
3244 status = be_open(netdev);
3245 if (status)
3246 goto err;
3247 }
3248 netif_device_attach(netdev);
3249 return;
3250err:
3251 dev_err(&adapter->pdev->dev, "EEH resume failed\n");
cf588477
SP		 3252}
3253
3254static struct pci_error_handlers be_eeh_handlers = {
3255 .error_detected = be_eeh_err_detected,
3256 .slot_reset = be_eeh_reset,
3257 .resume = be_eeh_resume,
3258};
3259
6b7c5b94
SP		 3260static struct pci_driver be_driver = {
3261 .name = DRV_NAME,
3262 .id_table = be_dev_ids,
3263 .probe = be_probe,
3264 .remove = be_remove,
3265 .suspend = be_suspend,
cf588477 3266 .resume = be_resume,
82456b03 3267 .shutdown = be_shutdown,
cf588477 3268 .err_handler = &be_eeh_handlers
6b7c5b94
SP		 3269};
3270
3271static int __init be_init_module(void)
3272{
8e95a202
JP		 3273 if (rx_frag_size != 8192 && rx_frag_size != 4096 &&
3274 rx_frag_size != 2048) {
6b7c5b94
SP		 3275 printk(KERN_WARNING DRV_NAME
3276 " : Module param rx_frag_size must be 2048/4096/8192."
3277 " Using 2048\n");
3278 rx_frag_size = 2048;
3279 }
6b7c5b94 3280
ba343c77
SB		 3281 if (num_vfs > 32) {
3282 printk(KERN_WARNING DRV_NAME
3283 " : Module param num_vfs must not be greater than 32."
3284 "Using 32\n");
3285 num_vfs = 32;
3286 }
3287
6b7c5b94
SP		 3288 return pci_register_driver(&be_driver);
3289}
3290module_init(be_init_module);
3291
3292static void __exit be_exit_module(void)
3293{
3294 pci_unregister_driver(&be_driver);
3295}
3296module_exit(be_exit_module);
Linux kernel - Deliverables
This page took 0.427176 seconds and 5 git commands to generate.