projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
r8169: enable 64-bit DMA by default for PCI Express devices (v2)
[deliverable/linux.git] / drivers / net / benet / be_main.c
CommitLineData
6b7c5b94
SP		 1/*
2 * Copyright (C) 2005 - 2009 ServerEngines
3 * All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License version 2
7 * as published by the Free Software Foundation. The full GNU General
8 * Public License is included in this distribution in the file called COPYING.
9 *
10 * Contact Information:
11 * linux-drivers@serverengines.com
12 *
13 * ServerEngines
14 * 209 N. Fair Oaks Ave
15 * Sunnyvale, CA 94085
16 */
17
18#include "be.h"
8788fdc2 19#include "be_cmds.h"
65f71b8b 20#include <asm/div64.h>
6b7c5b94
SP		 21
22MODULE_VERSION(DRV_VER);
23MODULE_DEVICE_TABLE(pci, be_dev_ids);
24MODULE_DESCRIPTION(DRV_DESC " " DRV_VER);
25MODULE_AUTHOR("ServerEngines Corporation");
26MODULE_LICENSE("GPL");
27
28static unsigned int rx_frag_size = 2048;
29module_param(rx_frag_size, uint, S_IRUGO);
30MODULE_PARM_DESC(rx_frag_size, "Size of a fragment that holds rcvd data.");
31
6b7c5b94 32static DEFINE_PCI_DEVICE_TABLE(be_dev_ids) = {
c4ca2374 33 { PCI_DEVICE(BE_VENDOR_ID, BE_DEVICE_ID1) },
59fd5d87 34 { PCI_DEVICE(BE_VENDOR_ID, BE_DEVICE_ID2) },
c4ca2374
AK		 35 { PCI_DEVICE(BE_VENDOR_ID, OC_DEVICE_ID1) },
36 { PCI_DEVICE(BE_VENDOR_ID, OC_DEVICE_ID2) },
6b7c5b94
SP		 37 { 0 }
38};
39MODULE_DEVICE_TABLE(pci, be_dev_ids);
40
41static void be_queue_free(struct be_adapter *adapter, struct be_queue_info *q)
42{
43 struct be_dma_mem *mem = &q->dma_mem;
44 if (mem->va)
45 pci_free_consistent(adapter->pdev, mem->size,
46 mem->va, mem->dma);
47}
48
49static int be_queue_alloc(struct be_adapter *adapter, struct be_queue_info *q,
50 u16 len, u16 entry_size)
51{
52 struct be_dma_mem *mem = &q->dma_mem;
53
54 memset(q, 0, sizeof(*q));
55 q->len = len;
56 q->entry_size = entry_size;
57 mem->size = len * entry_size;
58 mem->va = pci_alloc_consistent(adapter->pdev, mem->size, &mem->dma);
59 if (!mem->va)
60 return -1;
61 memset(mem->va, 0, mem->size);
62 return 0;
63}
64
8788fdc2 65static void be_intr_set(struct be_adapter *adapter, bool enable)
6b7c5b94 66{
8788fdc2 67 u8 __iomem *addr = adapter->pcicfg + PCICFG_MEMBAR_CTRL_INT_CTRL_OFFSET;
6b7c5b94
SP		 68 u32 reg = ioread32(addr);
69 u32 enabled = reg & MEMBAR_CTRL_INT_CTRL_HOSTINTR_MASK;
5f0b849e 70
cf588477
SP		 71 if (adapter->eeh_err)
72 return;
73
5f0b849e 74 if (!enabled && enable)
6b7c5b94 75 reg |= MEMBAR_CTRL_INT_CTRL_HOSTINTR_MASK;
5f0b849e 76 else if (enabled && !enable)
6b7c5b94 77 reg &= ~MEMBAR_CTRL_INT_CTRL_HOSTINTR_MASK;
5f0b849e 78 else
6b7c5b94 79 return;
5f0b849e 80
6b7c5b94
SP		 81 iowrite32(reg, addr);
82}
83
8788fdc2 84static void be_rxq_notify(struct be_adapter *adapter, u16 qid, u16 posted)
6b7c5b94
SP		 85{
86 u32 val = 0;
87 val |= qid & DB_RQ_RING_ID_MASK;
88 val |= posted << DB_RQ_NUM_POSTED_SHIFT;
8788fdc2 89 iowrite32(val, adapter->db + DB_RQ_OFFSET);
6b7c5b94
SP		 90}
91
8788fdc2 92static void be_txq_notify(struct be_adapter *adapter, u16 qid, u16 posted)
6b7c5b94
SP		 93{
94 u32 val = 0;
95 val |= qid & DB_TXULP_RING_ID_MASK;
96 val |= (posted & DB_TXULP_NUM_POSTED_MASK) << DB_TXULP_NUM_POSTED_SHIFT;
8788fdc2 97 iowrite32(val, adapter->db + DB_TXULP1_OFFSET);
6b7c5b94
SP		 98}
99
8788fdc2 100static void be_eq_notify(struct be_adapter *adapter, u16 qid,
6b7c5b94
SP		 101 bool arm, bool clear_int, u16 num_popped)
102{
103 u32 val = 0;
104 val |= qid & DB_EQ_RING_ID_MASK;
cf588477
SP		 105
106 if (adapter->eeh_err)
107 return;
108
6b7c5b94
SP		 109 if (arm)
110 val |= 1 << DB_EQ_REARM_SHIFT;
111 if (clear_int)
112 val |= 1 << DB_EQ_CLR_SHIFT;
113 val |= 1 << DB_EQ_EVNT_SHIFT;
114 val |= num_popped << DB_EQ_NUM_POPPED_SHIFT;
8788fdc2 115 iowrite32(val, adapter->db + DB_EQ_OFFSET);
6b7c5b94
SP		 116}
117
8788fdc2 118void be_cq_notify(struct be_adapter *adapter, u16 qid, bool arm, u16 num_popped)
6b7c5b94
SP		 119{
120 u32 val = 0;
121 val |= qid & DB_CQ_RING_ID_MASK;
cf588477
SP		 122
123 if (adapter->eeh_err)
124 return;
125
6b7c5b94
SP		 126 if (arm)
127 val |= 1 << DB_CQ_REARM_SHIFT;
128 val |= num_popped << DB_CQ_NUM_POPPED_SHIFT;
8788fdc2 129 iowrite32(val, adapter->db + DB_CQ_OFFSET);
6b7c5b94
SP		 130}
131
6b7c5b94
SP		 132static int be_mac_addr_set(struct net_device *netdev, void *p)
133{
134 struct be_adapter *adapter = netdev_priv(netdev);
135 struct sockaddr *addr = p;
136 int status = 0;
137
ca9e4988
AK		 138 if (!is_valid_ether_addr(addr->sa_data))
139 return -EADDRNOTAVAIL;
140
a65027e4
SP		 141 status = be_cmd_pmac_del(adapter, adapter->if_handle, adapter->pmac_id);
142 if (status)
143 return status;
6b7c5b94 144
a65027e4
SP		 145 status = be_cmd_pmac_add(adapter, (u8 *)addr->sa_data,
146 adapter->if_handle, &adapter->pmac_id);
6b7c5b94
SP		 147 if (!status)
148 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
149
150 return status;
151}
152
b31c50a7 153void netdev_stats_update(struct be_adapter *adapter)
6b7c5b94
SP		 154{
155 struct be_hw_stats *hw_stats = hw_stats_from_cmd(adapter->stats.cmd.va);
156 struct be_rxf_stats *rxf_stats = &hw_stats->rxf;
157 struct be_port_rxf_stats *port_stats =
158 &rxf_stats->port[adapter->port_num];
78122a52 159 struct net_device_stats *dev_stats = &adapter->netdev->stats;
68110868 160 struct be_erx_stats *erx_stats = &hw_stats->erx;
6b7c5b94
SP		 161
162 dev_stats->rx_packets = port_stats->rx_total_frames;
163 dev_stats->tx_packets = port_stats->tx_unicastframes +
164 port_stats->tx_multicastframes + port_stats->tx_broadcastframes;
165 dev_stats->rx_bytes = (u64) port_stats->rx_bytes_msd << 32 |
166 (u64) port_stats->rx_bytes_lsd;
167 dev_stats->tx_bytes = (u64) port_stats->tx_bytes_msd << 32 |
168 (u64) port_stats->tx_bytes_lsd;
169
170 /* bad pkts received */
171 dev_stats->rx_errors = port_stats->rx_crc_errors +
172 port_stats->rx_alignment_symbol_errors +
173 port_stats->rx_in_range_errors +
68110868
SP		 174 port_stats->rx_out_range_errors +
175 port_stats->rx_frame_too_long +
176 port_stats->rx_dropped_too_small +
177 port_stats->rx_dropped_too_short +
178 port_stats->rx_dropped_header_too_small +
179 port_stats->rx_dropped_tcp_length +
180 port_stats->rx_dropped_runt +
181 port_stats->rx_tcp_checksum_errs +
182 port_stats->rx_ip_checksum_errs +
183 port_stats->rx_udp_checksum_errs;
184
185 /* no space in linux buffers: best possible approximation */
01ed30da
SP		 186 dev_stats->rx_dropped =
187 erx_stats->rx_drops_no_fragments[adapter->rx_obj.q.id];
6b7c5b94
SP		 188
189 /* detailed rx errors */
190 dev_stats->rx_length_errors = port_stats->rx_in_range_errors +
68110868
SP		 191 port_stats->rx_out_range_errors +
192 port_stats->rx_frame_too_long;
193
6b7c5b94
SP		 194 /* receive ring buffer overflow */
195 dev_stats->rx_over_errors = 0;
68110868 196
6b7c5b94
SP		 197 dev_stats->rx_crc_errors = port_stats->rx_crc_errors;
198
199 /* frame alignment errors */
200 dev_stats->rx_frame_errors = port_stats->rx_alignment_symbol_errors;
68110868 201
6b7c5b94
SP		 202 /* receiver fifo overrun */
203 /* drops_no_pbuf is no per i/f, it's per BE card */
204 dev_stats->rx_fifo_errors = port_stats->rx_fifo_overflow +
205 port_stats->rx_input_fifo_overflow +
206 rxf_stats->rx_drops_no_pbuf;
207 /* receiver missed packetd */
208 dev_stats->rx_missed_errors = 0;
68110868
SP		 209
210 /* packet transmit problems */
211 dev_stats->tx_errors = 0;
212
213 /* no space available in linux */
214 dev_stats->tx_dropped = 0;
215
c5b9b92e 216 dev_stats->multicast = port_stats->rx_multicast_frames;
68110868
SP		 217 dev_stats->collisions = 0;
218
6b7c5b94
SP		 219 /* detailed tx_errors */
220 dev_stats->tx_aborted_errors = 0;
221 dev_stats->tx_carrier_errors = 0;
222 dev_stats->tx_fifo_errors = 0;
223 dev_stats->tx_heartbeat_errors = 0;
224 dev_stats->tx_window_errors = 0;
225}
226
8788fdc2 227void be_link_status_update(struct be_adapter *adapter, bool link_up)
6b7c5b94 228{
6b7c5b94
SP		 229 struct net_device *netdev = adapter->netdev;
230
6b7c5b94 231 /* If link came up or went down */
a8f447bd 232 if (adapter->link_up != link_up) {
0dffc83e 233 adapter->link_speed = -1;
a8f447bd 234 if (link_up) {
6b7c5b94
SP		 235 netif_start_queue(netdev);
236 netif_carrier_on(netdev);
237 printk(KERN_INFO "%s: Link up\n", netdev->name);
a8f447bd
SP		 238 } else {
239 netif_stop_queue(netdev);
240 netif_carrier_off(netdev);
241 printk(KERN_INFO "%s: Link down\n", netdev->name);
6b7c5b94 242 }
a8f447bd 243 adapter->link_up = link_up;
6b7c5b94 244 }
6b7c5b94
SP		 245}
246
247/* Update the EQ delay n BE based on the RX frags consumed / sec */
248static void be_rx_eqd_update(struct be_adapter *adapter)
249{
6b7c5b94
SP		 250 struct be_eq_obj *rx_eq = &adapter->rx_eq;
251 struct be_drvr_stats *stats = &adapter->stats.drvr_stats;
4097f663
SP		 252 ulong now = jiffies;
253 u32 eqd;
254
255 if (!rx_eq->enable_aic)
256 return;
257
258 /* Wrapped around */
259 if (time_before(now, stats->rx_fps_jiffies)) {
260 stats->rx_fps_jiffies = now;
261 return;
262 }
6b7c5b94
SP		 263
264 /* Update once a second */
4097f663 265 if ((now - stats->rx_fps_jiffies) < HZ)
6b7c5b94
SP		 266 return;
267
268 stats->be_rx_fps = (stats->be_rx_frags - stats->be_prev_rx_frags) /
4097f663 269 ((now - stats->rx_fps_jiffies) / HZ);
6b7c5b94 270
4097f663 271 stats->rx_fps_jiffies = now;
6b7c5b94
SP		 272 stats->be_prev_rx_frags = stats->be_rx_frags;
273 eqd = stats->be_rx_fps / 110000;
274 eqd = eqd << 3;
275 if (eqd > rx_eq->max_eqd)
276 eqd = rx_eq->max_eqd;
277 if (eqd < rx_eq->min_eqd)
278 eqd = rx_eq->min_eqd;
279 if (eqd < 10)
280 eqd = 0;
281 if (eqd != rx_eq->cur_eqd)
8788fdc2 282 be_cmd_modify_eqd(adapter, rx_eq->q.id, eqd);
6b7c5b94
SP		 283
284 rx_eq->cur_eqd = eqd;
285}
286
6b7c5b94
SP		 287static struct net_device_stats *be_get_stats(struct net_device *dev)
288{
78122a52 289 return &dev->stats;
6b7c5b94
SP		 290}
291
65f71b8b
SH		 292static u32 be_calc_rate(u64 bytes, unsigned long ticks)
293{
294 u64 rate = bytes;
295
296 do_div(rate, ticks / HZ);
297 rate <<= 3; /* bytes/sec -> bits/sec */
298 do_div(rate, 1000000ul); /* MB/Sec */
299
300 return rate;
301}
302
4097f663
SP		 303static void be_tx_rate_update(struct be_adapter *adapter)
304{
305 struct be_drvr_stats *stats = drvr_stats(adapter);
306 ulong now = jiffies;
307
308 /* Wrapped around? */
309 if (time_before(now, stats->be_tx_jiffies)) {
310 stats->be_tx_jiffies = now;
311 return;
312 }
313
314 /* Update tx rate once in two seconds */
315 if ((now - stats->be_tx_jiffies) > 2 * HZ) {
65f71b8b
SH		 316 stats->be_tx_rate = be_calc_rate(stats->be_tx_bytes
317 - stats->be_tx_bytes_prev,
318 now - stats->be_tx_jiffies);
4097f663
SP		 319 stats->be_tx_jiffies = now;
320 stats->be_tx_bytes_prev = stats->be_tx_bytes;
321 }
322}
323
6b7c5b94
SP		 324static void be_tx_stats_update(struct be_adapter *adapter,
325 u32 wrb_cnt, u32 copied, bool stopped)
326{
4097f663 327 struct be_drvr_stats *stats = drvr_stats(adapter);
6b7c5b94
SP		 328 stats->be_tx_reqs++;
329 stats->be_tx_wrbs += wrb_cnt;
330 stats->be_tx_bytes += copied;
331 if (stopped)
332 stats->be_tx_stops++;
6b7c5b94
SP		 333}
334
335/* Determine number of WRB entries needed to xmit data in an skb */
336static u32 wrb_cnt_for_skb(struct sk_buff *skb, bool *dummy)
337{
ebc8d2ab
DM		 338 int cnt = (skb->len > skb->data_len);
339
340 cnt += skb_shinfo(skb)->nr_frags;
341
6b7c5b94
SP		 342 /* to account for hdr wrb */
343 cnt++;
344 if (cnt & 1) {
345 /* add a dummy to make it an even num */
346 cnt++;
347 *dummy = true;
348 } else
349 *dummy = false;
350 BUG_ON(cnt > BE_MAX_TX_FRAG_COUNT);
351 return cnt;
352}
353
354static inline void wrb_fill(struct be_eth_wrb *wrb, u64 addr, int len)
355{
356 wrb->frag_pa_hi = upper_32_bits(addr);
357 wrb->frag_pa_lo = addr & 0xFFFFFFFF;
358 wrb->frag_len = len & ETH_WRB_FRAG_LEN_MASK;
359}
360
361static void wrb_fill_hdr(struct be_eth_hdr_wrb *hdr, struct sk_buff *skb,
362 bool vlan, u32 wrb_cnt, u32 len)
363{
364 memset(hdr, 0, sizeof(*hdr));
365
366 AMAP_SET_BITS(struct amap_eth_hdr_wrb, crc, hdr, 1);
367
368 if (skb_shinfo(skb)->gso_segs > 1 && skb_shinfo(skb)->gso_size) {
369 AMAP_SET_BITS(struct amap_eth_hdr_wrb, lso, hdr, 1);
370 AMAP_SET_BITS(struct amap_eth_hdr_wrb, lso_mss,
371 hdr, skb_shinfo(skb)->gso_size);
372 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
373 if (is_tcp_pkt(skb))
374 AMAP_SET_BITS(struct amap_eth_hdr_wrb, tcpcs, hdr, 1);
375 else if (is_udp_pkt(skb))
376 AMAP_SET_BITS(struct amap_eth_hdr_wrb, udpcs, hdr, 1);
377 }
378
379 if (vlan && vlan_tx_tag_present(skb)) {
380 AMAP_SET_BITS(struct amap_eth_hdr_wrb, vlan, hdr, 1);
381 AMAP_SET_BITS(struct amap_eth_hdr_wrb, vlan_tag,
382 hdr, vlan_tx_tag_get(skb));
383 }
384
385 AMAP_SET_BITS(struct amap_eth_hdr_wrb, event, hdr, 1);
386 AMAP_SET_BITS(struct amap_eth_hdr_wrb, complete, hdr, 1);
387 AMAP_SET_BITS(struct amap_eth_hdr_wrb, num_wrb, hdr, wrb_cnt);
388 AMAP_SET_BITS(struct amap_eth_hdr_wrb, len, hdr, len);
389}
390
391
392static int make_tx_wrbs(struct be_adapter *adapter,
393 struct sk_buff *skb, u32 wrb_cnt, bool dummy_wrb)
394{
395 u64 busaddr;
396 u32 i, copied = 0;
397 struct pci_dev *pdev = adapter->pdev;
398 struct sk_buff *first_skb = skb;
399 struct be_queue_info *txq = &adapter->tx_obj.q;
400 struct be_eth_wrb *wrb;
401 struct be_eth_hdr_wrb *hdr;
402
6b7c5b94 403 hdr = queue_head_node(txq);
c190e3c8 404 atomic_add(wrb_cnt, &txq->used);
6b7c5b94
SP		 405 queue_head_inc(txq);
406
ebc8d2ab
DM		 407 if (skb->len > skb->data_len) {
408 int len = skb->len - skb->data_len;
a73b796e
AD		 409 busaddr = pci_map_single(pdev, skb->data, len,
410 PCI_DMA_TODEVICE);
ebc8d2ab
DM		 411 wrb = queue_head_node(txq);
412 wrb_fill(wrb, busaddr, len);
413 be_dws_cpu_to_le(wrb, sizeof(*wrb));
414 queue_head_inc(txq);
415 copied += len;
416 }
6b7c5b94 417
ebc8d2ab
DM		 418 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
419 struct skb_frag_struct *frag =
420 &skb_shinfo(skb)->frags[i];
a73b796e
AD		 421 busaddr = pci_map_page(pdev, frag->page,
422 frag->page_offset,
423 frag->size, PCI_DMA_TODEVICE);
ebc8d2ab
DM		 424 wrb = queue_head_node(txq);
425 wrb_fill(wrb, busaddr, frag->size);
426 be_dws_cpu_to_le(wrb, sizeof(*wrb));
427 queue_head_inc(txq);
428 copied += frag->size;
6b7c5b94
SP		 429 }
430
431 if (dummy_wrb) {
432 wrb = queue_head_node(txq);
433 wrb_fill(wrb, 0, 0);
434 be_dws_cpu_to_le(wrb, sizeof(*wrb));
435 queue_head_inc(txq);
436 }
437
438 wrb_fill_hdr(hdr, first_skb, adapter->vlan_grp ? true : false,
439 wrb_cnt, copied);
440 be_dws_cpu_to_le(hdr, sizeof(*hdr));
441
442 return copied;
443}
444
61357325 445static netdev_tx_t be_xmit(struct sk_buff *skb,
b31c50a7 446 struct net_device *netdev)
6b7c5b94
SP		 447{
448 struct be_adapter *adapter = netdev_priv(netdev);
449 struct be_tx_obj *tx_obj = &adapter->tx_obj;
450 struct be_queue_info *txq = &tx_obj->q;
451 u32 wrb_cnt = 0, copied = 0;
452 u32 start = txq->head;
453 bool dummy_wrb, stopped = false;
454
455 wrb_cnt = wrb_cnt_for_skb(skb, &dummy_wrb);
456
457 copied = make_tx_wrbs(adapter, skb, wrb_cnt, dummy_wrb);
c190e3c8
AK		 458 if (copied) {
459 /* record the sent skb in the sent_skb table */
460 BUG_ON(tx_obj->sent_skb_list[start]);
461 tx_obj->sent_skb_list[start] = skb;
462
463 /* Ensure txq has space for the next skb; Else stop the queue
464 * *BEFORE* ringing the tx doorbell, so that we serialze the
465 * tx compls of the current transmit which'll wake up the queue
466 */
467 if ((BE_MAX_TX_FRAG_COUNT + atomic_read(&txq->used)) >=
468 txq->len) {
469 netif_stop_queue(netdev);
470 stopped = true;
471 }
6b7c5b94 472
c190e3c8 473 be_txq_notify(adapter, txq->id, wrb_cnt);
6b7c5b94 474
c190e3c8
AK		 475 be_tx_stats_update(adapter, wrb_cnt, copied, stopped);
476 } else {
477 txq->head = start;
478 dev_kfree_skb_any(skb);
6b7c5b94 479 }
6b7c5b94
SP		 480 return NETDEV_TX_OK;
481}
482
483static int be_change_mtu(struct net_device *netdev, int new_mtu)
484{
485 struct be_adapter *adapter = netdev_priv(netdev);
486 if (new_mtu < BE_MIN_MTU ||
34a89b8c
AK		 487 new_mtu > (BE_MAX_JUMBO_FRAME_SIZE -
488 (ETH_HLEN + ETH_FCS_LEN))) {
6b7c5b94
SP		 489 dev_info(&adapter->pdev->dev,
490 "MTU must be between %d and %d bytes\n",
34a89b8c
AK		 491 BE_MIN_MTU,
492 (BE_MAX_JUMBO_FRAME_SIZE - (ETH_HLEN + ETH_FCS_LEN)));
6b7c5b94
SP		 493 return -EINVAL;
494 }
495 dev_info(&adapter->pdev->dev, "MTU changed from %d to %d bytes\n",
496 netdev->mtu, new_mtu);
497 netdev->mtu = new_mtu;
498 return 0;
499}
500
501/*
82903e4b
AK		 502 * A max of 64 (BE_NUM_VLANS_SUPPORTED) vlans can be configured in BE.
503 * If the user configures more, place BE in vlan promiscuous mode.
6b7c5b94 504 */
b31c50a7 505static int be_vid_config(struct be_adapter *adapter)
6b7c5b94 506{
6b7c5b94
SP		 507 u16 vtag[BE_NUM_VLANS_SUPPORTED];
508 u16 ntags = 0, i;
82903e4b 509 int status = 0;
6b7c5b94 510
82903e4b 511 if (adapter->vlans_added <= adapter->max_vlans) {
6b7c5b94
SP		 512 /* Construct VLAN Table to give to HW */
513 for (i = 0; i < VLAN_GROUP_ARRAY_LEN; i++) {
514 if (adapter->vlan_tag[i]) {
515 vtag[ntags] = cpu_to_le16(i);
516 ntags++;
517 }
518 }
b31c50a7
SP		 519 status = be_cmd_vlan_config(adapter, adapter->if_handle,
520 vtag, ntags, 1, 0);
6b7c5b94 521 } else {
b31c50a7
SP		 522 status = be_cmd_vlan_config(adapter, adapter->if_handle,
523 NULL, 0, 1, 1);
6b7c5b94 524 }
b31c50a7 525 return status;
6b7c5b94
SP		 526}
527
528static void be_vlan_register(struct net_device *netdev, struct vlan_group *grp)
529{
530 struct be_adapter *adapter = netdev_priv(netdev);
531 struct be_eq_obj *rx_eq = &adapter->rx_eq;
532 struct be_eq_obj *tx_eq = &adapter->tx_eq;
6b7c5b94 533
8788fdc2
SP		 534 be_eq_notify(adapter, rx_eq->q.id, false, false, 0);
535 be_eq_notify(adapter, tx_eq->q.id, false, false, 0);
6b7c5b94 536 adapter->vlan_grp = grp;
8788fdc2
SP		 537 be_eq_notify(adapter, rx_eq->q.id, true, false, 0);
538 be_eq_notify(adapter, tx_eq->q.id, true, false, 0);
6b7c5b94
SP		 539}
540
541static void be_vlan_add_vid(struct net_device *netdev, u16 vid)
542{
543 struct be_adapter *adapter = netdev_priv(netdev);
544
6b7c5b94 545 adapter->vlan_tag[vid] = 1;
82903e4b
AK		 546 adapter->vlans_added++;
547 if (adapter->vlans_added <= (adapter->max_vlans + 1))
548 be_vid_config(adapter);
6b7c5b94
SP		 549}
550
551static void be_vlan_rem_vid(struct net_device *netdev, u16 vid)
552{
553 struct be_adapter *adapter = netdev_priv(netdev);
554
6b7c5b94 555 adapter->vlan_tag[vid] = 0;
6b7c5b94 556 vlan_group_set_device(adapter->vlan_grp, vid, NULL);
82903e4b
AK		 557 adapter->vlans_added--;
558 if (adapter->vlans_added <= adapter->max_vlans)
559 be_vid_config(adapter);
6b7c5b94
SP		 560}
561
24307eef 562static void be_set_multicast_list(struct net_device *netdev)
6b7c5b94
SP		 563{
564 struct be_adapter *adapter = netdev_priv(netdev);
6b7c5b94 565
24307eef 566 if (netdev->flags & IFF_PROMISC) {
8788fdc2 567 be_cmd_promiscuous_config(adapter, adapter->port_num, 1);
24307eef
SP		 568 adapter->promiscuous = true;
569 goto done;
6b7c5b94
SP		 570 }
571
24307eef
SP		 572 /* BE was previously in promiscous mode; disable it */
573 if (adapter->promiscuous) {
574 adapter->promiscuous = false;
8788fdc2 575 be_cmd_promiscuous_config(adapter, adapter->port_num, 0);
6b7c5b94
SP		 576 }
577
e7b909a6 578 /* Enable multicast promisc if num configured exceeds what we support */
4cd24eaf
JP		 579 if (netdev->flags & IFF_ALLMULTI ||
580 netdev_mc_count(netdev) > BE_MAX_MC) {
e7b909a6
SP		 581 be_cmd_multicast_set(adapter, adapter->if_handle, NULL, 0,
582 &adapter->mc_cmd_mem);
24307eef 583 goto done;
6b7c5b94 584 }
6b7c5b94 585
8788fdc2 586 be_cmd_multicast_set(adapter, adapter->if_handle, netdev->mc_list,
4cd24eaf 587 netdev_mc_count(netdev), &adapter->mc_cmd_mem);
24307eef
SP		 588done:
589 return;
6b7c5b94
SP		 590}
591
4097f663 592static void be_rx_rate_update(struct be_adapter *adapter)
6b7c5b94 593{
4097f663
SP		 594 struct be_drvr_stats *stats = drvr_stats(adapter);
595 ulong now = jiffies;
6b7c5b94 596
4097f663
SP		 597 /* Wrapped around */
598 if (time_before(now, stats->be_rx_jiffies)) {
599 stats->be_rx_jiffies = now;
600 return;
601 }
6b7c5b94
SP		 602
603 /* Update the rate once in two seconds */
4097f663 604 if ((now - stats->be_rx_jiffies) < 2 * HZ)
6b7c5b94
SP		 605 return;
606
65f71b8b
SH		 607 stats->be_rx_rate = be_calc_rate(stats->be_rx_bytes
608 - stats->be_rx_bytes_prev,
609 now - stats->be_rx_jiffies);
4097f663 610 stats->be_rx_jiffies = now;
6b7c5b94
SP		 611 stats->be_rx_bytes_prev = stats->be_rx_bytes;
612}
613
4097f663
SP		 614static void be_rx_stats_update(struct be_adapter *adapter,
615 u32 pktsize, u16 numfrags)
616{
617 struct be_drvr_stats *stats = drvr_stats(adapter);
618
619 stats->be_rx_compl++;
620 stats->be_rx_frags += numfrags;
621 stats->be_rx_bytes += pktsize;
622}
623
728a9972
AK		 624static inline bool do_pkt_csum(struct be_eth_rx_compl *rxcp, bool cso)
625{
626 u8 l4_cksm, ip_version, ipcksm, tcpf = 0, udpf = 0, ipv6_chk;
627
628 l4_cksm = AMAP_GET_BITS(struct amap_eth_rx_compl, l4_cksm, rxcp);
629 ipcksm = AMAP_GET_BITS(struct amap_eth_rx_compl, ipcksm, rxcp);
630 ip_version = AMAP_GET_BITS(struct amap_eth_rx_compl, ip_version, rxcp);
631 if (ip_version) {
632 tcpf = AMAP_GET_BITS(struct amap_eth_rx_compl, tcpf, rxcp);
633 udpf = AMAP_GET_BITS(struct amap_eth_rx_compl, udpf, rxcp);
634 }
635 ipv6_chk = (ip_version && (tcpf || udpf));
636
637 return ((l4_cksm && ipv6_chk && ipcksm) && cso) ? false : true;
638}
639
6b7c5b94
SP		 640static struct be_rx_page_info *
641get_rx_page_info(struct be_adapter *adapter, u16 frag_idx)
642{
643 struct be_rx_page_info *rx_page_info;
644 struct be_queue_info *rxq = &adapter->rx_obj.q;
645
646 rx_page_info = &adapter->rx_obj.page_info_tbl[frag_idx];
647 BUG_ON(!rx_page_info->page);
648
205859a2 649 if (rx_page_info->last_page_user) {
6b7c5b94
SP		 650 pci_unmap_page(adapter->pdev, pci_unmap_addr(rx_page_info, bus),
651 adapter->big_page_size, PCI_DMA_FROMDEVICE);
205859a2
AK		 652 rx_page_info->last_page_user = false;
653 }
6b7c5b94
SP		 654
655 atomic_dec(&rxq->used);
656 return rx_page_info;
657}
658
659/* Throwaway the data in the Rx completion */
660static void be_rx_compl_discard(struct be_adapter *adapter,
661 struct be_eth_rx_compl *rxcp)
662{
663 struct be_queue_info *rxq = &adapter->rx_obj.q;
664 struct be_rx_page_info *page_info;
665 u16 rxq_idx, i, num_rcvd;
666
667 rxq_idx = AMAP_GET_BITS(struct amap_eth_rx_compl, fragndx, rxcp);
668 num_rcvd = AMAP_GET_BITS(struct amap_eth_rx_compl, numfrags, rxcp);
669
670 for (i = 0; i < num_rcvd; i++) {
671 page_info = get_rx_page_info(adapter, rxq_idx);
672 put_page(page_info->page);
673 memset(page_info, 0, sizeof(*page_info));
674 index_inc(&rxq_idx, rxq->len);
675 }
676}
677
678/*
679 * skb_fill_rx_data forms a complete skb for an ether frame
680 * indicated by rxcp.
681 */
682static void skb_fill_rx_data(struct be_adapter *adapter,
89420424
SP		 683 struct sk_buff *skb, struct be_eth_rx_compl *rxcp,
684 u16 num_rcvd)
6b7c5b94
SP		 685{
686 struct be_queue_info *rxq = &adapter->rx_obj.q;
687 struct be_rx_page_info *page_info;
89420424 688 u16 rxq_idx, i, j;
fa77406a 689 u32 pktsize, hdr_len, curr_frag_len, size;
6b7c5b94
SP		 690 u8 *start;
691
692 rxq_idx = AMAP_GET_BITS(struct amap_eth_rx_compl, fragndx, rxcp);
693 pktsize = AMAP_GET_BITS(struct amap_eth_rx_compl, pktsize, rxcp);
6b7c5b94
SP		 694
695 page_info = get_rx_page_info(adapter, rxq_idx);
696
697 start = page_address(page_info->page) + page_info->page_offset;
698 prefetch(start);
699
700 /* Copy data in the first descriptor of this completion */
701 curr_frag_len = min(pktsize, rx_frag_size);
702
703 /* Copy the header portion into skb_data */
704 hdr_len = min((u32)BE_HDR_LEN, curr_frag_len);
705 memcpy(skb->data, start, hdr_len);
706 skb->len = curr_frag_len;
707 if (curr_frag_len <= BE_HDR_LEN) { /* tiny packet */
708 /* Complete packet has now been moved to data */
709 put_page(page_info->page);
710 skb->data_len = 0;
711 skb->tail += curr_frag_len;
712 } else {
713 skb_shinfo(skb)->nr_frags = 1;
714 skb_shinfo(skb)->frags[0].page = page_info->page;
715 skb_shinfo(skb)->frags[0].page_offset =
716 page_info->page_offset + hdr_len;
717 skb_shinfo(skb)->frags[0].size = curr_frag_len - hdr_len;
718 skb->data_len = curr_frag_len - hdr_len;
719 skb->tail += hdr_len;
720 }
205859a2 721 page_info->page = NULL;
6b7c5b94
SP		 722
723 if (pktsize <= rx_frag_size) {
724 BUG_ON(num_rcvd != 1);
76fbb429 725 goto done;
6b7c5b94
SP		 726 }
727
728 /* More frags present for this completion */
fa77406a 729 size = pktsize;
bd46cb6c 730 for (i = 1, j = 0; i < num_rcvd; i++) {
fa77406a 731 size -= curr_frag_len;
6b7c5b94
SP		 732 index_inc(&rxq_idx, rxq->len);
733 page_info = get_rx_page_info(adapter, rxq_idx);
734
fa77406a 735 curr_frag_len = min(size, rx_frag_size);
6b7c5b94 736
bd46cb6c
AK		 737 /* Coalesce all frags from the same physical page in one slot */
738 if (page_info->page_offset == 0) {
739 /* Fresh page */
740 j++;
741 skb_shinfo(skb)->frags[j].page = page_info->page;
742 skb_shinfo(skb)->frags[j].page_offset =
743 page_info->page_offset;
744 skb_shinfo(skb)->frags[j].size = 0;
745 skb_shinfo(skb)->nr_frags++;
746 } else {
747 put_page(page_info->page);
748 }
749
750 skb_shinfo(skb)->frags[j].size += curr_frag_len;
6b7c5b94
SP		 751 skb->len += curr_frag_len;
752 skb->data_len += curr_frag_len;
6b7c5b94 753
205859a2 754 page_info->page = NULL;
6b7c5b94 755 }
bd46cb6c 756 BUG_ON(j > MAX_SKB_FRAGS);
6b7c5b94 757
76fbb429 758done:
4097f663 759 be_rx_stats_update(adapter, pktsize, num_rcvd);
6b7c5b94
SP		 760 return;
761}
762
5be93b9a 763/* Process the RX completion indicated by rxcp when GRO is disabled */
6b7c5b94
SP		 764static void be_rx_compl_process(struct be_adapter *adapter,
765 struct be_eth_rx_compl *rxcp)
766{
767 struct sk_buff *skb;
dcb9b564 768 u32 vlanf, vid;
89420424 769 u16 num_rcvd;
dcb9b564 770 u8 vtm;
6b7c5b94 771
89420424
SP		 772 num_rcvd = AMAP_GET_BITS(struct amap_eth_rx_compl, numfrags, rxcp);
773 /* Is it a flush compl that has no data */
774 if (unlikely(num_rcvd == 0))
775 return;
776
89d71a66 777 skb = netdev_alloc_skb_ip_align(adapter->netdev, BE_HDR_LEN);
a058a632 778 if (unlikely(!skb)) {
6b7c5b94
SP		 779 if (net_ratelimit())
780 dev_warn(&adapter->pdev->dev, "skb alloc failed\n");
781 be_rx_compl_discard(adapter, rxcp);
782 return;
783 }
784
89420424 785 skb_fill_rx_data(adapter, skb, rxcp, num_rcvd);
6b7c5b94 786
728a9972 787 if (do_pkt_csum(rxcp, adapter->rx_csum))
6b7c5b94 788 skb->ip_summed = CHECKSUM_NONE;
728a9972
AK		 789 else
790 skb->ip_summed = CHECKSUM_UNNECESSARY;
6b7c5b94
SP		 791
792 skb->truesize = skb->len + sizeof(struct sk_buff);
793 skb->protocol = eth_type_trans(skb, adapter->netdev);
794 skb->dev = adapter->netdev;
795
a058a632
SP		 796 vlanf = AMAP_GET_BITS(struct amap_eth_rx_compl, vtp, rxcp);
797 vtm = AMAP_GET_BITS(struct amap_eth_rx_compl, vtm, rxcp);
798
799 /* vlanf could be wrongly set in some cards.
800 * ignore if vtm is not set */
801 if ((adapter->cap & 0x400) && !vtm)
802 vlanf = 0;
803
804 if (unlikely(vlanf)) {
82903e4b 805 if (!adapter->vlan_grp || adapter->vlans_added == 0) {
6b7c5b94
SP		 806 kfree_skb(skb);
807 return;
808 }
809 vid = AMAP_GET_BITS(struct amap_eth_rx_compl, vlan_tag, rxcp);
810 vid = be16_to_cpu(vid);
811 vlan_hwaccel_receive_skb(skb, adapter->vlan_grp, vid);
812 } else {
813 netif_receive_skb(skb);
814 }
815
6b7c5b94
SP		 816 return;
817}
818
5be93b9a
AK		 819/* Process the RX completion indicated by rxcp when GRO is enabled */
820static void be_rx_compl_process_gro(struct be_adapter *adapter,
6b7c5b94
SP		 821 struct be_eth_rx_compl *rxcp)
822{
823 struct be_rx_page_info *page_info;
5be93b9a 824 struct sk_buff *skb = NULL;
6b7c5b94 825 struct be_queue_info *rxq = &adapter->rx_obj.q;
5be93b9a 826 struct be_eq_obj *eq_obj = &adapter->rx_eq;
6b7c5b94 827 u32 num_rcvd, pkt_size, remaining, vlanf, curr_frag_len;
bd46cb6c 828 u16 i, rxq_idx = 0, vid, j;
dcb9b564 829 u8 vtm;
6b7c5b94
SP		 830
831 num_rcvd = AMAP_GET_BITS(struct amap_eth_rx_compl, numfrags, rxcp);
89420424
SP		 832 /* Is it a flush compl that has no data */
833 if (unlikely(num_rcvd == 0))
834 return;
835
6b7c5b94
SP		 836 pkt_size = AMAP_GET_BITS(struct amap_eth_rx_compl, pktsize, rxcp);
837 vlanf = AMAP_GET_BITS(struct amap_eth_rx_compl, vtp, rxcp);
838 rxq_idx = AMAP_GET_BITS(struct amap_eth_rx_compl, fragndx, rxcp);
dcb9b564
AK		 839 vtm = AMAP_GET_BITS(struct amap_eth_rx_compl, vtm, rxcp);
840
841 /* vlanf could be wrongly set in some cards.
842 * ignore if vtm is not set */
e1187b3b 843 if ((adapter->cap & 0x400) && !vtm)
dcb9b564 844 vlanf = 0;
6b7c5b94 845
5be93b9a
AK		 846 skb = napi_get_frags(&eq_obj->napi);
847 if (!skb) {
848 be_rx_compl_discard(adapter, rxcp);
849 return;
850 }
851
6b7c5b94 852 remaining = pkt_size;
bd46cb6c 853 for (i = 0, j = -1; i < num_rcvd; i++) {
6b7c5b94
SP		 854 page_info = get_rx_page_info(adapter, rxq_idx);
855
856 curr_frag_len = min(remaining, rx_frag_size);
857
bd46cb6c
AK		 858 /* Coalesce all frags from the same physical page in one slot */
859 if (i == 0 || page_info->page_offset == 0) {
860 /* First frag or Fresh page */
861 j++;
5be93b9a
AK		 862 skb_shinfo(skb)->frags[j].page = page_info->page;
863 skb_shinfo(skb)->frags[j].page_offset =
864 page_info->page_offset;
865 skb_shinfo(skb)->frags[j].size = 0;
bd46cb6c
AK		 866 } else {
867 put_page(page_info->page);
868 }
5be93b9a 869 skb_shinfo(skb)->frags[j].size += curr_frag_len;
6b7c5b94 870
bd46cb6c 871 remaining -= curr_frag_len;
6b7c5b94 872 index_inc(&rxq_idx, rxq->len);
6b7c5b94
SP		 873 memset(page_info, 0, sizeof(*page_info));
874 }
bd46cb6c 875 BUG_ON(j > MAX_SKB_FRAGS);
6b7c5b94 876
5be93b9a
AK		 877 skb_shinfo(skb)->nr_frags = j + 1;
878 skb->len = pkt_size;
879 skb->data_len = pkt_size;
880 skb->truesize += pkt_size;
881 skb->ip_summed = CHECKSUM_UNNECESSARY;
882
6b7c5b94 883 if (likely(!vlanf)) {
5be93b9a 884 napi_gro_frags(&eq_obj->napi);
6b7c5b94
SP		 885 } else {
886 vid = AMAP_GET_BITS(struct amap_eth_rx_compl, vlan_tag, rxcp);
887 vid = be16_to_cpu(vid);
888
82903e4b 889 if (!adapter->vlan_grp || adapter->vlans_added == 0)
6b7c5b94
SP		 890 return;
891
5be93b9a 892 vlan_gro_frags(&eq_obj->napi, adapter->vlan_grp, vid);
6b7c5b94
SP		 893 }
894
4097f663 895 be_rx_stats_update(adapter, pkt_size, num_rcvd);
6b7c5b94
SP		 896 return;
897}
898
899static struct be_eth_rx_compl *be_rx_compl_get(struct be_adapter *adapter)
900{
901 struct be_eth_rx_compl *rxcp = queue_tail_node(&adapter->rx_obj.cq);
902
903 if (rxcp->dw[offsetof(struct amap_eth_rx_compl, valid) / 32] == 0)
904 return NULL;
905
906 be_dws_le_to_cpu(rxcp, sizeof(*rxcp));
907
6b7c5b94
SP		 908 queue_tail_inc(&adapter->rx_obj.cq);
909 return rxcp;
910}
911
a7a0ef31
SP		 912/* To reset the valid bit, we need to reset the whole word as
913 * when walking the queue the valid entries are little-endian
914 * and invalid entries are host endian
915 */
916static inline void be_rx_compl_reset(struct be_eth_rx_compl *rxcp)
917{
918 rxcp->dw[offsetof(struct amap_eth_rx_compl, valid) / 32] = 0;
919}
920
6b7c5b94
SP		 921static inline struct page *be_alloc_pages(u32 size)
922{
923 gfp_t alloc_flags = GFP_ATOMIC;
924 u32 order = get_order(size);
925 if (order > 0)
926 alloc_flags |= __GFP_COMP;
927 return alloc_pages(alloc_flags, order);
928}
929
930/*
931 * Allocate a page, split it to fragments of size rx_frag_size and post as
932 * receive buffers to BE
933 */
934static void be_post_rx_frags(struct be_adapter *adapter)
935{
936 struct be_rx_page_info *page_info_tbl = adapter->rx_obj.page_info_tbl;
26d92f92 937 struct be_rx_page_info *page_info = NULL, *prev_page_info = NULL;
6b7c5b94
SP		 938 struct be_queue_info *rxq = &adapter->rx_obj.q;
939 struct page *pagep = NULL;
940 struct be_eth_rx_d *rxd;
941 u64 page_dmaaddr = 0, frag_dmaaddr;
942 u32 posted, page_offset = 0;
943
6b7c5b94
SP		 944 page_info = &page_info_tbl[rxq->head];
945 for (posted = 0; posted < MAX_RX_POST && !page_info->page; posted++) {
946 if (!pagep) {
947 pagep = be_alloc_pages(adapter->big_page_size);
948 if (unlikely(!pagep)) {
949 drvr_stats(adapter)->be_ethrx_post_fail++;
950 break;
951 }
952 page_dmaaddr = pci_map_page(adapter->pdev, pagep, 0,
953 adapter->big_page_size,
954 PCI_DMA_FROMDEVICE);
955 page_info->page_offset = 0;
956 } else {
957 get_page(pagep);
958 page_info->page_offset = page_offset + rx_frag_size;
959 }
960 page_offset = page_info->page_offset;
961 page_info->page = pagep;
962 pci_unmap_addr_set(page_info, bus, page_dmaaddr);
963 frag_dmaaddr = page_dmaaddr + page_info->page_offset;
964
965 rxd = queue_head_node(rxq);
966 rxd->fragpa_lo = cpu_to_le32(frag_dmaaddr & 0xFFFFFFFF);
967 rxd->fragpa_hi = cpu_to_le32(upper_32_bits(frag_dmaaddr));
6b7c5b94
SP		 968
969 /* Any space left in the current big page for another frag? */
970 if ((page_offset + rx_frag_size + rx_frag_size) >
971 adapter->big_page_size) {
972 pagep = NULL;
973 page_info->last_page_user = true;
974 }
26d92f92
SP		 975
976 prev_page_info = page_info;
977 queue_head_inc(rxq);
6b7c5b94
SP		 978 page_info = &page_info_tbl[rxq->head];
979 }
980 if (pagep)
26d92f92 981 prev_page_info->last_page_user = true;
6b7c5b94
SP		 982
983 if (posted) {
6b7c5b94 984 atomic_add(posted, &rxq->used);
8788fdc2 985 be_rxq_notify(adapter, rxq->id, posted);
ea1dae11
SP		 986 } else if (atomic_read(&rxq->used) == 0) {
987 /* Let be_worker replenish when memory is available */
988 adapter->rx_post_starved = true;
6b7c5b94
SP		 989 }
990
991 return;
992}
993
5fb379ee 994static struct be_eth_tx_compl *be_tx_compl_get(struct be_queue_info *tx_cq)
6b7c5b94 995{
6b7c5b94
SP		 996 struct be_eth_tx_compl *txcp = queue_tail_node(tx_cq);
997
998 if (txcp->dw[offsetof(struct amap_eth_tx_compl, valid) / 32] == 0)
999 return NULL;
1000
1001 be_dws_le_to_cpu(txcp, sizeof(*txcp));
1002
1003 txcp->dw[offsetof(struct amap_eth_tx_compl, valid) / 32] = 0;
1004
1005 queue_tail_inc(tx_cq);
1006 return txcp;
1007}
1008
1009static void be_tx_compl_process(struct be_adapter *adapter, u16 last_index)
1010{
1011 struct be_queue_info *txq = &adapter->tx_obj.q;
a73b796e 1012 struct be_eth_wrb *wrb;
6b7c5b94
SP		 1013 struct sk_buff **sent_skbs = adapter->tx_obj.sent_skb_list;
1014 struct sk_buff *sent_skb;
a73b796e 1015 u64 busaddr;
6b7c5b94
SP		 1016 u16 cur_index, num_wrbs = 0;
1017
1018 cur_index = txq->tail;
1019 sent_skb = sent_skbs[cur_index];
1020 BUG_ON(!sent_skb);
1021 sent_skbs[cur_index] = NULL;
a73b796e
AD		 1022 wrb = queue_tail_node(txq);
1023 be_dws_le_to_cpu(wrb, sizeof(*wrb));
1024 busaddr = ((u64)wrb->frag_pa_hi << 32) | (u64)wrb->frag_pa_lo;
1025 if (busaddr != 0) {
1026 pci_unmap_single(adapter->pdev, busaddr,
1027 wrb->frag_len, PCI_DMA_TODEVICE);
1028 }
1029 num_wrbs++;
1030 queue_tail_inc(txq);
6b7c5b94 1031
a73b796e 1032 while (cur_index != last_index) {
6b7c5b94 1033 cur_index = txq->tail;
a73b796e
AD		 1034 wrb = queue_tail_node(txq);
1035 be_dws_le_to_cpu(wrb, sizeof(*wrb));
1036 busaddr = ((u64)wrb->frag_pa_hi << 32) | (u64)wrb->frag_pa_lo;
1037 if (busaddr != 0) {
1038 pci_unmap_page(adapter->pdev, busaddr,
1039 wrb->frag_len, PCI_DMA_TODEVICE);
1040 }
6b7c5b94
SP		 1041 num_wrbs++;
1042 queue_tail_inc(txq);
a73b796e 1043 }
6b7c5b94
SP		 1044
1045 atomic_sub(num_wrbs, &txq->used);
a73b796e 1046
6b7c5b94
SP		 1047 kfree_skb(sent_skb);
1048}
1049
859b1e4e
SP		 1050static inline struct be_eq_entry *event_get(struct be_eq_obj *eq_obj)
1051{
1052 struct be_eq_entry *eqe = queue_tail_node(&eq_obj->q);
1053
1054 if (!eqe->evt)
1055 return NULL;
1056
1057 eqe->evt = le32_to_cpu(eqe->evt);
1058 queue_tail_inc(&eq_obj->q);
1059 return eqe;
1060}
1061
1062static int event_handle(struct be_adapter *adapter,
1063 struct be_eq_obj *eq_obj)
1064{
1065 struct be_eq_entry *eqe;
1066 u16 num = 0;
1067
1068 while ((eqe = event_get(eq_obj)) != NULL) {
1069 eqe->evt = 0;
1070 num++;
1071 }
1072
1073 /* Deal with any spurious interrupts that come
1074 * without events
1075 */
1076 be_eq_notify(adapter, eq_obj->q.id, true, true, num);
1077 if (num)
1078 napi_schedule(&eq_obj->napi);
1079
1080 return num;
1081}
1082
1083/* Just read and notify events without processing them.
1084 * Used at the time of destroying event queues */
1085static void be_eq_clean(struct be_adapter *adapter,
1086 struct be_eq_obj *eq_obj)
1087{
1088 struct be_eq_entry *eqe;
1089 u16 num = 0;
1090
1091 while ((eqe = event_get(eq_obj)) != NULL) {
1092 eqe->evt = 0;
1093 num++;
1094 }
1095
1096 if (num)
1097 be_eq_notify(adapter, eq_obj->q.id, false, true, num);
1098}
1099
6b7c5b94
SP		 1100static void be_rx_q_clean(struct be_adapter *adapter)
1101{
1102 struct be_rx_page_info *page_info;
1103 struct be_queue_info *rxq = &adapter->rx_obj.q;
1104 struct be_queue_info *rx_cq = &adapter->rx_obj.cq;
1105 struct be_eth_rx_compl *rxcp;
1106 u16 tail;
1107
1108 /* First cleanup pending rx completions */
1109 while ((rxcp = be_rx_compl_get(adapter)) != NULL) {
1110 be_rx_compl_discard(adapter, rxcp);
a7a0ef31 1111 be_rx_compl_reset(rxcp);
8788fdc2 1112 be_cq_notify(adapter, rx_cq->id, true, 1);
6b7c5b94
SP		 1113 }
1114
1115 /* Then free posted rx buffer that were not used */
1116 tail = (rxq->head + rxq->len - atomic_read(&rxq->used)) % rxq->len;
cdab23b7 1117 for (; atomic_read(&rxq->used) > 0; index_inc(&tail, rxq->len)) {
6b7c5b94
SP		 1118 page_info = get_rx_page_info(adapter, tail);
1119 put_page(page_info->page);
1120 memset(page_info, 0, sizeof(*page_info));
1121 }
1122 BUG_ON(atomic_read(&rxq->used));
1123}
1124
a8e9179a 1125static void be_tx_compl_clean(struct be_adapter *adapter)
6b7c5b94 1126{
a8e9179a 1127 struct be_queue_info *tx_cq = &adapter->tx_obj.cq;
6b7c5b94 1128 struct be_queue_info *txq = &adapter->tx_obj.q;
a8e9179a
SP		 1129 struct be_eth_tx_compl *txcp;
1130 u16 end_idx, cmpl = 0, timeo = 0;
b03388d6
SP		 1131 struct sk_buff **sent_skbs = adapter->tx_obj.sent_skb_list;
1132 struct sk_buff *sent_skb;
1133 bool dummy_wrb;
a8e9179a
SP		 1134
1135 /* Wait for a max of 200ms for all the tx-completions to arrive. */
1136 do {
1137 while ((txcp = be_tx_compl_get(tx_cq))) {
1138 end_idx = AMAP_GET_BITS(struct amap_eth_tx_compl,
1139 wrb_index, txcp);
1140 be_tx_compl_process(adapter, end_idx);
1141 cmpl++;
1142 }
1143 if (cmpl) {
1144 be_cq_notify(adapter, tx_cq->id, false, cmpl);
1145 cmpl = 0;
1146 }
1147
1148 if (atomic_read(&txq->used) == 0 || ++timeo > 200)
1149 break;
1150
1151 mdelay(1);
1152 } while (true);
1153
1154 if (atomic_read(&txq->used))
1155 dev_err(&adapter->pdev->dev, "%d pending tx-completions\n",
1156 atomic_read(&txq->used));
b03388d6
SP		 1157
1158 /* free posted tx for which compls will never arrive */
1159 while (atomic_read(&txq->used)) {
1160 sent_skb = sent_skbs[txq->tail];
1161 end_idx = txq->tail;
1162 index_adv(&end_idx,
1163 wrb_cnt_for_skb(sent_skb, &dummy_wrb) - 1, txq->len);
1164 be_tx_compl_process(adapter, end_idx);
1165 }
6b7c5b94
SP		 1166}
1167
5fb379ee
SP		 1168static void be_mcc_queues_destroy(struct be_adapter *adapter)
1169{
1170 struct be_queue_info *q;
5fb379ee 1171
8788fdc2 1172 q = &adapter->mcc_obj.q;
5fb379ee 1173 if (q->created)
8788fdc2 1174 be_cmd_q_destroy(adapter, q, QTYPE_MCCQ);
5fb379ee
SP		 1175 be_queue_free(adapter, q);
1176
8788fdc2 1177 q = &adapter->mcc_obj.cq;
5fb379ee 1178 if (q->created)
8788fdc2 1179 be_cmd_q_destroy(adapter, q, QTYPE_CQ);
5fb379ee
SP		 1180 be_queue_free(adapter, q);
1181}
1182
1183/* Must be called only after TX qs are created as MCC shares TX EQ */
1184static int be_mcc_queues_create(struct be_adapter *adapter)
1185{
1186 struct be_queue_info *q, *cq;
5fb379ee
SP		 1187
1188 /* Alloc MCC compl queue */
8788fdc2 1189 cq = &adapter->mcc_obj.cq;
5fb379ee 1190 if (be_queue_alloc(adapter, cq, MCC_CQ_LEN,
efd2e40a 1191 sizeof(struct be_mcc_compl)))
5fb379ee
SP		 1192 goto err;
1193
1194 /* Ask BE to create MCC compl queue; share TX's eq */
8788fdc2 1195 if (be_cmd_cq_create(adapter, cq, &adapter->tx_eq.q, false, true, 0))
5fb379ee
SP		 1196 goto mcc_cq_free;
1197
1198 /* Alloc MCC queue */
8788fdc2 1199 q = &adapter->mcc_obj.q;
5fb379ee
SP		 1200 if (be_queue_alloc(adapter, q, MCC_Q_LEN, sizeof(struct be_mcc_wrb)))
1201 goto mcc_cq_destroy;
1202
1203 /* Ask BE to create MCC queue */
8788fdc2 1204 if (be_cmd_mccq_create(adapter, q, cq))
5fb379ee
SP		 1205 goto mcc_q_free;
1206
1207 return 0;
1208
1209mcc_q_free:
1210 be_queue_free(adapter, q);
1211mcc_cq_destroy:
8788fdc2 1212 be_cmd_q_destroy(adapter, cq, QTYPE_CQ);
5fb379ee
SP		 1213mcc_cq_free:
1214 be_queue_free(adapter, cq);
1215err:
1216 return -1;
1217}
1218
6b7c5b94
SP		 1219static void be_tx_queues_destroy(struct be_adapter *adapter)
1220{
1221 struct be_queue_info *q;
1222
1223 q = &adapter->tx_obj.q;
a8e9179a 1224 if (q->created)
8788fdc2 1225 be_cmd_q_destroy(adapter, q, QTYPE_TXQ);
6b7c5b94
SP		 1226 be_queue_free(adapter, q);
1227
1228 q = &adapter->tx_obj.cq;
1229 if (q->created)
8788fdc2 1230 be_cmd_q_destroy(adapter, q, QTYPE_CQ);
6b7c5b94
SP		 1231 be_queue_free(adapter, q);
1232
859b1e4e
SP		 1233 /* Clear any residual events */
1234 be_eq_clean(adapter, &adapter->tx_eq);
1235
6b7c5b94
SP		 1236 q = &adapter->tx_eq.q;
1237 if (q->created)
8788fdc2 1238 be_cmd_q_destroy(adapter, q, QTYPE_EQ);
6b7c5b94
SP		 1239 be_queue_free(adapter, q);
1240}
1241
1242static int be_tx_queues_create(struct be_adapter *adapter)
1243{
1244 struct be_queue_info *eq, *q, *cq;
1245
1246 adapter->tx_eq.max_eqd = 0;
1247 adapter->tx_eq.min_eqd = 0;
1248 adapter->tx_eq.cur_eqd = 96;
1249 adapter->tx_eq.enable_aic = false;
1250 /* Alloc Tx Event queue */
1251 eq = &adapter->tx_eq.q;
1252 if (be_queue_alloc(adapter, eq, EVNT_Q_LEN, sizeof(struct be_eq_entry)))
1253 return -1;
1254
1255 /* Ask BE to create Tx Event queue */
8788fdc2 1256 if (be_cmd_eq_create(adapter, eq, adapter->tx_eq.cur_eqd))
6b7c5b94
SP		 1257 goto tx_eq_free;
1258 /* Alloc TX eth compl queue */
1259 cq = &adapter->tx_obj.cq;
1260 if (be_queue_alloc(adapter, cq, TX_CQ_LEN,
1261 sizeof(struct be_eth_tx_compl)))
1262 goto tx_eq_destroy;
1263
1264 /* Ask BE to create Tx eth compl queue */
8788fdc2 1265 if (be_cmd_cq_create(adapter, cq, eq, false, false, 3))
6b7c5b94
SP		 1266 goto tx_cq_free;
1267
1268 /* Alloc TX eth queue */
1269 q = &adapter->tx_obj.q;
1270 if (be_queue_alloc(adapter, q, TX_Q_LEN, sizeof(struct be_eth_wrb)))
1271 goto tx_cq_destroy;
1272
1273 /* Ask BE to create Tx eth queue */
8788fdc2 1274 if (be_cmd_txq_create(adapter, q, cq))
6b7c5b94
SP		 1275 goto tx_q_free;
1276 return 0;
1277
1278tx_q_free:
1279 be_queue_free(adapter, q);
1280tx_cq_destroy:
8788fdc2 1281 be_cmd_q_destroy(adapter, cq, QTYPE_CQ);
6b7c5b94
SP		 1282tx_cq_free:
1283 be_queue_free(adapter, cq);
1284tx_eq_destroy:
8788fdc2 1285 be_cmd_q_destroy(adapter, eq, QTYPE_EQ);
6b7c5b94
SP		 1286tx_eq_free:
1287 be_queue_free(adapter, eq);
1288 return -1;
1289}
1290
1291static void be_rx_queues_destroy(struct be_adapter *adapter)
1292{
1293 struct be_queue_info *q;
1294
1295 q = &adapter->rx_obj.q;
1296 if (q->created) {
8788fdc2 1297 be_cmd_q_destroy(adapter, q, QTYPE_RXQ);
89420424
SP		 1298
1299 /* After the rxq is invalidated, wait for a grace time
1300 * of 1ms for all dma to end and the flush compl to arrive
1301 */
1302 mdelay(1);
6b7c5b94
SP		 1303 be_rx_q_clean(adapter);
1304 }
1305 be_queue_free(adapter, q);
1306
1307 q = &adapter->rx_obj.cq;
1308 if (q->created)
8788fdc2 1309 be_cmd_q_destroy(adapter, q, QTYPE_CQ);
6b7c5b94
SP		 1310 be_queue_free(adapter, q);
1311
859b1e4e
SP		 1312 /* Clear any residual events */
1313 be_eq_clean(adapter, &adapter->rx_eq);
1314
6b7c5b94
SP		 1315 q = &adapter->rx_eq.q;
1316 if (q->created)
8788fdc2 1317 be_cmd_q_destroy(adapter, q, QTYPE_EQ);
6b7c5b94
SP		 1318 be_queue_free(adapter, q);
1319}
1320
1321static int be_rx_queues_create(struct be_adapter *adapter)
1322{
1323 struct be_queue_info *eq, *q, *cq;
1324 int rc;
1325
6b7c5b94
SP		 1326 adapter->big_page_size = (1 << get_order(rx_frag_size)) * PAGE_SIZE;
1327 adapter->rx_eq.max_eqd = BE_MAX_EQD;
1328 adapter->rx_eq.min_eqd = 0;
1329 adapter->rx_eq.cur_eqd = 0;
1330 adapter->rx_eq.enable_aic = true;
1331
1332 /* Alloc Rx Event queue */
1333 eq = &adapter->rx_eq.q;
1334 rc = be_queue_alloc(adapter, eq, EVNT_Q_LEN,
1335 sizeof(struct be_eq_entry));
1336 if (rc)
1337 return rc;
1338
1339 /* Ask BE to create Rx Event queue */
8788fdc2 1340 rc = be_cmd_eq_create(adapter, eq, adapter->rx_eq.cur_eqd);
6b7c5b94
SP		 1341 if (rc)
1342 goto rx_eq_free;
1343
1344 /* Alloc RX eth compl queue */
1345 cq = &adapter->rx_obj.cq;
1346 rc = be_queue_alloc(adapter, cq, RX_CQ_LEN,
1347 sizeof(struct be_eth_rx_compl));
1348 if (rc)
1349 goto rx_eq_destroy;
1350
1351 /* Ask BE to create Rx eth compl queue */
8788fdc2 1352 rc = be_cmd_cq_create(adapter, cq, eq, false, false, 3);
6b7c5b94
SP		 1353 if (rc)
1354 goto rx_cq_free;
1355
1356 /* Alloc RX eth queue */
1357 q = &adapter->rx_obj.q;
1358 rc = be_queue_alloc(adapter, q, RX_Q_LEN, sizeof(struct be_eth_rx_d));
1359 if (rc)
1360 goto rx_cq_destroy;
1361
1362 /* Ask BE to create Rx eth queue */
8788fdc2 1363 rc = be_cmd_rxq_create(adapter, q, cq->id, rx_frag_size,
6b7c5b94
SP		 1364 BE_MAX_JUMBO_FRAME_SIZE, adapter->if_handle, false);
1365 if (rc)
1366 goto rx_q_free;
1367
1368 return 0;
1369rx_q_free:
1370 be_queue_free(adapter, q);
1371rx_cq_destroy:
8788fdc2 1372 be_cmd_q_destroy(adapter, cq, QTYPE_CQ);
6b7c5b94
SP		 1373rx_cq_free:
1374 be_queue_free(adapter, cq);
1375rx_eq_destroy:
8788fdc2 1376 be_cmd_q_destroy(adapter, eq, QTYPE_EQ);
6b7c5b94
SP		 1377rx_eq_free:
1378 be_queue_free(adapter, eq);
1379 return rc;
1380}
6b7c5b94 1381
b628bde2
SP		 1382/* There are 8 evt ids per func. Retruns the evt id's bit number */
1383static inline int be_evt_bit_get(struct be_adapter *adapter, u32 eq_id)
1384{
1385 return eq_id - 8 * be_pci_func(adapter);
1386}
1387
6b7c5b94
SP		 1388static irqreturn_t be_intx(int irq, void *dev)
1389{
1390 struct be_adapter *adapter = dev;
8788fdc2 1391 int isr;
6b7c5b94 1392
8788fdc2 1393 isr = ioread32(adapter->csr + CEV_ISR0_OFFSET +
55bdeed9 1394 (adapter->tx_eq.q.id/ 8) * CEV_ISR_SIZE);
c001c213 1395 if (!isr)
8788fdc2 1396 return IRQ_NONE;
6b7c5b94 1397
8788fdc2
SP		 1398 event_handle(adapter, &adapter->tx_eq);
1399 event_handle(adapter, &adapter->rx_eq);
c001c213 1400
8788fdc2 1401 return IRQ_HANDLED;
6b7c5b94
SP		 1402}
1403
1404static irqreturn_t be_msix_rx(int irq, void *dev)
1405{
1406 struct be_adapter *adapter = dev;
1407
8788fdc2 1408 event_handle(adapter, &adapter->rx_eq);
6b7c5b94
SP		 1409
1410 return IRQ_HANDLED;
1411}
1412
5fb379ee 1413static irqreturn_t be_msix_tx_mcc(int irq, void *dev)
6b7c5b94
SP		 1414{
1415 struct be_adapter *adapter = dev;
1416
8788fdc2 1417 event_handle(adapter, &adapter->tx_eq);
6b7c5b94
SP		 1418
1419 return IRQ_HANDLED;
1420}
1421
5be93b9a 1422static inline bool do_gro(struct be_adapter *adapter,
6b7c5b94
SP		 1423 struct be_eth_rx_compl *rxcp)
1424{
1425 int err = AMAP_GET_BITS(struct amap_eth_rx_compl, err, rxcp);
1426 int tcp_frame = AMAP_GET_BITS(struct amap_eth_rx_compl, tcpf, rxcp);
1427
1428 if (err)
1429 drvr_stats(adapter)->be_rxcp_err++;
1430
5be93b9a 1431 return (tcp_frame && !err) ? true : false;
6b7c5b94
SP		 1432}
1433
1434int be_poll_rx(struct napi_struct *napi, int budget)
1435{
1436 struct be_eq_obj *rx_eq = container_of(napi, struct be_eq_obj, napi);
1437 struct be_adapter *adapter =
1438 container_of(rx_eq, struct be_adapter, rx_eq);
1439 struct be_queue_info *rx_cq = &adapter->rx_obj.cq;
1440 struct be_eth_rx_compl *rxcp;
1441 u32 work_done;
1442
b7b83ac3 1443 adapter->stats.drvr_stats.be_rx_polls++;
6b7c5b94
SP		 1444 for (work_done = 0; work_done < budget; work_done++) {
1445 rxcp = be_rx_compl_get(adapter);
1446 if (!rxcp)
1447 break;
1448
5be93b9a
AK		 1449 if (do_gro(adapter, rxcp))
1450 be_rx_compl_process_gro(adapter, rxcp);
6b7c5b94
SP		 1451 else
1452 be_rx_compl_process(adapter, rxcp);
a7a0ef31
SP		 1453
1454 be_rx_compl_reset(rxcp);
6b7c5b94
SP		 1455 }
1456
6b7c5b94
SP		 1457 /* Refill the queue */
1458 if (atomic_read(&adapter->rx_obj.q.used) < RX_FRAGS_REFILL_WM)
1459 be_post_rx_frags(adapter);
1460
1461 /* All consumed */
1462 if (work_done < budget) {
1463 napi_complete(napi);
8788fdc2 1464 be_cq_notify(adapter, rx_cq->id, true, work_done);
6b7c5b94
SP		 1465 } else {
1466 /* More to be consumed; continue with interrupts disabled */
8788fdc2 1467 be_cq_notify(adapter, rx_cq->id, false, work_done);
6b7c5b94
SP		 1468 }
1469 return work_done;
1470}
1471
5fb379ee 1472void be_process_tx(struct be_adapter *adapter)
6b7c5b94 1473{
5fb379ee
SP		 1474 struct be_queue_info *txq = &adapter->tx_obj.q;
1475 struct be_queue_info *tx_cq = &adapter->tx_obj.cq;
6b7c5b94
SP		 1476 struct be_eth_tx_compl *txcp;
1477 u32 num_cmpl = 0;
1478 u16 end_idx;
1479
5fb379ee 1480 while ((txcp = be_tx_compl_get(tx_cq))) {
6b7c5b94
SP		 1481 end_idx = AMAP_GET_BITS(struct amap_eth_tx_compl,
1482 wrb_index, txcp);
1483 be_tx_compl_process(adapter, end_idx);
1484 num_cmpl++;
1485 }
1486
5fb379ee 1487 if (num_cmpl) {
8788fdc2 1488 be_cq_notify(adapter, tx_cq->id, true, num_cmpl);
5fb379ee
SP		 1489
1490 /* As Tx wrbs have been freed up, wake up netdev queue if
1491 * it was stopped due to lack of tx wrbs.
1492 */
1493 if (netif_queue_stopped(adapter->netdev) &&
6b7c5b94 1494 atomic_read(&txq->used) < txq->len / 2) {
5fb379ee
SP		 1495 netif_wake_queue(adapter->netdev);
1496 }
1497
1498 drvr_stats(adapter)->be_tx_events++;
1499 drvr_stats(adapter)->be_tx_compl += num_cmpl;
6b7c5b94 1500 }
5fb379ee
SP		 1501}
1502
1503/* As TX and MCC share the same EQ check for both TX and MCC completions.
1504 * For TX/MCC we don't honour budget; consume everything
1505 */
1506static int be_poll_tx_mcc(struct napi_struct *napi, int budget)
1507{
1508 struct be_eq_obj *tx_eq = container_of(napi, struct be_eq_obj, napi);
1509 struct be_adapter *adapter =
1510 container_of(tx_eq, struct be_adapter, tx_eq);
6b7c5b94
SP		 1511
1512 napi_complete(napi);
1513
5fb379ee 1514 be_process_tx(adapter);
6b7c5b94 1515
8788fdc2 1516 be_process_mcc(adapter);
6b7c5b94
SP		 1517
1518 return 1;
1519}
1520
ea1dae11
SP		 1521static void be_worker(struct work_struct *work)
1522{
1523 struct be_adapter *adapter =
1524 container_of(work, struct be_adapter, work.work);
ea1dae11 1525
b31c50a7 1526 be_cmd_get_stats(adapter, &adapter->stats.cmd);
ea1dae11
SP		 1527
1528 /* Set EQ delay */
1529 be_rx_eqd_update(adapter);
1530
4097f663
SP		 1531 be_tx_rate_update(adapter);
1532 be_rx_rate_update(adapter);
1533
ea1dae11
SP		 1534 if (adapter->rx_post_starved) {
1535 adapter->rx_post_starved = false;
1536 be_post_rx_frags(adapter);
1537 }
1538
1539 schedule_delayed_work(&adapter->work, msecs_to_jiffies(1000));
1540}
1541
8d56ff11
SP		 1542static void be_msix_disable(struct be_adapter *adapter)
1543{
1544 if (adapter->msix_enabled) {
1545 pci_disable_msix(adapter->pdev);
1546 adapter->msix_enabled = false;
1547 }
1548}
1549
6b7c5b94
SP		 1550static void be_msix_enable(struct be_adapter *adapter)
1551{
1552 int i, status;
1553
1554 for (i = 0; i < BE_NUM_MSIX_VECTORS; i++)
1555 adapter->msix_entries[i].entry = i;
1556
1557 status = pci_enable_msix(adapter->pdev, adapter->msix_entries,
1558 BE_NUM_MSIX_VECTORS);
1559 if (status == 0)
1560 adapter->msix_enabled = true;
1561 return;
1562}
1563
1564static inline int be_msix_vec_get(struct be_adapter *adapter, u32 eq_id)
1565{
b628bde2
SP		 1566 return adapter->msix_entries[
1567 be_evt_bit_get(adapter, eq_id)].vector;
6b7c5b94
SP		 1568}
1569
b628bde2
SP		 1570static int be_request_irq(struct be_adapter *adapter,
1571 struct be_eq_obj *eq_obj,
1572 void *handler, char *desc)
6b7c5b94
SP		 1573{
1574 struct net_device *netdev = adapter->netdev;
b628bde2
SP		 1575 int vec;
1576
1577 sprintf(eq_obj->desc, "%s-%s", netdev->name, desc);
1578 vec = be_msix_vec_get(adapter, eq_obj->q.id);
1579 return request_irq(vec, handler, 0, eq_obj->desc, adapter);
1580}
1581
1582static void be_free_irq(struct be_adapter *adapter, struct be_eq_obj *eq_obj)
1583{
1584 int vec = be_msix_vec_get(adapter, eq_obj->q.id);
1585 free_irq(vec, adapter);
1586}
6b7c5b94 1587
b628bde2
SP		 1588static int be_msix_register(struct be_adapter *adapter)
1589{
1590 int status;
1591
1592 status = be_request_irq(adapter, &adapter->tx_eq, be_msix_tx_mcc, "tx");
6b7c5b94
SP		 1593 if (status)
1594 goto err;
1595
b628bde2
SP		 1596 status = be_request_irq(adapter, &adapter->rx_eq, be_msix_rx, "rx");
1597 if (status)
1598 goto free_tx_irq;
1599
6b7c5b94 1600 return 0;
b628bde2
SP		 1601
1602free_tx_irq:
1603 be_free_irq(adapter, &adapter->tx_eq);
6b7c5b94
SP		 1604err:
1605 dev_warn(&adapter->pdev->dev,
1606 "MSIX Request IRQ failed - err %d\n", status);
1607 pci_disable_msix(adapter->pdev);
1608 adapter->msix_enabled = false;
1609 return status;
1610}
1611
1612static int be_irq_register(struct be_adapter *adapter)
1613{
1614 struct net_device *netdev = adapter->netdev;
1615 int status;
1616
1617 if (adapter->msix_enabled) {
1618 status = be_msix_register(adapter);
1619 if (status == 0)
1620 goto done;
1621 }
1622
1623 /* INTx */
1624 netdev->irq = adapter->pdev->irq;
1625 status = request_irq(netdev->irq, be_intx, IRQF_SHARED, netdev->name,
1626 adapter);
1627 if (status) {
1628 dev_err(&adapter->pdev->dev,
1629 "INTx request IRQ failed - err %d\n", status);
1630 return status;
1631 }
1632done:
1633 adapter->isr_registered = true;
1634 return 0;
1635}
1636
1637static void be_irq_unregister(struct be_adapter *adapter)
1638{
1639 struct net_device *netdev = adapter->netdev;
6b7c5b94
SP		 1640
1641 if (!adapter->isr_registered)
1642 return;
1643
1644 /* INTx */
1645 if (!adapter->msix_enabled) {
1646 free_irq(netdev->irq, adapter);
1647 goto done;
1648 }
1649
1650 /* MSIx */
b628bde2
SP		 1651 be_free_irq(adapter, &adapter->tx_eq);
1652 be_free_irq(adapter, &adapter->rx_eq);
6b7c5b94
SP		 1653done:
1654 adapter->isr_registered = false;
1655 return;
1656}
1657
1658static int be_open(struct net_device *netdev)
1659{
1660 struct be_adapter *adapter = netdev_priv(netdev);
6b7c5b94
SP		 1661 struct be_eq_obj *rx_eq = &adapter->rx_eq;
1662 struct be_eq_obj *tx_eq = &adapter->tx_eq;
a8f447bd
SP		 1663 bool link_up;
1664 int status;
0388f251
SB		 1665 u8 mac_speed;
1666 u16 link_speed;
5fb379ee
SP		 1667
1668 /* First time posting */
1669 be_post_rx_frags(adapter);
1670
1671 napi_enable(&rx_eq->napi);
1672 napi_enable(&tx_eq->napi);
1673
1674 be_irq_register(adapter);
1675
8788fdc2 1676 be_intr_set(adapter, true);
5fb379ee
SP		 1677
1678 /* The evt queues are created in unarmed state; arm them */
8788fdc2
SP		 1679 be_eq_notify(adapter, rx_eq->q.id, true, false, 0);
1680 be_eq_notify(adapter, tx_eq->q.id, true, false, 0);
5fb379ee
SP		 1681
1682 /* Rx compl queue may be in unarmed state; rearm it */
8788fdc2 1683 be_cq_notify(adapter, adapter->rx_obj.cq.id, true, 0);
5fb379ee 1684
7a1e9b20
SP		 1685 /* Now that interrupts are on we can process async mcc */
1686 be_async_mcc_enable(adapter);
1687
0388f251
SB		 1688 status = be_cmd_link_status_query(adapter, &link_up, &mac_speed,
1689 &link_speed);
a8f447bd 1690 if (status)
4f2aa89c 1691 goto ret_sts;
a8f447bd 1692 be_link_status_update(adapter, link_up);
5fb379ee 1693
4f2aa89c
AK		 1694 status = be_vid_config(adapter);
1695 if (status)
1696 goto ret_sts;
1697
1698 status = be_cmd_set_flow_control(adapter,
1699 adapter->tx_fc, adapter->rx_fc);
1700 if (status)
1701 goto ret_sts;
1702
5fb379ee 1703 schedule_delayed_work(&adapter->work, msecs_to_jiffies(100));
4f2aa89c
AK		 1704ret_sts:
1705 return status;
5fb379ee
SP		 1706}
1707
71d8d1b5
AK		 1708static int be_setup_wol(struct be_adapter *adapter, bool enable)
1709{
1710 struct be_dma_mem cmd;
1711 int status = 0;
1712 u8 mac[ETH_ALEN];
1713
1714 memset(mac, 0, ETH_ALEN);
1715
1716 cmd.size = sizeof(struct be_cmd_req_acpi_wol_magic_config);
1717 cmd.va = pci_alloc_consistent(adapter->pdev, cmd.size, &cmd.dma);
1718 if (cmd.va == NULL)
1719 return -1;
1720 memset(cmd.va, 0, cmd.size);
1721
1722 if (enable) {
1723 status = pci_write_config_dword(adapter->pdev,
1724 PCICFG_PM_CONTROL_OFFSET, PCICFG_PM_CONTROL_MASK);
1725 if (status) {
1726 dev_err(&adapter->pdev->dev,
1727 "Could not enable Wake-on-lan \n");
1728 pci_free_consistent(adapter->pdev, cmd.size, cmd.va,
1729 cmd.dma);
1730 return status;
1731 }
1732 status = be_cmd_enable_magic_wol(adapter,
1733 adapter->netdev->dev_addr, &cmd);
1734 pci_enable_wake(adapter->pdev, PCI_D3hot, 1);
1735 pci_enable_wake(adapter->pdev, PCI_D3cold, 1);
1736 } else {
1737 status = be_cmd_enable_magic_wol(adapter, mac, &cmd);
1738 pci_enable_wake(adapter->pdev, PCI_D3hot, 0);
1739 pci_enable_wake(adapter->pdev, PCI_D3cold, 0);
1740 }
1741
1742 pci_free_consistent(adapter->pdev, cmd.size, cmd.va, cmd.dma);
1743 return status;
1744}
1745
5fb379ee
SP		 1746static int be_setup(struct be_adapter *adapter)
1747{
5fb379ee 1748 struct net_device *netdev = adapter->netdev;
73d540f2 1749 u32 cap_flags, en_flags;
6b7c5b94
SP		 1750 int status;
1751
73d540f2
SP		 1752 cap_flags = BE_IF_FLAGS_UNTAGGED | BE_IF_FLAGS_BROADCAST |
1753 BE_IF_FLAGS_MCAST_PROMISCUOUS |
1754 BE_IF_FLAGS_PROMISCUOUS |
1755 BE_IF_FLAGS_PASS_L3L4_ERRORS;
1756 en_flags = BE_IF_FLAGS_UNTAGGED | BE_IF_FLAGS_BROADCAST |
1757 BE_IF_FLAGS_PASS_L3L4_ERRORS;
1758
1759 status = be_cmd_if_create(adapter, cap_flags, en_flags,
1760 netdev->dev_addr, false/* pmac_invalid */,
1761 &adapter->if_handle, &adapter->pmac_id);
6b7c5b94
SP		 1762 if (status != 0)
1763 goto do_none;
1764
6b7c5b94
SP		 1765 status = be_tx_queues_create(adapter);
1766 if (status != 0)
1767 goto if_destroy;
1768
1769 status = be_rx_queues_create(adapter);
1770 if (status != 0)
1771 goto tx_qs_destroy;
1772
5fb379ee
SP		 1773 status = be_mcc_queues_create(adapter);
1774 if (status != 0)
1775 goto rx_qs_destroy;
6b7c5b94 1776
0dffc83e
AK		 1777 adapter->link_speed = -1;
1778
6b7c5b94
SP		 1779 return 0;
1780
5fb379ee
SP		 1781rx_qs_destroy:
1782 be_rx_queues_destroy(adapter);
6b7c5b94
SP		 1783tx_qs_destroy:
1784 be_tx_queues_destroy(adapter);
1785if_destroy:
8788fdc2 1786 be_cmd_if_destroy(adapter, adapter->if_handle);
6b7c5b94
SP		 1787do_none:
1788 return status;
1789}
1790
5fb379ee
SP		 1791static int be_clear(struct be_adapter *adapter)
1792{
1a8887d8 1793 be_mcc_queues_destroy(adapter);
5fb379ee
SP		 1794 be_rx_queues_destroy(adapter);
1795 be_tx_queues_destroy(adapter);
1796
8788fdc2 1797 be_cmd_if_destroy(adapter, adapter->if_handle);
5fb379ee 1798
2243e2e9
SP		 1799 /* tell fw we're done with firing cmds */
1800 be_cmd_fw_clean(adapter);
5fb379ee
SP		 1801 return 0;
1802}
1803
6b7c5b94
SP		 1804static int be_close(struct net_device *netdev)
1805{
1806 struct be_adapter *adapter = netdev_priv(netdev);
6b7c5b94
SP		 1807 struct be_eq_obj *rx_eq = &adapter->rx_eq;
1808 struct be_eq_obj *tx_eq = &adapter->tx_eq;
1809 int vec;
1810
b305be78 1811 cancel_delayed_work_sync(&adapter->work);
6b7c5b94 1812
7a1e9b20
SP		 1813 be_async_mcc_disable(adapter);
1814
6b7c5b94
SP		 1815 netif_stop_queue(netdev);
1816 netif_carrier_off(netdev);
a8f447bd 1817 adapter->link_up = false;
6b7c5b94 1818
8788fdc2 1819 be_intr_set(adapter, false);
6b7c5b94
SP		 1820
1821 if (adapter->msix_enabled) {
1822 vec = be_msix_vec_get(adapter, tx_eq->q.id);
1823 synchronize_irq(vec);
1824 vec = be_msix_vec_get(adapter, rx_eq->q.id);
1825 synchronize_irq(vec);
1826 } else {
1827 synchronize_irq(netdev->irq);
1828 }
1829 be_irq_unregister(adapter);
1830
1831 napi_disable(&rx_eq->napi);
1832 napi_disable(&tx_eq->napi);
1833
a8e9179a
SP		 1834 /* Wait for all pending tx completions to arrive so that
1835 * all tx skbs are freed.
1836 */
1837 be_tx_compl_clean(adapter);
1838
6b7c5b94
SP		 1839 return 0;
1840}
1841
84517482
AK		 1842#define FW_FILE_HDR_SIGN "ServerEngines Corp. "
1843char flash_cookie[2][16] = {"*** SE FLAS",
1844 "H DIRECTORY *** "};
fa9a6fed
SB		 1845
1846static bool be_flash_redboot(struct be_adapter *adapter,
3f0d4560
AK		 1847 const u8 *p, u32 img_start, int image_size,
1848 int hdr_size)
fa9a6fed
SB		 1849{
1850 u32 crc_offset;
1851 u8 flashed_crc[4];
1852 int status;
3f0d4560
AK		 1853
1854 crc_offset = hdr_size + img_start + image_size - 4;
1855
fa9a6fed 1856 p += crc_offset;
3f0d4560
AK		 1857
1858 status = be_cmd_get_flash_crc(adapter, flashed_crc,
1859 (img_start + image_size - 4));
fa9a6fed
SB		 1860 if (status) {
1861 dev_err(&adapter->pdev->dev,
1862 "could not get crc from flash, not flashing redboot\n");
1863 return false;
1864 }
1865
1866 /*update redboot only if crc does not match*/
1867 if (!memcmp(flashed_crc, p, 4))
1868 return false;
1869 else
1870 return true;
fa9a6fed
SB		 1871}
1872
3f0d4560 1873static int be_flash_data(struct be_adapter *adapter,
84517482 1874 const struct firmware *fw,
3f0d4560
AK		 1875 struct be_dma_mem *flash_cmd, int num_of_images)
1876
84517482 1877{
3f0d4560
AK		 1878 int status = 0, i, filehdr_size = 0;
1879 u32 total_bytes = 0, flash_op;
84517482
AK		 1880 int num_bytes;
1881 const u8 *p = fw->data;
1882 struct be_cmd_write_flashrom *req = flash_cmd->va;
3f0d4560
AK		 1883 struct flash_comp *pflashcomp;
1884
1885 struct flash_comp gen3_flash_types[8] = {
1886 { FLASH_iSCSI_PRIMARY_IMAGE_START_g3, IMG_TYPE_ISCSI_ACTIVE,
1887 FLASH_IMAGE_MAX_SIZE_g3},
1888 { FLASH_REDBOOT_START_g3, IMG_TYPE_REDBOOT,
1889 FLASH_REDBOOT_IMAGE_MAX_SIZE_g3},
1890 { FLASH_iSCSI_BIOS_START_g3, IMG_TYPE_BIOS,
1891 FLASH_BIOS_IMAGE_MAX_SIZE_g3},
1892 { FLASH_PXE_BIOS_START_g3, IMG_TYPE_PXE_BIOS,
1893 FLASH_BIOS_IMAGE_MAX_SIZE_g3},
1894 { FLASH_FCoE_BIOS_START_g3, IMG_TYPE_FCOE_BIOS,
1895 FLASH_BIOS_IMAGE_MAX_SIZE_g3},
1896 { FLASH_iSCSI_BACKUP_IMAGE_START_g3, IMG_TYPE_ISCSI_BACKUP,
1897 FLASH_IMAGE_MAX_SIZE_g3},
1898 { FLASH_FCoE_PRIMARY_IMAGE_START_g3, IMG_TYPE_FCOE_FW_ACTIVE,
1899 FLASH_IMAGE_MAX_SIZE_g3},
1900 { FLASH_FCoE_BACKUP_IMAGE_START_g3, IMG_TYPE_FCOE_FW_BACKUP,
1901 FLASH_IMAGE_MAX_SIZE_g3}
1902 };
1903 struct flash_comp gen2_flash_types[8] = {
1904 { FLASH_iSCSI_PRIMARY_IMAGE_START_g2, IMG_TYPE_ISCSI_ACTIVE,
1905 FLASH_IMAGE_MAX_SIZE_g2},
1906 { FLASH_REDBOOT_START_g2, IMG_TYPE_REDBOOT,
1907 FLASH_REDBOOT_IMAGE_MAX_SIZE_g2},
1908 { FLASH_iSCSI_BIOS_START_g2, IMG_TYPE_BIOS,
1909 FLASH_BIOS_IMAGE_MAX_SIZE_g2},
1910 { FLASH_PXE_BIOS_START_g2, IMG_TYPE_PXE_BIOS,
1911 FLASH_BIOS_IMAGE_MAX_SIZE_g2},
1912 { FLASH_FCoE_BIOS_START_g2, IMG_TYPE_FCOE_BIOS,
1913 FLASH_BIOS_IMAGE_MAX_SIZE_g2},
1914 { FLASH_iSCSI_BACKUP_IMAGE_START_g2, IMG_TYPE_ISCSI_BACKUP,
1915 FLASH_IMAGE_MAX_SIZE_g2},
1916 { FLASH_FCoE_PRIMARY_IMAGE_START_g2, IMG_TYPE_FCOE_FW_ACTIVE,
1917 FLASH_IMAGE_MAX_SIZE_g2},
1918 { FLASH_FCoE_BACKUP_IMAGE_START_g2, IMG_TYPE_FCOE_FW_BACKUP,
1919 FLASH_IMAGE_MAX_SIZE_g2}
1920 };
1921
1922 if (adapter->generation == BE_GEN3) {
1923 pflashcomp = gen3_flash_types;
1924 filehdr_size = sizeof(struct flash_file_hdr_g3);
1925 } else {
1926 pflashcomp = gen2_flash_types;
1927 filehdr_size = sizeof(struct flash_file_hdr_g2);
84517482 1928 }
3f0d4560
AK		 1929 for (i = 0; i < 8; i++) {
1930 if ((pflashcomp[i].optype == IMG_TYPE_REDBOOT) &&
1931 (!be_flash_redboot(adapter, fw->data,
1932 pflashcomp[i].offset, pflashcomp[i].size,
1933 filehdr_size)))
1934 continue;
1935 p = fw->data;
1936 p += filehdr_size + pflashcomp[i].offset
1937 + (num_of_images * sizeof(struct image_hdr));
1938 if (p + pflashcomp[i].size > fw->data + fw->size)
84517482 1939 return -1;
3f0d4560
AK		 1940 total_bytes = pflashcomp[i].size;
1941 while (total_bytes) {
1942 if (total_bytes > 32*1024)
1943 num_bytes = 32*1024;
1944 else
1945 num_bytes = total_bytes;
1946 total_bytes -= num_bytes;
1947
1948 if (!total_bytes)
1949 flash_op = FLASHROM_OPER_FLASH;
1950 else
1951 flash_op = FLASHROM_OPER_SAVE;
1952 memcpy(req->params.data_buf, p, num_bytes);
1953 p += num_bytes;
1954 status = be_cmd_write_flashrom(adapter, flash_cmd,
1955 pflashcomp[i].optype, flash_op, num_bytes);
1956 if (status) {
1957 dev_err(&adapter->pdev->dev,
1958 "cmd to write to flash rom failed.\n");
1959 return -1;
1960 }
1961 yield();
84517482 1962 }
84517482 1963 }
84517482
AK		 1964 return 0;
1965}
1966
3f0d4560
AK		 1967static int get_ufigen_type(struct flash_file_hdr_g2 *fhdr)
1968{
1969 if (fhdr == NULL)
1970 return 0;
1971 if (fhdr->build[0] == '3')
1972 return BE_GEN3;
1973 else if (fhdr->build[0] == '2')
1974 return BE_GEN2;
1975 else
1976 return 0;
1977}
1978
84517482
AK		 1979int be_load_fw(struct be_adapter *adapter, u8 *func)
1980{
1981 char fw_file[ETHTOOL_FLASH_MAX_FILENAME];
1982 const struct firmware *fw;
3f0d4560
AK		 1983 struct flash_file_hdr_g2 *fhdr;
1984 struct flash_file_hdr_g3 *fhdr3;
1985 struct image_hdr *img_hdr_ptr = NULL;
84517482 1986 struct be_dma_mem flash_cmd;
3f0d4560 1987 int status, i = 0;
84517482 1988 const u8 *p;
84517482
AK		 1989 char fw_ver[FW_VER_LEN];
1990 char fw_cfg;
1991
1992 status = be_cmd_get_fw_ver(adapter, fw_ver);
1993 if (status)
1994 return status;
1995
1996 fw_cfg = *(fw_ver + 2);
1997 if (fw_cfg == '0')
1998 fw_cfg = '1';
1999 strcpy(fw_file, func);
2000
2001 status = request_firmware(&fw, fw_file, &adapter->pdev->dev);
2002 if (status)
2003 goto fw_exit;
2004
2005 p = fw->data;
3f0d4560 2006 fhdr = (struct flash_file_hdr_g2 *) p;
84517482
AK		 2007 dev_info(&adapter->pdev->dev, "Flashing firmware file %s\n", fw_file);
2008
84517482
AK		 2009 flash_cmd.size = sizeof(struct be_cmd_write_flashrom) + 32*1024;
2010 flash_cmd.va = pci_alloc_consistent(adapter->pdev, flash_cmd.size,
2011 &flash_cmd.dma);
2012 if (!flash_cmd.va) {
2013 status = -ENOMEM;
2014 dev_err(&adapter->pdev->dev,
2015 "Memory allocation failure while flashing\n");
2016 goto fw_exit;
2017 }
2018
3f0d4560
AK		 2019 if ((adapter->generation == BE_GEN3) &&
2020 (get_ufigen_type(fhdr) == BE_GEN3)) {
2021 fhdr3 = (struct flash_file_hdr_g3 *) fw->data;
2022 for (i = 0; i < fhdr3->num_imgs; i++) {
2023 img_hdr_ptr = (struct image_hdr *) (fw->data +
2024 (sizeof(struct flash_file_hdr_g3) +
2025 i * sizeof(struct image_hdr)));
2026 if (img_hdr_ptr->imageid == 1) {
2027 status = be_flash_data(adapter, fw,
2028 &flash_cmd, fhdr3->num_imgs);
2029 }
2030
2031 }
2032 } else if ((adapter->generation == BE_GEN2) &&
2033 (get_ufigen_type(fhdr) == BE_GEN2)) {
2034 status = be_flash_data(adapter, fw, &flash_cmd, 0);
2035 } else {
2036 dev_err(&adapter->pdev->dev,
2037 "UFI and Interface are not compatible for flashing\n");
2038 status = -1;
84517482
AK		 2039 }
2040
2041 pci_free_consistent(adapter->pdev, flash_cmd.size, flash_cmd.va,
2042 flash_cmd.dma);
2043 if (status) {
2044 dev_err(&adapter->pdev->dev, "Firmware load error\n");
2045 goto fw_exit;
2046 }
2047
af901ca1 2048 dev_info(&adapter->pdev->dev, "Firmware flashed successfully\n");
84517482
AK		 2049
2050fw_exit:
2051 release_firmware(fw);
2052 return status;
2053}
2054
6b7c5b94
SP		 2055static struct net_device_ops be_netdev_ops = {
2056 .ndo_open = be_open,
2057 .ndo_stop = be_close,
2058 .ndo_start_xmit = be_xmit,
2059 .ndo_get_stats = be_get_stats,
2060 .ndo_set_rx_mode = be_set_multicast_list,
2061 .ndo_set_mac_address = be_mac_addr_set,
2062 .ndo_change_mtu = be_change_mtu,
2063 .ndo_validate_addr = eth_validate_addr,
2064 .ndo_vlan_rx_register = be_vlan_register,
2065 .ndo_vlan_rx_add_vid = be_vlan_add_vid,
2066 .ndo_vlan_rx_kill_vid = be_vlan_rem_vid,
2067};
2068
2069static void be_netdev_init(struct net_device *netdev)
2070{
2071 struct be_adapter *adapter = netdev_priv(netdev);
2072
2073 netdev->features |= NETIF_F_SG | NETIF_F_HW_VLAN_RX | NETIF_F_TSO |
583e3f34
AK		 2074 NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_FILTER | NETIF_F_HW_CSUM |
2075 NETIF_F_GRO;
6b7c5b94 2076
51c59870
AK		 2077 netdev->vlan_features |= NETIF_F_SG | NETIF_F_TSO | NETIF_F_HW_CSUM;
2078
6b7c5b94
SP		 2079 netdev->flags |= IFF_MULTICAST;
2080
728a9972
AK		 2081 adapter->rx_csum = true;
2082
9e90c961
AK		 2083 /* Default settings for Rx and Tx flow control */
2084 adapter->rx_fc = true;
2085 adapter->tx_fc = true;
2086
c190e3c8
AK		 2087 netif_set_gso_max_size(netdev, 65535);
2088
6b7c5b94
SP		 2089 BE_SET_NETDEV_OPS(netdev, &be_netdev_ops);
2090
2091 SET_ETHTOOL_OPS(netdev, &be_ethtool_ops);
2092
6b7c5b94
SP		 2093 netif_napi_add(netdev, &adapter->rx_eq.napi, be_poll_rx,
2094 BE_NAPI_WEIGHT);
5fb379ee 2095 netif_napi_add(netdev, &adapter->tx_eq.napi, be_poll_tx_mcc,
6b7c5b94
SP		 2096 BE_NAPI_WEIGHT);
2097
2098 netif_carrier_off(netdev);
2099 netif_stop_queue(netdev);
2100}
2101
2102static void be_unmap_pci_bars(struct be_adapter *adapter)
2103{
8788fdc2
SP		 2104 if (adapter->csr)
2105 iounmap(adapter->csr);
2106 if (adapter->db)
2107 iounmap(adapter->db);
2108 if (adapter->pcicfg)
2109 iounmap(adapter->pcicfg);
6b7c5b94
SP		 2110}
2111
2112static int be_map_pci_bars(struct be_adapter *adapter)
2113{
2114 u8 __iomem *addr;
7b139c83 2115 int pcicfg_reg;
6b7c5b94
SP		 2116
2117 addr = ioremap_nocache(pci_resource_start(adapter->pdev, 2),
2118 pci_resource_len(adapter->pdev, 2));
2119 if (addr == NULL)
2120 return -ENOMEM;
8788fdc2 2121 adapter->csr = addr;
6b7c5b94
SP		 2122
2123 addr = ioremap_nocache(pci_resource_start(adapter->pdev, 4),
2124 128 * 1024);
2125 if (addr == NULL)
2126 goto pci_map_err;
8788fdc2 2127 adapter->db = addr;
6b7c5b94 2128
7b139c83
AK		 2129 if (adapter->generation == BE_GEN2)
2130 pcicfg_reg = 1;
2131 else
2132 pcicfg_reg = 0;
2133
2134 addr = ioremap_nocache(pci_resource_start(adapter->pdev, pcicfg_reg),
2135 pci_resource_len(adapter->pdev, pcicfg_reg));
6b7c5b94
SP		 2136 if (addr == NULL)
2137 goto pci_map_err;
8788fdc2 2138 adapter->pcicfg = addr;
6b7c5b94
SP		 2139
2140 return 0;
2141pci_map_err:
2142 be_unmap_pci_bars(adapter);
2143 return -ENOMEM;
2144}
2145
2146
2147static void be_ctrl_cleanup(struct be_adapter *adapter)
2148{
8788fdc2 2149 struct be_dma_mem *mem = &adapter->mbox_mem_alloced;
6b7c5b94
SP		 2150
2151 be_unmap_pci_bars(adapter);
2152
2153 if (mem->va)
2154 pci_free_consistent(adapter->pdev, mem->size,
2155 mem->va, mem->dma);
e7b909a6
SP		 2156
2157 mem = &adapter->mc_cmd_mem;
2158 if (mem->va)
2159 pci_free_consistent(adapter->pdev, mem->size,
2160 mem->va, mem->dma);
6b7c5b94
SP		 2161}
2162
6b7c5b94
SP		 2163static int be_ctrl_init(struct be_adapter *adapter)
2164{
8788fdc2
SP		 2165 struct be_dma_mem *mbox_mem_alloc = &adapter->mbox_mem_alloced;
2166 struct be_dma_mem *mbox_mem_align = &adapter->mbox_mem;
e7b909a6 2167 struct be_dma_mem *mc_cmd_mem = &adapter->mc_cmd_mem;
6b7c5b94 2168 int status;
6b7c5b94
SP		 2169
2170 status = be_map_pci_bars(adapter);
2171 if (status)
e7b909a6 2172 goto done;
6b7c5b94
SP		 2173
2174 mbox_mem_alloc->size = sizeof(struct be_mcc_mailbox) + 16;
2175 mbox_mem_alloc->va = pci_alloc_consistent(adapter->pdev,
2176 mbox_mem_alloc->size, &mbox_mem_alloc->dma);
2177 if (!mbox_mem_alloc->va) {
e7b909a6
SP		 2178 status = -ENOMEM;
2179 goto unmap_pci_bars;
6b7c5b94 2180 }
e7b909a6 2181
6b7c5b94
SP		 2182 mbox_mem_align->size = sizeof(struct be_mcc_mailbox);
2183 mbox_mem_align->va = PTR_ALIGN(mbox_mem_alloc->va, 16);
2184 mbox_mem_align->dma = PTR_ALIGN(mbox_mem_alloc->dma, 16);
2185 memset(mbox_mem_align->va, 0, sizeof(struct be_mcc_mailbox));
e7b909a6
SP		 2186
2187 mc_cmd_mem->size = sizeof(struct be_cmd_req_mcast_mac_config);
2188 mc_cmd_mem->va = pci_alloc_consistent(adapter->pdev, mc_cmd_mem->size,
2189 &mc_cmd_mem->dma);
2190 if (mc_cmd_mem->va == NULL) {
2191 status = -ENOMEM;
2192 goto free_mbox;
2193 }
2194 memset(mc_cmd_mem->va, 0, mc_cmd_mem->size);
2195
8788fdc2
SP		 2196 spin_lock_init(&adapter->mbox_lock);
2197 spin_lock_init(&adapter->mcc_lock);
2198 spin_lock_init(&adapter->mcc_cq_lock);
a8f447bd 2199
cf588477 2200 pci_save_state(adapter->pdev);
6b7c5b94 2201 return 0;
e7b909a6
SP		 2202
2203free_mbox:
2204 pci_free_consistent(adapter->pdev, mbox_mem_alloc->size,
2205 mbox_mem_alloc->va, mbox_mem_alloc->dma);
2206
2207unmap_pci_bars:
2208 be_unmap_pci_bars(adapter);
2209
2210done:
2211 return status;
6b7c5b94
SP		 2212}
2213
2214static void be_stats_cleanup(struct be_adapter *adapter)
2215{
2216 struct be_stats_obj *stats = &adapter->stats;
2217 struct be_dma_mem *cmd = &stats->cmd;
2218
2219 if (cmd->va)
2220 pci_free_consistent(adapter->pdev, cmd->size,
2221 cmd->va, cmd->dma);
2222}
2223
2224static int be_stats_init(struct be_adapter *adapter)
2225{
2226 struct be_stats_obj *stats = &adapter->stats;
2227 struct be_dma_mem *cmd = &stats->cmd;
2228
2229 cmd->size = sizeof(struct be_cmd_req_get_stats);
2230 cmd->va = pci_alloc_consistent(adapter->pdev, cmd->size, &cmd->dma);
2231 if (cmd->va == NULL)
2232 return -1;
d291b9af 2233 memset(cmd->va, 0, cmd->size);
6b7c5b94
SP		 2234 return 0;
2235}
2236
2237static void __devexit be_remove(struct pci_dev *pdev)
2238{
2239 struct be_adapter *adapter = pci_get_drvdata(pdev);
8d56ff11 2240
6b7c5b94
SP		 2241 if (!adapter)
2242 return;
2243
2244 unregister_netdev(adapter->netdev);
2245
5fb379ee
SP		 2246 be_clear(adapter);
2247
6b7c5b94
SP		 2248 be_stats_cleanup(adapter);
2249
2250 be_ctrl_cleanup(adapter);
2251
8d56ff11 2252 be_msix_disable(adapter);
6b7c5b94
SP		 2253
2254 pci_set_drvdata(pdev, NULL);
2255 pci_release_regions(pdev);
2256 pci_disable_device(pdev);
2257
2258 free_netdev(adapter->netdev);
2259}
2260
2243e2e9 2261static int be_get_config(struct be_adapter *adapter)
6b7c5b94 2262{
6b7c5b94 2263 int status;
2243e2e9 2264 u8 mac[ETH_ALEN];
6b7c5b94 2265
2243e2e9 2266 status = be_cmd_get_fw_ver(adapter, adapter->fw_ver);
6b7c5b94
SP		 2267 if (status)
2268 return status;
2269
2243e2e9
SP		 2270 status = be_cmd_query_fw_cfg(adapter,
2271 &adapter->port_num, &adapter->cap);
43a04fdc
SP		 2272 if (status)
2273 return status;
2274
2243e2e9
SP		 2275 memset(mac, 0, ETH_ALEN);
2276 status = be_cmd_mac_addr_query(adapter, mac,
2277 MAC_ADDRESS_TYPE_NETWORK, true /*permanent */, 0);
6b7c5b94
SP		 2278 if (status)
2279 return status;
ca9e4988
AK		 2280
2281 if (!is_valid_ether_addr(mac))
2282 return -EADDRNOTAVAIL;
2283
2243e2e9 2284 memcpy(adapter->netdev->dev_addr, mac, ETH_ALEN);
35a65285 2285 memcpy(adapter->netdev->perm_addr, mac, ETH_ALEN);
6b7c5b94 2286
82903e4b
AK		 2287 if (adapter->cap & 0x400)
2288 adapter->max_vlans = BE_NUM_VLANS_SUPPORTED/4;
2289 else
2290 adapter->max_vlans = BE_NUM_VLANS_SUPPORTED;
2291
2243e2e9 2292 return 0;
6b7c5b94
SP		 2293}
2294
2295static int __devinit be_probe(struct pci_dev *pdev,
2296 const struct pci_device_id *pdev_id)
2297{
2298 int status = 0;
2299 struct be_adapter *adapter;
2300 struct net_device *netdev;
6b7c5b94
SP		 2301
2302 status = pci_enable_device(pdev);
2303 if (status)
2304 goto do_none;
2305
2306 status = pci_request_regions(pdev, DRV_NAME);
2307 if (status)
2308 goto disable_dev;
2309 pci_set_master(pdev);
2310
2311 netdev = alloc_etherdev(sizeof(struct be_adapter));
2312 if (netdev == NULL) {
2313 status = -ENOMEM;
2314 goto rel_reg;
2315 }
2316 adapter = netdev_priv(netdev);
7b139c83
AK		 2317
2318 switch (pdev->device) {
2319 case BE_DEVICE_ID1:
2320 case OC_DEVICE_ID1:
2321 adapter->generation = BE_GEN2;
2322 break;
2323 case BE_DEVICE_ID2:
2324 case OC_DEVICE_ID2:
2325 adapter->generation = BE_GEN3;
2326 break;
2327 default:
2328 adapter->generation = 0;
2329 }
2330
6b7c5b94
SP		 2331 adapter->pdev = pdev;
2332 pci_set_drvdata(pdev, adapter);
2333 adapter->netdev = netdev;
2243e2e9
SP		 2334 be_netdev_init(netdev);
2335 SET_NETDEV_DEV(netdev, &pdev->dev);
6b7c5b94
SP		 2336
2337 be_msix_enable(adapter);
2338
e930438c 2339 status = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
6b7c5b94
SP		 2340 if (!status) {
2341 netdev->features |= NETIF_F_HIGHDMA;
2342 } else {
e930438c 2343 status = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
6b7c5b94
SP		 2344 if (status) {
2345 dev_err(&pdev->dev, "Could not set PCI DMA Mask\n");
2346 goto free_netdev;
2347 }
2348 }
2349
6b7c5b94
SP		 2350 status = be_ctrl_init(adapter);
2351 if (status)
2352 goto free_netdev;
2353
2243e2e9
SP		 2354 /* sync up with fw's ready state */
2355 status = be_cmd_POST(adapter);
6b7c5b94
SP		 2356 if (status)
2357 goto ctrl_clean;
2358
2243e2e9
SP		 2359 /* tell fw we're ready to fire cmds */
2360 status = be_cmd_fw_init(adapter);
6b7c5b94 2361 if (status)
2243e2e9
SP		 2362 goto ctrl_clean;
2363
2364 status = be_cmd_reset_function(adapter);
2365 if (status)
2366 goto ctrl_clean;
6b7c5b94 2367
2243e2e9
SP		 2368 status = be_stats_init(adapter);
2369 if (status)
2370 goto ctrl_clean;
2371
2372 status = be_get_config(adapter);
6b7c5b94
SP		 2373 if (status)
2374 goto stats_clean;
6b7c5b94
SP		 2375
2376 INIT_DELAYED_WORK(&adapter->work, be_worker);
6b7c5b94 2377
5fb379ee
SP		 2378 status = be_setup(adapter);
2379 if (status)
2380 goto stats_clean;
2243e2e9 2381
6b7c5b94
SP		 2382 status = register_netdev(netdev);
2383 if (status != 0)
5fb379ee 2384 goto unsetup;
6b7c5b94 2385
c4ca2374 2386 dev_info(&pdev->dev, "%s port %d\n", nic_name(pdev), adapter->port_num);
6b7c5b94
SP		 2387 return 0;
2388
5fb379ee
SP		 2389unsetup:
2390 be_clear(adapter);
6b7c5b94
SP		 2391stats_clean:
2392 be_stats_cleanup(adapter);
2393ctrl_clean:
2394 be_ctrl_cleanup(adapter);
2395free_netdev:
8d56ff11 2396 be_msix_disable(adapter);
6b7c5b94 2397 free_netdev(adapter->netdev);
8d56ff11 2398 pci_set_drvdata(pdev, NULL);
6b7c5b94
SP		 2399rel_reg:
2400 pci_release_regions(pdev);
2401disable_dev:
2402 pci_disable_device(pdev);
2403do_none:
c4ca2374 2404 dev_err(&pdev->dev, "%s initialization failed\n", nic_name(pdev));
6b7c5b94
SP		 2405 return status;
2406}
2407
2408static int be_suspend(struct pci_dev *pdev, pm_message_t state)
2409{
2410 struct be_adapter *adapter = pci_get_drvdata(pdev);
2411 struct net_device *netdev = adapter->netdev;
2412
71d8d1b5
AK		 2413 if (adapter->wol)
2414 be_setup_wol(adapter, true);
2415
6b7c5b94
SP		 2416 netif_device_detach(netdev);
2417 if (netif_running(netdev)) {
2418 rtnl_lock();
2419 be_close(netdev);
2420 rtnl_unlock();
2421 }
9e90c961 2422 be_cmd_get_flow_control(adapter, &adapter->tx_fc, &adapter->rx_fc);
9b0365f1 2423 be_clear(adapter);
6b7c5b94
SP		 2424
2425 pci_save_state(pdev);
2426 pci_disable_device(pdev);
2427 pci_set_power_state(pdev, pci_choose_state(pdev, state));
2428 return 0;
2429}
2430
2431static int be_resume(struct pci_dev *pdev)
2432{
2433 int status = 0;
2434 struct be_adapter *adapter = pci_get_drvdata(pdev);
2435 struct net_device *netdev = adapter->netdev;
2436
2437 netif_device_detach(netdev);
2438
2439 status = pci_enable_device(pdev);
2440 if (status)
2441 return status;
2442
2443 pci_set_power_state(pdev, 0);
2444 pci_restore_state(pdev);
2445
2243e2e9
SP		 2446 /* tell fw we're ready to fire cmds */
2447 status = be_cmd_fw_init(adapter);
2448 if (status)
2449 return status;
2450
9b0365f1 2451 be_setup(adapter);
6b7c5b94
SP		 2452 if (netif_running(netdev)) {
2453 rtnl_lock();
2454 be_open(netdev);
2455 rtnl_unlock();
2456 }
2457 netif_device_attach(netdev);
71d8d1b5
AK		 2458
2459 if (adapter->wol)
2460 be_setup_wol(adapter, false);
6b7c5b94
SP		 2461 return 0;
2462}
2463
82456b03
SP		 2464/*
2465 * An FLR will stop BE from DMAing any data.
2466 */
2467static void be_shutdown(struct pci_dev *pdev)
2468{
2469 struct be_adapter *adapter = pci_get_drvdata(pdev);
2470 struct net_device *netdev = adapter->netdev;
2471
2472 netif_device_detach(netdev);
2473
2474 be_cmd_reset_function(adapter);
2475
2476 if (adapter->wol)
2477 be_setup_wol(adapter, true);
2478
2479 pci_disable_device(pdev);
2480
2481 return;
2482}
2483
cf588477
SP		 2484static pci_ers_result_t be_eeh_err_detected(struct pci_dev *pdev,
2485 pci_channel_state_t state)
2486{
2487 struct be_adapter *adapter = pci_get_drvdata(pdev);
2488 struct net_device *netdev = adapter->netdev;
2489
2490 dev_err(&adapter->pdev->dev, "EEH error detected\n");
2491
2492 adapter->eeh_err = true;
2493
2494 netif_device_detach(netdev);
2495
2496 if (netif_running(netdev)) {
2497 rtnl_lock();
2498 be_close(netdev);
2499 rtnl_unlock();
2500 }
2501 be_clear(adapter);
2502
2503 if (state == pci_channel_io_perm_failure)
2504 return PCI_ERS_RESULT_DISCONNECT;
2505
2506 pci_disable_device(pdev);
2507
2508 return PCI_ERS_RESULT_NEED_RESET;
2509}
2510
2511static pci_ers_result_t be_eeh_reset(struct pci_dev *pdev)
2512{
2513 struct be_adapter *adapter = pci_get_drvdata(pdev);
2514 int status;
2515
2516 dev_info(&adapter->pdev->dev, "EEH reset\n");
2517 adapter->eeh_err = false;
2518
2519 status = pci_enable_device(pdev);
2520 if (status)
2521 return PCI_ERS_RESULT_DISCONNECT;
2522
2523 pci_set_master(pdev);
2524 pci_set_power_state(pdev, 0);
2525 pci_restore_state(pdev);
2526
2527 /* Check if card is ok and fw is ready */
2528 status = be_cmd_POST(adapter);
2529 if (status)
2530 return PCI_ERS_RESULT_DISCONNECT;
2531
2532 return PCI_ERS_RESULT_RECOVERED;
2533}
2534
2535static void be_eeh_resume(struct pci_dev *pdev)
2536{
2537 int status = 0;
2538 struct be_adapter *adapter = pci_get_drvdata(pdev);
2539 struct net_device *netdev = adapter->netdev;
2540
2541 dev_info(&adapter->pdev->dev, "EEH resume\n");
2542
2543 pci_save_state(pdev);
2544
2545 /* tell fw we're ready to fire cmds */
2546 status = be_cmd_fw_init(adapter);
2547 if (status)
2548 goto err;
2549
2550 status = be_setup(adapter);
2551 if (status)
2552 goto err;
2553
2554 if (netif_running(netdev)) {
2555 status = be_open(netdev);
2556 if (status)
2557 goto err;
2558 }
2559 netif_device_attach(netdev);
2560 return;
2561err:
2562 dev_err(&adapter->pdev->dev, "EEH resume failed\n");
2563 return;
2564}
2565
2566static struct pci_error_handlers be_eeh_handlers = {
2567 .error_detected = be_eeh_err_detected,
2568 .slot_reset = be_eeh_reset,
2569 .resume = be_eeh_resume,
2570};
2571
6b7c5b94
SP		 2572static struct pci_driver be_driver = {
2573 .name = DRV_NAME,
2574 .id_table = be_dev_ids,
2575 .probe = be_probe,
2576 .remove = be_remove,
2577 .suspend = be_suspend,
cf588477 2578 .resume = be_resume,
82456b03 2579 .shutdown = be_shutdown,
cf588477 2580 .err_handler = &be_eeh_handlers
6b7c5b94
SP		 2581};
2582
2583static int __init be_init_module(void)
2584{
8e95a202
JP		 2585 if (rx_frag_size != 8192 && rx_frag_size != 4096 &&
2586 rx_frag_size != 2048) {
6b7c5b94
SP		 2587 printk(KERN_WARNING DRV_NAME
2588 " : Module param rx_frag_size must be 2048/4096/8192."
2589 " Using 2048\n");
2590 rx_frag_size = 2048;
2591 }
6b7c5b94
SP		 2592
2593 return pci_register_driver(&be_driver);
2594}
2595module_init(be_init_module);
2596
2597static void __exit be_exit_module(void)
2598{
2599 pci_unregister_driver(&be_driver);
2600}
2601module_exit(be_exit_module);
Linux kernel - Deliverables
This page took 0.256018 seconds and 5 git commands to generate.