projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
be2net: gracefully handle situations when UE is detected
[deliverable/linux.git] / drivers / net / benet / be_main.c
CommitLineData
6b7c5b94 1/*
294aedcf 2 * Copyright (C) 2005 - 2010 ServerEngines
6b7c5b94
SP		 3 * All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License version 2
7 * as published by the Free Software Foundation. The full GNU General
8 * Public License is included in this distribution in the file called COPYING.
9 *
10 * Contact Information:
11 * linux-drivers@serverengines.com
12 *
13 * ServerEngines
14 * 209 N. Fair Oaks Ave
15 * Sunnyvale, CA 94085
16 */
17
18#include "be.h"
8788fdc2 19#include "be_cmds.h"
65f71b8b 20#include <asm/div64.h>
6b7c5b94
SP		 21
22MODULE_VERSION(DRV_VER);
23MODULE_DEVICE_TABLE(pci, be_dev_ids);
24MODULE_DESCRIPTION(DRV_DESC " " DRV_VER);
25MODULE_AUTHOR("ServerEngines Corporation");
26MODULE_LICENSE("GPL");
27
28static unsigned int rx_frag_size = 2048;
ba343c77 29static unsigned int num_vfs;
6b7c5b94 30module_param(rx_frag_size, uint, S_IRUGO);
ba343c77 31module_param(num_vfs, uint, S_IRUGO);
6b7c5b94 32MODULE_PARM_DESC(rx_frag_size, "Size of a fragment that holds rcvd data.");
ba343c77 33MODULE_PARM_DESC(num_vfs, "Number of PCI VFs to initialize");
6b7c5b94 34
3abcdeda
SP		 35static bool multi_rxq = true;
36module_param(multi_rxq, bool, S_IRUGO | S_IWUSR);
37MODULE_PARM_DESC(multi_rxq, "Multi Rx Queue support. Enabled by default");
38
6b7c5b94 39static DEFINE_PCI_DEVICE_TABLE(be_dev_ids) = {
c4ca2374 40 { PCI_DEVICE(BE_VENDOR_ID, BE_DEVICE_ID1) },
59fd5d87 41 { PCI_DEVICE(BE_VENDOR_ID, BE_DEVICE_ID2) },
c4ca2374
AK		 42 { PCI_DEVICE(BE_VENDOR_ID, OC_DEVICE_ID1) },
43 { PCI_DEVICE(BE_VENDOR_ID, OC_DEVICE_ID2) },
fe6d2a38 44 { PCI_DEVICE(EMULEX_VENDOR_ID, OC_DEVICE_ID3)},
6b7c5b94
SP		 45 { 0 }
46};
47MODULE_DEVICE_TABLE(pci, be_dev_ids);
7c185276
AK		 48/* UE Status Low CSR */
49static char *ue_status_low_desc[] = {
50 "CEV",
51 "CTX",
52 "DBUF",
53 "ERX",
54 "Host",
55 "MPU",
56 "NDMA",
57 "PTC ",
58 "RDMA ",
59 "RXF ",
60 "RXIPS ",
61 "RXULP0 ",
62 "RXULP1 ",
63 "RXULP2 ",
64 "TIM ",
65 "TPOST ",
66 "TPRE ",
67 "TXIPS ",
68 "TXULP0 ",
69 "TXULP1 ",
70 "UC ",
71 "WDMA ",
72 "TXULP2 ",
73 "HOST1 ",
74 "P0_OB_LINK ",
75 "P1_OB_LINK ",
76 "HOST_GPIO ",
77 "MBOX ",
78 "AXGMAC0",
79 "AXGMAC1",
80 "JTAG",
81 "MPU_INTPEND"
82};
83/* UE Status High CSR */
84static char *ue_status_hi_desc[] = {
85 "LPCMEMHOST",
86 "MGMT_MAC",
87 "PCS0ONLINE",
88 "MPU_IRAM",
89 "PCS1ONLINE",
90 "PCTL0",
91 "PCTL1",
92 "PMEM",
93 "RR",
94 "TXPB",
95 "RXPP",
96 "XAUI",
97 "TXP",
98 "ARM",
99 "IPC",
100 "HOST2",
101 "HOST3",
102 "HOST4",
103 "HOST5",
104 "HOST6",
105 "HOST7",
106 "HOST8",
107 "HOST9",
108 "NETC"
109 "Unknown",
110 "Unknown",
111 "Unknown",
112 "Unknown",
113 "Unknown",
114 "Unknown",
115 "Unknown",
116 "Unknown"
117};
6b7c5b94 118
3abcdeda
SP		 119static inline bool be_multi_rxq(struct be_adapter *adapter)
120{
121 return (adapter->num_rx_qs > 1);
122}
123
6b7c5b94
SP		 124static void be_queue_free(struct be_adapter *adapter, struct be_queue_info *q)
125{
126 struct be_dma_mem *mem = &q->dma_mem;
127 if (mem->va)
2b7bcebf
IV		 128 dma_free_coherent(&adapter->pdev->dev, mem->size, mem->va,
129 mem->dma);
6b7c5b94
SP		 130}
131
132static int be_queue_alloc(struct be_adapter *adapter, struct be_queue_info *q,
133 u16 len, u16 entry_size)
134{
135 struct be_dma_mem *mem = &q->dma_mem;
136
137 memset(q, 0, sizeof(*q));
138 q->len = len;
139 q->entry_size = entry_size;
140 mem->size = len * entry_size;
2b7bcebf
IV		 141 mem->va = dma_alloc_coherent(&adapter->pdev->dev, mem->size, &mem->dma,
142 GFP_KERNEL);
6b7c5b94
SP		 143 if (!mem->va)
144 return -1;
145 memset(mem->va, 0, mem->size);
146 return 0;
147}
148
8788fdc2 149static void be_intr_set(struct be_adapter *adapter, bool enable)
6b7c5b94 150{
8788fdc2 151 u8 __iomem *addr = adapter->pcicfg + PCICFG_MEMBAR_CTRL_INT_CTRL_OFFSET;
6b7c5b94
SP		 152 u32 reg = ioread32(addr);
153 u32 enabled = reg & MEMBAR_CTRL_INT_CTRL_HOSTINTR_MASK;
5f0b849e 154
cf588477
SP		 155 if (adapter->eeh_err)
156 return;
157
5f0b849e 158 if (!enabled && enable)
6b7c5b94 159 reg |= MEMBAR_CTRL_INT_CTRL_HOSTINTR_MASK;
5f0b849e 160 else if (enabled && !enable)
6b7c5b94 161 reg &= ~MEMBAR_CTRL_INT_CTRL_HOSTINTR_MASK;
5f0b849e 162 else
6b7c5b94 163 return;
5f0b849e 164
6b7c5b94
SP		 165 iowrite32(reg, addr);
166}
167
8788fdc2 168static void be_rxq_notify(struct be_adapter *adapter, u16 qid, u16 posted)
6b7c5b94
SP		 169{
170 u32 val = 0;
171 val |= qid & DB_RQ_RING_ID_MASK;
172 val |= posted << DB_RQ_NUM_POSTED_SHIFT;
f3eb62d2
SP		 173
174 wmb();
8788fdc2 175 iowrite32(val, adapter->db + DB_RQ_OFFSET);
6b7c5b94
SP		 176}
177
8788fdc2 178static void be_txq_notify(struct be_adapter *adapter, u16 qid, u16 posted)
6b7c5b94
SP		 179{
180 u32 val = 0;
181 val |= qid & DB_TXULP_RING_ID_MASK;
182 val |= (posted & DB_TXULP_NUM_POSTED_MASK) << DB_TXULP_NUM_POSTED_SHIFT;
f3eb62d2
SP		 183
184 wmb();
8788fdc2 185 iowrite32(val, adapter->db + DB_TXULP1_OFFSET);
6b7c5b94
SP		 186}
187
8788fdc2 188static void be_eq_notify(struct be_adapter *adapter, u16 qid,
6b7c5b94
SP		 189 bool arm, bool clear_int, u16 num_popped)
190{
191 u32 val = 0;
192 val |= qid & DB_EQ_RING_ID_MASK;
fe6d2a38
SP		 193 val |= ((qid & DB_EQ_RING_ID_EXT_MASK) <<
194 DB_EQ_RING_ID_EXT_MASK_SHIFT);
cf588477
SP		 195
196 if (adapter->eeh_err)
197 return;
198
6b7c5b94
SP		 199 if (arm)
200 val |= 1 << DB_EQ_REARM_SHIFT;
201 if (clear_int)
202 val |= 1 << DB_EQ_CLR_SHIFT;
203 val |= 1 << DB_EQ_EVNT_SHIFT;
204 val |= num_popped << DB_EQ_NUM_POPPED_SHIFT;
8788fdc2 205 iowrite32(val, adapter->db + DB_EQ_OFFSET);
6b7c5b94
SP		 206}
207
8788fdc2 208void be_cq_notify(struct be_adapter *adapter, u16 qid, bool arm, u16 num_popped)
6b7c5b94
SP		 209{
210 u32 val = 0;
211 val |= qid & DB_CQ_RING_ID_MASK;
fe6d2a38
SP		 212 val |= ((qid & DB_CQ_RING_ID_EXT_MASK) <<
213 DB_CQ_RING_ID_EXT_MASK_SHIFT);
cf588477
SP		 214
215 if (adapter->eeh_err)
216 return;
217
6b7c5b94
SP		 218 if (arm)
219 val |= 1 << DB_CQ_REARM_SHIFT;
220 val |= num_popped << DB_CQ_NUM_POPPED_SHIFT;
8788fdc2 221 iowrite32(val, adapter->db + DB_CQ_OFFSET);
6b7c5b94
SP		 222}
223
6b7c5b94
SP		 224static int be_mac_addr_set(struct net_device *netdev, void *p)
225{
226 struct be_adapter *adapter = netdev_priv(netdev);
227 struct sockaddr *addr = p;
228 int status = 0;
229
ca9e4988
AK		 230 if (!is_valid_ether_addr(addr->sa_data))
231 return -EADDRNOTAVAIL;
232
ba343c77
SB		 233 /* MAC addr configuration will be done in hardware for VFs
234 * by their corresponding PFs. Just copy to netdev addr here
235 */
236 if (!be_physfn(adapter))
237 goto netdev_addr;
238
f8617e08
AK		 239 status = be_cmd_pmac_del(adapter, adapter->if_handle,
240 adapter->pmac_id, 0);
a65027e4
SP		 241 if (status)
242 return status;
6b7c5b94 243
a65027e4 244 status = be_cmd_pmac_add(adapter, (u8 *)addr->sa_data,
f8617e08 245 adapter->if_handle, &adapter->pmac_id, 0);
ba343c77 246netdev_addr:
6b7c5b94
SP		 247 if (!status)
248 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
249
250 return status;
251}
252
b31c50a7 253void netdev_stats_update(struct be_adapter *adapter)
6b7c5b94 254{
3abcdeda 255 struct be_hw_stats *hw_stats = hw_stats_from_cmd(adapter->stats_cmd.va);
6b7c5b94
SP		 256 struct be_rxf_stats *rxf_stats = &hw_stats->rxf;
257 struct be_port_rxf_stats *port_stats =
258 &rxf_stats->port[adapter->port_num];
78122a52 259 struct net_device_stats *dev_stats = &adapter->netdev->stats;
68110868 260 struct be_erx_stats *erx_stats = &hw_stats->erx;
3abcdeda
SP		 261 struct be_rx_obj *rxo;
262 int i;
6b7c5b94 263
3abcdeda
SP		 264 memset(dev_stats, 0, sizeof(*dev_stats));
265 for_all_rx_queues(adapter, rxo, i) {
266 dev_stats->rx_packets += rx_stats(rxo)->rx_pkts;
267 dev_stats->rx_bytes += rx_stats(rxo)->rx_bytes;
268 dev_stats->multicast += rx_stats(rxo)->rx_mcast_pkts;
269 /* no space in linux buffers: best possible approximation */
270 dev_stats->rx_dropped +=
271 erx_stats->rx_drops_no_fragments[rxo->q.id];
272 }
273
274 dev_stats->tx_packets = tx_stats(adapter)->be_tx_pkts;
275 dev_stats->tx_bytes = tx_stats(adapter)->be_tx_bytes;
6b7c5b94
SP		 276
277 /* bad pkts received */
278 dev_stats->rx_errors = port_stats->rx_crc_errors +
279 port_stats->rx_alignment_symbol_errors +
280 port_stats->rx_in_range_errors +
68110868
SP		 281 port_stats->rx_out_range_errors +
282 port_stats->rx_frame_too_long +
283 port_stats->rx_dropped_too_small +
284 port_stats->rx_dropped_too_short +
285 port_stats->rx_dropped_header_too_small +
286 port_stats->rx_dropped_tcp_length +
287 port_stats->rx_dropped_runt +
288 port_stats->rx_tcp_checksum_errs +
289 port_stats->rx_ip_checksum_errs +
290 port_stats->rx_udp_checksum_errs;
291
6b7c5b94
SP		 292 /* detailed rx errors */
293 dev_stats->rx_length_errors = port_stats->rx_in_range_errors +
68110868
SP		 294 port_stats->rx_out_range_errors +
295 port_stats->rx_frame_too_long;
296
6b7c5b94
SP		 297 dev_stats->rx_crc_errors = port_stats->rx_crc_errors;
298
299 /* frame alignment errors */
300 dev_stats->rx_frame_errors = port_stats->rx_alignment_symbol_errors;
68110868 301
6b7c5b94
SP		 302 /* receiver fifo overrun */
303 /* drops_no_pbuf is no per i/f, it's per BE card */
304 dev_stats->rx_fifo_errors = port_stats->rx_fifo_overflow +
305 port_stats->rx_input_fifo_overflow +
306 rxf_stats->rx_drops_no_pbuf;
6b7c5b94
SP		 307}
308
8788fdc2 309void be_link_status_update(struct be_adapter *adapter, bool link_up)
6b7c5b94 310{
6b7c5b94
SP		 311 struct net_device *netdev = adapter->netdev;
312
6b7c5b94 313 /* If link came up or went down */
a8f447bd 314 if (adapter->link_up != link_up) {
0dffc83e 315 adapter->link_speed = -1;
a8f447bd 316 if (link_up) {
6b7c5b94
SP		 317 netif_carrier_on(netdev);
318 printk(KERN_INFO "%s: Link up\n", netdev->name);
a8f447bd 319 } else {
a8f447bd
SP		 320 netif_carrier_off(netdev);
321 printk(KERN_INFO "%s: Link down\n", netdev->name);
6b7c5b94 322 }
a8f447bd 323 adapter->link_up = link_up;
6b7c5b94 324 }
6b7c5b94
SP		 325}
326
327/* Update the EQ delay n BE based on the RX frags consumed / sec */
3abcdeda 328static void be_rx_eqd_update(struct be_adapter *adapter, struct be_rx_obj *rxo)
6b7c5b94 329{
3abcdeda
SP		 330 struct be_eq_obj *rx_eq = &rxo->rx_eq;
331 struct be_rx_stats *stats = &rxo->stats;
4097f663
SP		 332 ulong now = jiffies;
333 u32 eqd;
334
335 if (!rx_eq->enable_aic)
336 return;
337
338 /* Wrapped around */
339 if (time_before(now, stats->rx_fps_jiffies)) {
340 stats->rx_fps_jiffies = now;
341 return;
342 }
6b7c5b94
SP		 343
344 /* Update once a second */
4097f663 345 if ((now - stats->rx_fps_jiffies) < HZ)
6b7c5b94
SP		 346 return;
347
3abcdeda 348 stats->rx_fps = (stats->rx_frags - stats->prev_rx_frags) /
4097f663 349 ((now - stats->rx_fps_jiffies) / HZ);
6b7c5b94 350
4097f663 351 stats->rx_fps_jiffies = now;
3abcdeda
SP		 352 stats->prev_rx_frags = stats->rx_frags;
353 eqd = stats->rx_fps / 110000;
6b7c5b94
SP		 354 eqd = eqd << 3;
355 if (eqd > rx_eq->max_eqd)
356 eqd = rx_eq->max_eqd;
357 if (eqd < rx_eq->min_eqd)
358 eqd = rx_eq->min_eqd;
359 if (eqd < 10)
360 eqd = 0;
361 if (eqd != rx_eq->cur_eqd)
8788fdc2 362 be_cmd_modify_eqd(adapter, rx_eq->q.id, eqd);
6b7c5b94
SP		 363
364 rx_eq->cur_eqd = eqd;
365}
366
65f71b8b
SH		 367static u32 be_calc_rate(u64 bytes, unsigned long ticks)
368{
369 u64 rate = bytes;
370
371 do_div(rate, ticks / HZ);
372 rate <<= 3; /* bytes/sec -> bits/sec */
373 do_div(rate, 1000000ul); /* MB/Sec */
374
375 return rate;
376}
377
4097f663
SP		 378static void be_tx_rate_update(struct be_adapter *adapter)
379{
3abcdeda 380 struct be_tx_stats *stats = tx_stats(adapter);
4097f663
SP		 381 ulong now = jiffies;
382
383 /* Wrapped around? */
384 if (time_before(now, stats->be_tx_jiffies)) {
385 stats->be_tx_jiffies = now;
386 return;
387 }
388
389 /* Update tx rate once in two seconds */
390 if ((now - stats->be_tx_jiffies) > 2 * HZ) {
65f71b8b
SH		 391 stats->be_tx_rate = be_calc_rate(stats->be_tx_bytes
392 - stats->be_tx_bytes_prev,
393 now - stats->be_tx_jiffies);
4097f663
SP		 394 stats->be_tx_jiffies = now;
395 stats->be_tx_bytes_prev = stats->be_tx_bytes;
396 }
397}
398
6b7c5b94 399static void be_tx_stats_update(struct be_adapter *adapter,
91992e44 400 u32 wrb_cnt, u32 copied, u32 gso_segs, bool stopped)
6b7c5b94 401{
3abcdeda 402 struct be_tx_stats *stats = tx_stats(adapter);
6b7c5b94
SP		 403 stats->be_tx_reqs++;
404 stats->be_tx_wrbs += wrb_cnt;
405 stats->be_tx_bytes += copied;
91992e44 406 stats->be_tx_pkts += (gso_segs ? gso_segs : 1);
6b7c5b94
SP		 407 if (stopped)
408 stats->be_tx_stops++;
6b7c5b94
SP		 409}
410
411/* Determine number of WRB entries needed to xmit data in an skb */
fe6d2a38
SP		 412static u32 wrb_cnt_for_skb(struct be_adapter *adapter, struct sk_buff *skb,
413 bool *dummy)
6b7c5b94 414{
ebc8d2ab
DM		 415 int cnt = (skb->len > skb->data_len);
416
417 cnt += skb_shinfo(skb)->nr_frags;
418
6b7c5b94
SP		 419 /* to account for hdr wrb */
420 cnt++;
fe6d2a38
SP		 421 if (lancer_chip(adapter) || !(cnt & 1)) {
422 *dummy = false;
423 } else {
6b7c5b94
SP		 424 /* add a dummy to make it an even num */
425 cnt++;
426 *dummy = true;
fe6d2a38 427 }
6b7c5b94
SP		 428 BUG_ON(cnt > BE_MAX_TX_FRAG_COUNT);
429 return cnt;
430}
431
432static inline void wrb_fill(struct be_eth_wrb *wrb, u64 addr, int len)
433{
434 wrb->frag_pa_hi = upper_32_bits(addr);
435 wrb->frag_pa_lo = addr & 0xFFFFFFFF;
436 wrb->frag_len = len & ETH_WRB_FRAG_LEN_MASK;
437}
438
cc4ce020
SK		 439static void wrb_fill_hdr(struct be_adapter *adapter, struct be_eth_hdr_wrb *hdr,
440 struct sk_buff *skb, u32 wrb_cnt, u32 len)
6b7c5b94 441{
cc4ce020
SK		 442 u8 vlan_prio = 0;
443 u16 vlan_tag = 0;
444
6b7c5b94
SP		 445 memset(hdr, 0, sizeof(*hdr));
446
447 AMAP_SET_BITS(struct amap_eth_hdr_wrb, crc, hdr, 1);
448
49e4b847 449 if (skb_is_gso(skb)) {
6b7c5b94
SP		 450 AMAP_SET_BITS(struct amap_eth_hdr_wrb, lso, hdr, 1);
451 AMAP_SET_BITS(struct amap_eth_hdr_wrb, lso_mss,
452 hdr, skb_shinfo(skb)->gso_size);
fe6d2a38 453 if (skb_is_gso_v6(skb) && !lancer_chip(adapter))
49e4b847 454 AMAP_SET_BITS(struct amap_eth_hdr_wrb, lso6, hdr, 1);
fe6d2a38
SP		 455 if (lancer_chip(adapter) && adapter->sli_family ==
456 LANCER_A0_SLI_FAMILY) {
457 AMAP_SET_BITS(struct amap_eth_hdr_wrb, ipcs, hdr, 1);
458 if (is_tcp_pkt(skb))
459 AMAP_SET_BITS(struct amap_eth_hdr_wrb,
460 tcpcs, hdr, 1);
461 else if (is_udp_pkt(skb))
462 AMAP_SET_BITS(struct amap_eth_hdr_wrb,
463 udpcs, hdr, 1);
464 }
6b7c5b94
SP		 465 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
466 if (is_tcp_pkt(skb))
467 AMAP_SET_BITS(struct amap_eth_hdr_wrb, tcpcs, hdr, 1);
468 else if (is_udp_pkt(skb))
469 AMAP_SET_BITS(struct amap_eth_hdr_wrb, udpcs, hdr, 1);
470 }
471
cc4ce020 472 if (adapter->vlan_grp && vlan_tx_tag_present(skb)) {
6b7c5b94 473 AMAP_SET_BITS(struct amap_eth_hdr_wrb, vlan, hdr, 1);
cc4ce020
SK		 474 vlan_tag = vlan_tx_tag_get(skb);
475 vlan_prio = (vlan_tag & VLAN_PRIO_MASK) >> VLAN_PRIO_SHIFT;
476 /* If vlan priority provided by OS is NOT in available bmap */
477 if (!(adapter->vlan_prio_bmap & (1 << vlan_prio)))
478 vlan_tag = (vlan_tag & ~VLAN_PRIO_MASK) |
479 adapter->recommended_prio;
480 AMAP_SET_BITS(struct amap_eth_hdr_wrb, vlan_tag, hdr, vlan_tag);
6b7c5b94
SP		 481 }
482
483 AMAP_SET_BITS(struct amap_eth_hdr_wrb, event, hdr, 1);
484 AMAP_SET_BITS(struct amap_eth_hdr_wrb, complete, hdr, 1);
485 AMAP_SET_BITS(struct amap_eth_hdr_wrb, num_wrb, hdr, wrb_cnt);
486 AMAP_SET_BITS(struct amap_eth_hdr_wrb, len, hdr, len);
487}
488
2b7bcebf 489static void unmap_tx_frag(struct device *dev, struct be_eth_wrb *wrb,
7101e111
SP		 490 bool unmap_single)
491{
492 dma_addr_t dma;
493
494 be_dws_le_to_cpu(wrb, sizeof(*wrb));
495
496 dma = (u64)wrb->frag_pa_hi << 32 | (u64)wrb->frag_pa_lo;
b681ee77 497 if (wrb->frag_len) {
7101e111 498 if (unmap_single)
2b7bcebf
IV		 499 dma_unmap_single(dev, dma, wrb->frag_len,
500 DMA_TO_DEVICE);
7101e111 501 else
2b7bcebf 502 dma_unmap_page(dev, dma, wrb->frag_len, DMA_TO_DEVICE);
7101e111
SP		 503 }
504}
6b7c5b94
SP		 505
506static int make_tx_wrbs(struct be_adapter *adapter,
507 struct sk_buff *skb, u32 wrb_cnt, bool dummy_wrb)
508{
7101e111
SP		 509 dma_addr_t busaddr;
510 int i, copied = 0;
2b7bcebf 511 struct device *dev = &adapter->pdev->dev;
6b7c5b94
SP		 512 struct sk_buff *first_skb = skb;
513 struct be_queue_info *txq = &adapter->tx_obj.q;
514 struct be_eth_wrb *wrb;
515 struct be_eth_hdr_wrb *hdr;
7101e111
SP		 516 bool map_single = false;
517 u16 map_head;
6b7c5b94 518
6b7c5b94
SP		 519 hdr = queue_head_node(txq);
520 queue_head_inc(txq);
7101e111 521 map_head = txq->head;
6b7c5b94 522
ebc8d2ab 523 if (skb->len > skb->data_len) {
e743d313 524 int len = skb_headlen(skb);
2b7bcebf
IV		 525 busaddr = dma_map_single(dev, skb->data, len, DMA_TO_DEVICE);
526 if (dma_mapping_error(dev, busaddr))
7101e111
SP		 527 goto dma_err;
528 map_single = true;
ebc8d2ab
DM		 529 wrb = queue_head_node(txq);
530 wrb_fill(wrb, busaddr, len);
531 be_dws_cpu_to_le(wrb, sizeof(*wrb));
532 queue_head_inc(txq);
533 copied += len;
534 }
6b7c5b94 535
ebc8d2ab
DM		 536 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
537 struct skb_frag_struct *frag =
538 &skb_shinfo(skb)->frags[i];
2b7bcebf
IV		 539 busaddr = dma_map_page(dev, frag->page, frag->page_offset,
540 frag->size, DMA_TO_DEVICE);
541 if (dma_mapping_error(dev, busaddr))
7101e111 542 goto dma_err;
ebc8d2ab
DM		 543 wrb = queue_head_node(txq);
544 wrb_fill(wrb, busaddr, frag->size);
545 be_dws_cpu_to_le(wrb, sizeof(*wrb));
546 queue_head_inc(txq);
547 copied += frag->size;
6b7c5b94
SP		 548 }
549
550 if (dummy_wrb) {
551 wrb = queue_head_node(txq);
552 wrb_fill(wrb, 0, 0);
553 be_dws_cpu_to_le(wrb, sizeof(*wrb));
554 queue_head_inc(txq);
555 }
556
cc4ce020 557 wrb_fill_hdr(adapter, hdr, first_skb, wrb_cnt, copied);
6b7c5b94
SP		 558 be_dws_cpu_to_le(hdr, sizeof(*hdr));
559
560 return copied;
7101e111
SP		 561dma_err:
562 txq->head = map_head;
563 while (copied) {
564 wrb = queue_head_node(txq);
2b7bcebf 565 unmap_tx_frag(dev, wrb, map_single);
7101e111
SP		 566 map_single = false;
567 copied -= wrb->frag_len;
568 queue_head_inc(txq);
569 }
570 return 0;
6b7c5b94
SP		 571}
572
61357325 573static netdev_tx_t be_xmit(struct sk_buff *skb,
b31c50a7 574 struct net_device *netdev)
6b7c5b94
SP		 575{
576 struct be_adapter *adapter = netdev_priv(netdev);
577 struct be_tx_obj *tx_obj = &adapter->tx_obj;
578 struct be_queue_info *txq = &tx_obj->q;
579 u32 wrb_cnt = 0, copied = 0;
580 u32 start = txq->head;
581 bool dummy_wrb, stopped = false;
582
fe6d2a38 583 wrb_cnt = wrb_cnt_for_skb(adapter, skb, &dummy_wrb);
6b7c5b94
SP		 584
585 copied = make_tx_wrbs(adapter, skb, wrb_cnt, dummy_wrb);
c190e3c8
AK		 586 if (copied) {
587 /* record the sent skb in the sent_skb table */
588 BUG_ON(tx_obj->sent_skb_list[start]);
589 tx_obj->sent_skb_list[start] = skb;
590
591 /* Ensure txq has space for the next skb; Else stop the queue
592 * *BEFORE* ringing the tx doorbell, so that we serialze the
593 * tx compls of the current transmit which'll wake up the queue
594 */
7101e111 595 atomic_add(wrb_cnt, &txq->used);
c190e3c8
AK		 596 if ((BE_MAX_TX_FRAG_COUNT + atomic_read(&txq->used)) >=
597 txq->len) {
598 netif_stop_queue(netdev);
599 stopped = true;
600 }
6b7c5b94 601
c190e3c8 602 be_txq_notify(adapter, txq->id, wrb_cnt);
6b7c5b94 603
91992e44
AK		 604 be_tx_stats_update(adapter, wrb_cnt, copied,
605 skb_shinfo(skb)->gso_segs, stopped);
c190e3c8
AK		 606 } else {
607 txq->head = start;
608 dev_kfree_skb_any(skb);
6b7c5b94 609 }
6b7c5b94
SP		 610 return NETDEV_TX_OK;
611}
612
613static int be_change_mtu(struct net_device *netdev, int new_mtu)
614{
615 struct be_adapter *adapter = netdev_priv(netdev);
616 if (new_mtu < BE_MIN_MTU ||
34a89b8c
AK		 617 new_mtu > (BE_MAX_JUMBO_FRAME_SIZE -
618 (ETH_HLEN + ETH_FCS_LEN))) {
6b7c5b94
SP		 619 dev_info(&adapter->pdev->dev,
620 "MTU must be between %d and %d bytes\n",
34a89b8c
AK		 621 BE_MIN_MTU,
622 (BE_MAX_JUMBO_FRAME_SIZE - (ETH_HLEN + ETH_FCS_LEN)));
6b7c5b94
SP		 623 return -EINVAL;
624 }
625 dev_info(&adapter->pdev->dev, "MTU changed from %d to %d bytes\n",
626 netdev->mtu, new_mtu);
627 netdev->mtu = new_mtu;
628 return 0;
629}
630
631/*
82903e4b
AK		 632 * A max of 64 (BE_NUM_VLANS_SUPPORTED) vlans can be configured in BE.
633 * If the user configures more, place BE in vlan promiscuous mode.
6b7c5b94 634 */
1da87b7f 635static int be_vid_config(struct be_adapter *adapter, bool vf, u32 vf_num)
6b7c5b94 636{
6b7c5b94
SP		 637 u16 vtag[BE_NUM_VLANS_SUPPORTED];
638 u16 ntags = 0, i;
82903e4b 639 int status = 0;
1da87b7f
AK		 640 u32 if_handle;
641
642 if (vf) {
643 if_handle = adapter->vf_cfg[vf_num].vf_if_handle;
644 vtag[0] = cpu_to_le16(adapter->vf_cfg[vf_num].vf_vlan_tag);
645 status = be_cmd_vlan_config(adapter, if_handle, vtag, 1, 1, 0);
646 }
6b7c5b94 647
82903e4b 648 if (adapter->vlans_added <= adapter->max_vlans) {
6b7c5b94 649 /* Construct VLAN Table to give to HW */
b738127d 650 for (i = 0; i < VLAN_N_VID; i++) {
6b7c5b94
SP		 651 if (adapter->vlan_tag[i]) {
652 vtag[ntags] = cpu_to_le16(i);
653 ntags++;
654 }
655 }
b31c50a7
SP		 656 status = be_cmd_vlan_config(adapter, adapter->if_handle,
657 vtag, ntags, 1, 0);
6b7c5b94 658 } else {
b31c50a7
SP		 659 status = be_cmd_vlan_config(adapter, adapter->if_handle,
660 NULL, 0, 1, 1);
6b7c5b94 661 }
1da87b7f 662
b31c50a7 663 return status;
6b7c5b94
SP		 664}
665
666static void be_vlan_register(struct net_device *netdev, struct vlan_group *grp)
667{
668 struct be_adapter *adapter = netdev_priv(netdev);
6b7c5b94 669
6b7c5b94 670 adapter->vlan_grp = grp;
6b7c5b94
SP		 671}
672
673static void be_vlan_add_vid(struct net_device *netdev, u16 vid)
674{
675 struct be_adapter *adapter = netdev_priv(netdev);
676
1da87b7f 677 adapter->vlans_added++;
ba343c77
SB		 678 if (!be_physfn(adapter))
679 return;
680
6b7c5b94 681 adapter->vlan_tag[vid] = 1;
82903e4b 682 if (adapter->vlans_added <= (adapter->max_vlans + 1))
1da87b7f 683 be_vid_config(adapter, false, 0);
6b7c5b94
SP		 684}
685
686static void be_vlan_rem_vid(struct net_device *netdev, u16 vid)
687{
688 struct be_adapter *adapter = netdev_priv(netdev);
689
1da87b7f
AK		 690 adapter->vlans_added--;
691 vlan_group_set_device(adapter->vlan_grp, vid, NULL);
692
ba343c77
SB		 693 if (!be_physfn(adapter))
694 return;
695
6b7c5b94 696 adapter->vlan_tag[vid] = 0;
82903e4b 697 if (adapter->vlans_added <= adapter->max_vlans)
1da87b7f 698 be_vid_config(adapter, false, 0);
6b7c5b94
SP		 699}
700
24307eef 701static void be_set_multicast_list(struct net_device *netdev)
6b7c5b94
SP		 702{
703 struct be_adapter *adapter = netdev_priv(netdev);
6b7c5b94 704
24307eef 705 if (netdev->flags & IFF_PROMISC) {
8788fdc2 706 be_cmd_promiscuous_config(adapter, adapter->port_num, 1);
24307eef
SP		 707 adapter->promiscuous = true;
708 goto done;
6b7c5b94
SP		 709 }
710
24307eef
SP		 711 /* BE was previously in promiscous mode; disable it */
712 if (adapter->promiscuous) {
713 adapter->promiscuous = false;
8788fdc2 714 be_cmd_promiscuous_config(adapter, adapter->port_num, 0);
6b7c5b94
SP		 715 }
716
e7b909a6 717 /* Enable multicast promisc if num configured exceeds what we support */
4cd24eaf
JP		 718 if (netdev->flags & IFF_ALLMULTI ||
719 netdev_mc_count(netdev) > BE_MAX_MC) {
0ddf477b 720 be_cmd_multicast_set(adapter, adapter->if_handle, NULL,
e7b909a6 721 &adapter->mc_cmd_mem);
24307eef 722 goto done;
6b7c5b94 723 }
6b7c5b94 724
0ddf477b 725 be_cmd_multicast_set(adapter, adapter->if_handle, netdev,
f31e50a8 726 &adapter->mc_cmd_mem);
24307eef
SP		 727done:
728 return;
6b7c5b94
SP		 729}
730
ba343c77
SB		 731static int be_set_vf_mac(struct net_device *netdev, int vf, u8 *mac)
732{
733 struct be_adapter *adapter = netdev_priv(netdev);
734 int status;
735
736 if (!adapter->sriov_enabled)
737 return -EPERM;
738
739 if (!is_valid_ether_addr(mac) || (vf >= num_vfs))
740 return -EINVAL;
741
64600ea5
AK		 742 if (adapter->vf_cfg[vf].vf_pmac_id != BE_INVALID_PMAC_ID)
743 status = be_cmd_pmac_del(adapter,
744 adapter->vf_cfg[vf].vf_if_handle,
f8617e08 745 adapter->vf_cfg[vf].vf_pmac_id, vf + 1);
ba343c77 746
64600ea5
AK		 747 status = be_cmd_pmac_add(adapter, mac,
748 adapter->vf_cfg[vf].vf_if_handle,
f8617e08 749 &adapter->vf_cfg[vf].vf_pmac_id, vf + 1);
64600ea5
AK		 750
751 if (status)
ba343c77
SB		 752 dev_err(&adapter->pdev->dev, "MAC %pM set on VF %d Failed\n",
753 mac, vf);
64600ea5
AK		 754 else
755 memcpy(adapter->vf_cfg[vf].vf_mac_addr, mac, ETH_ALEN);
756
ba343c77
SB		 757 return status;
758}
759
64600ea5
AK		 760static int be_get_vf_config(struct net_device *netdev, int vf,
761 struct ifla_vf_info *vi)
762{
763 struct be_adapter *adapter = netdev_priv(netdev);
764
765 if (!adapter->sriov_enabled)
766 return -EPERM;
767
768 if (vf >= num_vfs)
769 return -EINVAL;
770
771 vi->vf = vf;
e1d18735 772 vi->tx_rate = adapter->vf_cfg[vf].vf_tx_rate;
1da87b7f 773 vi->vlan = adapter->vf_cfg[vf].vf_vlan_tag;
64600ea5
AK		 774 vi->qos = 0;
775 memcpy(&vi->mac, adapter->vf_cfg[vf].vf_mac_addr, ETH_ALEN);
776
777 return 0;
778}
779
1da87b7f
AK		 780static int be_set_vf_vlan(struct net_device *netdev,
781 int vf, u16 vlan, u8 qos)
782{
783 struct be_adapter *adapter = netdev_priv(netdev);
784 int status = 0;
785
786 if (!adapter->sriov_enabled)
787 return -EPERM;
788
789 if ((vf >= num_vfs) || (vlan > 4095))
790 return -EINVAL;
791
792 if (vlan) {
793 adapter->vf_cfg[vf].vf_vlan_tag = vlan;
794 adapter->vlans_added++;
795 } else {
796 adapter->vf_cfg[vf].vf_vlan_tag = 0;
797 adapter->vlans_added--;
798 }
799
800 status = be_vid_config(adapter, true, vf);
801
802 if (status)
803 dev_info(&adapter->pdev->dev,
804 "VLAN %d config on VF %d failed\n", vlan, vf);
805 return status;
806}
807
e1d18735
AK		 808static int be_set_vf_tx_rate(struct net_device *netdev,
809 int vf, int rate)
810{
811 struct be_adapter *adapter = netdev_priv(netdev);
812 int status = 0;
813
814 if (!adapter->sriov_enabled)
815 return -EPERM;
816
817 if ((vf >= num_vfs) || (rate < 0))
818 return -EINVAL;
819
820 if (rate > 10000)
821 rate = 10000;
822
823 adapter->vf_cfg[vf].vf_tx_rate = rate;
856c4012 824 status = be_cmd_set_qos(adapter, rate / 10, vf + 1);
e1d18735
AK		 825
826 if (status)
827 dev_info(&adapter->pdev->dev,
828 "tx rate %d on VF %d failed\n", rate, vf);
829 return status;
830}
831
3abcdeda 832static void be_rx_rate_update(struct be_rx_obj *rxo)
6b7c5b94 833{
3abcdeda 834 struct be_rx_stats *stats = &rxo->stats;
4097f663 835 ulong now = jiffies;
6b7c5b94 836
4097f663 837 /* Wrapped around */
3abcdeda
SP		 838 if (time_before(now, stats->rx_jiffies)) {
839 stats->rx_jiffies = now;
4097f663
SP		 840 return;
841 }
6b7c5b94
SP		 842
843 /* Update the rate once in two seconds */
3abcdeda 844 if ((now - stats->rx_jiffies) < 2 * HZ)
6b7c5b94
SP		 845 return;
846
3abcdeda
SP		 847 stats->rx_rate = be_calc_rate(stats->rx_bytes - stats->rx_bytes_prev,
848 now - stats->rx_jiffies);
849 stats->rx_jiffies = now;
850 stats->rx_bytes_prev = stats->rx_bytes;
6b7c5b94
SP		 851}
852
3abcdeda 853static void be_rx_stats_update(struct be_rx_obj *rxo,
1ef78abe 854 u32 pktsize, u16 numfrags, u8 pkt_type)
4097f663 855{
3abcdeda 856 struct be_rx_stats *stats = &rxo->stats;
1ef78abe 857
3abcdeda
SP		 858 stats->rx_compl++;
859 stats->rx_frags += numfrags;
860 stats->rx_bytes += pktsize;
861 stats->rx_pkts++;
1ef78abe 862 if (pkt_type == BE_MULTICAST_PACKET)
3abcdeda 863 stats->rx_mcast_pkts++;
4097f663
SP		 864}
865
c6ce2f4b 866static inline bool csum_passed(struct be_eth_rx_compl *rxcp)
728a9972 867{
c6ce2f4b 868 u8 l4_cksm, ipv6, ipcksm;
728a9972
AK		 869
870 l4_cksm = AMAP_GET_BITS(struct amap_eth_rx_compl, l4_cksm, rxcp);
871 ipcksm = AMAP_GET_BITS(struct amap_eth_rx_compl, ipcksm, rxcp);
c6ce2f4b 872 ipv6 = AMAP_GET_BITS(struct amap_eth_rx_compl, ip_version, rxcp);
728a9972 873
c6ce2f4b
SK		 874 /* Ignore ipcksm for ipv6 pkts */
875 return l4_cksm && (ipcksm || ipv6);
728a9972
AK		 876}
877
6b7c5b94 878static struct be_rx_page_info *
3abcdeda
SP		 879get_rx_page_info(struct be_adapter *adapter,
880 struct be_rx_obj *rxo,
881 u16 frag_idx)
6b7c5b94
SP		 882{
883 struct be_rx_page_info *rx_page_info;
3abcdeda 884 struct be_queue_info *rxq = &rxo->q;
6b7c5b94 885
3abcdeda 886 rx_page_info = &rxo->page_info_tbl[frag_idx];
6b7c5b94
SP		 887 BUG_ON(!rx_page_info->page);
888
205859a2 889 if (rx_page_info->last_page_user) {
2b7bcebf
IV		 890 dma_unmap_page(&adapter->pdev->dev,
891 dma_unmap_addr(rx_page_info, bus),
892 adapter->big_page_size, DMA_FROM_DEVICE);
205859a2
AK		 893 rx_page_info->last_page_user = false;
894 }
6b7c5b94
SP		 895
896 atomic_dec(&rxq->used);
897 return rx_page_info;
898}
899
900/* Throwaway the data in the Rx completion */
901static void be_rx_compl_discard(struct be_adapter *adapter,
3abcdeda
SP		 902 struct be_rx_obj *rxo,
903 struct be_eth_rx_compl *rxcp)
6b7c5b94 904{
3abcdeda 905 struct be_queue_info *rxq = &rxo->q;
6b7c5b94
SP		 906 struct be_rx_page_info *page_info;
907 u16 rxq_idx, i, num_rcvd;
908
909 rxq_idx = AMAP_GET_BITS(struct amap_eth_rx_compl, fragndx, rxcp);
910 num_rcvd = AMAP_GET_BITS(struct amap_eth_rx_compl, numfrags, rxcp);
911
64642811
SP		 912 /* Skip out-of-buffer compl(lancer) or flush compl(BE) */
913 if (likely(rxq_idx != rxo->last_frag_index && num_rcvd != 0)) {
914
915 rxo->last_frag_index = rxq_idx;
916
917 for (i = 0; i < num_rcvd; i++) {
918 page_info = get_rx_page_info(adapter, rxo, rxq_idx);
919 put_page(page_info->page);
920 memset(page_info, 0, sizeof(*page_info));
921 index_inc(&rxq_idx, rxq->len);
922 }
6b7c5b94
SP		 923 }
924}
925
926/*
927 * skb_fill_rx_data forms a complete skb for an ether frame
928 * indicated by rxcp.
929 */
3abcdeda 930static void skb_fill_rx_data(struct be_adapter *adapter, struct be_rx_obj *rxo,
89420424
SP		 931 struct sk_buff *skb, struct be_eth_rx_compl *rxcp,
932 u16 num_rcvd)
6b7c5b94 933{
3abcdeda 934 struct be_queue_info *rxq = &rxo->q;
6b7c5b94 935 struct be_rx_page_info *page_info;
89420424 936 u16 rxq_idx, i, j;
fa77406a 937 u32 pktsize, hdr_len, curr_frag_len, size;
6b7c5b94 938 u8 *start;
1ef78abe 939 u8 pkt_type;
6b7c5b94
SP		 940
941 rxq_idx = AMAP_GET_BITS(struct amap_eth_rx_compl, fragndx, rxcp);
942 pktsize = AMAP_GET_BITS(struct amap_eth_rx_compl, pktsize, rxcp);
1ef78abe 943 pkt_type = AMAP_GET_BITS(struct amap_eth_rx_compl, cast_enc, rxcp);
6b7c5b94 944
3abcdeda 945 page_info = get_rx_page_info(adapter, rxo, rxq_idx);
6b7c5b94
SP		 946
947 start = page_address(page_info->page) + page_info->page_offset;
948 prefetch(start);
949
950 /* Copy data in the first descriptor of this completion */
951 curr_frag_len = min(pktsize, rx_frag_size);
952
953 /* Copy the header portion into skb_data */
954 hdr_len = min((u32)BE_HDR_LEN, curr_frag_len);
955 memcpy(skb->data, start, hdr_len);
956 skb->len = curr_frag_len;
957 if (curr_frag_len <= BE_HDR_LEN) { /* tiny packet */
958 /* Complete packet has now been moved to data */
959 put_page(page_info->page);
960 skb->data_len = 0;
961 skb->tail += curr_frag_len;
962 } else {
963 skb_shinfo(skb)->nr_frags = 1;
964 skb_shinfo(skb)->frags[0].page = page_info->page;
965 skb_shinfo(skb)->frags[0].page_offset =
966 page_info->page_offset + hdr_len;
967 skb_shinfo(skb)->frags[0].size = curr_frag_len - hdr_len;
968 skb->data_len = curr_frag_len - hdr_len;
969 skb->tail += hdr_len;
970 }
205859a2 971 page_info->page = NULL;
6b7c5b94
SP		 972
973 if (pktsize <= rx_frag_size) {
974 BUG_ON(num_rcvd != 1);
76fbb429 975 goto done;
6b7c5b94
SP		 976 }
977
978 /* More frags present for this completion */
fa77406a 979 size = pktsize;
bd46cb6c 980 for (i = 1, j = 0; i < num_rcvd; i++) {
fa77406a 981 size -= curr_frag_len;
6b7c5b94 982 index_inc(&rxq_idx, rxq->len);
3abcdeda 983 page_info = get_rx_page_info(adapter, rxo, rxq_idx);
6b7c5b94 984
fa77406a 985 curr_frag_len = min(size, rx_frag_size);
6b7c5b94 986
bd46cb6c
AK		 987 /* Coalesce all frags from the same physical page in one slot */
988 if (page_info->page_offset == 0) {
989 /* Fresh page */
990 j++;
991 skb_shinfo(skb)->frags[j].page = page_info->page;
992 skb_shinfo(skb)->frags[j].page_offset =
993 page_info->page_offset;
994 skb_shinfo(skb)->frags[j].size = 0;
995 skb_shinfo(skb)->nr_frags++;
996 } else {
997 put_page(page_info->page);
998 }
999
1000 skb_shinfo(skb)->frags[j].size += curr_frag_len;
6b7c5b94
SP		 1001 skb->len += curr_frag_len;
1002 skb->data_len += curr_frag_len;
6b7c5b94 1003
205859a2 1004 page_info->page = NULL;
6b7c5b94 1005 }
bd46cb6c 1006 BUG_ON(j > MAX_SKB_FRAGS);
6b7c5b94 1007
76fbb429 1008done:
3abcdeda 1009 be_rx_stats_update(rxo, pktsize, num_rcvd, pkt_type);
6b7c5b94
SP		 1010}
1011
5be93b9a 1012/* Process the RX completion indicated by rxcp when GRO is disabled */
6b7c5b94 1013static void be_rx_compl_process(struct be_adapter *adapter,
3abcdeda 1014 struct be_rx_obj *rxo,
6b7c5b94
SP		 1015 struct be_eth_rx_compl *rxcp)
1016{
1017 struct sk_buff *skb;
dcb9b564 1018 u32 vlanf, vid;
89420424 1019 u16 num_rcvd;
dcb9b564 1020 u8 vtm;
6b7c5b94 1021
89420424 1022 num_rcvd = AMAP_GET_BITS(struct amap_eth_rx_compl, numfrags, rxcp);
89420424 1023
89d71a66 1024 skb = netdev_alloc_skb_ip_align(adapter->netdev, BE_HDR_LEN);
a058a632 1025 if (unlikely(!skb)) {
6b7c5b94
SP		 1026 if (net_ratelimit())
1027 dev_warn(&adapter->pdev->dev, "skb alloc failed\n");
3abcdeda 1028 be_rx_compl_discard(adapter, rxo, rxcp);
6b7c5b94
SP		 1029 return;
1030 }
1031
3abcdeda 1032 skb_fill_rx_data(adapter, rxo, skb, rxcp, num_rcvd);
6b7c5b94 1033
c6ce2f4b 1034 if (likely(adapter->rx_csum && csum_passed(rxcp)))
728a9972 1035 skb->ip_summed = CHECKSUM_UNNECESSARY;
c6ce2f4b
SK		 1036 else
1037 skb_checksum_none_assert(skb);
6b7c5b94
SP		 1038
1039 skb->truesize = skb->len + sizeof(struct sk_buff);
1040 skb->protocol = eth_type_trans(skb, adapter->netdev);
6b7c5b94 1041
a058a632
SP		 1042 vlanf = AMAP_GET_BITS(struct amap_eth_rx_compl, vtp, rxcp);
1043 vtm = AMAP_GET_BITS(struct amap_eth_rx_compl, vtm, rxcp);
1044
1045 /* vlanf could be wrongly set in some cards.
1046 * ignore if vtm is not set */
3486be29 1047 if ((adapter->function_mode & 0x400) && !vtm)
a058a632
SP		 1048 vlanf = 0;
1049
1050 if (unlikely(vlanf)) {
82903e4b 1051 if (!adapter->vlan_grp || adapter->vlans_added == 0) {
6b7c5b94
SP		 1052 kfree_skb(skb);
1053 return;
1054 }
1055 vid = AMAP_GET_BITS(struct amap_eth_rx_compl, vlan_tag, rxcp);
fe6d2a38
SP		 1056 if (!lancer_chip(adapter))
1057 vid = swab16(vid);
6b7c5b94
SP		 1058 vlan_hwaccel_receive_skb(skb, adapter->vlan_grp, vid);
1059 } else {
1060 netif_receive_skb(skb);
1061 }
6b7c5b94
SP		 1062}
1063
5be93b9a
AK		 1064/* Process the RX completion indicated by rxcp when GRO is enabled */
1065static void be_rx_compl_process_gro(struct be_adapter *adapter,
3abcdeda
SP		 1066 struct be_rx_obj *rxo,
1067 struct be_eth_rx_compl *rxcp)
6b7c5b94
SP		 1068{
1069 struct be_rx_page_info *page_info;
5be93b9a 1070 struct sk_buff *skb = NULL;
3abcdeda
SP		 1071 struct be_queue_info *rxq = &rxo->q;
1072 struct be_eq_obj *eq_obj = &rxo->rx_eq;
6b7c5b94 1073 u32 num_rcvd, pkt_size, remaining, vlanf, curr_frag_len;
bd46cb6c 1074 u16 i, rxq_idx = 0, vid, j;
dcb9b564 1075 u8 vtm;
1ef78abe 1076 u8 pkt_type;
6b7c5b94
SP		 1077
1078 num_rcvd = AMAP_GET_BITS(struct amap_eth_rx_compl, numfrags, rxcp);
1079 pkt_size = AMAP_GET_BITS(struct amap_eth_rx_compl, pktsize, rxcp);
1080 vlanf = AMAP_GET_BITS(struct amap_eth_rx_compl, vtp, rxcp);
1081 rxq_idx = AMAP_GET_BITS(struct amap_eth_rx_compl, fragndx, rxcp);
dcb9b564 1082 vtm = AMAP_GET_BITS(struct amap_eth_rx_compl, vtm, rxcp);
1ef78abe 1083 pkt_type = AMAP_GET_BITS(struct amap_eth_rx_compl, cast_enc, rxcp);
dcb9b564
AK		 1084
1085 /* vlanf could be wrongly set in some cards.
1086 * ignore if vtm is not set */
3486be29 1087 if ((adapter->function_mode & 0x400) && !vtm)
dcb9b564 1088 vlanf = 0;
6b7c5b94 1089
5be93b9a
AK		 1090 skb = napi_get_frags(&eq_obj->napi);
1091 if (!skb) {
3abcdeda 1092 be_rx_compl_discard(adapter, rxo, rxcp);
5be93b9a
AK		 1093 return;
1094 }
1095
6b7c5b94 1096 remaining = pkt_size;
bd46cb6c 1097 for (i = 0, j = -1; i < num_rcvd; i++) {
3abcdeda 1098 page_info = get_rx_page_info(adapter, rxo, rxq_idx);
6b7c5b94
SP		 1099
1100 curr_frag_len = min(remaining, rx_frag_size);
1101
bd46cb6c
AK		 1102 /* Coalesce all frags from the same physical page in one slot */
1103 if (i == 0 || page_info->page_offset == 0) {
1104 /* First frag or Fresh page */
1105 j++;
5be93b9a
AK		 1106 skb_shinfo(skb)->frags[j].page = page_info->page;
1107 skb_shinfo(skb)->frags[j].page_offset =
1108 page_info->page_offset;
1109 skb_shinfo(skb)->frags[j].size = 0;
bd46cb6c
AK		 1110 } else {
1111 put_page(page_info->page);
1112 }
5be93b9a 1113 skb_shinfo(skb)->frags[j].size += curr_frag_len;
6b7c5b94 1114
bd46cb6c 1115 remaining -= curr_frag_len;
6b7c5b94 1116 index_inc(&rxq_idx, rxq->len);
6b7c5b94
SP		 1117 memset(page_info, 0, sizeof(*page_info));
1118 }
bd46cb6c 1119 BUG_ON(j > MAX_SKB_FRAGS);
6b7c5b94 1120
5be93b9a
AK		 1121 skb_shinfo(skb)->nr_frags = j + 1;
1122 skb->len = pkt_size;
1123 skb->data_len = pkt_size;
1124 skb->truesize += pkt_size;
1125 skb->ip_summed = CHECKSUM_UNNECESSARY;
1126
6b7c5b94 1127 if (likely(!vlanf)) {
5be93b9a 1128 napi_gro_frags(&eq_obj->napi);
6b7c5b94
SP		 1129 } else {
1130 vid = AMAP_GET_BITS(struct amap_eth_rx_compl, vlan_tag, rxcp);
fe6d2a38
SP		 1131 if (!lancer_chip(adapter))
1132 vid = swab16(vid);
6b7c5b94 1133
82903e4b 1134 if (!adapter->vlan_grp || adapter->vlans_added == 0)
6b7c5b94
SP		 1135 return;
1136
5be93b9a 1137 vlan_gro_frags(&eq_obj->napi, adapter->vlan_grp, vid);
6b7c5b94
SP		 1138 }
1139
3abcdeda 1140 be_rx_stats_update(rxo, pkt_size, num_rcvd, pkt_type);
6b7c5b94
SP		 1141}
1142
3abcdeda 1143static struct be_eth_rx_compl *be_rx_compl_get(struct be_rx_obj *rxo)
6b7c5b94 1144{
3abcdeda 1145 struct be_eth_rx_compl *rxcp = queue_tail_node(&rxo->cq);
6b7c5b94
SP		 1146
1147 if (rxcp->dw[offsetof(struct amap_eth_rx_compl, valid) / 32] == 0)
1148 return NULL;
1149
f3eb62d2 1150 rmb();
6b7c5b94
SP		 1151 be_dws_le_to_cpu(rxcp, sizeof(*rxcp));
1152
3abcdeda 1153 queue_tail_inc(&rxo->cq);
6b7c5b94
SP		 1154 return rxcp;
1155}
1156
a7a0ef31
SP		 1157/* To reset the valid bit, we need to reset the whole word as
1158 * when walking the queue the valid entries are little-endian
1159 * and invalid entries are host endian
1160 */
1161static inline void be_rx_compl_reset(struct be_eth_rx_compl *rxcp)
1162{
1163 rxcp->dw[offsetof(struct amap_eth_rx_compl, valid) / 32] = 0;
1164}
1165
6b7c5b94
SP		 1166static inline struct page *be_alloc_pages(u32 size)
1167{
1168 gfp_t alloc_flags = GFP_ATOMIC;
1169 u32 order = get_order(size);
1170 if (order > 0)
1171 alloc_flags |= __GFP_COMP;
1172 return alloc_pages(alloc_flags, order);
1173}
1174
1175/*
1176 * Allocate a page, split it to fragments of size rx_frag_size and post as
1177 * receive buffers to BE
1178 */
3abcdeda 1179static void be_post_rx_frags(struct be_rx_obj *rxo)
6b7c5b94 1180{
3abcdeda
SP		 1181 struct be_adapter *adapter = rxo->adapter;
1182 struct be_rx_page_info *page_info_tbl = rxo->page_info_tbl;
26d92f92 1183 struct be_rx_page_info *page_info = NULL, *prev_page_info = NULL;
3abcdeda 1184 struct be_queue_info *rxq = &rxo->q;
6b7c5b94
SP		 1185 struct page *pagep = NULL;
1186 struct be_eth_rx_d *rxd;
1187 u64 page_dmaaddr = 0, frag_dmaaddr;
1188 u32 posted, page_offset = 0;
1189
3abcdeda 1190 page_info = &rxo->page_info_tbl[rxq->head];
6b7c5b94
SP		 1191 for (posted = 0; posted < MAX_RX_POST && !page_info->page; posted++) {
1192 if (!pagep) {
1193 pagep = be_alloc_pages(adapter->big_page_size);
1194 if (unlikely(!pagep)) {
3abcdeda 1195 rxo->stats.rx_post_fail++;
6b7c5b94
SP		 1196 break;
1197 }
2b7bcebf
IV		 1198 page_dmaaddr = dma_map_page(&adapter->pdev->dev, pagep,
1199 0, adapter->big_page_size,
1200 DMA_FROM_DEVICE);
6b7c5b94
SP		 1201 page_info->page_offset = 0;
1202 } else {
1203 get_page(pagep);
1204 page_info->page_offset = page_offset + rx_frag_size;
1205 }
1206 page_offset = page_info->page_offset;
1207 page_info->page = pagep;
fac6da5b 1208 dma_unmap_addr_set(page_info, bus, page_dmaaddr);
6b7c5b94
SP		 1209 frag_dmaaddr = page_dmaaddr + page_info->page_offset;
1210
1211 rxd = queue_head_node(rxq);
1212 rxd->fragpa_lo = cpu_to_le32(frag_dmaaddr & 0xFFFFFFFF);
1213 rxd->fragpa_hi = cpu_to_le32(upper_32_bits(frag_dmaaddr));
6b7c5b94
SP		 1214
1215 /* Any space left in the current big page for another frag? */
1216 if ((page_offset + rx_frag_size + rx_frag_size) >
1217 adapter->big_page_size) {
1218 pagep = NULL;
1219 page_info->last_page_user = true;
1220 }
26d92f92
SP		 1221
1222 prev_page_info = page_info;
1223 queue_head_inc(rxq);
6b7c5b94
SP		 1224 page_info = &page_info_tbl[rxq->head];
1225 }
1226 if (pagep)
26d92f92 1227 prev_page_info->last_page_user = true;
6b7c5b94
SP		 1228
1229 if (posted) {
6b7c5b94 1230 atomic_add(posted, &rxq->used);
8788fdc2 1231 be_rxq_notify(adapter, rxq->id, posted);
ea1dae11
SP		 1232 } else if (atomic_read(&rxq->used) == 0) {
1233 /* Let be_worker replenish when memory is available */
3abcdeda 1234 rxo->rx_post_starved = true;
6b7c5b94 1235 }
6b7c5b94
SP		 1236}
1237
5fb379ee 1238static struct be_eth_tx_compl *be_tx_compl_get(struct be_queue_info *tx_cq)
6b7c5b94 1239{
6b7c5b94
SP		 1240 struct be_eth_tx_compl *txcp = queue_tail_node(tx_cq);
1241
1242 if (txcp->dw[offsetof(struct amap_eth_tx_compl, valid) / 32] == 0)
1243 return NULL;
1244
f3eb62d2 1245 rmb();
6b7c5b94
SP		 1246 be_dws_le_to_cpu(txcp, sizeof(*txcp));
1247
1248 txcp->dw[offsetof(struct amap_eth_tx_compl, valid) / 32] = 0;
1249
1250 queue_tail_inc(tx_cq);
1251 return txcp;
1252}
1253
1254static void be_tx_compl_process(struct be_adapter *adapter, u16 last_index)
1255{
1256 struct be_queue_info *txq = &adapter->tx_obj.q;
a73b796e 1257 struct be_eth_wrb *wrb;
6b7c5b94
SP		 1258 struct sk_buff **sent_skbs = adapter->tx_obj.sent_skb_list;
1259 struct sk_buff *sent_skb;
ec43b1a6
SP		 1260 u16 cur_index, num_wrbs = 1; /* account for hdr wrb */
1261 bool unmap_skb_hdr = true;
6b7c5b94 1262
ec43b1a6 1263 sent_skb = sent_skbs[txq->tail];
6b7c5b94 1264 BUG_ON(!sent_skb);
ec43b1a6
SP		 1265 sent_skbs[txq->tail] = NULL;
1266
1267 /* skip header wrb */
a73b796e 1268 queue_tail_inc(txq);
6b7c5b94 1269
ec43b1a6 1270 do {
6b7c5b94 1271 cur_index = txq->tail;
a73b796e 1272 wrb = queue_tail_node(txq);
2b7bcebf
IV		 1273 unmap_tx_frag(&adapter->pdev->dev, wrb,
1274 (unmap_skb_hdr && skb_headlen(sent_skb)));
ec43b1a6
SP		 1275 unmap_skb_hdr = false;
1276
6b7c5b94
SP		 1277 num_wrbs++;
1278 queue_tail_inc(txq);
ec43b1a6 1279 } while (cur_index != last_index);
6b7c5b94
SP		 1280
1281 atomic_sub(num_wrbs, &txq->used);
a73b796e 1282
6b7c5b94
SP		 1283 kfree_skb(sent_skb);
1284}
1285
859b1e4e
SP		 1286static inline struct be_eq_entry *event_get(struct be_eq_obj *eq_obj)
1287{
1288 struct be_eq_entry *eqe = queue_tail_node(&eq_obj->q);
1289
1290 if (!eqe->evt)
1291 return NULL;
1292
f3eb62d2 1293 rmb();
859b1e4e
SP		 1294 eqe->evt = le32_to_cpu(eqe->evt);
1295 queue_tail_inc(&eq_obj->q);
1296 return eqe;
1297}
1298
1299static int event_handle(struct be_adapter *adapter,
1300 struct be_eq_obj *eq_obj)
1301{
1302 struct be_eq_entry *eqe;
1303 u16 num = 0;
1304
1305 while ((eqe = event_get(eq_obj)) != NULL) {
1306 eqe->evt = 0;
1307 num++;
1308 }
1309
1310 /* Deal with any spurious interrupts that come
1311 * without events
1312 */
1313 be_eq_notify(adapter, eq_obj->q.id, true, true, num);
1314 if (num)
1315 napi_schedule(&eq_obj->napi);
1316
1317 return num;
1318}
1319
1320/* Just read and notify events without processing them.
1321 * Used at the time of destroying event queues */
1322static void be_eq_clean(struct be_adapter *adapter,
1323 struct be_eq_obj *eq_obj)
1324{
1325 struct be_eq_entry *eqe;
1326 u16 num = 0;
1327
1328 while ((eqe = event_get(eq_obj)) != NULL) {
1329 eqe->evt = 0;
1330 num++;
1331 }
1332
1333 if (num)
1334 be_eq_notify(adapter, eq_obj->q.id, false, true, num);
1335}
1336
3abcdeda 1337static void be_rx_q_clean(struct be_adapter *adapter, struct be_rx_obj *rxo)
6b7c5b94
SP		 1338{
1339 struct be_rx_page_info *page_info;
3abcdeda
SP		 1340 struct be_queue_info *rxq = &rxo->q;
1341 struct be_queue_info *rx_cq = &rxo->cq;
6b7c5b94
SP		 1342 struct be_eth_rx_compl *rxcp;
1343 u16 tail;
1344
1345 /* First cleanup pending rx completions */
3abcdeda
SP		 1346 while ((rxcp = be_rx_compl_get(rxo)) != NULL) {
1347 be_rx_compl_discard(adapter, rxo, rxcp);
a7a0ef31 1348 be_rx_compl_reset(rxcp);
64642811 1349 be_cq_notify(adapter, rx_cq->id, false, 1);
6b7c5b94
SP		 1350 }
1351
1352 /* Then free posted rx buffer that were not used */
1353 tail = (rxq->head + rxq->len - atomic_read(&rxq->used)) % rxq->len;
cdab23b7 1354 for (; atomic_read(&rxq->used) > 0; index_inc(&tail, rxq->len)) {
3abcdeda 1355 page_info = get_rx_page_info(adapter, rxo, tail);
6b7c5b94
SP		 1356 put_page(page_info->page);
1357 memset(page_info, 0, sizeof(*page_info));
1358 }
1359 BUG_ON(atomic_read(&rxq->used));
1360}
1361
a8e9179a 1362static void be_tx_compl_clean(struct be_adapter *adapter)
6b7c5b94 1363{
a8e9179a 1364 struct be_queue_info *tx_cq = &adapter->tx_obj.cq;
6b7c5b94 1365 struct be_queue_info *txq = &adapter->tx_obj.q;
a8e9179a
SP		 1366 struct be_eth_tx_compl *txcp;
1367 u16 end_idx, cmpl = 0, timeo = 0;
b03388d6
SP		 1368 struct sk_buff **sent_skbs = adapter->tx_obj.sent_skb_list;
1369 struct sk_buff *sent_skb;
1370 bool dummy_wrb;
a8e9179a
SP		 1371
1372 /* Wait for a max of 200ms for all the tx-completions to arrive. */
1373 do {
1374 while ((txcp = be_tx_compl_get(tx_cq))) {
1375 end_idx = AMAP_GET_BITS(struct amap_eth_tx_compl,
1376 wrb_index, txcp);
1377 be_tx_compl_process(adapter, end_idx);
1378 cmpl++;
1379 }
1380 if (cmpl) {
1381 be_cq_notify(adapter, tx_cq->id, false, cmpl);
1382 cmpl = 0;
1383 }
1384
1385 if (atomic_read(&txq->used) == 0 || ++timeo > 200)
1386 break;
1387
1388 mdelay(1);
1389 } while (true);
1390
1391 if (atomic_read(&txq->used))
1392 dev_err(&adapter->pdev->dev, "%d pending tx-completions\n",
1393 atomic_read(&txq->used));
b03388d6
SP		 1394
1395 /* free posted tx for which compls will never arrive */
1396 while (atomic_read(&txq->used)) {
1397 sent_skb = sent_skbs[txq->tail];
1398 end_idx = txq->tail;
1399 index_adv(&end_idx,
fe6d2a38
SP		 1400 wrb_cnt_for_skb(adapter, sent_skb, &dummy_wrb) - 1,
1401 txq->len);
b03388d6
SP		 1402 be_tx_compl_process(adapter, end_idx);
1403 }
6b7c5b94
SP		 1404}
1405
5fb379ee
SP		 1406static void be_mcc_queues_destroy(struct be_adapter *adapter)
1407{
1408 struct be_queue_info *q;
5fb379ee 1409
8788fdc2 1410 q = &adapter->mcc_obj.q;
5fb379ee 1411 if (q->created)
8788fdc2 1412 be_cmd_q_destroy(adapter, q, QTYPE_MCCQ);
5fb379ee
SP		 1413 be_queue_free(adapter, q);
1414
8788fdc2 1415 q = &adapter->mcc_obj.cq;
5fb379ee 1416 if (q->created)
8788fdc2 1417 be_cmd_q_destroy(adapter, q, QTYPE_CQ);
5fb379ee
SP		 1418 be_queue_free(adapter, q);
1419}
1420
1421/* Must be called only after TX qs are created as MCC shares TX EQ */
1422static int be_mcc_queues_create(struct be_adapter *adapter)
1423{
1424 struct be_queue_info *q, *cq;
5fb379ee
SP		 1425
1426 /* Alloc MCC compl queue */
8788fdc2 1427 cq = &adapter->mcc_obj.cq;
5fb379ee 1428 if (be_queue_alloc(adapter, cq, MCC_CQ_LEN,
efd2e40a 1429 sizeof(struct be_mcc_compl)))
5fb379ee
SP		 1430 goto err;
1431
1432 /* Ask BE to create MCC compl queue; share TX's eq */
8788fdc2 1433 if (be_cmd_cq_create(adapter, cq, &adapter->tx_eq.q, false, true, 0))
5fb379ee
SP		 1434 goto mcc_cq_free;
1435
1436 /* Alloc MCC queue */
8788fdc2 1437 q = &adapter->mcc_obj.q;
5fb379ee
SP		 1438 if (be_queue_alloc(adapter, q, MCC_Q_LEN, sizeof(struct be_mcc_wrb)))
1439 goto mcc_cq_destroy;
1440
1441 /* Ask BE to create MCC queue */
8788fdc2 1442 if (be_cmd_mccq_create(adapter, q, cq))
5fb379ee
SP		 1443 goto mcc_q_free;
1444
1445 return 0;
1446
1447mcc_q_free:
1448 be_queue_free(adapter, q);
1449mcc_cq_destroy:
8788fdc2 1450 be_cmd_q_destroy(adapter, cq, QTYPE_CQ);
5fb379ee
SP		 1451mcc_cq_free:
1452 be_queue_free(adapter, cq);
1453err:
1454 return -1;
1455}
1456
6b7c5b94
SP		 1457static void be_tx_queues_destroy(struct be_adapter *adapter)
1458{
1459 struct be_queue_info *q;
1460
1461 q = &adapter->tx_obj.q;
a8e9179a 1462 if (q->created)
8788fdc2 1463 be_cmd_q_destroy(adapter, q, QTYPE_TXQ);
6b7c5b94
SP		 1464 be_queue_free(adapter, q);
1465
1466 q = &adapter->tx_obj.cq;
1467 if (q->created)
8788fdc2 1468 be_cmd_q_destroy(adapter, q, QTYPE_CQ);
6b7c5b94
SP		 1469 be_queue_free(adapter, q);
1470
859b1e4e
SP		 1471 /* Clear any residual events */
1472 be_eq_clean(adapter, &adapter->tx_eq);
1473
6b7c5b94
SP		 1474 q = &adapter->tx_eq.q;
1475 if (q->created)
8788fdc2 1476 be_cmd_q_destroy(adapter, q, QTYPE_EQ);
6b7c5b94
SP		 1477 be_queue_free(adapter, q);
1478}
1479
1480static int be_tx_queues_create(struct be_adapter *adapter)
1481{
1482 struct be_queue_info *eq, *q, *cq;
1483
1484 adapter->tx_eq.max_eqd = 0;
1485 adapter->tx_eq.min_eqd = 0;
1486 adapter->tx_eq.cur_eqd = 96;
1487 adapter->tx_eq.enable_aic = false;
1488 /* Alloc Tx Event queue */
1489 eq = &adapter->tx_eq.q;
1490 if (be_queue_alloc(adapter, eq, EVNT_Q_LEN, sizeof(struct be_eq_entry)))
1491 return -1;
1492
1493 /* Ask BE to create Tx Event queue */
8788fdc2 1494 if (be_cmd_eq_create(adapter, eq, adapter->tx_eq.cur_eqd))
6b7c5b94 1495 goto tx_eq_free;
fe6d2a38
SP		 1496
1497 adapter->tx_eq.msix_vec_idx = adapter->msix_vec_next_idx++;
1498
ba343c77 1499
6b7c5b94
SP		 1500 /* Alloc TX eth compl queue */
1501 cq = &adapter->tx_obj.cq;
1502 if (be_queue_alloc(adapter, cq, TX_CQ_LEN,
1503 sizeof(struct be_eth_tx_compl)))
1504 goto tx_eq_destroy;
1505
1506 /* Ask BE to create Tx eth compl queue */
8788fdc2 1507 if (be_cmd_cq_create(adapter, cq, eq, false, false, 3))
6b7c5b94
SP		 1508 goto tx_cq_free;
1509
1510 /* Alloc TX eth queue */
1511 q = &adapter->tx_obj.q;
1512 if (be_queue_alloc(adapter, q, TX_Q_LEN, sizeof(struct be_eth_wrb)))
1513 goto tx_cq_destroy;
1514
1515 /* Ask BE to create Tx eth queue */
8788fdc2 1516 if (be_cmd_txq_create(adapter, q, cq))
6b7c5b94
SP		 1517 goto tx_q_free;
1518 return 0;
1519
1520tx_q_free:
1521 be_queue_free(adapter, q);
1522tx_cq_destroy:
8788fdc2 1523 be_cmd_q_destroy(adapter, cq, QTYPE_CQ);
6b7c5b94
SP		 1524tx_cq_free:
1525 be_queue_free(adapter, cq);
1526tx_eq_destroy:
8788fdc2 1527 be_cmd_q_destroy(adapter, eq, QTYPE_EQ);
6b7c5b94
SP		 1528tx_eq_free:
1529 be_queue_free(adapter, eq);
1530 return -1;
1531}
1532
1533static void be_rx_queues_destroy(struct be_adapter *adapter)
1534{
1535 struct be_queue_info *q;
3abcdeda
SP		 1536 struct be_rx_obj *rxo;
1537 int i;
1538
1539 for_all_rx_queues(adapter, rxo, i) {
1540 q = &rxo->q;
1541 if (q->created) {
1542 be_cmd_q_destroy(adapter, q, QTYPE_RXQ);
1543 /* After the rxq is invalidated, wait for a grace time
1544 * of 1ms for all dma to end and the flush compl to
1545 * arrive
1546 */
1547 mdelay(1);
1548 be_rx_q_clean(adapter, rxo);
1549 }
1550 be_queue_free(adapter, q);
1551
1552 q = &rxo->cq;
1553 if (q->created)
1554 be_cmd_q_destroy(adapter, q, QTYPE_CQ);
1555 be_queue_free(adapter, q);
1556
1557 /* Clear any residual events */
1558 q = &rxo->rx_eq.q;
1559 if (q->created) {
1560 be_eq_clean(adapter, &rxo->rx_eq);
1561 be_cmd_q_destroy(adapter, q, QTYPE_EQ);
1562 }
1563 be_queue_free(adapter, q);
6b7c5b94 1564 }
6b7c5b94
SP		 1565}
1566
1567static int be_rx_queues_create(struct be_adapter *adapter)
1568{
1569 struct be_queue_info *eq, *q, *cq;
3abcdeda
SP		 1570 struct be_rx_obj *rxo;
1571 int rc, i;
6b7c5b94 1572
6b7c5b94 1573 adapter->big_page_size = (1 << get_order(rx_frag_size)) * PAGE_SIZE;
3abcdeda
SP		 1574 for_all_rx_queues(adapter, rxo, i) {
1575 rxo->adapter = adapter;
64642811
SP		 1576 /* Init last_frag_index so that the frag index in the first
1577 * completion will never match */
1578 rxo->last_frag_index = 0xffff;
3abcdeda
SP		 1579 rxo->rx_eq.max_eqd = BE_MAX_EQD;
1580 rxo->rx_eq.enable_aic = true;
1581
1582 /* EQ */
1583 eq = &rxo->rx_eq.q;
1584 rc = be_queue_alloc(adapter, eq, EVNT_Q_LEN,
1585 sizeof(struct be_eq_entry));
1586 if (rc)
1587 goto err;
1588
1589 rc = be_cmd_eq_create(adapter, eq, rxo->rx_eq.cur_eqd);
1590 if (rc)
1591 goto err;
1592
fe6d2a38
SP		 1593 rxo->rx_eq.msix_vec_idx = adapter->msix_vec_next_idx++;
1594
3abcdeda
SP		 1595 /* CQ */
1596 cq = &rxo->cq;
1597 rc = be_queue_alloc(adapter, cq, RX_CQ_LEN,
1598 sizeof(struct be_eth_rx_compl));
1599 if (rc)
1600 goto err;
1601
1602 rc = be_cmd_cq_create(adapter, cq, eq, false, false, 3);
1603 if (rc)
1604 goto err;
3abcdeda
SP		 1605 /* Rx Q */
1606 q = &rxo->q;
1607 rc = be_queue_alloc(adapter, q, RX_Q_LEN,
1608 sizeof(struct be_eth_rx_d));
1609 if (rc)
1610 goto err;
1611
1612 rc = be_cmd_rxq_create(adapter, q, cq->id, rx_frag_size,
1613 BE_MAX_JUMBO_FRAME_SIZE, adapter->if_handle,
1614 (i > 0) ? 1 : 0/* rss enable */, &rxo->rss_id);
1615 if (rc)
1616 goto err;
1617 }
1618
1619 if (be_multi_rxq(adapter)) {
1620 u8 rsstable[MAX_RSS_QS];
1621
1622 for_all_rss_queues(adapter, rxo, i)
1623 rsstable[i] = rxo->rss_id;
1624
1625 rc = be_cmd_rss_config(adapter, rsstable,
1626 adapter->num_rx_qs - 1);
1627 if (rc)
1628 goto err;
1629 }
6b7c5b94
SP		 1630
1631 return 0;
3abcdeda
SP		 1632err:
1633 be_rx_queues_destroy(adapter);
1634 return -1;
6b7c5b94 1635}
6b7c5b94 1636
fe6d2a38 1637static bool event_peek(struct be_eq_obj *eq_obj)
b628bde2 1638{
fe6d2a38
SP		 1639 struct be_eq_entry *eqe = queue_tail_node(&eq_obj->q);
1640 if (!eqe->evt)
1641 return false;
1642 else
1643 return true;
b628bde2
SP		 1644}
1645
6b7c5b94
SP		 1646static irqreturn_t be_intx(int irq, void *dev)
1647{
1648 struct be_adapter *adapter = dev;
3abcdeda 1649 struct be_rx_obj *rxo;
fe6d2a38 1650 int isr, i, tx = 0 , rx = 0;
6b7c5b94 1651
fe6d2a38
SP		 1652 if (lancer_chip(adapter)) {
1653 if (event_peek(&adapter->tx_eq))
1654 tx = event_handle(adapter, &adapter->tx_eq);
1655 for_all_rx_queues(adapter, rxo, i) {
1656 if (event_peek(&rxo->rx_eq))
1657 rx |= event_handle(adapter, &rxo->rx_eq);
1658 }
6b7c5b94 1659
fe6d2a38
SP		 1660 if (!(tx || rx))
1661 return IRQ_NONE;
3abcdeda 1662
fe6d2a38
SP		 1663 } else {
1664 isr = ioread32(adapter->csr + CEV_ISR0_OFFSET +
1665 (adapter->tx_eq.q.id / 8) * CEV_ISR_SIZE);
1666 if (!isr)
1667 return IRQ_NONE;
1668
1669 if ((1 << adapter->tx_eq.msix_vec_idx & isr))
1670 event_handle(adapter, &adapter->tx_eq);
1671
1672 for_all_rx_queues(adapter, rxo, i) {
1673 if ((1 << rxo->rx_eq.msix_vec_idx & isr))
1674 event_handle(adapter, &rxo->rx_eq);
1675 }
3abcdeda 1676 }
c001c213 1677
8788fdc2 1678 return IRQ_HANDLED;
6b7c5b94
SP		 1679}
1680
1681static irqreturn_t be_msix_rx(int irq, void *dev)
1682{
3abcdeda
SP		 1683 struct be_rx_obj *rxo = dev;
1684 struct be_adapter *adapter = rxo->adapter;
6b7c5b94 1685
3abcdeda 1686 event_handle(adapter, &rxo->rx_eq);
6b7c5b94
SP		 1687
1688 return IRQ_HANDLED;
1689}
1690
5fb379ee 1691static irqreturn_t be_msix_tx_mcc(int irq, void *dev)
6b7c5b94
SP		 1692{
1693 struct be_adapter *adapter = dev;
1694
8788fdc2 1695 event_handle(adapter, &adapter->tx_eq);
6b7c5b94
SP		 1696
1697 return IRQ_HANDLED;
1698}
1699
64642811
SP		 1700static inline bool do_gro(struct be_rx_obj *rxo,
1701 struct be_eth_rx_compl *rxcp, u8 err)
6b7c5b94 1702{
6b7c5b94
SP		 1703 int tcp_frame = AMAP_GET_BITS(struct amap_eth_rx_compl, tcpf, rxcp);
1704
1705 if (err)
3abcdeda 1706 rxo->stats.rxcp_err++;
6b7c5b94 1707
5be93b9a 1708 return (tcp_frame && !err) ? true : false;
6b7c5b94
SP		 1709}
1710
49b05221 1711static int be_poll_rx(struct napi_struct *napi, int budget)
6b7c5b94
SP		 1712{
1713 struct be_eq_obj *rx_eq = container_of(napi, struct be_eq_obj, napi);
3abcdeda
SP		 1714 struct be_rx_obj *rxo = container_of(rx_eq, struct be_rx_obj, rx_eq);
1715 struct be_adapter *adapter = rxo->adapter;
1716 struct be_queue_info *rx_cq = &rxo->cq;
6b7c5b94
SP		 1717 struct be_eth_rx_compl *rxcp;
1718 u32 work_done;
64642811
SP		 1719 u16 frag_index, num_rcvd;
1720 u8 err;
6b7c5b94 1721
3abcdeda 1722 rxo->stats.rx_polls++;
6b7c5b94 1723 for (work_done = 0; work_done < budget; work_done++) {
3abcdeda 1724 rxcp = be_rx_compl_get(rxo);
6b7c5b94
SP		 1725 if (!rxcp)
1726 break;
1727
64642811
SP		 1728 err = AMAP_GET_BITS(struct amap_eth_rx_compl, err, rxcp);
1729 frag_index = AMAP_GET_BITS(struct amap_eth_rx_compl, fragndx,
1730 rxcp);
1731 num_rcvd = AMAP_GET_BITS(struct amap_eth_rx_compl, numfrags,
1732 rxcp);
1733
1734 /* Skip out-of-buffer compl(lancer) or flush compl(BE) */
1735 if (likely(frag_index != rxo->last_frag_index &&
1736 num_rcvd != 0)) {
1737 rxo->last_frag_index = frag_index;
1738
1739 if (do_gro(rxo, rxcp, err))
1740 be_rx_compl_process_gro(adapter, rxo, rxcp);
1741 else
1742 be_rx_compl_process(adapter, rxo, rxcp);
1743 }
a7a0ef31
SP		 1744
1745 be_rx_compl_reset(rxcp);
6b7c5b94
SP		 1746 }
1747
6b7c5b94 1748 /* Refill the queue */
3abcdeda
SP		 1749 if (atomic_read(&rxo->q.used) < RX_FRAGS_REFILL_WM)
1750 be_post_rx_frags(rxo);
6b7c5b94
SP		 1751
1752 /* All consumed */
1753 if (work_done < budget) {
1754 napi_complete(napi);
8788fdc2 1755 be_cq_notify(adapter, rx_cq->id, true, work_done);
6b7c5b94
SP		 1756 } else {
1757 /* More to be consumed; continue with interrupts disabled */
8788fdc2 1758 be_cq_notify(adapter, rx_cq->id, false, work_done);
6b7c5b94
SP		 1759 }
1760 return work_done;
1761}
1762
f31e50a8
SP		 1763/* As TX and MCC share the same EQ check for both TX and MCC completions.
1764 * For TX/MCC we don't honour budget; consume everything
1765 */
1766static int be_poll_tx_mcc(struct napi_struct *napi, int budget)
6b7c5b94 1767{
f31e50a8
SP		 1768 struct be_eq_obj *tx_eq = container_of(napi, struct be_eq_obj, napi);
1769 struct be_adapter *adapter =
1770 container_of(tx_eq, struct be_adapter, tx_eq);
5fb379ee
SP		 1771 struct be_queue_info *txq = &adapter->tx_obj.q;
1772 struct be_queue_info *tx_cq = &adapter->tx_obj.cq;
6b7c5b94 1773 struct be_eth_tx_compl *txcp;
f31e50a8 1774 int tx_compl = 0, mcc_compl, status = 0;
6b7c5b94
SP		 1775 u16 end_idx;
1776
5fb379ee 1777 while ((txcp = be_tx_compl_get(tx_cq))) {
6b7c5b94 1778 end_idx = AMAP_GET_BITS(struct amap_eth_tx_compl,
f31e50a8 1779 wrb_index, txcp);
6b7c5b94 1780 be_tx_compl_process(adapter, end_idx);
f31e50a8 1781 tx_compl++;
6b7c5b94
SP		 1782 }
1783
f31e50a8
SP		 1784 mcc_compl = be_process_mcc(adapter, &status);
1785
1786 napi_complete(napi);
1787
1788 if (mcc_compl) {
1789 struct be_mcc_obj *mcc_obj = &adapter->mcc_obj;
1790 be_cq_notify(adapter, mcc_obj->cq.id, true, mcc_compl);
1791 }
1792
1793 if (tx_compl) {
1794 be_cq_notify(adapter, adapter->tx_obj.cq.id, true, tx_compl);
5fb379ee
SP		 1795
1796 /* As Tx wrbs have been freed up, wake up netdev queue if
1797 * it was stopped due to lack of tx wrbs.
1798 */
1799 if (netif_queue_stopped(adapter->netdev) &&
6b7c5b94 1800 atomic_read(&txq->used) < txq->len / 2) {
5fb379ee
SP		 1801 netif_wake_queue(adapter->netdev);
1802 }
1803
3abcdeda
SP		 1804 tx_stats(adapter)->be_tx_events++;
1805 tx_stats(adapter)->be_tx_compl += tx_compl;
6b7c5b94 1806 }
6b7c5b94
SP		 1807
1808 return 1;
1809}
1810
d053de91 1811void be_detect_dump_ue(struct be_adapter *adapter)
7c185276
AK		 1812{
1813 u32 ue_status_lo, ue_status_hi, ue_status_lo_mask, ue_status_hi_mask;
1814 u32 i;
1815
1816 pci_read_config_dword(adapter->pdev,
1817 PCICFG_UE_STATUS_LOW, &ue_status_lo);
1818 pci_read_config_dword(adapter->pdev,
1819 PCICFG_UE_STATUS_HIGH, &ue_status_hi);
1820 pci_read_config_dword(adapter->pdev,
1821 PCICFG_UE_STATUS_LOW_MASK, &ue_status_lo_mask);
1822 pci_read_config_dword(adapter->pdev,
1823 PCICFG_UE_STATUS_HI_MASK, &ue_status_hi_mask);
1824
1825 ue_status_lo = (ue_status_lo & (~ue_status_lo_mask));
1826 ue_status_hi = (ue_status_hi & (~ue_status_hi_mask));
1827
d053de91
AK		 1828 if (ue_status_lo || ue_status_hi) {
1829 adapter->ue_detected = true;
7acc2087 1830 adapter->eeh_err = true;
d053de91
AK		 1831 dev_err(&adapter->pdev->dev, "UE Detected!!\n");
1832 }
1833
7c185276
AK		 1834 if (ue_status_lo) {
1835 for (i = 0; ue_status_lo; ue_status_lo >>= 1, i++) {
1836 if (ue_status_lo & 1)
1837 dev_err(&adapter->pdev->dev,
1838 "UE: %s bit set\n", ue_status_low_desc[i]);
1839 }
1840 }
1841 if (ue_status_hi) {
1842 for (i = 0; ue_status_hi; ue_status_hi >>= 1, i++) {
1843 if (ue_status_hi & 1)
1844 dev_err(&adapter->pdev->dev,
1845 "UE: %s bit set\n", ue_status_hi_desc[i]);
1846 }
1847 }
1848
1849}
1850
ea1dae11
SP		 1851static void be_worker(struct work_struct *work)
1852{
1853 struct be_adapter *adapter =
1854 container_of(work, struct be_adapter, work.work);
3abcdeda
SP		 1855 struct be_rx_obj *rxo;
1856 int i;
ea1dae11 1857
f203af70
SK		 1858 /* when interrupts are not yet enabled, just reap any pending
1859 * mcc completions */
1860 if (!netif_running(adapter->netdev)) {
1861 int mcc_compl, status = 0;
1862
1863 mcc_compl = be_process_mcc(adapter, &status);
1864
1865 if (mcc_compl) {
1866 struct be_mcc_obj *mcc_obj = &adapter->mcc_obj;
1867 be_cq_notify(adapter, mcc_obj->cq.id, false, mcc_compl);
1868 }
1869 goto reschedule;
1870 }
1871
0fc48c37 1872 if (!adapter->stats_ioctl_sent)
3abcdeda 1873 be_cmd_get_stats(adapter, &adapter->stats_cmd);
ea1dae11 1874
4097f663 1875 be_tx_rate_update(adapter);
4097f663 1876
3abcdeda
SP		 1877 for_all_rx_queues(adapter, rxo, i) {
1878 be_rx_rate_update(rxo);
1879 be_rx_eqd_update(adapter, rxo);
1880
1881 if (rxo->rx_post_starved) {
1882 rxo->rx_post_starved = false;
1883 be_post_rx_frags(rxo);
1884 }
ea1dae11 1885 }
fe6d2a38 1886 if (!adapter->ue_detected && !lancer_chip(adapter))
d053de91 1887 be_detect_dump_ue(adapter);
ea1dae11 1888
f203af70 1889reschedule:
ea1dae11
SP		 1890 schedule_delayed_work(&adapter->work, msecs_to_jiffies(1000));
1891}
1892
8d56ff11
SP		 1893static void be_msix_disable(struct be_adapter *adapter)
1894{
1895 if (adapter->msix_enabled) {
1896 pci_disable_msix(adapter->pdev);
1897 adapter->msix_enabled = false;
1898 }
1899}
1900
3abcdeda
SP		 1901static int be_num_rxqs_get(struct be_adapter *adapter)
1902{
1903 if (multi_rxq && (adapter->function_caps & BE_FUNCTION_CAPS_RSS) &&
1904 !adapter->sriov_enabled && !(adapter->function_mode & 0x400)) {
1905 return 1 + MAX_RSS_QS; /* one default non-RSS queue */
1906 } else {
1907 dev_warn(&adapter->pdev->dev,
1908 "No support for multiple RX queues\n");
1909 return 1;
1910 }
1911}
1912
6b7c5b94
SP		 1913static void be_msix_enable(struct be_adapter *adapter)
1914{
3abcdeda 1915#define BE_MIN_MSIX_VECTORS (1 + 1) /* Rx + Tx */
6b7c5b94
SP		 1916 int i, status;
1917
3abcdeda
SP		 1918 adapter->num_rx_qs = be_num_rxqs_get(adapter);
1919
1920 for (i = 0; i < (adapter->num_rx_qs + 1); i++)
6b7c5b94
SP		 1921 adapter->msix_entries[i].entry = i;
1922
1923 status = pci_enable_msix(adapter->pdev, adapter->msix_entries,
3abcdeda
SP		 1924 adapter->num_rx_qs + 1);
1925 if (status == 0) {
1926 goto done;
1927 } else if (status >= BE_MIN_MSIX_VECTORS) {
1928 if (pci_enable_msix(adapter->pdev, adapter->msix_entries,
1929 status) == 0) {
1930 adapter->num_rx_qs = status - 1;
1931 dev_warn(&adapter->pdev->dev,
1932 "Could alloc only %d MSIx vectors. "
1933 "Using %d RX Qs\n", status, adapter->num_rx_qs);
1934 goto done;
1935 }
1936 }
1937 return;
1938done:
1939 adapter->msix_enabled = true;
6b7c5b94
SP		 1940}
1941
ba343c77
SB		 1942static void be_sriov_enable(struct be_adapter *adapter)
1943{
344dbf10 1944 be_check_sriov_fn_type(adapter);
6dedec81 1945#ifdef CONFIG_PCI_IOV
ba343c77 1946 if (be_physfn(adapter) && num_vfs) {
6dedec81
AK		 1947 int status;
1948
ba343c77
SB		 1949 status = pci_enable_sriov(adapter->pdev, num_vfs);
1950 adapter->sriov_enabled = status ? false : true;
1951 }
1952#endif
ba343c77
SB		 1953}
1954
1955static void be_sriov_disable(struct be_adapter *adapter)
1956{
1957#ifdef CONFIG_PCI_IOV
1958 if (adapter->sriov_enabled) {
1959 pci_disable_sriov(adapter->pdev);
1960 adapter->sriov_enabled = false;
1961 }
1962#endif
1963}
1964
fe6d2a38
SP		 1965static inline int be_msix_vec_get(struct be_adapter *adapter,
1966 struct be_eq_obj *eq_obj)
6b7c5b94 1967{
fe6d2a38 1968 return adapter->msix_entries[eq_obj->msix_vec_idx].vector;
6b7c5b94
SP		 1969}
1970
b628bde2
SP		 1971static int be_request_irq(struct be_adapter *adapter,
1972 struct be_eq_obj *eq_obj,
3abcdeda 1973 void *handler, char *desc, void *context)
6b7c5b94
SP		 1974{
1975 struct net_device *netdev = adapter->netdev;
b628bde2
SP		 1976 int vec;
1977
1978 sprintf(eq_obj->desc, "%s-%s", netdev->name, desc);
fe6d2a38 1979 vec = be_msix_vec_get(adapter, eq_obj);
3abcdeda 1980 return request_irq(vec, handler, 0, eq_obj->desc, context);
b628bde2
SP		 1981}
1982
3abcdeda
SP		 1983static void be_free_irq(struct be_adapter *adapter, struct be_eq_obj *eq_obj,
1984 void *context)
b628bde2 1985{
fe6d2a38 1986 int vec = be_msix_vec_get(adapter, eq_obj);
3abcdeda 1987 free_irq(vec, context);
b628bde2 1988}
6b7c5b94 1989
b628bde2
SP		 1990static int be_msix_register(struct be_adapter *adapter)
1991{
3abcdeda
SP		 1992 struct be_rx_obj *rxo;
1993 int status, i;
1994 char qname[10];
b628bde2 1995
3abcdeda
SP		 1996 status = be_request_irq(adapter, &adapter->tx_eq, be_msix_tx_mcc, "tx",
1997 adapter);
6b7c5b94
SP		 1998 if (status)
1999 goto err;
2000
3abcdeda
SP		 2001 for_all_rx_queues(adapter, rxo, i) {
2002 sprintf(qname, "rxq%d", i);
2003 status = be_request_irq(adapter, &rxo->rx_eq, be_msix_rx,
2004 qname, rxo);
2005 if (status)
2006 goto err_msix;
2007 }
b628bde2 2008
6b7c5b94 2009 return 0;
b628bde2 2010
3abcdeda
SP		 2011err_msix:
2012 be_free_irq(adapter, &adapter->tx_eq, adapter);
2013
2014 for (i--, rxo = &adapter->rx_obj[i]; i >= 0; i--, rxo--)
2015 be_free_irq(adapter, &rxo->rx_eq, rxo);
2016
6b7c5b94
SP		 2017err:
2018 dev_warn(&adapter->pdev->dev,
2019 "MSIX Request IRQ failed - err %d\n", status);
2020 pci_disable_msix(adapter->pdev);
2021 adapter->msix_enabled = false;
2022 return status;
2023}
2024
2025static int be_irq_register(struct be_adapter *adapter)
2026{
2027 struct net_device *netdev = adapter->netdev;
2028 int status;
2029
2030 if (adapter->msix_enabled) {
2031 status = be_msix_register(adapter);
2032 if (status == 0)
2033 goto done;
ba343c77
SB		 2034 /* INTx is not supported for VF */
2035 if (!be_physfn(adapter))
2036 return status;
6b7c5b94
SP		 2037 }
2038
2039 /* INTx */
2040 netdev->irq = adapter->pdev->irq;
2041 status = request_irq(netdev->irq, be_intx, IRQF_SHARED, netdev->name,
2042 adapter);
2043 if (status) {
2044 dev_err(&adapter->pdev->dev,
2045 "INTx request IRQ failed - err %d\n", status);
2046 return status;
2047 }
2048done:
2049 adapter->isr_registered = true;
2050 return 0;
2051}
2052
2053static void be_irq_unregister(struct be_adapter *adapter)
2054{
2055 struct net_device *netdev = adapter->netdev;
3abcdeda
SP		 2056 struct be_rx_obj *rxo;
2057 int i;
6b7c5b94
SP		 2058
2059 if (!adapter->isr_registered)
2060 return;
2061
2062 /* INTx */
2063 if (!adapter->msix_enabled) {
2064 free_irq(netdev->irq, adapter);
2065 goto done;
2066 }
2067
2068 /* MSIx */
3abcdeda
SP		 2069 be_free_irq(adapter, &adapter->tx_eq, adapter);
2070
2071 for_all_rx_queues(adapter, rxo, i)
2072 be_free_irq(adapter, &rxo->rx_eq, rxo);
2073
6b7c5b94
SP		 2074done:
2075 adapter->isr_registered = false;
6b7c5b94
SP		 2076}
2077
889cd4b2
SP		 2078static int be_close(struct net_device *netdev)
2079{
2080 struct be_adapter *adapter = netdev_priv(netdev);
3abcdeda 2081 struct be_rx_obj *rxo;
889cd4b2 2082 struct be_eq_obj *tx_eq = &adapter->tx_eq;
3abcdeda 2083 int vec, i;
889cd4b2 2084
889cd4b2
SP		 2085 be_async_mcc_disable(adapter);
2086
2087 netif_stop_queue(netdev);
2088 netif_carrier_off(netdev);
2089 adapter->link_up = false;
2090
fe6d2a38
SP		 2091 if (!lancer_chip(adapter))
2092 be_intr_set(adapter, false);
889cd4b2
SP		 2093
2094 if (adapter->msix_enabled) {
fe6d2a38 2095 vec = be_msix_vec_get(adapter, tx_eq);
889cd4b2 2096 synchronize_irq(vec);
3abcdeda
SP		 2097
2098 for_all_rx_queues(adapter, rxo, i) {
fe6d2a38 2099 vec = be_msix_vec_get(adapter, &rxo->rx_eq);
3abcdeda
SP		 2100 synchronize_irq(vec);
2101 }
889cd4b2
SP		 2102 } else {
2103 synchronize_irq(netdev->irq);
2104 }
2105 be_irq_unregister(adapter);
2106
3abcdeda
SP		 2107 for_all_rx_queues(adapter, rxo, i)
2108 napi_disable(&rxo->rx_eq.napi);
2109
889cd4b2
SP		 2110 napi_disable(&tx_eq->napi);
2111
2112 /* Wait for all pending tx completions to arrive so that
2113 * all tx skbs are freed.
2114 */
2115 be_tx_compl_clean(adapter);
2116
2117 return 0;
2118}
2119
6b7c5b94
SP		 2120static int be_open(struct net_device *netdev)
2121{
2122 struct be_adapter *adapter = netdev_priv(netdev);
6b7c5b94 2123 struct be_eq_obj *tx_eq = &adapter->tx_eq;
3abcdeda 2124 struct be_rx_obj *rxo;
a8f447bd 2125 bool link_up;
3abcdeda 2126 int status, i;
0388f251
SB		 2127 u8 mac_speed;
2128 u16 link_speed;
5fb379ee 2129
3abcdeda
SP		 2130 for_all_rx_queues(adapter, rxo, i) {
2131 be_post_rx_frags(rxo);
2132 napi_enable(&rxo->rx_eq.napi);
2133 }
5fb379ee
SP		 2134 napi_enable(&tx_eq->napi);
2135
2136 be_irq_register(adapter);
2137
fe6d2a38
SP		 2138 if (!lancer_chip(adapter))
2139 be_intr_set(adapter, true);
5fb379ee
SP		 2140
2141 /* The evt queues are created in unarmed state; arm them */
3abcdeda
SP		 2142 for_all_rx_queues(adapter, rxo, i) {
2143 be_eq_notify(adapter, rxo->rx_eq.q.id, true, false, 0);
2144 be_cq_notify(adapter, rxo->cq.id, true, 0);
2145 }
8788fdc2 2146 be_eq_notify(adapter, tx_eq->q.id, true, false, 0);
5fb379ee 2147
7a1e9b20
SP		 2148 /* Now that interrupts are on we can process async mcc */
2149 be_async_mcc_enable(adapter);
2150
0388f251
SB		 2151 status = be_cmd_link_status_query(adapter, &link_up, &mac_speed,
2152 &link_speed);
a8f447bd 2153 if (status)
889cd4b2 2154 goto err;
a8f447bd 2155 be_link_status_update(adapter, link_up);
5fb379ee 2156
889cd4b2 2157 if (be_physfn(adapter)) {
1da87b7f 2158 status = be_vid_config(adapter, false, 0);
889cd4b2
SP		 2159 if (status)
2160 goto err;
4f2aa89c 2161
ba343c77
SB		 2162 status = be_cmd_set_flow_control(adapter,
2163 adapter->tx_fc, adapter->rx_fc);
2164 if (status)
889cd4b2 2165 goto err;
ba343c77 2166 }
4f2aa89c 2167
889cd4b2
SP		 2168 return 0;
2169err:
2170 be_close(adapter->netdev);
2171 return -EIO;
5fb379ee
SP		 2172}
2173
71d8d1b5
AK		 2174static int be_setup_wol(struct be_adapter *adapter, bool enable)
2175{
2176 struct be_dma_mem cmd;
2177 int status = 0;
2178 u8 mac[ETH_ALEN];
2179
2180 memset(mac, 0, ETH_ALEN);
2181
2182 cmd.size = sizeof(struct be_cmd_req_acpi_wol_magic_config);
2b7bcebf
IV		 2183 cmd.va = dma_alloc_coherent(&adapter->pdev->dev, cmd.size, &cmd.dma,
2184 GFP_KERNEL);
71d8d1b5
AK		 2185 if (cmd.va == NULL)
2186 return -1;
2187 memset(cmd.va, 0, cmd.size);
2188
2189 if (enable) {
2190 status = pci_write_config_dword(adapter->pdev,
2191 PCICFG_PM_CONTROL_OFFSET, PCICFG_PM_CONTROL_MASK);
2192 if (status) {
2193 dev_err(&adapter->pdev->dev,
2381a55c 2194 "Could not enable Wake-on-lan\n");
2b7bcebf
IV		 2195 dma_free_coherent(&adapter->pdev->dev, cmd.size, cmd.va,
2196 cmd.dma);
71d8d1b5
AK		 2197 return status;
2198 }
2199 status = be_cmd_enable_magic_wol(adapter,
2200 adapter->netdev->dev_addr, &cmd);
2201 pci_enable_wake(adapter->pdev, PCI_D3hot, 1);
2202 pci_enable_wake(adapter->pdev, PCI_D3cold, 1);
2203 } else {
2204 status = be_cmd_enable_magic_wol(adapter, mac, &cmd);
2205 pci_enable_wake(adapter->pdev, PCI_D3hot, 0);
2206 pci_enable_wake(adapter->pdev, PCI_D3cold, 0);
2207 }
2208
2b7bcebf 2209 dma_free_coherent(&adapter->pdev->dev, cmd.size, cmd.va, cmd.dma);
71d8d1b5
AK		 2210 return status;
2211}
2212
6d87f5c3
AK		 2213/*
2214 * Generate a seed MAC address from the PF MAC Address using jhash.
2215 * MAC Address for VFs are assigned incrementally starting from the seed.
2216 * These addresses are programmed in the ASIC by the PF and the VF driver
2217 * queries for the MAC address during its probe.
2218 */
2219static inline int be_vf_eth_addr_config(struct be_adapter *adapter)
2220{
2221 u32 vf = 0;
3abcdeda 2222 int status = 0;
6d87f5c3
AK		 2223 u8 mac[ETH_ALEN];
2224
2225 be_vf_eth_addr_generate(adapter, mac);
2226
2227 for (vf = 0; vf < num_vfs; vf++) {
2228 status = be_cmd_pmac_add(adapter, mac,
2229 adapter->vf_cfg[vf].vf_if_handle,
f8617e08
AK		 2230 &adapter->vf_cfg[vf].vf_pmac_id,
2231 vf + 1);
6d87f5c3
AK		 2232 if (status)
2233 dev_err(&adapter->pdev->dev,
2234 "Mac address add failed for VF %d\n", vf);
2235 else
2236 memcpy(adapter->vf_cfg[vf].vf_mac_addr, mac, ETH_ALEN);
2237
2238 mac[5] += 1;
2239 }
2240 return status;
2241}
2242
2243static inline void be_vf_eth_addr_rem(struct be_adapter *adapter)
2244{
2245 u32 vf;
2246
2247 for (vf = 0; vf < num_vfs; vf++) {
2248 if (adapter->vf_cfg[vf].vf_pmac_id != BE_INVALID_PMAC_ID)
2249 be_cmd_pmac_del(adapter,
2250 adapter->vf_cfg[vf].vf_if_handle,
f8617e08 2251 adapter->vf_cfg[vf].vf_pmac_id, vf + 1);
6d87f5c3
AK		 2252 }
2253}
2254
5fb379ee
SP		 2255static int be_setup(struct be_adapter *adapter)
2256{
5fb379ee 2257 struct net_device *netdev = adapter->netdev;
ba343c77 2258 u32 cap_flags, en_flags, vf = 0;
6b7c5b94 2259 int status;
ba343c77
SB		 2260 u8 mac[ETH_ALEN];
2261
2262 cap_flags = en_flags = BE_IF_FLAGS_UNTAGGED | BE_IF_FLAGS_BROADCAST;
6b7c5b94 2263
ba343c77
SB		 2264 if (be_physfn(adapter)) {
2265 cap_flags |= BE_IF_FLAGS_MCAST_PROMISCUOUS |
2266 BE_IF_FLAGS_PROMISCUOUS |
2267 BE_IF_FLAGS_PASS_L3L4_ERRORS;
2268 en_flags |= BE_IF_FLAGS_PASS_L3L4_ERRORS;
3abcdeda
SP		 2269
2270 if (be_multi_rxq(adapter)) {
2271 cap_flags |= BE_IF_FLAGS_RSS;
2272 en_flags |= BE_IF_FLAGS_RSS;
2273 }
ba343c77 2274 }
73d540f2
SP		 2275
2276 status = be_cmd_if_create(adapter, cap_flags, en_flags,
2277 netdev->dev_addr, false/* pmac_invalid */,
ba343c77 2278 &adapter->if_handle, &adapter->pmac_id, 0);
6b7c5b94
SP		 2279 if (status != 0)
2280 goto do_none;
2281
ba343c77 2282 if (be_physfn(adapter)) {
c99ac3e7
AK		 2283 if (adapter->sriov_enabled) {
2284 while (vf < num_vfs) {
2285 cap_flags = en_flags = BE_IF_FLAGS_UNTAGGED |
2286 BE_IF_FLAGS_BROADCAST;
2287 status = be_cmd_if_create(adapter, cap_flags,
2288 en_flags, mac, true,
64600ea5 2289 &adapter->vf_cfg[vf].vf_if_handle,
ba343c77 2290 NULL, vf+1);
c99ac3e7
AK		 2291 if (status) {
2292 dev_err(&adapter->pdev->dev,
2293 "Interface Create failed for VF %d\n",
2294 vf);
2295 goto if_destroy;
2296 }
2297 adapter->vf_cfg[vf].vf_pmac_id =
2298 BE_INVALID_PMAC_ID;
2299 vf++;
ba343c77 2300 }
84e5b9f7 2301 }
c99ac3e7 2302 } else {
ba343c77
SB		 2303 status = be_cmd_mac_addr_query(adapter, mac,
2304 MAC_ADDRESS_TYPE_NETWORK, false, adapter->if_handle);
2305 if (!status) {
2306 memcpy(adapter->netdev->dev_addr, mac, ETH_ALEN);
2307 memcpy(adapter->netdev->perm_addr, mac, ETH_ALEN);
2308 }
2309 }
2310
6b7c5b94
SP		 2311 status = be_tx_queues_create(adapter);
2312 if (status != 0)
2313 goto if_destroy;
2314
2315 status = be_rx_queues_create(adapter);
2316 if (status != 0)
2317 goto tx_qs_destroy;
2318
5fb379ee
SP		 2319 status = be_mcc_queues_create(adapter);
2320 if (status != 0)
2321 goto rx_qs_destroy;
6b7c5b94 2322
0dffc83e
AK		 2323 adapter->link_speed = -1;
2324
6b7c5b94
SP		 2325 return 0;
2326
6d87f5c3 2327 be_mcc_queues_destroy(adapter);
5fb379ee
SP		 2328rx_qs_destroy:
2329 be_rx_queues_destroy(adapter);
6b7c5b94
SP		 2330tx_qs_destroy:
2331 be_tx_queues_destroy(adapter);
2332if_destroy:
c99ac3e7
AK		 2333 if (be_physfn(adapter) && adapter->sriov_enabled)
2334 for (vf = 0; vf < num_vfs; vf++)
2335 if (adapter->vf_cfg[vf].vf_if_handle)
2336 be_cmd_if_destroy(adapter,
658681f7
AK		 2337 adapter->vf_cfg[vf].vf_if_handle,
2338 vf + 1);
2339 be_cmd_if_destroy(adapter, adapter->if_handle, 0);
6b7c5b94
SP		 2340do_none:
2341 return status;
2342}
2343
5fb379ee
SP		 2344static int be_clear(struct be_adapter *adapter)
2345{
7ab8b0b4
AK		 2346 int vf;
2347
c99ac3e7 2348 if (be_physfn(adapter) && adapter->sriov_enabled)
6d87f5c3
AK		 2349 be_vf_eth_addr_rem(adapter);
2350
1a8887d8 2351 be_mcc_queues_destroy(adapter);
5fb379ee
SP		 2352 be_rx_queues_destroy(adapter);
2353 be_tx_queues_destroy(adapter);
2354
7ab8b0b4
AK		 2355 if (be_physfn(adapter) && adapter->sriov_enabled)
2356 for (vf = 0; vf < num_vfs; vf++)
2357 if (adapter->vf_cfg[vf].vf_if_handle)
2358 be_cmd_if_destroy(adapter,
2359 adapter->vf_cfg[vf].vf_if_handle,
2360 vf + 1);
2361
658681f7 2362 be_cmd_if_destroy(adapter, adapter->if_handle, 0);
5fb379ee 2363
2243e2e9
SP		 2364 /* tell fw we're done with firing cmds */
2365 be_cmd_fw_clean(adapter);
5fb379ee
SP		 2366 return 0;
2367}
2368
6b7c5b94 2369
84517482 2370#define FW_FILE_HDR_SIGN "ServerEngines Corp. "
fa9a6fed 2371static bool be_flash_redboot(struct be_adapter *adapter,
3f0d4560
AK		 2372 const u8 *p, u32 img_start, int image_size,
2373 int hdr_size)
fa9a6fed
SB		 2374{
2375 u32 crc_offset;
2376 u8 flashed_crc[4];
2377 int status;
3f0d4560
AK		 2378
2379 crc_offset = hdr_size + img_start + image_size - 4;
2380
fa9a6fed 2381 p += crc_offset;
3f0d4560
AK		 2382
2383 status = be_cmd_get_flash_crc(adapter, flashed_crc,
f510fc64 2384 (image_size - 4));
fa9a6fed
SB		 2385 if (status) {
2386 dev_err(&adapter->pdev->dev,
2387 "could not get crc from flash, not flashing redboot\n");
2388 return false;
2389 }
2390
2391 /*update redboot only if crc does not match*/
2392 if (!memcmp(flashed_crc, p, 4))
2393 return false;
2394 else
2395 return true;
fa9a6fed
SB		 2396}
2397
3f0d4560 2398static int be_flash_data(struct be_adapter *adapter,
84517482 2399 const struct firmware *fw,
3f0d4560
AK		 2400 struct be_dma_mem *flash_cmd, int num_of_images)
2401
84517482 2402{
3f0d4560
AK		 2403 int status = 0, i, filehdr_size = 0;
2404 u32 total_bytes = 0, flash_op;
84517482
AK		 2405 int num_bytes;
2406 const u8 *p = fw->data;
2407 struct be_cmd_write_flashrom *req = flash_cmd->va;
215faf9c 2408 const struct flash_comp *pflashcomp;
9fe96934 2409 int num_comp;
3f0d4560 2410
215faf9c 2411 static const struct flash_comp gen3_flash_types[9] = {
3f0d4560
AK		 2412 { FLASH_iSCSI_PRIMARY_IMAGE_START_g3, IMG_TYPE_ISCSI_ACTIVE,
2413 FLASH_IMAGE_MAX_SIZE_g3},
2414 { FLASH_REDBOOT_START_g3, IMG_TYPE_REDBOOT,
2415 FLASH_REDBOOT_IMAGE_MAX_SIZE_g3},
2416 { FLASH_iSCSI_BIOS_START_g3, IMG_TYPE_BIOS,
2417 FLASH_BIOS_IMAGE_MAX_SIZE_g3},
2418 { FLASH_PXE_BIOS_START_g3, IMG_TYPE_PXE_BIOS,
2419 FLASH_BIOS_IMAGE_MAX_SIZE_g3},
2420 { FLASH_FCoE_BIOS_START_g3, IMG_TYPE_FCOE_BIOS,
2421 FLASH_BIOS_IMAGE_MAX_SIZE_g3},
2422 { FLASH_iSCSI_BACKUP_IMAGE_START_g3, IMG_TYPE_ISCSI_BACKUP,
2423 FLASH_IMAGE_MAX_SIZE_g3},
2424 { FLASH_FCoE_PRIMARY_IMAGE_START_g3, IMG_TYPE_FCOE_FW_ACTIVE,
2425 FLASH_IMAGE_MAX_SIZE_g3},
2426 { FLASH_FCoE_BACKUP_IMAGE_START_g3, IMG_TYPE_FCOE_FW_BACKUP,
9fe96934
SB		 2427 FLASH_IMAGE_MAX_SIZE_g3},
2428 { FLASH_NCSI_START_g3, IMG_TYPE_NCSI_FW,
2429 FLASH_NCSI_IMAGE_MAX_SIZE_g3}
3f0d4560 2430 };
215faf9c 2431 static const struct flash_comp gen2_flash_types[8] = {
3f0d4560
AK		 2432 { FLASH_iSCSI_PRIMARY_IMAGE_START_g2, IMG_TYPE_ISCSI_ACTIVE,
2433 FLASH_IMAGE_MAX_SIZE_g2},
2434 { FLASH_REDBOOT_START_g2, IMG_TYPE_REDBOOT,
2435 FLASH_REDBOOT_IMAGE_MAX_SIZE_g2},
2436 { FLASH_iSCSI_BIOS_START_g2, IMG_TYPE_BIOS,
2437 FLASH_BIOS_IMAGE_MAX_SIZE_g2},
2438 { FLASH_PXE_BIOS_START_g2, IMG_TYPE_PXE_BIOS,
2439 FLASH_BIOS_IMAGE_MAX_SIZE_g2},
2440 { FLASH_FCoE_BIOS_START_g2, IMG_TYPE_FCOE_BIOS,
2441 FLASH_BIOS_IMAGE_MAX_SIZE_g2},
2442 { FLASH_iSCSI_BACKUP_IMAGE_START_g2, IMG_TYPE_ISCSI_BACKUP,
2443 FLASH_IMAGE_MAX_SIZE_g2},
2444 { FLASH_FCoE_PRIMARY_IMAGE_START_g2, IMG_TYPE_FCOE_FW_ACTIVE,
2445 FLASH_IMAGE_MAX_SIZE_g2},
2446 { FLASH_FCoE_BACKUP_IMAGE_START_g2, IMG_TYPE_FCOE_FW_BACKUP,
2447 FLASH_IMAGE_MAX_SIZE_g2}
2448 };
2449
2450 if (adapter->generation == BE_GEN3) {
2451 pflashcomp = gen3_flash_types;
2452 filehdr_size = sizeof(struct flash_file_hdr_g3);
215faf9c 2453 num_comp = ARRAY_SIZE(gen3_flash_types);
3f0d4560
AK		 2454 } else {
2455 pflashcomp = gen2_flash_types;
2456 filehdr_size = sizeof(struct flash_file_hdr_g2);
215faf9c 2457 num_comp = ARRAY_SIZE(gen2_flash_types);
84517482 2458 }
9fe96934
SB		 2459 for (i = 0; i < num_comp; i++) {
2460 if ((pflashcomp[i].optype == IMG_TYPE_NCSI_FW) &&
2461 memcmp(adapter->fw_ver, "3.102.148.0", 11) < 0)
2462 continue;
3f0d4560
AK		 2463 if ((pflashcomp[i].optype == IMG_TYPE_REDBOOT) &&
2464 (!be_flash_redboot(adapter, fw->data,
fae21a4d
AK		 2465 pflashcomp[i].offset, pflashcomp[i].size, filehdr_size +
2466 (num_of_images * sizeof(struct image_hdr)))))
3f0d4560
AK		 2467 continue;
2468 p = fw->data;
2469 p += filehdr_size + pflashcomp[i].offset
2470 + (num_of_images * sizeof(struct image_hdr));
2471 if (p + pflashcomp[i].size > fw->data + fw->size)
84517482 2472 return -1;
3f0d4560
AK		 2473 total_bytes = pflashcomp[i].size;
2474 while (total_bytes) {
2475 if (total_bytes > 32*1024)
2476 num_bytes = 32*1024;
2477 else
2478 num_bytes = total_bytes;
2479 total_bytes -= num_bytes;
2480
2481 if (!total_bytes)
2482 flash_op = FLASHROM_OPER_FLASH;
2483 else
2484 flash_op = FLASHROM_OPER_SAVE;
2485 memcpy(req->params.data_buf, p, num_bytes);
2486 p += num_bytes;
2487 status = be_cmd_write_flashrom(adapter, flash_cmd,
2488 pflashcomp[i].optype, flash_op, num_bytes);
2489 if (status) {
2490 dev_err(&adapter->pdev->dev,
2491 "cmd to write to flash rom failed.\n");
2492 return -1;
2493 }
2494 yield();
84517482 2495 }
84517482 2496 }
84517482
AK		 2497 return 0;
2498}
2499
3f0d4560
AK		 2500static int get_ufigen_type(struct flash_file_hdr_g2 *fhdr)
2501{
2502 if (fhdr == NULL)
2503 return 0;
2504 if (fhdr->build[0] == '3')
2505 return BE_GEN3;
2506 else if (fhdr->build[0] == '2')
2507 return BE_GEN2;
2508 else
2509 return 0;
2510}
2511
84517482
AK		 2512int be_load_fw(struct be_adapter *adapter, u8 *func)
2513{
2514 char fw_file[ETHTOOL_FLASH_MAX_FILENAME];
2515 const struct firmware *fw;
3f0d4560
AK		 2516 struct flash_file_hdr_g2 *fhdr;
2517 struct flash_file_hdr_g3 *fhdr3;
2518 struct image_hdr *img_hdr_ptr = NULL;
84517482 2519 struct be_dma_mem flash_cmd;
8b93b710 2520 int status, i = 0, num_imgs = 0;
84517482 2521 const u8 *p;
84517482 2522
d9efd2af
SB		 2523 if (!netif_running(adapter->netdev)) {
2524 dev_err(&adapter->pdev->dev,
2525 "Firmware load not allowed (interface is down)\n");
2526 return -EPERM;
2527 }
2528
84517482
AK		 2529 strcpy(fw_file, func);
2530
2531 status = request_firmware(&fw, fw_file, &adapter->pdev->dev);
2532 if (status)
2533 goto fw_exit;
2534
2535 p = fw->data;
3f0d4560 2536 fhdr = (struct flash_file_hdr_g2 *) p;
84517482
AK		 2537 dev_info(&adapter->pdev->dev, "Flashing firmware file %s\n", fw_file);
2538
84517482 2539 flash_cmd.size = sizeof(struct be_cmd_write_flashrom) + 32*1024;
2b7bcebf
IV		 2540 flash_cmd.va = dma_alloc_coherent(&adapter->pdev->dev, flash_cmd.size,
2541 &flash_cmd.dma, GFP_KERNEL);
84517482
AK		 2542 if (!flash_cmd.va) {
2543 status = -ENOMEM;
2544 dev_err(&adapter->pdev->dev,
2545 "Memory allocation failure while flashing\n");
2546 goto fw_exit;
2547 }
2548
3f0d4560
AK		 2549 if ((adapter->generation == BE_GEN3) &&
2550 (get_ufigen_type(fhdr) == BE_GEN3)) {
2551 fhdr3 = (struct flash_file_hdr_g3 *) fw->data;
8b93b710
AK		 2552 num_imgs = le32_to_cpu(fhdr3->num_imgs);
2553 for (i = 0; i < num_imgs; i++) {
3f0d4560
AK		 2554 img_hdr_ptr = (struct image_hdr *) (fw->data +
2555 (sizeof(struct flash_file_hdr_g3) +
8b93b710
AK		 2556 i * sizeof(struct image_hdr)));
2557 if (le32_to_cpu(img_hdr_ptr->imageid) == 1)
2558 status = be_flash_data(adapter, fw, &flash_cmd,
2559 num_imgs);
3f0d4560
AK		 2560 }
2561 } else if ((adapter->generation == BE_GEN2) &&
2562 (get_ufigen_type(fhdr) == BE_GEN2)) {
2563 status = be_flash_data(adapter, fw, &flash_cmd, 0);
2564 } else {
2565 dev_err(&adapter->pdev->dev,
2566 "UFI and Interface are not compatible for flashing\n");
2567 status = -1;
84517482
AK		 2568 }
2569
2b7bcebf
IV		 2570 dma_free_coherent(&adapter->pdev->dev, flash_cmd.size, flash_cmd.va,
2571 flash_cmd.dma);
84517482
AK		 2572 if (status) {
2573 dev_err(&adapter->pdev->dev, "Firmware load error\n");
2574 goto fw_exit;
2575 }
2576
af901ca1 2577 dev_info(&adapter->pdev->dev, "Firmware flashed successfully\n");
84517482
AK		 2578
2579fw_exit:
2580 release_firmware(fw);
2581 return status;
2582}
2583
6b7c5b94
SP		 2584static struct net_device_ops be_netdev_ops = {
2585 .ndo_open = be_open,
2586 .ndo_stop = be_close,
2587 .ndo_start_xmit = be_xmit,
6b7c5b94
SP		 2588 .ndo_set_rx_mode = be_set_multicast_list,
2589 .ndo_set_mac_address = be_mac_addr_set,
2590 .ndo_change_mtu = be_change_mtu,
2591 .ndo_validate_addr = eth_validate_addr,
2592 .ndo_vlan_rx_register = be_vlan_register,
2593 .ndo_vlan_rx_add_vid = be_vlan_add_vid,
2594 .ndo_vlan_rx_kill_vid = be_vlan_rem_vid,
64600ea5 2595 .ndo_set_vf_mac = be_set_vf_mac,
1da87b7f 2596 .ndo_set_vf_vlan = be_set_vf_vlan,
e1d18735 2597 .ndo_set_vf_tx_rate = be_set_vf_tx_rate,
64600ea5 2598 .ndo_get_vf_config = be_get_vf_config
6b7c5b94
SP		 2599};
2600
2601static void be_netdev_init(struct net_device *netdev)
2602{
2603 struct be_adapter *adapter = netdev_priv(netdev);
3abcdeda
SP		 2604 struct be_rx_obj *rxo;
2605 int i;
6b7c5b94
SP		 2606
2607 netdev->features |= NETIF_F_SG | NETIF_F_HW_VLAN_RX | NETIF_F_TSO |
79032644
MM		 2608 NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_FILTER |
2609 NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
49e4b847 2610 NETIF_F_GRO | NETIF_F_TSO6;
6b7c5b94 2611
79032644
MM		 2612 netdev->vlan_features |= NETIF_F_SG | NETIF_F_TSO |
2613 NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM;
51c59870 2614
fe6d2a38
SP		 2615 if (lancer_chip(adapter))
2616 netdev->vlan_features |= NETIF_F_TSO6;
2617
6b7c5b94
SP		 2618 netdev->flags |= IFF_MULTICAST;
2619
728a9972
AK		 2620 adapter->rx_csum = true;
2621
9e90c961
AK		 2622 /* Default settings for Rx and Tx flow control */
2623 adapter->rx_fc = true;
2624 adapter->tx_fc = true;
2625
c190e3c8
AK		 2626 netif_set_gso_max_size(netdev, 65535);
2627
6b7c5b94
SP		 2628 BE_SET_NETDEV_OPS(netdev, &be_netdev_ops);
2629
2630 SET_ETHTOOL_OPS(netdev, &be_ethtool_ops);
2631
3abcdeda
SP		 2632 for_all_rx_queues(adapter, rxo, i)
2633 netif_napi_add(netdev, &rxo->rx_eq.napi, be_poll_rx,
2634 BE_NAPI_WEIGHT);
2635
5fb379ee 2636 netif_napi_add(netdev, &adapter->tx_eq.napi, be_poll_tx_mcc,
6b7c5b94 2637 BE_NAPI_WEIGHT);
6b7c5b94
SP		 2638}
2639
2640static void be_unmap_pci_bars(struct be_adapter *adapter)
2641{
8788fdc2
SP		 2642 if (adapter->csr)
2643 iounmap(adapter->csr);
2644 if (adapter->db)
2645 iounmap(adapter->db);
ba343c77 2646 if (adapter->pcicfg && be_physfn(adapter))
8788fdc2 2647 iounmap(adapter->pcicfg);
6b7c5b94
SP		 2648}
2649
2650static int be_map_pci_bars(struct be_adapter *adapter)
2651{
2652 u8 __iomem *addr;
ba343c77 2653 int pcicfg_reg, db_reg;
6b7c5b94 2654
fe6d2a38
SP		 2655 if (lancer_chip(adapter)) {
2656 addr = ioremap_nocache(pci_resource_start(adapter->pdev, 0),
2657 pci_resource_len(adapter->pdev, 0));
2658 if (addr == NULL)
2659 return -ENOMEM;
2660 adapter->db = addr;
2661 return 0;
2662 }
2663
ba343c77
SB		 2664 if (be_physfn(adapter)) {
2665 addr = ioremap_nocache(pci_resource_start(adapter->pdev, 2),
2666 pci_resource_len(adapter->pdev, 2));
2667 if (addr == NULL)
2668 return -ENOMEM;
2669 adapter->csr = addr;
2670 }
6b7c5b94 2671
ba343c77 2672 if (adapter->generation == BE_GEN2) {
7b139c83 2673 pcicfg_reg = 1;
ba343c77
SB		 2674 db_reg = 4;
2675 } else {
7b139c83 2676 pcicfg_reg = 0;
ba343c77
SB		 2677 if (be_physfn(adapter))
2678 db_reg = 4;
2679 else
2680 db_reg = 0;
2681 }
2682 addr = ioremap_nocache(pci_resource_start(adapter->pdev, db_reg),
2683 pci_resource_len(adapter->pdev, db_reg));
6b7c5b94
SP		 2684 if (addr == NULL)
2685 goto pci_map_err;
ba343c77
SB		 2686 adapter->db = addr;
2687
2688 if (be_physfn(adapter)) {
2689 addr = ioremap_nocache(
2690 pci_resource_start(adapter->pdev, pcicfg_reg),
2691 pci_resource_len(adapter->pdev, pcicfg_reg));
2692 if (addr == NULL)
2693 goto pci_map_err;
2694 adapter->pcicfg = addr;
2695 } else
2696 adapter->pcicfg = adapter->db + SRIOV_VF_PCICFG_OFFSET;
6b7c5b94
SP		 2697
2698 return 0;
2699pci_map_err:
2700 be_unmap_pci_bars(adapter);
2701 return -ENOMEM;
2702}
2703
2704
2705static void be_ctrl_cleanup(struct be_adapter *adapter)
2706{
8788fdc2 2707 struct be_dma_mem *mem = &adapter->mbox_mem_alloced;
6b7c5b94
SP		 2708
2709 be_unmap_pci_bars(adapter);
2710
2711 if (mem->va)
2b7bcebf
IV		 2712 dma_free_coherent(&adapter->pdev->dev, mem->size, mem->va,
2713 mem->dma);
e7b909a6
SP		 2714
2715 mem = &adapter->mc_cmd_mem;
2716 if (mem->va)
2b7bcebf
IV		 2717 dma_free_coherent(&adapter->pdev->dev, mem->size, mem->va,
2718 mem->dma);
6b7c5b94
SP		 2719}
2720
6b7c5b94
SP		 2721static int be_ctrl_init(struct be_adapter *adapter)
2722{
8788fdc2
SP		 2723 struct be_dma_mem *mbox_mem_alloc = &adapter->mbox_mem_alloced;
2724 struct be_dma_mem *mbox_mem_align = &adapter->mbox_mem;
e7b909a6 2725 struct be_dma_mem *mc_cmd_mem = &adapter->mc_cmd_mem;
6b7c5b94 2726 int status;
6b7c5b94
SP		 2727
2728 status = be_map_pci_bars(adapter);
2729 if (status)
e7b909a6 2730 goto done;
6b7c5b94
SP		 2731
2732 mbox_mem_alloc->size = sizeof(struct be_mcc_mailbox) + 16;
2b7bcebf
IV		 2733 mbox_mem_alloc->va = dma_alloc_coherent(&adapter->pdev->dev,
2734 mbox_mem_alloc->size,
2735 &mbox_mem_alloc->dma,
2736 GFP_KERNEL);
6b7c5b94 2737 if (!mbox_mem_alloc->va) {
e7b909a6
SP		 2738 status = -ENOMEM;
2739 goto unmap_pci_bars;
6b7c5b94 2740 }
e7b909a6 2741
6b7c5b94
SP		 2742 mbox_mem_align->size = sizeof(struct be_mcc_mailbox);
2743 mbox_mem_align->va = PTR_ALIGN(mbox_mem_alloc->va, 16);
2744 mbox_mem_align->dma = PTR_ALIGN(mbox_mem_alloc->dma, 16);
2745 memset(mbox_mem_align->va, 0, sizeof(struct be_mcc_mailbox));
e7b909a6
SP		 2746
2747 mc_cmd_mem->size = sizeof(struct be_cmd_req_mcast_mac_config);
2b7bcebf
IV		 2748 mc_cmd_mem->va = dma_alloc_coherent(&adapter->pdev->dev,
2749 mc_cmd_mem->size, &mc_cmd_mem->dma,
2750 GFP_KERNEL);
e7b909a6
SP		 2751 if (mc_cmd_mem->va == NULL) {
2752 status = -ENOMEM;
2753 goto free_mbox;
2754 }
2755 memset(mc_cmd_mem->va, 0, mc_cmd_mem->size);
2756
2984961c 2757 mutex_init(&adapter->mbox_lock);
8788fdc2
SP		 2758 spin_lock_init(&adapter->mcc_lock);
2759 spin_lock_init(&adapter->mcc_cq_lock);
a8f447bd 2760
dd131e76 2761 init_completion(&adapter->flash_compl);
cf588477 2762 pci_save_state(adapter->pdev);
6b7c5b94 2763 return 0;
e7b909a6
SP		 2764
2765free_mbox:
2b7bcebf
IV		 2766 dma_free_coherent(&adapter->pdev->dev, mbox_mem_alloc->size,
2767 mbox_mem_alloc->va, mbox_mem_alloc->dma);
e7b909a6
SP		 2768
2769unmap_pci_bars:
2770 be_unmap_pci_bars(adapter);
2771
2772done:
2773 return status;
6b7c5b94
SP		 2774}
2775
2776static void be_stats_cleanup(struct be_adapter *adapter)
2777{
3abcdeda 2778 struct be_dma_mem *cmd = &adapter->stats_cmd;
6b7c5b94
SP		 2779
2780 if (cmd->va)
2b7bcebf
IV		 2781 dma_free_coherent(&adapter->pdev->dev, cmd->size,
2782 cmd->va, cmd->dma);
6b7c5b94
SP		 2783}
2784
2785static int be_stats_init(struct be_adapter *adapter)
2786{
3abcdeda 2787 struct be_dma_mem *cmd = &adapter->stats_cmd;
6b7c5b94
SP		 2788
2789 cmd->size = sizeof(struct be_cmd_req_get_stats);
2b7bcebf
IV		 2790 cmd->va = dma_alloc_coherent(&adapter->pdev->dev, cmd->size, &cmd->dma,
2791 GFP_KERNEL);
6b7c5b94
SP		 2792 if (cmd->va == NULL)
2793 return -1;
d291b9af 2794 memset(cmd->va, 0, cmd->size);
6b7c5b94
SP		 2795 return 0;
2796}
2797
2798static void __devexit be_remove(struct pci_dev *pdev)
2799{
2800 struct be_adapter *adapter = pci_get_drvdata(pdev);
8d56ff11 2801
6b7c5b94
SP		 2802 if (!adapter)
2803 return;
2804
f203af70
SK		 2805 cancel_delayed_work_sync(&adapter->work);
2806
6b7c5b94
SP		 2807 unregister_netdev(adapter->netdev);
2808
5fb379ee
SP		 2809 be_clear(adapter);
2810
6b7c5b94
SP		 2811 be_stats_cleanup(adapter);
2812
2813 be_ctrl_cleanup(adapter);
2814
ba343c77
SB		 2815 be_sriov_disable(adapter);
2816
8d56ff11 2817 be_msix_disable(adapter);
6b7c5b94
SP		 2818
2819 pci_set_drvdata(pdev, NULL);
2820 pci_release_regions(pdev);
2821 pci_disable_device(pdev);
2822
2823 free_netdev(adapter->netdev);
2824}
2825
2243e2e9 2826static int be_get_config(struct be_adapter *adapter)
6b7c5b94 2827{
6b7c5b94 2828 int status;
2243e2e9 2829 u8 mac[ETH_ALEN];
6b7c5b94 2830
2243e2e9 2831 status = be_cmd_get_fw_ver(adapter, adapter->fw_ver);
6b7c5b94
SP		 2832 if (status)
2833 return status;
2834
3abcdeda
SP		 2835 status = be_cmd_query_fw_cfg(adapter, &adapter->port_num,
2836 &adapter->function_mode, &adapter->function_caps);
43a04fdc
SP		 2837 if (status)
2838 return status;
2839
2243e2e9 2840 memset(mac, 0, ETH_ALEN);
ba343c77
SB		 2841
2842 if (be_physfn(adapter)) {
2843 status = be_cmd_mac_addr_query(adapter, mac,
2243e2e9 2844 MAC_ADDRESS_TYPE_NETWORK, true /*permanent */, 0);
ca9e4988 2845
ba343c77
SB		 2846 if (status)
2847 return status;
ca9e4988 2848
ba343c77
SB		 2849 if (!is_valid_ether_addr(mac))
2850 return -EADDRNOTAVAIL;
2851
2852 memcpy(adapter->netdev->dev_addr, mac, ETH_ALEN);
2853 memcpy(adapter->netdev->perm_addr, mac, ETH_ALEN);
2854 }
6b7c5b94 2855
3486be29 2856 if (adapter->function_mode & 0x400)
82903e4b
AK		 2857 adapter->max_vlans = BE_NUM_VLANS_SUPPORTED/4;
2858 else
2859 adapter->max_vlans = BE_NUM_VLANS_SUPPORTED;
2860
2243e2e9 2861 return 0;
6b7c5b94
SP		 2862}
2863
fe6d2a38
SP		 2864static int be_dev_family_check(struct be_adapter *adapter)
2865{
2866 struct pci_dev *pdev = adapter->pdev;
2867 u32 sli_intf = 0, if_type;
2868
2869 switch (pdev->device) {
2870 case BE_DEVICE_ID1:
2871 case OC_DEVICE_ID1:
2872 adapter->generation = BE_GEN2;
2873 break;
2874 case BE_DEVICE_ID2:
2875 case OC_DEVICE_ID2:
2876 adapter->generation = BE_GEN3;
2877 break;
2878 case OC_DEVICE_ID3:
2879 pci_read_config_dword(pdev, SLI_INTF_REG_OFFSET, &sli_intf);
2880 if_type = (sli_intf & SLI_INTF_IF_TYPE_MASK) >>
2881 SLI_INTF_IF_TYPE_SHIFT;
2882
2883 if (((sli_intf & SLI_INTF_VALID_MASK) != SLI_INTF_VALID) ||
2884 if_type != 0x02) {
2885 dev_err(&pdev->dev, "SLI_INTF reg val is not valid\n");
2886 return -EINVAL;
2887 }
2888 if (num_vfs > 0) {
2889 dev_err(&pdev->dev, "VFs not supported\n");
2890 return -EINVAL;
2891 }
2892 adapter->sli_family = ((sli_intf & SLI_INTF_FAMILY_MASK) >>
2893 SLI_INTF_FAMILY_SHIFT);
2894 adapter->generation = BE_GEN3;
2895 break;
2896 default:
2897 adapter->generation = 0;
2898 }
2899 return 0;
2900}
2901
6b7c5b94
SP		 2902static int __devinit be_probe(struct pci_dev *pdev,
2903 const struct pci_device_id *pdev_id)
2904{
2905 int status = 0;
2906 struct be_adapter *adapter;
2907 struct net_device *netdev;
6b7c5b94
SP		 2908
2909 status = pci_enable_device(pdev);
2910 if (status)
2911 goto do_none;
2912
2913 status = pci_request_regions(pdev, DRV_NAME);
2914 if (status)
2915 goto disable_dev;
2916 pci_set_master(pdev);
2917
2918 netdev = alloc_etherdev(sizeof(struct be_adapter));
2919 if (netdev == NULL) {
2920 status = -ENOMEM;
2921 goto rel_reg;
2922 }
2923 adapter = netdev_priv(netdev);
2924 adapter->pdev = pdev;
2925 pci_set_drvdata(pdev, adapter);
fe6d2a38
SP		 2926
2927 status = be_dev_family_check(adapter);
63657b9c 2928 if (status)
fe6d2a38
SP		 2929 goto free_netdev;
2930
6b7c5b94 2931 adapter->netdev = netdev;
2243e2e9 2932 SET_NETDEV_DEV(netdev, &pdev->dev);
6b7c5b94 2933
2b7bcebf 2934 status = dma_set_mask(&pdev->dev, DMA_BIT_MASK(64));
6b7c5b94
SP		 2935 if (!status) {
2936 netdev->features |= NETIF_F_HIGHDMA;
2937 } else {
2b7bcebf 2938 status = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
6b7c5b94
SP		 2939 if (status) {
2940 dev_err(&pdev->dev, "Could not set PCI DMA Mask\n");
2941 goto free_netdev;
2942 }
2943 }
2944
ba343c77
SB		 2945 be_sriov_enable(adapter);
2946
6b7c5b94
SP		 2947 status = be_ctrl_init(adapter);
2948 if (status)
2949 goto free_netdev;
2950
2243e2e9 2951 /* sync up with fw's ready state */
ba343c77
SB		 2952 if (be_physfn(adapter)) {
2953 status = be_cmd_POST(adapter);
2954 if (status)
2955 goto ctrl_clean;
ba343c77 2956 }
6b7c5b94 2957
2243e2e9
SP		 2958 /* tell fw we're ready to fire cmds */
2959 status = be_cmd_fw_init(adapter);
6b7c5b94 2960 if (status)
2243e2e9
SP		 2961 goto ctrl_clean;
2962
a4b4dfab
AK		 2963 status = be_cmd_reset_function(adapter);
2964 if (status)
2965 goto ctrl_clean;
556ae191 2966
2243e2e9
SP		 2967 status = be_stats_init(adapter);
2968 if (status)
2969 goto ctrl_clean;
2970
2971 status = be_get_config(adapter);
6b7c5b94
SP		 2972 if (status)
2973 goto stats_clean;
6b7c5b94 2974
3abcdeda
SP		 2975 be_msix_enable(adapter);
2976
6b7c5b94 2977 INIT_DELAYED_WORK(&adapter->work, be_worker);
6b7c5b94 2978
5fb379ee
SP		 2979 status = be_setup(adapter);
2980 if (status)
3abcdeda 2981 goto msix_disable;
2243e2e9 2982
3abcdeda 2983 be_netdev_init(netdev);
6b7c5b94
SP		 2984 status = register_netdev(netdev);
2985 if (status != 0)
5fb379ee 2986 goto unsetup;
63a76944 2987 netif_carrier_off(netdev);
6b7c5b94 2988
e6319365
AK		 2989 if (be_physfn(adapter) && adapter->sriov_enabled) {
2990 status = be_vf_eth_addr_config(adapter);
2991 if (status)
2992 goto unreg_netdev;
2993 }
2994
c4ca2374 2995 dev_info(&pdev->dev, "%s port %d\n", nic_name(pdev), adapter->port_num);
f203af70 2996 schedule_delayed_work(&adapter->work, msecs_to_jiffies(100));
6b7c5b94
SP		 2997 return 0;
2998
e6319365
AK		 2999unreg_netdev:
3000 unregister_netdev(netdev);
5fb379ee
SP		 3001unsetup:
3002 be_clear(adapter);
3abcdeda
SP		 3003msix_disable:
3004 be_msix_disable(adapter);
6b7c5b94
SP		 3005stats_clean:
3006 be_stats_cleanup(adapter);
3007ctrl_clean:
3008 be_ctrl_cleanup(adapter);
3009free_netdev:
ba343c77 3010 be_sriov_disable(adapter);
fe6d2a38 3011 free_netdev(netdev);
8d56ff11 3012 pci_set_drvdata(pdev, NULL);
6b7c5b94
SP		 3013rel_reg:
3014 pci_release_regions(pdev);
3015disable_dev:
3016 pci_disable_device(pdev);
3017do_none:
c4ca2374 3018 dev_err(&pdev->dev, "%s initialization failed\n", nic_name(pdev));
6b7c5b94
SP		 3019 return status;
3020}
3021
3022static int be_suspend(struct pci_dev *pdev, pm_message_t state)
3023{
3024 struct be_adapter *adapter = pci_get_drvdata(pdev);
3025 struct net_device *netdev = adapter->netdev;
3026
a4ca055f 3027 cancel_delayed_work_sync(&adapter->work);
71d8d1b5
AK		 3028 if (adapter->wol)
3029 be_setup_wol(adapter, true);
3030
6b7c5b94
SP		 3031 netif_device_detach(netdev);
3032 if (netif_running(netdev)) {
3033 rtnl_lock();
3034 be_close(netdev);
3035 rtnl_unlock();
3036 }
9e90c961 3037 be_cmd_get_flow_control(adapter, &adapter->tx_fc, &adapter->rx_fc);
9b0365f1 3038 be_clear(adapter);
6b7c5b94 3039
a4ca055f 3040 be_msix_disable(adapter);
6b7c5b94
SP		 3041 pci_save_state(pdev);
3042 pci_disable_device(pdev);
3043 pci_set_power_state(pdev, pci_choose_state(pdev, state));
3044 return 0;
3045}
3046
3047static int be_resume(struct pci_dev *pdev)
3048{
3049 int status = 0;
3050 struct be_adapter *adapter = pci_get_drvdata(pdev);
3051 struct net_device *netdev = adapter->netdev;
3052
3053 netif_device_detach(netdev);
3054
3055 status = pci_enable_device(pdev);
3056 if (status)
3057 return status;
3058
3059 pci_set_power_state(pdev, 0);
3060 pci_restore_state(pdev);
3061
a4ca055f 3062 be_msix_enable(adapter);
2243e2e9
SP		 3063 /* tell fw we're ready to fire cmds */
3064 status = be_cmd_fw_init(adapter);
3065 if (status)
3066 return status;
3067
9b0365f1 3068 be_setup(adapter);
6b7c5b94
SP		 3069 if (netif_running(netdev)) {
3070 rtnl_lock();
3071 be_open(netdev);
3072 rtnl_unlock();
3073 }
3074 netif_device_attach(netdev);
71d8d1b5
AK		 3075
3076 if (adapter->wol)
3077 be_setup_wol(adapter, false);
a4ca055f
AK		 3078
3079 schedule_delayed_work(&adapter->work, msecs_to_jiffies(100));
6b7c5b94
SP		 3080 return 0;
3081}
3082
82456b03
SP		 3083/*
3084 * An FLR will stop BE from DMAing any data.
3085 */
3086static void be_shutdown(struct pci_dev *pdev)
3087{
3088 struct be_adapter *adapter = pci_get_drvdata(pdev);
3089 struct net_device *netdev = adapter->netdev;
3090
a4ca055f
AK		 3091 if (netif_running(netdev))
3092 cancel_delayed_work_sync(&adapter->work);
3093
82456b03
SP		 3094 netif_device_detach(netdev);
3095
3096 be_cmd_reset_function(adapter);
3097
3098 if (adapter->wol)
3099 be_setup_wol(adapter, true);
3100
3101 pci_disable_device(pdev);
82456b03
SP		 3102}
3103
cf588477
SP		 3104static pci_ers_result_t be_eeh_err_detected(struct pci_dev *pdev,
3105 pci_channel_state_t state)
3106{
3107 struct be_adapter *adapter = pci_get_drvdata(pdev);
3108 struct net_device *netdev = adapter->netdev;
3109
3110 dev_err(&adapter->pdev->dev, "EEH error detected\n");
3111
3112 adapter->eeh_err = true;
3113
3114 netif_device_detach(netdev);
3115
3116 if (netif_running(netdev)) {
3117 rtnl_lock();
3118 be_close(netdev);
3119 rtnl_unlock();
3120 }
3121 be_clear(adapter);
3122
3123 if (state == pci_channel_io_perm_failure)
3124 return PCI_ERS_RESULT_DISCONNECT;
3125
3126 pci_disable_device(pdev);
3127
3128 return PCI_ERS_RESULT_NEED_RESET;
3129}
3130
3131static pci_ers_result_t be_eeh_reset(struct pci_dev *pdev)
3132{
3133 struct be_adapter *adapter = pci_get_drvdata(pdev);
3134 int status;
3135
3136 dev_info(&adapter->pdev->dev, "EEH reset\n");
3137 adapter->eeh_err = false;
3138
3139 status = pci_enable_device(pdev);
3140 if (status)
3141 return PCI_ERS_RESULT_DISCONNECT;
3142
3143 pci_set_master(pdev);
3144 pci_set_power_state(pdev, 0);
3145 pci_restore_state(pdev);
3146
3147 /* Check if card is ok and fw is ready */
3148 status = be_cmd_POST(adapter);
3149 if (status)
3150 return PCI_ERS_RESULT_DISCONNECT;
3151
3152 return PCI_ERS_RESULT_RECOVERED;
3153}
3154
3155static void be_eeh_resume(struct pci_dev *pdev)
3156{
3157 int status = 0;
3158 struct be_adapter *adapter = pci_get_drvdata(pdev);
3159 struct net_device *netdev = adapter->netdev;
3160
3161 dev_info(&adapter->pdev->dev, "EEH resume\n");
3162
3163 pci_save_state(pdev);
3164
3165 /* tell fw we're ready to fire cmds */
3166 status = be_cmd_fw_init(adapter);
3167 if (status)
3168 goto err;
3169
3170 status = be_setup(adapter);
3171 if (status)
3172 goto err;
3173
3174 if (netif_running(netdev)) {
3175 status = be_open(netdev);
3176 if (status)
3177 goto err;
3178 }
3179 netif_device_attach(netdev);
3180 return;
3181err:
3182 dev_err(&adapter->pdev->dev, "EEH resume failed\n");
cf588477
SP		 3183}
3184
3185static struct pci_error_handlers be_eeh_handlers = {
3186 .error_detected = be_eeh_err_detected,
3187 .slot_reset = be_eeh_reset,
3188 .resume = be_eeh_resume,
3189};
3190
6b7c5b94
SP		 3191static struct pci_driver be_driver = {
3192 .name = DRV_NAME,
3193 .id_table = be_dev_ids,
3194 .probe = be_probe,
3195 .remove = be_remove,
3196 .suspend = be_suspend,
cf588477 3197 .resume = be_resume,
82456b03 3198 .shutdown = be_shutdown,
cf588477 3199 .err_handler = &be_eeh_handlers
6b7c5b94
SP		 3200};
3201
3202static int __init be_init_module(void)
3203{
8e95a202
JP		 3204 if (rx_frag_size != 8192 && rx_frag_size != 4096 &&
3205 rx_frag_size != 2048) {
6b7c5b94
SP		 3206 printk(KERN_WARNING DRV_NAME
3207 " : Module param rx_frag_size must be 2048/4096/8192."
3208 " Using 2048\n");
3209 rx_frag_size = 2048;
3210 }
6b7c5b94 3211
ba343c77
SB		 3212 if (num_vfs > 32) {
3213 printk(KERN_WARNING DRV_NAME
3214 " : Module param num_vfs must not be greater than 32."
3215 "Using 32\n");
3216 num_vfs = 32;
3217 }
3218
6b7c5b94
SP		 3219 return pci_register_driver(&be_driver);
3220}
3221module_init(be_init_module);
3222
3223static void __exit be_exit_module(void)
3224{
3225 pci_unregister_driver(&be_driver);
3226}
3227module_exit(be_exit_module);
Linux kernel - Deliverables
This page took 0.403307 seconds and 5 git commands to generate.