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be2net: change to call pmac_del only if necessary
[deliverable/linux.git] / drivers / net / benet / be_main.c
CommitLineData
6b7c5b94 1/*
294aedcf 2 * Copyright (C) 2005 - 2010 ServerEngines
6b7c5b94
SP		 3 * All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License version 2
7 * as published by the Free Software Foundation. The full GNU General
8 * Public License is included in this distribution in the file called COPYING.
9 *
10 * Contact Information:
11 * linux-drivers@serverengines.com
12 *
13 * ServerEngines
14 * 209 N. Fair Oaks Ave
15 * Sunnyvale, CA 94085
16 */
17
18#include "be.h"
8788fdc2 19#include "be_cmds.h"
65f71b8b 20#include <asm/div64.h>
6b7c5b94
SP		 21
22MODULE_VERSION(DRV_VER);
23MODULE_DEVICE_TABLE(pci, be_dev_ids);
24MODULE_DESCRIPTION(DRV_DESC " " DRV_VER);
25MODULE_AUTHOR("ServerEngines Corporation");
26MODULE_LICENSE("GPL");
27
28static unsigned int rx_frag_size = 2048;
ba343c77 29static unsigned int num_vfs;
6b7c5b94 30module_param(rx_frag_size, uint, S_IRUGO);
ba343c77 31module_param(num_vfs, uint, S_IRUGO);
6b7c5b94 32MODULE_PARM_DESC(rx_frag_size, "Size of a fragment that holds rcvd data.");
ba343c77 33MODULE_PARM_DESC(num_vfs, "Number of PCI VFs to initialize");
6b7c5b94 34
6b7c5b94 35static DEFINE_PCI_DEVICE_TABLE(be_dev_ids) = {
c4ca2374 36 { PCI_DEVICE(BE_VENDOR_ID, BE_DEVICE_ID1) },
59fd5d87 37 { PCI_DEVICE(BE_VENDOR_ID, BE_DEVICE_ID2) },
c4ca2374
AK		 38 { PCI_DEVICE(BE_VENDOR_ID, OC_DEVICE_ID1) },
39 { PCI_DEVICE(BE_VENDOR_ID, OC_DEVICE_ID2) },
6b7c5b94
SP		 40 { 0 }
41};
42MODULE_DEVICE_TABLE(pci, be_dev_ids);
43
44static void be_queue_free(struct be_adapter *adapter, struct be_queue_info *q)
45{
46 struct be_dma_mem *mem = &q->dma_mem;
47 if (mem->va)
48 pci_free_consistent(adapter->pdev, mem->size,
49 mem->va, mem->dma);
50}
51
52static int be_queue_alloc(struct be_adapter *adapter, struct be_queue_info *q,
53 u16 len, u16 entry_size)
54{
55 struct be_dma_mem *mem = &q->dma_mem;
56
57 memset(q, 0, sizeof(*q));
58 q->len = len;
59 q->entry_size = entry_size;
60 mem->size = len * entry_size;
61 mem->va = pci_alloc_consistent(adapter->pdev, mem->size, &mem->dma);
62 if (!mem->va)
63 return -1;
64 memset(mem->va, 0, mem->size);
65 return 0;
66}
67
8788fdc2 68static void be_intr_set(struct be_adapter *adapter, bool enable)
6b7c5b94 69{
8788fdc2 70 u8 __iomem *addr = adapter->pcicfg + PCICFG_MEMBAR_CTRL_INT_CTRL_OFFSET;
6b7c5b94
SP		 71 u32 reg = ioread32(addr);
72 u32 enabled = reg & MEMBAR_CTRL_INT_CTRL_HOSTINTR_MASK;
5f0b849e 73
cf588477
SP		 74 if (adapter->eeh_err)
75 return;
76
5f0b849e 77 if (!enabled && enable)
6b7c5b94 78 reg |= MEMBAR_CTRL_INT_CTRL_HOSTINTR_MASK;
5f0b849e 79 else if (enabled && !enable)
6b7c5b94 80 reg &= ~MEMBAR_CTRL_INT_CTRL_HOSTINTR_MASK;
5f0b849e 81 else
6b7c5b94 82 return;
5f0b849e 83
6b7c5b94
SP		 84 iowrite32(reg, addr);
85}
86
8788fdc2 87static void be_rxq_notify(struct be_adapter *adapter, u16 qid, u16 posted)
6b7c5b94
SP		 88{
89 u32 val = 0;
90 val |= qid & DB_RQ_RING_ID_MASK;
91 val |= posted << DB_RQ_NUM_POSTED_SHIFT;
f3eb62d2
SP		 92
93 wmb();
8788fdc2 94 iowrite32(val, adapter->db + DB_RQ_OFFSET);
6b7c5b94
SP		 95}
96
8788fdc2 97static void be_txq_notify(struct be_adapter *adapter, u16 qid, u16 posted)
6b7c5b94
SP		 98{
99 u32 val = 0;
100 val |= qid & DB_TXULP_RING_ID_MASK;
101 val |= (posted & DB_TXULP_NUM_POSTED_MASK) << DB_TXULP_NUM_POSTED_SHIFT;
f3eb62d2
SP		 102
103 wmb();
8788fdc2 104 iowrite32(val, adapter->db + DB_TXULP1_OFFSET);
6b7c5b94
SP		 105}
106
8788fdc2 107static void be_eq_notify(struct be_adapter *adapter, u16 qid,
6b7c5b94
SP		 108 bool arm, bool clear_int, u16 num_popped)
109{
110 u32 val = 0;
111 val |= qid & DB_EQ_RING_ID_MASK;
cf588477
SP		 112
113 if (adapter->eeh_err)
114 return;
115
6b7c5b94
SP		 116 if (arm)
117 val |= 1 << DB_EQ_REARM_SHIFT;
118 if (clear_int)
119 val |= 1 << DB_EQ_CLR_SHIFT;
120 val |= 1 << DB_EQ_EVNT_SHIFT;
121 val |= num_popped << DB_EQ_NUM_POPPED_SHIFT;
8788fdc2 122 iowrite32(val, adapter->db + DB_EQ_OFFSET);
6b7c5b94
SP		 123}
124
8788fdc2 125void be_cq_notify(struct be_adapter *adapter, u16 qid, bool arm, u16 num_popped)
6b7c5b94
SP		 126{
127 u32 val = 0;
128 val |= qid & DB_CQ_RING_ID_MASK;
cf588477
SP		 129
130 if (adapter->eeh_err)
131 return;
132
6b7c5b94
SP		 133 if (arm)
134 val |= 1 << DB_CQ_REARM_SHIFT;
135 val |= num_popped << DB_CQ_NUM_POPPED_SHIFT;
8788fdc2 136 iowrite32(val, adapter->db + DB_CQ_OFFSET);
6b7c5b94
SP		 137}
138
6b7c5b94
SP		 139static int be_mac_addr_set(struct net_device *netdev, void *p)
140{
141 struct be_adapter *adapter = netdev_priv(netdev);
142 struct sockaddr *addr = p;
143 int status = 0;
144
ca9e4988
AK		 145 if (!is_valid_ether_addr(addr->sa_data))
146 return -EADDRNOTAVAIL;
147
ba343c77
SB		 148 /* MAC addr configuration will be done in hardware for VFs
149 * by their corresponding PFs. Just copy to netdev addr here
150 */
151 if (!be_physfn(adapter))
152 goto netdev_addr;
153
a65027e4
SP		 154 status = be_cmd_pmac_del(adapter, adapter->if_handle, adapter->pmac_id);
155 if (status)
156 return status;
6b7c5b94 157
a65027e4
SP		 158 status = be_cmd_pmac_add(adapter, (u8 *)addr->sa_data,
159 adapter->if_handle, &adapter->pmac_id);
ba343c77 160netdev_addr:
6b7c5b94
SP		 161 if (!status)
162 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
163
164 return status;
165}
166
b31c50a7 167void netdev_stats_update(struct be_adapter *adapter)
6b7c5b94
SP		 168{
169 struct be_hw_stats *hw_stats = hw_stats_from_cmd(adapter->stats.cmd.va);
170 struct be_rxf_stats *rxf_stats = &hw_stats->rxf;
171 struct be_port_rxf_stats *port_stats =
172 &rxf_stats->port[adapter->port_num];
78122a52 173 struct net_device_stats *dev_stats = &adapter->netdev->stats;
68110868 174 struct be_erx_stats *erx_stats = &hw_stats->erx;
6b7c5b94 175
91992e44
AK		 176 dev_stats->rx_packets = drvr_stats(adapter)->be_rx_pkts;
177 dev_stats->tx_packets = drvr_stats(adapter)->be_tx_pkts;
178 dev_stats->rx_bytes = drvr_stats(adapter)->be_rx_bytes;
179 dev_stats->tx_bytes = drvr_stats(adapter)->be_tx_bytes;
6b7c5b94
SP		 180
181 /* bad pkts received */
182 dev_stats->rx_errors = port_stats->rx_crc_errors +
183 port_stats->rx_alignment_symbol_errors +
184 port_stats->rx_in_range_errors +
68110868
SP		 185 port_stats->rx_out_range_errors +
186 port_stats->rx_frame_too_long +
187 port_stats->rx_dropped_too_small +
188 port_stats->rx_dropped_too_short +
189 port_stats->rx_dropped_header_too_small +
190 port_stats->rx_dropped_tcp_length +
191 port_stats->rx_dropped_runt +
192 port_stats->rx_tcp_checksum_errs +
193 port_stats->rx_ip_checksum_errs +
194 port_stats->rx_udp_checksum_errs;
195
196 /* no space in linux buffers: best possible approximation */
01ed30da
SP		 197 dev_stats->rx_dropped =
198 erx_stats->rx_drops_no_fragments[adapter->rx_obj.q.id];
6b7c5b94
SP		 199
200 /* detailed rx errors */
201 dev_stats->rx_length_errors = port_stats->rx_in_range_errors +
68110868
SP		 202 port_stats->rx_out_range_errors +
203 port_stats->rx_frame_too_long;
204
6b7c5b94
SP		 205 /* receive ring buffer overflow */
206 dev_stats->rx_over_errors = 0;
68110868 207
6b7c5b94
SP		 208 dev_stats->rx_crc_errors = port_stats->rx_crc_errors;
209
210 /* frame alignment errors */
211 dev_stats->rx_frame_errors = port_stats->rx_alignment_symbol_errors;
68110868 212
6b7c5b94
SP		 213 /* receiver fifo overrun */
214 /* drops_no_pbuf is no per i/f, it's per BE card */
215 dev_stats->rx_fifo_errors = port_stats->rx_fifo_overflow +
216 port_stats->rx_input_fifo_overflow +
217 rxf_stats->rx_drops_no_pbuf;
218 /* receiver missed packetd */
219 dev_stats->rx_missed_errors = 0;
68110868
SP		 220
221 /* packet transmit problems */
222 dev_stats->tx_errors = 0;
223
224 /* no space available in linux */
225 dev_stats->tx_dropped = 0;
226
c5b9b92e 227 dev_stats->multicast = port_stats->rx_multicast_frames;
68110868
SP		 228 dev_stats->collisions = 0;
229
6b7c5b94
SP		 230 /* detailed tx_errors */
231 dev_stats->tx_aborted_errors = 0;
232 dev_stats->tx_carrier_errors = 0;
233 dev_stats->tx_fifo_errors = 0;
234 dev_stats->tx_heartbeat_errors = 0;
235 dev_stats->tx_window_errors = 0;
236}
237
8788fdc2 238void be_link_status_update(struct be_adapter *adapter, bool link_up)
6b7c5b94 239{
6b7c5b94
SP		 240 struct net_device *netdev = adapter->netdev;
241
6b7c5b94 242 /* If link came up or went down */
a8f447bd 243 if (adapter->link_up != link_up) {
0dffc83e 244 adapter->link_speed = -1;
a8f447bd 245 if (link_up) {
6b7c5b94
SP		 246 netif_start_queue(netdev);
247 netif_carrier_on(netdev);
248 printk(KERN_INFO "%s: Link up\n", netdev->name);
a8f447bd
SP		 249 } else {
250 netif_stop_queue(netdev);
251 netif_carrier_off(netdev);
252 printk(KERN_INFO "%s: Link down\n", netdev->name);
6b7c5b94 253 }
a8f447bd 254 adapter->link_up = link_up;
6b7c5b94 255 }
6b7c5b94
SP		 256}
257
258/* Update the EQ delay n BE based on the RX frags consumed / sec */
259static void be_rx_eqd_update(struct be_adapter *adapter)
260{
6b7c5b94
SP		 261 struct be_eq_obj *rx_eq = &adapter->rx_eq;
262 struct be_drvr_stats *stats = &adapter->stats.drvr_stats;
4097f663
SP		 263 ulong now = jiffies;
264 u32 eqd;
265
266 if (!rx_eq->enable_aic)
267 return;
268
269 /* Wrapped around */
270 if (time_before(now, stats->rx_fps_jiffies)) {
271 stats->rx_fps_jiffies = now;
272 return;
273 }
6b7c5b94
SP		 274
275 /* Update once a second */
4097f663 276 if ((now - stats->rx_fps_jiffies) < HZ)
6b7c5b94
SP		 277 return;
278
279 stats->be_rx_fps = (stats->be_rx_frags - stats->be_prev_rx_frags) /
4097f663 280 ((now - stats->rx_fps_jiffies) / HZ);
6b7c5b94 281
4097f663 282 stats->rx_fps_jiffies = now;
6b7c5b94
SP		 283 stats->be_prev_rx_frags = stats->be_rx_frags;
284 eqd = stats->be_rx_fps / 110000;
285 eqd = eqd << 3;
286 if (eqd > rx_eq->max_eqd)
287 eqd = rx_eq->max_eqd;
288 if (eqd < rx_eq->min_eqd)
289 eqd = rx_eq->min_eqd;
290 if (eqd < 10)
291 eqd = 0;
292 if (eqd != rx_eq->cur_eqd)
8788fdc2 293 be_cmd_modify_eqd(adapter, rx_eq->q.id, eqd);
6b7c5b94
SP		 294
295 rx_eq->cur_eqd = eqd;
296}
297
6b7c5b94
SP		 298static struct net_device_stats *be_get_stats(struct net_device *dev)
299{
78122a52 300 return &dev->stats;
6b7c5b94
SP		 301}
302
65f71b8b
SH		 303static u32 be_calc_rate(u64 bytes, unsigned long ticks)
304{
305 u64 rate = bytes;
306
307 do_div(rate, ticks / HZ);
308 rate <<= 3; /* bytes/sec -> bits/sec */
309 do_div(rate, 1000000ul); /* MB/Sec */
310
311 return rate;
312}
313
4097f663
SP		 314static void be_tx_rate_update(struct be_adapter *adapter)
315{
316 struct be_drvr_stats *stats = drvr_stats(adapter);
317 ulong now = jiffies;
318
319 /* Wrapped around? */
320 if (time_before(now, stats->be_tx_jiffies)) {
321 stats->be_tx_jiffies = now;
322 return;
323 }
324
325 /* Update tx rate once in two seconds */
326 if ((now - stats->be_tx_jiffies) > 2 * HZ) {
65f71b8b
SH		 327 stats->be_tx_rate = be_calc_rate(stats->be_tx_bytes
328 - stats->be_tx_bytes_prev,
329 now - stats->be_tx_jiffies);
4097f663
SP		 330 stats->be_tx_jiffies = now;
331 stats->be_tx_bytes_prev = stats->be_tx_bytes;
332 }
333}
334
6b7c5b94 335static void be_tx_stats_update(struct be_adapter *adapter,
91992e44 336 u32 wrb_cnt, u32 copied, u32 gso_segs, bool stopped)
6b7c5b94 337{
4097f663 338 struct be_drvr_stats *stats = drvr_stats(adapter);
6b7c5b94
SP		 339 stats->be_tx_reqs++;
340 stats->be_tx_wrbs += wrb_cnt;
341 stats->be_tx_bytes += copied;
91992e44 342 stats->be_tx_pkts += (gso_segs ? gso_segs : 1);
6b7c5b94
SP		 343 if (stopped)
344 stats->be_tx_stops++;
6b7c5b94
SP		 345}
346
347/* Determine number of WRB entries needed to xmit data in an skb */
348static u32 wrb_cnt_for_skb(struct sk_buff *skb, bool *dummy)
349{
ebc8d2ab
DM		 350 int cnt = (skb->len > skb->data_len);
351
352 cnt += skb_shinfo(skb)->nr_frags;
353
6b7c5b94
SP		 354 /* to account for hdr wrb */
355 cnt++;
356 if (cnt & 1) {
357 /* add a dummy to make it an even num */
358 cnt++;
359 *dummy = true;
360 } else
361 *dummy = false;
362 BUG_ON(cnt > BE_MAX_TX_FRAG_COUNT);
363 return cnt;
364}
365
366static inline void wrb_fill(struct be_eth_wrb *wrb, u64 addr, int len)
367{
368 wrb->frag_pa_hi = upper_32_bits(addr);
369 wrb->frag_pa_lo = addr & 0xFFFFFFFF;
370 wrb->frag_len = len & ETH_WRB_FRAG_LEN_MASK;
371}
372
373static void wrb_fill_hdr(struct be_eth_hdr_wrb *hdr, struct sk_buff *skb,
374 bool vlan, u32 wrb_cnt, u32 len)
375{
376 memset(hdr, 0, sizeof(*hdr));
377
378 AMAP_SET_BITS(struct amap_eth_hdr_wrb, crc, hdr, 1);
379
49e4b847 380 if (skb_is_gso(skb)) {
6b7c5b94
SP		 381 AMAP_SET_BITS(struct amap_eth_hdr_wrb, lso, hdr, 1);
382 AMAP_SET_BITS(struct amap_eth_hdr_wrb, lso_mss,
383 hdr, skb_shinfo(skb)->gso_size);
49e4b847
AK		 384 if (skb_is_gso_v6(skb))
385 AMAP_SET_BITS(struct amap_eth_hdr_wrb, lso6, hdr, 1);
6b7c5b94
SP		 386 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
387 if (is_tcp_pkt(skb))
388 AMAP_SET_BITS(struct amap_eth_hdr_wrb, tcpcs, hdr, 1);
389 else if (is_udp_pkt(skb))
390 AMAP_SET_BITS(struct amap_eth_hdr_wrb, udpcs, hdr, 1);
391 }
392
393 if (vlan && vlan_tx_tag_present(skb)) {
394 AMAP_SET_BITS(struct amap_eth_hdr_wrb, vlan, hdr, 1);
395 AMAP_SET_BITS(struct amap_eth_hdr_wrb, vlan_tag,
396 hdr, vlan_tx_tag_get(skb));
397 }
398
399 AMAP_SET_BITS(struct amap_eth_hdr_wrb, event, hdr, 1);
400 AMAP_SET_BITS(struct amap_eth_hdr_wrb, complete, hdr, 1);
401 AMAP_SET_BITS(struct amap_eth_hdr_wrb, num_wrb, hdr, wrb_cnt);
402 AMAP_SET_BITS(struct amap_eth_hdr_wrb, len, hdr, len);
403}
404
7101e111
SP		 405static void unmap_tx_frag(struct pci_dev *pdev, struct be_eth_wrb *wrb,
406 bool unmap_single)
407{
408 dma_addr_t dma;
409
410 be_dws_le_to_cpu(wrb, sizeof(*wrb));
411
412 dma = (u64)wrb->frag_pa_hi << 32 | (u64)wrb->frag_pa_lo;
b681ee77 413 if (wrb->frag_len) {
7101e111
SP		 414 if (unmap_single)
415 pci_unmap_single(pdev, dma, wrb->frag_len,
416 PCI_DMA_TODEVICE);
417 else
418 pci_unmap_page(pdev, dma, wrb->frag_len,
419 PCI_DMA_TODEVICE);
420 }
421}
6b7c5b94
SP		 422
423static int make_tx_wrbs(struct be_adapter *adapter,
424 struct sk_buff *skb, u32 wrb_cnt, bool dummy_wrb)
425{
7101e111
SP		 426 dma_addr_t busaddr;
427 int i, copied = 0;
6b7c5b94
SP		 428 struct pci_dev *pdev = adapter->pdev;
429 struct sk_buff *first_skb = skb;
430 struct be_queue_info *txq = &adapter->tx_obj.q;
431 struct be_eth_wrb *wrb;
432 struct be_eth_hdr_wrb *hdr;
7101e111
SP		 433 bool map_single = false;
434 u16 map_head;
6b7c5b94 435
6b7c5b94
SP		 436 hdr = queue_head_node(txq);
437 queue_head_inc(txq);
7101e111 438 map_head = txq->head;
6b7c5b94 439
ebc8d2ab 440 if (skb->len > skb->data_len) {
e743d313 441 int len = skb_headlen(skb);
a73b796e
AD		 442 busaddr = pci_map_single(pdev, skb->data, len,
443 PCI_DMA_TODEVICE);
7101e111
SP		 444 if (pci_dma_mapping_error(pdev, busaddr))
445 goto dma_err;
446 map_single = true;
ebc8d2ab
DM		 447 wrb = queue_head_node(txq);
448 wrb_fill(wrb, busaddr, len);
449 be_dws_cpu_to_le(wrb, sizeof(*wrb));
450 queue_head_inc(txq);
451 copied += len;
452 }
6b7c5b94 453
ebc8d2ab
DM		 454 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
455 struct skb_frag_struct *frag =
456 &skb_shinfo(skb)->frags[i];
a73b796e
AD		 457 busaddr = pci_map_page(pdev, frag->page,
458 frag->page_offset,
459 frag->size, PCI_DMA_TODEVICE);
7101e111
SP		 460 if (pci_dma_mapping_error(pdev, busaddr))
461 goto dma_err;
ebc8d2ab
DM		 462 wrb = queue_head_node(txq);
463 wrb_fill(wrb, busaddr, frag->size);
464 be_dws_cpu_to_le(wrb, sizeof(*wrb));
465 queue_head_inc(txq);
466 copied += frag->size;
6b7c5b94
SP		 467 }
468
469 if (dummy_wrb) {
470 wrb = queue_head_node(txq);
471 wrb_fill(wrb, 0, 0);
472 be_dws_cpu_to_le(wrb, sizeof(*wrb));
473 queue_head_inc(txq);
474 }
475
476 wrb_fill_hdr(hdr, first_skb, adapter->vlan_grp ? true : false,
477 wrb_cnt, copied);
478 be_dws_cpu_to_le(hdr, sizeof(*hdr));
479
480 return copied;
7101e111
SP		 481dma_err:
482 txq->head = map_head;
483 while (copied) {
484 wrb = queue_head_node(txq);
485 unmap_tx_frag(pdev, wrb, map_single);
486 map_single = false;
487 copied -= wrb->frag_len;
488 queue_head_inc(txq);
489 }
490 return 0;
6b7c5b94
SP		 491}
492
61357325 493static netdev_tx_t be_xmit(struct sk_buff *skb,
b31c50a7 494 struct net_device *netdev)
6b7c5b94
SP		 495{
496 struct be_adapter *adapter = netdev_priv(netdev);
497 struct be_tx_obj *tx_obj = &adapter->tx_obj;
498 struct be_queue_info *txq = &tx_obj->q;
499 u32 wrb_cnt = 0, copied = 0;
500 u32 start = txq->head;
501 bool dummy_wrb, stopped = false;
502
503 wrb_cnt = wrb_cnt_for_skb(skb, &dummy_wrb);
504
505 copied = make_tx_wrbs(adapter, skb, wrb_cnt, dummy_wrb);
c190e3c8
AK		 506 if (copied) {
507 /* record the sent skb in the sent_skb table */
508 BUG_ON(tx_obj->sent_skb_list[start]);
509 tx_obj->sent_skb_list[start] = skb;
510
511 /* Ensure txq has space for the next skb; Else stop the queue
512 * *BEFORE* ringing the tx doorbell, so that we serialze the
513 * tx compls of the current transmit which'll wake up the queue
514 */
7101e111 515 atomic_add(wrb_cnt, &txq->used);
c190e3c8
AK		 516 if ((BE_MAX_TX_FRAG_COUNT + atomic_read(&txq->used)) >=
517 txq->len) {
518 netif_stop_queue(netdev);
519 stopped = true;
520 }
6b7c5b94 521
c190e3c8 522 be_txq_notify(adapter, txq->id, wrb_cnt);
6b7c5b94 523
91992e44
AK		 524 be_tx_stats_update(adapter, wrb_cnt, copied,
525 skb_shinfo(skb)->gso_segs, stopped);
c190e3c8
AK		 526 } else {
527 txq->head = start;
528 dev_kfree_skb_any(skb);
6b7c5b94 529 }
6b7c5b94
SP		 530 return NETDEV_TX_OK;
531}
532
533static int be_change_mtu(struct net_device *netdev, int new_mtu)
534{
535 struct be_adapter *adapter = netdev_priv(netdev);
536 if (new_mtu < BE_MIN_MTU ||
34a89b8c
AK		 537 new_mtu > (BE_MAX_JUMBO_FRAME_SIZE -
538 (ETH_HLEN + ETH_FCS_LEN))) {
6b7c5b94
SP		 539 dev_info(&adapter->pdev->dev,
540 "MTU must be between %d and %d bytes\n",
34a89b8c
AK		 541 BE_MIN_MTU,
542 (BE_MAX_JUMBO_FRAME_SIZE - (ETH_HLEN + ETH_FCS_LEN)));
6b7c5b94
SP		 543 return -EINVAL;
544 }
545 dev_info(&adapter->pdev->dev, "MTU changed from %d to %d bytes\n",
546 netdev->mtu, new_mtu);
547 netdev->mtu = new_mtu;
548 return 0;
549}
550
551/*
82903e4b
AK		 552 * A max of 64 (BE_NUM_VLANS_SUPPORTED) vlans can be configured in BE.
553 * If the user configures more, place BE in vlan promiscuous mode.
6b7c5b94 554 */
b31c50a7 555static int be_vid_config(struct be_adapter *adapter)
6b7c5b94 556{
6b7c5b94
SP		 557 u16 vtag[BE_NUM_VLANS_SUPPORTED];
558 u16 ntags = 0, i;
82903e4b 559 int status = 0;
6b7c5b94 560
82903e4b 561 if (adapter->vlans_added <= adapter->max_vlans) {
6b7c5b94
SP		 562 /* Construct VLAN Table to give to HW */
563 for (i = 0; i < VLAN_GROUP_ARRAY_LEN; i++) {
564 if (adapter->vlan_tag[i]) {
565 vtag[ntags] = cpu_to_le16(i);
566 ntags++;
567 }
568 }
b31c50a7
SP		 569 status = be_cmd_vlan_config(adapter, adapter->if_handle,
570 vtag, ntags, 1, 0);
6b7c5b94 571 } else {
b31c50a7
SP		 572 status = be_cmd_vlan_config(adapter, adapter->if_handle,
573 NULL, 0, 1, 1);
6b7c5b94 574 }
b31c50a7 575 return status;
6b7c5b94
SP		 576}
577
578static void be_vlan_register(struct net_device *netdev, struct vlan_group *grp)
579{
580 struct be_adapter *adapter = netdev_priv(netdev);
581 struct be_eq_obj *rx_eq = &adapter->rx_eq;
582 struct be_eq_obj *tx_eq = &adapter->tx_eq;
6b7c5b94 583
8788fdc2
SP		 584 be_eq_notify(adapter, rx_eq->q.id, false, false, 0);
585 be_eq_notify(adapter, tx_eq->q.id, false, false, 0);
6b7c5b94 586 adapter->vlan_grp = grp;
8788fdc2
SP		 587 be_eq_notify(adapter, rx_eq->q.id, true, false, 0);
588 be_eq_notify(adapter, tx_eq->q.id, true, false, 0);
6b7c5b94
SP		 589}
590
591static void be_vlan_add_vid(struct net_device *netdev, u16 vid)
592{
593 struct be_adapter *adapter = netdev_priv(netdev);
594
ba343c77
SB		 595 if (!be_physfn(adapter))
596 return;
597
6b7c5b94 598 adapter->vlan_tag[vid] = 1;
82903e4b
AK		 599 adapter->vlans_added++;
600 if (adapter->vlans_added <= (adapter->max_vlans + 1))
601 be_vid_config(adapter);
6b7c5b94
SP		 602}
603
604static void be_vlan_rem_vid(struct net_device *netdev, u16 vid)
605{
606 struct be_adapter *adapter = netdev_priv(netdev);
607
ba343c77
SB		 608 if (!be_physfn(adapter))
609 return;
610
6b7c5b94 611 adapter->vlan_tag[vid] = 0;
6b7c5b94 612 vlan_group_set_device(adapter->vlan_grp, vid, NULL);
82903e4b
AK		 613 adapter->vlans_added--;
614 if (adapter->vlans_added <= adapter->max_vlans)
615 be_vid_config(adapter);
6b7c5b94
SP		 616}
617
24307eef 618static void be_set_multicast_list(struct net_device *netdev)
6b7c5b94
SP		 619{
620 struct be_adapter *adapter = netdev_priv(netdev);
6b7c5b94 621
24307eef 622 if (netdev->flags & IFF_PROMISC) {
8788fdc2 623 be_cmd_promiscuous_config(adapter, adapter->port_num, 1);
24307eef
SP		 624 adapter->promiscuous = true;
625 goto done;
6b7c5b94
SP		 626 }
627
24307eef
SP		 628 /* BE was previously in promiscous mode; disable it */
629 if (adapter->promiscuous) {
630 adapter->promiscuous = false;
8788fdc2 631 be_cmd_promiscuous_config(adapter, adapter->port_num, 0);
6b7c5b94
SP		 632 }
633
e7b909a6 634 /* Enable multicast promisc if num configured exceeds what we support */
4cd24eaf
JP		 635 if (netdev->flags & IFF_ALLMULTI ||
636 netdev_mc_count(netdev) > BE_MAX_MC) {
0ddf477b 637 be_cmd_multicast_set(adapter, adapter->if_handle, NULL,
e7b909a6 638 &adapter->mc_cmd_mem);
24307eef 639 goto done;
6b7c5b94 640 }
6b7c5b94 641
0ddf477b 642 be_cmd_multicast_set(adapter, adapter->if_handle, netdev,
f31e50a8 643 &adapter->mc_cmd_mem);
24307eef
SP		 644done:
645 return;
6b7c5b94
SP		 646}
647
ba343c77
SB		 648static int be_set_vf_mac(struct net_device *netdev, int vf, u8 *mac)
649{
650 struct be_adapter *adapter = netdev_priv(netdev);
651 int status;
652
653 if (!adapter->sriov_enabled)
654 return -EPERM;
655
656 if (!is_valid_ether_addr(mac) || (vf >= num_vfs))
657 return -EINVAL;
658
9cd9000b
AK		 659 if (adapter->vf_pmac_id[vf] != BE_INVALID_PMAC_ID)
660 status = be_cmd_pmac_del(adapter, adapter->vf_if_handle[vf],
661 adapter->vf_pmac_id[vf]);
ba343c77
SB		 662
663 status = be_cmd_pmac_add(adapter, mac, adapter->vf_if_handle[vf],
664 &adapter->vf_pmac_id[vf]);
665 if (!status)
666 dev_err(&adapter->pdev->dev, "MAC %pM set on VF %d Failed\n",
667 mac, vf);
668 return status;
669}
670
4097f663 671static void be_rx_rate_update(struct be_adapter *adapter)
6b7c5b94 672{
4097f663
SP		 673 struct be_drvr_stats *stats = drvr_stats(adapter);
674 ulong now = jiffies;
6b7c5b94 675
4097f663
SP		 676 /* Wrapped around */
677 if (time_before(now, stats->be_rx_jiffies)) {
678 stats->be_rx_jiffies = now;
679 return;
680 }
6b7c5b94
SP		 681
682 /* Update the rate once in two seconds */
4097f663 683 if ((now - stats->be_rx_jiffies) < 2 * HZ)
6b7c5b94
SP		 684 return;
685
65f71b8b
SH		 686 stats->be_rx_rate = be_calc_rate(stats->be_rx_bytes
687 - stats->be_rx_bytes_prev,
688 now - stats->be_rx_jiffies);
4097f663 689 stats->be_rx_jiffies = now;
6b7c5b94
SP		 690 stats->be_rx_bytes_prev = stats->be_rx_bytes;
691}
692
4097f663
SP		 693static void be_rx_stats_update(struct be_adapter *adapter,
694 u32 pktsize, u16 numfrags)
695{
696 struct be_drvr_stats *stats = drvr_stats(adapter);
697
698 stats->be_rx_compl++;
699 stats->be_rx_frags += numfrags;
700 stats->be_rx_bytes += pktsize;
91992e44 701 stats->be_rx_pkts++;
4097f663
SP		 702}
703
728a9972
AK		 704static inline bool do_pkt_csum(struct be_eth_rx_compl *rxcp, bool cso)
705{
706 u8 l4_cksm, ip_version, ipcksm, tcpf = 0, udpf = 0, ipv6_chk;
707
708 l4_cksm = AMAP_GET_BITS(struct amap_eth_rx_compl, l4_cksm, rxcp);
709 ipcksm = AMAP_GET_BITS(struct amap_eth_rx_compl, ipcksm, rxcp);
710 ip_version = AMAP_GET_BITS(struct amap_eth_rx_compl, ip_version, rxcp);
711 if (ip_version) {
712 tcpf = AMAP_GET_BITS(struct amap_eth_rx_compl, tcpf, rxcp);
713 udpf = AMAP_GET_BITS(struct amap_eth_rx_compl, udpf, rxcp);
714 }
715 ipv6_chk = (ip_version && (tcpf || udpf));
716
717 return ((l4_cksm && ipv6_chk && ipcksm) && cso) ? false : true;
718}
719
6b7c5b94
SP		 720static struct be_rx_page_info *
721get_rx_page_info(struct be_adapter *adapter, u16 frag_idx)
722{
723 struct be_rx_page_info *rx_page_info;
724 struct be_queue_info *rxq = &adapter->rx_obj.q;
725
726 rx_page_info = &adapter->rx_obj.page_info_tbl[frag_idx];
727 BUG_ON(!rx_page_info->page);
728
205859a2 729 if (rx_page_info->last_page_user) {
fac6da5b 730 pci_unmap_page(adapter->pdev, dma_unmap_addr(rx_page_info, bus),
6b7c5b94 731 adapter->big_page_size, PCI_DMA_FROMDEVICE);
205859a2
AK		 732 rx_page_info->last_page_user = false;
733 }
6b7c5b94
SP		 734
735 atomic_dec(&rxq->used);
736 return rx_page_info;
737}
738
739/* Throwaway the data in the Rx completion */
740static void be_rx_compl_discard(struct be_adapter *adapter,
741 struct be_eth_rx_compl *rxcp)
742{
743 struct be_queue_info *rxq = &adapter->rx_obj.q;
744 struct be_rx_page_info *page_info;
745 u16 rxq_idx, i, num_rcvd;
746
747 rxq_idx = AMAP_GET_BITS(struct amap_eth_rx_compl, fragndx, rxcp);
748 num_rcvd = AMAP_GET_BITS(struct amap_eth_rx_compl, numfrags, rxcp);
749
750 for (i = 0; i < num_rcvd; i++) {
751 page_info = get_rx_page_info(adapter, rxq_idx);
752 put_page(page_info->page);
753 memset(page_info, 0, sizeof(*page_info));
754 index_inc(&rxq_idx, rxq->len);
755 }
756}
757
758/*
759 * skb_fill_rx_data forms a complete skb for an ether frame
760 * indicated by rxcp.
761 */
762static void skb_fill_rx_data(struct be_adapter *adapter,
89420424
SP		 763 struct sk_buff *skb, struct be_eth_rx_compl *rxcp,
764 u16 num_rcvd)
6b7c5b94
SP		 765{
766 struct be_queue_info *rxq = &adapter->rx_obj.q;
767 struct be_rx_page_info *page_info;
89420424 768 u16 rxq_idx, i, j;
fa77406a 769 u32 pktsize, hdr_len, curr_frag_len, size;
6b7c5b94
SP		 770 u8 *start;
771
772 rxq_idx = AMAP_GET_BITS(struct amap_eth_rx_compl, fragndx, rxcp);
773 pktsize = AMAP_GET_BITS(struct amap_eth_rx_compl, pktsize, rxcp);
6b7c5b94
SP		 774
775 page_info = get_rx_page_info(adapter, rxq_idx);
776
777 start = page_address(page_info->page) + page_info->page_offset;
778 prefetch(start);
779
780 /* Copy data in the first descriptor of this completion */
781 curr_frag_len = min(pktsize, rx_frag_size);
782
783 /* Copy the header portion into skb_data */
784 hdr_len = min((u32)BE_HDR_LEN, curr_frag_len);
785 memcpy(skb->data, start, hdr_len);
786 skb->len = curr_frag_len;
787 if (curr_frag_len <= BE_HDR_LEN) { /* tiny packet */
788 /* Complete packet has now been moved to data */
789 put_page(page_info->page);
790 skb->data_len = 0;
791 skb->tail += curr_frag_len;
792 } else {
793 skb_shinfo(skb)->nr_frags = 1;
794 skb_shinfo(skb)->frags[0].page = page_info->page;
795 skb_shinfo(skb)->frags[0].page_offset =
796 page_info->page_offset + hdr_len;
797 skb_shinfo(skb)->frags[0].size = curr_frag_len - hdr_len;
798 skb->data_len = curr_frag_len - hdr_len;
799 skb->tail += hdr_len;
800 }
205859a2 801 page_info->page = NULL;
6b7c5b94
SP		 802
803 if (pktsize <= rx_frag_size) {
804 BUG_ON(num_rcvd != 1);
76fbb429 805 goto done;
6b7c5b94
SP		 806 }
807
808 /* More frags present for this completion */
fa77406a 809 size = pktsize;
bd46cb6c 810 for (i = 1, j = 0; i < num_rcvd; i++) {
fa77406a 811 size -= curr_frag_len;
6b7c5b94
SP		 812 index_inc(&rxq_idx, rxq->len);
813 page_info = get_rx_page_info(adapter, rxq_idx);
814
fa77406a 815 curr_frag_len = min(size, rx_frag_size);
6b7c5b94 816
bd46cb6c
AK		 817 /* Coalesce all frags from the same physical page in one slot */
818 if (page_info->page_offset == 0) {
819 /* Fresh page */
820 j++;
821 skb_shinfo(skb)->frags[j].page = page_info->page;
822 skb_shinfo(skb)->frags[j].page_offset =
823 page_info->page_offset;
824 skb_shinfo(skb)->frags[j].size = 0;
825 skb_shinfo(skb)->nr_frags++;
826 } else {
827 put_page(page_info->page);
828 }
829
830 skb_shinfo(skb)->frags[j].size += curr_frag_len;
6b7c5b94
SP		 831 skb->len += curr_frag_len;
832 skb->data_len += curr_frag_len;
6b7c5b94 833
205859a2 834 page_info->page = NULL;
6b7c5b94 835 }
bd46cb6c 836 BUG_ON(j > MAX_SKB_FRAGS);
6b7c5b94 837
76fbb429 838done:
4097f663 839 be_rx_stats_update(adapter, pktsize, num_rcvd);
6b7c5b94
SP		 840}
841
5be93b9a 842/* Process the RX completion indicated by rxcp when GRO is disabled */
6b7c5b94
SP		 843static void be_rx_compl_process(struct be_adapter *adapter,
844 struct be_eth_rx_compl *rxcp)
845{
846 struct sk_buff *skb;
dcb9b564 847 u32 vlanf, vid;
89420424 848 u16 num_rcvd;
dcb9b564 849 u8 vtm;
6b7c5b94 850
89420424
SP		 851 num_rcvd = AMAP_GET_BITS(struct amap_eth_rx_compl, numfrags, rxcp);
852 /* Is it a flush compl that has no data */
853 if (unlikely(num_rcvd == 0))
854 return;
855
89d71a66 856 skb = netdev_alloc_skb_ip_align(adapter->netdev, BE_HDR_LEN);
a058a632 857 if (unlikely(!skb)) {
6b7c5b94
SP		 858 if (net_ratelimit())
859 dev_warn(&adapter->pdev->dev, "skb alloc failed\n");
860 be_rx_compl_discard(adapter, rxcp);
861 return;
862 }
863
89420424 864 skb_fill_rx_data(adapter, skb, rxcp, num_rcvd);
6b7c5b94 865
728a9972 866 if (do_pkt_csum(rxcp, adapter->rx_csum))
6b7c5b94 867 skb->ip_summed = CHECKSUM_NONE;
728a9972
AK		 868 else
869 skb->ip_summed = CHECKSUM_UNNECESSARY;
6b7c5b94
SP		 870
871 skb->truesize = skb->len + sizeof(struct sk_buff);
872 skb->protocol = eth_type_trans(skb, adapter->netdev);
6b7c5b94 873
a058a632
SP		 874 vlanf = AMAP_GET_BITS(struct amap_eth_rx_compl, vtp, rxcp);
875 vtm = AMAP_GET_BITS(struct amap_eth_rx_compl, vtm, rxcp);
876
877 /* vlanf could be wrongly set in some cards.
878 * ignore if vtm is not set */
879 if ((adapter->cap & 0x400) && !vtm)
880 vlanf = 0;
881
882 if (unlikely(vlanf)) {
82903e4b 883 if (!adapter->vlan_grp || adapter->vlans_added == 0) {
6b7c5b94
SP		 884 kfree_skb(skb);
885 return;
886 }
887 vid = AMAP_GET_BITS(struct amap_eth_rx_compl, vlan_tag, rxcp);
9cae9e4f 888 vid = swab16(vid);
6b7c5b94
SP		 889 vlan_hwaccel_receive_skb(skb, adapter->vlan_grp, vid);
890 } else {
891 netif_receive_skb(skb);
892 }
6b7c5b94
SP		 893}
894
5be93b9a
AK		 895/* Process the RX completion indicated by rxcp when GRO is enabled */
896static void be_rx_compl_process_gro(struct be_adapter *adapter,
6b7c5b94
SP		 897 struct be_eth_rx_compl *rxcp)
898{
899 struct be_rx_page_info *page_info;
5be93b9a 900 struct sk_buff *skb = NULL;
6b7c5b94 901 struct be_queue_info *rxq = &adapter->rx_obj.q;
5be93b9a 902 struct be_eq_obj *eq_obj = &adapter->rx_eq;
6b7c5b94 903 u32 num_rcvd, pkt_size, remaining, vlanf, curr_frag_len;
bd46cb6c 904 u16 i, rxq_idx = 0, vid, j;
dcb9b564 905 u8 vtm;
6b7c5b94
SP		 906
907 num_rcvd = AMAP_GET_BITS(struct amap_eth_rx_compl, numfrags, rxcp);
89420424
SP		 908 /* Is it a flush compl that has no data */
909 if (unlikely(num_rcvd == 0))
910 return;
911
6b7c5b94
SP		 912 pkt_size = AMAP_GET_BITS(struct amap_eth_rx_compl, pktsize, rxcp);
913 vlanf = AMAP_GET_BITS(struct amap_eth_rx_compl, vtp, rxcp);
914 rxq_idx = AMAP_GET_BITS(struct amap_eth_rx_compl, fragndx, rxcp);
dcb9b564
AK		 915 vtm = AMAP_GET_BITS(struct amap_eth_rx_compl, vtm, rxcp);
916
917 /* vlanf could be wrongly set in some cards.
918 * ignore if vtm is not set */
e1187b3b 919 if ((adapter->cap & 0x400) && !vtm)
dcb9b564 920 vlanf = 0;
6b7c5b94 921
5be93b9a
AK		 922 skb = napi_get_frags(&eq_obj->napi);
923 if (!skb) {
924 be_rx_compl_discard(adapter, rxcp);
925 return;
926 }
927
6b7c5b94 928 remaining = pkt_size;
bd46cb6c 929 for (i = 0, j = -1; i < num_rcvd; i++) {
6b7c5b94
SP		 930 page_info = get_rx_page_info(adapter, rxq_idx);
931
932 curr_frag_len = min(remaining, rx_frag_size);
933
bd46cb6c
AK		 934 /* Coalesce all frags from the same physical page in one slot */
935 if (i == 0 || page_info->page_offset == 0) {
936 /* First frag or Fresh page */
937 j++;
5be93b9a
AK		 938 skb_shinfo(skb)->frags[j].page = page_info->page;
939 skb_shinfo(skb)->frags[j].page_offset =
940 page_info->page_offset;
941 skb_shinfo(skb)->frags[j].size = 0;
bd46cb6c
AK		 942 } else {
943 put_page(page_info->page);
944 }
5be93b9a 945 skb_shinfo(skb)->frags[j].size += curr_frag_len;
6b7c5b94 946
bd46cb6c 947 remaining -= curr_frag_len;
6b7c5b94 948 index_inc(&rxq_idx, rxq->len);
6b7c5b94
SP		 949 memset(page_info, 0, sizeof(*page_info));
950 }
bd46cb6c 951 BUG_ON(j > MAX_SKB_FRAGS);
6b7c5b94 952
5be93b9a
AK		 953 skb_shinfo(skb)->nr_frags = j + 1;
954 skb->len = pkt_size;
955 skb->data_len = pkt_size;
956 skb->truesize += pkt_size;
957 skb->ip_summed = CHECKSUM_UNNECESSARY;
958
6b7c5b94 959 if (likely(!vlanf)) {
5be93b9a 960 napi_gro_frags(&eq_obj->napi);
6b7c5b94
SP		 961 } else {
962 vid = AMAP_GET_BITS(struct amap_eth_rx_compl, vlan_tag, rxcp);
9cae9e4f 963 vid = swab16(vid);
6b7c5b94 964
82903e4b 965 if (!adapter->vlan_grp || adapter->vlans_added == 0)
6b7c5b94
SP		 966 return;
967
5be93b9a 968 vlan_gro_frags(&eq_obj->napi, adapter->vlan_grp, vid);
6b7c5b94
SP		 969 }
970
4097f663 971 be_rx_stats_update(adapter, pkt_size, num_rcvd);
6b7c5b94
SP		 972}
973
974static struct be_eth_rx_compl *be_rx_compl_get(struct be_adapter *adapter)
975{
976 struct be_eth_rx_compl *rxcp = queue_tail_node(&adapter->rx_obj.cq);
977
978 if (rxcp->dw[offsetof(struct amap_eth_rx_compl, valid) / 32] == 0)
979 return NULL;
980
f3eb62d2 981 rmb();
6b7c5b94
SP		 982 be_dws_le_to_cpu(rxcp, sizeof(*rxcp));
983
6b7c5b94
SP		 984 queue_tail_inc(&adapter->rx_obj.cq);
985 return rxcp;
986}
987
a7a0ef31
SP		 988/* To reset the valid bit, we need to reset the whole word as
989 * when walking the queue the valid entries are little-endian
990 * and invalid entries are host endian
991 */
992static inline void be_rx_compl_reset(struct be_eth_rx_compl *rxcp)
993{
994 rxcp->dw[offsetof(struct amap_eth_rx_compl, valid) / 32] = 0;
995}
996
6b7c5b94
SP		 997static inline struct page *be_alloc_pages(u32 size)
998{
999 gfp_t alloc_flags = GFP_ATOMIC;
1000 u32 order = get_order(size);
1001 if (order > 0)
1002 alloc_flags |= __GFP_COMP;
1003 return alloc_pages(alloc_flags, order);
1004}
1005
1006/*
1007 * Allocate a page, split it to fragments of size rx_frag_size and post as
1008 * receive buffers to BE
1009 */
1010static void be_post_rx_frags(struct be_adapter *adapter)
1011{
1012 struct be_rx_page_info *page_info_tbl = adapter->rx_obj.page_info_tbl;
26d92f92 1013 struct be_rx_page_info *page_info = NULL, *prev_page_info = NULL;
6b7c5b94
SP		 1014 struct be_queue_info *rxq = &adapter->rx_obj.q;
1015 struct page *pagep = NULL;
1016 struct be_eth_rx_d *rxd;
1017 u64 page_dmaaddr = 0, frag_dmaaddr;
1018 u32 posted, page_offset = 0;
1019
6b7c5b94
SP		 1020 page_info = &page_info_tbl[rxq->head];
1021 for (posted = 0; posted < MAX_RX_POST && !page_info->page; posted++) {
1022 if (!pagep) {
1023 pagep = be_alloc_pages(adapter->big_page_size);
1024 if (unlikely(!pagep)) {
1025 drvr_stats(adapter)->be_ethrx_post_fail++;
1026 break;
1027 }
1028 page_dmaaddr = pci_map_page(adapter->pdev, pagep, 0,
1029 adapter->big_page_size,
1030 PCI_DMA_FROMDEVICE);
1031 page_info->page_offset = 0;
1032 } else {
1033 get_page(pagep);
1034 page_info->page_offset = page_offset + rx_frag_size;
1035 }
1036 page_offset = page_info->page_offset;
1037 page_info->page = pagep;
fac6da5b 1038 dma_unmap_addr_set(page_info, bus, page_dmaaddr);
6b7c5b94
SP		 1039 frag_dmaaddr = page_dmaaddr + page_info->page_offset;
1040
1041 rxd = queue_head_node(rxq);
1042 rxd->fragpa_lo = cpu_to_le32(frag_dmaaddr & 0xFFFFFFFF);
1043 rxd->fragpa_hi = cpu_to_le32(upper_32_bits(frag_dmaaddr));
6b7c5b94
SP		 1044
1045 /* Any space left in the current big page for another frag? */
1046 if ((page_offset + rx_frag_size + rx_frag_size) >
1047 adapter->big_page_size) {
1048 pagep = NULL;
1049 page_info->last_page_user = true;
1050 }
26d92f92
SP		 1051
1052 prev_page_info = page_info;
1053 queue_head_inc(rxq);
6b7c5b94
SP		 1054 page_info = &page_info_tbl[rxq->head];
1055 }
1056 if (pagep)
26d92f92 1057 prev_page_info->last_page_user = true;
6b7c5b94
SP		 1058
1059 if (posted) {
6b7c5b94 1060 atomic_add(posted, &rxq->used);
8788fdc2 1061 be_rxq_notify(adapter, rxq->id, posted);
ea1dae11
SP		 1062 } else if (atomic_read(&rxq->used) == 0) {
1063 /* Let be_worker replenish when memory is available */
1064 adapter->rx_post_starved = true;
6b7c5b94 1065 }
6b7c5b94
SP		 1066}
1067
5fb379ee 1068static struct be_eth_tx_compl *be_tx_compl_get(struct be_queue_info *tx_cq)
6b7c5b94 1069{
6b7c5b94
SP		 1070 struct be_eth_tx_compl *txcp = queue_tail_node(tx_cq);
1071
1072 if (txcp->dw[offsetof(struct amap_eth_tx_compl, valid) / 32] == 0)
1073 return NULL;
1074
f3eb62d2 1075 rmb();
6b7c5b94
SP		 1076 be_dws_le_to_cpu(txcp, sizeof(*txcp));
1077
1078 txcp->dw[offsetof(struct amap_eth_tx_compl, valid) / 32] = 0;
1079
1080 queue_tail_inc(tx_cq);
1081 return txcp;
1082}
1083
1084static void be_tx_compl_process(struct be_adapter *adapter, u16 last_index)
1085{
1086 struct be_queue_info *txq = &adapter->tx_obj.q;
a73b796e 1087 struct be_eth_wrb *wrb;
6b7c5b94
SP		 1088 struct sk_buff **sent_skbs = adapter->tx_obj.sent_skb_list;
1089 struct sk_buff *sent_skb;
ec43b1a6
SP		 1090 u16 cur_index, num_wrbs = 1; /* account for hdr wrb */
1091 bool unmap_skb_hdr = true;
6b7c5b94 1092
ec43b1a6 1093 sent_skb = sent_skbs[txq->tail];
6b7c5b94 1094 BUG_ON(!sent_skb);
ec43b1a6
SP		 1095 sent_skbs[txq->tail] = NULL;
1096
1097 /* skip header wrb */
a73b796e 1098 queue_tail_inc(txq);
6b7c5b94 1099
ec43b1a6 1100 do {
6b7c5b94 1101 cur_index = txq->tail;
a73b796e 1102 wrb = queue_tail_node(txq);
ec43b1a6 1103 unmap_tx_frag(adapter->pdev, wrb, (unmap_skb_hdr &&
e743d313 1104 skb_headlen(sent_skb)));
ec43b1a6
SP		 1105 unmap_skb_hdr = false;
1106
6b7c5b94
SP		 1107 num_wrbs++;
1108 queue_tail_inc(txq);
ec43b1a6 1109 } while (cur_index != last_index);
6b7c5b94
SP		 1110
1111 atomic_sub(num_wrbs, &txq->used);
a73b796e 1112
6b7c5b94
SP		 1113 kfree_skb(sent_skb);
1114}
1115
859b1e4e
SP		 1116static inline struct be_eq_entry *event_get(struct be_eq_obj *eq_obj)
1117{
1118 struct be_eq_entry *eqe = queue_tail_node(&eq_obj->q);
1119
1120 if (!eqe->evt)
1121 return NULL;
1122
f3eb62d2 1123 rmb();
859b1e4e
SP		 1124 eqe->evt = le32_to_cpu(eqe->evt);
1125 queue_tail_inc(&eq_obj->q);
1126 return eqe;
1127}
1128
1129static int event_handle(struct be_adapter *adapter,
1130 struct be_eq_obj *eq_obj)
1131{
1132 struct be_eq_entry *eqe;
1133 u16 num = 0;
1134
1135 while ((eqe = event_get(eq_obj)) != NULL) {
1136 eqe->evt = 0;
1137 num++;
1138 }
1139
1140 /* Deal with any spurious interrupts that come
1141 * without events
1142 */
1143 be_eq_notify(adapter, eq_obj->q.id, true, true, num);
1144 if (num)
1145 napi_schedule(&eq_obj->napi);
1146
1147 return num;
1148}
1149
1150/* Just read and notify events without processing them.
1151 * Used at the time of destroying event queues */
1152static void be_eq_clean(struct be_adapter *adapter,
1153 struct be_eq_obj *eq_obj)
1154{
1155 struct be_eq_entry *eqe;
1156 u16 num = 0;
1157
1158 while ((eqe = event_get(eq_obj)) != NULL) {
1159 eqe->evt = 0;
1160 num++;
1161 }
1162
1163 if (num)
1164 be_eq_notify(adapter, eq_obj->q.id, false, true, num);
1165}
1166
6b7c5b94
SP		 1167static void be_rx_q_clean(struct be_adapter *adapter)
1168{
1169 struct be_rx_page_info *page_info;
1170 struct be_queue_info *rxq = &adapter->rx_obj.q;
1171 struct be_queue_info *rx_cq = &adapter->rx_obj.cq;
1172 struct be_eth_rx_compl *rxcp;
1173 u16 tail;
1174
1175 /* First cleanup pending rx completions */
1176 while ((rxcp = be_rx_compl_get(adapter)) != NULL) {
1177 be_rx_compl_discard(adapter, rxcp);
a7a0ef31 1178 be_rx_compl_reset(rxcp);
8788fdc2 1179 be_cq_notify(adapter, rx_cq->id, true, 1);
6b7c5b94
SP		 1180 }
1181
1182 /* Then free posted rx buffer that were not used */
1183 tail = (rxq->head + rxq->len - atomic_read(&rxq->used)) % rxq->len;
cdab23b7 1184 for (; atomic_read(&rxq->used) > 0; index_inc(&tail, rxq->len)) {
6b7c5b94
SP		 1185 page_info = get_rx_page_info(adapter, tail);
1186 put_page(page_info->page);
1187 memset(page_info, 0, sizeof(*page_info));
1188 }
1189 BUG_ON(atomic_read(&rxq->used));
1190}
1191
a8e9179a 1192static void be_tx_compl_clean(struct be_adapter *adapter)
6b7c5b94 1193{
a8e9179a 1194 struct be_queue_info *tx_cq = &adapter->tx_obj.cq;
6b7c5b94 1195 struct be_queue_info *txq = &adapter->tx_obj.q;
a8e9179a
SP		 1196 struct be_eth_tx_compl *txcp;
1197 u16 end_idx, cmpl = 0, timeo = 0;
b03388d6
SP		 1198 struct sk_buff **sent_skbs = adapter->tx_obj.sent_skb_list;
1199 struct sk_buff *sent_skb;
1200 bool dummy_wrb;
a8e9179a
SP		 1201
1202 /* Wait for a max of 200ms for all the tx-completions to arrive. */
1203 do {
1204 while ((txcp = be_tx_compl_get(tx_cq))) {
1205 end_idx = AMAP_GET_BITS(struct amap_eth_tx_compl,
1206 wrb_index, txcp);
1207 be_tx_compl_process(adapter, end_idx);
1208 cmpl++;
1209 }
1210 if (cmpl) {
1211 be_cq_notify(adapter, tx_cq->id, false, cmpl);
1212 cmpl = 0;
1213 }
1214
1215 if (atomic_read(&txq->used) == 0 || ++timeo > 200)
1216 break;
1217
1218 mdelay(1);
1219 } while (true);
1220
1221 if (atomic_read(&txq->used))
1222 dev_err(&adapter->pdev->dev, "%d pending tx-completions\n",
1223 atomic_read(&txq->used));
b03388d6
SP		 1224
1225 /* free posted tx for which compls will never arrive */
1226 while (atomic_read(&txq->used)) {
1227 sent_skb = sent_skbs[txq->tail];
1228 end_idx = txq->tail;
1229 index_adv(&end_idx,
1230 wrb_cnt_for_skb(sent_skb, &dummy_wrb) - 1, txq->len);
1231 be_tx_compl_process(adapter, end_idx);
1232 }
6b7c5b94
SP		 1233}
1234
5fb379ee
SP		 1235static void be_mcc_queues_destroy(struct be_adapter *adapter)
1236{
1237 struct be_queue_info *q;
5fb379ee 1238
8788fdc2 1239 q = &adapter->mcc_obj.q;
5fb379ee 1240 if (q->created)
8788fdc2 1241 be_cmd_q_destroy(adapter, q, QTYPE_MCCQ);
5fb379ee
SP		 1242 be_queue_free(adapter, q);
1243
8788fdc2 1244 q = &adapter->mcc_obj.cq;
5fb379ee 1245 if (q->created)
8788fdc2 1246 be_cmd_q_destroy(adapter, q, QTYPE_CQ);
5fb379ee
SP		 1247 be_queue_free(adapter, q);
1248}
1249
1250/* Must be called only after TX qs are created as MCC shares TX EQ */
1251static int be_mcc_queues_create(struct be_adapter *adapter)
1252{
1253 struct be_queue_info *q, *cq;
5fb379ee
SP		 1254
1255 /* Alloc MCC compl queue */
8788fdc2 1256 cq = &adapter->mcc_obj.cq;
5fb379ee 1257 if (be_queue_alloc(adapter, cq, MCC_CQ_LEN,
efd2e40a 1258 sizeof(struct be_mcc_compl)))
5fb379ee
SP		 1259 goto err;
1260
1261 /* Ask BE to create MCC compl queue; share TX's eq */
8788fdc2 1262 if (be_cmd_cq_create(adapter, cq, &adapter->tx_eq.q, false, true, 0))
5fb379ee
SP		 1263 goto mcc_cq_free;
1264
1265 /* Alloc MCC queue */
8788fdc2 1266 q = &adapter->mcc_obj.q;
5fb379ee
SP		 1267 if (be_queue_alloc(adapter, q, MCC_Q_LEN, sizeof(struct be_mcc_wrb)))
1268 goto mcc_cq_destroy;
1269
1270 /* Ask BE to create MCC queue */
8788fdc2 1271 if (be_cmd_mccq_create(adapter, q, cq))
5fb379ee
SP		 1272 goto mcc_q_free;
1273
1274 return 0;
1275
1276mcc_q_free:
1277 be_queue_free(adapter, q);
1278mcc_cq_destroy:
8788fdc2 1279 be_cmd_q_destroy(adapter, cq, QTYPE_CQ);
5fb379ee
SP		 1280mcc_cq_free:
1281 be_queue_free(adapter, cq);
1282err:
1283 return -1;
1284}
1285
6b7c5b94
SP		 1286static void be_tx_queues_destroy(struct be_adapter *adapter)
1287{
1288 struct be_queue_info *q;
1289
1290 q = &adapter->tx_obj.q;
a8e9179a 1291 if (q->created)
8788fdc2 1292 be_cmd_q_destroy(adapter, q, QTYPE_TXQ);
6b7c5b94
SP		 1293 be_queue_free(adapter, q);
1294
1295 q = &adapter->tx_obj.cq;
1296 if (q->created)
8788fdc2 1297 be_cmd_q_destroy(adapter, q, QTYPE_CQ);
6b7c5b94
SP		 1298 be_queue_free(adapter, q);
1299
859b1e4e
SP		 1300 /* Clear any residual events */
1301 be_eq_clean(adapter, &adapter->tx_eq);
1302
6b7c5b94
SP		 1303 q = &adapter->tx_eq.q;
1304 if (q->created)
8788fdc2 1305 be_cmd_q_destroy(adapter, q, QTYPE_EQ);
6b7c5b94
SP		 1306 be_queue_free(adapter, q);
1307}
1308
1309static int be_tx_queues_create(struct be_adapter *adapter)
1310{
1311 struct be_queue_info *eq, *q, *cq;
1312
1313 adapter->tx_eq.max_eqd = 0;
1314 adapter->tx_eq.min_eqd = 0;
1315 adapter->tx_eq.cur_eqd = 96;
1316 adapter->tx_eq.enable_aic = false;
1317 /* Alloc Tx Event queue */
1318 eq = &adapter->tx_eq.q;
1319 if (be_queue_alloc(adapter, eq, EVNT_Q_LEN, sizeof(struct be_eq_entry)))
1320 return -1;
1321
1322 /* Ask BE to create Tx Event queue */
8788fdc2 1323 if (be_cmd_eq_create(adapter, eq, adapter->tx_eq.cur_eqd))
6b7c5b94 1324 goto tx_eq_free;
ba343c77
SB		 1325 adapter->base_eq_id = adapter->tx_eq.q.id;
1326
6b7c5b94
SP		 1327 /* Alloc TX eth compl queue */
1328 cq = &adapter->tx_obj.cq;
1329 if (be_queue_alloc(adapter, cq, TX_CQ_LEN,
1330 sizeof(struct be_eth_tx_compl)))
1331 goto tx_eq_destroy;
1332
1333 /* Ask BE to create Tx eth compl queue */
8788fdc2 1334 if (be_cmd_cq_create(adapter, cq, eq, false, false, 3))
6b7c5b94
SP		 1335 goto tx_cq_free;
1336
1337 /* Alloc TX eth queue */
1338 q = &adapter->tx_obj.q;
1339 if (be_queue_alloc(adapter, q, TX_Q_LEN, sizeof(struct be_eth_wrb)))
1340 goto tx_cq_destroy;
1341
1342 /* Ask BE to create Tx eth queue */
8788fdc2 1343 if (be_cmd_txq_create(adapter, q, cq))
6b7c5b94
SP		 1344 goto tx_q_free;
1345 return 0;
1346
1347tx_q_free:
1348 be_queue_free(adapter, q);
1349tx_cq_destroy:
8788fdc2 1350 be_cmd_q_destroy(adapter, cq, QTYPE_CQ);
6b7c5b94
SP		 1351tx_cq_free:
1352 be_queue_free(adapter, cq);
1353tx_eq_destroy:
8788fdc2 1354 be_cmd_q_destroy(adapter, eq, QTYPE_EQ);
6b7c5b94
SP		 1355tx_eq_free:
1356 be_queue_free(adapter, eq);
1357 return -1;
1358}
1359
1360static void be_rx_queues_destroy(struct be_adapter *adapter)
1361{
1362 struct be_queue_info *q;
1363
1364 q = &adapter->rx_obj.q;
1365 if (q->created) {
8788fdc2 1366 be_cmd_q_destroy(adapter, q, QTYPE_RXQ);
89420424
SP		 1367
1368 /* After the rxq is invalidated, wait for a grace time
1369 * of 1ms for all dma to end and the flush compl to arrive
1370 */
1371 mdelay(1);
6b7c5b94
SP		 1372 be_rx_q_clean(adapter);
1373 }
1374 be_queue_free(adapter, q);
1375
1376 q = &adapter->rx_obj.cq;
1377 if (q->created)
8788fdc2 1378 be_cmd_q_destroy(adapter, q, QTYPE_CQ);
6b7c5b94
SP		 1379 be_queue_free(adapter, q);
1380
859b1e4e
SP		 1381 /* Clear any residual events */
1382 be_eq_clean(adapter, &adapter->rx_eq);
1383
6b7c5b94
SP		 1384 q = &adapter->rx_eq.q;
1385 if (q->created)
8788fdc2 1386 be_cmd_q_destroy(adapter, q, QTYPE_EQ);
6b7c5b94
SP		 1387 be_queue_free(adapter, q);
1388}
1389
1390static int be_rx_queues_create(struct be_adapter *adapter)
1391{
1392 struct be_queue_info *eq, *q, *cq;
1393 int rc;
1394
6b7c5b94
SP		 1395 adapter->big_page_size = (1 << get_order(rx_frag_size)) * PAGE_SIZE;
1396 adapter->rx_eq.max_eqd = BE_MAX_EQD;
1397 adapter->rx_eq.min_eqd = 0;
1398 adapter->rx_eq.cur_eqd = 0;
1399 adapter->rx_eq.enable_aic = true;
1400
1401 /* Alloc Rx Event queue */
1402 eq = &adapter->rx_eq.q;
1403 rc = be_queue_alloc(adapter, eq, EVNT_Q_LEN,
1404 sizeof(struct be_eq_entry));
1405 if (rc)
1406 return rc;
1407
1408 /* Ask BE to create Rx Event queue */
8788fdc2 1409 rc = be_cmd_eq_create(adapter, eq, adapter->rx_eq.cur_eqd);
6b7c5b94
SP		 1410 if (rc)
1411 goto rx_eq_free;
1412
1413 /* Alloc RX eth compl queue */
1414 cq = &adapter->rx_obj.cq;
1415 rc = be_queue_alloc(adapter, cq, RX_CQ_LEN,
1416 sizeof(struct be_eth_rx_compl));
1417 if (rc)
1418 goto rx_eq_destroy;
1419
1420 /* Ask BE to create Rx eth compl queue */
8788fdc2 1421 rc = be_cmd_cq_create(adapter, cq, eq, false, false, 3);
6b7c5b94
SP		 1422 if (rc)
1423 goto rx_cq_free;
1424
1425 /* Alloc RX eth queue */
1426 q = &adapter->rx_obj.q;
1427 rc = be_queue_alloc(adapter, q, RX_Q_LEN, sizeof(struct be_eth_rx_d));
1428 if (rc)
1429 goto rx_cq_destroy;
1430
1431 /* Ask BE to create Rx eth queue */
8788fdc2 1432 rc = be_cmd_rxq_create(adapter, q, cq->id, rx_frag_size,
6b7c5b94
SP		 1433 BE_MAX_JUMBO_FRAME_SIZE, adapter->if_handle, false);
1434 if (rc)
1435 goto rx_q_free;
1436
1437 return 0;
1438rx_q_free:
1439 be_queue_free(adapter, q);
1440rx_cq_destroy:
8788fdc2 1441 be_cmd_q_destroy(adapter, cq, QTYPE_CQ);
6b7c5b94
SP		 1442rx_cq_free:
1443 be_queue_free(adapter, cq);
1444rx_eq_destroy:
8788fdc2 1445 be_cmd_q_destroy(adapter, eq, QTYPE_EQ);
6b7c5b94
SP		 1446rx_eq_free:
1447 be_queue_free(adapter, eq);
1448 return rc;
1449}
6b7c5b94 1450
b628bde2
SP		 1451/* There are 8 evt ids per func. Retruns the evt id's bit number */
1452static inline int be_evt_bit_get(struct be_adapter *adapter, u32 eq_id)
1453{
ba343c77 1454 return eq_id - adapter->base_eq_id;
b628bde2
SP		 1455}
1456
6b7c5b94
SP		 1457static irqreturn_t be_intx(int irq, void *dev)
1458{
1459 struct be_adapter *adapter = dev;
8788fdc2 1460 int isr;
6b7c5b94 1461
8788fdc2 1462 isr = ioread32(adapter->csr + CEV_ISR0_OFFSET +
55bdeed9 1463 (adapter->tx_eq.q.id/ 8) * CEV_ISR_SIZE);
c001c213 1464 if (!isr)
8788fdc2 1465 return IRQ_NONE;
6b7c5b94 1466
8788fdc2
SP		 1467 event_handle(adapter, &adapter->tx_eq);
1468 event_handle(adapter, &adapter->rx_eq);
c001c213 1469
8788fdc2 1470 return IRQ_HANDLED;
6b7c5b94
SP		 1471}
1472
1473static irqreturn_t be_msix_rx(int irq, void *dev)
1474{
1475 struct be_adapter *adapter = dev;
1476
8788fdc2 1477 event_handle(adapter, &adapter->rx_eq);
6b7c5b94
SP		 1478
1479 return IRQ_HANDLED;
1480}
1481
5fb379ee 1482static irqreturn_t be_msix_tx_mcc(int irq, void *dev)
6b7c5b94
SP		 1483{
1484 struct be_adapter *adapter = dev;
1485
8788fdc2 1486 event_handle(adapter, &adapter->tx_eq);
6b7c5b94
SP		 1487
1488 return IRQ_HANDLED;
1489}
1490
5be93b9a 1491static inline bool do_gro(struct be_adapter *adapter,
6b7c5b94
SP		 1492 struct be_eth_rx_compl *rxcp)
1493{
1494 int err = AMAP_GET_BITS(struct amap_eth_rx_compl, err, rxcp);
1495 int tcp_frame = AMAP_GET_BITS(struct amap_eth_rx_compl, tcpf, rxcp);
1496
1497 if (err)
1498 drvr_stats(adapter)->be_rxcp_err++;
1499
5be93b9a 1500 return (tcp_frame && !err) ? true : false;
6b7c5b94
SP		 1501}
1502
1503int be_poll_rx(struct napi_struct *napi, int budget)
1504{
1505 struct be_eq_obj *rx_eq = container_of(napi, struct be_eq_obj, napi);
1506 struct be_adapter *adapter =
1507 container_of(rx_eq, struct be_adapter, rx_eq);
1508 struct be_queue_info *rx_cq = &adapter->rx_obj.cq;
1509 struct be_eth_rx_compl *rxcp;
1510 u32 work_done;
1511
b7b83ac3 1512 adapter->stats.drvr_stats.be_rx_polls++;
6b7c5b94
SP		 1513 for (work_done = 0; work_done < budget; work_done++) {
1514 rxcp = be_rx_compl_get(adapter);
1515 if (!rxcp)
1516 break;
1517
5be93b9a
AK		 1518 if (do_gro(adapter, rxcp))
1519 be_rx_compl_process_gro(adapter, rxcp);
6b7c5b94
SP		 1520 else
1521 be_rx_compl_process(adapter, rxcp);
a7a0ef31
SP		 1522
1523 be_rx_compl_reset(rxcp);
6b7c5b94
SP		 1524 }
1525
6b7c5b94
SP		 1526 /* Refill the queue */
1527 if (atomic_read(&adapter->rx_obj.q.used) < RX_FRAGS_REFILL_WM)
1528 be_post_rx_frags(adapter);
1529
1530 /* All consumed */
1531 if (work_done < budget) {
1532 napi_complete(napi);
8788fdc2 1533 be_cq_notify(adapter, rx_cq->id, true, work_done);
6b7c5b94
SP		 1534 } else {
1535 /* More to be consumed; continue with interrupts disabled */
8788fdc2 1536 be_cq_notify(adapter, rx_cq->id, false, work_done);
6b7c5b94
SP		 1537 }
1538 return work_done;
1539}
1540
f31e50a8
SP		 1541/* As TX and MCC share the same EQ check for both TX and MCC completions.
1542 * For TX/MCC we don't honour budget; consume everything
1543 */
1544static int be_poll_tx_mcc(struct napi_struct *napi, int budget)
6b7c5b94 1545{
f31e50a8
SP		 1546 struct be_eq_obj *tx_eq = container_of(napi, struct be_eq_obj, napi);
1547 struct be_adapter *adapter =
1548 container_of(tx_eq, struct be_adapter, tx_eq);
5fb379ee
SP		 1549 struct be_queue_info *txq = &adapter->tx_obj.q;
1550 struct be_queue_info *tx_cq = &adapter->tx_obj.cq;
6b7c5b94 1551 struct be_eth_tx_compl *txcp;
f31e50a8 1552 int tx_compl = 0, mcc_compl, status = 0;
6b7c5b94
SP		 1553 u16 end_idx;
1554
5fb379ee 1555 while ((txcp = be_tx_compl_get(tx_cq))) {
6b7c5b94 1556 end_idx = AMAP_GET_BITS(struct amap_eth_tx_compl,
f31e50a8 1557 wrb_index, txcp);
6b7c5b94 1558 be_tx_compl_process(adapter, end_idx);
f31e50a8 1559 tx_compl++;
6b7c5b94
SP		 1560 }
1561
f31e50a8
SP		 1562 mcc_compl = be_process_mcc(adapter, &status);
1563
1564 napi_complete(napi);
1565
1566 if (mcc_compl) {
1567 struct be_mcc_obj *mcc_obj = &adapter->mcc_obj;
1568 be_cq_notify(adapter, mcc_obj->cq.id, true, mcc_compl);
1569 }
1570
1571 if (tx_compl) {
1572 be_cq_notify(adapter, adapter->tx_obj.cq.id, true, tx_compl);
5fb379ee
SP		 1573
1574 /* As Tx wrbs have been freed up, wake up netdev queue if
1575 * it was stopped due to lack of tx wrbs.
1576 */
1577 if (netif_queue_stopped(adapter->netdev) &&
6b7c5b94 1578 atomic_read(&txq->used) < txq->len / 2) {
5fb379ee
SP		 1579 netif_wake_queue(adapter->netdev);
1580 }
1581
1582 drvr_stats(adapter)->be_tx_events++;
f31e50a8 1583 drvr_stats(adapter)->be_tx_compl += tx_compl;
6b7c5b94 1584 }
6b7c5b94
SP		 1585
1586 return 1;
1587}
1588
ea1dae11
SP		 1589static void be_worker(struct work_struct *work)
1590{
1591 struct be_adapter *adapter =
1592 container_of(work, struct be_adapter, work.work);
ea1dae11 1593
b31c50a7 1594 be_cmd_get_stats(adapter, &adapter->stats.cmd);
ea1dae11
SP		 1595
1596 /* Set EQ delay */
1597 be_rx_eqd_update(adapter);
1598
4097f663
SP		 1599 be_tx_rate_update(adapter);
1600 be_rx_rate_update(adapter);
1601
ea1dae11
SP		 1602 if (adapter->rx_post_starved) {
1603 adapter->rx_post_starved = false;
1604 be_post_rx_frags(adapter);
1605 }
1606
1607 schedule_delayed_work(&adapter->work, msecs_to_jiffies(1000));
1608}
1609
8d56ff11
SP		 1610static void be_msix_disable(struct be_adapter *adapter)
1611{
1612 if (adapter->msix_enabled) {
1613 pci_disable_msix(adapter->pdev);
1614 adapter->msix_enabled = false;
1615 }
1616}
1617
6b7c5b94
SP		 1618static void be_msix_enable(struct be_adapter *adapter)
1619{
1620 int i, status;
1621
1622 for (i = 0; i < BE_NUM_MSIX_VECTORS; i++)
1623 adapter->msix_entries[i].entry = i;
1624
1625 status = pci_enable_msix(adapter->pdev, adapter->msix_entries,
1626 BE_NUM_MSIX_VECTORS);
1627 if (status == 0)
1628 adapter->msix_enabled = true;
6b7c5b94
SP		 1629}
1630
ba343c77
SB		 1631static void be_sriov_enable(struct be_adapter *adapter)
1632{
1633#ifdef CONFIG_PCI_IOV
1634 int status;
344dbf10 1635 be_check_sriov_fn_type(adapter);
ba343c77
SB		 1636 if (be_physfn(adapter) && num_vfs) {
1637 status = pci_enable_sriov(adapter->pdev, num_vfs);
1638 adapter->sriov_enabled = status ? false : true;
1639 }
1640#endif
ba343c77
SB		 1641}
1642
1643static void be_sriov_disable(struct be_adapter *adapter)
1644{
1645#ifdef CONFIG_PCI_IOV
1646 if (adapter->sriov_enabled) {
1647 pci_disable_sriov(adapter->pdev);
1648 adapter->sriov_enabled = false;
1649 }
1650#endif
1651}
1652
6b7c5b94
SP		 1653static inline int be_msix_vec_get(struct be_adapter *adapter, u32 eq_id)
1654{
b628bde2
SP		 1655 return adapter->msix_entries[
1656 be_evt_bit_get(adapter, eq_id)].vector;
6b7c5b94
SP		 1657}
1658
b628bde2
SP		 1659static int be_request_irq(struct be_adapter *adapter,
1660 struct be_eq_obj *eq_obj,
1661 void *handler, char *desc)
6b7c5b94
SP		 1662{
1663 struct net_device *netdev = adapter->netdev;
b628bde2
SP		 1664 int vec;
1665
1666 sprintf(eq_obj->desc, "%s-%s", netdev->name, desc);
1667 vec = be_msix_vec_get(adapter, eq_obj->q.id);
1668 return request_irq(vec, handler, 0, eq_obj->desc, adapter);
1669}
1670
1671static void be_free_irq(struct be_adapter *adapter, struct be_eq_obj *eq_obj)
1672{
1673 int vec = be_msix_vec_get(adapter, eq_obj->q.id);
1674 free_irq(vec, adapter);
1675}
6b7c5b94 1676
b628bde2
SP		 1677static int be_msix_register(struct be_adapter *adapter)
1678{
1679 int status;
1680
1681 status = be_request_irq(adapter, &adapter->tx_eq, be_msix_tx_mcc, "tx");
6b7c5b94
SP		 1682 if (status)
1683 goto err;
1684
b628bde2
SP		 1685 status = be_request_irq(adapter, &adapter->rx_eq, be_msix_rx, "rx");
1686 if (status)
1687 goto free_tx_irq;
1688
6b7c5b94 1689 return 0;
b628bde2
SP		 1690
1691free_tx_irq:
1692 be_free_irq(adapter, &adapter->tx_eq);
6b7c5b94
SP		 1693err:
1694 dev_warn(&adapter->pdev->dev,
1695 "MSIX Request IRQ failed - err %d\n", status);
1696 pci_disable_msix(adapter->pdev);
1697 adapter->msix_enabled = false;
1698 return status;
1699}
1700
1701static int be_irq_register(struct be_adapter *adapter)
1702{
1703 struct net_device *netdev = adapter->netdev;
1704 int status;
1705
1706 if (adapter->msix_enabled) {
1707 status = be_msix_register(adapter);
1708 if (status == 0)
1709 goto done;
ba343c77
SB		 1710 /* INTx is not supported for VF */
1711 if (!be_physfn(adapter))
1712 return status;
6b7c5b94
SP		 1713 }
1714
1715 /* INTx */
1716 netdev->irq = adapter->pdev->irq;
1717 status = request_irq(netdev->irq, be_intx, IRQF_SHARED, netdev->name,
1718 adapter);
1719 if (status) {
1720 dev_err(&adapter->pdev->dev,
1721 "INTx request IRQ failed - err %d\n", status);
1722 return status;
1723 }
1724done:
1725 adapter->isr_registered = true;
1726 return 0;
1727}
1728
1729static void be_irq_unregister(struct be_adapter *adapter)
1730{
1731 struct net_device *netdev = adapter->netdev;
6b7c5b94
SP		 1732
1733 if (!adapter->isr_registered)
1734 return;
1735
1736 /* INTx */
1737 if (!adapter->msix_enabled) {
1738 free_irq(netdev->irq, adapter);
1739 goto done;
1740 }
1741
1742 /* MSIx */
b628bde2
SP		 1743 be_free_irq(adapter, &adapter->tx_eq);
1744 be_free_irq(adapter, &adapter->rx_eq);
6b7c5b94
SP		 1745done:
1746 adapter->isr_registered = false;
6b7c5b94
SP		 1747}
1748
889cd4b2
SP		 1749static int be_close(struct net_device *netdev)
1750{
1751 struct be_adapter *adapter = netdev_priv(netdev);
1752 struct be_eq_obj *rx_eq = &adapter->rx_eq;
1753 struct be_eq_obj *tx_eq = &adapter->tx_eq;
1754 int vec;
1755
1756 cancel_delayed_work_sync(&adapter->work);
1757
1758 be_async_mcc_disable(adapter);
1759
1760 netif_stop_queue(netdev);
1761 netif_carrier_off(netdev);
1762 adapter->link_up = false;
1763
1764 be_intr_set(adapter, false);
1765
1766 if (adapter->msix_enabled) {
1767 vec = be_msix_vec_get(adapter, tx_eq->q.id);
1768 synchronize_irq(vec);
1769 vec = be_msix_vec_get(adapter, rx_eq->q.id);
1770 synchronize_irq(vec);
1771 } else {
1772 synchronize_irq(netdev->irq);
1773 }
1774 be_irq_unregister(adapter);
1775
1776 napi_disable(&rx_eq->napi);
1777 napi_disable(&tx_eq->napi);
1778
1779 /* Wait for all pending tx completions to arrive so that
1780 * all tx skbs are freed.
1781 */
1782 be_tx_compl_clean(adapter);
1783
1784 return 0;
1785}
1786
6b7c5b94
SP		 1787static int be_open(struct net_device *netdev)
1788{
1789 struct be_adapter *adapter = netdev_priv(netdev);
6b7c5b94
SP		 1790 struct be_eq_obj *rx_eq = &adapter->rx_eq;
1791 struct be_eq_obj *tx_eq = &adapter->tx_eq;
a8f447bd
SP		 1792 bool link_up;
1793 int status;
0388f251
SB		 1794 u8 mac_speed;
1795 u16 link_speed;
5fb379ee
SP		 1796
1797 /* First time posting */
1798 be_post_rx_frags(adapter);
1799
1800 napi_enable(&rx_eq->napi);
1801 napi_enable(&tx_eq->napi);
1802
1803 be_irq_register(adapter);
1804
8788fdc2 1805 be_intr_set(adapter, true);
5fb379ee
SP		 1806
1807 /* The evt queues are created in unarmed state; arm them */
8788fdc2
SP		 1808 be_eq_notify(adapter, rx_eq->q.id, true, false, 0);
1809 be_eq_notify(adapter, tx_eq->q.id, true, false, 0);
5fb379ee
SP		 1810
1811 /* Rx compl queue may be in unarmed state; rearm it */
8788fdc2 1812 be_cq_notify(adapter, adapter->rx_obj.cq.id, true, 0);
5fb379ee 1813
7a1e9b20
SP		 1814 /* Now that interrupts are on we can process async mcc */
1815 be_async_mcc_enable(adapter);
1816
889cd4b2
SP		 1817 schedule_delayed_work(&adapter->work, msecs_to_jiffies(100));
1818
0388f251
SB		 1819 status = be_cmd_link_status_query(adapter, &link_up, &mac_speed,
1820 &link_speed);
a8f447bd 1821 if (status)
889cd4b2 1822 goto err;
a8f447bd 1823 be_link_status_update(adapter, link_up);
5fb379ee 1824
889cd4b2 1825 if (be_physfn(adapter)) {
ba343c77 1826 status = be_vid_config(adapter);
889cd4b2
SP		 1827 if (status)
1828 goto err;
4f2aa89c 1829
ba343c77
SB		 1830 status = be_cmd_set_flow_control(adapter,
1831 adapter->tx_fc, adapter->rx_fc);
1832 if (status)
889cd4b2 1833 goto err;
ba343c77 1834 }
4f2aa89c 1835
889cd4b2
SP		 1836 return 0;
1837err:
1838 be_close(adapter->netdev);
1839 return -EIO;
5fb379ee
SP		 1840}
1841
71d8d1b5
AK		 1842static int be_setup_wol(struct be_adapter *adapter, bool enable)
1843{
1844 struct be_dma_mem cmd;
1845 int status = 0;
1846 u8 mac[ETH_ALEN];
1847
1848 memset(mac, 0, ETH_ALEN);
1849
1850 cmd.size = sizeof(struct be_cmd_req_acpi_wol_magic_config);
1851 cmd.va = pci_alloc_consistent(adapter->pdev, cmd.size, &cmd.dma);
1852 if (cmd.va == NULL)
1853 return -1;
1854 memset(cmd.va, 0, cmd.size);
1855
1856 if (enable) {
1857 status = pci_write_config_dword(adapter->pdev,
1858 PCICFG_PM_CONTROL_OFFSET, PCICFG_PM_CONTROL_MASK);
1859 if (status) {
1860 dev_err(&adapter->pdev->dev,
2381a55c 1861 "Could not enable Wake-on-lan\n");
71d8d1b5
AK		 1862 pci_free_consistent(adapter->pdev, cmd.size, cmd.va,
1863 cmd.dma);
1864 return status;
1865 }
1866 status = be_cmd_enable_magic_wol(adapter,
1867 adapter->netdev->dev_addr, &cmd);
1868 pci_enable_wake(adapter->pdev, PCI_D3hot, 1);
1869 pci_enable_wake(adapter->pdev, PCI_D3cold, 1);
1870 } else {
1871 status = be_cmd_enable_magic_wol(adapter, mac, &cmd);
1872 pci_enable_wake(adapter->pdev, PCI_D3hot, 0);
1873 pci_enable_wake(adapter->pdev, PCI_D3cold, 0);
1874 }
1875
1876 pci_free_consistent(adapter->pdev, cmd.size, cmd.va, cmd.dma);
1877 return status;
1878}
1879
5fb379ee
SP		 1880static int be_setup(struct be_adapter *adapter)
1881{
5fb379ee 1882 struct net_device *netdev = adapter->netdev;
ba343c77 1883 u32 cap_flags, en_flags, vf = 0;
6b7c5b94 1884 int status;
ba343c77
SB		 1885 u8 mac[ETH_ALEN];
1886
1887 cap_flags = en_flags = BE_IF_FLAGS_UNTAGGED | BE_IF_FLAGS_BROADCAST;
6b7c5b94 1888
ba343c77
SB		 1889 if (be_physfn(adapter)) {
1890 cap_flags |= BE_IF_FLAGS_MCAST_PROMISCUOUS |
1891 BE_IF_FLAGS_PROMISCUOUS |
1892 BE_IF_FLAGS_PASS_L3L4_ERRORS;
1893 en_flags |= BE_IF_FLAGS_PASS_L3L4_ERRORS;
1894 }
73d540f2
SP		 1895
1896 status = be_cmd_if_create(adapter, cap_flags, en_flags,
1897 netdev->dev_addr, false/* pmac_invalid */,
ba343c77 1898 &adapter->if_handle, &adapter->pmac_id, 0);
6b7c5b94
SP		 1899 if (status != 0)
1900 goto do_none;
1901
ba343c77
SB		 1902 if (be_physfn(adapter)) {
1903 while (vf < num_vfs) {
1904 cap_flags = en_flags = BE_IF_FLAGS_UNTAGGED
1905 | BE_IF_FLAGS_BROADCAST;
1906 status = be_cmd_if_create(adapter, cap_flags, en_flags,
1907 mac, true, &adapter->vf_if_handle[vf],
1908 NULL, vf+1);
1909 if (status) {
1910 dev_err(&adapter->pdev->dev,
1911 "Interface Create failed for VF %d\n", vf);
1912 goto if_destroy;
1913 }
9cd9000b 1914 adapter->vf_pmac_id[vf] = BE_INVALID_PMAC_ID;
ba343c77 1915 vf++;
84e5b9f7 1916 }
ba343c77
SB		 1917 } else if (!be_physfn(adapter)) {
1918 status = be_cmd_mac_addr_query(adapter, mac,
1919 MAC_ADDRESS_TYPE_NETWORK, false, adapter->if_handle);
1920 if (!status) {
1921 memcpy(adapter->netdev->dev_addr, mac, ETH_ALEN);
1922 memcpy(adapter->netdev->perm_addr, mac, ETH_ALEN);
1923 }
1924 }
1925
6b7c5b94
SP		 1926 status = be_tx_queues_create(adapter);
1927 if (status != 0)
1928 goto if_destroy;
1929
1930 status = be_rx_queues_create(adapter);
1931 if (status != 0)
1932 goto tx_qs_destroy;
1933
5fb379ee
SP		 1934 status = be_mcc_queues_create(adapter);
1935 if (status != 0)
1936 goto rx_qs_destroy;
6b7c5b94 1937
0dffc83e
AK		 1938 adapter->link_speed = -1;
1939
6b7c5b94
SP		 1940 return 0;
1941
5fb379ee
SP		 1942rx_qs_destroy:
1943 be_rx_queues_destroy(adapter);
6b7c5b94
SP		 1944tx_qs_destroy:
1945 be_tx_queues_destroy(adapter);
1946if_destroy:
ba343c77
SB		 1947 for (vf = 0; vf < num_vfs; vf++)
1948 if (adapter->vf_if_handle[vf])
1949 be_cmd_if_destroy(adapter, adapter->vf_if_handle[vf]);
8788fdc2 1950 be_cmd_if_destroy(adapter, adapter->if_handle);
6b7c5b94
SP		 1951do_none:
1952 return status;
1953}
1954
5fb379ee
SP		 1955static int be_clear(struct be_adapter *adapter)
1956{
1a8887d8 1957 be_mcc_queues_destroy(adapter);
5fb379ee
SP		 1958 be_rx_queues_destroy(adapter);
1959 be_tx_queues_destroy(adapter);
1960
8788fdc2 1961 be_cmd_if_destroy(adapter, adapter->if_handle);
5fb379ee 1962
2243e2e9
SP		 1963 /* tell fw we're done with firing cmds */
1964 be_cmd_fw_clean(adapter);
5fb379ee
SP		 1965 return 0;
1966}
1967
6b7c5b94 1968
84517482
AK		 1969#define FW_FILE_HDR_SIGN "ServerEngines Corp. "
1970char flash_cookie[2][16] = {"*** SE FLAS",
1971 "H DIRECTORY *** "};
fa9a6fed
SB		 1972
1973static bool be_flash_redboot(struct be_adapter *adapter,
3f0d4560
AK		 1974 const u8 *p, u32 img_start, int image_size,
1975 int hdr_size)
fa9a6fed
SB		 1976{
1977 u32 crc_offset;
1978 u8 flashed_crc[4];
1979 int status;
3f0d4560
AK		 1980
1981 crc_offset = hdr_size + img_start + image_size - 4;
1982
fa9a6fed 1983 p += crc_offset;
3f0d4560
AK		 1984
1985 status = be_cmd_get_flash_crc(adapter, flashed_crc,
f510fc64 1986 (image_size - 4));
fa9a6fed
SB		 1987 if (status) {
1988 dev_err(&adapter->pdev->dev,
1989 "could not get crc from flash, not flashing redboot\n");
1990 return false;
1991 }
1992
1993 /*update redboot only if crc does not match*/
1994 if (!memcmp(flashed_crc, p, 4))
1995 return false;
1996 else
1997 return true;
fa9a6fed
SB		 1998}
1999
3f0d4560 2000static int be_flash_data(struct be_adapter *adapter,
84517482 2001 const struct firmware *fw,
3f0d4560
AK		 2002 struct be_dma_mem *flash_cmd, int num_of_images)
2003
84517482 2004{
3f0d4560
AK		 2005 int status = 0, i, filehdr_size = 0;
2006 u32 total_bytes = 0, flash_op;
84517482
AK		 2007 int num_bytes;
2008 const u8 *p = fw->data;
2009 struct be_cmd_write_flashrom *req = flash_cmd->va;
3f0d4560 2010 struct flash_comp *pflashcomp;
9fe96934 2011 int num_comp;
3f0d4560 2012
9fe96934 2013 struct flash_comp gen3_flash_types[9] = {
3f0d4560
AK		 2014 { FLASH_iSCSI_PRIMARY_IMAGE_START_g3, IMG_TYPE_ISCSI_ACTIVE,
2015 FLASH_IMAGE_MAX_SIZE_g3},
2016 { FLASH_REDBOOT_START_g3, IMG_TYPE_REDBOOT,
2017 FLASH_REDBOOT_IMAGE_MAX_SIZE_g3},
2018 { FLASH_iSCSI_BIOS_START_g3, IMG_TYPE_BIOS,
2019 FLASH_BIOS_IMAGE_MAX_SIZE_g3},
2020 { FLASH_PXE_BIOS_START_g3, IMG_TYPE_PXE_BIOS,
2021 FLASH_BIOS_IMAGE_MAX_SIZE_g3},
2022 { FLASH_FCoE_BIOS_START_g3, IMG_TYPE_FCOE_BIOS,
2023 FLASH_BIOS_IMAGE_MAX_SIZE_g3},
2024 { FLASH_iSCSI_BACKUP_IMAGE_START_g3, IMG_TYPE_ISCSI_BACKUP,
2025 FLASH_IMAGE_MAX_SIZE_g3},
2026 { FLASH_FCoE_PRIMARY_IMAGE_START_g3, IMG_TYPE_FCOE_FW_ACTIVE,
2027 FLASH_IMAGE_MAX_SIZE_g3},
2028 { FLASH_FCoE_BACKUP_IMAGE_START_g3, IMG_TYPE_FCOE_FW_BACKUP,
9fe96934
SB		 2029 FLASH_IMAGE_MAX_SIZE_g3},
2030 { FLASH_NCSI_START_g3, IMG_TYPE_NCSI_FW,
2031 FLASH_NCSI_IMAGE_MAX_SIZE_g3}
3f0d4560
AK		 2032 };
2033 struct flash_comp gen2_flash_types[8] = {
2034 { FLASH_iSCSI_PRIMARY_IMAGE_START_g2, IMG_TYPE_ISCSI_ACTIVE,
2035 FLASH_IMAGE_MAX_SIZE_g2},
2036 { FLASH_REDBOOT_START_g2, IMG_TYPE_REDBOOT,
2037 FLASH_REDBOOT_IMAGE_MAX_SIZE_g2},
2038 { FLASH_iSCSI_BIOS_START_g2, IMG_TYPE_BIOS,
2039 FLASH_BIOS_IMAGE_MAX_SIZE_g2},
2040 { FLASH_PXE_BIOS_START_g2, IMG_TYPE_PXE_BIOS,
2041 FLASH_BIOS_IMAGE_MAX_SIZE_g2},
2042 { FLASH_FCoE_BIOS_START_g2, IMG_TYPE_FCOE_BIOS,
2043 FLASH_BIOS_IMAGE_MAX_SIZE_g2},
2044 { FLASH_iSCSI_BACKUP_IMAGE_START_g2, IMG_TYPE_ISCSI_BACKUP,
2045 FLASH_IMAGE_MAX_SIZE_g2},
2046 { FLASH_FCoE_PRIMARY_IMAGE_START_g2, IMG_TYPE_FCOE_FW_ACTIVE,
2047 FLASH_IMAGE_MAX_SIZE_g2},
2048 { FLASH_FCoE_BACKUP_IMAGE_START_g2, IMG_TYPE_FCOE_FW_BACKUP,
2049 FLASH_IMAGE_MAX_SIZE_g2}
2050 };
2051
2052 if (adapter->generation == BE_GEN3) {
2053 pflashcomp = gen3_flash_types;
2054 filehdr_size = sizeof(struct flash_file_hdr_g3);
9fe96934 2055 num_comp = 9;
3f0d4560
AK		 2056 } else {
2057 pflashcomp = gen2_flash_types;
2058 filehdr_size = sizeof(struct flash_file_hdr_g2);
9fe96934 2059 num_comp = 8;
84517482 2060 }
9fe96934
SB		 2061 for (i = 0; i < num_comp; i++) {
2062 if ((pflashcomp[i].optype == IMG_TYPE_NCSI_FW) &&
2063 memcmp(adapter->fw_ver, "3.102.148.0", 11) < 0)
2064 continue;
3f0d4560
AK		 2065 if ((pflashcomp[i].optype == IMG_TYPE_REDBOOT) &&
2066 (!be_flash_redboot(adapter, fw->data,
2067 pflashcomp[i].offset, pflashcomp[i].size,
2068 filehdr_size)))
2069 continue;
2070 p = fw->data;
2071 p += filehdr_size + pflashcomp[i].offset
2072 + (num_of_images * sizeof(struct image_hdr));
2073 if (p + pflashcomp[i].size > fw->data + fw->size)
84517482 2074 return -1;
3f0d4560
AK		 2075 total_bytes = pflashcomp[i].size;
2076 while (total_bytes) {
2077 if (total_bytes > 32*1024)
2078 num_bytes = 32*1024;
2079 else
2080 num_bytes = total_bytes;
2081 total_bytes -= num_bytes;
2082
2083 if (!total_bytes)
2084 flash_op = FLASHROM_OPER_FLASH;
2085 else
2086 flash_op = FLASHROM_OPER_SAVE;
2087 memcpy(req->params.data_buf, p, num_bytes);
2088 p += num_bytes;
2089 status = be_cmd_write_flashrom(adapter, flash_cmd,
2090 pflashcomp[i].optype, flash_op, num_bytes);
2091 if (status) {
2092 dev_err(&adapter->pdev->dev,
2093 "cmd to write to flash rom failed.\n");
2094 return -1;
2095 }
2096 yield();
84517482 2097 }
84517482 2098 }
84517482
AK		 2099 return 0;
2100}
2101
3f0d4560
AK		 2102static int get_ufigen_type(struct flash_file_hdr_g2 *fhdr)
2103{
2104 if (fhdr == NULL)
2105 return 0;
2106 if (fhdr->build[0] == '3')
2107 return BE_GEN3;
2108 else if (fhdr->build[0] == '2')
2109 return BE_GEN2;
2110 else
2111 return 0;
2112}
2113
84517482
AK		 2114int be_load_fw(struct be_adapter *adapter, u8 *func)
2115{
2116 char fw_file[ETHTOOL_FLASH_MAX_FILENAME];
2117 const struct firmware *fw;
3f0d4560
AK		 2118 struct flash_file_hdr_g2 *fhdr;
2119 struct flash_file_hdr_g3 *fhdr3;
2120 struct image_hdr *img_hdr_ptr = NULL;
84517482 2121 struct be_dma_mem flash_cmd;
8b93b710 2122 int status, i = 0, num_imgs = 0;
84517482 2123 const u8 *p;
84517482 2124
84517482
AK		 2125 strcpy(fw_file, func);
2126
2127 status = request_firmware(&fw, fw_file, &adapter->pdev->dev);
2128 if (status)
2129 goto fw_exit;
2130
2131 p = fw->data;
3f0d4560 2132 fhdr = (struct flash_file_hdr_g2 *) p;
84517482
AK		 2133 dev_info(&adapter->pdev->dev, "Flashing firmware file %s\n", fw_file);
2134
84517482
AK		 2135 flash_cmd.size = sizeof(struct be_cmd_write_flashrom) + 32*1024;
2136 flash_cmd.va = pci_alloc_consistent(adapter->pdev, flash_cmd.size,
2137 &flash_cmd.dma);
2138 if (!flash_cmd.va) {
2139 status = -ENOMEM;
2140 dev_err(&adapter->pdev->dev,
2141 "Memory allocation failure while flashing\n");
2142 goto fw_exit;
2143 }
2144
3f0d4560
AK		 2145 if ((adapter->generation == BE_GEN3) &&
2146 (get_ufigen_type(fhdr) == BE_GEN3)) {
2147 fhdr3 = (struct flash_file_hdr_g3 *) fw->data;
8b93b710
AK		 2148 num_imgs = le32_to_cpu(fhdr3->num_imgs);
2149 for (i = 0; i < num_imgs; i++) {
3f0d4560
AK		 2150 img_hdr_ptr = (struct image_hdr *) (fw->data +
2151 (sizeof(struct flash_file_hdr_g3) +
8b93b710
AK		 2152 i * sizeof(struct image_hdr)));
2153 if (le32_to_cpu(img_hdr_ptr->imageid) == 1)
2154 status = be_flash_data(adapter, fw, &flash_cmd,
2155 num_imgs);
3f0d4560
AK		 2156 }
2157 } else if ((adapter->generation == BE_GEN2) &&
2158 (get_ufigen_type(fhdr) == BE_GEN2)) {
2159 status = be_flash_data(adapter, fw, &flash_cmd, 0);
2160 } else {
2161 dev_err(&adapter->pdev->dev,
2162 "UFI and Interface are not compatible for flashing\n");
2163 status = -1;
84517482
AK		 2164 }
2165
2166 pci_free_consistent(adapter->pdev, flash_cmd.size, flash_cmd.va,
2167 flash_cmd.dma);
2168 if (status) {
2169 dev_err(&adapter->pdev->dev, "Firmware load error\n");
2170 goto fw_exit;
2171 }
2172
af901ca1 2173 dev_info(&adapter->pdev->dev, "Firmware flashed successfully\n");
84517482
AK		 2174
2175fw_exit:
2176 release_firmware(fw);
2177 return status;
2178}
2179
6b7c5b94
SP		 2180static struct net_device_ops be_netdev_ops = {
2181 .ndo_open = be_open,
2182 .ndo_stop = be_close,
2183 .ndo_start_xmit = be_xmit,
2184 .ndo_get_stats = be_get_stats,
2185 .ndo_set_rx_mode = be_set_multicast_list,
2186 .ndo_set_mac_address = be_mac_addr_set,
2187 .ndo_change_mtu = be_change_mtu,
2188 .ndo_validate_addr = eth_validate_addr,
2189 .ndo_vlan_rx_register = be_vlan_register,
2190 .ndo_vlan_rx_add_vid = be_vlan_add_vid,
2191 .ndo_vlan_rx_kill_vid = be_vlan_rem_vid,
ba343c77 2192 .ndo_set_vf_mac = be_set_vf_mac
6b7c5b94
SP		 2193};
2194
2195static void be_netdev_init(struct net_device *netdev)
2196{
2197 struct be_adapter *adapter = netdev_priv(netdev);
2198
2199 netdev->features |= NETIF_F_SG | NETIF_F_HW_VLAN_RX | NETIF_F_TSO |
583e3f34 2200 NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_FILTER | NETIF_F_HW_CSUM |
49e4b847 2201 NETIF_F_GRO | NETIF_F_TSO6;
6b7c5b94 2202
51c59870
AK		 2203 netdev->vlan_features |= NETIF_F_SG | NETIF_F_TSO | NETIF_F_HW_CSUM;
2204
6b7c5b94
SP		 2205 netdev->flags |= IFF_MULTICAST;
2206
728a9972
AK		 2207 adapter->rx_csum = true;
2208
9e90c961
AK		 2209 /* Default settings for Rx and Tx flow control */
2210 adapter->rx_fc = true;
2211 adapter->tx_fc = true;
2212
c190e3c8
AK		 2213 netif_set_gso_max_size(netdev, 65535);
2214
6b7c5b94
SP		 2215 BE_SET_NETDEV_OPS(netdev, &be_netdev_ops);
2216
2217 SET_ETHTOOL_OPS(netdev, &be_ethtool_ops);
2218
6b7c5b94
SP		 2219 netif_napi_add(netdev, &adapter->rx_eq.napi, be_poll_rx,
2220 BE_NAPI_WEIGHT);
5fb379ee 2221 netif_napi_add(netdev, &adapter->tx_eq.napi, be_poll_tx_mcc,
6b7c5b94
SP		 2222 BE_NAPI_WEIGHT);
2223
2224 netif_carrier_off(netdev);
2225 netif_stop_queue(netdev);
2226}
2227
2228static void be_unmap_pci_bars(struct be_adapter *adapter)
2229{
8788fdc2
SP		 2230 if (adapter->csr)
2231 iounmap(adapter->csr);
2232 if (adapter->db)
2233 iounmap(adapter->db);
ba343c77 2234 if (adapter->pcicfg && be_physfn(adapter))
8788fdc2 2235 iounmap(adapter->pcicfg);
6b7c5b94
SP		 2236}
2237
2238static int be_map_pci_bars(struct be_adapter *adapter)
2239{
2240 u8 __iomem *addr;
ba343c77 2241 int pcicfg_reg, db_reg;
6b7c5b94 2242
ba343c77
SB		 2243 if (be_physfn(adapter)) {
2244 addr = ioremap_nocache(pci_resource_start(adapter->pdev, 2),
2245 pci_resource_len(adapter->pdev, 2));
2246 if (addr == NULL)
2247 return -ENOMEM;
2248 adapter->csr = addr;
2249 }
6b7c5b94 2250
ba343c77 2251 if (adapter->generation == BE_GEN2) {
7b139c83 2252 pcicfg_reg = 1;
ba343c77
SB		 2253 db_reg = 4;
2254 } else {
7b139c83 2255 pcicfg_reg = 0;
ba343c77
SB		 2256 if (be_physfn(adapter))
2257 db_reg = 4;
2258 else
2259 db_reg = 0;
2260 }
2261 addr = ioremap_nocache(pci_resource_start(adapter->pdev, db_reg),
2262 pci_resource_len(adapter->pdev, db_reg));
6b7c5b94
SP		 2263 if (addr == NULL)
2264 goto pci_map_err;
ba343c77
SB		 2265 adapter->db = addr;
2266
2267 if (be_physfn(adapter)) {
2268 addr = ioremap_nocache(
2269 pci_resource_start(adapter->pdev, pcicfg_reg),
2270 pci_resource_len(adapter->pdev, pcicfg_reg));
2271 if (addr == NULL)
2272 goto pci_map_err;
2273 adapter->pcicfg = addr;
2274 } else
2275 adapter->pcicfg = adapter->db + SRIOV_VF_PCICFG_OFFSET;
6b7c5b94
SP		 2276
2277 return 0;
2278pci_map_err:
2279 be_unmap_pci_bars(adapter);
2280 return -ENOMEM;
2281}
2282
2283
2284static void be_ctrl_cleanup(struct be_adapter *adapter)
2285{
8788fdc2 2286 struct be_dma_mem *mem = &adapter->mbox_mem_alloced;
6b7c5b94
SP		 2287
2288 be_unmap_pci_bars(adapter);
2289
2290 if (mem->va)
2291 pci_free_consistent(adapter->pdev, mem->size,
2292 mem->va, mem->dma);
e7b909a6
SP		 2293
2294 mem = &adapter->mc_cmd_mem;
2295 if (mem->va)
2296 pci_free_consistent(adapter->pdev, mem->size,
2297 mem->va, mem->dma);
6b7c5b94
SP		 2298}
2299
6b7c5b94
SP		 2300static int be_ctrl_init(struct be_adapter *adapter)
2301{
8788fdc2
SP		 2302 struct be_dma_mem *mbox_mem_alloc = &adapter->mbox_mem_alloced;
2303 struct be_dma_mem *mbox_mem_align = &adapter->mbox_mem;
e7b909a6 2304 struct be_dma_mem *mc_cmd_mem = &adapter->mc_cmd_mem;
6b7c5b94 2305 int status;
6b7c5b94
SP		 2306
2307 status = be_map_pci_bars(adapter);
2308 if (status)
e7b909a6 2309 goto done;
6b7c5b94
SP		 2310
2311 mbox_mem_alloc->size = sizeof(struct be_mcc_mailbox) + 16;
2312 mbox_mem_alloc->va = pci_alloc_consistent(adapter->pdev,
2313 mbox_mem_alloc->size, &mbox_mem_alloc->dma);
2314 if (!mbox_mem_alloc->va) {
e7b909a6
SP		 2315 status = -ENOMEM;
2316 goto unmap_pci_bars;
6b7c5b94 2317 }
e7b909a6 2318
6b7c5b94
SP		 2319 mbox_mem_align->size = sizeof(struct be_mcc_mailbox);
2320 mbox_mem_align->va = PTR_ALIGN(mbox_mem_alloc->va, 16);
2321 mbox_mem_align->dma = PTR_ALIGN(mbox_mem_alloc->dma, 16);
2322 memset(mbox_mem_align->va, 0, sizeof(struct be_mcc_mailbox));
e7b909a6
SP		 2323
2324 mc_cmd_mem->size = sizeof(struct be_cmd_req_mcast_mac_config);
2325 mc_cmd_mem->va = pci_alloc_consistent(adapter->pdev, mc_cmd_mem->size,
2326 &mc_cmd_mem->dma);
2327 if (mc_cmd_mem->va == NULL) {
2328 status = -ENOMEM;
2329 goto free_mbox;
2330 }
2331 memset(mc_cmd_mem->va, 0, mc_cmd_mem->size);
2332
8788fdc2
SP		 2333 spin_lock_init(&adapter->mbox_lock);
2334 spin_lock_init(&adapter->mcc_lock);
2335 spin_lock_init(&adapter->mcc_cq_lock);
a8f447bd 2336
dd131e76 2337 init_completion(&adapter->flash_compl);
cf588477 2338 pci_save_state(adapter->pdev);
6b7c5b94 2339 return 0;
e7b909a6
SP		 2340
2341free_mbox:
2342 pci_free_consistent(adapter->pdev, mbox_mem_alloc->size,
2343 mbox_mem_alloc->va, mbox_mem_alloc->dma);
2344
2345unmap_pci_bars:
2346 be_unmap_pci_bars(adapter);
2347
2348done:
2349 return status;
6b7c5b94
SP		 2350}
2351
2352static void be_stats_cleanup(struct be_adapter *adapter)
2353{
2354 struct be_stats_obj *stats = &adapter->stats;
2355 struct be_dma_mem *cmd = &stats->cmd;
2356
2357 if (cmd->va)
2358 pci_free_consistent(adapter->pdev, cmd->size,
2359 cmd->va, cmd->dma);
2360}
2361
2362static int be_stats_init(struct be_adapter *adapter)
2363{
2364 struct be_stats_obj *stats = &adapter->stats;
2365 struct be_dma_mem *cmd = &stats->cmd;
2366
2367 cmd->size = sizeof(struct be_cmd_req_get_stats);
2368 cmd->va = pci_alloc_consistent(adapter->pdev, cmd->size, &cmd->dma);
2369 if (cmd->va == NULL)
2370 return -1;
d291b9af 2371 memset(cmd->va, 0, cmd->size);
6b7c5b94
SP		 2372 return 0;
2373}
2374
2375static void __devexit be_remove(struct pci_dev *pdev)
2376{
2377 struct be_adapter *adapter = pci_get_drvdata(pdev);
8d56ff11 2378
6b7c5b94
SP		 2379 if (!adapter)
2380 return;
2381
2382 unregister_netdev(adapter->netdev);
2383
5fb379ee
SP		 2384 be_clear(adapter);
2385
6b7c5b94
SP		 2386 be_stats_cleanup(adapter);
2387
2388 be_ctrl_cleanup(adapter);
2389
ba343c77
SB		 2390 be_sriov_disable(adapter);
2391
8d56ff11 2392 be_msix_disable(adapter);
6b7c5b94
SP		 2393
2394 pci_set_drvdata(pdev, NULL);
2395 pci_release_regions(pdev);
2396 pci_disable_device(pdev);
2397
2398 free_netdev(adapter->netdev);
2399}
2400
2243e2e9 2401static int be_get_config(struct be_adapter *adapter)
6b7c5b94 2402{
6b7c5b94 2403 int status;
2243e2e9 2404 u8 mac[ETH_ALEN];
6b7c5b94 2405
2243e2e9 2406 status = be_cmd_get_fw_ver(adapter, adapter->fw_ver);
6b7c5b94
SP		 2407 if (status)
2408 return status;
2409
2243e2e9
SP		 2410 status = be_cmd_query_fw_cfg(adapter,
2411 &adapter->port_num, &adapter->cap);
43a04fdc
SP		 2412 if (status)
2413 return status;
2414
2243e2e9 2415 memset(mac, 0, ETH_ALEN);
ba343c77
SB		 2416
2417 if (be_physfn(adapter)) {
2418 status = be_cmd_mac_addr_query(adapter, mac,
2243e2e9 2419 MAC_ADDRESS_TYPE_NETWORK, true /*permanent */, 0);
ca9e4988 2420
ba343c77
SB		 2421 if (status)
2422 return status;
ca9e4988 2423
ba343c77
SB		 2424 if (!is_valid_ether_addr(mac))
2425 return -EADDRNOTAVAIL;
2426
2427 memcpy(adapter->netdev->dev_addr, mac, ETH_ALEN);
2428 memcpy(adapter->netdev->perm_addr, mac, ETH_ALEN);
2429 }
6b7c5b94 2430
82903e4b
AK		 2431 if (adapter->cap & 0x400)
2432 adapter->max_vlans = BE_NUM_VLANS_SUPPORTED/4;
2433 else
2434 adapter->max_vlans = BE_NUM_VLANS_SUPPORTED;
2435
2243e2e9 2436 return 0;
6b7c5b94
SP		 2437}
2438
2439static int __devinit be_probe(struct pci_dev *pdev,
2440 const struct pci_device_id *pdev_id)
2441{
2442 int status = 0;
2443 struct be_adapter *adapter;
2444 struct net_device *netdev;
6b7c5b94 2445
ba343c77 2446
6b7c5b94
SP		 2447 status = pci_enable_device(pdev);
2448 if (status)
2449 goto do_none;
2450
2451 status = pci_request_regions(pdev, DRV_NAME);
2452 if (status)
2453 goto disable_dev;
2454 pci_set_master(pdev);
2455
2456 netdev = alloc_etherdev(sizeof(struct be_adapter));
2457 if (netdev == NULL) {
2458 status = -ENOMEM;
2459 goto rel_reg;
2460 }
2461 adapter = netdev_priv(netdev);
7b139c83
AK		 2462
2463 switch (pdev->device) {
2464 case BE_DEVICE_ID1:
2465 case OC_DEVICE_ID1:
2466 adapter->generation = BE_GEN2;
2467 break;
2468 case BE_DEVICE_ID2:
2469 case OC_DEVICE_ID2:
2470 adapter->generation = BE_GEN3;
2471 break;
2472 default:
2473 adapter->generation = 0;
2474 }
2475
6b7c5b94
SP		 2476 adapter->pdev = pdev;
2477 pci_set_drvdata(pdev, adapter);
2478 adapter->netdev = netdev;
2243e2e9
SP		 2479 be_netdev_init(netdev);
2480 SET_NETDEV_DEV(netdev, &pdev->dev);
6b7c5b94
SP		 2481
2482 be_msix_enable(adapter);
2483
e930438c 2484 status = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
6b7c5b94
SP		 2485 if (!status) {
2486 netdev->features |= NETIF_F_HIGHDMA;
2487 } else {
e930438c 2488 status = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
6b7c5b94
SP		 2489 if (status) {
2490 dev_err(&pdev->dev, "Could not set PCI DMA Mask\n");
2491 goto free_netdev;
2492 }
2493 }
2494
ba343c77
SB		 2495 be_sriov_enable(adapter);
2496
6b7c5b94
SP		 2497 status = be_ctrl_init(adapter);
2498 if (status)
2499 goto free_netdev;
2500
2243e2e9 2501 /* sync up with fw's ready state */
ba343c77
SB		 2502 if (be_physfn(adapter)) {
2503 status = be_cmd_POST(adapter);
2504 if (status)
2505 goto ctrl_clean;
ba343c77 2506 }
6b7c5b94 2507
2243e2e9
SP		 2508 /* tell fw we're ready to fire cmds */
2509 status = be_cmd_fw_init(adapter);
6b7c5b94 2510 if (status)
2243e2e9
SP		 2511 goto ctrl_clean;
2512
556ae191
SB		 2513 if (be_physfn(adapter)) {
2514 status = be_cmd_reset_function(adapter);
2515 if (status)
2516 goto ctrl_clean;
2517 }
2518
2243e2e9
SP		 2519 status = be_stats_init(adapter);
2520 if (status)
2521 goto ctrl_clean;
2522
2523 status = be_get_config(adapter);
6b7c5b94
SP		 2524 if (status)
2525 goto stats_clean;
6b7c5b94
SP		 2526
2527 INIT_DELAYED_WORK(&adapter->work, be_worker);
6b7c5b94 2528
5fb379ee
SP		 2529 status = be_setup(adapter);
2530 if (status)
2531 goto stats_clean;
2243e2e9 2532
6b7c5b94
SP		 2533 status = register_netdev(netdev);
2534 if (status != 0)
5fb379ee 2535 goto unsetup;
6b7c5b94 2536
c4ca2374 2537 dev_info(&pdev->dev, "%s port %d\n", nic_name(pdev), adapter->port_num);
6b7c5b94
SP		 2538 return 0;
2539
5fb379ee
SP		 2540unsetup:
2541 be_clear(adapter);
6b7c5b94
SP		 2542stats_clean:
2543 be_stats_cleanup(adapter);
2544ctrl_clean:
2545 be_ctrl_cleanup(adapter);
2546free_netdev:
8d56ff11 2547 be_msix_disable(adapter);
ba343c77 2548 be_sriov_disable(adapter);
6b7c5b94 2549 free_netdev(adapter->netdev);
8d56ff11 2550 pci_set_drvdata(pdev, NULL);
6b7c5b94
SP		 2551rel_reg:
2552 pci_release_regions(pdev);
2553disable_dev:
2554 pci_disable_device(pdev);
2555do_none:
c4ca2374 2556 dev_err(&pdev->dev, "%s initialization failed\n", nic_name(pdev));
6b7c5b94
SP		 2557 return status;
2558}
2559
2560static int be_suspend(struct pci_dev *pdev, pm_message_t state)
2561{
2562 struct be_adapter *adapter = pci_get_drvdata(pdev);
2563 struct net_device *netdev = adapter->netdev;
2564
71d8d1b5
AK		 2565 if (adapter->wol)
2566 be_setup_wol(adapter, true);
2567
6b7c5b94
SP		 2568 netif_device_detach(netdev);
2569 if (netif_running(netdev)) {
2570 rtnl_lock();
2571 be_close(netdev);
2572 rtnl_unlock();
2573 }
9e90c961 2574 be_cmd_get_flow_control(adapter, &adapter->tx_fc, &adapter->rx_fc);
9b0365f1 2575 be_clear(adapter);
6b7c5b94
SP		 2576
2577 pci_save_state(pdev);
2578 pci_disable_device(pdev);
2579 pci_set_power_state(pdev, pci_choose_state(pdev, state));
2580 return 0;
2581}
2582
2583static int be_resume(struct pci_dev *pdev)
2584{
2585 int status = 0;
2586 struct be_adapter *adapter = pci_get_drvdata(pdev);
2587 struct net_device *netdev = adapter->netdev;
2588
2589 netif_device_detach(netdev);
2590
2591 status = pci_enable_device(pdev);
2592 if (status)
2593 return status;
2594
2595 pci_set_power_state(pdev, 0);
2596 pci_restore_state(pdev);
2597
2243e2e9
SP		 2598 /* tell fw we're ready to fire cmds */
2599 status = be_cmd_fw_init(adapter);
2600 if (status)
2601 return status;
2602
9b0365f1 2603 be_setup(adapter);
6b7c5b94
SP		 2604 if (netif_running(netdev)) {
2605 rtnl_lock();
2606 be_open(netdev);
2607 rtnl_unlock();
2608 }
2609 netif_device_attach(netdev);
71d8d1b5
AK		 2610
2611 if (adapter->wol)
2612 be_setup_wol(adapter, false);
6b7c5b94
SP		 2613 return 0;
2614}
2615
82456b03
SP		 2616/*
2617 * An FLR will stop BE from DMAing any data.
2618 */
2619static void be_shutdown(struct pci_dev *pdev)
2620{
2621 struct be_adapter *adapter = pci_get_drvdata(pdev);
2622 struct net_device *netdev = adapter->netdev;
2623
2624 netif_device_detach(netdev);
2625
2626 be_cmd_reset_function(adapter);
2627
2628 if (adapter->wol)
2629 be_setup_wol(adapter, true);
2630
2631 pci_disable_device(pdev);
82456b03
SP		 2632}
2633
cf588477
SP		 2634static pci_ers_result_t be_eeh_err_detected(struct pci_dev *pdev,
2635 pci_channel_state_t state)
2636{
2637 struct be_adapter *adapter = pci_get_drvdata(pdev);
2638 struct net_device *netdev = adapter->netdev;
2639
2640 dev_err(&adapter->pdev->dev, "EEH error detected\n");
2641
2642 adapter->eeh_err = true;
2643
2644 netif_device_detach(netdev);
2645
2646 if (netif_running(netdev)) {
2647 rtnl_lock();
2648 be_close(netdev);
2649 rtnl_unlock();
2650 }
2651 be_clear(adapter);
2652
2653 if (state == pci_channel_io_perm_failure)
2654 return PCI_ERS_RESULT_DISCONNECT;
2655
2656 pci_disable_device(pdev);
2657
2658 return PCI_ERS_RESULT_NEED_RESET;
2659}
2660
2661static pci_ers_result_t be_eeh_reset(struct pci_dev *pdev)
2662{
2663 struct be_adapter *adapter = pci_get_drvdata(pdev);
2664 int status;
2665
2666 dev_info(&adapter->pdev->dev, "EEH reset\n");
2667 adapter->eeh_err = false;
2668
2669 status = pci_enable_device(pdev);
2670 if (status)
2671 return PCI_ERS_RESULT_DISCONNECT;
2672
2673 pci_set_master(pdev);
2674 pci_set_power_state(pdev, 0);
2675 pci_restore_state(pdev);
2676
2677 /* Check if card is ok and fw is ready */
2678 status = be_cmd_POST(adapter);
2679 if (status)
2680 return PCI_ERS_RESULT_DISCONNECT;
2681
2682 return PCI_ERS_RESULT_RECOVERED;
2683}
2684
2685static void be_eeh_resume(struct pci_dev *pdev)
2686{
2687 int status = 0;
2688 struct be_adapter *adapter = pci_get_drvdata(pdev);
2689 struct net_device *netdev = adapter->netdev;
2690
2691 dev_info(&adapter->pdev->dev, "EEH resume\n");
2692
2693 pci_save_state(pdev);
2694
2695 /* tell fw we're ready to fire cmds */
2696 status = be_cmd_fw_init(adapter);
2697 if (status)
2698 goto err;
2699
2700 status = be_setup(adapter);
2701 if (status)
2702 goto err;
2703
2704 if (netif_running(netdev)) {
2705 status = be_open(netdev);
2706 if (status)
2707 goto err;
2708 }
2709 netif_device_attach(netdev);
2710 return;
2711err:
2712 dev_err(&adapter->pdev->dev, "EEH resume failed\n");
cf588477
SP		 2713}
2714
2715static struct pci_error_handlers be_eeh_handlers = {
2716 .error_detected = be_eeh_err_detected,
2717 .slot_reset = be_eeh_reset,
2718 .resume = be_eeh_resume,
2719};
2720
6b7c5b94
SP		 2721static struct pci_driver be_driver = {
2722 .name = DRV_NAME,
2723 .id_table = be_dev_ids,
2724 .probe = be_probe,
2725 .remove = be_remove,
2726 .suspend = be_suspend,
cf588477 2727 .resume = be_resume,
82456b03 2728 .shutdown = be_shutdown,
cf588477 2729 .err_handler = &be_eeh_handlers
6b7c5b94
SP		 2730};
2731
2732static int __init be_init_module(void)
2733{
8e95a202
JP		 2734 if (rx_frag_size != 8192 && rx_frag_size != 4096 &&
2735 rx_frag_size != 2048) {
6b7c5b94
SP		 2736 printk(KERN_WARNING DRV_NAME
2737 " : Module param rx_frag_size must be 2048/4096/8192."
2738 " Using 2048\n");
2739 rx_frag_size = 2048;
2740 }
6b7c5b94 2741
ba343c77
SB		 2742 if (num_vfs > 32) {
2743 printk(KERN_WARNING DRV_NAME
2744 " : Module param num_vfs must not be greater than 32."
2745 "Using 32\n");
2746 num_vfs = 32;
2747 }
2748
6b7c5b94
SP		 2749 return pci_register_driver(&be_driver);
2750}
2751module_init(be_init_module);
2752
2753static void __exit be_exit_module(void)
2754{
2755 pci_unregister_driver(&be_driver);
2756}
2757module_exit(be_exit_module);
Linux kernel - Deliverables
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