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be2net: refactor code that decides adapter->num_rx_queues
[deliverable/linux.git] / drivers / net / benet / be_main.c
CommitLineData
6b7c5b94 1/*
d2145cde 2 * Copyright (C) 2005 - 2011 Emulex
6b7c5b94
SP		 3 * All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License version 2
7 * as published by the Free Software Foundation. The full GNU General
8 * Public License is included in this distribution in the file called COPYING.
9 *
10 * Contact Information:
d2145cde 11 * linux-drivers@emulex.com
6b7c5b94 12 *
d2145cde
AK		 13 * Emulex
14 * 3333 Susan Street
15 * Costa Mesa, CA 92626
6b7c5b94
SP		 16 */
17
18#include "be.h"
8788fdc2 19#include "be_cmds.h"
65f71b8b 20#include <asm/div64.h>
6b7c5b94
SP		 21
22MODULE_VERSION(DRV_VER);
23MODULE_DEVICE_TABLE(pci, be_dev_ids);
24MODULE_DESCRIPTION(DRV_DESC " " DRV_VER);
25MODULE_AUTHOR("ServerEngines Corporation");
26MODULE_LICENSE("GPL");
27
2e588f84 28static ushort rx_frag_size = 2048;
ba343c77 29static unsigned int num_vfs;
2e588f84 30module_param(rx_frag_size, ushort, S_IRUGO);
ba343c77 31module_param(num_vfs, uint, S_IRUGO);
6b7c5b94 32MODULE_PARM_DESC(rx_frag_size, "Size of a fragment that holds rcvd data.");
ba343c77 33MODULE_PARM_DESC(num_vfs, "Number of PCI VFs to initialize");
6b7c5b94 34
3abcdeda
SP		 35static bool multi_rxq = true;
36module_param(multi_rxq, bool, S_IRUGO | S_IWUSR);
37MODULE_PARM_DESC(multi_rxq, "Multi Rx Queue support. Enabled by default");
38
6b7c5b94 39static DEFINE_PCI_DEVICE_TABLE(be_dev_ids) = {
c4ca2374 40 { PCI_DEVICE(BE_VENDOR_ID, BE_DEVICE_ID1) },
59fd5d87 41 { PCI_DEVICE(BE_VENDOR_ID, BE_DEVICE_ID2) },
c4ca2374
AK		 42 { PCI_DEVICE(BE_VENDOR_ID, OC_DEVICE_ID1) },
43 { PCI_DEVICE(BE_VENDOR_ID, OC_DEVICE_ID2) },
fe6d2a38 44 { PCI_DEVICE(EMULEX_VENDOR_ID, OC_DEVICE_ID3)},
6b7c5b94
SP		 45 { 0 }
46};
47MODULE_DEVICE_TABLE(pci, be_dev_ids);
7c185276
AK		 48/* UE Status Low CSR */
49static char *ue_status_low_desc[] = {
50 "CEV",
51 "CTX",
52 "DBUF",
53 "ERX",
54 "Host",
55 "MPU",
56 "NDMA",
57 "PTC ",
58 "RDMA ",
59 "RXF ",
60 "RXIPS ",
61 "RXULP0 ",
62 "RXULP1 ",
63 "RXULP2 ",
64 "TIM ",
65 "TPOST ",
66 "TPRE ",
67 "TXIPS ",
68 "TXULP0 ",
69 "TXULP1 ",
70 "UC ",
71 "WDMA ",
72 "TXULP2 ",
73 "HOST1 ",
74 "P0_OB_LINK ",
75 "P1_OB_LINK ",
76 "HOST_GPIO ",
77 "MBOX ",
78 "AXGMAC0",
79 "AXGMAC1",
80 "JTAG",
81 "MPU_INTPEND"
82};
83/* UE Status High CSR */
84static char *ue_status_hi_desc[] = {
85 "LPCMEMHOST",
86 "MGMT_MAC",
87 "PCS0ONLINE",
88 "MPU_IRAM",
89 "PCS1ONLINE",
90 "PCTL0",
91 "PCTL1",
92 "PMEM",
93 "RR",
94 "TXPB",
95 "RXPP",
96 "XAUI",
97 "TXP",
98 "ARM",
99 "IPC",
100 "HOST2",
101 "HOST3",
102 "HOST4",
103 "HOST5",
104 "HOST6",
105 "HOST7",
106 "HOST8",
107 "HOST9",
108 "NETC"
109 "Unknown",
110 "Unknown",
111 "Unknown",
112 "Unknown",
113 "Unknown",
114 "Unknown",
115 "Unknown",
116 "Unknown"
117};
6b7c5b94 118
3abcdeda
SP		 119static inline bool be_multi_rxq(struct be_adapter *adapter)
120{
121 return (adapter->num_rx_qs > 1);
122}
123
6b7c5b94
SP		 124static void be_queue_free(struct be_adapter *adapter, struct be_queue_info *q)
125{
126 struct be_dma_mem *mem = &q->dma_mem;
127 if (mem->va)
2b7bcebf
IV		 128 dma_free_coherent(&adapter->pdev->dev, mem->size, mem->va,
129 mem->dma);
6b7c5b94
SP		 130}
131
132static int be_queue_alloc(struct be_adapter *adapter, struct be_queue_info *q,
133 u16 len, u16 entry_size)
134{
135 struct be_dma_mem *mem = &q->dma_mem;
136
137 memset(q, 0, sizeof(*q));
138 q->len = len;
139 q->entry_size = entry_size;
140 mem->size = len * entry_size;
2b7bcebf
IV		 141 mem->va = dma_alloc_coherent(&adapter->pdev->dev, mem->size, &mem->dma,
142 GFP_KERNEL);
6b7c5b94
SP		 143 if (!mem->va)
144 return -1;
145 memset(mem->va, 0, mem->size);
146 return 0;
147}
148
8788fdc2 149static void be_intr_set(struct be_adapter *adapter, bool enable)
6b7c5b94 150{
8788fdc2 151 u8 __iomem *addr = adapter->pcicfg + PCICFG_MEMBAR_CTRL_INT_CTRL_OFFSET;
6b7c5b94
SP		 152 u32 reg = ioread32(addr);
153 u32 enabled = reg & MEMBAR_CTRL_INT_CTRL_HOSTINTR_MASK;
5f0b849e 154
cf588477
SP		 155 if (adapter->eeh_err)
156 return;
157
5f0b849e 158 if (!enabled && enable)
6b7c5b94 159 reg |= MEMBAR_CTRL_INT_CTRL_HOSTINTR_MASK;
5f0b849e 160 else if (enabled && !enable)
6b7c5b94 161 reg &= ~MEMBAR_CTRL_INT_CTRL_HOSTINTR_MASK;
5f0b849e 162 else
6b7c5b94 163 return;
5f0b849e 164
6b7c5b94
SP		 165 iowrite32(reg, addr);
166}
167
8788fdc2 168static void be_rxq_notify(struct be_adapter *adapter, u16 qid, u16 posted)
6b7c5b94
SP		 169{
170 u32 val = 0;
171 val |= qid & DB_RQ_RING_ID_MASK;
172 val |= posted << DB_RQ_NUM_POSTED_SHIFT;
f3eb62d2
SP		 173
174 wmb();
8788fdc2 175 iowrite32(val, adapter->db + DB_RQ_OFFSET);
6b7c5b94
SP		 176}
177
8788fdc2 178static void be_txq_notify(struct be_adapter *adapter, u16 qid, u16 posted)
6b7c5b94
SP		 179{
180 u32 val = 0;
181 val |= qid & DB_TXULP_RING_ID_MASK;
182 val |= (posted & DB_TXULP_NUM_POSTED_MASK) << DB_TXULP_NUM_POSTED_SHIFT;
f3eb62d2
SP		 183
184 wmb();
8788fdc2 185 iowrite32(val, adapter->db + DB_TXULP1_OFFSET);
6b7c5b94
SP		 186}
187
8788fdc2 188static void be_eq_notify(struct be_adapter *adapter, u16 qid,
6b7c5b94
SP		 189 bool arm, bool clear_int, u16 num_popped)
190{
191 u32 val = 0;
192 val |= qid & DB_EQ_RING_ID_MASK;
fe6d2a38
SP		 193 val |= ((qid & DB_EQ_RING_ID_EXT_MASK) <<
194 DB_EQ_RING_ID_EXT_MASK_SHIFT);
cf588477
SP		 195
196 if (adapter->eeh_err)
197 return;
198
6b7c5b94
SP		 199 if (arm)
200 val |= 1 << DB_EQ_REARM_SHIFT;
201 if (clear_int)
202 val |= 1 << DB_EQ_CLR_SHIFT;
203 val |= 1 << DB_EQ_EVNT_SHIFT;
204 val |= num_popped << DB_EQ_NUM_POPPED_SHIFT;
8788fdc2 205 iowrite32(val, adapter->db + DB_EQ_OFFSET);
6b7c5b94
SP		 206}
207
8788fdc2 208void be_cq_notify(struct be_adapter *adapter, u16 qid, bool arm, u16 num_popped)
6b7c5b94
SP		 209{
210 u32 val = 0;
211 val |= qid & DB_CQ_RING_ID_MASK;
fe6d2a38
SP		 212 val |= ((qid & DB_CQ_RING_ID_EXT_MASK) <<
213 DB_CQ_RING_ID_EXT_MASK_SHIFT);
cf588477
SP		 214
215 if (adapter->eeh_err)
216 return;
217
6b7c5b94
SP		 218 if (arm)
219 val |= 1 << DB_CQ_REARM_SHIFT;
220 val |= num_popped << DB_CQ_NUM_POPPED_SHIFT;
8788fdc2 221 iowrite32(val, adapter->db + DB_CQ_OFFSET);
6b7c5b94
SP		 222}
223
6b7c5b94
SP		 224static int be_mac_addr_set(struct net_device *netdev, void *p)
225{
226 struct be_adapter *adapter = netdev_priv(netdev);
227 struct sockaddr *addr = p;
228 int status = 0;
229
ca9e4988
AK		 230 if (!is_valid_ether_addr(addr->sa_data))
231 return -EADDRNOTAVAIL;
232
ba343c77
SB		 233 /* MAC addr configuration will be done in hardware for VFs
234 * by their corresponding PFs. Just copy to netdev addr here
235 */
236 if (!be_physfn(adapter))
237 goto netdev_addr;
238
f8617e08
AK		 239 status = be_cmd_pmac_del(adapter, adapter->if_handle,
240 adapter->pmac_id, 0);
a65027e4
SP		 241 if (status)
242 return status;
6b7c5b94 243
a65027e4 244 status = be_cmd_pmac_add(adapter, (u8 *)addr->sa_data,
f8617e08 245 adapter->if_handle, &adapter->pmac_id, 0);
ba343c77 246netdev_addr:
6b7c5b94
SP		 247 if (!status)
248 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
249
250 return status;
251}
252
b31c50a7 253void netdev_stats_update(struct be_adapter *adapter)
6b7c5b94 254{
3abcdeda 255 struct be_hw_stats *hw_stats = hw_stats_from_cmd(adapter->stats_cmd.va);
6b7c5b94
SP		 256 struct be_rxf_stats *rxf_stats = &hw_stats->rxf;
257 struct be_port_rxf_stats *port_stats =
258 &rxf_stats->port[adapter->port_num];
78122a52 259 struct net_device_stats *dev_stats = &adapter->netdev->stats;
68110868 260 struct be_erx_stats *erx_stats = &hw_stats->erx;
3abcdeda
SP		 261 struct be_rx_obj *rxo;
262 int i;
6b7c5b94 263
3abcdeda
SP		 264 memset(dev_stats, 0, sizeof(*dev_stats));
265 for_all_rx_queues(adapter, rxo, i) {
266 dev_stats->rx_packets += rx_stats(rxo)->rx_pkts;
267 dev_stats->rx_bytes += rx_stats(rxo)->rx_bytes;
268 dev_stats->multicast += rx_stats(rxo)->rx_mcast_pkts;
269 /* no space in linux buffers: best possible approximation */
270 dev_stats->rx_dropped +=
271 erx_stats->rx_drops_no_fragments[rxo->q.id];
272 }
273
274 dev_stats->tx_packets = tx_stats(adapter)->be_tx_pkts;
275 dev_stats->tx_bytes = tx_stats(adapter)->be_tx_bytes;
6b7c5b94
SP		 276
277 /* bad pkts received */
278 dev_stats->rx_errors = port_stats->rx_crc_errors +
279 port_stats->rx_alignment_symbol_errors +
280 port_stats->rx_in_range_errors +
68110868
SP		 281 port_stats->rx_out_range_errors +
282 port_stats->rx_frame_too_long +
283 port_stats->rx_dropped_too_small +
284 port_stats->rx_dropped_too_short +
285 port_stats->rx_dropped_header_too_small +
286 port_stats->rx_dropped_tcp_length +
287 port_stats->rx_dropped_runt +
288 port_stats->rx_tcp_checksum_errs +
289 port_stats->rx_ip_checksum_errs +
290 port_stats->rx_udp_checksum_errs;
291
6b7c5b94
SP		 292 /* detailed rx errors */
293 dev_stats->rx_length_errors = port_stats->rx_in_range_errors +
68110868
SP		 294 port_stats->rx_out_range_errors +
295 port_stats->rx_frame_too_long;
296
6b7c5b94
SP		 297 dev_stats->rx_crc_errors = port_stats->rx_crc_errors;
298
299 /* frame alignment errors */
300 dev_stats->rx_frame_errors = port_stats->rx_alignment_symbol_errors;
68110868 301
6b7c5b94
SP		 302 /* receiver fifo overrun */
303 /* drops_no_pbuf is no per i/f, it's per BE card */
304 dev_stats->rx_fifo_errors = port_stats->rx_fifo_overflow +
305 port_stats->rx_input_fifo_overflow +
306 rxf_stats->rx_drops_no_pbuf;
6b7c5b94
SP		 307}
308
8788fdc2 309void be_link_status_update(struct be_adapter *adapter, bool link_up)
6b7c5b94 310{
6b7c5b94
SP		 311 struct net_device *netdev = adapter->netdev;
312
6b7c5b94 313 /* If link came up or went down */
a8f447bd 314 if (adapter->link_up != link_up) {
0dffc83e 315 adapter->link_speed = -1;
a8f447bd 316 if (link_up) {
6b7c5b94
SP		 317 netif_carrier_on(netdev);
318 printk(KERN_INFO "%s: Link up\n", netdev->name);
a8f447bd 319 } else {
a8f447bd
SP		 320 netif_carrier_off(netdev);
321 printk(KERN_INFO "%s: Link down\n", netdev->name);
6b7c5b94 322 }
a8f447bd 323 adapter->link_up = link_up;
6b7c5b94 324 }
6b7c5b94
SP		 325}
326
327/* Update the EQ delay n BE based on the RX frags consumed / sec */
3abcdeda 328static void be_rx_eqd_update(struct be_adapter *adapter, struct be_rx_obj *rxo)
6b7c5b94 329{
3abcdeda
SP		 330 struct be_eq_obj *rx_eq = &rxo->rx_eq;
331 struct be_rx_stats *stats = &rxo->stats;
4097f663
SP		 332 ulong now = jiffies;
333 u32 eqd;
334
335 if (!rx_eq->enable_aic)
336 return;
337
338 /* Wrapped around */
339 if (time_before(now, stats->rx_fps_jiffies)) {
340 stats->rx_fps_jiffies = now;
341 return;
342 }
6b7c5b94
SP		 343
344 /* Update once a second */
4097f663 345 if ((now - stats->rx_fps_jiffies) < HZ)
6b7c5b94
SP		 346 return;
347
3abcdeda 348 stats->rx_fps = (stats->rx_frags - stats->prev_rx_frags) /
4097f663 349 ((now - stats->rx_fps_jiffies) / HZ);
6b7c5b94 350
4097f663 351 stats->rx_fps_jiffies = now;
3abcdeda
SP		 352 stats->prev_rx_frags = stats->rx_frags;
353 eqd = stats->rx_fps / 110000;
6b7c5b94
SP		 354 eqd = eqd << 3;
355 if (eqd > rx_eq->max_eqd)
356 eqd = rx_eq->max_eqd;
357 if (eqd < rx_eq->min_eqd)
358 eqd = rx_eq->min_eqd;
359 if (eqd < 10)
360 eqd = 0;
361 if (eqd != rx_eq->cur_eqd)
8788fdc2 362 be_cmd_modify_eqd(adapter, rx_eq->q.id, eqd);
6b7c5b94
SP		 363
364 rx_eq->cur_eqd = eqd;
365}
366
65f71b8b
SH		 367static u32 be_calc_rate(u64 bytes, unsigned long ticks)
368{
369 u64 rate = bytes;
370
371 do_div(rate, ticks / HZ);
372 rate <<= 3; /* bytes/sec -> bits/sec */
373 do_div(rate, 1000000ul); /* MB/Sec */
374
375 return rate;
376}
377
4097f663
SP		 378static void be_tx_rate_update(struct be_adapter *adapter)
379{
3abcdeda 380 struct be_tx_stats *stats = tx_stats(adapter);
4097f663
SP		 381 ulong now = jiffies;
382
383 /* Wrapped around? */
384 if (time_before(now, stats->be_tx_jiffies)) {
385 stats->be_tx_jiffies = now;
386 return;
387 }
388
389 /* Update tx rate once in two seconds */
390 if ((now - stats->be_tx_jiffies) > 2 * HZ) {
65f71b8b
SH		 391 stats->be_tx_rate = be_calc_rate(stats->be_tx_bytes
392 - stats->be_tx_bytes_prev,
393 now - stats->be_tx_jiffies);
4097f663
SP		 394 stats->be_tx_jiffies = now;
395 stats->be_tx_bytes_prev = stats->be_tx_bytes;
396 }
397}
398
6b7c5b94 399static void be_tx_stats_update(struct be_adapter *adapter,
91992e44 400 u32 wrb_cnt, u32 copied, u32 gso_segs, bool stopped)
6b7c5b94 401{
3abcdeda 402 struct be_tx_stats *stats = tx_stats(adapter);
6b7c5b94
SP		 403 stats->be_tx_reqs++;
404 stats->be_tx_wrbs += wrb_cnt;
405 stats->be_tx_bytes += copied;
91992e44 406 stats->be_tx_pkts += (gso_segs ? gso_segs : 1);
6b7c5b94
SP		 407 if (stopped)
408 stats->be_tx_stops++;
6b7c5b94
SP		 409}
410
411/* Determine number of WRB entries needed to xmit data in an skb */
fe6d2a38
SP		 412static u32 wrb_cnt_for_skb(struct be_adapter *adapter, struct sk_buff *skb,
413 bool *dummy)
6b7c5b94 414{
ebc8d2ab
DM		 415 int cnt = (skb->len > skb->data_len);
416
417 cnt += skb_shinfo(skb)->nr_frags;
418
6b7c5b94
SP		 419 /* to account for hdr wrb */
420 cnt++;
fe6d2a38
SP		 421 if (lancer_chip(adapter) || !(cnt & 1)) {
422 *dummy = false;
423 } else {
6b7c5b94
SP		 424 /* add a dummy to make it an even num */
425 cnt++;
426 *dummy = true;
fe6d2a38 427 }
6b7c5b94
SP		 428 BUG_ON(cnt > BE_MAX_TX_FRAG_COUNT);
429 return cnt;
430}
431
432static inline void wrb_fill(struct be_eth_wrb *wrb, u64 addr, int len)
433{
434 wrb->frag_pa_hi = upper_32_bits(addr);
435 wrb->frag_pa_lo = addr & 0xFFFFFFFF;
436 wrb->frag_len = len & ETH_WRB_FRAG_LEN_MASK;
437}
438
cc4ce020
SK		 439static void wrb_fill_hdr(struct be_adapter *adapter, struct be_eth_hdr_wrb *hdr,
440 struct sk_buff *skb, u32 wrb_cnt, u32 len)
6b7c5b94 441{
cc4ce020
SK		 442 u8 vlan_prio = 0;
443 u16 vlan_tag = 0;
444
6b7c5b94
SP		 445 memset(hdr, 0, sizeof(*hdr));
446
447 AMAP_SET_BITS(struct amap_eth_hdr_wrb, crc, hdr, 1);
448
49e4b847 449 if (skb_is_gso(skb)) {
6b7c5b94
SP		 450 AMAP_SET_BITS(struct amap_eth_hdr_wrb, lso, hdr, 1);
451 AMAP_SET_BITS(struct amap_eth_hdr_wrb, lso_mss,
452 hdr, skb_shinfo(skb)->gso_size);
fe6d2a38 453 if (skb_is_gso_v6(skb) && !lancer_chip(adapter))
49e4b847 454 AMAP_SET_BITS(struct amap_eth_hdr_wrb, lso6, hdr, 1);
fe6d2a38
SP		 455 if (lancer_chip(adapter) && adapter->sli_family ==
456 LANCER_A0_SLI_FAMILY) {
457 AMAP_SET_BITS(struct amap_eth_hdr_wrb, ipcs, hdr, 1);
458 if (is_tcp_pkt(skb))
459 AMAP_SET_BITS(struct amap_eth_hdr_wrb,
460 tcpcs, hdr, 1);
461 else if (is_udp_pkt(skb))
462 AMAP_SET_BITS(struct amap_eth_hdr_wrb,
463 udpcs, hdr, 1);
464 }
6b7c5b94
SP		 465 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
466 if (is_tcp_pkt(skb))
467 AMAP_SET_BITS(struct amap_eth_hdr_wrb, tcpcs, hdr, 1);
468 else if (is_udp_pkt(skb))
469 AMAP_SET_BITS(struct amap_eth_hdr_wrb, udpcs, hdr, 1);
470 }
471
cc4ce020 472 if (adapter->vlan_grp && vlan_tx_tag_present(skb)) {
6b7c5b94 473 AMAP_SET_BITS(struct amap_eth_hdr_wrb, vlan, hdr, 1);
cc4ce020
SK		 474 vlan_tag = vlan_tx_tag_get(skb);
475 vlan_prio = (vlan_tag & VLAN_PRIO_MASK) >> VLAN_PRIO_SHIFT;
476 /* If vlan priority provided by OS is NOT in available bmap */
477 if (!(adapter->vlan_prio_bmap & (1 << vlan_prio)))
478 vlan_tag = (vlan_tag & ~VLAN_PRIO_MASK) |
479 adapter->recommended_prio;
480 AMAP_SET_BITS(struct amap_eth_hdr_wrb, vlan_tag, hdr, vlan_tag);
6b7c5b94
SP		 481 }
482
483 AMAP_SET_BITS(struct amap_eth_hdr_wrb, event, hdr, 1);
484 AMAP_SET_BITS(struct amap_eth_hdr_wrb, complete, hdr, 1);
485 AMAP_SET_BITS(struct amap_eth_hdr_wrb, num_wrb, hdr, wrb_cnt);
486 AMAP_SET_BITS(struct amap_eth_hdr_wrb, len, hdr, len);
487}
488
2b7bcebf 489static void unmap_tx_frag(struct device *dev, struct be_eth_wrb *wrb,
7101e111
SP		 490 bool unmap_single)
491{
492 dma_addr_t dma;
493
494 be_dws_le_to_cpu(wrb, sizeof(*wrb));
495
496 dma = (u64)wrb->frag_pa_hi << 32 | (u64)wrb->frag_pa_lo;
b681ee77 497 if (wrb->frag_len) {
7101e111 498 if (unmap_single)
2b7bcebf
IV		 499 dma_unmap_single(dev, dma, wrb->frag_len,
500 DMA_TO_DEVICE);
7101e111 501 else
2b7bcebf 502 dma_unmap_page(dev, dma, wrb->frag_len, DMA_TO_DEVICE);
7101e111
SP		 503 }
504}
6b7c5b94
SP		 505
506static int make_tx_wrbs(struct be_adapter *adapter,
507 struct sk_buff *skb, u32 wrb_cnt, bool dummy_wrb)
508{
7101e111
SP		 509 dma_addr_t busaddr;
510 int i, copied = 0;
2b7bcebf 511 struct device *dev = &adapter->pdev->dev;
6b7c5b94
SP		 512 struct sk_buff *first_skb = skb;
513 struct be_queue_info *txq = &adapter->tx_obj.q;
514 struct be_eth_wrb *wrb;
515 struct be_eth_hdr_wrb *hdr;
7101e111
SP		 516 bool map_single = false;
517 u16 map_head;
6b7c5b94 518
6b7c5b94
SP		 519 hdr = queue_head_node(txq);
520 queue_head_inc(txq);
7101e111 521 map_head = txq->head;
6b7c5b94 522
ebc8d2ab 523 if (skb->len > skb->data_len) {
e743d313 524 int len = skb_headlen(skb);
2b7bcebf
IV		 525 busaddr = dma_map_single(dev, skb->data, len, DMA_TO_DEVICE);
526 if (dma_mapping_error(dev, busaddr))
7101e111
SP		 527 goto dma_err;
528 map_single = true;
ebc8d2ab
DM		 529 wrb = queue_head_node(txq);
530 wrb_fill(wrb, busaddr, len);
531 be_dws_cpu_to_le(wrb, sizeof(*wrb));
532 queue_head_inc(txq);
533 copied += len;
534 }
6b7c5b94 535
ebc8d2ab
DM		 536 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
537 struct skb_frag_struct *frag =
538 &skb_shinfo(skb)->frags[i];
2b7bcebf
IV		 539 busaddr = dma_map_page(dev, frag->page, frag->page_offset,
540 frag->size, DMA_TO_DEVICE);
541 if (dma_mapping_error(dev, busaddr))
7101e111 542 goto dma_err;
ebc8d2ab
DM		 543 wrb = queue_head_node(txq);
544 wrb_fill(wrb, busaddr, frag->size);
545 be_dws_cpu_to_le(wrb, sizeof(*wrb));
546 queue_head_inc(txq);
547 copied += frag->size;
6b7c5b94
SP		 548 }
549
550 if (dummy_wrb) {
551 wrb = queue_head_node(txq);
552 wrb_fill(wrb, 0, 0);
553 be_dws_cpu_to_le(wrb, sizeof(*wrb));
554 queue_head_inc(txq);
555 }
556
cc4ce020 557 wrb_fill_hdr(adapter, hdr, first_skb, wrb_cnt, copied);
6b7c5b94
SP		 558 be_dws_cpu_to_le(hdr, sizeof(*hdr));
559
560 return copied;
7101e111
SP		 561dma_err:
562 txq->head = map_head;
563 while (copied) {
564 wrb = queue_head_node(txq);
2b7bcebf 565 unmap_tx_frag(dev, wrb, map_single);
7101e111
SP		 566 map_single = false;
567 copied -= wrb->frag_len;
568 queue_head_inc(txq);
569 }
570 return 0;
6b7c5b94
SP		 571}
572
61357325 573static netdev_tx_t be_xmit(struct sk_buff *skb,
b31c50a7 574 struct net_device *netdev)
6b7c5b94
SP		 575{
576 struct be_adapter *adapter = netdev_priv(netdev);
577 struct be_tx_obj *tx_obj = &adapter->tx_obj;
578 struct be_queue_info *txq = &tx_obj->q;
579 u32 wrb_cnt = 0, copied = 0;
580 u32 start = txq->head;
581 bool dummy_wrb, stopped = false;
582
fe6d2a38 583 wrb_cnt = wrb_cnt_for_skb(adapter, skb, &dummy_wrb);
6b7c5b94
SP		 584
585 copied = make_tx_wrbs(adapter, skb, wrb_cnt, dummy_wrb);
c190e3c8
AK		 586 if (copied) {
587 /* record the sent skb in the sent_skb table */
588 BUG_ON(tx_obj->sent_skb_list[start]);
589 tx_obj->sent_skb_list[start] = skb;
590
591 /* Ensure txq has space for the next skb; Else stop the queue
592 * *BEFORE* ringing the tx doorbell, so that we serialze the
593 * tx compls of the current transmit which'll wake up the queue
594 */
7101e111 595 atomic_add(wrb_cnt, &txq->used);
c190e3c8
AK		 596 if ((BE_MAX_TX_FRAG_COUNT + atomic_read(&txq->used)) >=
597 txq->len) {
598 netif_stop_queue(netdev);
599 stopped = true;
600 }
6b7c5b94 601
c190e3c8 602 be_txq_notify(adapter, txq->id, wrb_cnt);
6b7c5b94 603
91992e44
AK		 604 be_tx_stats_update(adapter, wrb_cnt, copied,
605 skb_shinfo(skb)->gso_segs, stopped);
c190e3c8
AK		 606 } else {
607 txq->head = start;
608 dev_kfree_skb_any(skb);
6b7c5b94 609 }
6b7c5b94
SP		 610 return NETDEV_TX_OK;
611}
612
613static int be_change_mtu(struct net_device *netdev, int new_mtu)
614{
615 struct be_adapter *adapter = netdev_priv(netdev);
616 if (new_mtu < BE_MIN_MTU ||
34a89b8c
AK		 617 new_mtu > (BE_MAX_JUMBO_FRAME_SIZE -
618 (ETH_HLEN + ETH_FCS_LEN))) {
6b7c5b94
SP		 619 dev_info(&adapter->pdev->dev,
620 "MTU must be between %d and %d bytes\n",
34a89b8c
AK		 621 BE_MIN_MTU,
622 (BE_MAX_JUMBO_FRAME_SIZE - (ETH_HLEN + ETH_FCS_LEN)));
6b7c5b94
SP		 623 return -EINVAL;
624 }
625 dev_info(&adapter->pdev->dev, "MTU changed from %d to %d bytes\n",
626 netdev->mtu, new_mtu);
627 netdev->mtu = new_mtu;
628 return 0;
629}
630
631/*
82903e4b
AK		 632 * A max of 64 (BE_NUM_VLANS_SUPPORTED) vlans can be configured in BE.
633 * If the user configures more, place BE in vlan promiscuous mode.
6b7c5b94 634 */
1da87b7f 635static int be_vid_config(struct be_adapter *adapter, bool vf, u32 vf_num)
6b7c5b94 636{
6b7c5b94
SP		 637 u16 vtag[BE_NUM_VLANS_SUPPORTED];
638 u16 ntags = 0, i;
82903e4b 639 int status = 0;
1da87b7f
AK		 640 u32 if_handle;
641
642 if (vf) {
643 if_handle = adapter->vf_cfg[vf_num].vf_if_handle;
644 vtag[0] = cpu_to_le16(adapter->vf_cfg[vf_num].vf_vlan_tag);
645 status = be_cmd_vlan_config(adapter, if_handle, vtag, 1, 1, 0);
646 }
6b7c5b94 647
82903e4b 648 if (adapter->vlans_added <= adapter->max_vlans) {
6b7c5b94 649 /* Construct VLAN Table to give to HW */
b738127d 650 for (i = 0; i < VLAN_N_VID; i++) {
6b7c5b94
SP		 651 if (adapter->vlan_tag[i]) {
652 vtag[ntags] = cpu_to_le16(i);
653 ntags++;
654 }
655 }
b31c50a7
SP		 656 status = be_cmd_vlan_config(adapter, adapter->if_handle,
657 vtag, ntags, 1, 0);
6b7c5b94 658 } else {
b31c50a7
SP		 659 status = be_cmd_vlan_config(adapter, adapter->if_handle,
660 NULL, 0, 1, 1);
6b7c5b94 661 }
1da87b7f 662
b31c50a7 663 return status;
6b7c5b94
SP		 664}
665
666static void be_vlan_register(struct net_device *netdev, struct vlan_group *grp)
667{
668 struct be_adapter *adapter = netdev_priv(netdev);
6b7c5b94 669
6b7c5b94 670 adapter->vlan_grp = grp;
6b7c5b94
SP		 671}
672
673static void be_vlan_add_vid(struct net_device *netdev, u16 vid)
674{
675 struct be_adapter *adapter = netdev_priv(netdev);
676
1da87b7f 677 adapter->vlans_added++;
ba343c77
SB		 678 if (!be_physfn(adapter))
679 return;
680
6b7c5b94 681 adapter->vlan_tag[vid] = 1;
82903e4b 682 if (adapter->vlans_added <= (adapter->max_vlans + 1))
1da87b7f 683 be_vid_config(adapter, false, 0);
6b7c5b94
SP		 684}
685
686static void be_vlan_rem_vid(struct net_device *netdev, u16 vid)
687{
688 struct be_adapter *adapter = netdev_priv(netdev);
689
1da87b7f
AK		 690 adapter->vlans_added--;
691 vlan_group_set_device(adapter->vlan_grp, vid, NULL);
692
ba343c77
SB		 693 if (!be_physfn(adapter))
694 return;
695
6b7c5b94 696 adapter->vlan_tag[vid] = 0;
82903e4b 697 if (adapter->vlans_added <= adapter->max_vlans)
1da87b7f 698 be_vid_config(adapter, false, 0);
6b7c5b94
SP		 699}
700
24307eef 701static void be_set_multicast_list(struct net_device *netdev)
6b7c5b94
SP		 702{
703 struct be_adapter *adapter = netdev_priv(netdev);
6b7c5b94 704
24307eef 705 if (netdev->flags & IFF_PROMISC) {
8788fdc2 706 be_cmd_promiscuous_config(adapter, adapter->port_num, 1);
24307eef
SP		 707 adapter->promiscuous = true;
708 goto done;
6b7c5b94
SP		 709 }
710
24307eef
SP		 711 /* BE was previously in promiscous mode; disable it */
712 if (adapter->promiscuous) {
713 adapter->promiscuous = false;
8788fdc2 714 be_cmd_promiscuous_config(adapter, adapter->port_num, 0);
6b7c5b94
SP		 715 }
716
e7b909a6 717 /* Enable multicast promisc if num configured exceeds what we support */
4cd24eaf
JP		 718 if (netdev->flags & IFF_ALLMULTI ||
719 netdev_mc_count(netdev) > BE_MAX_MC) {
0ddf477b 720 be_cmd_multicast_set(adapter, adapter->if_handle, NULL,
e7b909a6 721 &adapter->mc_cmd_mem);
24307eef 722 goto done;
6b7c5b94 723 }
6b7c5b94 724
0ddf477b 725 be_cmd_multicast_set(adapter, adapter->if_handle, netdev,
f31e50a8 726 &adapter->mc_cmd_mem);
24307eef
SP		 727done:
728 return;
6b7c5b94
SP		 729}
730
ba343c77
SB		 731static int be_set_vf_mac(struct net_device *netdev, int vf, u8 *mac)
732{
733 struct be_adapter *adapter = netdev_priv(netdev);
734 int status;
735
736 if (!adapter->sriov_enabled)
737 return -EPERM;
738
739 if (!is_valid_ether_addr(mac) || (vf >= num_vfs))
740 return -EINVAL;
741
64600ea5
AK		 742 if (adapter->vf_cfg[vf].vf_pmac_id != BE_INVALID_PMAC_ID)
743 status = be_cmd_pmac_del(adapter,
744 adapter->vf_cfg[vf].vf_if_handle,
f8617e08 745 adapter->vf_cfg[vf].vf_pmac_id, vf + 1);
ba343c77 746
64600ea5
AK		 747 status = be_cmd_pmac_add(adapter, mac,
748 adapter->vf_cfg[vf].vf_if_handle,
f8617e08 749 &adapter->vf_cfg[vf].vf_pmac_id, vf + 1);
64600ea5
AK		 750
751 if (status)
ba343c77
SB		 752 dev_err(&adapter->pdev->dev, "MAC %pM set on VF %d Failed\n",
753 mac, vf);
64600ea5
AK		 754 else
755 memcpy(adapter->vf_cfg[vf].vf_mac_addr, mac, ETH_ALEN);
756
ba343c77
SB		 757 return status;
758}
759
64600ea5
AK		 760static int be_get_vf_config(struct net_device *netdev, int vf,
761 struct ifla_vf_info *vi)
762{
763 struct be_adapter *adapter = netdev_priv(netdev);
764
765 if (!adapter->sriov_enabled)
766 return -EPERM;
767
768 if (vf >= num_vfs)
769 return -EINVAL;
770
771 vi->vf = vf;
e1d18735 772 vi->tx_rate = adapter->vf_cfg[vf].vf_tx_rate;
1da87b7f 773 vi->vlan = adapter->vf_cfg[vf].vf_vlan_tag;
64600ea5
AK		 774 vi->qos = 0;
775 memcpy(&vi->mac, adapter->vf_cfg[vf].vf_mac_addr, ETH_ALEN);
776
777 return 0;
778}
779
1da87b7f
AK		 780static int be_set_vf_vlan(struct net_device *netdev,
781 int vf, u16 vlan, u8 qos)
782{
783 struct be_adapter *adapter = netdev_priv(netdev);
784 int status = 0;
785
786 if (!adapter->sriov_enabled)
787 return -EPERM;
788
789 if ((vf >= num_vfs) || (vlan > 4095))
790 return -EINVAL;
791
792 if (vlan) {
793 adapter->vf_cfg[vf].vf_vlan_tag = vlan;
794 adapter->vlans_added++;
795 } else {
796 adapter->vf_cfg[vf].vf_vlan_tag = 0;
797 adapter->vlans_added--;
798 }
799
800 status = be_vid_config(adapter, true, vf);
801
802 if (status)
803 dev_info(&adapter->pdev->dev,
804 "VLAN %d config on VF %d failed\n", vlan, vf);
805 return status;
806}
807
e1d18735
AK		 808static int be_set_vf_tx_rate(struct net_device *netdev,
809 int vf, int rate)
810{
811 struct be_adapter *adapter = netdev_priv(netdev);
812 int status = 0;
813
814 if (!adapter->sriov_enabled)
815 return -EPERM;
816
817 if ((vf >= num_vfs) || (rate < 0))
818 return -EINVAL;
819
820 if (rate > 10000)
821 rate = 10000;
822
823 adapter->vf_cfg[vf].vf_tx_rate = rate;
856c4012 824 status = be_cmd_set_qos(adapter, rate / 10, vf + 1);
e1d18735
AK		 825
826 if (status)
827 dev_info(&adapter->pdev->dev,
828 "tx rate %d on VF %d failed\n", rate, vf);
829 return status;
830}
831
3abcdeda 832static void be_rx_rate_update(struct be_rx_obj *rxo)
6b7c5b94 833{
3abcdeda 834 struct be_rx_stats *stats = &rxo->stats;
4097f663 835 ulong now = jiffies;
6b7c5b94 836
4097f663 837 /* Wrapped around */
3abcdeda
SP		 838 if (time_before(now, stats->rx_jiffies)) {
839 stats->rx_jiffies = now;
4097f663
SP		 840 return;
841 }
6b7c5b94
SP		 842
843 /* Update the rate once in two seconds */
3abcdeda 844 if ((now - stats->rx_jiffies) < 2 * HZ)
6b7c5b94
SP		 845 return;
846
3abcdeda
SP		 847 stats->rx_rate = be_calc_rate(stats->rx_bytes - stats->rx_bytes_prev,
848 now - stats->rx_jiffies);
849 stats->rx_jiffies = now;
850 stats->rx_bytes_prev = stats->rx_bytes;
6b7c5b94
SP		 851}
852
3abcdeda 853static void be_rx_stats_update(struct be_rx_obj *rxo,
2e588f84 854 struct be_rx_compl_info *rxcp)
4097f663 855{
3abcdeda 856 struct be_rx_stats *stats = &rxo->stats;
1ef78abe 857
3abcdeda 858 stats->rx_compl++;
2e588f84
SP		 859 stats->rx_frags += rxcp->num_rcvd;
860 stats->rx_bytes += rxcp->pkt_size;
3abcdeda 861 stats->rx_pkts++;
2e588f84 862 if (rxcp->pkt_type == BE_MULTICAST_PACKET)
3abcdeda 863 stats->rx_mcast_pkts++;
2e588f84
SP		 864 if (rxcp->err)
865 stats->rxcp_err++;
4097f663
SP		 866}
867
2e588f84 868static inline bool csum_passed(struct be_rx_compl_info *rxcp)
728a9972 869{
19fad86f
PR		 870 /* L4 checksum is not reliable for non TCP/UDP packets.
871 * Also ignore ipcksm for ipv6 pkts */
2e588f84
SP		 872 return (rxcp->tcpf || rxcp->udpf) && rxcp->l4_csum &&
873 (rxcp->ip_csum || rxcp->ipv6);
728a9972
AK		 874}
875
6b7c5b94 876static struct be_rx_page_info *
3abcdeda
SP		 877get_rx_page_info(struct be_adapter *adapter,
878 struct be_rx_obj *rxo,
879 u16 frag_idx)
6b7c5b94
SP		 880{
881 struct be_rx_page_info *rx_page_info;
3abcdeda 882 struct be_queue_info *rxq = &rxo->q;
6b7c5b94 883
3abcdeda 884 rx_page_info = &rxo->page_info_tbl[frag_idx];
6b7c5b94
SP		 885 BUG_ON(!rx_page_info->page);
886
205859a2 887 if (rx_page_info->last_page_user) {
2b7bcebf
IV		 888 dma_unmap_page(&adapter->pdev->dev,
889 dma_unmap_addr(rx_page_info, bus),
890 adapter->big_page_size, DMA_FROM_DEVICE);
205859a2
AK		 891 rx_page_info->last_page_user = false;
892 }
6b7c5b94
SP		 893
894 atomic_dec(&rxq->used);
895 return rx_page_info;
896}
897
898/* Throwaway the data in the Rx completion */
899static void be_rx_compl_discard(struct be_adapter *adapter,
3abcdeda 900 struct be_rx_obj *rxo,
2e588f84 901 struct be_rx_compl_info *rxcp)
6b7c5b94 902{
3abcdeda 903 struct be_queue_info *rxq = &rxo->q;
6b7c5b94 904 struct be_rx_page_info *page_info;
2e588f84 905 u16 i, num_rcvd = rxcp->num_rcvd;
6b7c5b94 906
e80d9da6 907 for (i = 0; i < num_rcvd; i++) {
2e588f84 908 page_info = get_rx_page_info(adapter, rxo, rxcp->rxq_idx);
e80d9da6
PR		 909 put_page(page_info->page);
910 memset(page_info, 0, sizeof(*page_info));
2e588f84 911 index_inc(&rxcp->rxq_idx, rxq->len);
6b7c5b94
SP		 912 }
913}
914
915/*
916 * skb_fill_rx_data forms a complete skb for an ether frame
917 * indicated by rxcp.
918 */
3abcdeda 919static void skb_fill_rx_data(struct be_adapter *adapter, struct be_rx_obj *rxo,
2e588f84 920 struct sk_buff *skb, struct be_rx_compl_info *rxcp)
6b7c5b94 921{
3abcdeda 922 struct be_queue_info *rxq = &rxo->q;
6b7c5b94 923 struct be_rx_page_info *page_info;
2e588f84
SP		 924 u16 i, j;
925 u16 hdr_len, curr_frag_len, remaining;
6b7c5b94 926 u8 *start;
6b7c5b94 927
2e588f84 928 page_info = get_rx_page_info(adapter, rxo, rxcp->rxq_idx);
6b7c5b94
SP		 929 start = page_address(page_info->page) + page_info->page_offset;
930 prefetch(start);
931
932 /* Copy data in the first descriptor of this completion */
2e588f84 933 curr_frag_len = min(rxcp->pkt_size, rx_frag_size);
6b7c5b94
SP		 934
935 /* Copy the header portion into skb_data */
2e588f84 936 hdr_len = min(BE_HDR_LEN, curr_frag_len);
6b7c5b94
SP		 937 memcpy(skb->data, start, hdr_len);
938 skb->len = curr_frag_len;
939 if (curr_frag_len <= BE_HDR_LEN) { /* tiny packet */
940 /* Complete packet has now been moved to data */
941 put_page(page_info->page);
942 skb->data_len = 0;
943 skb->tail += curr_frag_len;
944 } else {
945 skb_shinfo(skb)->nr_frags = 1;
946 skb_shinfo(skb)->frags[0].page = page_info->page;
947 skb_shinfo(skb)->frags[0].page_offset =
948 page_info->page_offset + hdr_len;
949 skb_shinfo(skb)->frags[0].size = curr_frag_len - hdr_len;
950 skb->data_len = curr_frag_len - hdr_len;
951 skb->tail += hdr_len;
952 }
205859a2 953 page_info->page = NULL;
6b7c5b94 954
2e588f84
SP		 955 if (rxcp->pkt_size <= rx_frag_size) {
956 BUG_ON(rxcp->num_rcvd != 1);
957 return;
6b7c5b94
SP		 958 }
959
960 /* More frags present for this completion */
2e588f84
SP		 961 index_inc(&rxcp->rxq_idx, rxq->len);
962 remaining = rxcp->pkt_size - curr_frag_len;
963 for (i = 1, j = 0; i < rxcp->num_rcvd; i++) {
964 page_info = get_rx_page_info(adapter, rxo, rxcp->rxq_idx);
965 curr_frag_len = min(remaining, rx_frag_size);
6b7c5b94 966
bd46cb6c
AK		 967 /* Coalesce all frags from the same physical page in one slot */
968 if (page_info->page_offset == 0) {
969 /* Fresh page */
970 j++;
971 skb_shinfo(skb)->frags[j].page = page_info->page;
972 skb_shinfo(skb)->frags[j].page_offset =
973 page_info->page_offset;
974 skb_shinfo(skb)->frags[j].size = 0;
975 skb_shinfo(skb)->nr_frags++;
976 } else {
977 put_page(page_info->page);
978 }
979
980 skb_shinfo(skb)->frags[j].size += curr_frag_len;
6b7c5b94
SP		 981 skb->len += curr_frag_len;
982 skb->data_len += curr_frag_len;
6b7c5b94 983
2e588f84
SP		 984 remaining -= curr_frag_len;
985 index_inc(&rxcp->rxq_idx, rxq->len);
205859a2 986 page_info->page = NULL;
6b7c5b94 987 }
bd46cb6c 988 BUG_ON(j > MAX_SKB_FRAGS);
6b7c5b94
SP		 989}
990
5be93b9a 991/* Process the RX completion indicated by rxcp when GRO is disabled */
6b7c5b94 992static void be_rx_compl_process(struct be_adapter *adapter,
3abcdeda 993 struct be_rx_obj *rxo,
2e588f84 994 struct be_rx_compl_info *rxcp)
6b7c5b94
SP		 995{
996 struct sk_buff *skb;
89420424 997
89d71a66 998 skb = netdev_alloc_skb_ip_align(adapter->netdev, BE_HDR_LEN);
a058a632 999 if (unlikely(!skb)) {
6b7c5b94
SP		 1000 if (net_ratelimit())
1001 dev_warn(&adapter->pdev->dev, "skb alloc failed\n");
3abcdeda 1002 be_rx_compl_discard(adapter, rxo, rxcp);
6b7c5b94
SP		 1003 return;
1004 }
1005
2e588f84 1006 skb_fill_rx_data(adapter, rxo, skb, rxcp);
6b7c5b94 1007
c6ce2f4b 1008 if (likely(adapter->rx_csum && csum_passed(rxcp)))
728a9972 1009 skb->ip_summed = CHECKSUM_UNNECESSARY;
c6ce2f4b
SK		 1010 else
1011 skb_checksum_none_assert(skb);
6b7c5b94
SP		 1012
1013 skb->truesize = skb->len + sizeof(struct sk_buff);
1014 skb->protocol = eth_type_trans(skb, adapter->netdev);
6b7c5b94 1015
2e588f84 1016 if (unlikely(rxcp->vlanf)) {
82903e4b 1017 if (!adapter->vlan_grp || adapter->vlans_added == 0) {
6b7c5b94
SP		 1018 kfree_skb(skb);
1019 return;
1020 }
2e588f84 1021 vlan_hwaccel_receive_skb(skb, adapter->vlan_grp, rxcp->vid);
6b7c5b94
SP		 1022 } else {
1023 netif_receive_skb(skb);
1024 }
6b7c5b94
SP		 1025}
1026
5be93b9a
AK		 1027/* Process the RX completion indicated by rxcp when GRO is enabled */
1028static void be_rx_compl_process_gro(struct be_adapter *adapter,
3abcdeda 1029 struct be_rx_obj *rxo,
2e588f84 1030 struct be_rx_compl_info *rxcp)
6b7c5b94
SP		 1031{
1032 struct be_rx_page_info *page_info;
5be93b9a 1033 struct sk_buff *skb = NULL;
3abcdeda
SP		 1034 struct be_queue_info *rxq = &rxo->q;
1035 struct be_eq_obj *eq_obj = &rxo->rx_eq;
2e588f84
SP		 1036 u16 remaining, curr_frag_len;
1037 u16 i, j;
3968fa1e 1038
5be93b9a
AK		 1039 skb = napi_get_frags(&eq_obj->napi);
1040 if (!skb) {
3abcdeda 1041 be_rx_compl_discard(adapter, rxo, rxcp);
5be93b9a
AK		 1042 return;
1043 }
1044
2e588f84
SP		 1045 remaining = rxcp->pkt_size;
1046 for (i = 0, j = -1; i < rxcp->num_rcvd; i++) {
1047 page_info = get_rx_page_info(adapter, rxo, rxcp->rxq_idx);
6b7c5b94
SP		 1048
1049 curr_frag_len = min(remaining, rx_frag_size);
1050
bd46cb6c
AK		 1051 /* Coalesce all frags from the same physical page in one slot */
1052 if (i == 0 || page_info->page_offset == 0) {
1053 /* First frag or Fresh page */
1054 j++;
5be93b9a
AK		 1055 skb_shinfo(skb)->frags[j].page = page_info->page;
1056 skb_shinfo(skb)->frags[j].page_offset =
1057 page_info->page_offset;
1058 skb_shinfo(skb)->frags[j].size = 0;
bd46cb6c
AK		 1059 } else {
1060 put_page(page_info->page);
1061 }
5be93b9a 1062 skb_shinfo(skb)->frags[j].size += curr_frag_len;
6b7c5b94 1063
bd46cb6c 1064 remaining -= curr_frag_len;
2e588f84 1065 index_inc(&rxcp->rxq_idx, rxq->len);
6b7c5b94
SP		 1066 memset(page_info, 0, sizeof(*page_info));
1067 }
bd46cb6c 1068 BUG_ON(j > MAX_SKB_FRAGS);
6b7c5b94 1069
5be93b9a 1070 skb_shinfo(skb)->nr_frags = j + 1;
2e588f84
SP		 1071 skb->len = rxcp->pkt_size;
1072 skb->data_len = rxcp->pkt_size;
1073 skb->truesize += rxcp->pkt_size;
5be93b9a
AK		 1074 skb->ip_summed = CHECKSUM_UNNECESSARY;
1075
2e588f84 1076 if (likely(!rxcp->vlanf))
5be93b9a 1077 napi_gro_frags(&eq_obj->napi);
2e588f84
SP		 1078 else
1079 vlan_gro_frags(&eq_obj->napi, adapter->vlan_grp, rxcp->vid);
1080}
1081
1082static void be_parse_rx_compl_v1(struct be_adapter *adapter,
1083 struct be_eth_rx_compl *compl,
1084 struct be_rx_compl_info *rxcp)
1085{
1086 rxcp->pkt_size =
1087 AMAP_GET_BITS(struct amap_eth_rx_compl_v1, pktsize, compl);
1088 rxcp->vlanf = AMAP_GET_BITS(struct amap_eth_rx_compl_v1, vtp, compl);
1089 rxcp->err = AMAP_GET_BITS(struct amap_eth_rx_compl_v1, err, compl);
1090 rxcp->tcpf = AMAP_GET_BITS(struct amap_eth_rx_compl_v1, tcpf, compl);
9ecb42fd 1091 rxcp->udpf = AMAP_GET_BITS(struct amap_eth_rx_compl_v1, udpf, compl);
2e588f84
SP		 1092 rxcp->ip_csum =
1093 AMAP_GET_BITS(struct amap_eth_rx_compl_v1, ipcksm, compl);
1094 rxcp->l4_csum =
1095 AMAP_GET_BITS(struct amap_eth_rx_compl_v1, l4_cksm, compl);
1096 rxcp->ipv6 =
1097 AMAP_GET_BITS(struct amap_eth_rx_compl_v1, ip_version, compl);
1098 rxcp->rxq_idx =
1099 AMAP_GET_BITS(struct amap_eth_rx_compl_v1, fragndx, compl);
1100 rxcp->num_rcvd =
1101 AMAP_GET_BITS(struct amap_eth_rx_compl_v1, numfrags, compl);
1102 rxcp->pkt_type =
1103 AMAP_GET_BITS(struct amap_eth_rx_compl_v1, cast_enc, compl);
1104 rxcp->vtm = AMAP_GET_BITS(struct amap_eth_rx_compl_v1, vtm, compl);
1105 rxcp->vid = AMAP_GET_BITS(struct amap_eth_rx_compl_v1, vlan_tag, compl);
1106}
1107
1108static void be_parse_rx_compl_v0(struct be_adapter *adapter,
1109 struct be_eth_rx_compl *compl,
1110 struct be_rx_compl_info *rxcp)
1111{
1112 rxcp->pkt_size =
1113 AMAP_GET_BITS(struct amap_eth_rx_compl_v0, pktsize, compl);
1114 rxcp->vlanf = AMAP_GET_BITS(struct amap_eth_rx_compl_v0, vtp, compl);
1115 rxcp->err = AMAP_GET_BITS(struct amap_eth_rx_compl_v0, err, compl);
1116 rxcp->tcpf = AMAP_GET_BITS(struct amap_eth_rx_compl_v0, tcpf, compl);
9ecb42fd 1117 rxcp->udpf = AMAP_GET_BITS(struct amap_eth_rx_compl_v0, udpf, compl);
2e588f84
SP		 1118 rxcp->ip_csum =
1119 AMAP_GET_BITS(struct amap_eth_rx_compl_v0, ipcksm, compl);
1120 rxcp->l4_csum =
1121 AMAP_GET_BITS(struct amap_eth_rx_compl_v0, l4_cksm, compl);
1122 rxcp->ipv6 =
1123 AMAP_GET_BITS(struct amap_eth_rx_compl_v0, ip_version, compl);
1124 rxcp->rxq_idx =
1125 AMAP_GET_BITS(struct amap_eth_rx_compl_v0, fragndx, compl);
1126 rxcp->num_rcvd =
1127 AMAP_GET_BITS(struct amap_eth_rx_compl_v0, numfrags, compl);
1128 rxcp->pkt_type =
1129 AMAP_GET_BITS(struct amap_eth_rx_compl_v0, cast_enc, compl);
1130 rxcp->vtm = AMAP_GET_BITS(struct amap_eth_rx_compl_v0, vtm, compl);
1131 rxcp->vid = AMAP_GET_BITS(struct amap_eth_rx_compl_v0, vlan_tag, compl);
1132}
1133
1134static struct be_rx_compl_info *be_rx_compl_get(struct be_rx_obj *rxo)
1135{
1136 struct be_eth_rx_compl *compl = queue_tail_node(&rxo->cq);
1137 struct be_rx_compl_info *rxcp = &rxo->rxcp;
1138 struct be_adapter *adapter = rxo->adapter;
6b7c5b94 1139
2e588f84
SP		 1140 /* For checking the valid bit it is Ok to use either definition as the
1141 * valid bit is at the same position in both v0 and v1 Rx compl */
1142 if (compl->dw[offsetof(struct amap_eth_rx_compl_v1, valid) / 32] == 0)
1143 return NULL;
6b7c5b94 1144
2e588f84
SP		 1145 rmb();
1146 be_dws_le_to_cpu(compl, sizeof(*compl));
6b7c5b94 1147
2e588f84
SP		 1148 if (adapter->be3_native)
1149 be_parse_rx_compl_v1(adapter, compl, rxcp);
1150 else
1151 be_parse_rx_compl_v0(adapter, compl, rxcp);
6b7c5b94 1152
2e588f84
SP		 1153 /* vlanf could be wrongly set in some cards. ignore if vtm is not set */
1154 if ((adapter->function_mode & 0x400) && !rxcp->vtm)
1155 rxcp->vlanf = 0;
6b7c5b94 1156
2e588f84
SP		 1157 if (!lancer_chip(adapter))
1158 rxcp->vid = swab16(rxcp->vid);
6b7c5b94 1159
2e588f84
SP		 1160 if ((adapter->pvid == rxcp->vid) && !adapter->vlan_tag[rxcp->vid])
1161 rxcp->vlanf = 0;
1162
1163 /* As the compl has been parsed, reset it; we wont touch it again */
1164 compl->dw[offsetof(struct amap_eth_rx_compl_v1, valid) / 32] = 0;
6b7c5b94 1165
3abcdeda 1166 queue_tail_inc(&rxo->cq);
6b7c5b94
SP		 1167 return rxcp;
1168}
1169
1829b086 1170static inline struct page *be_alloc_pages(u32 size, gfp_t gfp)
6b7c5b94 1171{
6b7c5b94 1172 u32 order = get_order(size);
1829b086 1173
6b7c5b94 1174 if (order > 0)
1829b086
ED		 1175 gfp |= __GFP_COMP;
1176 return alloc_pages(gfp, order);
6b7c5b94
SP		 1177}
1178
1179/*
1180 * Allocate a page, split it to fragments of size rx_frag_size and post as
1181 * receive buffers to BE
1182 */
1829b086 1183static void be_post_rx_frags(struct be_rx_obj *rxo, gfp_t gfp)
6b7c5b94 1184{
3abcdeda
SP		 1185 struct be_adapter *adapter = rxo->adapter;
1186 struct be_rx_page_info *page_info_tbl = rxo->page_info_tbl;
26d92f92 1187 struct be_rx_page_info *page_info = NULL, *prev_page_info = NULL;
3abcdeda 1188 struct be_queue_info *rxq = &rxo->q;
6b7c5b94
SP		 1189 struct page *pagep = NULL;
1190 struct be_eth_rx_d *rxd;
1191 u64 page_dmaaddr = 0, frag_dmaaddr;
1192 u32 posted, page_offset = 0;
1193
3abcdeda 1194 page_info = &rxo->page_info_tbl[rxq->head];
6b7c5b94
SP		 1195 for (posted = 0; posted < MAX_RX_POST && !page_info->page; posted++) {
1196 if (!pagep) {
1829b086 1197 pagep = be_alloc_pages(adapter->big_page_size, gfp);
6b7c5b94 1198 if (unlikely(!pagep)) {
3abcdeda 1199 rxo->stats.rx_post_fail++;
6b7c5b94
SP		 1200 break;
1201 }
2b7bcebf
IV		 1202 page_dmaaddr = dma_map_page(&adapter->pdev->dev, pagep,
1203 0, adapter->big_page_size,
1204 DMA_FROM_DEVICE);
6b7c5b94
SP		 1205 page_info->page_offset = 0;
1206 } else {
1207 get_page(pagep);
1208 page_info->page_offset = page_offset + rx_frag_size;
1209 }
1210 page_offset = page_info->page_offset;
1211 page_info->page = pagep;
fac6da5b 1212 dma_unmap_addr_set(page_info, bus, page_dmaaddr);
6b7c5b94
SP		 1213 frag_dmaaddr = page_dmaaddr + page_info->page_offset;
1214
1215 rxd = queue_head_node(rxq);
1216 rxd->fragpa_lo = cpu_to_le32(frag_dmaaddr & 0xFFFFFFFF);
1217 rxd->fragpa_hi = cpu_to_le32(upper_32_bits(frag_dmaaddr));
6b7c5b94
SP		 1218
1219 /* Any space left in the current big page for another frag? */
1220 if ((page_offset + rx_frag_size + rx_frag_size) >
1221 adapter->big_page_size) {
1222 pagep = NULL;
1223 page_info->last_page_user = true;
1224 }
26d92f92
SP		 1225
1226 prev_page_info = page_info;
1227 queue_head_inc(rxq);
6b7c5b94
SP		 1228 page_info = &page_info_tbl[rxq->head];
1229 }
1230 if (pagep)
26d92f92 1231 prev_page_info->last_page_user = true;
6b7c5b94
SP		 1232
1233 if (posted) {
6b7c5b94 1234 atomic_add(posted, &rxq->used);
8788fdc2 1235 be_rxq_notify(adapter, rxq->id, posted);
ea1dae11
SP		 1236 } else if (atomic_read(&rxq->used) == 0) {
1237 /* Let be_worker replenish when memory is available */
3abcdeda 1238 rxo->rx_post_starved = true;
6b7c5b94 1239 }
6b7c5b94
SP		 1240}
1241
5fb379ee 1242static struct be_eth_tx_compl *be_tx_compl_get(struct be_queue_info *tx_cq)
6b7c5b94 1243{
6b7c5b94
SP		 1244 struct be_eth_tx_compl *txcp = queue_tail_node(tx_cq);
1245
1246 if (txcp->dw[offsetof(struct amap_eth_tx_compl, valid) / 32] == 0)
1247 return NULL;
1248
f3eb62d2 1249 rmb();
6b7c5b94
SP		 1250 be_dws_le_to_cpu(txcp, sizeof(*txcp));
1251
1252 txcp->dw[offsetof(struct amap_eth_tx_compl, valid) / 32] = 0;
1253
1254 queue_tail_inc(tx_cq);
1255 return txcp;
1256}
1257
1258static void be_tx_compl_process(struct be_adapter *adapter, u16 last_index)
1259{
1260 struct be_queue_info *txq = &adapter->tx_obj.q;
a73b796e 1261 struct be_eth_wrb *wrb;
6b7c5b94
SP		 1262 struct sk_buff **sent_skbs = adapter->tx_obj.sent_skb_list;
1263 struct sk_buff *sent_skb;
ec43b1a6
SP		 1264 u16 cur_index, num_wrbs = 1; /* account for hdr wrb */
1265 bool unmap_skb_hdr = true;
6b7c5b94 1266
ec43b1a6 1267 sent_skb = sent_skbs[txq->tail];
6b7c5b94 1268 BUG_ON(!sent_skb);
ec43b1a6
SP		 1269 sent_skbs[txq->tail] = NULL;
1270
1271 /* skip header wrb */
a73b796e 1272 queue_tail_inc(txq);
6b7c5b94 1273
ec43b1a6 1274 do {
6b7c5b94 1275 cur_index = txq->tail;
a73b796e 1276 wrb = queue_tail_node(txq);
2b7bcebf
IV		 1277 unmap_tx_frag(&adapter->pdev->dev, wrb,
1278 (unmap_skb_hdr && skb_headlen(sent_skb)));
ec43b1a6
SP		 1279 unmap_skb_hdr = false;
1280
6b7c5b94
SP		 1281 num_wrbs++;
1282 queue_tail_inc(txq);
ec43b1a6 1283 } while (cur_index != last_index);
6b7c5b94
SP		 1284
1285 atomic_sub(num_wrbs, &txq->used);
a73b796e 1286
6b7c5b94
SP		 1287 kfree_skb(sent_skb);
1288}
1289
859b1e4e
SP		 1290static inline struct be_eq_entry *event_get(struct be_eq_obj *eq_obj)
1291{
1292 struct be_eq_entry *eqe = queue_tail_node(&eq_obj->q);
1293
1294 if (!eqe->evt)
1295 return NULL;
1296
f3eb62d2 1297 rmb();
859b1e4e
SP		 1298 eqe->evt = le32_to_cpu(eqe->evt);
1299 queue_tail_inc(&eq_obj->q);
1300 return eqe;
1301}
1302
1303static int event_handle(struct be_adapter *adapter,
1304 struct be_eq_obj *eq_obj)
1305{
1306 struct be_eq_entry *eqe;
1307 u16 num = 0;
1308
1309 while ((eqe = event_get(eq_obj)) != NULL) {
1310 eqe->evt = 0;
1311 num++;
1312 }
1313
1314 /* Deal with any spurious interrupts that come
1315 * without events
1316 */
1317 be_eq_notify(adapter, eq_obj->q.id, true, true, num);
1318 if (num)
1319 napi_schedule(&eq_obj->napi);
1320
1321 return num;
1322}
1323
1324/* Just read and notify events without processing them.
1325 * Used at the time of destroying event queues */
1326static void be_eq_clean(struct be_adapter *adapter,
1327 struct be_eq_obj *eq_obj)
1328{
1329 struct be_eq_entry *eqe;
1330 u16 num = 0;
1331
1332 while ((eqe = event_get(eq_obj)) != NULL) {
1333 eqe->evt = 0;
1334 num++;
1335 }
1336
1337 if (num)
1338 be_eq_notify(adapter, eq_obj->q.id, false, true, num);
1339}
1340
3abcdeda 1341static void be_rx_q_clean(struct be_adapter *adapter, struct be_rx_obj *rxo)
6b7c5b94
SP		 1342{
1343 struct be_rx_page_info *page_info;
3abcdeda
SP		 1344 struct be_queue_info *rxq = &rxo->q;
1345 struct be_queue_info *rx_cq = &rxo->cq;
2e588f84 1346 struct be_rx_compl_info *rxcp;
6b7c5b94
SP		 1347 u16 tail;
1348
1349 /* First cleanup pending rx completions */
3abcdeda
SP		 1350 while ((rxcp = be_rx_compl_get(rxo)) != NULL) {
1351 be_rx_compl_discard(adapter, rxo, rxcp);
64642811 1352 be_cq_notify(adapter, rx_cq->id, false, 1);
6b7c5b94
SP		 1353 }
1354
1355 /* Then free posted rx buffer that were not used */
1356 tail = (rxq->head + rxq->len - atomic_read(&rxq->used)) % rxq->len;
cdab23b7 1357 for (; atomic_read(&rxq->used) > 0; index_inc(&tail, rxq->len)) {
3abcdeda 1358 page_info = get_rx_page_info(adapter, rxo, tail);
6b7c5b94
SP		 1359 put_page(page_info->page);
1360 memset(page_info, 0, sizeof(*page_info));
1361 }
1362 BUG_ON(atomic_read(&rxq->used));
1363}
1364
a8e9179a 1365static void be_tx_compl_clean(struct be_adapter *adapter)
6b7c5b94 1366{
a8e9179a 1367 struct be_queue_info *tx_cq = &adapter->tx_obj.cq;
6b7c5b94 1368 struct be_queue_info *txq = &adapter->tx_obj.q;
a8e9179a
SP		 1369 struct be_eth_tx_compl *txcp;
1370 u16 end_idx, cmpl = 0, timeo = 0;
b03388d6
SP		 1371 struct sk_buff **sent_skbs = adapter->tx_obj.sent_skb_list;
1372 struct sk_buff *sent_skb;
1373 bool dummy_wrb;
a8e9179a
SP		 1374
1375 /* Wait for a max of 200ms for all the tx-completions to arrive. */
1376 do {
1377 while ((txcp = be_tx_compl_get(tx_cq))) {
1378 end_idx = AMAP_GET_BITS(struct amap_eth_tx_compl,
1379 wrb_index, txcp);
1380 be_tx_compl_process(adapter, end_idx);
1381 cmpl++;
1382 }
1383 if (cmpl) {
1384 be_cq_notify(adapter, tx_cq->id, false, cmpl);
1385 cmpl = 0;
1386 }
1387
1388 if (atomic_read(&txq->used) == 0 || ++timeo > 200)
1389 break;
1390
1391 mdelay(1);
1392 } while (true);
1393
1394 if (atomic_read(&txq->used))
1395 dev_err(&adapter->pdev->dev, "%d pending tx-completions\n",
1396 atomic_read(&txq->used));
b03388d6
SP		 1397
1398 /* free posted tx for which compls will never arrive */
1399 while (atomic_read(&txq->used)) {
1400 sent_skb = sent_skbs[txq->tail];
1401 end_idx = txq->tail;
1402 index_adv(&end_idx,
fe6d2a38
SP		 1403 wrb_cnt_for_skb(adapter, sent_skb, &dummy_wrb) - 1,
1404 txq->len);
b03388d6
SP		 1405 be_tx_compl_process(adapter, end_idx);
1406 }
6b7c5b94
SP		 1407}
1408
5fb379ee
SP		 1409static void be_mcc_queues_destroy(struct be_adapter *adapter)
1410{
1411 struct be_queue_info *q;
5fb379ee 1412
8788fdc2 1413 q = &adapter->mcc_obj.q;
5fb379ee 1414 if (q->created)
8788fdc2 1415 be_cmd_q_destroy(adapter, q, QTYPE_MCCQ);
5fb379ee
SP		 1416 be_queue_free(adapter, q);
1417
8788fdc2 1418 q = &adapter->mcc_obj.cq;
5fb379ee 1419 if (q->created)
8788fdc2 1420 be_cmd_q_destroy(adapter, q, QTYPE_CQ);
5fb379ee
SP		 1421 be_queue_free(adapter, q);
1422}
1423
1424/* Must be called only after TX qs are created as MCC shares TX EQ */
1425static int be_mcc_queues_create(struct be_adapter *adapter)
1426{
1427 struct be_queue_info *q, *cq;
5fb379ee
SP		 1428
1429 /* Alloc MCC compl queue */
8788fdc2 1430 cq = &adapter->mcc_obj.cq;
5fb379ee 1431 if (be_queue_alloc(adapter, cq, MCC_CQ_LEN,
efd2e40a 1432 sizeof(struct be_mcc_compl)))
5fb379ee
SP		 1433 goto err;
1434
1435 /* Ask BE to create MCC compl queue; share TX's eq */
8788fdc2 1436 if (be_cmd_cq_create(adapter, cq, &adapter->tx_eq.q, false, true, 0))
5fb379ee
SP		 1437 goto mcc_cq_free;
1438
1439 /* Alloc MCC queue */
8788fdc2 1440 q = &adapter->mcc_obj.q;
5fb379ee
SP		 1441 if (be_queue_alloc(adapter, q, MCC_Q_LEN, sizeof(struct be_mcc_wrb)))
1442 goto mcc_cq_destroy;
1443
1444 /* Ask BE to create MCC queue */
8788fdc2 1445 if (be_cmd_mccq_create(adapter, q, cq))
5fb379ee
SP		 1446 goto mcc_q_free;
1447
1448 return 0;
1449
1450mcc_q_free:
1451 be_queue_free(adapter, q);
1452mcc_cq_destroy:
8788fdc2 1453 be_cmd_q_destroy(adapter, cq, QTYPE_CQ);
5fb379ee
SP		 1454mcc_cq_free:
1455 be_queue_free(adapter, cq);
1456err:
1457 return -1;
1458}
1459
6b7c5b94
SP		 1460static void be_tx_queues_destroy(struct be_adapter *adapter)
1461{
1462 struct be_queue_info *q;
1463
1464 q = &adapter->tx_obj.q;
a8e9179a 1465 if (q->created)
8788fdc2 1466 be_cmd_q_destroy(adapter, q, QTYPE_TXQ);
6b7c5b94
SP		 1467 be_queue_free(adapter, q);
1468
1469 q = &adapter->tx_obj.cq;
1470 if (q->created)
8788fdc2 1471 be_cmd_q_destroy(adapter, q, QTYPE_CQ);
6b7c5b94
SP		 1472 be_queue_free(adapter, q);
1473
859b1e4e
SP		 1474 /* Clear any residual events */
1475 be_eq_clean(adapter, &adapter->tx_eq);
1476
6b7c5b94
SP		 1477 q = &adapter->tx_eq.q;
1478 if (q->created)
8788fdc2 1479 be_cmd_q_destroy(adapter, q, QTYPE_EQ);
6b7c5b94
SP		 1480 be_queue_free(adapter, q);
1481}
1482
1483static int be_tx_queues_create(struct be_adapter *adapter)
1484{
1485 struct be_queue_info *eq, *q, *cq;
1486
1487 adapter->tx_eq.max_eqd = 0;
1488 adapter->tx_eq.min_eqd = 0;
1489 adapter->tx_eq.cur_eqd = 96;
1490 adapter->tx_eq.enable_aic = false;
1491 /* Alloc Tx Event queue */
1492 eq = &adapter->tx_eq.q;
1493 if (be_queue_alloc(adapter, eq, EVNT_Q_LEN, sizeof(struct be_eq_entry)))
1494 return -1;
1495
1496 /* Ask BE to create Tx Event queue */
8788fdc2 1497 if (be_cmd_eq_create(adapter, eq, adapter->tx_eq.cur_eqd))
6b7c5b94 1498 goto tx_eq_free;
fe6d2a38
SP		 1499
1500 adapter->tx_eq.msix_vec_idx = adapter->msix_vec_next_idx++;
1501
ba343c77 1502
6b7c5b94
SP		 1503 /* Alloc TX eth compl queue */
1504 cq = &adapter->tx_obj.cq;
1505 if (be_queue_alloc(adapter, cq, TX_CQ_LEN,
1506 sizeof(struct be_eth_tx_compl)))
1507 goto tx_eq_destroy;
1508
1509 /* Ask BE to create Tx eth compl queue */
8788fdc2 1510 if (be_cmd_cq_create(adapter, cq, eq, false, false, 3))
6b7c5b94
SP		 1511 goto tx_cq_free;
1512
1513 /* Alloc TX eth queue */
1514 q = &adapter->tx_obj.q;
1515 if (be_queue_alloc(adapter, q, TX_Q_LEN, sizeof(struct be_eth_wrb)))
1516 goto tx_cq_destroy;
1517
1518 /* Ask BE to create Tx eth queue */
8788fdc2 1519 if (be_cmd_txq_create(adapter, q, cq))
6b7c5b94
SP		 1520 goto tx_q_free;
1521 return 0;
1522
1523tx_q_free:
1524 be_queue_free(adapter, q);
1525tx_cq_destroy:
8788fdc2 1526 be_cmd_q_destroy(adapter, cq, QTYPE_CQ);
6b7c5b94
SP		 1527tx_cq_free:
1528 be_queue_free(adapter, cq);
1529tx_eq_destroy:
8788fdc2 1530 be_cmd_q_destroy(adapter, eq, QTYPE_EQ);
6b7c5b94
SP		 1531tx_eq_free:
1532 be_queue_free(adapter, eq);
1533 return -1;
1534}
1535
1536static void be_rx_queues_destroy(struct be_adapter *adapter)
1537{
1538 struct be_queue_info *q;
3abcdeda
SP		 1539 struct be_rx_obj *rxo;
1540 int i;
1541
1542 for_all_rx_queues(adapter, rxo, i) {
1543 q = &rxo->q;
1544 if (q->created) {
1545 be_cmd_q_destroy(adapter, q, QTYPE_RXQ);
1546 /* After the rxq is invalidated, wait for a grace time
1547 * of 1ms for all dma to end and the flush compl to
1548 * arrive
1549 */
1550 mdelay(1);
1551 be_rx_q_clean(adapter, rxo);
1552 }
1553 be_queue_free(adapter, q);
1554
1555 q = &rxo->cq;
1556 if (q->created)
1557 be_cmd_q_destroy(adapter, q, QTYPE_CQ);
1558 be_queue_free(adapter, q);
1559
1560 /* Clear any residual events */
1561 q = &rxo->rx_eq.q;
1562 if (q->created) {
1563 be_eq_clean(adapter, &rxo->rx_eq);
1564 be_cmd_q_destroy(adapter, q, QTYPE_EQ);
1565 }
1566 be_queue_free(adapter, q);
6b7c5b94 1567 }
6b7c5b94
SP		 1568}
1569
ac6a0c4a
SP		 1570static u32 be_num_rxqs_want(struct be_adapter *adapter)
1571{
1572 if (multi_rxq && (adapter->function_caps & BE_FUNCTION_CAPS_RSS) &&
1573 !adapter->sriov_enabled && !(adapter->function_mode & 0x400)) {
1574 return 1 + MAX_RSS_QS; /* one default non-RSS queue */
1575 } else {
1576 dev_warn(&adapter->pdev->dev,
1577 "No support for multiple RX queues\n");
1578 return 1;
1579 }
1580}
1581
6b7c5b94
SP		 1582static int be_rx_queues_create(struct be_adapter *adapter)
1583{
1584 struct be_queue_info *eq, *q, *cq;
3abcdeda
SP		 1585 struct be_rx_obj *rxo;
1586 int rc, i;
6b7c5b94 1587
ac6a0c4a
SP		 1588 adapter->num_rx_qs = min(be_num_rxqs_want(adapter),
1589 msix_enabled(adapter) ?
1590 adapter->num_msix_vec - 1 : 1);
1591 if (adapter->num_rx_qs != MAX_RX_QS)
1592 dev_warn(&adapter->pdev->dev,
1593 "Can create only %d RX queues", adapter->num_rx_qs);
1594
6b7c5b94 1595 adapter->big_page_size = (1 << get_order(rx_frag_size)) * PAGE_SIZE;
3abcdeda
SP		 1596 for_all_rx_queues(adapter, rxo, i) {
1597 rxo->adapter = adapter;
1598 rxo->rx_eq.max_eqd = BE_MAX_EQD;
1599 rxo->rx_eq.enable_aic = true;
1600
1601 /* EQ */
1602 eq = &rxo->rx_eq.q;
1603 rc = be_queue_alloc(adapter, eq, EVNT_Q_LEN,
1604 sizeof(struct be_eq_entry));
1605 if (rc)
1606 goto err;
1607
1608 rc = be_cmd_eq_create(adapter, eq, rxo->rx_eq.cur_eqd);
1609 if (rc)
1610 goto err;
1611
fe6d2a38
SP		 1612 rxo->rx_eq.msix_vec_idx = adapter->msix_vec_next_idx++;
1613
3abcdeda
SP		 1614 /* CQ */
1615 cq = &rxo->cq;
1616 rc = be_queue_alloc(adapter, cq, RX_CQ_LEN,
1617 sizeof(struct be_eth_rx_compl));
1618 if (rc)
1619 goto err;
1620
1621 rc = be_cmd_cq_create(adapter, cq, eq, false, false, 3);
1622 if (rc)
1623 goto err;
3abcdeda
SP		 1624 /* Rx Q */
1625 q = &rxo->q;
1626 rc = be_queue_alloc(adapter, q, RX_Q_LEN,
1627 sizeof(struct be_eth_rx_d));
1628 if (rc)
1629 goto err;
1630
1631 rc = be_cmd_rxq_create(adapter, q, cq->id, rx_frag_size,
1632 BE_MAX_JUMBO_FRAME_SIZE, adapter->if_handle,
1633 (i > 0) ? 1 : 0/* rss enable */, &rxo->rss_id);
1634 if (rc)
1635 goto err;
1636 }
1637
1638 if (be_multi_rxq(adapter)) {
1639 u8 rsstable[MAX_RSS_QS];
1640
1641 for_all_rss_queues(adapter, rxo, i)
1642 rsstable[i] = rxo->rss_id;
1643
1644 rc = be_cmd_rss_config(adapter, rsstable,
1645 adapter->num_rx_qs - 1);
1646 if (rc)
1647 goto err;
1648 }
6b7c5b94
SP		 1649
1650 return 0;
3abcdeda
SP		 1651err:
1652 be_rx_queues_destroy(adapter);
1653 return -1;
6b7c5b94 1654}
6b7c5b94 1655
fe6d2a38 1656static bool event_peek(struct be_eq_obj *eq_obj)
b628bde2 1657{
fe6d2a38
SP		 1658 struct be_eq_entry *eqe = queue_tail_node(&eq_obj->q);
1659 if (!eqe->evt)
1660 return false;
1661 else
1662 return true;
b628bde2
SP		 1663}
1664
6b7c5b94
SP		 1665static irqreturn_t be_intx(int irq, void *dev)
1666{
1667 struct be_adapter *adapter = dev;
3abcdeda 1668 struct be_rx_obj *rxo;
fe6d2a38 1669 int isr, i, tx = 0 , rx = 0;
6b7c5b94 1670
fe6d2a38
SP		 1671 if (lancer_chip(adapter)) {
1672 if (event_peek(&adapter->tx_eq))
1673 tx = event_handle(adapter, &adapter->tx_eq);
1674 for_all_rx_queues(adapter, rxo, i) {
1675 if (event_peek(&rxo->rx_eq))
1676 rx |= event_handle(adapter, &rxo->rx_eq);
1677 }
6b7c5b94 1678
fe6d2a38
SP		 1679 if (!(tx || rx))
1680 return IRQ_NONE;
3abcdeda 1681
fe6d2a38
SP		 1682 } else {
1683 isr = ioread32(adapter->csr + CEV_ISR0_OFFSET +
1684 (adapter->tx_eq.q.id / 8) * CEV_ISR_SIZE);
1685 if (!isr)
1686 return IRQ_NONE;
1687
1688 if ((1 << adapter->tx_eq.msix_vec_idx & isr))
1689 event_handle(adapter, &adapter->tx_eq);
1690
1691 for_all_rx_queues(adapter, rxo, i) {
1692 if ((1 << rxo->rx_eq.msix_vec_idx & isr))
1693 event_handle(adapter, &rxo->rx_eq);
1694 }
3abcdeda 1695 }
c001c213 1696
8788fdc2 1697 return IRQ_HANDLED;
6b7c5b94
SP		 1698}
1699
1700static irqreturn_t be_msix_rx(int irq, void *dev)
1701{
3abcdeda
SP		 1702 struct be_rx_obj *rxo = dev;
1703 struct be_adapter *adapter = rxo->adapter;
6b7c5b94 1704
3abcdeda 1705 event_handle(adapter, &rxo->rx_eq);
6b7c5b94
SP		 1706
1707 return IRQ_HANDLED;
1708}
1709
5fb379ee 1710static irqreturn_t be_msix_tx_mcc(int irq, void *dev)
6b7c5b94
SP		 1711{
1712 struct be_adapter *adapter = dev;
1713
8788fdc2 1714 event_handle(adapter, &adapter->tx_eq);
6b7c5b94
SP		 1715
1716 return IRQ_HANDLED;
1717}
1718
2e588f84 1719static inline bool do_gro(struct be_rx_compl_info *rxcp)
6b7c5b94 1720{
2e588f84 1721 return (rxcp->tcpf && !rxcp->err) ? true : false;
6b7c5b94
SP		 1722}
1723
49b05221 1724static int be_poll_rx(struct napi_struct *napi, int budget)
6b7c5b94
SP		 1725{
1726 struct be_eq_obj *rx_eq = container_of(napi, struct be_eq_obj, napi);
3abcdeda
SP		 1727 struct be_rx_obj *rxo = container_of(rx_eq, struct be_rx_obj, rx_eq);
1728 struct be_adapter *adapter = rxo->adapter;
1729 struct be_queue_info *rx_cq = &rxo->cq;
2e588f84 1730 struct be_rx_compl_info *rxcp;
6b7c5b94
SP		 1731 u32 work_done;
1732
3abcdeda 1733 rxo->stats.rx_polls++;
6b7c5b94 1734 for (work_done = 0; work_done < budget; work_done++) {
3abcdeda 1735 rxcp = be_rx_compl_get(rxo);
6b7c5b94
SP		 1736 if (!rxcp)
1737 break;
1738
e80d9da6 1739 /* Ignore flush completions */
2e588f84
SP		 1740 if (rxcp->num_rcvd) {
1741 if (do_gro(rxcp))
64642811
SP		 1742 be_rx_compl_process_gro(adapter, rxo, rxcp);
1743 else
1744 be_rx_compl_process(adapter, rxo, rxcp);
1745 }
2e588f84 1746 be_rx_stats_update(rxo, rxcp);
6b7c5b94
SP		 1747 }
1748
6b7c5b94 1749 /* Refill the queue */
3abcdeda 1750 if (atomic_read(&rxo->q.used) < RX_FRAGS_REFILL_WM)
1829b086 1751 be_post_rx_frags(rxo, GFP_ATOMIC);
6b7c5b94
SP		 1752
1753 /* All consumed */
1754 if (work_done < budget) {
1755 napi_complete(napi);
8788fdc2 1756 be_cq_notify(adapter, rx_cq->id, true, work_done);
6b7c5b94
SP		 1757 } else {
1758 /* More to be consumed; continue with interrupts disabled */
8788fdc2 1759 be_cq_notify(adapter, rx_cq->id, false, work_done);
6b7c5b94
SP		 1760 }
1761 return work_done;
1762}
1763
f31e50a8
SP		 1764/* As TX and MCC share the same EQ check for both TX and MCC completions.
1765 * For TX/MCC we don't honour budget; consume everything
1766 */
1767static int be_poll_tx_mcc(struct napi_struct *napi, int budget)
6b7c5b94 1768{
f31e50a8
SP		 1769 struct be_eq_obj *tx_eq = container_of(napi, struct be_eq_obj, napi);
1770 struct be_adapter *adapter =
1771 container_of(tx_eq, struct be_adapter, tx_eq);
5fb379ee
SP		 1772 struct be_queue_info *txq = &adapter->tx_obj.q;
1773 struct be_queue_info *tx_cq = &adapter->tx_obj.cq;
6b7c5b94 1774 struct be_eth_tx_compl *txcp;
f31e50a8 1775 int tx_compl = 0, mcc_compl, status = 0;
6b7c5b94
SP		 1776 u16 end_idx;
1777
5fb379ee 1778 while ((txcp = be_tx_compl_get(tx_cq))) {
6b7c5b94 1779 end_idx = AMAP_GET_BITS(struct amap_eth_tx_compl,
f31e50a8 1780 wrb_index, txcp);
6b7c5b94 1781 be_tx_compl_process(adapter, end_idx);
f31e50a8 1782 tx_compl++;
6b7c5b94
SP		 1783 }
1784
f31e50a8
SP		 1785 mcc_compl = be_process_mcc(adapter, &status);
1786
1787 napi_complete(napi);
1788
1789 if (mcc_compl) {
1790 struct be_mcc_obj *mcc_obj = &adapter->mcc_obj;
1791 be_cq_notify(adapter, mcc_obj->cq.id, true, mcc_compl);
1792 }
1793
1794 if (tx_compl) {
1795 be_cq_notify(adapter, adapter->tx_obj.cq.id, true, tx_compl);
5fb379ee
SP		 1796
1797 /* As Tx wrbs have been freed up, wake up netdev queue if
1798 * it was stopped due to lack of tx wrbs.
1799 */
1800 if (netif_queue_stopped(adapter->netdev) &&
6b7c5b94 1801 atomic_read(&txq->used) < txq->len / 2) {
5fb379ee
SP		 1802 netif_wake_queue(adapter->netdev);
1803 }
1804
3abcdeda
SP		 1805 tx_stats(adapter)->be_tx_events++;
1806 tx_stats(adapter)->be_tx_compl += tx_compl;
6b7c5b94 1807 }
6b7c5b94
SP		 1808
1809 return 1;
1810}
1811
d053de91 1812void be_detect_dump_ue(struct be_adapter *adapter)
7c185276
AK		 1813{
1814 u32 ue_status_lo, ue_status_hi, ue_status_lo_mask, ue_status_hi_mask;
1815 u32 i;
1816
1817 pci_read_config_dword(adapter->pdev,
1818 PCICFG_UE_STATUS_LOW, &ue_status_lo);
1819 pci_read_config_dword(adapter->pdev,
1820 PCICFG_UE_STATUS_HIGH, &ue_status_hi);
1821 pci_read_config_dword(adapter->pdev,
1822 PCICFG_UE_STATUS_LOW_MASK, &ue_status_lo_mask);
1823 pci_read_config_dword(adapter->pdev,
1824 PCICFG_UE_STATUS_HI_MASK, &ue_status_hi_mask);
1825
1826 ue_status_lo = (ue_status_lo & (~ue_status_lo_mask));
1827 ue_status_hi = (ue_status_hi & (~ue_status_hi_mask));
1828
d053de91
AK		 1829 if (ue_status_lo || ue_status_hi) {
1830 adapter->ue_detected = true;
7acc2087 1831 adapter->eeh_err = true;
d053de91
AK		 1832 dev_err(&adapter->pdev->dev, "UE Detected!!\n");
1833 }
1834
7c185276
AK		 1835 if (ue_status_lo) {
1836 for (i = 0; ue_status_lo; ue_status_lo >>= 1, i++) {
1837 if (ue_status_lo & 1)
1838 dev_err(&adapter->pdev->dev,
1839 "UE: %s bit set\n", ue_status_low_desc[i]);
1840 }
1841 }
1842 if (ue_status_hi) {
1843 for (i = 0; ue_status_hi; ue_status_hi >>= 1, i++) {
1844 if (ue_status_hi & 1)
1845 dev_err(&adapter->pdev->dev,
1846 "UE: %s bit set\n", ue_status_hi_desc[i]);
1847 }
1848 }
1849
1850}
1851
ea1dae11
SP		 1852static void be_worker(struct work_struct *work)
1853{
1854 struct be_adapter *adapter =
1855 container_of(work, struct be_adapter, work.work);
3abcdeda
SP		 1856 struct be_rx_obj *rxo;
1857 int i;
ea1dae11 1858
f203af70
SK		 1859 /* when interrupts are not yet enabled, just reap any pending
1860 * mcc completions */
1861 if (!netif_running(adapter->netdev)) {
1862 int mcc_compl, status = 0;
1863
1864 mcc_compl = be_process_mcc(adapter, &status);
1865
1866 if (mcc_compl) {
1867 struct be_mcc_obj *mcc_obj = &adapter->mcc_obj;
1868 be_cq_notify(adapter, mcc_obj->cq.id, false, mcc_compl);
1869 }
9b037f38
AK		 1870
1871 if (!adapter->ue_detected && !lancer_chip(adapter))
1872 be_detect_dump_ue(adapter);
1873
f203af70
SK		 1874 goto reschedule;
1875 }
1876
b2aebe6d 1877 if (!adapter->stats_cmd_sent)
3abcdeda 1878 be_cmd_get_stats(adapter, &adapter->stats_cmd);
ea1dae11 1879
4097f663 1880 be_tx_rate_update(adapter);
4097f663 1881
3abcdeda
SP		 1882 for_all_rx_queues(adapter, rxo, i) {
1883 be_rx_rate_update(rxo);
1884 be_rx_eqd_update(adapter, rxo);
1885
1886 if (rxo->rx_post_starved) {
1887 rxo->rx_post_starved = false;
1829b086 1888 be_post_rx_frags(rxo, GFP_KERNEL);
3abcdeda 1889 }
ea1dae11 1890 }
fe6d2a38 1891 if (!adapter->ue_detected && !lancer_chip(adapter))
d053de91 1892 be_detect_dump_ue(adapter);
ea1dae11 1893
f203af70 1894reschedule:
ea1dae11
SP		 1895 schedule_delayed_work(&adapter->work, msecs_to_jiffies(1000));
1896}
1897
8d56ff11
SP		 1898static void be_msix_disable(struct be_adapter *adapter)
1899{
ac6a0c4a 1900 if (msix_enabled(adapter)) {
8d56ff11 1901 pci_disable_msix(adapter->pdev);
ac6a0c4a 1902 adapter->num_msix_vec = 0;
3abcdeda
SP		 1903 }
1904}
1905
6b7c5b94
SP		 1906static void be_msix_enable(struct be_adapter *adapter)
1907{
3abcdeda 1908#define BE_MIN_MSIX_VECTORS (1 + 1) /* Rx + Tx */
ac6a0c4a 1909 int i, status, num_vec;
6b7c5b94 1910
ac6a0c4a 1911 num_vec = be_num_rxqs_want(adapter) + 1;
3abcdeda 1912
ac6a0c4a 1913 for (i = 0; i < num_vec; i++)
6b7c5b94
SP		 1914 adapter->msix_entries[i].entry = i;
1915
ac6a0c4a 1916 status = pci_enable_msix(adapter->pdev, adapter->msix_entries, num_vec);
3abcdeda
SP		 1917 if (status == 0) {
1918 goto done;
1919 } else if (status >= BE_MIN_MSIX_VECTORS) {
ac6a0c4a 1920 num_vec = status;
3abcdeda 1921 if (pci_enable_msix(adapter->pdev, adapter->msix_entries,
ac6a0c4a 1922 num_vec) == 0)
3abcdeda 1923 goto done;
3abcdeda
SP		 1924 }
1925 return;
1926done:
ac6a0c4a
SP		 1927 adapter->num_msix_vec = num_vec;
1928 return;
6b7c5b94
SP		 1929}
1930
ba343c77
SB		 1931static void be_sriov_enable(struct be_adapter *adapter)
1932{
344dbf10 1933 be_check_sriov_fn_type(adapter);
6dedec81 1934#ifdef CONFIG_PCI_IOV
ba343c77 1935 if (be_physfn(adapter) && num_vfs) {
6dedec81
AK		 1936 int status;
1937
ba343c77
SB		 1938 status = pci_enable_sriov(adapter->pdev, num_vfs);
1939 adapter->sriov_enabled = status ? false : true;
1940 }
1941#endif
ba343c77
SB		 1942}
1943
1944static void be_sriov_disable(struct be_adapter *adapter)
1945{
1946#ifdef CONFIG_PCI_IOV
1947 if (adapter->sriov_enabled) {
1948 pci_disable_sriov(adapter->pdev);
1949 adapter->sriov_enabled = false;
1950 }
1951#endif
1952}
1953
fe6d2a38
SP		 1954static inline int be_msix_vec_get(struct be_adapter *adapter,
1955 struct be_eq_obj *eq_obj)
6b7c5b94 1956{
fe6d2a38 1957 return adapter->msix_entries[eq_obj->msix_vec_idx].vector;
6b7c5b94
SP		 1958}
1959
b628bde2
SP		 1960static int be_request_irq(struct be_adapter *adapter,
1961 struct be_eq_obj *eq_obj,
3abcdeda 1962 void *handler, char *desc, void *context)
6b7c5b94
SP		 1963{
1964 struct net_device *netdev = adapter->netdev;
b628bde2
SP		 1965 int vec;
1966
1967 sprintf(eq_obj->desc, "%s-%s", netdev->name, desc);
fe6d2a38 1968 vec = be_msix_vec_get(adapter, eq_obj);
3abcdeda 1969 return request_irq(vec, handler, 0, eq_obj->desc, context);
b628bde2
SP		 1970}
1971
3abcdeda
SP		 1972static void be_free_irq(struct be_adapter *adapter, struct be_eq_obj *eq_obj,
1973 void *context)
b628bde2 1974{
fe6d2a38 1975 int vec = be_msix_vec_get(adapter, eq_obj);
3abcdeda 1976 free_irq(vec, context);
b628bde2 1977}
6b7c5b94 1978
b628bde2
SP		 1979static int be_msix_register(struct be_adapter *adapter)
1980{
3abcdeda
SP		 1981 struct be_rx_obj *rxo;
1982 int status, i;
1983 char qname[10];
b628bde2 1984
3abcdeda
SP		 1985 status = be_request_irq(adapter, &adapter->tx_eq, be_msix_tx_mcc, "tx",
1986 adapter);
6b7c5b94
SP		 1987 if (status)
1988 goto err;
1989
3abcdeda
SP		 1990 for_all_rx_queues(adapter, rxo, i) {
1991 sprintf(qname, "rxq%d", i);
1992 status = be_request_irq(adapter, &rxo->rx_eq, be_msix_rx,
1993 qname, rxo);
1994 if (status)
1995 goto err_msix;
1996 }
b628bde2 1997
6b7c5b94 1998 return 0;
b628bde2 1999
3abcdeda
SP		 2000err_msix:
2001 be_free_irq(adapter, &adapter->tx_eq, adapter);
2002
2003 for (i--, rxo = &adapter->rx_obj[i]; i >= 0; i--, rxo--)
2004 be_free_irq(adapter, &rxo->rx_eq, rxo);
2005
6b7c5b94
SP		 2006err:
2007 dev_warn(&adapter->pdev->dev,
2008 "MSIX Request IRQ failed - err %d\n", status);
ac6a0c4a 2009 be_msix_disable(adapter);
6b7c5b94
SP		 2010 return status;
2011}
2012
2013static int be_irq_register(struct be_adapter *adapter)
2014{
2015 struct net_device *netdev = adapter->netdev;
2016 int status;
2017
ac6a0c4a 2018 if (msix_enabled(adapter)) {
6b7c5b94
SP		 2019 status = be_msix_register(adapter);
2020 if (status == 0)
2021 goto done;
ba343c77
SB		 2022 /* INTx is not supported for VF */
2023 if (!be_physfn(adapter))
2024 return status;
6b7c5b94
SP		 2025 }
2026
2027 /* INTx */
2028 netdev->irq = adapter->pdev->irq;
2029 status = request_irq(netdev->irq, be_intx, IRQF_SHARED, netdev->name,
2030 adapter);
2031 if (status) {
2032 dev_err(&adapter->pdev->dev,
2033 "INTx request IRQ failed - err %d\n", status);
2034 return status;
2035 }
2036done:
2037 adapter->isr_registered = true;
2038 return 0;
2039}
2040
2041static void be_irq_unregister(struct be_adapter *adapter)
2042{
2043 struct net_device *netdev = adapter->netdev;
3abcdeda
SP		 2044 struct be_rx_obj *rxo;
2045 int i;
6b7c5b94
SP		 2046
2047 if (!adapter->isr_registered)
2048 return;
2049
2050 /* INTx */
ac6a0c4a 2051 if (!msix_enabled(adapter)) {
6b7c5b94
SP		 2052 free_irq(netdev->irq, adapter);
2053 goto done;
2054 }
2055
2056 /* MSIx */
3abcdeda
SP		 2057 be_free_irq(adapter, &adapter->tx_eq, adapter);
2058
2059 for_all_rx_queues(adapter, rxo, i)
2060 be_free_irq(adapter, &rxo->rx_eq, rxo);
2061
6b7c5b94
SP		 2062done:
2063 adapter->isr_registered = false;
6b7c5b94
SP		 2064}
2065
889cd4b2
SP		 2066static int be_close(struct net_device *netdev)
2067{
2068 struct be_adapter *adapter = netdev_priv(netdev);
3abcdeda 2069 struct be_rx_obj *rxo;
889cd4b2 2070 struct be_eq_obj *tx_eq = &adapter->tx_eq;
3abcdeda 2071 int vec, i;
889cd4b2 2072
889cd4b2
SP		 2073 be_async_mcc_disable(adapter);
2074
889cd4b2
SP		 2075 netif_carrier_off(netdev);
2076 adapter->link_up = false;
2077
fe6d2a38
SP		 2078 if (!lancer_chip(adapter))
2079 be_intr_set(adapter, false);
889cd4b2 2080
63fcb27f
PR		 2081 for_all_rx_queues(adapter, rxo, i)
2082 napi_disable(&rxo->rx_eq.napi);
2083
2084 napi_disable(&tx_eq->napi);
2085
2086 if (lancer_chip(adapter)) {
2087 be_cq_notify(adapter, adapter->tx_obj.cq.id, false, 0);
2088 be_cq_notify(adapter, adapter->mcc_obj.cq.id, false, 0);
2089 for_all_rx_queues(adapter, rxo, i)
2090 be_cq_notify(adapter, rxo->cq.id, false, 0);
2091 }
2092
ac6a0c4a 2093 if (msix_enabled(adapter)) {
fe6d2a38 2094 vec = be_msix_vec_get(adapter, tx_eq);
889cd4b2 2095 synchronize_irq(vec);
3abcdeda
SP		 2096
2097 for_all_rx_queues(adapter, rxo, i) {
fe6d2a38 2098 vec = be_msix_vec_get(adapter, &rxo->rx_eq);
3abcdeda
SP		 2099 synchronize_irq(vec);
2100 }
889cd4b2
SP		 2101 } else {
2102 synchronize_irq(netdev->irq);
2103 }
2104 be_irq_unregister(adapter);
2105
889cd4b2
SP		 2106 /* Wait for all pending tx completions to arrive so that
2107 * all tx skbs are freed.
2108 */
2109 be_tx_compl_clean(adapter);
2110
2111 return 0;
2112}
2113
6b7c5b94
SP		 2114static int be_open(struct net_device *netdev)
2115{
2116 struct be_adapter *adapter = netdev_priv(netdev);
6b7c5b94 2117 struct be_eq_obj *tx_eq = &adapter->tx_eq;
3abcdeda 2118 struct be_rx_obj *rxo;
a8f447bd 2119 bool link_up;
3abcdeda 2120 int status, i;
0388f251
SB		 2121 u8 mac_speed;
2122 u16 link_speed;
5fb379ee 2123
3abcdeda 2124 for_all_rx_queues(adapter, rxo, i) {
1829b086 2125 be_post_rx_frags(rxo, GFP_KERNEL);
3abcdeda
SP		 2126 napi_enable(&rxo->rx_eq.napi);
2127 }
5fb379ee
SP		 2128 napi_enable(&tx_eq->napi);
2129
2130 be_irq_register(adapter);
2131
fe6d2a38
SP		 2132 if (!lancer_chip(adapter))
2133 be_intr_set(adapter, true);
5fb379ee
SP		 2134
2135 /* The evt queues are created in unarmed state; arm them */
3abcdeda
SP		 2136 for_all_rx_queues(adapter, rxo, i) {
2137 be_eq_notify(adapter, rxo->rx_eq.q.id, true, false, 0);
2138 be_cq_notify(adapter, rxo->cq.id, true, 0);
2139 }
8788fdc2 2140 be_eq_notify(adapter, tx_eq->q.id, true, false, 0);
5fb379ee 2141
7a1e9b20
SP		 2142 /* Now that interrupts are on we can process async mcc */
2143 be_async_mcc_enable(adapter);
2144
0388f251
SB		 2145 status = be_cmd_link_status_query(adapter, &link_up, &mac_speed,
2146 &link_speed);
a8f447bd 2147 if (status)
889cd4b2 2148 goto err;
a8f447bd 2149 be_link_status_update(adapter, link_up);
5fb379ee 2150
889cd4b2 2151 if (be_physfn(adapter)) {
1da87b7f 2152 status = be_vid_config(adapter, false, 0);
889cd4b2
SP		 2153 if (status)
2154 goto err;
4f2aa89c 2155
ba343c77
SB		 2156 status = be_cmd_set_flow_control(adapter,
2157 adapter->tx_fc, adapter->rx_fc);
2158 if (status)
889cd4b2 2159 goto err;
ba343c77 2160 }
4f2aa89c 2161
889cd4b2
SP		 2162 return 0;
2163err:
2164 be_close(adapter->netdev);
2165 return -EIO;
5fb379ee
SP		 2166}
2167
71d8d1b5
AK		 2168static int be_setup_wol(struct be_adapter *adapter, bool enable)
2169{
2170 struct be_dma_mem cmd;
2171 int status = 0;
2172 u8 mac[ETH_ALEN];
2173
2174 memset(mac, 0, ETH_ALEN);
2175
2176 cmd.size = sizeof(struct be_cmd_req_acpi_wol_magic_config);
2b7bcebf
IV		 2177 cmd.va = dma_alloc_coherent(&adapter->pdev->dev, cmd.size, &cmd.dma,
2178 GFP_KERNEL);
71d8d1b5
AK		 2179 if (cmd.va == NULL)
2180 return -1;
2181 memset(cmd.va, 0, cmd.size);
2182
2183 if (enable) {
2184 status = pci_write_config_dword(adapter->pdev,
2185 PCICFG_PM_CONTROL_OFFSET, PCICFG_PM_CONTROL_MASK);
2186 if (status) {
2187 dev_err(&adapter->pdev->dev,
2381a55c 2188 "Could not enable Wake-on-lan\n");
2b7bcebf
IV		 2189 dma_free_coherent(&adapter->pdev->dev, cmd.size, cmd.va,
2190 cmd.dma);
71d8d1b5
AK		 2191 return status;
2192 }
2193 status = be_cmd_enable_magic_wol(adapter,
2194 adapter->netdev->dev_addr, &cmd);
2195 pci_enable_wake(adapter->pdev, PCI_D3hot, 1);
2196 pci_enable_wake(adapter->pdev, PCI_D3cold, 1);
2197 } else {
2198 status = be_cmd_enable_magic_wol(adapter, mac, &cmd);
2199 pci_enable_wake(adapter->pdev, PCI_D3hot, 0);
2200 pci_enable_wake(adapter->pdev, PCI_D3cold, 0);
2201 }
2202
2b7bcebf 2203 dma_free_coherent(&adapter->pdev->dev, cmd.size, cmd.va, cmd.dma);
71d8d1b5
AK		 2204 return status;
2205}
2206
6d87f5c3
AK		 2207/*
2208 * Generate a seed MAC address from the PF MAC Address using jhash.
2209 * MAC Address for VFs are assigned incrementally starting from the seed.
2210 * These addresses are programmed in the ASIC by the PF and the VF driver
2211 * queries for the MAC address during its probe.
2212 */
2213static inline int be_vf_eth_addr_config(struct be_adapter *adapter)
2214{
2215 u32 vf = 0;
3abcdeda 2216 int status = 0;
6d87f5c3
AK		 2217 u8 mac[ETH_ALEN];
2218
2219 be_vf_eth_addr_generate(adapter, mac);
2220
2221 for (vf = 0; vf < num_vfs; vf++) {
2222 status = be_cmd_pmac_add(adapter, mac,
2223 adapter->vf_cfg[vf].vf_if_handle,
f8617e08
AK		 2224 &adapter->vf_cfg[vf].vf_pmac_id,
2225 vf + 1);
6d87f5c3
AK		 2226 if (status)
2227 dev_err(&adapter->pdev->dev,
2228 "Mac address add failed for VF %d\n", vf);
2229 else
2230 memcpy(adapter->vf_cfg[vf].vf_mac_addr, mac, ETH_ALEN);
2231
2232 mac[5] += 1;
2233 }
2234 return status;
2235}
2236
2237static inline void be_vf_eth_addr_rem(struct be_adapter *adapter)
2238{
2239 u32 vf;
2240
2241 for (vf = 0; vf < num_vfs; vf++) {
2242 if (adapter->vf_cfg[vf].vf_pmac_id != BE_INVALID_PMAC_ID)
2243 be_cmd_pmac_del(adapter,
2244 adapter->vf_cfg[vf].vf_if_handle,
f8617e08 2245 adapter->vf_cfg[vf].vf_pmac_id, vf + 1);
6d87f5c3
AK		 2246 }
2247}
2248
5fb379ee
SP		 2249static int be_setup(struct be_adapter *adapter)
2250{
5fb379ee 2251 struct net_device *netdev = adapter->netdev;
ba343c77 2252 u32 cap_flags, en_flags, vf = 0;
6b7c5b94 2253 int status;
ba343c77
SB		 2254 u8 mac[ETH_ALEN];
2255
f21b538c
PR		 2256 cap_flags = en_flags = BE_IF_FLAGS_UNTAGGED |
2257 BE_IF_FLAGS_BROADCAST |
2258 BE_IF_FLAGS_MULTICAST;
6b7c5b94 2259
ba343c77
SB		 2260 if (be_physfn(adapter)) {
2261 cap_flags |= BE_IF_FLAGS_MCAST_PROMISCUOUS |
2262 BE_IF_FLAGS_PROMISCUOUS |
2263 BE_IF_FLAGS_PASS_L3L4_ERRORS;
2264 en_flags |= BE_IF_FLAGS_PASS_L3L4_ERRORS;
3abcdeda 2265
ac6a0c4a 2266 if (adapter->function_caps & BE_FUNCTION_CAPS_RSS) {
3abcdeda
SP		 2267 cap_flags |= BE_IF_FLAGS_RSS;
2268 en_flags |= BE_IF_FLAGS_RSS;
2269 }
ba343c77 2270 }
73d540f2
SP		 2271
2272 status = be_cmd_if_create(adapter, cap_flags, en_flags,
2273 netdev->dev_addr, false/* pmac_invalid */,
ba343c77 2274 &adapter->if_handle, &adapter->pmac_id, 0);
6b7c5b94
SP		 2275 if (status != 0)
2276 goto do_none;
2277
ba343c77 2278 if (be_physfn(adapter)) {
c99ac3e7
AK		 2279 if (adapter->sriov_enabled) {
2280 while (vf < num_vfs) {
2281 cap_flags = en_flags = BE_IF_FLAGS_UNTAGGED |
2282 BE_IF_FLAGS_BROADCAST;
2283 status = be_cmd_if_create(adapter, cap_flags,
2284 en_flags, mac, true,
64600ea5 2285 &adapter->vf_cfg[vf].vf_if_handle,
ba343c77 2286 NULL, vf+1);
c99ac3e7
AK		 2287 if (status) {
2288 dev_err(&adapter->pdev->dev,
2289 "Interface Create failed for VF %d\n",
2290 vf);
2291 goto if_destroy;
2292 }
2293 adapter->vf_cfg[vf].vf_pmac_id =
2294 BE_INVALID_PMAC_ID;
2295 vf++;
ba343c77 2296 }
84e5b9f7 2297 }
c99ac3e7 2298 } else {
ba343c77
SB		 2299 status = be_cmd_mac_addr_query(adapter, mac,
2300 MAC_ADDRESS_TYPE_NETWORK, false, adapter->if_handle);
2301 if (!status) {
2302 memcpy(adapter->netdev->dev_addr, mac, ETH_ALEN);
2303 memcpy(adapter->netdev->perm_addr, mac, ETH_ALEN);
2304 }
2305 }
2306
6b7c5b94
SP		 2307 status = be_tx_queues_create(adapter);
2308 if (status != 0)
2309 goto if_destroy;
2310
2311 status = be_rx_queues_create(adapter);
2312 if (status != 0)
2313 goto tx_qs_destroy;
2314
5fb379ee
SP		 2315 status = be_mcc_queues_create(adapter);
2316 if (status != 0)
2317 goto rx_qs_destroy;
6b7c5b94 2318
0dffc83e
AK		 2319 adapter->link_speed = -1;
2320
6b7c5b94
SP		 2321 return 0;
2322
6d87f5c3 2323 be_mcc_queues_destroy(adapter);
5fb379ee
SP		 2324rx_qs_destroy:
2325 be_rx_queues_destroy(adapter);
6b7c5b94
SP		 2326tx_qs_destroy:
2327 be_tx_queues_destroy(adapter);
2328if_destroy:
c99ac3e7
AK		 2329 if (be_physfn(adapter) && adapter->sriov_enabled)
2330 for (vf = 0; vf < num_vfs; vf++)
2331 if (adapter->vf_cfg[vf].vf_if_handle)
2332 be_cmd_if_destroy(adapter,
658681f7
AK		 2333 adapter->vf_cfg[vf].vf_if_handle,
2334 vf + 1);
2335 be_cmd_if_destroy(adapter, adapter->if_handle, 0);
6b7c5b94
SP		 2336do_none:
2337 return status;
2338}
2339
5fb379ee
SP		 2340static int be_clear(struct be_adapter *adapter)
2341{
7ab8b0b4
AK		 2342 int vf;
2343
c99ac3e7 2344 if (be_physfn(adapter) && adapter->sriov_enabled)
6d87f5c3
AK		 2345 be_vf_eth_addr_rem(adapter);
2346
1a8887d8 2347 be_mcc_queues_destroy(adapter);
5fb379ee
SP		 2348 be_rx_queues_destroy(adapter);
2349 be_tx_queues_destroy(adapter);
2350
7ab8b0b4
AK		 2351 if (be_physfn(adapter) && adapter->sriov_enabled)
2352 for (vf = 0; vf < num_vfs; vf++)
2353 if (adapter->vf_cfg[vf].vf_if_handle)
2354 be_cmd_if_destroy(adapter,
2355 adapter->vf_cfg[vf].vf_if_handle,
2356 vf + 1);
2357
658681f7 2358 be_cmd_if_destroy(adapter, adapter->if_handle, 0);
5fb379ee 2359
2243e2e9
SP		 2360 /* tell fw we're done with firing cmds */
2361 be_cmd_fw_clean(adapter);
5fb379ee
SP		 2362 return 0;
2363}
2364
6b7c5b94 2365
84517482 2366#define FW_FILE_HDR_SIGN "ServerEngines Corp. "
fa9a6fed 2367static bool be_flash_redboot(struct be_adapter *adapter,
3f0d4560
AK		 2368 const u8 *p, u32 img_start, int image_size,
2369 int hdr_size)
fa9a6fed
SB		 2370{
2371 u32 crc_offset;
2372 u8 flashed_crc[4];
2373 int status;
3f0d4560
AK		 2374
2375 crc_offset = hdr_size + img_start + image_size - 4;
2376
fa9a6fed 2377 p += crc_offset;
3f0d4560
AK		 2378
2379 status = be_cmd_get_flash_crc(adapter, flashed_crc,
f510fc64 2380 (image_size - 4));
fa9a6fed
SB		 2381 if (status) {
2382 dev_err(&adapter->pdev->dev,
2383 "could not get crc from flash, not flashing redboot\n");
2384 return false;
2385 }
2386
2387 /*update redboot only if crc does not match*/
2388 if (!memcmp(flashed_crc, p, 4))
2389 return false;
2390 else
2391 return true;
fa9a6fed
SB		 2392}
2393
3f0d4560 2394static int be_flash_data(struct be_adapter *adapter,
84517482 2395 const struct firmware *fw,
3f0d4560
AK		 2396 struct be_dma_mem *flash_cmd, int num_of_images)
2397
84517482 2398{
3f0d4560
AK		 2399 int status = 0, i, filehdr_size = 0;
2400 u32 total_bytes = 0, flash_op;
84517482
AK		 2401 int num_bytes;
2402 const u8 *p = fw->data;
2403 struct be_cmd_write_flashrom *req = flash_cmd->va;
215faf9c 2404 const struct flash_comp *pflashcomp;
9fe96934 2405 int num_comp;
3f0d4560 2406
215faf9c 2407 static const struct flash_comp gen3_flash_types[9] = {
3f0d4560
AK		 2408 { FLASH_iSCSI_PRIMARY_IMAGE_START_g3, IMG_TYPE_ISCSI_ACTIVE,
2409 FLASH_IMAGE_MAX_SIZE_g3},
2410 { FLASH_REDBOOT_START_g3, IMG_TYPE_REDBOOT,
2411 FLASH_REDBOOT_IMAGE_MAX_SIZE_g3},
2412 { FLASH_iSCSI_BIOS_START_g3, IMG_TYPE_BIOS,
2413 FLASH_BIOS_IMAGE_MAX_SIZE_g3},
2414 { FLASH_PXE_BIOS_START_g3, IMG_TYPE_PXE_BIOS,
2415 FLASH_BIOS_IMAGE_MAX_SIZE_g3},
2416 { FLASH_FCoE_BIOS_START_g3, IMG_TYPE_FCOE_BIOS,
2417 FLASH_BIOS_IMAGE_MAX_SIZE_g3},
2418 { FLASH_iSCSI_BACKUP_IMAGE_START_g3, IMG_TYPE_ISCSI_BACKUP,
2419 FLASH_IMAGE_MAX_SIZE_g3},
2420 { FLASH_FCoE_PRIMARY_IMAGE_START_g3, IMG_TYPE_FCOE_FW_ACTIVE,
2421 FLASH_IMAGE_MAX_SIZE_g3},
2422 { FLASH_FCoE_BACKUP_IMAGE_START_g3, IMG_TYPE_FCOE_FW_BACKUP,
9fe96934
SB		 2423 FLASH_IMAGE_MAX_SIZE_g3},
2424 { FLASH_NCSI_START_g3, IMG_TYPE_NCSI_FW,
2425 FLASH_NCSI_IMAGE_MAX_SIZE_g3}
3f0d4560 2426 };
215faf9c 2427 static const struct flash_comp gen2_flash_types[8] = {
3f0d4560
AK		 2428 { FLASH_iSCSI_PRIMARY_IMAGE_START_g2, IMG_TYPE_ISCSI_ACTIVE,
2429 FLASH_IMAGE_MAX_SIZE_g2},
2430 { FLASH_REDBOOT_START_g2, IMG_TYPE_REDBOOT,
2431 FLASH_REDBOOT_IMAGE_MAX_SIZE_g2},
2432 { FLASH_iSCSI_BIOS_START_g2, IMG_TYPE_BIOS,
2433 FLASH_BIOS_IMAGE_MAX_SIZE_g2},
2434 { FLASH_PXE_BIOS_START_g2, IMG_TYPE_PXE_BIOS,
2435 FLASH_BIOS_IMAGE_MAX_SIZE_g2},
2436 { FLASH_FCoE_BIOS_START_g2, IMG_TYPE_FCOE_BIOS,
2437 FLASH_BIOS_IMAGE_MAX_SIZE_g2},
2438 { FLASH_iSCSI_BACKUP_IMAGE_START_g2, IMG_TYPE_ISCSI_BACKUP,
2439 FLASH_IMAGE_MAX_SIZE_g2},
2440 { FLASH_FCoE_PRIMARY_IMAGE_START_g2, IMG_TYPE_FCOE_FW_ACTIVE,
2441 FLASH_IMAGE_MAX_SIZE_g2},
2442 { FLASH_FCoE_BACKUP_IMAGE_START_g2, IMG_TYPE_FCOE_FW_BACKUP,
2443 FLASH_IMAGE_MAX_SIZE_g2}
2444 };
2445
2446 if (adapter->generation == BE_GEN3) {
2447 pflashcomp = gen3_flash_types;
2448 filehdr_size = sizeof(struct flash_file_hdr_g3);
215faf9c 2449 num_comp = ARRAY_SIZE(gen3_flash_types);
3f0d4560
AK		 2450 } else {
2451 pflashcomp = gen2_flash_types;
2452 filehdr_size = sizeof(struct flash_file_hdr_g2);
215faf9c 2453 num_comp = ARRAY_SIZE(gen2_flash_types);
84517482 2454 }
9fe96934
SB		 2455 for (i = 0; i < num_comp; i++) {
2456 if ((pflashcomp[i].optype == IMG_TYPE_NCSI_FW) &&
2457 memcmp(adapter->fw_ver, "3.102.148.0", 11) < 0)
2458 continue;
3f0d4560
AK		 2459 if ((pflashcomp[i].optype == IMG_TYPE_REDBOOT) &&
2460 (!be_flash_redboot(adapter, fw->data,
fae21a4d
AK		 2461 pflashcomp[i].offset, pflashcomp[i].size, filehdr_size +
2462 (num_of_images * sizeof(struct image_hdr)))))
3f0d4560
AK		 2463 continue;
2464 p = fw->data;
2465 p += filehdr_size + pflashcomp[i].offset
2466 + (num_of_images * sizeof(struct image_hdr));
2467 if (p + pflashcomp[i].size > fw->data + fw->size)
84517482 2468 return -1;
3f0d4560
AK		 2469 total_bytes = pflashcomp[i].size;
2470 while (total_bytes) {
2471 if (total_bytes > 32*1024)
2472 num_bytes = 32*1024;
2473 else
2474 num_bytes = total_bytes;
2475 total_bytes -= num_bytes;
2476
2477 if (!total_bytes)
2478 flash_op = FLASHROM_OPER_FLASH;
2479 else
2480 flash_op = FLASHROM_OPER_SAVE;
2481 memcpy(req->params.data_buf, p, num_bytes);
2482 p += num_bytes;
2483 status = be_cmd_write_flashrom(adapter, flash_cmd,
2484 pflashcomp[i].optype, flash_op, num_bytes);
2485 if (status) {
2486 dev_err(&adapter->pdev->dev,
2487 "cmd to write to flash rom failed.\n");
2488 return -1;
2489 }
2490 yield();
84517482 2491 }
84517482 2492 }
84517482
AK		 2493 return 0;
2494}
2495
3f0d4560
AK		 2496static int get_ufigen_type(struct flash_file_hdr_g2 *fhdr)
2497{
2498 if (fhdr == NULL)
2499 return 0;
2500 if (fhdr->build[0] == '3')
2501 return BE_GEN3;
2502 else if (fhdr->build[0] == '2')
2503 return BE_GEN2;
2504 else
2505 return 0;
2506}
2507
84517482
AK		 2508int be_load_fw(struct be_adapter *adapter, u8 *func)
2509{
2510 char fw_file[ETHTOOL_FLASH_MAX_FILENAME];
2511 const struct firmware *fw;
3f0d4560
AK		 2512 struct flash_file_hdr_g2 *fhdr;
2513 struct flash_file_hdr_g3 *fhdr3;
2514 struct image_hdr *img_hdr_ptr = NULL;
84517482 2515 struct be_dma_mem flash_cmd;
8b93b710 2516 int status, i = 0, num_imgs = 0;
84517482 2517 const u8 *p;
84517482 2518
d9efd2af
SB		 2519 if (!netif_running(adapter->netdev)) {
2520 dev_err(&adapter->pdev->dev,
2521 "Firmware load not allowed (interface is down)\n");
2522 return -EPERM;
2523 }
2524
84517482
AK		 2525 strcpy(fw_file, func);
2526
2527 status = request_firmware(&fw, fw_file, &adapter->pdev->dev);
2528 if (status)
2529 goto fw_exit;
2530
2531 p = fw->data;
3f0d4560 2532 fhdr = (struct flash_file_hdr_g2 *) p;
84517482
AK		 2533 dev_info(&adapter->pdev->dev, "Flashing firmware file %s\n", fw_file);
2534
84517482 2535 flash_cmd.size = sizeof(struct be_cmd_write_flashrom) + 32*1024;
2b7bcebf
IV		 2536 flash_cmd.va = dma_alloc_coherent(&adapter->pdev->dev, flash_cmd.size,
2537 &flash_cmd.dma, GFP_KERNEL);
84517482
AK		 2538 if (!flash_cmd.va) {
2539 status = -ENOMEM;
2540 dev_err(&adapter->pdev->dev,
2541 "Memory allocation failure while flashing\n");
2542 goto fw_exit;
2543 }
2544
3f0d4560
AK		 2545 if ((adapter->generation == BE_GEN3) &&
2546 (get_ufigen_type(fhdr) == BE_GEN3)) {
2547 fhdr3 = (struct flash_file_hdr_g3 *) fw->data;
8b93b710
AK		 2548 num_imgs = le32_to_cpu(fhdr3->num_imgs);
2549 for (i = 0; i < num_imgs; i++) {
3f0d4560
AK		 2550 img_hdr_ptr = (struct image_hdr *) (fw->data +
2551 (sizeof(struct flash_file_hdr_g3) +
8b93b710
AK		 2552 i * sizeof(struct image_hdr)));
2553 if (le32_to_cpu(img_hdr_ptr->imageid) == 1)
2554 status = be_flash_data(adapter, fw, &flash_cmd,
2555 num_imgs);
3f0d4560
AK		 2556 }
2557 } else if ((adapter->generation == BE_GEN2) &&
2558 (get_ufigen_type(fhdr) == BE_GEN2)) {
2559 status = be_flash_data(adapter, fw, &flash_cmd, 0);
2560 } else {
2561 dev_err(&adapter->pdev->dev,
2562 "UFI and Interface are not compatible for flashing\n");
2563 status = -1;
84517482
AK		 2564 }
2565
2b7bcebf
IV		 2566 dma_free_coherent(&adapter->pdev->dev, flash_cmd.size, flash_cmd.va,
2567 flash_cmd.dma);
84517482
AK		 2568 if (status) {
2569 dev_err(&adapter->pdev->dev, "Firmware load error\n");
2570 goto fw_exit;
2571 }
2572
af901ca1 2573 dev_info(&adapter->pdev->dev, "Firmware flashed successfully\n");
84517482
AK		 2574
2575fw_exit:
2576 release_firmware(fw);
2577 return status;
2578}
2579
6b7c5b94
SP		 2580static struct net_device_ops be_netdev_ops = {
2581 .ndo_open = be_open,
2582 .ndo_stop = be_close,
2583 .ndo_start_xmit = be_xmit,
6b7c5b94
SP		 2584 .ndo_set_rx_mode = be_set_multicast_list,
2585 .ndo_set_mac_address = be_mac_addr_set,
2586 .ndo_change_mtu = be_change_mtu,
2587 .ndo_validate_addr = eth_validate_addr,
2588 .ndo_vlan_rx_register = be_vlan_register,
2589 .ndo_vlan_rx_add_vid = be_vlan_add_vid,
2590 .ndo_vlan_rx_kill_vid = be_vlan_rem_vid,
64600ea5 2591 .ndo_set_vf_mac = be_set_vf_mac,
1da87b7f 2592 .ndo_set_vf_vlan = be_set_vf_vlan,
e1d18735 2593 .ndo_set_vf_tx_rate = be_set_vf_tx_rate,
64600ea5 2594 .ndo_get_vf_config = be_get_vf_config
6b7c5b94
SP		 2595};
2596
2597static void be_netdev_init(struct net_device *netdev)
2598{
2599 struct be_adapter *adapter = netdev_priv(netdev);
3abcdeda
SP		 2600 struct be_rx_obj *rxo;
2601 int i;
6b7c5b94
SP		 2602
2603 netdev->features |= NETIF_F_SG | NETIF_F_HW_VLAN_RX | NETIF_F_TSO |
79032644
MM		 2604 NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_FILTER |
2605 NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
49e4b847 2606 NETIF_F_GRO | NETIF_F_TSO6;
6b7c5b94 2607
79032644
MM		 2608 netdev->vlan_features |= NETIF_F_SG | NETIF_F_TSO |
2609 NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM;
51c59870 2610
fe6d2a38
SP		 2611 if (lancer_chip(adapter))
2612 netdev->vlan_features |= NETIF_F_TSO6;
2613
6b7c5b94
SP		 2614 netdev->flags |= IFF_MULTICAST;
2615
728a9972
AK		 2616 adapter->rx_csum = true;
2617
9e90c961
AK		 2618 /* Default settings for Rx and Tx flow control */
2619 adapter->rx_fc = true;
2620 adapter->tx_fc = true;
2621
c190e3c8
AK		 2622 netif_set_gso_max_size(netdev, 65535);
2623
6b7c5b94
SP		 2624 BE_SET_NETDEV_OPS(netdev, &be_netdev_ops);
2625
2626 SET_ETHTOOL_OPS(netdev, &be_ethtool_ops);
2627
3abcdeda
SP		 2628 for_all_rx_queues(adapter, rxo, i)
2629 netif_napi_add(netdev, &rxo->rx_eq.napi, be_poll_rx,
2630 BE_NAPI_WEIGHT);
2631
5fb379ee 2632 netif_napi_add(netdev, &adapter->tx_eq.napi, be_poll_tx_mcc,
6b7c5b94 2633 BE_NAPI_WEIGHT);
6b7c5b94
SP		 2634}
2635
2636static void be_unmap_pci_bars(struct be_adapter *adapter)
2637{
8788fdc2
SP		 2638 if (adapter->csr)
2639 iounmap(adapter->csr);
2640 if (adapter->db)
2641 iounmap(adapter->db);
ba343c77 2642 if (adapter->pcicfg && be_physfn(adapter))
8788fdc2 2643 iounmap(adapter->pcicfg);
6b7c5b94
SP		 2644}
2645
2646static int be_map_pci_bars(struct be_adapter *adapter)
2647{
2648 u8 __iomem *addr;
ba343c77 2649 int pcicfg_reg, db_reg;
6b7c5b94 2650
fe6d2a38
SP		 2651 if (lancer_chip(adapter)) {
2652 addr = ioremap_nocache(pci_resource_start(adapter->pdev, 0),
2653 pci_resource_len(adapter->pdev, 0));
2654 if (addr == NULL)
2655 return -ENOMEM;
2656 adapter->db = addr;
2657 return 0;
2658 }
2659
ba343c77
SB		 2660 if (be_physfn(adapter)) {
2661 addr = ioremap_nocache(pci_resource_start(adapter->pdev, 2),
2662 pci_resource_len(adapter->pdev, 2));
2663 if (addr == NULL)
2664 return -ENOMEM;
2665 adapter->csr = addr;
2666 }
6b7c5b94 2667
ba343c77 2668 if (adapter->generation == BE_GEN2) {
7b139c83 2669 pcicfg_reg = 1;
ba343c77
SB		 2670 db_reg = 4;
2671 } else {
7b139c83 2672 pcicfg_reg = 0;
ba343c77
SB		 2673 if (be_physfn(adapter))
2674 db_reg = 4;
2675 else
2676 db_reg = 0;
2677 }
2678 addr = ioremap_nocache(pci_resource_start(adapter->pdev, db_reg),
2679 pci_resource_len(adapter->pdev, db_reg));
6b7c5b94
SP		 2680 if (addr == NULL)
2681 goto pci_map_err;
ba343c77
SB		 2682 adapter->db = addr;
2683
2684 if (be_physfn(adapter)) {
2685 addr = ioremap_nocache(
2686 pci_resource_start(adapter->pdev, pcicfg_reg),
2687 pci_resource_len(adapter->pdev, pcicfg_reg));
2688 if (addr == NULL)
2689 goto pci_map_err;
2690 adapter->pcicfg = addr;
2691 } else
2692 adapter->pcicfg = adapter->db + SRIOV_VF_PCICFG_OFFSET;
6b7c5b94
SP		 2693
2694 return 0;
2695pci_map_err:
2696 be_unmap_pci_bars(adapter);
2697 return -ENOMEM;
2698}
2699
2700
2701static void be_ctrl_cleanup(struct be_adapter *adapter)
2702{
8788fdc2 2703 struct be_dma_mem *mem = &adapter->mbox_mem_alloced;
6b7c5b94
SP		 2704
2705 be_unmap_pci_bars(adapter);
2706
2707 if (mem->va)
2b7bcebf
IV		 2708 dma_free_coherent(&adapter->pdev->dev, mem->size, mem->va,
2709 mem->dma);
e7b909a6
SP		 2710
2711 mem = &adapter->mc_cmd_mem;
2712 if (mem->va)
2b7bcebf
IV		 2713 dma_free_coherent(&adapter->pdev->dev, mem->size, mem->va,
2714 mem->dma);
6b7c5b94
SP		 2715}
2716
6b7c5b94
SP		 2717static int be_ctrl_init(struct be_adapter *adapter)
2718{
8788fdc2
SP		 2719 struct be_dma_mem *mbox_mem_alloc = &adapter->mbox_mem_alloced;
2720 struct be_dma_mem *mbox_mem_align = &adapter->mbox_mem;
e7b909a6 2721 struct be_dma_mem *mc_cmd_mem = &adapter->mc_cmd_mem;
6b7c5b94 2722 int status;
6b7c5b94
SP		 2723
2724 status = be_map_pci_bars(adapter);
2725 if (status)
e7b909a6 2726 goto done;
6b7c5b94
SP		 2727
2728 mbox_mem_alloc->size = sizeof(struct be_mcc_mailbox) + 16;
2b7bcebf
IV		 2729 mbox_mem_alloc->va = dma_alloc_coherent(&adapter->pdev->dev,
2730 mbox_mem_alloc->size,
2731 &mbox_mem_alloc->dma,
2732 GFP_KERNEL);
6b7c5b94 2733 if (!mbox_mem_alloc->va) {
e7b909a6
SP		 2734 status = -ENOMEM;
2735 goto unmap_pci_bars;
6b7c5b94 2736 }
e7b909a6 2737
6b7c5b94
SP		 2738 mbox_mem_align->size = sizeof(struct be_mcc_mailbox);
2739 mbox_mem_align->va = PTR_ALIGN(mbox_mem_alloc->va, 16);
2740 mbox_mem_align->dma = PTR_ALIGN(mbox_mem_alloc->dma, 16);
2741 memset(mbox_mem_align->va, 0, sizeof(struct be_mcc_mailbox));
e7b909a6
SP		 2742
2743 mc_cmd_mem->size = sizeof(struct be_cmd_req_mcast_mac_config);
2b7bcebf
IV		 2744 mc_cmd_mem->va = dma_alloc_coherent(&adapter->pdev->dev,
2745 mc_cmd_mem->size, &mc_cmd_mem->dma,
2746 GFP_KERNEL);
e7b909a6
SP		 2747 if (mc_cmd_mem->va == NULL) {
2748 status = -ENOMEM;
2749 goto free_mbox;
2750 }
2751 memset(mc_cmd_mem->va, 0, mc_cmd_mem->size);
2752
2984961c 2753 mutex_init(&adapter->mbox_lock);
8788fdc2
SP		 2754 spin_lock_init(&adapter->mcc_lock);
2755 spin_lock_init(&adapter->mcc_cq_lock);
a8f447bd 2756
dd131e76 2757 init_completion(&adapter->flash_compl);
cf588477 2758 pci_save_state(adapter->pdev);
6b7c5b94 2759 return 0;
e7b909a6
SP		 2760
2761free_mbox:
2b7bcebf
IV		 2762 dma_free_coherent(&adapter->pdev->dev, mbox_mem_alloc->size,
2763 mbox_mem_alloc->va, mbox_mem_alloc->dma);
e7b909a6
SP		 2764
2765unmap_pci_bars:
2766 be_unmap_pci_bars(adapter);
2767
2768done:
2769 return status;
6b7c5b94
SP		 2770}
2771
2772static void be_stats_cleanup(struct be_adapter *adapter)
2773{
3abcdeda 2774 struct be_dma_mem *cmd = &adapter->stats_cmd;
6b7c5b94
SP		 2775
2776 if (cmd->va)
2b7bcebf
IV		 2777 dma_free_coherent(&adapter->pdev->dev, cmd->size,
2778 cmd->va, cmd->dma);
6b7c5b94
SP		 2779}
2780
2781static int be_stats_init(struct be_adapter *adapter)
2782{
3abcdeda 2783 struct be_dma_mem *cmd = &adapter->stats_cmd;
6b7c5b94
SP		 2784
2785 cmd->size = sizeof(struct be_cmd_req_get_stats);
2b7bcebf
IV		 2786 cmd->va = dma_alloc_coherent(&adapter->pdev->dev, cmd->size, &cmd->dma,
2787 GFP_KERNEL);
6b7c5b94
SP		 2788 if (cmd->va == NULL)
2789 return -1;
d291b9af 2790 memset(cmd->va, 0, cmd->size);
6b7c5b94
SP		 2791 return 0;
2792}
2793
2794static void __devexit be_remove(struct pci_dev *pdev)
2795{
2796 struct be_adapter *adapter = pci_get_drvdata(pdev);
8d56ff11 2797
6b7c5b94
SP		 2798 if (!adapter)
2799 return;
2800
f203af70
SK		 2801 cancel_delayed_work_sync(&adapter->work);
2802
6b7c5b94
SP		 2803 unregister_netdev(adapter->netdev);
2804
5fb379ee
SP		 2805 be_clear(adapter);
2806
6b7c5b94
SP		 2807 be_stats_cleanup(adapter);
2808
2809 be_ctrl_cleanup(adapter);
2810
ba343c77
SB		 2811 be_sriov_disable(adapter);
2812
8d56ff11 2813 be_msix_disable(adapter);
6b7c5b94
SP		 2814
2815 pci_set_drvdata(pdev, NULL);
2816 pci_release_regions(pdev);
2817 pci_disable_device(pdev);
2818
2819 free_netdev(adapter->netdev);
2820}
2821
2243e2e9 2822static int be_get_config(struct be_adapter *adapter)
6b7c5b94 2823{
6b7c5b94 2824 int status;
2243e2e9 2825 u8 mac[ETH_ALEN];
6b7c5b94 2826
2243e2e9 2827 status = be_cmd_get_fw_ver(adapter, adapter->fw_ver);
6b7c5b94
SP		 2828 if (status)
2829 return status;
2830
3abcdeda
SP		 2831 status = be_cmd_query_fw_cfg(adapter, &adapter->port_num,
2832 &adapter->function_mode, &adapter->function_caps);
43a04fdc
SP		 2833 if (status)
2834 return status;
2835
2243e2e9 2836 memset(mac, 0, ETH_ALEN);
ba343c77
SB		 2837
2838 if (be_physfn(adapter)) {
2839 status = be_cmd_mac_addr_query(adapter, mac,
2243e2e9 2840 MAC_ADDRESS_TYPE_NETWORK, true /*permanent */, 0);
ca9e4988 2841
ba343c77
SB		 2842 if (status)
2843 return status;
ca9e4988 2844
ba343c77
SB		 2845 if (!is_valid_ether_addr(mac))
2846 return -EADDRNOTAVAIL;
2847
2848 memcpy(adapter->netdev->dev_addr, mac, ETH_ALEN);
2849 memcpy(adapter->netdev->perm_addr, mac, ETH_ALEN);
2850 }
6b7c5b94 2851
3486be29 2852 if (adapter->function_mode & 0x400)
82903e4b
AK		 2853 adapter->max_vlans = BE_NUM_VLANS_SUPPORTED/4;
2854 else
2855 adapter->max_vlans = BE_NUM_VLANS_SUPPORTED;
2856
9e1453c5
AK		 2857 status = be_cmd_get_cntl_attributes(adapter);
2858 if (status)
2859 return status;
2860
2e588f84 2861 be_cmd_check_native_mode(adapter);
2243e2e9 2862 return 0;
6b7c5b94
SP		 2863}
2864
fe6d2a38
SP		 2865static int be_dev_family_check(struct be_adapter *adapter)
2866{
2867 struct pci_dev *pdev = adapter->pdev;
2868 u32 sli_intf = 0, if_type;
2869
2870 switch (pdev->device) {
2871 case BE_DEVICE_ID1:
2872 case OC_DEVICE_ID1:
2873 adapter->generation = BE_GEN2;
2874 break;
2875 case BE_DEVICE_ID2:
2876 case OC_DEVICE_ID2:
2877 adapter->generation = BE_GEN3;
2878 break;
2879 case OC_DEVICE_ID3:
2880 pci_read_config_dword(pdev, SLI_INTF_REG_OFFSET, &sli_intf);
2881 if_type = (sli_intf & SLI_INTF_IF_TYPE_MASK) >>
2882 SLI_INTF_IF_TYPE_SHIFT;
2883
2884 if (((sli_intf & SLI_INTF_VALID_MASK) != SLI_INTF_VALID) ||
2885 if_type != 0x02) {
2886 dev_err(&pdev->dev, "SLI_INTF reg val is not valid\n");
2887 return -EINVAL;
2888 }
2889 if (num_vfs > 0) {
2890 dev_err(&pdev->dev, "VFs not supported\n");
2891 return -EINVAL;
2892 }
2893 adapter->sli_family = ((sli_intf & SLI_INTF_FAMILY_MASK) >>
2894 SLI_INTF_FAMILY_SHIFT);
2895 adapter->generation = BE_GEN3;
2896 break;
2897 default:
2898 adapter->generation = 0;
2899 }
2900 return 0;
2901}
2902
37eed1cb
PR		 2903static int lancer_wait_ready(struct be_adapter *adapter)
2904{
2905#define SLIPORT_READY_TIMEOUT 500
2906 u32 sliport_status;
2907 int status = 0, i;
2908
2909 for (i = 0; i < SLIPORT_READY_TIMEOUT; i++) {
2910 sliport_status = ioread32(adapter->db + SLIPORT_STATUS_OFFSET);
2911 if (sliport_status & SLIPORT_STATUS_RDY_MASK)
2912 break;
2913
2914 msleep(20);
2915 }
2916
2917 if (i == SLIPORT_READY_TIMEOUT)
2918 status = -1;
2919
2920 return status;
2921}
2922
2923static int lancer_test_and_set_rdy_state(struct be_adapter *adapter)
2924{
2925 int status;
2926 u32 sliport_status, err, reset_needed;
2927 status = lancer_wait_ready(adapter);
2928 if (!status) {
2929 sliport_status = ioread32(adapter->db + SLIPORT_STATUS_OFFSET);
2930 err = sliport_status & SLIPORT_STATUS_ERR_MASK;
2931 reset_needed = sliport_status & SLIPORT_STATUS_RN_MASK;
2932 if (err && reset_needed) {
2933 iowrite32(SLI_PORT_CONTROL_IP_MASK,
2934 adapter->db + SLIPORT_CONTROL_OFFSET);
2935
2936 /* check adapter has corrected the error */
2937 status = lancer_wait_ready(adapter);
2938 sliport_status = ioread32(adapter->db +
2939 SLIPORT_STATUS_OFFSET);
2940 sliport_status &= (SLIPORT_STATUS_ERR_MASK |
2941 SLIPORT_STATUS_RN_MASK);
2942 if (status || sliport_status)
2943 status = -1;
2944 } else if (err || reset_needed) {
2945 status = -1;
2946 }
2947 }
2948 return status;
2949}
2950
6b7c5b94
SP		 2951static int __devinit be_probe(struct pci_dev *pdev,
2952 const struct pci_device_id *pdev_id)
2953{
2954 int status = 0;
2955 struct be_adapter *adapter;
2956 struct net_device *netdev;
6b7c5b94
SP		 2957
2958 status = pci_enable_device(pdev);
2959 if (status)
2960 goto do_none;
2961
2962 status = pci_request_regions(pdev, DRV_NAME);
2963 if (status)
2964 goto disable_dev;
2965 pci_set_master(pdev);
2966
2967 netdev = alloc_etherdev(sizeof(struct be_adapter));
2968 if (netdev == NULL) {
2969 status = -ENOMEM;
2970 goto rel_reg;
2971 }
2972 adapter = netdev_priv(netdev);
2973 adapter->pdev = pdev;
2974 pci_set_drvdata(pdev, adapter);
fe6d2a38
SP		 2975
2976 status = be_dev_family_check(adapter);
63657b9c 2977 if (status)
fe6d2a38
SP		 2978 goto free_netdev;
2979
6b7c5b94 2980 adapter->netdev = netdev;
2243e2e9 2981 SET_NETDEV_DEV(netdev, &pdev->dev);
6b7c5b94 2982
2b7bcebf 2983 status = dma_set_mask(&pdev->dev, DMA_BIT_MASK(64));
6b7c5b94
SP		 2984 if (!status) {
2985 netdev->features |= NETIF_F_HIGHDMA;
2986 } else {
2b7bcebf 2987 status = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
6b7c5b94
SP		 2988 if (status) {
2989 dev_err(&pdev->dev, "Could not set PCI DMA Mask\n");
2990 goto free_netdev;
2991 }
2992 }
2993
ba343c77
SB		 2994 be_sriov_enable(adapter);
2995
6b7c5b94
SP		 2996 status = be_ctrl_init(adapter);
2997 if (status)
2998 goto free_netdev;
2999
37eed1cb
PR		 3000 if (lancer_chip(adapter)) {
3001 status = lancer_test_and_set_rdy_state(adapter);
3002 if (status) {
3003 dev_err(&pdev->dev, "Adapter in non recoverable error\n");
3004 goto free_netdev;
3005 }
3006 }
3007
2243e2e9 3008 /* sync up with fw's ready state */
ba343c77
SB		 3009 if (be_physfn(adapter)) {
3010 status = be_cmd_POST(adapter);
3011 if (status)
3012 goto ctrl_clean;
ba343c77 3013 }
6b7c5b94 3014
2243e2e9
SP		 3015 /* tell fw we're ready to fire cmds */
3016 status = be_cmd_fw_init(adapter);
6b7c5b94 3017 if (status)
2243e2e9
SP		 3018 goto ctrl_clean;
3019
a4b4dfab
AK		 3020 status = be_cmd_reset_function(adapter);
3021 if (status)
3022 goto ctrl_clean;
556ae191 3023
2243e2e9
SP		 3024 status = be_stats_init(adapter);
3025 if (status)
3026 goto ctrl_clean;
3027
3028 status = be_get_config(adapter);
6b7c5b94
SP		 3029 if (status)
3030 goto stats_clean;
6b7c5b94 3031
3abcdeda
SP		 3032 be_msix_enable(adapter);
3033
6b7c5b94 3034 INIT_DELAYED_WORK(&adapter->work, be_worker);
6b7c5b94 3035
5fb379ee
SP		 3036 status = be_setup(adapter);
3037 if (status)
3abcdeda 3038 goto msix_disable;
2243e2e9 3039
3abcdeda 3040 be_netdev_init(netdev);
6b7c5b94
SP		 3041 status = register_netdev(netdev);
3042 if (status != 0)
5fb379ee 3043 goto unsetup;
63a76944 3044 netif_carrier_off(netdev);
6b7c5b94 3045
e6319365
AK		 3046 if (be_physfn(adapter) && adapter->sriov_enabled) {
3047 status = be_vf_eth_addr_config(adapter);
3048 if (status)
3049 goto unreg_netdev;
3050 }
3051
c4ca2374 3052 dev_info(&pdev->dev, "%s port %d\n", nic_name(pdev), adapter->port_num);
f203af70 3053 schedule_delayed_work(&adapter->work, msecs_to_jiffies(100));
6b7c5b94
SP		 3054 return 0;
3055
e6319365
AK		 3056unreg_netdev:
3057 unregister_netdev(netdev);
5fb379ee
SP		 3058unsetup:
3059 be_clear(adapter);
3abcdeda
SP		 3060msix_disable:
3061 be_msix_disable(adapter);
6b7c5b94
SP		 3062stats_clean:
3063 be_stats_cleanup(adapter);
3064ctrl_clean:
3065 be_ctrl_cleanup(adapter);
3066free_netdev:
ba343c77 3067 be_sriov_disable(adapter);
fe6d2a38 3068 free_netdev(netdev);
8d56ff11 3069 pci_set_drvdata(pdev, NULL);
6b7c5b94
SP		 3070rel_reg:
3071 pci_release_regions(pdev);
3072disable_dev:
3073 pci_disable_device(pdev);
3074do_none:
c4ca2374 3075 dev_err(&pdev->dev, "%s initialization failed\n", nic_name(pdev));
6b7c5b94
SP		 3076 return status;
3077}
3078
3079static int be_suspend(struct pci_dev *pdev, pm_message_t state)
3080{
3081 struct be_adapter *adapter = pci_get_drvdata(pdev);
3082 struct net_device *netdev = adapter->netdev;
3083
a4ca055f 3084 cancel_delayed_work_sync(&adapter->work);
71d8d1b5
AK		 3085 if (adapter->wol)
3086 be_setup_wol(adapter, true);
3087
6b7c5b94
SP		 3088 netif_device_detach(netdev);
3089 if (netif_running(netdev)) {
3090 rtnl_lock();
3091 be_close(netdev);
3092 rtnl_unlock();
3093 }
9e90c961 3094 be_cmd_get_flow_control(adapter, &adapter->tx_fc, &adapter->rx_fc);
9b0365f1 3095 be_clear(adapter);
6b7c5b94 3096
a4ca055f 3097 be_msix_disable(adapter);
6b7c5b94
SP		 3098 pci_save_state(pdev);
3099 pci_disable_device(pdev);
3100 pci_set_power_state(pdev, pci_choose_state(pdev, state));
3101 return 0;
3102}
3103
3104static int be_resume(struct pci_dev *pdev)
3105{
3106 int status = 0;
3107 struct be_adapter *adapter = pci_get_drvdata(pdev);
3108 struct net_device *netdev = adapter->netdev;
3109
3110 netif_device_detach(netdev);
3111
3112 status = pci_enable_device(pdev);
3113 if (status)
3114 return status;
3115
3116 pci_set_power_state(pdev, 0);
3117 pci_restore_state(pdev);
3118
a4ca055f 3119 be_msix_enable(adapter);
2243e2e9
SP		 3120 /* tell fw we're ready to fire cmds */
3121 status = be_cmd_fw_init(adapter);
3122 if (status)
3123 return status;
3124
9b0365f1 3125 be_setup(adapter);
6b7c5b94
SP		 3126 if (netif_running(netdev)) {
3127 rtnl_lock();
3128 be_open(netdev);
3129 rtnl_unlock();
3130 }
3131 netif_device_attach(netdev);
71d8d1b5
AK		 3132
3133 if (adapter->wol)
3134 be_setup_wol(adapter, false);
a4ca055f
AK		 3135
3136 schedule_delayed_work(&adapter->work, msecs_to_jiffies(100));
6b7c5b94
SP		 3137 return 0;
3138}
3139
82456b03
SP		 3140/*
3141 * An FLR will stop BE from DMAing any data.
3142 */
3143static void be_shutdown(struct pci_dev *pdev)
3144{
3145 struct be_adapter *adapter = pci_get_drvdata(pdev);
3146 struct net_device *netdev = adapter->netdev;
3147
a4ca055f
AK		 3148 if (netif_running(netdev))
3149 cancel_delayed_work_sync(&adapter->work);
3150
82456b03
SP		 3151 netif_device_detach(netdev);
3152
3153 be_cmd_reset_function(adapter);
3154
3155 if (adapter->wol)
3156 be_setup_wol(adapter, true);
3157
3158 pci_disable_device(pdev);
82456b03
SP		 3159}
3160
cf588477
SP		 3161static pci_ers_result_t be_eeh_err_detected(struct pci_dev *pdev,
3162 pci_channel_state_t state)
3163{
3164 struct be_adapter *adapter = pci_get_drvdata(pdev);
3165 struct net_device *netdev = adapter->netdev;
3166
3167 dev_err(&adapter->pdev->dev, "EEH error detected\n");
3168
3169 adapter->eeh_err = true;
3170
3171 netif_device_detach(netdev);
3172
3173 if (netif_running(netdev)) {
3174 rtnl_lock();
3175 be_close(netdev);
3176 rtnl_unlock();
3177 }
3178 be_clear(adapter);
3179
3180 if (state == pci_channel_io_perm_failure)
3181 return PCI_ERS_RESULT_DISCONNECT;
3182
3183 pci_disable_device(pdev);
3184
3185 return PCI_ERS_RESULT_NEED_RESET;
3186}
3187
3188static pci_ers_result_t be_eeh_reset(struct pci_dev *pdev)
3189{
3190 struct be_adapter *adapter = pci_get_drvdata(pdev);
3191 int status;
3192
3193 dev_info(&adapter->pdev->dev, "EEH reset\n");
3194 adapter->eeh_err = false;
3195
3196 status = pci_enable_device(pdev);
3197 if (status)
3198 return PCI_ERS_RESULT_DISCONNECT;
3199
3200 pci_set_master(pdev);
3201 pci_set_power_state(pdev, 0);
3202 pci_restore_state(pdev);
3203
3204 /* Check if card is ok and fw is ready */
3205 status = be_cmd_POST(adapter);
3206 if (status)
3207 return PCI_ERS_RESULT_DISCONNECT;
3208
3209 return PCI_ERS_RESULT_RECOVERED;
3210}
3211
3212static void be_eeh_resume(struct pci_dev *pdev)
3213{
3214 int status = 0;
3215 struct be_adapter *adapter = pci_get_drvdata(pdev);
3216 struct net_device *netdev = adapter->netdev;
3217
3218 dev_info(&adapter->pdev->dev, "EEH resume\n");
3219
3220 pci_save_state(pdev);
3221
3222 /* tell fw we're ready to fire cmds */
3223 status = be_cmd_fw_init(adapter);
3224 if (status)
3225 goto err;
3226
3227 status = be_setup(adapter);
3228 if (status)
3229 goto err;
3230
3231 if (netif_running(netdev)) {
3232 status = be_open(netdev);
3233 if (status)
3234 goto err;
3235 }
3236 netif_device_attach(netdev);
3237 return;
3238err:
3239 dev_err(&adapter->pdev->dev, "EEH resume failed\n");
cf588477
SP		 3240}
3241
3242static struct pci_error_handlers be_eeh_handlers = {
3243 .error_detected = be_eeh_err_detected,
3244 .slot_reset = be_eeh_reset,
3245 .resume = be_eeh_resume,
3246};
3247
6b7c5b94
SP		 3248static struct pci_driver be_driver = {
3249 .name = DRV_NAME,
3250 .id_table = be_dev_ids,
3251 .probe = be_probe,
3252 .remove = be_remove,
3253 .suspend = be_suspend,
cf588477 3254 .resume = be_resume,
82456b03 3255 .shutdown = be_shutdown,
cf588477 3256 .err_handler = &be_eeh_handlers
6b7c5b94
SP		 3257};
3258
3259static int __init be_init_module(void)
3260{
8e95a202
JP		 3261 if (rx_frag_size != 8192 && rx_frag_size != 4096 &&
3262 rx_frag_size != 2048) {
6b7c5b94
SP		 3263 printk(KERN_WARNING DRV_NAME
3264 " : Module param rx_frag_size must be 2048/4096/8192."
3265 " Using 2048\n");
3266 rx_frag_size = 2048;
3267 }
6b7c5b94 3268
ba343c77
SB		 3269 if (num_vfs > 32) {
3270 printk(KERN_WARNING DRV_NAME
3271 " : Module param num_vfs must not be greater than 32."
3272 "Using 32\n");
3273 num_vfs = 32;
3274 }
3275
6b7c5b94
SP		 3276 return pci_register_driver(&be_driver);
3277}
3278module_init(be_init_module);
3279
3280static void __exit be_exit_module(void)
3281{
3282 pci_unregister_driver(&be_driver);
3283}
3284module_exit(be_exit_module);
Linux kernel - Deliverables
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