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be2net: call be_vf_eth_addr_config() after register_netdev
[deliverable/linux.git] / drivers / net / benet / be_main.c
CommitLineData
6b7c5b94 1/*
294aedcf 2 * Copyright (C) 2005 - 2010 ServerEngines
6b7c5b94
SP		 3 * All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License version 2
7 * as published by the Free Software Foundation. The full GNU General
8 * Public License is included in this distribution in the file called COPYING.
9 *
10 * Contact Information:
11 * linux-drivers@serverengines.com
12 *
13 * ServerEngines
14 * 209 N. Fair Oaks Ave
15 * Sunnyvale, CA 94085
16 */
17
18#include "be.h"
8788fdc2 19#include "be_cmds.h"
65f71b8b 20#include <asm/div64.h>
6b7c5b94
SP		 21
22MODULE_VERSION(DRV_VER);
23MODULE_DEVICE_TABLE(pci, be_dev_ids);
24MODULE_DESCRIPTION(DRV_DESC " " DRV_VER);
25MODULE_AUTHOR("ServerEngines Corporation");
26MODULE_LICENSE("GPL");
27
28static unsigned int rx_frag_size = 2048;
ba343c77 29static unsigned int num_vfs;
6b7c5b94 30module_param(rx_frag_size, uint, S_IRUGO);
ba343c77 31module_param(num_vfs, uint, S_IRUGO);
6b7c5b94 32MODULE_PARM_DESC(rx_frag_size, "Size of a fragment that holds rcvd data.");
ba343c77 33MODULE_PARM_DESC(num_vfs, "Number of PCI VFs to initialize");
6b7c5b94 34
3abcdeda
SP		 35static bool multi_rxq = true;
36module_param(multi_rxq, bool, S_IRUGO | S_IWUSR);
37MODULE_PARM_DESC(multi_rxq, "Multi Rx Queue support. Enabled by default");
38
6b7c5b94 39static DEFINE_PCI_DEVICE_TABLE(be_dev_ids) = {
c4ca2374 40 { PCI_DEVICE(BE_VENDOR_ID, BE_DEVICE_ID1) },
59fd5d87 41 { PCI_DEVICE(BE_VENDOR_ID, BE_DEVICE_ID2) },
c4ca2374
AK		 42 { PCI_DEVICE(BE_VENDOR_ID, OC_DEVICE_ID1) },
43 { PCI_DEVICE(BE_VENDOR_ID, OC_DEVICE_ID2) },
fe6d2a38 44 { PCI_DEVICE(EMULEX_VENDOR_ID, OC_DEVICE_ID3)},
6b7c5b94
SP		 45 { 0 }
46};
47MODULE_DEVICE_TABLE(pci, be_dev_ids);
7c185276
AK		 48/* UE Status Low CSR */
49static char *ue_status_low_desc[] = {
50 "CEV",
51 "CTX",
52 "DBUF",
53 "ERX",
54 "Host",
55 "MPU",
56 "NDMA",
57 "PTC ",
58 "RDMA ",
59 "RXF ",
60 "RXIPS ",
61 "RXULP0 ",
62 "RXULP1 ",
63 "RXULP2 ",
64 "TIM ",
65 "TPOST ",
66 "TPRE ",
67 "TXIPS ",
68 "TXULP0 ",
69 "TXULP1 ",
70 "UC ",
71 "WDMA ",
72 "TXULP2 ",
73 "HOST1 ",
74 "P0_OB_LINK ",
75 "P1_OB_LINK ",
76 "HOST_GPIO ",
77 "MBOX ",
78 "AXGMAC0",
79 "AXGMAC1",
80 "JTAG",
81 "MPU_INTPEND"
82};
83/* UE Status High CSR */
84static char *ue_status_hi_desc[] = {
85 "LPCMEMHOST",
86 "MGMT_MAC",
87 "PCS0ONLINE",
88 "MPU_IRAM",
89 "PCS1ONLINE",
90 "PCTL0",
91 "PCTL1",
92 "PMEM",
93 "RR",
94 "TXPB",
95 "RXPP",
96 "XAUI",
97 "TXP",
98 "ARM",
99 "IPC",
100 "HOST2",
101 "HOST3",
102 "HOST4",
103 "HOST5",
104 "HOST6",
105 "HOST7",
106 "HOST8",
107 "HOST9",
108 "NETC"
109 "Unknown",
110 "Unknown",
111 "Unknown",
112 "Unknown",
113 "Unknown",
114 "Unknown",
115 "Unknown",
116 "Unknown"
117};
6b7c5b94 118
3abcdeda
SP		 119static inline bool be_multi_rxq(struct be_adapter *adapter)
120{
121 return (adapter->num_rx_qs > 1);
122}
123
6b7c5b94
SP		 124static void be_queue_free(struct be_adapter *adapter, struct be_queue_info *q)
125{
126 struct be_dma_mem *mem = &q->dma_mem;
127 if (mem->va)
2b7bcebf
IV		 128 dma_free_coherent(&adapter->pdev->dev, mem->size, mem->va,
129 mem->dma);
6b7c5b94
SP		 130}
131
132static int be_queue_alloc(struct be_adapter *adapter, struct be_queue_info *q,
133 u16 len, u16 entry_size)
134{
135 struct be_dma_mem *mem = &q->dma_mem;
136
137 memset(q, 0, sizeof(*q));
138 q->len = len;
139 q->entry_size = entry_size;
140 mem->size = len * entry_size;
2b7bcebf
IV		 141 mem->va = dma_alloc_coherent(&adapter->pdev->dev, mem->size, &mem->dma,
142 GFP_KERNEL);
6b7c5b94
SP		 143 if (!mem->va)
144 return -1;
145 memset(mem->va, 0, mem->size);
146 return 0;
147}
148
8788fdc2 149static void be_intr_set(struct be_adapter *adapter, bool enable)
6b7c5b94 150{
8788fdc2 151 u8 __iomem *addr = adapter->pcicfg + PCICFG_MEMBAR_CTRL_INT_CTRL_OFFSET;
6b7c5b94
SP		 152 u32 reg = ioread32(addr);
153 u32 enabled = reg & MEMBAR_CTRL_INT_CTRL_HOSTINTR_MASK;
5f0b849e 154
cf588477
SP		 155 if (adapter->eeh_err)
156 return;
157
5f0b849e 158 if (!enabled && enable)
6b7c5b94 159 reg |= MEMBAR_CTRL_INT_CTRL_HOSTINTR_MASK;
5f0b849e 160 else if (enabled && !enable)
6b7c5b94 161 reg &= ~MEMBAR_CTRL_INT_CTRL_HOSTINTR_MASK;
5f0b849e 162 else
6b7c5b94 163 return;
5f0b849e 164
6b7c5b94
SP		 165 iowrite32(reg, addr);
166}
167
8788fdc2 168static void be_rxq_notify(struct be_adapter *adapter, u16 qid, u16 posted)
6b7c5b94
SP		 169{
170 u32 val = 0;
171 val |= qid & DB_RQ_RING_ID_MASK;
172 val |= posted << DB_RQ_NUM_POSTED_SHIFT;
f3eb62d2
SP		 173
174 wmb();
8788fdc2 175 iowrite32(val, adapter->db + DB_RQ_OFFSET);
6b7c5b94
SP		 176}
177
8788fdc2 178static void be_txq_notify(struct be_adapter *adapter, u16 qid, u16 posted)
6b7c5b94
SP		 179{
180 u32 val = 0;
181 val |= qid & DB_TXULP_RING_ID_MASK;
182 val |= (posted & DB_TXULP_NUM_POSTED_MASK) << DB_TXULP_NUM_POSTED_SHIFT;
f3eb62d2
SP		 183
184 wmb();
8788fdc2 185 iowrite32(val, adapter->db + DB_TXULP1_OFFSET);
6b7c5b94
SP		 186}
187
8788fdc2 188static void be_eq_notify(struct be_adapter *adapter, u16 qid,
6b7c5b94
SP		 189 bool arm, bool clear_int, u16 num_popped)
190{
191 u32 val = 0;
192 val |= qid & DB_EQ_RING_ID_MASK;
fe6d2a38
SP		 193 val |= ((qid & DB_EQ_RING_ID_EXT_MASK) <<
194 DB_EQ_RING_ID_EXT_MASK_SHIFT);
cf588477
SP		 195
196 if (adapter->eeh_err)
197 return;
198
6b7c5b94
SP		 199 if (arm)
200 val |= 1 << DB_EQ_REARM_SHIFT;
201 if (clear_int)
202 val |= 1 << DB_EQ_CLR_SHIFT;
203 val |= 1 << DB_EQ_EVNT_SHIFT;
204 val |= num_popped << DB_EQ_NUM_POPPED_SHIFT;
8788fdc2 205 iowrite32(val, adapter->db + DB_EQ_OFFSET);
6b7c5b94
SP		 206}
207
8788fdc2 208void be_cq_notify(struct be_adapter *adapter, u16 qid, bool arm, u16 num_popped)
6b7c5b94
SP		 209{
210 u32 val = 0;
211 val |= qid & DB_CQ_RING_ID_MASK;
fe6d2a38
SP		 212 val |= ((qid & DB_CQ_RING_ID_EXT_MASK) <<
213 DB_CQ_RING_ID_EXT_MASK_SHIFT);
cf588477
SP		 214
215 if (adapter->eeh_err)
216 return;
217
6b7c5b94
SP		 218 if (arm)
219 val |= 1 << DB_CQ_REARM_SHIFT;
220 val |= num_popped << DB_CQ_NUM_POPPED_SHIFT;
8788fdc2 221 iowrite32(val, adapter->db + DB_CQ_OFFSET);
6b7c5b94
SP		 222}
223
6b7c5b94
SP		 224static int be_mac_addr_set(struct net_device *netdev, void *p)
225{
226 struct be_adapter *adapter = netdev_priv(netdev);
227 struct sockaddr *addr = p;
228 int status = 0;
229
ca9e4988
AK		 230 if (!is_valid_ether_addr(addr->sa_data))
231 return -EADDRNOTAVAIL;
232
ba343c77
SB		 233 /* MAC addr configuration will be done in hardware for VFs
234 * by their corresponding PFs. Just copy to netdev addr here
235 */
236 if (!be_physfn(adapter))
237 goto netdev_addr;
238
a65027e4
SP		 239 status = be_cmd_pmac_del(adapter, adapter->if_handle, adapter->pmac_id);
240 if (status)
241 return status;
6b7c5b94 242
a65027e4
SP		 243 status = be_cmd_pmac_add(adapter, (u8 *)addr->sa_data,
244 adapter->if_handle, &adapter->pmac_id);
ba343c77 245netdev_addr:
6b7c5b94
SP		 246 if (!status)
247 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
248
249 return status;
250}
251
b31c50a7 252void netdev_stats_update(struct be_adapter *adapter)
6b7c5b94 253{
3abcdeda 254 struct be_hw_stats *hw_stats = hw_stats_from_cmd(adapter->stats_cmd.va);
6b7c5b94
SP		 255 struct be_rxf_stats *rxf_stats = &hw_stats->rxf;
256 struct be_port_rxf_stats *port_stats =
257 &rxf_stats->port[adapter->port_num];
78122a52 258 struct net_device_stats *dev_stats = &adapter->netdev->stats;
68110868 259 struct be_erx_stats *erx_stats = &hw_stats->erx;
3abcdeda
SP		 260 struct be_rx_obj *rxo;
261 int i;
6b7c5b94 262
3abcdeda
SP		 263 memset(dev_stats, 0, sizeof(*dev_stats));
264 for_all_rx_queues(adapter, rxo, i) {
265 dev_stats->rx_packets += rx_stats(rxo)->rx_pkts;
266 dev_stats->rx_bytes += rx_stats(rxo)->rx_bytes;
267 dev_stats->multicast += rx_stats(rxo)->rx_mcast_pkts;
268 /* no space in linux buffers: best possible approximation */
269 dev_stats->rx_dropped +=
270 erx_stats->rx_drops_no_fragments[rxo->q.id];
271 }
272
273 dev_stats->tx_packets = tx_stats(adapter)->be_tx_pkts;
274 dev_stats->tx_bytes = tx_stats(adapter)->be_tx_bytes;
6b7c5b94
SP		 275
276 /* bad pkts received */
277 dev_stats->rx_errors = port_stats->rx_crc_errors +
278 port_stats->rx_alignment_symbol_errors +
279 port_stats->rx_in_range_errors +
68110868
SP		 280 port_stats->rx_out_range_errors +
281 port_stats->rx_frame_too_long +
282 port_stats->rx_dropped_too_small +
283 port_stats->rx_dropped_too_short +
284 port_stats->rx_dropped_header_too_small +
285 port_stats->rx_dropped_tcp_length +
286 port_stats->rx_dropped_runt +
287 port_stats->rx_tcp_checksum_errs +
288 port_stats->rx_ip_checksum_errs +
289 port_stats->rx_udp_checksum_errs;
290
6b7c5b94
SP		 291 /* detailed rx errors */
292 dev_stats->rx_length_errors = port_stats->rx_in_range_errors +
68110868
SP		 293 port_stats->rx_out_range_errors +
294 port_stats->rx_frame_too_long;
295
6b7c5b94
SP		 296 dev_stats->rx_crc_errors = port_stats->rx_crc_errors;
297
298 /* frame alignment errors */
299 dev_stats->rx_frame_errors = port_stats->rx_alignment_symbol_errors;
68110868 300
6b7c5b94
SP		 301 /* receiver fifo overrun */
302 /* drops_no_pbuf is no per i/f, it's per BE card */
303 dev_stats->rx_fifo_errors = port_stats->rx_fifo_overflow +
304 port_stats->rx_input_fifo_overflow +
305 rxf_stats->rx_drops_no_pbuf;
6b7c5b94
SP		 306}
307
8788fdc2 308void be_link_status_update(struct be_adapter *adapter, bool link_up)
6b7c5b94 309{
6b7c5b94
SP		 310 struct net_device *netdev = adapter->netdev;
311
6b7c5b94 312 /* If link came up or went down */
a8f447bd 313 if (adapter->link_up != link_up) {
0dffc83e 314 adapter->link_speed = -1;
a8f447bd 315 if (link_up) {
6b7c5b94
SP		 316 netif_carrier_on(netdev);
317 printk(KERN_INFO "%s: Link up\n", netdev->name);
a8f447bd 318 } else {
a8f447bd
SP		 319 netif_carrier_off(netdev);
320 printk(KERN_INFO "%s: Link down\n", netdev->name);
6b7c5b94 321 }
a8f447bd 322 adapter->link_up = link_up;
6b7c5b94 323 }
6b7c5b94
SP		 324}
325
326/* Update the EQ delay n BE based on the RX frags consumed / sec */
3abcdeda 327static void be_rx_eqd_update(struct be_adapter *adapter, struct be_rx_obj *rxo)
6b7c5b94 328{
3abcdeda
SP		 329 struct be_eq_obj *rx_eq = &rxo->rx_eq;
330 struct be_rx_stats *stats = &rxo->stats;
4097f663
SP		 331 ulong now = jiffies;
332 u32 eqd;
333
334 if (!rx_eq->enable_aic)
335 return;
336
337 /* Wrapped around */
338 if (time_before(now, stats->rx_fps_jiffies)) {
339 stats->rx_fps_jiffies = now;
340 return;
341 }
6b7c5b94
SP		 342
343 /* Update once a second */
4097f663 344 if ((now - stats->rx_fps_jiffies) < HZ)
6b7c5b94
SP		 345 return;
346
3abcdeda 347 stats->rx_fps = (stats->rx_frags - stats->prev_rx_frags) /
4097f663 348 ((now - stats->rx_fps_jiffies) / HZ);
6b7c5b94 349
4097f663 350 stats->rx_fps_jiffies = now;
3abcdeda
SP		 351 stats->prev_rx_frags = stats->rx_frags;
352 eqd = stats->rx_fps / 110000;
6b7c5b94
SP		 353 eqd = eqd << 3;
354 if (eqd > rx_eq->max_eqd)
355 eqd = rx_eq->max_eqd;
356 if (eqd < rx_eq->min_eqd)
357 eqd = rx_eq->min_eqd;
358 if (eqd < 10)
359 eqd = 0;
360 if (eqd != rx_eq->cur_eqd)
8788fdc2 361 be_cmd_modify_eqd(adapter, rx_eq->q.id, eqd);
6b7c5b94
SP		 362
363 rx_eq->cur_eqd = eqd;
364}
365
65f71b8b
SH		 366static u32 be_calc_rate(u64 bytes, unsigned long ticks)
367{
368 u64 rate = bytes;
369
370 do_div(rate, ticks / HZ);
371 rate <<= 3; /* bytes/sec -> bits/sec */
372 do_div(rate, 1000000ul); /* MB/Sec */
373
374 return rate;
375}
376
4097f663
SP		 377static void be_tx_rate_update(struct be_adapter *adapter)
378{
3abcdeda 379 struct be_tx_stats *stats = tx_stats(adapter);
4097f663
SP		 380 ulong now = jiffies;
381
382 /* Wrapped around? */
383 if (time_before(now, stats->be_tx_jiffies)) {
384 stats->be_tx_jiffies = now;
385 return;
386 }
387
388 /* Update tx rate once in two seconds */
389 if ((now - stats->be_tx_jiffies) > 2 * HZ) {
65f71b8b
SH		 390 stats->be_tx_rate = be_calc_rate(stats->be_tx_bytes
391 - stats->be_tx_bytes_prev,
392 now - stats->be_tx_jiffies);
4097f663
SP		 393 stats->be_tx_jiffies = now;
394 stats->be_tx_bytes_prev = stats->be_tx_bytes;
395 }
396}
397
6b7c5b94 398static void be_tx_stats_update(struct be_adapter *adapter,
91992e44 399 u32 wrb_cnt, u32 copied, u32 gso_segs, bool stopped)
6b7c5b94 400{
3abcdeda 401 struct be_tx_stats *stats = tx_stats(adapter);
6b7c5b94
SP		 402 stats->be_tx_reqs++;
403 stats->be_tx_wrbs += wrb_cnt;
404 stats->be_tx_bytes += copied;
91992e44 405 stats->be_tx_pkts += (gso_segs ? gso_segs : 1);
6b7c5b94
SP		 406 if (stopped)
407 stats->be_tx_stops++;
6b7c5b94
SP		 408}
409
410/* Determine number of WRB entries needed to xmit data in an skb */
fe6d2a38
SP		 411static u32 wrb_cnt_for_skb(struct be_adapter *adapter, struct sk_buff *skb,
412 bool *dummy)
6b7c5b94 413{
ebc8d2ab
DM		 414 int cnt = (skb->len > skb->data_len);
415
416 cnt += skb_shinfo(skb)->nr_frags;
417
6b7c5b94
SP		 418 /* to account for hdr wrb */
419 cnt++;
fe6d2a38
SP		 420 if (lancer_chip(adapter) || !(cnt & 1)) {
421 *dummy = false;
422 } else {
6b7c5b94
SP		 423 /* add a dummy to make it an even num */
424 cnt++;
425 *dummy = true;
fe6d2a38 426 }
6b7c5b94
SP		 427 BUG_ON(cnt > BE_MAX_TX_FRAG_COUNT);
428 return cnt;
429}
430
431static inline void wrb_fill(struct be_eth_wrb *wrb, u64 addr, int len)
432{
433 wrb->frag_pa_hi = upper_32_bits(addr);
434 wrb->frag_pa_lo = addr & 0xFFFFFFFF;
435 wrb->frag_len = len & ETH_WRB_FRAG_LEN_MASK;
436}
437
cc4ce020
SK		 438static void wrb_fill_hdr(struct be_adapter *adapter, struct be_eth_hdr_wrb *hdr,
439 struct sk_buff *skb, u32 wrb_cnt, u32 len)
6b7c5b94 440{
cc4ce020
SK		 441 u8 vlan_prio = 0;
442 u16 vlan_tag = 0;
443
6b7c5b94
SP		 444 memset(hdr, 0, sizeof(*hdr));
445
446 AMAP_SET_BITS(struct amap_eth_hdr_wrb, crc, hdr, 1);
447
49e4b847 448 if (skb_is_gso(skb)) {
6b7c5b94
SP		 449 AMAP_SET_BITS(struct amap_eth_hdr_wrb, lso, hdr, 1);
450 AMAP_SET_BITS(struct amap_eth_hdr_wrb, lso_mss,
451 hdr, skb_shinfo(skb)->gso_size);
fe6d2a38 452 if (skb_is_gso_v6(skb) && !lancer_chip(adapter))
49e4b847 453 AMAP_SET_BITS(struct amap_eth_hdr_wrb, lso6, hdr, 1);
fe6d2a38
SP		 454 if (lancer_chip(adapter) && adapter->sli_family ==
455 LANCER_A0_SLI_FAMILY) {
456 AMAP_SET_BITS(struct amap_eth_hdr_wrb, ipcs, hdr, 1);
457 if (is_tcp_pkt(skb))
458 AMAP_SET_BITS(struct amap_eth_hdr_wrb,
459 tcpcs, hdr, 1);
460 else if (is_udp_pkt(skb))
461 AMAP_SET_BITS(struct amap_eth_hdr_wrb,
462 udpcs, hdr, 1);
463 }
6b7c5b94
SP		 464 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
465 if (is_tcp_pkt(skb))
466 AMAP_SET_BITS(struct amap_eth_hdr_wrb, tcpcs, hdr, 1);
467 else if (is_udp_pkt(skb))
468 AMAP_SET_BITS(struct amap_eth_hdr_wrb, udpcs, hdr, 1);
469 }
470
cc4ce020 471 if (adapter->vlan_grp && vlan_tx_tag_present(skb)) {
6b7c5b94 472 AMAP_SET_BITS(struct amap_eth_hdr_wrb, vlan, hdr, 1);
cc4ce020
SK		 473 vlan_tag = vlan_tx_tag_get(skb);
474 vlan_prio = (vlan_tag & VLAN_PRIO_MASK) >> VLAN_PRIO_SHIFT;
475 /* If vlan priority provided by OS is NOT in available bmap */
476 if (!(adapter->vlan_prio_bmap & (1 << vlan_prio)))
477 vlan_tag = (vlan_tag & ~VLAN_PRIO_MASK) |
478 adapter->recommended_prio;
479 AMAP_SET_BITS(struct amap_eth_hdr_wrb, vlan_tag, hdr, vlan_tag);
6b7c5b94
SP		 480 }
481
482 AMAP_SET_BITS(struct amap_eth_hdr_wrb, event, hdr, 1);
483 AMAP_SET_BITS(struct amap_eth_hdr_wrb, complete, hdr, 1);
484 AMAP_SET_BITS(struct amap_eth_hdr_wrb, num_wrb, hdr, wrb_cnt);
485 AMAP_SET_BITS(struct amap_eth_hdr_wrb, len, hdr, len);
486}
487
2b7bcebf 488static void unmap_tx_frag(struct device *dev, struct be_eth_wrb *wrb,
7101e111
SP		 489 bool unmap_single)
490{
491 dma_addr_t dma;
492
493 be_dws_le_to_cpu(wrb, sizeof(*wrb));
494
495 dma = (u64)wrb->frag_pa_hi << 32 | (u64)wrb->frag_pa_lo;
b681ee77 496 if (wrb->frag_len) {
7101e111 497 if (unmap_single)
2b7bcebf
IV		 498 dma_unmap_single(dev, dma, wrb->frag_len,
499 DMA_TO_DEVICE);
7101e111 500 else
2b7bcebf 501 dma_unmap_page(dev, dma, wrb->frag_len, DMA_TO_DEVICE);
7101e111
SP		 502 }
503}
6b7c5b94
SP		 504
505static int make_tx_wrbs(struct be_adapter *adapter,
506 struct sk_buff *skb, u32 wrb_cnt, bool dummy_wrb)
507{
7101e111
SP		 508 dma_addr_t busaddr;
509 int i, copied = 0;
2b7bcebf 510 struct device *dev = &adapter->pdev->dev;
6b7c5b94
SP		 511 struct sk_buff *first_skb = skb;
512 struct be_queue_info *txq = &adapter->tx_obj.q;
513 struct be_eth_wrb *wrb;
514 struct be_eth_hdr_wrb *hdr;
7101e111
SP		 515 bool map_single = false;
516 u16 map_head;
6b7c5b94 517
6b7c5b94
SP		 518 hdr = queue_head_node(txq);
519 queue_head_inc(txq);
7101e111 520 map_head = txq->head;
6b7c5b94 521
ebc8d2ab 522 if (skb->len > skb->data_len) {
e743d313 523 int len = skb_headlen(skb);
2b7bcebf
IV		 524 busaddr = dma_map_single(dev, skb->data, len, DMA_TO_DEVICE);
525 if (dma_mapping_error(dev, busaddr))
7101e111
SP		 526 goto dma_err;
527 map_single = true;
ebc8d2ab
DM		 528 wrb = queue_head_node(txq);
529 wrb_fill(wrb, busaddr, len);
530 be_dws_cpu_to_le(wrb, sizeof(*wrb));
531 queue_head_inc(txq);
532 copied += len;
533 }
6b7c5b94 534
ebc8d2ab
DM		 535 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
536 struct skb_frag_struct *frag =
537 &skb_shinfo(skb)->frags[i];
2b7bcebf
IV		 538 busaddr = dma_map_page(dev, frag->page, frag->page_offset,
539 frag->size, DMA_TO_DEVICE);
540 if (dma_mapping_error(dev, busaddr))
7101e111 541 goto dma_err;
ebc8d2ab
DM		 542 wrb = queue_head_node(txq);
543 wrb_fill(wrb, busaddr, frag->size);
544 be_dws_cpu_to_le(wrb, sizeof(*wrb));
545 queue_head_inc(txq);
546 copied += frag->size;
6b7c5b94
SP		 547 }
548
549 if (dummy_wrb) {
550 wrb = queue_head_node(txq);
551 wrb_fill(wrb, 0, 0);
552 be_dws_cpu_to_le(wrb, sizeof(*wrb));
553 queue_head_inc(txq);
554 }
555
cc4ce020 556 wrb_fill_hdr(adapter, hdr, first_skb, wrb_cnt, copied);
6b7c5b94
SP		 557 be_dws_cpu_to_le(hdr, sizeof(*hdr));
558
559 return copied;
7101e111
SP		 560dma_err:
561 txq->head = map_head;
562 while (copied) {
563 wrb = queue_head_node(txq);
2b7bcebf 564 unmap_tx_frag(dev, wrb, map_single);
7101e111
SP		 565 map_single = false;
566 copied -= wrb->frag_len;
567 queue_head_inc(txq);
568 }
569 return 0;
6b7c5b94
SP		 570}
571
61357325 572static netdev_tx_t be_xmit(struct sk_buff *skb,
b31c50a7 573 struct net_device *netdev)
6b7c5b94
SP		 574{
575 struct be_adapter *adapter = netdev_priv(netdev);
576 struct be_tx_obj *tx_obj = &adapter->tx_obj;
577 struct be_queue_info *txq = &tx_obj->q;
578 u32 wrb_cnt = 0, copied = 0;
579 u32 start = txq->head;
580 bool dummy_wrb, stopped = false;
581
fe6d2a38 582 wrb_cnt = wrb_cnt_for_skb(adapter, skb, &dummy_wrb);
6b7c5b94
SP		 583
584 copied = make_tx_wrbs(adapter, skb, wrb_cnt, dummy_wrb);
c190e3c8
AK		 585 if (copied) {
586 /* record the sent skb in the sent_skb table */
587 BUG_ON(tx_obj->sent_skb_list[start]);
588 tx_obj->sent_skb_list[start] = skb;
589
590 /* Ensure txq has space for the next skb; Else stop the queue
591 * *BEFORE* ringing the tx doorbell, so that we serialze the
592 * tx compls of the current transmit which'll wake up the queue
593 */
7101e111 594 atomic_add(wrb_cnt, &txq->used);
c190e3c8
AK		 595 if ((BE_MAX_TX_FRAG_COUNT + atomic_read(&txq->used)) >=
596 txq->len) {
597 netif_stop_queue(netdev);
598 stopped = true;
599 }
6b7c5b94 600
c190e3c8 601 be_txq_notify(adapter, txq->id, wrb_cnt);
6b7c5b94 602
91992e44
AK		 603 be_tx_stats_update(adapter, wrb_cnt, copied,
604 skb_shinfo(skb)->gso_segs, stopped);
c190e3c8
AK		 605 } else {
606 txq->head = start;
607 dev_kfree_skb_any(skb);
6b7c5b94 608 }
6b7c5b94
SP		 609 return NETDEV_TX_OK;
610}
611
612static int be_change_mtu(struct net_device *netdev, int new_mtu)
613{
614 struct be_adapter *adapter = netdev_priv(netdev);
615 if (new_mtu < BE_MIN_MTU ||
34a89b8c
AK		 616 new_mtu > (BE_MAX_JUMBO_FRAME_SIZE -
617 (ETH_HLEN + ETH_FCS_LEN))) {
6b7c5b94
SP		 618 dev_info(&adapter->pdev->dev,
619 "MTU must be between %d and %d bytes\n",
34a89b8c
AK		 620 BE_MIN_MTU,
621 (BE_MAX_JUMBO_FRAME_SIZE - (ETH_HLEN + ETH_FCS_LEN)));
6b7c5b94
SP		 622 return -EINVAL;
623 }
624 dev_info(&adapter->pdev->dev, "MTU changed from %d to %d bytes\n",
625 netdev->mtu, new_mtu);
626 netdev->mtu = new_mtu;
627 return 0;
628}
629
630/*
82903e4b
AK		 631 * A max of 64 (BE_NUM_VLANS_SUPPORTED) vlans can be configured in BE.
632 * If the user configures more, place BE in vlan promiscuous mode.
6b7c5b94 633 */
1da87b7f 634static int be_vid_config(struct be_adapter *adapter, bool vf, u32 vf_num)
6b7c5b94 635{
6b7c5b94
SP		 636 u16 vtag[BE_NUM_VLANS_SUPPORTED];
637 u16 ntags = 0, i;
82903e4b 638 int status = 0;
1da87b7f
AK		 639 u32 if_handle;
640
641 if (vf) {
642 if_handle = adapter->vf_cfg[vf_num].vf_if_handle;
643 vtag[0] = cpu_to_le16(adapter->vf_cfg[vf_num].vf_vlan_tag);
644 status = be_cmd_vlan_config(adapter, if_handle, vtag, 1, 1, 0);
645 }
6b7c5b94 646
82903e4b 647 if (adapter->vlans_added <= adapter->max_vlans) {
6b7c5b94 648 /* Construct VLAN Table to give to HW */
b738127d 649 for (i = 0; i < VLAN_N_VID; i++) {
6b7c5b94
SP		 650 if (adapter->vlan_tag[i]) {
651 vtag[ntags] = cpu_to_le16(i);
652 ntags++;
653 }
654 }
b31c50a7
SP		 655 status = be_cmd_vlan_config(adapter, adapter->if_handle,
656 vtag, ntags, 1, 0);
6b7c5b94 657 } else {
b31c50a7
SP		 658 status = be_cmd_vlan_config(adapter, adapter->if_handle,
659 NULL, 0, 1, 1);
6b7c5b94 660 }
1da87b7f 661
b31c50a7 662 return status;
6b7c5b94
SP		 663}
664
665static void be_vlan_register(struct net_device *netdev, struct vlan_group *grp)
666{
667 struct be_adapter *adapter = netdev_priv(netdev);
6b7c5b94 668
6b7c5b94 669 adapter->vlan_grp = grp;
6b7c5b94
SP		 670}
671
672static void be_vlan_add_vid(struct net_device *netdev, u16 vid)
673{
674 struct be_adapter *adapter = netdev_priv(netdev);
675
1da87b7f 676 adapter->vlans_added++;
ba343c77
SB		 677 if (!be_physfn(adapter))
678 return;
679
6b7c5b94 680 adapter->vlan_tag[vid] = 1;
82903e4b 681 if (adapter->vlans_added <= (adapter->max_vlans + 1))
1da87b7f 682 be_vid_config(adapter, false, 0);
6b7c5b94
SP		 683}
684
685static void be_vlan_rem_vid(struct net_device *netdev, u16 vid)
686{
687 struct be_adapter *adapter = netdev_priv(netdev);
688
1da87b7f
AK		 689 adapter->vlans_added--;
690 vlan_group_set_device(adapter->vlan_grp, vid, NULL);
691
ba343c77
SB		 692 if (!be_physfn(adapter))
693 return;
694
6b7c5b94 695 adapter->vlan_tag[vid] = 0;
82903e4b 696 if (adapter->vlans_added <= adapter->max_vlans)
1da87b7f 697 be_vid_config(adapter, false, 0);
6b7c5b94
SP		 698}
699
24307eef 700static void be_set_multicast_list(struct net_device *netdev)
6b7c5b94
SP		 701{
702 struct be_adapter *adapter = netdev_priv(netdev);
6b7c5b94 703
24307eef 704 if (netdev->flags & IFF_PROMISC) {
8788fdc2 705 be_cmd_promiscuous_config(adapter, adapter->port_num, 1);
24307eef
SP		 706 adapter->promiscuous = true;
707 goto done;
6b7c5b94
SP		 708 }
709
24307eef
SP		 710 /* BE was previously in promiscous mode; disable it */
711 if (adapter->promiscuous) {
712 adapter->promiscuous = false;
8788fdc2 713 be_cmd_promiscuous_config(adapter, adapter->port_num, 0);
6b7c5b94
SP		 714 }
715
e7b909a6 716 /* Enable multicast promisc if num configured exceeds what we support */
4cd24eaf
JP		 717 if (netdev->flags & IFF_ALLMULTI ||
718 netdev_mc_count(netdev) > BE_MAX_MC) {
0ddf477b 719 be_cmd_multicast_set(adapter, adapter->if_handle, NULL,
e7b909a6 720 &adapter->mc_cmd_mem);
24307eef 721 goto done;
6b7c5b94 722 }
6b7c5b94 723
0ddf477b 724 be_cmd_multicast_set(adapter, adapter->if_handle, netdev,
f31e50a8 725 &adapter->mc_cmd_mem);
24307eef
SP		 726done:
727 return;
6b7c5b94
SP		 728}
729
ba343c77
SB		 730static int be_set_vf_mac(struct net_device *netdev, int vf, u8 *mac)
731{
732 struct be_adapter *adapter = netdev_priv(netdev);
733 int status;
734
735 if (!adapter->sriov_enabled)
736 return -EPERM;
737
738 if (!is_valid_ether_addr(mac) || (vf >= num_vfs))
739 return -EINVAL;
740
64600ea5
AK		 741 if (adapter->vf_cfg[vf].vf_pmac_id != BE_INVALID_PMAC_ID)
742 status = be_cmd_pmac_del(adapter,
743 adapter->vf_cfg[vf].vf_if_handle,
744 adapter->vf_cfg[vf].vf_pmac_id);
ba343c77 745
64600ea5
AK		 746 status = be_cmd_pmac_add(adapter, mac,
747 adapter->vf_cfg[vf].vf_if_handle,
748 &adapter->vf_cfg[vf].vf_pmac_id);
749
750 if (status)
ba343c77
SB		 751 dev_err(&adapter->pdev->dev, "MAC %pM set on VF %d Failed\n",
752 mac, vf);
64600ea5
AK		 753 else
754 memcpy(adapter->vf_cfg[vf].vf_mac_addr, mac, ETH_ALEN);
755
ba343c77
SB		 756 return status;
757}
758
64600ea5
AK		 759static int be_get_vf_config(struct net_device *netdev, int vf,
760 struct ifla_vf_info *vi)
761{
762 struct be_adapter *adapter = netdev_priv(netdev);
763
764 if (!adapter->sriov_enabled)
765 return -EPERM;
766
767 if (vf >= num_vfs)
768 return -EINVAL;
769
770 vi->vf = vf;
e1d18735 771 vi->tx_rate = adapter->vf_cfg[vf].vf_tx_rate;
1da87b7f 772 vi->vlan = adapter->vf_cfg[vf].vf_vlan_tag;
64600ea5
AK		 773 vi->qos = 0;
774 memcpy(&vi->mac, adapter->vf_cfg[vf].vf_mac_addr, ETH_ALEN);
775
776 return 0;
777}
778
1da87b7f
AK		 779static int be_set_vf_vlan(struct net_device *netdev,
780 int vf, u16 vlan, u8 qos)
781{
782 struct be_adapter *adapter = netdev_priv(netdev);
783 int status = 0;
784
785 if (!adapter->sriov_enabled)
786 return -EPERM;
787
788 if ((vf >= num_vfs) || (vlan > 4095))
789 return -EINVAL;
790
791 if (vlan) {
792 adapter->vf_cfg[vf].vf_vlan_tag = vlan;
793 adapter->vlans_added++;
794 } else {
795 adapter->vf_cfg[vf].vf_vlan_tag = 0;
796 adapter->vlans_added--;
797 }
798
799 status = be_vid_config(adapter, true, vf);
800
801 if (status)
802 dev_info(&adapter->pdev->dev,
803 "VLAN %d config on VF %d failed\n", vlan, vf);
804 return status;
805}
806
e1d18735
AK		 807static int be_set_vf_tx_rate(struct net_device *netdev,
808 int vf, int rate)
809{
810 struct be_adapter *adapter = netdev_priv(netdev);
811 int status = 0;
812
813 if (!adapter->sriov_enabled)
814 return -EPERM;
815
816 if ((vf >= num_vfs) || (rate < 0))
817 return -EINVAL;
818
819 if (rate > 10000)
820 rate = 10000;
821
822 adapter->vf_cfg[vf].vf_tx_rate = rate;
856c4012 823 status = be_cmd_set_qos(adapter, rate / 10, vf + 1);
e1d18735
AK		 824
825 if (status)
826 dev_info(&adapter->pdev->dev,
827 "tx rate %d on VF %d failed\n", rate, vf);
828 return status;
829}
830
3abcdeda 831static void be_rx_rate_update(struct be_rx_obj *rxo)
6b7c5b94 832{
3abcdeda 833 struct be_rx_stats *stats = &rxo->stats;
4097f663 834 ulong now = jiffies;
6b7c5b94 835
4097f663 836 /* Wrapped around */
3abcdeda
SP		 837 if (time_before(now, stats->rx_jiffies)) {
838 stats->rx_jiffies = now;
4097f663
SP		 839 return;
840 }
6b7c5b94
SP		 841
842 /* Update the rate once in two seconds */
3abcdeda 843 if ((now - stats->rx_jiffies) < 2 * HZ)
6b7c5b94
SP		 844 return;
845
3abcdeda
SP		 846 stats->rx_rate = be_calc_rate(stats->rx_bytes - stats->rx_bytes_prev,
847 now - stats->rx_jiffies);
848 stats->rx_jiffies = now;
849 stats->rx_bytes_prev = stats->rx_bytes;
6b7c5b94
SP		 850}
851
3abcdeda 852static void be_rx_stats_update(struct be_rx_obj *rxo,
1ef78abe 853 u32 pktsize, u16 numfrags, u8 pkt_type)
4097f663 854{
3abcdeda 855 struct be_rx_stats *stats = &rxo->stats;
1ef78abe 856
3abcdeda
SP		 857 stats->rx_compl++;
858 stats->rx_frags += numfrags;
859 stats->rx_bytes += pktsize;
860 stats->rx_pkts++;
1ef78abe 861 if (pkt_type == BE_MULTICAST_PACKET)
3abcdeda 862 stats->rx_mcast_pkts++;
4097f663
SP		 863}
864
c6ce2f4b 865static inline bool csum_passed(struct be_eth_rx_compl *rxcp)
728a9972 866{
c6ce2f4b 867 u8 l4_cksm, ipv6, ipcksm;
728a9972
AK		 868
869 l4_cksm = AMAP_GET_BITS(struct amap_eth_rx_compl, l4_cksm, rxcp);
870 ipcksm = AMAP_GET_BITS(struct amap_eth_rx_compl, ipcksm, rxcp);
c6ce2f4b 871 ipv6 = AMAP_GET_BITS(struct amap_eth_rx_compl, ip_version, rxcp);
728a9972 872
c6ce2f4b
SK		 873 /* Ignore ipcksm for ipv6 pkts */
874 return l4_cksm && (ipcksm || ipv6);
728a9972
AK		 875}
876
6b7c5b94 877static struct be_rx_page_info *
3abcdeda
SP		 878get_rx_page_info(struct be_adapter *adapter,
879 struct be_rx_obj *rxo,
880 u16 frag_idx)
6b7c5b94
SP		 881{
882 struct be_rx_page_info *rx_page_info;
3abcdeda 883 struct be_queue_info *rxq = &rxo->q;
6b7c5b94 884
3abcdeda 885 rx_page_info = &rxo->page_info_tbl[frag_idx];
6b7c5b94
SP		 886 BUG_ON(!rx_page_info->page);
887
205859a2 888 if (rx_page_info->last_page_user) {
2b7bcebf
IV		 889 dma_unmap_page(&adapter->pdev->dev,
890 dma_unmap_addr(rx_page_info, bus),
891 adapter->big_page_size, DMA_FROM_DEVICE);
205859a2
AK		 892 rx_page_info->last_page_user = false;
893 }
6b7c5b94
SP		 894
895 atomic_dec(&rxq->used);
896 return rx_page_info;
897}
898
899/* Throwaway the data in the Rx completion */
900static void be_rx_compl_discard(struct be_adapter *adapter,
3abcdeda
SP		 901 struct be_rx_obj *rxo,
902 struct be_eth_rx_compl *rxcp)
6b7c5b94 903{
3abcdeda 904 struct be_queue_info *rxq = &rxo->q;
6b7c5b94
SP		 905 struct be_rx_page_info *page_info;
906 u16 rxq_idx, i, num_rcvd;
907
908 rxq_idx = AMAP_GET_BITS(struct amap_eth_rx_compl, fragndx, rxcp);
909 num_rcvd = AMAP_GET_BITS(struct amap_eth_rx_compl, numfrags, rxcp);
910
64642811
SP		 911 /* Skip out-of-buffer compl(lancer) or flush compl(BE) */
912 if (likely(rxq_idx != rxo->last_frag_index && num_rcvd != 0)) {
913
914 rxo->last_frag_index = rxq_idx;
915
916 for (i = 0; i < num_rcvd; i++) {
917 page_info = get_rx_page_info(adapter, rxo, rxq_idx);
918 put_page(page_info->page);
919 memset(page_info, 0, sizeof(*page_info));
920 index_inc(&rxq_idx, rxq->len);
921 }
6b7c5b94
SP		 922 }
923}
924
925/*
926 * skb_fill_rx_data forms a complete skb for an ether frame
927 * indicated by rxcp.
928 */
3abcdeda 929static void skb_fill_rx_data(struct be_adapter *adapter, struct be_rx_obj *rxo,
89420424
SP		 930 struct sk_buff *skb, struct be_eth_rx_compl *rxcp,
931 u16 num_rcvd)
6b7c5b94 932{
3abcdeda 933 struct be_queue_info *rxq = &rxo->q;
6b7c5b94 934 struct be_rx_page_info *page_info;
89420424 935 u16 rxq_idx, i, j;
fa77406a 936 u32 pktsize, hdr_len, curr_frag_len, size;
6b7c5b94 937 u8 *start;
1ef78abe 938 u8 pkt_type;
6b7c5b94
SP		 939
940 rxq_idx = AMAP_GET_BITS(struct amap_eth_rx_compl, fragndx, rxcp);
941 pktsize = AMAP_GET_BITS(struct amap_eth_rx_compl, pktsize, rxcp);
1ef78abe 942 pkt_type = AMAP_GET_BITS(struct amap_eth_rx_compl, cast_enc, rxcp);
6b7c5b94 943
3abcdeda 944 page_info = get_rx_page_info(adapter, rxo, rxq_idx);
6b7c5b94
SP		 945
946 start = page_address(page_info->page) + page_info->page_offset;
947 prefetch(start);
948
949 /* Copy data in the first descriptor of this completion */
950 curr_frag_len = min(pktsize, rx_frag_size);
951
952 /* Copy the header portion into skb_data */
953 hdr_len = min((u32)BE_HDR_LEN, curr_frag_len);
954 memcpy(skb->data, start, hdr_len);
955 skb->len = curr_frag_len;
956 if (curr_frag_len <= BE_HDR_LEN) { /* tiny packet */
957 /* Complete packet has now been moved to data */
958 put_page(page_info->page);
959 skb->data_len = 0;
960 skb->tail += curr_frag_len;
961 } else {
962 skb_shinfo(skb)->nr_frags = 1;
963 skb_shinfo(skb)->frags[0].page = page_info->page;
964 skb_shinfo(skb)->frags[0].page_offset =
965 page_info->page_offset + hdr_len;
966 skb_shinfo(skb)->frags[0].size = curr_frag_len - hdr_len;
967 skb->data_len = curr_frag_len - hdr_len;
968 skb->tail += hdr_len;
969 }
205859a2 970 page_info->page = NULL;
6b7c5b94
SP		 971
972 if (pktsize <= rx_frag_size) {
973 BUG_ON(num_rcvd != 1);
76fbb429 974 goto done;
6b7c5b94
SP		 975 }
976
977 /* More frags present for this completion */
fa77406a 978 size = pktsize;
bd46cb6c 979 for (i = 1, j = 0; i < num_rcvd; i++) {
fa77406a 980 size -= curr_frag_len;
6b7c5b94 981 index_inc(&rxq_idx, rxq->len);
3abcdeda 982 page_info = get_rx_page_info(adapter, rxo, rxq_idx);
6b7c5b94 983
fa77406a 984 curr_frag_len = min(size, rx_frag_size);
6b7c5b94 985
bd46cb6c
AK		 986 /* Coalesce all frags from the same physical page in one slot */
987 if (page_info->page_offset == 0) {
988 /* Fresh page */
989 j++;
990 skb_shinfo(skb)->frags[j].page = page_info->page;
991 skb_shinfo(skb)->frags[j].page_offset =
992 page_info->page_offset;
993 skb_shinfo(skb)->frags[j].size = 0;
994 skb_shinfo(skb)->nr_frags++;
995 } else {
996 put_page(page_info->page);
997 }
998
999 skb_shinfo(skb)->frags[j].size += curr_frag_len;
6b7c5b94
SP		 1000 skb->len += curr_frag_len;
1001 skb->data_len += curr_frag_len;
6b7c5b94 1002
205859a2 1003 page_info->page = NULL;
6b7c5b94 1004 }
bd46cb6c 1005 BUG_ON(j > MAX_SKB_FRAGS);
6b7c5b94 1006
76fbb429 1007done:
3abcdeda 1008 be_rx_stats_update(rxo, pktsize, num_rcvd, pkt_type);
6b7c5b94
SP		 1009}
1010
5be93b9a 1011/* Process the RX completion indicated by rxcp when GRO is disabled */
6b7c5b94 1012static void be_rx_compl_process(struct be_adapter *adapter,
3abcdeda 1013 struct be_rx_obj *rxo,
6b7c5b94
SP		 1014 struct be_eth_rx_compl *rxcp)
1015{
1016 struct sk_buff *skb;
dcb9b564 1017 u32 vlanf, vid;
89420424 1018 u16 num_rcvd;
dcb9b564 1019 u8 vtm;
6b7c5b94 1020
89420424 1021 num_rcvd = AMAP_GET_BITS(struct amap_eth_rx_compl, numfrags, rxcp);
89420424 1022
89d71a66 1023 skb = netdev_alloc_skb_ip_align(adapter->netdev, BE_HDR_LEN);
a058a632 1024 if (unlikely(!skb)) {
6b7c5b94
SP		 1025 if (net_ratelimit())
1026 dev_warn(&adapter->pdev->dev, "skb alloc failed\n");
3abcdeda 1027 be_rx_compl_discard(adapter, rxo, rxcp);
6b7c5b94
SP		 1028 return;
1029 }
1030
3abcdeda 1031 skb_fill_rx_data(adapter, rxo, skb, rxcp, num_rcvd);
6b7c5b94 1032
c6ce2f4b 1033 if (likely(adapter->rx_csum && csum_passed(rxcp)))
728a9972 1034 skb->ip_summed = CHECKSUM_UNNECESSARY;
c6ce2f4b
SK		 1035 else
1036 skb_checksum_none_assert(skb);
6b7c5b94
SP		 1037
1038 skb->truesize = skb->len + sizeof(struct sk_buff);
1039 skb->protocol = eth_type_trans(skb, adapter->netdev);
6b7c5b94 1040
a058a632
SP		 1041 vlanf = AMAP_GET_BITS(struct amap_eth_rx_compl, vtp, rxcp);
1042 vtm = AMAP_GET_BITS(struct amap_eth_rx_compl, vtm, rxcp);
1043
1044 /* vlanf could be wrongly set in some cards.
1045 * ignore if vtm is not set */
3486be29 1046 if ((adapter->function_mode & 0x400) && !vtm)
a058a632
SP		 1047 vlanf = 0;
1048
1049 if (unlikely(vlanf)) {
82903e4b 1050 if (!adapter->vlan_grp || adapter->vlans_added == 0) {
6b7c5b94
SP		 1051 kfree_skb(skb);
1052 return;
1053 }
1054 vid = AMAP_GET_BITS(struct amap_eth_rx_compl, vlan_tag, rxcp);
fe6d2a38
SP		 1055 if (!lancer_chip(adapter))
1056 vid = swab16(vid);
6b7c5b94
SP		 1057 vlan_hwaccel_receive_skb(skb, adapter->vlan_grp, vid);
1058 } else {
1059 netif_receive_skb(skb);
1060 }
6b7c5b94
SP		 1061}
1062
5be93b9a
AK		 1063/* Process the RX completion indicated by rxcp when GRO is enabled */
1064static void be_rx_compl_process_gro(struct be_adapter *adapter,
3abcdeda
SP		 1065 struct be_rx_obj *rxo,
1066 struct be_eth_rx_compl *rxcp)
6b7c5b94
SP		 1067{
1068 struct be_rx_page_info *page_info;
5be93b9a 1069 struct sk_buff *skb = NULL;
3abcdeda
SP		 1070 struct be_queue_info *rxq = &rxo->q;
1071 struct be_eq_obj *eq_obj = &rxo->rx_eq;
6b7c5b94 1072 u32 num_rcvd, pkt_size, remaining, vlanf, curr_frag_len;
bd46cb6c 1073 u16 i, rxq_idx = 0, vid, j;
dcb9b564 1074 u8 vtm;
1ef78abe 1075 u8 pkt_type;
6b7c5b94
SP		 1076
1077 num_rcvd = AMAP_GET_BITS(struct amap_eth_rx_compl, numfrags, rxcp);
1078 pkt_size = AMAP_GET_BITS(struct amap_eth_rx_compl, pktsize, rxcp);
1079 vlanf = AMAP_GET_BITS(struct amap_eth_rx_compl, vtp, rxcp);
1080 rxq_idx = AMAP_GET_BITS(struct amap_eth_rx_compl, fragndx, rxcp);
dcb9b564 1081 vtm = AMAP_GET_BITS(struct amap_eth_rx_compl, vtm, rxcp);
1ef78abe 1082 pkt_type = AMAP_GET_BITS(struct amap_eth_rx_compl, cast_enc, rxcp);
dcb9b564
AK		 1083
1084 /* vlanf could be wrongly set in some cards.
1085 * ignore if vtm is not set */
3486be29 1086 if ((adapter->function_mode & 0x400) && !vtm)
dcb9b564 1087 vlanf = 0;
6b7c5b94 1088
5be93b9a
AK		 1089 skb = napi_get_frags(&eq_obj->napi);
1090 if (!skb) {
3abcdeda 1091 be_rx_compl_discard(adapter, rxo, rxcp);
5be93b9a
AK		 1092 return;
1093 }
1094
6b7c5b94 1095 remaining = pkt_size;
bd46cb6c 1096 for (i = 0, j = -1; i < num_rcvd; i++) {
3abcdeda 1097 page_info = get_rx_page_info(adapter, rxo, rxq_idx);
6b7c5b94
SP		 1098
1099 curr_frag_len = min(remaining, rx_frag_size);
1100
bd46cb6c
AK		 1101 /* Coalesce all frags from the same physical page in one slot */
1102 if (i == 0 || page_info->page_offset == 0) {
1103 /* First frag or Fresh page */
1104 j++;
5be93b9a
AK		 1105 skb_shinfo(skb)->frags[j].page = page_info->page;
1106 skb_shinfo(skb)->frags[j].page_offset =
1107 page_info->page_offset;
1108 skb_shinfo(skb)->frags[j].size = 0;
bd46cb6c
AK		 1109 } else {
1110 put_page(page_info->page);
1111 }
5be93b9a 1112 skb_shinfo(skb)->frags[j].size += curr_frag_len;
6b7c5b94 1113
bd46cb6c 1114 remaining -= curr_frag_len;
6b7c5b94 1115 index_inc(&rxq_idx, rxq->len);
6b7c5b94
SP		 1116 memset(page_info, 0, sizeof(*page_info));
1117 }
bd46cb6c 1118 BUG_ON(j > MAX_SKB_FRAGS);
6b7c5b94 1119
5be93b9a
AK		 1120 skb_shinfo(skb)->nr_frags = j + 1;
1121 skb->len = pkt_size;
1122 skb->data_len = pkt_size;
1123 skb->truesize += pkt_size;
1124 skb->ip_summed = CHECKSUM_UNNECESSARY;
1125
6b7c5b94 1126 if (likely(!vlanf)) {
5be93b9a 1127 napi_gro_frags(&eq_obj->napi);
6b7c5b94
SP		 1128 } else {
1129 vid = AMAP_GET_BITS(struct amap_eth_rx_compl, vlan_tag, rxcp);
fe6d2a38
SP		 1130 if (!lancer_chip(adapter))
1131 vid = swab16(vid);
6b7c5b94 1132
82903e4b 1133 if (!adapter->vlan_grp || adapter->vlans_added == 0)
6b7c5b94
SP		 1134 return;
1135
5be93b9a 1136 vlan_gro_frags(&eq_obj->napi, adapter->vlan_grp, vid);
6b7c5b94
SP		 1137 }
1138
3abcdeda 1139 be_rx_stats_update(rxo, pkt_size, num_rcvd, pkt_type);
6b7c5b94
SP		 1140}
1141
3abcdeda 1142static struct be_eth_rx_compl *be_rx_compl_get(struct be_rx_obj *rxo)
6b7c5b94 1143{
3abcdeda 1144 struct be_eth_rx_compl *rxcp = queue_tail_node(&rxo->cq);
6b7c5b94
SP		 1145
1146 if (rxcp->dw[offsetof(struct amap_eth_rx_compl, valid) / 32] == 0)
1147 return NULL;
1148
f3eb62d2 1149 rmb();
6b7c5b94
SP		 1150 be_dws_le_to_cpu(rxcp, sizeof(*rxcp));
1151
3abcdeda 1152 queue_tail_inc(&rxo->cq);
6b7c5b94
SP		 1153 return rxcp;
1154}
1155
a7a0ef31
SP		 1156/* To reset the valid bit, we need to reset the whole word as
1157 * when walking the queue the valid entries are little-endian
1158 * and invalid entries are host endian
1159 */
1160static inline void be_rx_compl_reset(struct be_eth_rx_compl *rxcp)
1161{
1162 rxcp->dw[offsetof(struct amap_eth_rx_compl, valid) / 32] = 0;
1163}
1164
6b7c5b94
SP		 1165static inline struct page *be_alloc_pages(u32 size)
1166{
1167 gfp_t alloc_flags = GFP_ATOMIC;
1168 u32 order = get_order(size);
1169 if (order > 0)
1170 alloc_flags |= __GFP_COMP;
1171 return alloc_pages(alloc_flags, order);
1172}
1173
1174/*
1175 * Allocate a page, split it to fragments of size rx_frag_size and post as
1176 * receive buffers to BE
1177 */
3abcdeda 1178static void be_post_rx_frags(struct be_rx_obj *rxo)
6b7c5b94 1179{
3abcdeda
SP		 1180 struct be_adapter *adapter = rxo->adapter;
1181 struct be_rx_page_info *page_info_tbl = rxo->page_info_tbl;
26d92f92 1182 struct be_rx_page_info *page_info = NULL, *prev_page_info = NULL;
3abcdeda 1183 struct be_queue_info *rxq = &rxo->q;
6b7c5b94
SP		 1184 struct page *pagep = NULL;
1185 struct be_eth_rx_d *rxd;
1186 u64 page_dmaaddr = 0, frag_dmaaddr;
1187 u32 posted, page_offset = 0;
1188
3abcdeda 1189 page_info = &rxo->page_info_tbl[rxq->head];
6b7c5b94
SP		 1190 for (posted = 0; posted < MAX_RX_POST && !page_info->page; posted++) {
1191 if (!pagep) {
1192 pagep = be_alloc_pages(adapter->big_page_size);
1193 if (unlikely(!pagep)) {
3abcdeda 1194 rxo->stats.rx_post_fail++;
6b7c5b94
SP		 1195 break;
1196 }
2b7bcebf
IV		 1197 page_dmaaddr = dma_map_page(&adapter->pdev->dev, pagep,
1198 0, adapter->big_page_size,
1199 DMA_FROM_DEVICE);
6b7c5b94
SP		 1200 page_info->page_offset = 0;
1201 } else {
1202 get_page(pagep);
1203 page_info->page_offset = page_offset + rx_frag_size;
1204 }
1205 page_offset = page_info->page_offset;
1206 page_info->page = pagep;
fac6da5b 1207 dma_unmap_addr_set(page_info, bus, page_dmaaddr);
6b7c5b94
SP		 1208 frag_dmaaddr = page_dmaaddr + page_info->page_offset;
1209
1210 rxd = queue_head_node(rxq);
1211 rxd->fragpa_lo = cpu_to_le32(frag_dmaaddr & 0xFFFFFFFF);
1212 rxd->fragpa_hi = cpu_to_le32(upper_32_bits(frag_dmaaddr));
6b7c5b94
SP		 1213
1214 /* Any space left in the current big page for another frag? */
1215 if ((page_offset + rx_frag_size + rx_frag_size) >
1216 adapter->big_page_size) {
1217 pagep = NULL;
1218 page_info->last_page_user = true;
1219 }
26d92f92
SP		 1220
1221 prev_page_info = page_info;
1222 queue_head_inc(rxq);
6b7c5b94
SP		 1223 page_info = &page_info_tbl[rxq->head];
1224 }
1225 if (pagep)
26d92f92 1226 prev_page_info->last_page_user = true;
6b7c5b94
SP		 1227
1228 if (posted) {
6b7c5b94 1229 atomic_add(posted, &rxq->used);
8788fdc2 1230 be_rxq_notify(adapter, rxq->id, posted);
ea1dae11
SP		 1231 } else if (atomic_read(&rxq->used) == 0) {
1232 /* Let be_worker replenish when memory is available */
3abcdeda 1233 rxo->rx_post_starved = true;
6b7c5b94 1234 }
6b7c5b94
SP		 1235}
1236
5fb379ee 1237static struct be_eth_tx_compl *be_tx_compl_get(struct be_queue_info *tx_cq)
6b7c5b94 1238{
6b7c5b94
SP		 1239 struct be_eth_tx_compl *txcp = queue_tail_node(tx_cq);
1240
1241 if (txcp->dw[offsetof(struct amap_eth_tx_compl, valid) / 32] == 0)
1242 return NULL;
1243
f3eb62d2 1244 rmb();
6b7c5b94
SP		 1245 be_dws_le_to_cpu(txcp, sizeof(*txcp));
1246
1247 txcp->dw[offsetof(struct amap_eth_tx_compl, valid) / 32] = 0;
1248
1249 queue_tail_inc(tx_cq);
1250 return txcp;
1251}
1252
1253static void be_tx_compl_process(struct be_adapter *adapter, u16 last_index)
1254{
1255 struct be_queue_info *txq = &adapter->tx_obj.q;
a73b796e 1256 struct be_eth_wrb *wrb;
6b7c5b94
SP		 1257 struct sk_buff **sent_skbs = adapter->tx_obj.sent_skb_list;
1258 struct sk_buff *sent_skb;
ec43b1a6
SP		 1259 u16 cur_index, num_wrbs = 1; /* account for hdr wrb */
1260 bool unmap_skb_hdr = true;
6b7c5b94 1261
ec43b1a6 1262 sent_skb = sent_skbs[txq->tail];
6b7c5b94 1263 BUG_ON(!sent_skb);
ec43b1a6
SP		 1264 sent_skbs[txq->tail] = NULL;
1265
1266 /* skip header wrb */
a73b796e 1267 queue_tail_inc(txq);
6b7c5b94 1268
ec43b1a6 1269 do {
6b7c5b94 1270 cur_index = txq->tail;
a73b796e 1271 wrb = queue_tail_node(txq);
2b7bcebf
IV		 1272 unmap_tx_frag(&adapter->pdev->dev, wrb,
1273 (unmap_skb_hdr && skb_headlen(sent_skb)));
ec43b1a6
SP		 1274 unmap_skb_hdr = false;
1275
6b7c5b94
SP		 1276 num_wrbs++;
1277 queue_tail_inc(txq);
ec43b1a6 1278 } while (cur_index != last_index);
6b7c5b94
SP		 1279
1280 atomic_sub(num_wrbs, &txq->used);
a73b796e 1281
6b7c5b94
SP		 1282 kfree_skb(sent_skb);
1283}
1284
859b1e4e
SP		 1285static inline struct be_eq_entry *event_get(struct be_eq_obj *eq_obj)
1286{
1287 struct be_eq_entry *eqe = queue_tail_node(&eq_obj->q);
1288
1289 if (!eqe->evt)
1290 return NULL;
1291
f3eb62d2 1292 rmb();
859b1e4e
SP		 1293 eqe->evt = le32_to_cpu(eqe->evt);
1294 queue_tail_inc(&eq_obj->q);
1295 return eqe;
1296}
1297
1298static int event_handle(struct be_adapter *adapter,
1299 struct be_eq_obj *eq_obj)
1300{
1301 struct be_eq_entry *eqe;
1302 u16 num = 0;
1303
1304 while ((eqe = event_get(eq_obj)) != NULL) {
1305 eqe->evt = 0;
1306 num++;
1307 }
1308
1309 /* Deal with any spurious interrupts that come
1310 * without events
1311 */
1312 be_eq_notify(adapter, eq_obj->q.id, true, true, num);
1313 if (num)
1314 napi_schedule(&eq_obj->napi);
1315
1316 return num;
1317}
1318
1319/* Just read and notify events without processing them.
1320 * Used at the time of destroying event queues */
1321static void be_eq_clean(struct be_adapter *adapter,
1322 struct be_eq_obj *eq_obj)
1323{
1324 struct be_eq_entry *eqe;
1325 u16 num = 0;
1326
1327 while ((eqe = event_get(eq_obj)) != NULL) {
1328 eqe->evt = 0;
1329 num++;
1330 }
1331
1332 if (num)
1333 be_eq_notify(adapter, eq_obj->q.id, false, true, num);
1334}
1335
3abcdeda 1336static void be_rx_q_clean(struct be_adapter *adapter, struct be_rx_obj *rxo)
6b7c5b94
SP		 1337{
1338 struct be_rx_page_info *page_info;
3abcdeda
SP		 1339 struct be_queue_info *rxq = &rxo->q;
1340 struct be_queue_info *rx_cq = &rxo->cq;
6b7c5b94
SP		 1341 struct be_eth_rx_compl *rxcp;
1342 u16 tail;
1343
1344 /* First cleanup pending rx completions */
3abcdeda
SP		 1345 while ((rxcp = be_rx_compl_get(rxo)) != NULL) {
1346 be_rx_compl_discard(adapter, rxo, rxcp);
a7a0ef31 1347 be_rx_compl_reset(rxcp);
64642811 1348 be_cq_notify(adapter, rx_cq->id, false, 1);
6b7c5b94
SP		 1349 }
1350
1351 /* Then free posted rx buffer that were not used */
1352 tail = (rxq->head + rxq->len - atomic_read(&rxq->used)) % rxq->len;
cdab23b7 1353 for (; atomic_read(&rxq->used) > 0; index_inc(&tail, rxq->len)) {
3abcdeda 1354 page_info = get_rx_page_info(adapter, rxo, tail);
6b7c5b94
SP		 1355 put_page(page_info->page);
1356 memset(page_info, 0, sizeof(*page_info));
1357 }
1358 BUG_ON(atomic_read(&rxq->used));
1359}
1360
a8e9179a 1361static void be_tx_compl_clean(struct be_adapter *adapter)
6b7c5b94 1362{
a8e9179a 1363 struct be_queue_info *tx_cq = &adapter->tx_obj.cq;
6b7c5b94 1364 struct be_queue_info *txq = &adapter->tx_obj.q;
a8e9179a
SP		 1365 struct be_eth_tx_compl *txcp;
1366 u16 end_idx, cmpl = 0, timeo = 0;
b03388d6
SP		 1367 struct sk_buff **sent_skbs = adapter->tx_obj.sent_skb_list;
1368 struct sk_buff *sent_skb;
1369 bool dummy_wrb;
a8e9179a
SP		 1370
1371 /* Wait for a max of 200ms for all the tx-completions to arrive. */
1372 do {
1373 while ((txcp = be_tx_compl_get(tx_cq))) {
1374 end_idx = AMAP_GET_BITS(struct amap_eth_tx_compl,
1375 wrb_index, txcp);
1376 be_tx_compl_process(adapter, end_idx);
1377 cmpl++;
1378 }
1379 if (cmpl) {
1380 be_cq_notify(adapter, tx_cq->id, false, cmpl);
1381 cmpl = 0;
1382 }
1383
1384 if (atomic_read(&txq->used) == 0 || ++timeo > 200)
1385 break;
1386
1387 mdelay(1);
1388 } while (true);
1389
1390 if (atomic_read(&txq->used))
1391 dev_err(&adapter->pdev->dev, "%d pending tx-completions\n",
1392 atomic_read(&txq->used));
b03388d6
SP		 1393
1394 /* free posted tx for which compls will never arrive */
1395 while (atomic_read(&txq->used)) {
1396 sent_skb = sent_skbs[txq->tail];
1397 end_idx = txq->tail;
1398 index_adv(&end_idx,
fe6d2a38
SP		 1399 wrb_cnt_for_skb(adapter, sent_skb, &dummy_wrb) - 1,
1400 txq->len);
b03388d6
SP		 1401 be_tx_compl_process(adapter, end_idx);
1402 }
6b7c5b94
SP		 1403}
1404
5fb379ee
SP		 1405static void be_mcc_queues_destroy(struct be_adapter *adapter)
1406{
1407 struct be_queue_info *q;
5fb379ee 1408
8788fdc2 1409 q = &adapter->mcc_obj.q;
5fb379ee 1410 if (q->created)
8788fdc2 1411 be_cmd_q_destroy(adapter, q, QTYPE_MCCQ);
5fb379ee
SP		 1412 be_queue_free(adapter, q);
1413
8788fdc2 1414 q = &adapter->mcc_obj.cq;
5fb379ee 1415 if (q->created)
8788fdc2 1416 be_cmd_q_destroy(adapter, q, QTYPE_CQ);
5fb379ee
SP		 1417 be_queue_free(adapter, q);
1418}
1419
1420/* Must be called only after TX qs are created as MCC shares TX EQ */
1421static int be_mcc_queues_create(struct be_adapter *adapter)
1422{
1423 struct be_queue_info *q, *cq;
5fb379ee
SP		 1424
1425 /* Alloc MCC compl queue */
8788fdc2 1426 cq = &adapter->mcc_obj.cq;
5fb379ee 1427 if (be_queue_alloc(adapter, cq, MCC_CQ_LEN,
efd2e40a 1428 sizeof(struct be_mcc_compl)))
5fb379ee
SP		 1429 goto err;
1430
1431 /* Ask BE to create MCC compl queue; share TX's eq */
8788fdc2 1432 if (be_cmd_cq_create(adapter, cq, &adapter->tx_eq.q, false, true, 0))
5fb379ee
SP		 1433 goto mcc_cq_free;
1434
1435 /* Alloc MCC queue */
8788fdc2 1436 q = &adapter->mcc_obj.q;
5fb379ee
SP		 1437 if (be_queue_alloc(adapter, q, MCC_Q_LEN, sizeof(struct be_mcc_wrb)))
1438 goto mcc_cq_destroy;
1439
1440 /* Ask BE to create MCC queue */
8788fdc2 1441 if (be_cmd_mccq_create(adapter, q, cq))
5fb379ee
SP		 1442 goto mcc_q_free;
1443
1444 return 0;
1445
1446mcc_q_free:
1447 be_queue_free(adapter, q);
1448mcc_cq_destroy:
8788fdc2 1449 be_cmd_q_destroy(adapter, cq, QTYPE_CQ);
5fb379ee
SP		 1450mcc_cq_free:
1451 be_queue_free(adapter, cq);
1452err:
1453 return -1;
1454}
1455
6b7c5b94
SP		 1456static void be_tx_queues_destroy(struct be_adapter *adapter)
1457{
1458 struct be_queue_info *q;
1459
1460 q = &adapter->tx_obj.q;
a8e9179a 1461 if (q->created)
8788fdc2 1462 be_cmd_q_destroy(adapter, q, QTYPE_TXQ);
6b7c5b94
SP		 1463 be_queue_free(adapter, q);
1464
1465 q = &adapter->tx_obj.cq;
1466 if (q->created)
8788fdc2 1467 be_cmd_q_destroy(adapter, q, QTYPE_CQ);
6b7c5b94
SP		 1468 be_queue_free(adapter, q);
1469
859b1e4e
SP		 1470 /* Clear any residual events */
1471 be_eq_clean(adapter, &adapter->tx_eq);
1472
6b7c5b94
SP		 1473 q = &adapter->tx_eq.q;
1474 if (q->created)
8788fdc2 1475 be_cmd_q_destroy(adapter, q, QTYPE_EQ);
6b7c5b94
SP		 1476 be_queue_free(adapter, q);
1477}
1478
1479static int be_tx_queues_create(struct be_adapter *adapter)
1480{
1481 struct be_queue_info *eq, *q, *cq;
1482
1483 adapter->tx_eq.max_eqd = 0;
1484 adapter->tx_eq.min_eqd = 0;
1485 adapter->tx_eq.cur_eqd = 96;
1486 adapter->tx_eq.enable_aic = false;
1487 /* Alloc Tx Event queue */
1488 eq = &adapter->tx_eq.q;
1489 if (be_queue_alloc(adapter, eq, EVNT_Q_LEN, sizeof(struct be_eq_entry)))
1490 return -1;
1491
1492 /* Ask BE to create Tx Event queue */
8788fdc2 1493 if (be_cmd_eq_create(adapter, eq, adapter->tx_eq.cur_eqd))
6b7c5b94 1494 goto tx_eq_free;
fe6d2a38
SP		 1495
1496 adapter->tx_eq.msix_vec_idx = adapter->msix_vec_next_idx++;
1497
ba343c77 1498
6b7c5b94
SP		 1499 /* Alloc TX eth compl queue */
1500 cq = &adapter->tx_obj.cq;
1501 if (be_queue_alloc(adapter, cq, TX_CQ_LEN,
1502 sizeof(struct be_eth_tx_compl)))
1503 goto tx_eq_destroy;
1504
1505 /* Ask BE to create Tx eth compl queue */
8788fdc2 1506 if (be_cmd_cq_create(adapter, cq, eq, false, false, 3))
6b7c5b94
SP		 1507 goto tx_cq_free;
1508
1509 /* Alloc TX eth queue */
1510 q = &adapter->tx_obj.q;
1511 if (be_queue_alloc(adapter, q, TX_Q_LEN, sizeof(struct be_eth_wrb)))
1512 goto tx_cq_destroy;
1513
1514 /* Ask BE to create Tx eth queue */
8788fdc2 1515 if (be_cmd_txq_create(adapter, q, cq))
6b7c5b94
SP		 1516 goto tx_q_free;
1517 return 0;
1518
1519tx_q_free:
1520 be_queue_free(adapter, q);
1521tx_cq_destroy:
8788fdc2 1522 be_cmd_q_destroy(adapter, cq, QTYPE_CQ);
6b7c5b94
SP		 1523tx_cq_free:
1524 be_queue_free(adapter, cq);
1525tx_eq_destroy:
8788fdc2 1526 be_cmd_q_destroy(adapter, eq, QTYPE_EQ);
6b7c5b94
SP		 1527tx_eq_free:
1528 be_queue_free(adapter, eq);
1529 return -1;
1530}
1531
1532static void be_rx_queues_destroy(struct be_adapter *adapter)
1533{
1534 struct be_queue_info *q;
3abcdeda
SP		 1535 struct be_rx_obj *rxo;
1536 int i;
1537
1538 for_all_rx_queues(adapter, rxo, i) {
1539 q = &rxo->q;
1540 if (q->created) {
1541 be_cmd_q_destroy(adapter, q, QTYPE_RXQ);
1542 /* After the rxq is invalidated, wait for a grace time
1543 * of 1ms for all dma to end and the flush compl to
1544 * arrive
1545 */
1546 mdelay(1);
1547 be_rx_q_clean(adapter, rxo);
1548 }
1549 be_queue_free(adapter, q);
1550
1551 q = &rxo->cq;
1552 if (q->created)
1553 be_cmd_q_destroy(adapter, q, QTYPE_CQ);
1554 be_queue_free(adapter, q);
1555
1556 /* Clear any residual events */
1557 q = &rxo->rx_eq.q;
1558 if (q->created) {
1559 be_eq_clean(adapter, &rxo->rx_eq);
1560 be_cmd_q_destroy(adapter, q, QTYPE_EQ);
1561 }
1562 be_queue_free(adapter, q);
6b7c5b94 1563 }
6b7c5b94
SP		 1564}
1565
1566static int be_rx_queues_create(struct be_adapter *adapter)
1567{
1568 struct be_queue_info *eq, *q, *cq;
3abcdeda
SP		 1569 struct be_rx_obj *rxo;
1570 int rc, i;
6b7c5b94 1571
6b7c5b94 1572 adapter->big_page_size = (1 << get_order(rx_frag_size)) * PAGE_SIZE;
3abcdeda
SP		 1573 for_all_rx_queues(adapter, rxo, i) {
1574 rxo->adapter = adapter;
64642811
SP		 1575 /* Init last_frag_index so that the frag index in the first
1576 * completion will never match */
1577 rxo->last_frag_index = 0xffff;
3abcdeda
SP		 1578 rxo->rx_eq.max_eqd = BE_MAX_EQD;
1579 rxo->rx_eq.enable_aic = true;
1580
1581 /* EQ */
1582 eq = &rxo->rx_eq.q;
1583 rc = be_queue_alloc(adapter, eq, EVNT_Q_LEN,
1584 sizeof(struct be_eq_entry));
1585 if (rc)
1586 goto err;
1587
1588 rc = be_cmd_eq_create(adapter, eq, rxo->rx_eq.cur_eqd);
1589 if (rc)
1590 goto err;
1591
fe6d2a38
SP		 1592 rxo->rx_eq.msix_vec_idx = adapter->msix_vec_next_idx++;
1593
3abcdeda
SP		 1594 /* CQ */
1595 cq = &rxo->cq;
1596 rc = be_queue_alloc(adapter, cq, RX_CQ_LEN,
1597 sizeof(struct be_eth_rx_compl));
1598 if (rc)
1599 goto err;
1600
1601 rc = be_cmd_cq_create(adapter, cq, eq, false, false, 3);
1602 if (rc)
1603 goto err;
3abcdeda
SP		 1604 /* Rx Q */
1605 q = &rxo->q;
1606 rc = be_queue_alloc(adapter, q, RX_Q_LEN,
1607 sizeof(struct be_eth_rx_d));
1608 if (rc)
1609 goto err;
1610
1611 rc = be_cmd_rxq_create(adapter, q, cq->id, rx_frag_size,
1612 BE_MAX_JUMBO_FRAME_SIZE, adapter->if_handle,
1613 (i > 0) ? 1 : 0/* rss enable */, &rxo->rss_id);
1614 if (rc)
1615 goto err;
1616 }
1617
1618 if (be_multi_rxq(adapter)) {
1619 u8 rsstable[MAX_RSS_QS];
1620
1621 for_all_rss_queues(adapter, rxo, i)
1622 rsstable[i] = rxo->rss_id;
1623
1624 rc = be_cmd_rss_config(adapter, rsstable,
1625 adapter->num_rx_qs - 1);
1626 if (rc)
1627 goto err;
1628 }
6b7c5b94
SP		 1629
1630 return 0;
3abcdeda
SP		 1631err:
1632 be_rx_queues_destroy(adapter);
1633 return -1;
6b7c5b94 1634}
6b7c5b94 1635
fe6d2a38 1636static bool event_peek(struct be_eq_obj *eq_obj)
b628bde2 1637{
fe6d2a38
SP		 1638 struct be_eq_entry *eqe = queue_tail_node(&eq_obj->q);
1639 if (!eqe->evt)
1640 return false;
1641 else
1642 return true;
b628bde2
SP		 1643}
1644
6b7c5b94
SP		 1645static irqreturn_t be_intx(int irq, void *dev)
1646{
1647 struct be_adapter *adapter = dev;
3abcdeda 1648 struct be_rx_obj *rxo;
fe6d2a38 1649 int isr, i, tx = 0 , rx = 0;
6b7c5b94 1650
fe6d2a38
SP		 1651 if (lancer_chip(adapter)) {
1652 if (event_peek(&adapter->tx_eq))
1653 tx = event_handle(adapter, &adapter->tx_eq);
1654 for_all_rx_queues(adapter, rxo, i) {
1655 if (event_peek(&rxo->rx_eq))
1656 rx |= event_handle(adapter, &rxo->rx_eq);
1657 }
6b7c5b94 1658
fe6d2a38
SP		 1659 if (!(tx || rx))
1660 return IRQ_NONE;
3abcdeda 1661
fe6d2a38
SP		 1662 } else {
1663 isr = ioread32(adapter->csr + CEV_ISR0_OFFSET +
1664 (adapter->tx_eq.q.id / 8) * CEV_ISR_SIZE);
1665 if (!isr)
1666 return IRQ_NONE;
1667
1668 if ((1 << adapter->tx_eq.msix_vec_idx & isr))
1669 event_handle(adapter, &adapter->tx_eq);
1670
1671 for_all_rx_queues(adapter, rxo, i) {
1672 if ((1 << rxo->rx_eq.msix_vec_idx & isr))
1673 event_handle(adapter, &rxo->rx_eq);
1674 }
3abcdeda 1675 }
c001c213 1676
8788fdc2 1677 return IRQ_HANDLED;
6b7c5b94
SP		 1678}
1679
1680static irqreturn_t be_msix_rx(int irq, void *dev)
1681{
3abcdeda
SP		 1682 struct be_rx_obj *rxo = dev;
1683 struct be_adapter *adapter = rxo->adapter;
6b7c5b94 1684
3abcdeda 1685 event_handle(adapter, &rxo->rx_eq);
6b7c5b94
SP		 1686
1687 return IRQ_HANDLED;
1688}
1689
5fb379ee 1690static irqreturn_t be_msix_tx_mcc(int irq, void *dev)
6b7c5b94
SP		 1691{
1692 struct be_adapter *adapter = dev;
1693
8788fdc2 1694 event_handle(adapter, &adapter->tx_eq);
6b7c5b94
SP		 1695
1696 return IRQ_HANDLED;
1697}
1698
64642811
SP		 1699static inline bool do_gro(struct be_rx_obj *rxo,
1700 struct be_eth_rx_compl *rxcp, u8 err)
6b7c5b94 1701{
6b7c5b94
SP		 1702 int tcp_frame = AMAP_GET_BITS(struct amap_eth_rx_compl, tcpf, rxcp);
1703
1704 if (err)
3abcdeda 1705 rxo->stats.rxcp_err++;
6b7c5b94 1706
5be93b9a 1707 return (tcp_frame && !err) ? true : false;
6b7c5b94
SP		 1708}
1709
49b05221 1710static int be_poll_rx(struct napi_struct *napi, int budget)
6b7c5b94
SP		 1711{
1712 struct be_eq_obj *rx_eq = container_of(napi, struct be_eq_obj, napi);
3abcdeda
SP		 1713 struct be_rx_obj *rxo = container_of(rx_eq, struct be_rx_obj, rx_eq);
1714 struct be_adapter *adapter = rxo->adapter;
1715 struct be_queue_info *rx_cq = &rxo->cq;
6b7c5b94
SP		 1716 struct be_eth_rx_compl *rxcp;
1717 u32 work_done;
64642811
SP		 1718 u16 frag_index, num_rcvd;
1719 u8 err;
6b7c5b94 1720
3abcdeda 1721 rxo->stats.rx_polls++;
6b7c5b94 1722 for (work_done = 0; work_done < budget; work_done++) {
3abcdeda 1723 rxcp = be_rx_compl_get(rxo);
6b7c5b94
SP		 1724 if (!rxcp)
1725 break;
1726
64642811
SP		 1727 err = AMAP_GET_BITS(struct amap_eth_rx_compl, err, rxcp);
1728 frag_index = AMAP_GET_BITS(struct amap_eth_rx_compl, fragndx,
1729 rxcp);
1730 num_rcvd = AMAP_GET_BITS(struct amap_eth_rx_compl, numfrags,
1731 rxcp);
1732
1733 /* Skip out-of-buffer compl(lancer) or flush compl(BE) */
1734 if (likely(frag_index != rxo->last_frag_index &&
1735 num_rcvd != 0)) {
1736 rxo->last_frag_index = frag_index;
1737
1738 if (do_gro(rxo, rxcp, err))
1739 be_rx_compl_process_gro(adapter, rxo, rxcp);
1740 else
1741 be_rx_compl_process(adapter, rxo, rxcp);
1742 }
a7a0ef31
SP		 1743
1744 be_rx_compl_reset(rxcp);
6b7c5b94
SP		 1745 }
1746
6b7c5b94 1747 /* Refill the queue */
3abcdeda
SP		 1748 if (atomic_read(&rxo->q.used) < RX_FRAGS_REFILL_WM)
1749 be_post_rx_frags(rxo);
6b7c5b94
SP		 1750
1751 /* All consumed */
1752 if (work_done < budget) {
1753 napi_complete(napi);
8788fdc2 1754 be_cq_notify(adapter, rx_cq->id, true, work_done);
6b7c5b94
SP		 1755 } else {
1756 /* More to be consumed; continue with interrupts disabled */
8788fdc2 1757 be_cq_notify(adapter, rx_cq->id, false, work_done);
6b7c5b94
SP		 1758 }
1759 return work_done;
1760}
1761
f31e50a8
SP		 1762/* As TX and MCC share the same EQ check for both TX and MCC completions.
1763 * For TX/MCC we don't honour budget; consume everything
1764 */
1765static int be_poll_tx_mcc(struct napi_struct *napi, int budget)
6b7c5b94 1766{
f31e50a8
SP		 1767 struct be_eq_obj *tx_eq = container_of(napi, struct be_eq_obj, napi);
1768 struct be_adapter *adapter =
1769 container_of(tx_eq, struct be_adapter, tx_eq);
5fb379ee
SP		 1770 struct be_queue_info *txq = &adapter->tx_obj.q;
1771 struct be_queue_info *tx_cq = &adapter->tx_obj.cq;
6b7c5b94 1772 struct be_eth_tx_compl *txcp;
f31e50a8 1773 int tx_compl = 0, mcc_compl, status = 0;
6b7c5b94
SP		 1774 u16 end_idx;
1775
5fb379ee 1776 while ((txcp = be_tx_compl_get(tx_cq))) {
6b7c5b94 1777 end_idx = AMAP_GET_BITS(struct amap_eth_tx_compl,
f31e50a8 1778 wrb_index, txcp);
6b7c5b94 1779 be_tx_compl_process(adapter, end_idx);
f31e50a8 1780 tx_compl++;
6b7c5b94
SP		 1781 }
1782
f31e50a8
SP		 1783 mcc_compl = be_process_mcc(adapter, &status);
1784
1785 napi_complete(napi);
1786
1787 if (mcc_compl) {
1788 struct be_mcc_obj *mcc_obj = &adapter->mcc_obj;
1789 be_cq_notify(adapter, mcc_obj->cq.id, true, mcc_compl);
1790 }
1791
1792 if (tx_compl) {
1793 be_cq_notify(adapter, adapter->tx_obj.cq.id, true, tx_compl);
5fb379ee
SP		 1794
1795 /* As Tx wrbs have been freed up, wake up netdev queue if
1796 * it was stopped due to lack of tx wrbs.
1797 */
1798 if (netif_queue_stopped(adapter->netdev) &&
6b7c5b94 1799 atomic_read(&txq->used) < txq->len / 2) {
5fb379ee
SP		 1800 netif_wake_queue(adapter->netdev);
1801 }
1802
3abcdeda
SP		 1803 tx_stats(adapter)->be_tx_events++;
1804 tx_stats(adapter)->be_tx_compl += tx_compl;
6b7c5b94 1805 }
6b7c5b94
SP		 1806
1807 return 1;
1808}
1809
d053de91 1810void be_detect_dump_ue(struct be_adapter *adapter)
7c185276
AK		 1811{
1812 u32 ue_status_lo, ue_status_hi, ue_status_lo_mask, ue_status_hi_mask;
1813 u32 i;
1814
1815 pci_read_config_dword(adapter->pdev,
1816 PCICFG_UE_STATUS_LOW, &ue_status_lo);
1817 pci_read_config_dword(adapter->pdev,
1818 PCICFG_UE_STATUS_HIGH, &ue_status_hi);
1819 pci_read_config_dword(adapter->pdev,
1820 PCICFG_UE_STATUS_LOW_MASK, &ue_status_lo_mask);
1821 pci_read_config_dword(adapter->pdev,
1822 PCICFG_UE_STATUS_HI_MASK, &ue_status_hi_mask);
1823
1824 ue_status_lo = (ue_status_lo & (~ue_status_lo_mask));
1825 ue_status_hi = (ue_status_hi & (~ue_status_hi_mask));
1826
d053de91
AK		 1827 if (ue_status_lo || ue_status_hi) {
1828 adapter->ue_detected = true;
1829 dev_err(&adapter->pdev->dev, "UE Detected!!\n");
1830 }
1831
7c185276
AK		 1832 if (ue_status_lo) {
1833 for (i = 0; ue_status_lo; ue_status_lo >>= 1, i++) {
1834 if (ue_status_lo & 1)
1835 dev_err(&adapter->pdev->dev,
1836 "UE: %s bit set\n", ue_status_low_desc[i]);
1837 }
1838 }
1839 if (ue_status_hi) {
1840 for (i = 0; ue_status_hi; ue_status_hi >>= 1, i++) {
1841 if (ue_status_hi & 1)
1842 dev_err(&adapter->pdev->dev,
1843 "UE: %s bit set\n", ue_status_hi_desc[i]);
1844 }
1845 }
1846
1847}
1848
ea1dae11
SP		 1849static void be_worker(struct work_struct *work)
1850{
1851 struct be_adapter *adapter =
1852 container_of(work, struct be_adapter, work.work);
3abcdeda
SP		 1853 struct be_rx_obj *rxo;
1854 int i;
ea1dae11 1855
f203af70
SK		 1856 /* when interrupts are not yet enabled, just reap any pending
1857 * mcc completions */
1858 if (!netif_running(adapter->netdev)) {
1859 int mcc_compl, status = 0;
1860
1861 mcc_compl = be_process_mcc(adapter, &status);
1862
1863 if (mcc_compl) {
1864 struct be_mcc_obj *mcc_obj = &adapter->mcc_obj;
1865 be_cq_notify(adapter, mcc_obj->cq.id, false, mcc_compl);
1866 }
1867 goto reschedule;
1868 }
1869
0fc48c37 1870 if (!adapter->stats_ioctl_sent)
3abcdeda 1871 be_cmd_get_stats(adapter, &adapter->stats_cmd);
ea1dae11 1872
4097f663 1873 be_tx_rate_update(adapter);
4097f663 1874
3abcdeda
SP		 1875 for_all_rx_queues(adapter, rxo, i) {
1876 be_rx_rate_update(rxo);
1877 be_rx_eqd_update(adapter, rxo);
1878
1879 if (rxo->rx_post_starved) {
1880 rxo->rx_post_starved = false;
1881 be_post_rx_frags(rxo);
1882 }
ea1dae11 1883 }
fe6d2a38 1884 if (!adapter->ue_detected && !lancer_chip(adapter))
d053de91 1885 be_detect_dump_ue(adapter);
ea1dae11 1886
f203af70 1887reschedule:
ea1dae11
SP		 1888 schedule_delayed_work(&adapter->work, msecs_to_jiffies(1000));
1889}
1890
8d56ff11
SP		 1891static void be_msix_disable(struct be_adapter *adapter)
1892{
1893 if (adapter->msix_enabled) {
1894 pci_disable_msix(adapter->pdev);
1895 adapter->msix_enabled = false;
1896 }
1897}
1898
3abcdeda
SP		 1899static int be_num_rxqs_get(struct be_adapter *adapter)
1900{
1901 if (multi_rxq && (adapter->function_caps & BE_FUNCTION_CAPS_RSS) &&
1902 !adapter->sriov_enabled && !(adapter->function_mode & 0x400)) {
1903 return 1 + MAX_RSS_QS; /* one default non-RSS queue */
1904 } else {
1905 dev_warn(&adapter->pdev->dev,
1906 "No support for multiple RX queues\n");
1907 return 1;
1908 }
1909}
1910
6b7c5b94
SP		 1911static void be_msix_enable(struct be_adapter *adapter)
1912{
3abcdeda 1913#define BE_MIN_MSIX_VECTORS (1 + 1) /* Rx + Tx */
6b7c5b94
SP		 1914 int i, status;
1915
3abcdeda
SP		 1916 adapter->num_rx_qs = be_num_rxqs_get(adapter);
1917
1918 for (i = 0; i < (adapter->num_rx_qs + 1); i++)
6b7c5b94
SP		 1919 adapter->msix_entries[i].entry = i;
1920
1921 status = pci_enable_msix(adapter->pdev, adapter->msix_entries,
3abcdeda
SP		 1922 adapter->num_rx_qs + 1);
1923 if (status == 0) {
1924 goto done;
1925 } else if (status >= BE_MIN_MSIX_VECTORS) {
1926 if (pci_enable_msix(adapter->pdev, adapter->msix_entries,
1927 status) == 0) {
1928 adapter->num_rx_qs = status - 1;
1929 dev_warn(&adapter->pdev->dev,
1930 "Could alloc only %d MSIx vectors. "
1931 "Using %d RX Qs\n", status, adapter->num_rx_qs);
1932 goto done;
1933 }
1934 }
1935 return;
1936done:
1937 adapter->msix_enabled = true;
6b7c5b94
SP		 1938}
1939
ba343c77
SB		 1940static void be_sriov_enable(struct be_adapter *adapter)
1941{
344dbf10 1942 be_check_sriov_fn_type(adapter);
6dedec81 1943#ifdef CONFIG_PCI_IOV
ba343c77 1944 if (be_physfn(adapter) && num_vfs) {
6dedec81
AK		 1945 int status;
1946
ba343c77
SB		 1947 status = pci_enable_sriov(adapter->pdev, num_vfs);
1948 adapter->sriov_enabled = status ? false : true;
1949 }
1950#endif
ba343c77
SB		 1951}
1952
1953static void be_sriov_disable(struct be_adapter *adapter)
1954{
1955#ifdef CONFIG_PCI_IOV
1956 if (adapter->sriov_enabled) {
1957 pci_disable_sriov(adapter->pdev);
1958 adapter->sriov_enabled = false;
1959 }
1960#endif
1961}
1962
fe6d2a38
SP		 1963static inline int be_msix_vec_get(struct be_adapter *adapter,
1964 struct be_eq_obj *eq_obj)
6b7c5b94 1965{
fe6d2a38 1966 return adapter->msix_entries[eq_obj->msix_vec_idx].vector;
6b7c5b94
SP		 1967}
1968
b628bde2
SP		 1969static int be_request_irq(struct be_adapter *adapter,
1970 struct be_eq_obj *eq_obj,
3abcdeda 1971 void *handler, char *desc, void *context)
6b7c5b94
SP		 1972{
1973 struct net_device *netdev = adapter->netdev;
b628bde2
SP		 1974 int vec;
1975
1976 sprintf(eq_obj->desc, "%s-%s", netdev->name, desc);
fe6d2a38 1977 vec = be_msix_vec_get(adapter, eq_obj);
3abcdeda 1978 return request_irq(vec, handler, 0, eq_obj->desc, context);
b628bde2
SP		 1979}
1980
3abcdeda
SP		 1981static void be_free_irq(struct be_adapter *adapter, struct be_eq_obj *eq_obj,
1982 void *context)
b628bde2 1983{
fe6d2a38 1984 int vec = be_msix_vec_get(adapter, eq_obj);
3abcdeda 1985 free_irq(vec, context);
b628bde2 1986}
6b7c5b94 1987
b628bde2
SP		 1988static int be_msix_register(struct be_adapter *adapter)
1989{
3abcdeda
SP		 1990 struct be_rx_obj *rxo;
1991 int status, i;
1992 char qname[10];
b628bde2 1993
3abcdeda
SP		 1994 status = be_request_irq(adapter, &adapter->tx_eq, be_msix_tx_mcc, "tx",
1995 adapter);
6b7c5b94
SP		 1996 if (status)
1997 goto err;
1998
3abcdeda
SP		 1999 for_all_rx_queues(adapter, rxo, i) {
2000 sprintf(qname, "rxq%d", i);
2001 status = be_request_irq(adapter, &rxo->rx_eq, be_msix_rx,
2002 qname, rxo);
2003 if (status)
2004 goto err_msix;
2005 }
b628bde2 2006
6b7c5b94 2007 return 0;
b628bde2 2008
3abcdeda
SP		 2009err_msix:
2010 be_free_irq(adapter, &adapter->tx_eq, adapter);
2011
2012 for (i--, rxo = &adapter->rx_obj[i]; i >= 0; i--, rxo--)
2013 be_free_irq(adapter, &rxo->rx_eq, rxo);
2014
6b7c5b94
SP		 2015err:
2016 dev_warn(&adapter->pdev->dev,
2017 "MSIX Request IRQ failed - err %d\n", status);
2018 pci_disable_msix(adapter->pdev);
2019 adapter->msix_enabled = false;
2020 return status;
2021}
2022
2023static int be_irq_register(struct be_adapter *adapter)
2024{
2025 struct net_device *netdev = adapter->netdev;
2026 int status;
2027
2028 if (adapter->msix_enabled) {
2029 status = be_msix_register(adapter);
2030 if (status == 0)
2031 goto done;
ba343c77
SB		 2032 /* INTx is not supported for VF */
2033 if (!be_physfn(adapter))
2034 return status;
6b7c5b94
SP		 2035 }
2036
2037 /* INTx */
2038 netdev->irq = adapter->pdev->irq;
2039 status = request_irq(netdev->irq, be_intx, IRQF_SHARED, netdev->name,
2040 adapter);
2041 if (status) {
2042 dev_err(&adapter->pdev->dev,
2043 "INTx request IRQ failed - err %d\n", status);
2044 return status;
2045 }
2046done:
2047 adapter->isr_registered = true;
2048 return 0;
2049}
2050
2051static void be_irq_unregister(struct be_adapter *adapter)
2052{
2053 struct net_device *netdev = adapter->netdev;
3abcdeda
SP		 2054 struct be_rx_obj *rxo;
2055 int i;
6b7c5b94
SP		 2056
2057 if (!adapter->isr_registered)
2058 return;
2059
2060 /* INTx */
2061 if (!adapter->msix_enabled) {
2062 free_irq(netdev->irq, adapter);
2063 goto done;
2064 }
2065
2066 /* MSIx */
3abcdeda
SP		 2067 be_free_irq(adapter, &adapter->tx_eq, adapter);
2068
2069 for_all_rx_queues(adapter, rxo, i)
2070 be_free_irq(adapter, &rxo->rx_eq, rxo);
2071
6b7c5b94
SP		 2072done:
2073 adapter->isr_registered = false;
6b7c5b94
SP		 2074}
2075
889cd4b2
SP		 2076static int be_close(struct net_device *netdev)
2077{
2078 struct be_adapter *adapter = netdev_priv(netdev);
3abcdeda 2079 struct be_rx_obj *rxo;
889cd4b2 2080 struct be_eq_obj *tx_eq = &adapter->tx_eq;
3abcdeda 2081 int vec, i;
889cd4b2 2082
889cd4b2
SP		 2083 be_async_mcc_disable(adapter);
2084
2085 netif_stop_queue(netdev);
2086 netif_carrier_off(netdev);
2087 adapter->link_up = false;
2088
fe6d2a38
SP		 2089 if (!lancer_chip(adapter))
2090 be_intr_set(adapter, false);
889cd4b2
SP		 2091
2092 if (adapter->msix_enabled) {
fe6d2a38 2093 vec = be_msix_vec_get(adapter, tx_eq);
889cd4b2 2094 synchronize_irq(vec);
3abcdeda
SP		 2095
2096 for_all_rx_queues(adapter, rxo, i) {
fe6d2a38 2097 vec = be_msix_vec_get(adapter, &rxo->rx_eq);
3abcdeda
SP		 2098 synchronize_irq(vec);
2099 }
889cd4b2
SP		 2100 } else {
2101 synchronize_irq(netdev->irq);
2102 }
2103 be_irq_unregister(adapter);
2104
3abcdeda
SP		 2105 for_all_rx_queues(adapter, rxo, i)
2106 napi_disable(&rxo->rx_eq.napi);
2107
889cd4b2
SP		 2108 napi_disable(&tx_eq->napi);
2109
2110 /* Wait for all pending tx completions to arrive so that
2111 * all tx skbs are freed.
2112 */
2113 be_tx_compl_clean(adapter);
2114
2115 return 0;
2116}
2117
6b7c5b94
SP		 2118static int be_open(struct net_device *netdev)
2119{
2120 struct be_adapter *adapter = netdev_priv(netdev);
6b7c5b94 2121 struct be_eq_obj *tx_eq = &adapter->tx_eq;
3abcdeda 2122 struct be_rx_obj *rxo;
a8f447bd 2123 bool link_up;
3abcdeda 2124 int status, i;
0388f251
SB		 2125 u8 mac_speed;
2126 u16 link_speed;
5fb379ee 2127
3abcdeda
SP		 2128 for_all_rx_queues(adapter, rxo, i) {
2129 be_post_rx_frags(rxo);
2130 napi_enable(&rxo->rx_eq.napi);
2131 }
5fb379ee
SP		 2132 napi_enable(&tx_eq->napi);
2133
2134 be_irq_register(adapter);
2135
fe6d2a38
SP		 2136 if (!lancer_chip(adapter))
2137 be_intr_set(adapter, true);
5fb379ee
SP		 2138
2139 /* The evt queues are created in unarmed state; arm them */
3abcdeda
SP		 2140 for_all_rx_queues(adapter, rxo, i) {
2141 be_eq_notify(adapter, rxo->rx_eq.q.id, true, false, 0);
2142 be_cq_notify(adapter, rxo->cq.id, true, 0);
2143 }
8788fdc2 2144 be_eq_notify(adapter, tx_eq->q.id, true, false, 0);
5fb379ee 2145
7a1e9b20
SP		 2146 /* Now that interrupts are on we can process async mcc */
2147 be_async_mcc_enable(adapter);
2148
0388f251
SB		 2149 status = be_cmd_link_status_query(adapter, &link_up, &mac_speed,
2150 &link_speed);
a8f447bd 2151 if (status)
889cd4b2 2152 goto err;
a8f447bd 2153 be_link_status_update(adapter, link_up);
5fb379ee 2154
889cd4b2 2155 if (be_physfn(adapter)) {
1da87b7f 2156 status = be_vid_config(adapter, false, 0);
889cd4b2
SP		 2157 if (status)
2158 goto err;
4f2aa89c 2159
ba343c77
SB		 2160 status = be_cmd_set_flow_control(adapter,
2161 adapter->tx_fc, adapter->rx_fc);
2162 if (status)
889cd4b2 2163 goto err;
ba343c77 2164 }
4f2aa89c 2165
889cd4b2
SP		 2166 return 0;
2167err:
2168 be_close(adapter->netdev);
2169 return -EIO;
5fb379ee
SP		 2170}
2171
71d8d1b5
AK		 2172static int be_setup_wol(struct be_adapter *adapter, bool enable)
2173{
2174 struct be_dma_mem cmd;
2175 int status = 0;
2176 u8 mac[ETH_ALEN];
2177
2178 memset(mac, 0, ETH_ALEN);
2179
2180 cmd.size = sizeof(struct be_cmd_req_acpi_wol_magic_config);
2b7bcebf
IV		 2181 cmd.va = dma_alloc_coherent(&adapter->pdev->dev, cmd.size, &cmd.dma,
2182 GFP_KERNEL);
71d8d1b5
AK		 2183 if (cmd.va == NULL)
2184 return -1;
2185 memset(cmd.va, 0, cmd.size);
2186
2187 if (enable) {
2188 status = pci_write_config_dword(adapter->pdev,
2189 PCICFG_PM_CONTROL_OFFSET, PCICFG_PM_CONTROL_MASK);
2190 if (status) {
2191 dev_err(&adapter->pdev->dev,
2381a55c 2192 "Could not enable Wake-on-lan\n");
2b7bcebf
IV		 2193 dma_free_coherent(&adapter->pdev->dev, cmd.size, cmd.va,
2194 cmd.dma);
71d8d1b5
AK		 2195 return status;
2196 }
2197 status = be_cmd_enable_magic_wol(adapter,
2198 adapter->netdev->dev_addr, &cmd);
2199 pci_enable_wake(adapter->pdev, PCI_D3hot, 1);
2200 pci_enable_wake(adapter->pdev, PCI_D3cold, 1);
2201 } else {
2202 status = be_cmd_enable_magic_wol(adapter, mac, &cmd);
2203 pci_enable_wake(adapter->pdev, PCI_D3hot, 0);
2204 pci_enable_wake(adapter->pdev, PCI_D3cold, 0);
2205 }
2206
2b7bcebf 2207 dma_free_coherent(&adapter->pdev->dev, cmd.size, cmd.va, cmd.dma);
71d8d1b5
AK		 2208 return status;
2209}
2210
6d87f5c3
AK		 2211/*
2212 * Generate a seed MAC address from the PF MAC Address using jhash.
2213 * MAC Address for VFs are assigned incrementally starting from the seed.
2214 * These addresses are programmed in the ASIC by the PF and the VF driver
2215 * queries for the MAC address during its probe.
2216 */
2217static inline int be_vf_eth_addr_config(struct be_adapter *adapter)
2218{
2219 u32 vf = 0;
3abcdeda 2220 int status = 0;
6d87f5c3
AK		 2221 u8 mac[ETH_ALEN];
2222
2223 be_vf_eth_addr_generate(adapter, mac);
2224
2225 for (vf = 0; vf < num_vfs; vf++) {
2226 status = be_cmd_pmac_add(adapter, mac,
2227 adapter->vf_cfg[vf].vf_if_handle,
2228 &adapter->vf_cfg[vf].vf_pmac_id);
2229 if (status)
2230 dev_err(&adapter->pdev->dev,
2231 "Mac address add failed for VF %d\n", vf);
2232 else
2233 memcpy(adapter->vf_cfg[vf].vf_mac_addr, mac, ETH_ALEN);
2234
2235 mac[5] += 1;
2236 }
2237 return status;
2238}
2239
2240static inline void be_vf_eth_addr_rem(struct be_adapter *adapter)
2241{
2242 u32 vf;
2243
2244 for (vf = 0; vf < num_vfs; vf++) {
2245 if (adapter->vf_cfg[vf].vf_pmac_id != BE_INVALID_PMAC_ID)
2246 be_cmd_pmac_del(adapter,
2247 adapter->vf_cfg[vf].vf_if_handle,
2248 adapter->vf_cfg[vf].vf_pmac_id);
2249 }
2250}
2251
5fb379ee
SP		 2252static int be_setup(struct be_adapter *adapter)
2253{
5fb379ee 2254 struct net_device *netdev = adapter->netdev;
ba343c77 2255 u32 cap_flags, en_flags, vf = 0;
6b7c5b94 2256 int status;
ba343c77
SB		 2257 u8 mac[ETH_ALEN];
2258
2259 cap_flags = en_flags = BE_IF_FLAGS_UNTAGGED | BE_IF_FLAGS_BROADCAST;
6b7c5b94 2260
ba343c77
SB		 2261 if (be_physfn(adapter)) {
2262 cap_flags |= BE_IF_FLAGS_MCAST_PROMISCUOUS |
2263 BE_IF_FLAGS_PROMISCUOUS |
2264 BE_IF_FLAGS_PASS_L3L4_ERRORS;
2265 en_flags |= BE_IF_FLAGS_PASS_L3L4_ERRORS;
3abcdeda
SP		 2266
2267 if (be_multi_rxq(adapter)) {
2268 cap_flags |= BE_IF_FLAGS_RSS;
2269 en_flags |= BE_IF_FLAGS_RSS;
2270 }
ba343c77 2271 }
73d540f2
SP		 2272
2273 status = be_cmd_if_create(adapter, cap_flags, en_flags,
2274 netdev->dev_addr, false/* pmac_invalid */,
ba343c77 2275 &adapter->if_handle, &adapter->pmac_id, 0);
6b7c5b94
SP		 2276 if (status != 0)
2277 goto do_none;
2278
ba343c77 2279 if (be_physfn(adapter)) {
c99ac3e7
AK		 2280 if (adapter->sriov_enabled) {
2281 while (vf < num_vfs) {
2282 cap_flags = en_flags = BE_IF_FLAGS_UNTAGGED |
2283 BE_IF_FLAGS_BROADCAST;
2284 status = be_cmd_if_create(adapter, cap_flags,
2285 en_flags, mac, true,
64600ea5 2286 &adapter->vf_cfg[vf].vf_if_handle,
ba343c77 2287 NULL, vf+1);
c99ac3e7
AK		 2288 if (status) {
2289 dev_err(&adapter->pdev->dev,
2290 "Interface Create failed for VF %d\n",
2291 vf);
2292 goto if_destroy;
2293 }
2294 adapter->vf_cfg[vf].vf_pmac_id =
2295 BE_INVALID_PMAC_ID;
2296 vf++;
ba343c77 2297 }
84e5b9f7 2298 }
c99ac3e7 2299 } else {
ba343c77
SB		 2300 status = be_cmd_mac_addr_query(adapter, mac,
2301 MAC_ADDRESS_TYPE_NETWORK, false, adapter->if_handle);
2302 if (!status) {
2303 memcpy(adapter->netdev->dev_addr, mac, ETH_ALEN);
2304 memcpy(adapter->netdev->perm_addr, mac, ETH_ALEN);
2305 }
2306 }
2307
6b7c5b94
SP		 2308 status = be_tx_queues_create(adapter);
2309 if (status != 0)
2310 goto if_destroy;
2311
2312 status = be_rx_queues_create(adapter);
2313 if (status != 0)
2314 goto tx_qs_destroy;
2315
5fb379ee
SP		 2316 status = be_mcc_queues_create(adapter);
2317 if (status != 0)
2318 goto rx_qs_destroy;
6b7c5b94 2319
0dffc83e
AK		 2320 adapter->link_speed = -1;
2321
6b7c5b94
SP		 2322 return 0;
2323
6d87f5c3 2324 be_mcc_queues_destroy(adapter);
5fb379ee
SP		 2325rx_qs_destroy:
2326 be_rx_queues_destroy(adapter);
6b7c5b94
SP		 2327tx_qs_destroy:
2328 be_tx_queues_destroy(adapter);
2329if_destroy:
c99ac3e7
AK		 2330 if (be_physfn(adapter) && adapter->sriov_enabled)
2331 for (vf = 0; vf < num_vfs; vf++)
2332 if (adapter->vf_cfg[vf].vf_if_handle)
2333 be_cmd_if_destroy(adapter,
658681f7
AK		 2334 adapter->vf_cfg[vf].vf_if_handle,
2335 vf + 1);
2336 be_cmd_if_destroy(adapter, adapter->if_handle, 0);
6b7c5b94
SP		 2337do_none:
2338 return status;
2339}
2340
5fb379ee
SP		 2341static int be_clear(struct be_adapter *adapter)
2342{
c99ac3e7 2343 if (be_physfn(adapter) && adapter->sriov_enabled)
6d87f5c3
AK		 2344 be_vf_eth_addr_rem(adapter);
2345
1a8887d8 2346 be_mcc_queues_destroy(adapter);
5fb379ee
SP		 2347 be_rx_queues_destroy(adapter);
2348 be_tx_queues_destroy(adapter);
2349
658681f7 2350 be_cmd_if_destroy(adapter, adapter->if_handle, 0);
5fb379ee 2351
2243e2e9
SP		 2352 /* tell fw we're done with firing cmds */
2353 be_cmd_fw_clean(adapter);
5fb379ee
SP		 2354 return 0;
2355}
2356
6b7c5b94 2357
84517482 2358#define FW_FILE_HDR_SIGN "ServerEngines Corp. "
fa9a6fed 2359static bool be_flash_redboot(struct be_adapter *adapter,
3f0d4560
AK		 2360 const u8 *p, u32 img_start, int image_size,
2361 int hdr_size)
fa9a6fed
SB		 2362{
2363 u32 crc_offset;
2364 u8 flashed_crc[4];
2365 int status;
3f0d4560
AK		 2366
2367 crc_offset = hdr_size + img_start + image_size - 4;
2368
fa9a6fed 2369 p += crc_offset;
3f0d4560
AK		 2370
2371 status = be_cmd_get_flash_crc(adapter, flashed_crc,
f510fc64 2372 (image_size - 4));
fa9a6fed
SB		 2373 if (status) {
2374 dev_err(&adapter->pdev->dev,
2375 "could not get crc from flash, not flashing redboot\n");
2376 return false;
2377 }
2378
2379 /*update redboot only if crc does not match*/
2380 if (!memcmp(flashed_crc, p, 4))
2381 return false;
2382 else
2383 return true;
fa9a6fed
SB		 2384}
2385
3f0d4560 2386static int be_flash_data(struct be_adapter *adapter,
84517482 2387 const struct firmware *fw,
3f0d4560
AK		 2388 struct be_dma_mem *flash_cmd, int num_of_images)
2389
84517482 2390{
3f0d4560
AK		 2391 int status = 0, i, filehdr_size = 0;
2392 u32 total_bytes = 0, flash_op;
84517482
AK		 2393 int num_bytes;
2394 const u8 *p = fw->data;
2395 struct be_cmd_write_flashrom *req = flash_cmd->va;
215faf9c 2396 const struct flash_comp *pflashcomp;
9fe96934 2397 int num_comp;
3f0d4560 2398
215faf9c 2399 static const struct flash_comp gen3_flash_types[9] = {
3f0d4560
AK		 2400 { FLASH_iSCSI_PRIMARY_IMAGE_START_g3, IMG_TYPE_ISCSI_ACTIVE,
2401 FLASH_IMAGE_MAX_SIZE_g3},
2402 { FLASH_REDBOOT_START_g3, IMG_TYPE_REDBOOT,
2403 FLASH_REDBOOT_IMAGE_MAX_SIZE_g3},
2404 { FLASH_iSCSI_BIOS_START_g3, IMG_TYPE_BIOS,
2405 FLASH_BIOS_IMAGE_MAX_SIZE_g3},
2406 { FLASH_PXE_BIOS_START_g3, IMG_TYPE_PXE_BIOS,
2407 FLASH_BIOS_IMAGE_MAX_SIZE_g3},
2408 { FLASH_FCoE_BIOS_START_g3, IMG_TYPE_FCOE_BIOS,
2409 FLASH_BIOS_IMAGE_MAX_SIZE_g3},
2410 { FLASH_iSCSI_BACKUP_IMAGE_START_g3, IMG_TYPE_ISCSI_BACKUP,
2411 FLASH_IMAGE_MAX_SIZE_g3},
2412 { FLASH_FCoE_PRIMARY_IMAGE_START_g3, IMG_TYPE_FCOE_FW_ACTIVE,
2413 FLASH_IMAGE_MAX_SIZE_g3},
2414 { FLASH_FCoE_BACKUP_IMAGE_START_g3, IMG_TYPE_FCOE_FW_BACKUP,
9fe96934
SB		 2415 FLASH_IMAGE_MAX_SIZE_g3},
2416 { FLASH_NCSI_START_g3, IMG_TYPE_NCSI_FW,
2417 FLASH_NCSI_IMAGE_MAX_SIZE_g3}
3f0d4560 2418 };
215faf9c 2419 static const struct flash_comp gen2_flash_types[8] = {
3f0d4560
AK		 2420 { FLASH_iSCSI_PRIMARY_IMAGE_START_g2, IMG_TYPE_ISCSI_ACTIVE,
2421 FLASH_IMAGE_MAX_SIZE_g2},
2422 { FLASH_REDBOOT_START_g2, IMG_TYPE_REDBOOT,
2423 FLASH_REDBOOT_IMAGE_MAX_SIZE_g2},
2424 { FLASH_iSCSI_BIOS_START_g2, IMG_TYPE_BIOS,
2425 FLASH_BIOS_IMAGE_MAX_SIZE_g2},
2426 { FLASH_PXE_BIOS_START_g2, IMG_TYPE_PXE_BIOS,
2427 FLASH_BIOS_IMAGE_MAX_SIZE_g2},
2428 { FLASH_FCoE_BIOS_START_g2, IMG_TYPE_FCOE_BIOS,
2429 FLASH_BIOS_IMAGE_MAX_SIZE_g2},
2430 { FLASH_iSCSI_BACKUP_IMAGE_START_g2, IMG_TYPE_ISCSI_BACKUP,
2431 FLASH_IMAGE_MAX_SIZE_g2},
2432 { FLASH_FCoE_PRIMARY_IMAGE_START_g2, IMG_TYPE_FCOE_FW_ACTIVE,
2433 FLASH_IMAGE_MAX_SIZE_g2},
2434 { FLASH_FCoE_BACKUP_IMAGE_START_g2, IMG_TYPE_FCOE_FW_BACKUP,
2435 FLASH_IMAGE_MAX_SIZE_g2}
2436 };
2437
2438 if (adapter->generation == BE_GEN3) {
2439 pflashcomp = gen3_flash_types;
2440 filehdr_size = sizeof(struct flash_file_hdr_g3);
215faf9c 2441 num_comp = ARRAY_SIZE(gen3_flash_types);
3f0d4560
AK		 2442 } else {
2443 pflashcomp = gen2_flash_types;
2444 filehdr_size = sizeof(struct flash_file_hdr_g2);
215faf9c 2445 num_comp = ARRAY_SIZE(gen2_flash_types);
84517482 2446 }
9fe96934
SB		 2447 for (i = 0; i < num_comp; i++) {
2448 if ((pflashcomp[i].optype == IMG_TYPE_NCSI_FW) &&
2449 memcmp(adapter->fw_ver, "3.102.148.0", 11) < 0)
2450 continue;
3f0d4560
AK		 2451 if ((pflashcomp[i].optype == IMG_TYPE_REDBOOT) &&
2452 (!be_flash_redboot(adapter, fw->data,
2453 pflashcomp[i].offset, pflashcomp[i].size,
2454 filehdr_size)))
2455 continue;
2456 p = fw->data;
2457 p += filehdr_size + pflashcomp[i].offset
2458 + (num_of_images * sizeof(struct image_hdr));
2459 if (p + pflashcomp[i].size > fw->data + fw->size)
84517482 2460 return -1;
3f0d4560
AK		 2461 total_bytes = pflashcomp[i].size;
2462 while (total_bytes) {
2463 if (total_bytes > 32*1024)
2464 num_bytes = 32*1024;
2465 else
2466 num_bytes = total_bytes;
2467 total_bytes -= num_bytes;
2468
2469 if (!total_bytes)
2470 flash_op = FLASHROM_OPER_FLASH;
2471 else
2472 flash_op = FLASHROM_OPER_SAVE;
2473 memcpy(req->params.data_buf, p, num_bytes);
2474 p += num_bytes;
2475 status = be_cmd_write_flashrom(adapter, flash_cmd,
2476 pflashcomp[i].optype, flash_op, num_bytes);
2477 if (status) {
2478 dev_err(&adapter->pdev->dev,
2479 "cmd to write to flash rom failed.\n");
2480 return -1;
2481 }
2482 yield();
84517482 2483 }
84517482 2484 }
84517482
AK		 2485 return 0;
2486}
2487
3f0d4560
AK		 2488static int get_ufigen_type(struct flash_file_hdr_g2 *fhdr)
2489{
2490 if (fhdr == NULL)
2491 return 0;
2492 if (fhdr->build[0] == '3')
2493 return BE_GEN3;
2494 else if (fhdr->build[0] == '2')
2495 return BE_GEN2;
2496 else
2497 return 0;
2498}
2499
84517482
AK		 2500int be_load_fw(struct be_adapter *adapter, u8 *func)
2501{
2502 char fw_file[ETHTOOL_FLASH_MAX_FILENAME];
2503 const struct firmware *fw;
3f0d4560
AK		 2504 struct flash_file_hdr_g2 *fhdr;
2505 struct flash_file_hdr_g3 *fhdr3;
2506 struct image_hdr *img_hdr_ptr = NULL;
84517482 2507 struct be_dma_mem flash_cmd;
8b93b710 2508 int status, i = 0, num_imgs = 0;
84517482 2509 const u8 *p;
84517482 2510
d9efd2af
SB		 2511 if (!netif_running(adapter->netdev)) {
2512 dev_err(&adapter->pdev->dev,
2513 "Firmware load not allowed (interface is down)\n");
2514 return -EPERM;
2515 }
2516
84517482
AK		 2517 strcpy(fw_file, func);
2518
2519 status = request_firmware(&fw, fw_file, &adapter->pdev->dev);
2520 if (status)
2521 goto fw_exit;
2522
2523 p = fw->data;
3f0d4560 2524 fhdr = (struct flash_file_hdr_g2 *) p;
84517482
AK		 2525 dev_info(&adapter->pdev->dev, "Flashing firmware file %s\n", fw_file);
2526
84517482 2527 flash_cmd.size = sizeof(struct be_cmd_write_flashrom) + 32*1024;
2b7bcebf
IV		 2528 flash_cmd.va = dma_alloc_coherent(&adapter->pdev->dev, flash_cmd.size,
2529 &flash_cmd.dma, GFP_KERNEL);
84517482
AK		 2530 if (!flash_cmd.va) {
2531 status = -ENOMEM;
2532 dev_err(&adapter->pdev->dev,
2533 "Memory allocation failure while flashing\n");
2534 goto fw_exit;
2535 }
2536
3f0d4560
AK		 2537 if ((adapter->generation == BE_GEN3) &&
2538 (get_ufigen_type(fhdr) == BE_GEN3)) {
2539 fhdr3 = (struct flash_file_hdr_g3 *) fw->data;
8b93b710
AK		 2540 num_imgs = le32_to_cpu(fhdr3->num_imgs);
2541 for (i = 0; i < num_imgs; i++) {
3f0d4560
AK		 2542 img_hdr_ptr = (struct image_hdr *) (fw->data +
2543 (sizeof(struct flash_file_hdr_g3) +
8b93b710
AK		 2544 i * sizeof(struct image_hdr)));
2545 if (le32_to_cpu(img_hdr_ptr->imageid) == 1)
2546 status = be_flash_data(adapter, fw, &flash_cmd,
2547 num_imgs);
3f0d4560
AK		 2548 }
2549 } else if ((adapter->generation == BE_GEN2) &&
2550 (get_ufigen_type(fhdr) == BE_GEN2)) {
2551 status = be_flash_data(adapter, fw, &flash_cmd, 0);
2552 } else {
2553 dev_err(&adapter->pdev->dev,
2554 "UFI and Interface are not compatible for flashing\n");
2555 status = -1;
84517482
AK		 2556 }
2557
2b7bcebf
IV		 2558 dma_free_coherent(&adapter->pdev->dev, flash_cmd.size, flash_cmd.va,
2559 flash_cmd.dma);
84517482
AK		 2560 if (status) {
2561 dev_err(&adapter->pdev->dev, "Firmware load error\n");
2562 goto fw_exit;
2563 }
2564
af901ca1 2565 dev_info(&adapter->pdev->dev, "Firmware flashed successfully\n");
84517482
AK		 2566
2567fw_exit:
2568 release_firmware(fw);
2569 return status;
2570}
2571
6b7c5b94
SP		 2572static struct net_device_ops be_netdev_ops = {
2573 .ndo_open = be_open,
2574 .ndo_stop = be_close,
2575 .ndo_start_xmit = be_xmit,
6b7c5b94
SP		 2576 .ndo_set_rx_mode = be_set_multicast_list,
2577 .ndo_set_mac_address = be_mac_addr_set,
2578 .ndo_change_mtu = be_change_mtu,
2579 .ndo_validate_addr = eth_validate_addr,
2580 .ndo_vlan_rx_register = be_vlan_register,
2581 .ndo_vlan_rx_add_vid = be_vlan_add_vid,
2582 .ndo_vlan_rx_kill_vid = be_vlan_rem_vid,
64600ea5 2583 .ndo_set_vf_mac = be_set_vf_mac,
1da87b7f 2584 .ndo_set_vf_vlan = be_set_vf_vlan,
e1d18735 2585 .ndo_set_vf_tx_rate = be_set_vf_tx_rate,
64600ea5 2586 .ndo_get_vf_config = be_get_vf_config
6b7c5b94
SP		 2587};
2588
2589static void be_netdev_init(struct net_device *netdev)
2590{
2591 struct be_adapter *adapter = netdev_priv(netdev);
3abcdeda
SP		 2592 struct be_rx_obj *rxo;
2593 int i;
6b7c5b94
SP		 2594
2595 netdev->features |= NETIF_F_SG | NETIF_F_HW_VLAN_RX | NETIF_F_TSO |
79032644
MM		 2596 NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_FILTER |
2597 NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
49e4b847 2598 NETIF_F_GRO | NETIF_F_TSO6;
6b7c5b94 2599
79032644
MM		 2600 netdev->vlan_features |= NETIF_F_SG | NETIF_F_TSO |
2601 NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM;
51c59870 2602
fe6d2a38
SP		 2603 if (lancer_chip(adapter))
2604 netdev->vlan_features |= NETIF_F_TSO6;
2605
6b7c5b94
SP		 2606 netdev->flags |= IFF_MULTICAST;
2607
728a9972
AK		 2608 adapter->rx_csum = true;
2609
9e90c961
AK		 2610 /* Default settings for Rx and Tx flow control */
2611 adapter->rx_fc = true;
2612 adapter->tx_fc = true;
2613
c190e3c8
AK		 2614 netif_set_gso_max_size(netdev, 65535);
2615
6b7c5b94
SP		 2616 BE_SET_NETDEV_OPS(netdev, &be_netdev_ops);
2617
2618 SET_ETHTOOL_OPS(netdev, &be_ethtool_ops);
2619
3abcdeda
SP		 2620 for_all_rx_queues(adapter, rxo, i)
2621 netif_napi_add(netdev, &rxo->rx_eq.napi, be_poll_rx,
2622 BE_NAPI_WEIGHT);
2623
5fb379ee 2624 netif_napi_add(netdev, &adapter->tx_eq.napi, be_poll_tx_mcc,
6b7c5b94 2625 BE_NAPI_WEIGHT);
6b7c5b94
SP		 2626}
2627
2628static void be_unmap_pci_bars(struct be_adapter *adapter)
2629{
8788fdc2
SP		 2630 if (adapter->csr)
2631 iounmap(adapter->csr);
2632 if (adapter->db)
2633 iounmap(adapter->db);
ba343c77 2634 if (adapter->pcicfg && be_physfn(adapter))
8788fdc2 2635 iounmap(adapter->pcicfg);
6b7c5b94
SP		 2636}
2637
2638static int be_map_pci_bars(struct be_adapter *adapter)
2639{
2640 u8 __iomem *addr;
ba343c77 2641 int pcicfg_reg, db_reg;
6b7c5b94 2642
fe6d2a38
SP		 2643 if (lancer_chip(adapter)) {
2644 addr = ioremap_nocache(pci_resource_start(adapter->pdev, 0),
2645 pci_resource_len(adapter->pdev, 0));
2646 if (addr == NULL)
2647 return -ENOMEM;
2648 adapter->db = addr;
2649 return 0;
2650 }
2651
ba343c77
SB		 2652 if (be_physfn(adapter)) {
2653 addr = ioremap_nocache(pci_resource_start(adapter->pdev, 2),
2654 pci_resource_len(adapter->pdev, 2));
2655 if (addr == NULL)
2656 return -ENOMEM;
2657 adapter->csr = addr;
2658 }
6b7c5b94 2659
ba343c77 2660 if (adapter->generation == BE_GEN2) {
7b139c83 2661 pcicfg_reg = 1;
ba343c77
SB		 2662 db_reg = 4;
2663 } else {
7b139c83 2664 pcicfg_reg = 0;
ba343c77
SB		 2665 if (be_physfn(adapter))
2666 db_reg = 4;
2667 else
2668 db_reg = 0;
2669 }
2670 addr = ioremap_nocache(pci_resource_start(adapter->pdev, db_reg),
2671 pci_resource_len(adapter->pdev, db_reg));
6b7c5b94
SP		 2672 if (addr == NULL)
2673 goto pci_map_err;
ba343c77
SB		 2674 adapter->db = addr;
2675
2676 if (be_physfn(adapter)) {
2677 addr = ioremap_nocache(
2678 pci_resource_start(adapter->pdev, pcicfg_reg),
2679 pci_resource_len(adapter->pdev, pcicfg_reg));
2680 if (addr == NULL)
2681 goto pci_map_err;
2682 adapter->pcicfg = addr;
2683 } else
2684 adapter->pcicfg = adapter->db + SRIOV_VF_PCICFG_OFFSET;
6b7c5b94
SP		 2685
2686 return 0;
2687pci_map_err:
2688 be_unmap_pci_bars(adapter);
2689 return -ENOMEM;
2690}
2691
2692
2693static void be_ctrl_cleanup(struct be_adapter *adapter)
2694{
8788fdc2 2695 struct be_dma_mem *mem = &adapter->mbox_mem_alloced;
6b7c5b94
SP		 2696
2697 be_unmap_pci_bars(adapter);
2698
2699 if (mem->va)
2b7bcebf
IV		 2700 dma_free_coherent(&adapter->pdev->dev, mem->size, mem->va,
2701 mem->dma);
e7b909a6
SP		 2702
2703 mem = &adapter->mc_cmd_mem;
2704 if (mem->va)
2b7bcebf
IV		 2705 dma_free_coherent(&adapter->pdev->dev, mem->size, mem->va,
2706 mem->dma);
6b7c5b94
SP		 2707}
2708
6b7c5b94
SP		 2709static int be_ctrl_init(struct be_adapter *adapter)
2710{
8788fdc2
SP		 2711 struct be_dma_mem *mbox_mem_alloc = &adapter->mbox_mem_alloced;
2712 struct be_dma_mem *mbox_mem_align = &adapter->mbox_mem;
e7b909a6 2713 struct be_dma_mem *mc_cmd_mem = &adapter->mc_cmd_mem;
6b7c5b94 2714 int status;
6b7c5b94
SP		 2715
2716 status = be_map_pci_bars(adapter);
2717 if (status)
e7b909a6 2718 goto done;
6b7c5b94
SP		 2719
2720 mbox_mem_alloc->size = sizeof(struct be_mcc_mailbox) + 16;
2b7bcebf
IV		 2721 mbox_mem_alloc->va = dma_alloc_coherent(&adapter->pdev->dev,
2722 mbox_mem_alloc->size,
2723 &mbox_mem_alloc->dma,
2724 GFP_KERNEL);
6b7c5b94 2725 if (!mbox_mem_alloc->va) {
e7b909a6
SP		 2726 status = -ENOMEM;
2727 goto unmap_pci_bars;
6b7c5b94 2728 }
e7b909a6 2729
6b7c5b94
SP		 2730 mbox_mem_align->size = sizeof(struct be_mcc_mailbox);
2731 mbox_mem_align->va = PTR_ALIGN(mbox_mem_alloc->va, 16);
2732 mbox_mem_align->dma = PTR_ALIGN(mbox_mem_alloc->dma, 16);
2733 memset(mbox_mem_align->va, 0, sizeof(struct be_mcc_mailbox));
e7b909a6
SP		 2734
2735 mc_cmd_mem->size = sizeof(struct be_cmd_req_mcast_mac_config);
2b7bcebf
IV		 2736 mc_cmd_mem->va = dma_alloc_coherent(&adapter->pdev->dev,
2737 mc_cmd_mem->size, &mc_cmd_mem->dma,
2738 GFP_KERNEL);
e7b909a6
SP		 2739 if (mc_cmd_mem->va == NULL) {
2740 status = -ENOMEM;
2741 goto free_mbox;
2742 }
2743 memset(mc_cmd_mem->va, 0, mc_cmd_mem->size);
2744
2984961c 2745 mutex_init(&adapter->mbox_lock);
8788fdc2
SP		 2746 spin_lock_init(&adapter->mcc_lock);
2747 spin_lock_init(&adapter->mcc_cq_lock);
a8f447bd 2748
dd131e76 2749 init_completion(&adapter->flash_compl);
cf588477 2750 pci_save_state(adapter->pdev);
6b7c5b94 2751 return 0;
e7b909a6
SP		 2752
2753free_mbox:
2b7bcebf
IV		 2754 dma_free_coherent(&adapter->pdev->dev, mbox_mem_alloc->size,
2755 mbox_mem_alloc->va, mbox_mem_alloc->dma);
e7b909a6
SP		 2756
2757unmap_pci_bars:
2758 be_unmap_pci_bars(adapter);
2759
2760done:
2761 return status;
6b7c5b94
SP		 2762}
2763
2764static void be_stats_cleanup(struct be_adapter *adapter)
2765{
3abcdeda 2766 struct be_dma_mem *cmd = &adapter->stats_cmd;
6b7c5b94
SP		 2767
2768 if (cmd->va)
2b7bcebf
IV		 2769 dma_free_coherent(&adapter->pdev->dev, cmd->size,
2770 cmd->va, cmd->dma);
6b7c5b94
SP		 2771}
2772
2773static int be_stats_init(struct be_adapter *adapter)
2774{
3abcdeda 2775 struct be_dma_mem *cmd = &adapter->stats_cmd;
6b7c5b94
SP		 2776
2777 cmd->size = sizeof(struct be_cmd_req_get_stats);
2b7bcebf
IV		 2778 cmd->va = dma_alloc_coherent(&adapter->pdev->dev, cmd->size, &cmd->dma,
2779 GFP_KERNEL);
6b7c5b94
SP		 2780 if (cmd->va == NULL)
2781 return -1;
d291b9af 2782 memset(cmd->va, 0, cmd->size);
6b7c5b94
SP		 2783 return 0;
2784}
2785
2786static void __devexit be_remove(struct pci_dev *pdev)
2787{
2788 struct be_adapter *adapter = pci_get_drvdata(pdev);
8d56ff11 2789
6b7c5b94
SP		 2790 if (!adapter)
2791 return;
2792
f203af70
SK		 2793 cancel_delayed_work_sync(&adapter->work);
2794
6b7c5b94
SP		 2795 unregister_netdev(adapter->netdev);
2796
5fb379ee
SP		 2797 be_clear(adapter);
2798
6b7c5b94
SP		 2799 be_stats_cleanup(adapter);
2800
2801 be_ctrl_cleanup(adapter);
2802
ba343c77
SB		 2803 be_sriov_disable(adapter);
2804
8d56ff11 2805 be_msix_disable(adapter);
6b7c5b94
SP		 2806
2807 pci_set_drvdata(pdev, NULL);
2808 pci_release_regions(pdev);
2809 pci_disable_device(pdev);
2810
2811 free_netdev(adapter->netdev);
2812}
2813
2243e2e9 2814static int be_get_config(struct be_adapter *adapter)
6b7c5b94 2815{
6b7c5b94 2816 int status;
2243e2e9 2817 u8 mac[ETH_ALEN];
6b7c5b94 2818
2243e2e9 2819 status = be_cmd_get_fw_ver(adapter, adapter->fw_ver);
6b7c5b94
SP		 2820 if (status)
2821 return status;
2822
3abcdeda
SP		 2823 status = be_cmd_query_fw_cfg(adapter, &adapter->port_num,
2824 &adapter->function_mode, &adapter->function_caps);
43a04fdc
SP		 2825 if (status)
2826 return status;
2827
2243e2e9 2828 memset(mac, 0, ETH_ALEN);
ba343c77
SB		 2829
2830 if (be_physfn(adapter)) {
2831 status = be_cmd_mac_addr_query(adapter, mac,
2243e2e9 2832 MAC_ADDRESS_TYPE_NETWORK, true /*permanent */, 0);
ca9e4988 2833
ba343c77
SB		 2834 if (status)
2835 return status;
ca9e4988 2836
ba343c77
SB		 2837 if (!is_valid_ether_addr(mac))
2838 return -EADDRNOTAVAIL;
2839
2840 memcpy(adapter->netdev->dev_addr, mac, ETH_ALEN);
2841 memcpy(adapter->netdev->perm_addr, mac, ETH_ALEN);
2842 }
6b7c5b94 2843
3486be29 2844 if (adapter->function_mode & 0x400)
82903e4b
AK		 2845 adapter->max_vlans = BE_NUM_VLANS_SUPPORTED/4;
2846 else
2847 adapter->max_vlans = BE_NUM_VLANS_SUPPORTED;
2848
2243e2e9 2849 return 0;
6b7c5b94
SP		 2850}
2851
fe6d2a38
SP		 2852static int be_dev_family_check(struct be_adapter *adapter)
2853{
2854 struct pci_dev *pdev = adapter->pdev;
2855 u32 sli_intf = 0, if_type;
2856
2857 switch (pdev->device) {
2858 case BE_DEVICE_ID1:
2859 case OC_DEVICE_ID1:
2860 adapter->generation = BE_GEN2;
2861 break;
2862 case BE_DEVICE_ID2:
2863 case OC_DEVICE_ID2:
2864 adapter->generation = BE_GEN3;
2865 break;
2866 case OC_DEVICE_ID3:
2867 pci_read_config_dword(pdev, SLI_INTF_REG_OFFSET, &sli_intf);
2868 if_type = (sli_intf & SLI_INTF_IF_TYPE_MASK) >>
2869 SLI_INTF_IF_TYPE_SHIFT;
2870
2871 if (((sli_intf & SLI_INTF_VALID_MASK) != SLI_INTF_VALID) ||
2872 if_type != 0x02) {
2873 dev_err(&pdev->dev, "SLI_INTF reg val is not valid\n");
2874 return -EINVAL;
2875 }
2876 if (num_vfs > 0) {
2877 dev_err(&pdev->dev, "VFs not supported\n");
2878 return -EINVAL;
2879 }
2880 adapter->sli_family = ((sli_intf & SLI_INTF_FAMILY_MASK) >>
2881 SLI_INTF_FAMILY_SHIFT);
2882 adapter->generation = BE_GEN3;
2883 break;
2884 default:
2885 adapter->generation = 0;
2886 }
2887 return 0;
2888}
2889
6b7c5b94
SP		 2890static int __devinit be_probe(struct pci_dev *pdev,
2891 const struct pci_device_id *pdev_id)
2892{
2893 int status = 0;
2894 struct be_adapter *adapter;
2895 struct net_device *netdev;
6b7c5b94
SP		 2896
2897 status = pci_enable_device(pdev);
2898 if (status)
2899 goto do_none;
2900
2901 status = pci_request_regions(pdev, DRV_NAME);
2902 if (status)
2903 goto disable_dev;
2904 pci_set_master(pdev);
2905
2906 netdev = alloc_etherdev(sizeof(struct be_adapter));
2907 if (netdev == NULL) {
2908 status = -ENOMEM;
2909 goto rel_reg;
2910 }
2911 adapter = netdev_priv(netdev);
2912 adapter->pdev = pdev;
2913 pci_set_drvdata(pdev, adapter);
fe6d2a38
SP		 2914
2915 status = be_dev_family_check(adapter);
63657b9c 2916 if (status)
fe6d2a38
SP		 2917 goto free_netdev;
2918
6b7c5b94 2919 adapter->netdev = netdev;
2243e2e9 2920 SET_NETDEV_DEV(netdev, &pdev->dev);
6b7c5b94 2921
2b7bcebf 2922 status = dma_set_mask(&pdev->dev, DMA_BIT_MASK(64));
6b7c5b94
SP		 2923 if (!status) {
2924 netdev->features |= NETIF_F_HIGHDMA;
2925 } else {
2b7bcebf 2926 status = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
6b7c5b94
SP		 2927 if (status) {
2928 dev_err(&pdev->dev, "Could not set PCI DMA Mask\n");
2929 goto free_netdev;
2930 }
2931 }
2932
ba343c77
SB		 2933 be_sriov_enable(adapter);
2934
6b7c5b94
SP		 2935 status = be_ctrl_init(adapter);
2936 if (status)
2937 goto free_netdev;
2938
2243e2e9 2939 /* sync up with fw's ready state */
ba343c77
SB		 2940 if (be_physfn(adapter)) {
2941 status = be_cmd_POST(adapter);
2942 if (status)
2943 goto ctrl_clean;
ba343c77 2944 }
6b7c5b94 2945
2243e2e9
SP		 2946 /* tell fw we're ready to fire cmds */
2947 status = be_cmd_fw_init(adapter);
6b7c5b94 2948 if (status)
2243e2e9
SP		 2949 goto ctrl_clean;
2950
556ae191
SB		 2951 if (be_physfn(adapter)) {
2952 status = be_cmd_reset_function(adapter);
2953 if (status)
2954 goto ctrl_clean;
2955 }
2956
2243e2e9
SP		 2957 status = be_stats_init(adapter);
2958 if (status)
2959 goto ctrl_clean;
2960
2961 status = be_get_config(adapter);
6b7c5b94
SP		 2962 if (status)
2963 goto stats_clean;
6b7c5b94 2964
3abcdeda
SP		 2965 be_msix_enable(adapter);
2966
6b7c5b94 2967 INIT_DELAYED_WORK(&adapter->work, be_worker);
6b7c5b94 2968
5fb379ee
SP		 2969 status = be_setup(adapter);
2970 if (status)
3abcdeda 2971 goto msix_disable;
2243e2e9 2972
3abcdeda 2973 be_netdev_init(netdev);
6b7c5b94
SP		 2974 status = register_netdev(netdev);
2975 if (status != 0)
5fb379ee 2976 goto unsetup;
63a76944 2977 netif_carrier_off(netdev);
6b7c5b94 2978
e6319365
AK		 2979 if (be_physfn(adapter) && adapter->sriov_enabled) {
2980 status = be_vf_eth_addr_config(adapter);
2981 if (status)
2982 goto unreg_netdev;
2983 }
2984
c4ca2374 2985 dev_info(&pdev->dev, "%s port %d\n", nic_name(pdev), adapter->port_num);
f203af70 2986 schedule_delayed_work(&adapter->work, msecs_to_jiffies(100));
6b7c5b94
SP		 2987 return 0;
2988
e6319365
AK		 2989unreg_netdev:
2990 unregister_netdev(netdev);
5fb379ee
SP		 2991unsetup:
2992 be_clear(adapter);
3abcdeda
SP		 2993msix_disable:
2994 be_msix_disable(adapter);
6b7c5b94
SP		 2995stats_clean:
2996 be_stats_cleanup(adapter);
2997ctrl_clean:
2998 be_ctrl_cleanup(adapter);
2999free_netdev:
ba343c77 3000 be_sriov_disable(adapter);
fe6d2a38 3001 free_netdev(netdev);
8d56ff11 3002 pci_set_drvdata(pdev, NULL);
6b7c5b94
SP		 3003rel_reg:
3004 pci_release_regions(pdev);
3005disable_dev:
3006 pci_disable_device(pdev);
3007do_none:
c4ca2374 3008 dev_err(&pdev->dev, "%s initialization failed\n", nic_name(pdev));
6b7c5b94
SP		 3009 return status;
3010}
3011
3012static int be_suspend(struct pci_dev *pdev, pm_message_t state)
3013{
3014 struct be_adapter *adapter = pci_get_drvdata(pdev);
3015 struct net_device *netdev = adapter->netdev;
3016
71d8d1b5
AK		 3017 if (adapter->wol)
3018 be_setup_wol(adapter, true);
3019
6b7c5b94
SP		 3020 netif_device_detach(netdev);
3021 if (netif_running(netdev)) {
3022 rtnl_lock();
3023 be_close(netdev);
3024 rtnl_unlock();
3025 }
9e90c961 3026 be_cmd_get_flow_control(adapter, &adapter->tx_fc, &adapter->rx_fc);
9b0365f1 3027 be_clear(adapter);
6b7c5b94
SP		 3028
3029 pci_save_state(pdev);
3030 pci_disable_device(pdev);
3031 pci_set_power_state(pdev, pci_choose_state(pdev, state));
3032 return 0;
3033}
3034
3035static int be_resume(struct pci_dev *pdev)
3036{
3037 int status = 0;
3038 struct be_adapter *adapter = pci_get_drvdata(pdev);
3039 struct net_device *netdev = adapter->netdev;
3040
3041 netif_device_detach(netdev);
3042
3043 status = pci_enable_device(pdev);
3044 if (status)
3045 return status;
3046
3047 pci_set_power_state(pdev, 0);
3048 pci_restore_state(pdev);
3049
2243e2e9
SP		 3050 /* tell fw we're ready to fire cmds */
3051 status = be_cmd_fw_init(adapter);
3052 if (status)
3053 return status;
3054
9b0365f1 3055 be_setup(adapter);
6b7c5b94
SP		 3056 if (netif_running(netdev)) {
3057 rtnl_lock();
3058 be_open(netdev);
3059 rtnl_unlock();
3060 }
3061 netif_device_attach(netdev);
71d8d1b5
AK		 3062
3063 if (adapter->wol)
3064 be_setup_wol(adapter, false);
6b7c5b94
SP		 3065 return 0;
3066}
3067
82456b03
SP		 3068/*
3069 * An FLR will stop BE from DMAing any data.
3070 */
3071static void be_shutdown(struct pci_dev *pdev)
3072{
3073 struct be_adapter *adapter = pci_get_drvdata(pdev);
3074 struct net_device *netdev = adapter->netdev;
3075
3076 netif_device_detach(netdev);
3077
3078 be_cmd_reset_function(adapter);
3079
3080 if (adapter->wol)
3081 be_setup_wol(adapter, true);
3082
3083 pci_disable_device(pdev);
82456b03
SP		 3084}
3085
cf588477
SP		 3086static pci_ers_result_t be_eeh_err_detected(struct pci_dev *pdev,
3087 pci_channel_state_t state)
3088{
3089 struct be_adapter *adapter = pci_get_drvdata(pdev);
3090 struct net_device *netdev = adapter->netdev;
3091
3092 dev_err(&adapter->pdev->dev, "EEH error detected\n");
3093
3094 adapter->eeh_err = true;
3095
3096 netif_device_detach(netdev);
3097
3098 if (netif_running(netdev)) {
3099 rtnl_lock();
3100 be_close(netdev);
3101 rtnl_unlock();
3102 }
3103 be_clear(adapter);
3104
3105 if (state == pci_channel_io_perm_failure)
3106 return PCI_ERS_RESULT_DISCONNECT;
3107
3108 pci_disable_device(pdev);
3109
3110 return PCI_ERS_RESULT_NEED_RESET;
3111}
3112
3113static pci_ers_result_t be_eeh_reset(struct pci_dev *pdev)
3114{
3115 struct be_adapter *adapter = pci_get_drvdata(pdev);
3116 int status;
3117
3118 dev_info(&adapter->pdev->dev, "EEH reset\n");
3119 adapter->eeh_err = false;
3120
3121 status = pci_enable_device(pdev);
3122 if (status)
3123 return PCI_ERS_RESULT_DISCONNECT;
3124
3125 pci_set_master(pdev);
3126 pci_set_power_state(pdev, 0);
3127 pci_restore_state(pdev);
3128
3129 /* Check if card is ok and fw is ready */
3130 status = be_cmd_POST(adapter);
3131 if (status)
3132 return PCI_ERS_RESULT_DISCONNECT;
3133
3134 return PCI_ERS_RESULT_RECOVERED;
3135}
3136
3137static void be_eeh_resume(struct pci_dev *pdev)
3138{
3139 int status = 0;
3140 struct be_adapter *adapter = pci_get_drvdata(pdev);
3141 struct net_device *netdev = adapter->netdev;
3142
3143 dev_info(&adapter->pdev->dev, "EEH resume\n");
3144
3145 pci_save_state(pdev);
3146
3147 /* tell fw we're ready to fire cmds */
3148 status = be_cmd_fw_init(adapter);
3149 if (status)
3150 goto err;
3151
3152 status = be_setup(adapter);
3153 if (status)
3154 goto err;
3155
3156 if (netif_running(netdev)) {
3157 status = be_open(netdev);
3158 if (status)
3159 goto err;
3160 }
3161 netif_device_attach(netdev);
3162 return;
3163err:
3164 dev_err(&adapter->pdev->dev, "EEH resume failed\n");
cf588477
SP		 3165}
3166
3167static struct pci_error_handlers be_eeh_handlers = {
3168 .error_detected = be_eeh_err_detected,
3169 .slot_reset = be_eeh_reset,
3170 .resume = be_eeh_resume,
3171};
3172
6b7c5b94
SP		 3173static struct pci_driver be_driver = {
3174 .name = DRV_NAME,
3175 .id_table = be_dev_ids,
3176 .probe = be_probe,
3177 .remove = be_remove,
3178 .suspend = be_suspend,
cf588477 3179 .resume = be_resume,
82456b03 3180 .shutdown = be_shutdown,
cf588477 3181 .err_handler = &be_eeh_handlers
6b7c5b94
SP		 3182};
3183
3184static int __init be_init_module(void)
3185{
8e95a202
JP		 3186 if (rx_frag_size != 8192 && rx_frag_size != 4096 &&
3187 rx_frag_size != 2048) {
6b7c5b94
SP		 3188 printk(KERN_WARNING DRV_NAME
3189 " : Module param rx_frag_size must be 2048/4096/8192."
3190 " Using 2048\n");
3191 rx_frag_size = 2048;
3192 }
6b7c5b94 3193
ba343c77
SB		 3194 if (num_vfs > 32) {
3195 printk(KERN_WARNING DRV_NAME
3196 " : Module param num_vfs must not be greater than 32."
3197 "Using 32\n");
3198 num_vfs = 32;
3199 }
3200
6b7c5b94
SP		 3201 return pci_register_driver(&be_driver);
3202}
3203module_init(be_init_module);
3204
3205static void __exit be_exit_module(void)
3206{
3207 pci_unregister_driver(&be_driver);
3208}
3209module_exit(be_exit_module);
Linux kernel - Deliverables
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