Commit | Line | Data |
---|---|---|
e190d6b1 | 1 | /* |
2fb9d6f5 | 2 | * Blackfin On-Chip MAC Driver |
e190d6b1 | 3 | * |
2fb9d6f5 | 4 | * Copyright 2004-2007 Analog Devices Inc. |
e190d6b1 | 5 | * |
2fb9d6f5 | 6 | * Enter bugs at http://blackfin.uclinux.org/ |
e190d6b1 | 7 | * |
2fb9d6f5 | 8 | * Licensed under the GPL-2 or later. |
e190d6b1 BW |
9 | */ |
10 | ||
11 | #include <linux/init.h> | |
12 | #include <linux/module.h> | |
13 | #include <linux/kernel.h> | |
14 | #include <linux/sched.h> | |
15 | #include <linux/slab.h> | |
16 | #include <linux/delay.h> | |
17 | #include <linux/timer.h> | |
18 | #include <linux/errno.h> | |
19 | #include <linux/irq.h> | |
20 | #include <linux/io.h> | |
21 | #include <linux/ioport.h> | |
22 | #include <linux/crc32.h> | |
23 | #include <linux/device.h> | |
24 | #include <linux/spinlock.h> | |
e190d6b1 | 25 | #include <linux/mii.h> |
4ae5a3ad | 26 | #include <linux/phy.h> |
e190d6b1 BW |
27 | #include <linux/netdevice.h> |
28 | #include <linux/etherdevice.h> | |
679dce39 | 29 | #include <linux/ethtool.h> |
e190d6b1 | 30 | #include <linux/skbuff.h> |
e190d6b1 | 31 | #include <linux/platform_device.h> |
e190d6b1 BW |
32 | |
33 | #include <asm/dma.h> | |
34 | #include <linux/dma-mapping.h> | |
35 | ||
fe92afed | 36 | #include <asm/div64.h> |
98f672ca | 37 | #include <asm/dpmc.h> |
e190d6b1 BW |
38 | #include <asm/blackfin.h> |
39 | #include <asm/cacheflush.h> | |
40 | #include <asm/portmux.h> | |
41 | ||
42 | #include "bfin_mac.h" | |
43 | ||
44 | #define DRV_NAME "bfin_mac" | |
45 | #define DRV_VERSION "1.1" | |
46 | #define DRV_AUTHOR "Bryan Wu, Luke Yang" | |
7ef0a7ee | 47 | #define DRV_DESC "Blackfin on-chip Ethernet MAC driver" |
e190d6b1 BW |
48 | |
49 | MODULE_AUTHOR(DRV_AUTHOR); | |
50 | MODULE_LICENSE("GPL"); | |
51 | MODULE_DESCRIPTION(DRV_DESC); | |
72abb461 | 52 | MODULE_ALIAS("platform:bfin_mac"); |
e190d6b1 BW |
53 | |
54 | #if defined(CONFIG_BFIN_MAC_USE_L1) | |
55 | # define bfin_mac_alloc(dma_handle, size) l1_data_sram_zalloc(size) | |
56 | # define bfin_mac_free(dma_handle, ptr) l1_data_sram_free(ptr) | |
57 | #else | |
58 | # define bfin_mac_alloc(dma_handle, size) \ | |
59 | dma_alloc_coherent(NULL, size, dma_handle, GFP_KERNEL) | |
60 | # define bfin_mac_free(dma_handle, ptr) \ | |
61 | dma_free_coherent(NULL, sizeof(*ptr), ptr, dma_handle) | |
62 | #endif | |
63 | ||
64 | #define PKT_BUF_SZ 1580 | |
65 | ||
66 | #define MAX_TIMEOUT_CNT 500 | |
67 | ||
68 | /* pointers to maintain transmit list */ | |
69 | static struct net_dma_desc_tx *tx_list_head; | |
70 | static struct net_dma_desc_tx *tx_list_tail; | |
71 | static struct net_dma_desc_rx *rx_list_head; | |
72 | static struct net_dma_desc_rx *rx_list_tail; | |
73 | static struct net_dma_desc_rx *current_rx_ptr; | |
74 | static struct net_dma_desc_tx *current_tx_ptr; | |
75 | static struct net_dma_desc_tx *tx_desc; | |
76 | static struct net_dma_desc_rx *rx_desc; | |
77 | ||
7ef0a7ee BW |
78 | #if defined(CONFIG_BFIN_MAC_RMII) |
79 | static u16 pin_req[] = P_RMII0; | |
80 | #else | |
81 | static u16 pin_req[] = P_MII0; | |
82 | #endif | |
83 | ||
e190d6b1 BW |
84 | static void desc_list_free(void) |
85 | { | |
86 | struct net_dma_desc_rx *r; | |
87 | struct net_dma_desc_tx *t; | |
88 | int i; | |
89 | #if !defined(CONFIG_BFIN_MAC_USE_L1) | |
90 | dma_addr_t dma_handle = 0; | |
91 | #endif | |
92 | ||
93 | if (tx_desc) { | |
94 | t = tx_list_head; | |
95 | for (i = 0; i < CONFIG_BFIN_TX_DESC_NUM; i++) { | |
96 | if (t) { | |
97 | if (t->skb) { | |
98 | dev_kfree_skb(t->skb); | |
99 | t->skb = NULL; | |
100 | } | |
101 | t = t->next; | |
102 | } | |
103 | } | |
104 | bfin_mac_free(dma_handle, tx_desc); | |
105 | } | |
106 | ||
107 | if (rx_desc) { | |
108 | r = rx_list_head; | |
109 | for (i = 0; i < CONFIG_BFIN_RX_DESC_NUM; i++) { | |
110 | if (r) { | |
111 | if (r->skb) { | |
112 | dev_kfree_skb(r->skb); | |
113 | r->skb = NULL; | |
114 | } | |
115 | r = r->next; | |
116 | } | |
117 | } | |
118 | bfin_mac_free(dma_handle, rx_desc); | |
119 | } | |
120 | } | |
121 | ||
122 | static int desc_list_init(void) | |
123 | { | |
124 | int i; | |
125 | struct sk_buff *new_skb; | |
126 | #if !defined(CONFIG_BFIN_MAC_USE_L1) | |
127 | /* | |
128 | * This dma_handle is useless in Blackfin dma_alloc_coherent(). | |
129 | * The real dma handler is the return value of dma_alloc_coherent(). | |
130 | */ | |
131 | dma_addr_t dma_handle; | |
132 | #endif | |
133 | ||
134 | tx_desc = bfin_mac_alloc(&dma_handle, | |
135 | sizeof(struct net_dma_desc_tx) * | |
136 | CONFIG_BFIN_TX_DESC_NUM); | |
137 | if (tx_desc == NULL) | |
138 | goto init_error; | |
139 | ||
140 | rx_desc = bfin_mac_alloc(&dma_handle, | |
141 | sizeof(struct net_dma_desc_rx) * | |
142 | CONFIG_BFIN_RX_DESC_NUM); | |
143 | if (rx_desc == NULL) | |
144 | goto init_error; | |
145 | ||
146 | /* init tx_list */ | |
147 | tx_list_head = tx_list_tail = tx_desc; | |
148 | ||
149 | for (i = 0; i < CONFIG_BFIN_TX_DESC_NUM; i++) { | |
150 | struct net_dma_desc_tx *t = tx_desc + i; | |
151 | struct dma_descriptor *a = &(t->desc_a); | |
152 | struct dma_descriptor *b = &(t->desc_b); | |
153 | ||
154 | /* | |
155 | * disable DMA | |
156 | * read from memory WNR = 0 | |
157 | * wordsize is 32 bits | |
158 | * 6 half words is desc size | |
159 | * large desc flow | |
160 | */ | |
161 | a->config = WDSIZE_32 | NDSIZE_6 | DMAFLOW_LARGE; | |
162 | a->start_addr = (unsigned long)t->packet; | |
163 | a->x_count = 0; | |
164 | a->next_dma_desc = b; | |
165 | ||
166 | /* | |
167 | * enabled DMA | |
168 | * write to memory WNR = 1 | |
169 | * wordsize is 32 bits | |
170 | * disable interrupt | |
171 | * 6 half words is desc size | |
172 | * large desc flow | |
173 | */ | |
174 | b->config = DMAEN | WNR | WDSIZE_32 | NDSIZE_6 | DMAFLOW_LARGE; | |
175 | b->start_addr = (unsigned long)(&(t->status)); | |
176 | b->x_count = 0; | |
177 | ||
178 | t->skb = NULL; | |
179 | tx_list_tail->desc_b.next_dma_desc = a; | |
180 | tx_list_tail->next = t; | |
181 | tx_list_tail = t; | |
182 | } | |
183 | tx_list_tail->next = tx_list_head; /* tx_list is a circle */ | |
184 | tx_list_tail->desc_b.next_dma_desc = &(tx_list_head->desc_a); | |
185 | current_tx_ptr = tx_list_head; | |
186 | ||
187 | /* init rx_list */ | |
188 | rx_list_head = rx_list_tail = rx_desc; | |
189 | ||
190 | for (i = 0; i < CONFIG_BFIN_RX_DESC_NUM; i++) { | |
191 | struct net_dma_desc_rx *r = rx_desc + i; | |
192 | struct dma_descriptor *a = &(r->desc_a); | |
193 | struct dma_descriptor *b = &(r->desc_b); | |
194 | ||
195 | /* allocate a new skb for next time receive */ | |
015dac88 | 196 | new_skb = dev_alloc_skb(PKT_BUF_SZ + NET_IP_ALIGN); |
e190d6b1 BW |
197 | if (!new_skb) { |
198 | printk(KERN_NOTICE DRV_NAME | |
199 | ": init: low on mem - packet dropped\n"); | |
200 | goto init_error; | |
201 | } | |
015dac88 | 202 | skb_reserve(new_skb, NET_IP_ALIGN); |
f6e1e4f3 SZ |
203 | /* Invidate the data cache of skb->data range when it is write back |
204 | * cache. It will prevent overwritting the new data from DMA | |
205 | */ | |
206 | blackfin_dcache_invalidate_range((unsigned long)new_skb->head, | |
207 | (unsigned long)new_skb->end); | |
e190d6b1 BW |
208 | r->skb = new_skb; |
209 | ||
210 | /* | |
211 | * enabled DMA | |
212 | * write to memory WNR = 1 | |
213 | * wordsize is 32 bits | |
214 | * disable interrupt | |
215 | * 6 half words is desc size | |
216 | * large desc flow | |
217 | */ | |
218 | a->config = DMAEN | WNR | WDSIZE_32 | NDSIZE_6 | DMAFLOW_LARGE; | |
219 | /* since RXDWA is enabled */ | |
220 | a->start_addr = (unsigned long)new_skb->data - 2; | |
221 | a->x_count = 0; | |
222 | a->next_dma_desc = b; | |
223 | ||
224 | /* | |
225 | * enabled DMA | |
226 | * write to memory WNR = 1 | |
227 | * wordsize is 32 bits | |
228 | * enable interrupt | |
229 | * 6 half words is desc size | |
230 | * large desc flow | |
231 | */ | |
232 | b->config = DMAEN | WNR | WDSIZE_32 | DI_EN | | |
233 | NDSIZE_6 | DMAFLOW_LARGE; | |
234 | b->start_addr = (unsigned long)(&(r->status)); | |
235 | b->x_count = 0; | |
236 | ||
237 | rx_list_tail->desc_b.next_dma_desc = a; | |
238 | rx_list_tail->next = r; | |
239 | rx_list_tail = r; | |
240 | } | |
241 | rx_list_tail->next = rx_list_head; /* rx_list is a circle */ | |
242 | rx_list_tail->desc_b.next_dma_desc = &(rx_list_head->desc_a); | |
243 | current_rx_ptr = rx_list_head; | |
244 | ||
245 | return 0; | |
246 | ||
247 | init_error: | |
248 | desc_list_free(); | |
249 | printk(KERN_ERR DRV_NAME ": kmalloc failed\n"); | |
250 | return -ENOMEM; | |
251 | } | |
252 | ||
253 | ||
254 | /*---PHY CONTROL AND CONFIGURATION-----------------------------------------*/ | |
255 | ||
4ae5a3ad BW |
256 | /* |
257 | * MII operations | |
258 | */ | |
e190d6b1 | 259 | /* Wait until the previous MDC/MDIO transaction has completed */ |
2bfa0f0c | 260 | static int bfin_mdio_poll(void) |
e190d6b1 BW |
261 | { |
262 | int timeout_cnt = MAX_TIMEOUT_CNT; | |
263 | ||
264 | /* poll the STABUSY bit */ | |
265 | while ((bfin_read_EMAC_STAADD()) & STABUSY) { | |
6db9e461 | 266 | udelay(1); |
e190d6b1 BW |
267 | if (timeout_cnt-- < 0) { |
268 | printk(KERN_ERR DRV_NAME | |
269 | ": wait MDC/MDIO transaction to complete timeout\n"); | |
2bfa0f0c | 270 | return -ETIMEDOUT; |
e190d6b1 BW |
271 | } |
272 | } | |
2bfa0f0c MF |
273 | |
274 | return 0; | |
e190d6b1 BW |
275 | } |
276 | ||
277 | /* Read an off-chip register in a PHY through the MDC/MDIO port */ | |
0ed0563e | 278 | static int bfin_mdiobus_read(struct mii_bus *bus, int phy_addr, int regnum) |
e190d6b1 | 279 | { |
2bfa0f0c MF |
280 | int ret; |
281 | ||
282 | ret = bfin_mdio_poll(); | |
283 | if (ret) | |
284 | return ret; | |
4ae5a3ad | 285 | |
e190d6b1 | 286 | /* read mode */ |
4ae5a3ad BW |
287 | bfin_write_EMAC_STAADD(SET_PHYAD((u16) phy_addr) | |
288 | SET_REGAD((u16) regnum) | | |
e190d6b1 | 289 | STABUSY); |
e190d6b1 | 290 | |
2bfa0f0c MF |
291 | ret = bfin_mdio_poll(); |
292 | if (ret) | |
293 | return ret; | |
4ae5a3ad BW |
294 | |
295 | return (int) bfin_read_EMAC_STADAT(); | |
e190d6b1 BW |
296 | } |
297 | ||
298 | /* Write an off-chip register in a PHY through the MDC/MDIO port */ | |
0ed0563e AB |
299 | static int bfin_mdiobus_write(struct mii_bus *bus, int phy_addr, int regnum, |
300 | u16 value) | |
e190d6b1 | 301 | { |
2bfa0f0c MF |
302 | int ret; |
303 | ||
304 | ret = bfin_mdio_poll(); | |
305 | if (ret) | |
306 | return ret; | |
4ae5a3ad BW |
307 | |
308 | bfin_write_EMAC_STADAT((u32) value); | |
e190d6b1 BW |
309 | |
310 | /* write mode */ | |
4ae5a3ad BW |
311 | bfin_write_EMAC_STAADD(SET_PHYAD((u16) phy_addr) | |
312 | SET_REGAD((u16) regnum) | | |
e190d6b1 BW |
313 | STAOP | |
314 | STABUSY); | |
315 | ||
2bfa0f0c | 316 | return bfin_mdio_poll(); |
e190d6b1 BW |
317 | } |
318 | ||
0ed0563e | 319 | static int bfin_mdiobus_reset(struct mii_bus *bus) |
e190d6b1 | 320 | { |
4ae5a3ad | 321 | return 0; |
e190d6b1 BW |
322 | } |
323 | ||
7ef0a7ee | 324 | static void bfin_mac_adjust_link(struct net_device *dev) |
e190d6b1 | 325 | { |
7ef0a7ee | 326 | struct bfin_mac_local *lp = netdev_priv(dev); |
4ae5a3ad BW |
327 | struct phy_device *phydev = lp->phydev; |
328 | unsigned long flags; | |
329 | int new_state = 0; | |
330 | ||
331 | spin_lock_irqsave(&lp->lock, flags); | |
332 | if (phydev->link) { | |
333 | /* Now we make sure that we can be in full duplex mode. | |
334 | * If not, we operate in half-duplex mode. */ | |
335 | if (phydev->duplex != lp->old_duplex) { | |
336 | u32 opmode = bfin_read_EMAC_OPMODE(); | |
337 | new_state = 1; | |
338 | ||
339 | if (phydev->duplex) | |
340 | opmode |= FDMODE; | |
341 | else | |
342 | opmode &= ~(FDMODE); | |
343 | ||
344 | bfin_write_EMAC_OPMODE(opmode); | |
345 | lp->old_duplex = phydev->duplex; | |
346 | } | |
e190d6b1 | 347 | |
4ae5a3ad BW |
348 | if (phydev->speed != lp->old_speed) { |
349 | #if defined(CONFIG_BFIN_MAC_RMII) | |
350 | u32 opmode = bfin_read_EMAC_OPMODE(); | |
4ae5a3ad BW |
351 | switch (phydev->speed) { |
352 | case 10: | |
353 | opmode |= RMII_10; | |
354 | break; | |
355 | case 100: | |
356 | opmode &= ~(RMII_10); | |
357 | break; | |
358 | default: | |
359 | printk(KERN_WARNING | |
360 | "%s: Ack! Speed (%d) is not 10/100!\n", | |
361 | DRV_NAME, phydev->speed); | |
362 | break; | |
363 | } | |
364 | bfin_write_EMAC_OPMODE(opmode); | |
4ae5a3ad | 365 | #endif |
e190d6b1 | 366 | |
4ae5a3ad BW |
367 | new_state = 1; |
368 | lp->old_speed = phydev->speed; | |
369 | } | |
e190d6b1 | 370 | |
4ae5a3ad BW |
371 | if (!lp->old_link) { |
372 | new_state = 1; | |
373 | lp->old_link = 1; | |
4ae5a3ad BW |
374 | } |
375 | } else if (lp->old_link) { | |
376 | new_state = 1; | |
377 | lp->old_link = 0; | |
378 | lp->old_speed = 0; | |
379 | lp->old_duplex = -1; | |
e190d6b1 BW |
380 | } |
381 | ||
4ae5a3ad BW |
382 | if (new_state) { |
383 | u32 opmode = bfin_read_EMAC_OPMODE(); | |
384 | phy_print_status(phydev); | |
385 | pr_debug("EMAC_OPMODE = 0x%08x\n", opmode); | |
e190d6b1 | 386 | } |
4ae5a3ad BW |
387 | |
388 | spin_unlock_irqrestore(&lp->lock, flags); | |
e190d6b1 BW |
389 | } |
390 | ||
7cc8f381 BW |
391 | /* MDC = 2.5 MHz */ |
392 | #define MDC_CLK 2500000 | |
393 | ||
4ae5a3ad | 394 | static int mii_probe(struct net_device *dev) |
e190d6b1 | 395 | { |
7ef0a7ee | 396 | struct bfin_mac_local *lp = netdev_priv(dev); |
4ae5a3ad BW |
397 | struct phy_device *phydev = NULL; |
398 | unsigned short sysctl; | |
399 | int i; | |
7cc8f381 | 400 | u32 sclk, mdc_div; |
e190d6b1 | 401 | |
4ae5a3ad | 402 | /* Enable PHY output early */ |
98f672ca MF |
403 | if (!(bfin_read_VR_CTL() & CLKBUFOE)) |
404 | bfin_write_VR_CTL(bfin_read_VR_CTL() | CLKBUFOE); | |
e190d6b1 | 405 | |
7cc8f381 BW |
406 | sclk = get_sclk(); |
407 | mdc_div = ((sclk / MDC_CLK) / 2) - 1; | |
408 | ||
4ae5a3ad | 409 | sysctl = bfin_read_EMAC_SYSCTL(); |
9dc7f30e | 410 | sysctl = (sysctl & ~MDCDIV) | SET_MDCDIV(mdc_div); |
e190d6b1 | 411 | bfin_write_EMAC_SYSCTL(sysctl); |
e190d6b1 | 412 | |
4ae5a3ad BW |
413 | /* search for connect PHY device */ |
414 | for (i = 0; i < PHY_MAX_ADDR; i++) { | |
298cf9be | 415 | struct phy_device *const tmp_phydev = lp->mii_bus->phy_map[i]; |
e190d6b1 | 416 | |
4ae5a3ad BW |
417 | if (!tmp_phydev) |
418 | continue; /* no PHY here... */ | |
e190d6b1 | 419 | |
4ae5a3ad BW |
420 | phydev = tmp_phydev; |
421 | break; /* found it */ | |
422 | } | |
423 | ||
424 | /* now we are supposed to have a proper phydev, to attach to... */ | |
425 | if (!phydev) { | |
426 | printk(KERN_INFO "%s: Don't found any phy device at all\n", | |
427 | dev->name); | |
428 | return -ENODEV; | |
e190d6b1 BW |
429 | } |
430 | ||
431 | #if defined(CONFIG_BFIN_MAC_RMII) | |
c2313557 KS |
432 | phydev = phy_connect(dev, dev_name(&phydev->dev), &bfin_mac_adjust_link, |
433 | 0, PHY_INTERFACE_MODE_RMII); | |
4ae5a3ad | 434 | #else |
c2313557 KS |
435 | phydev = phy_connect(dev, dev_name(&phydev->dev), &bfin_mac_adjust_link, |
436 | 0, PHY_INTERFACE_MODE_MII); | |
e190d6b1 BW |
437 | #endif |
438 | ||
4ae5a3ad BW |
439 | if (IS_ERR(phydev)) { |
440 | printk(KERN_ERR "%s: Could not attach to PHY\n", dev->name); | |
441 | return PTR_ERR(phydev); | |
442 | } | |
443 | ||
444 | /* mask with MAC supported features */ | |
445 | phydev->supported &= (SUPPORTED_10baseT_Half | |
446 | | SUPPORTED_10baseT_Full | |
447 | | SUPPORTED_100baseT_Half | |
448 | | SUPPORTED_100baseT_Full | |
449 | | SUPPORTED_Autoneg | |
450 | | SUPPORTED_Pause | SUPPORTED_Asym_Pause | |
451 | | SUPPORTED_MII | |
452 | | SUPPORTED_TP); | |
453 | ||
454 | phydev->advertising = phydev->supported; | |
455 | ||
456 | lp->old_link = 0; | |
457 | lp->old_speed = 0; | |
458 | lp->old_duplex = -1; | |
459 | lp->phydev = phydev; | |
460 | ||
461 | printk(KERN_INFO "%s: attached PHY driver [%s] " | |
7cc8f381 BW |
462 | "(mii_bus:phy_addr=%s, irq=%d, mdc_clk=%dHz(mdc_div=%d)" |
463 | "@sclk=%dMHz)\n", | |
c2313557 | 464 | DRV_NAME, phydev->drv->name, dev_name(&phydev->dev), phydev->irq, |
7cc8f381 | 465 | MDC_CLK, mdc_div, sclk/1000000); |
4ae5a3ad BW |
466 | |
467 | return 0; | |
468 | } | |
469 | ||
679dce39 BW |
470 | /* |
471 | * Ethtool support | |
472 | */ | |
473 | ||
53fd3f28 MH |
474 | /* |
475 | * interrupt routine for magic packet wakeup | |
476 | */ | |
477 | static irqreturn_t bfin_mac_wake_interrupt(int irq, void *dev_id) | |
478 | { | |
479 | return IRQ_HANDLED; | |
480 | } | |
481 | ||
679dce39 BW |
482 | static int |
483 | bfin_mac_ethtool_getsettings(struct net_device *dev, struct ethtool_cmd *cmd) | |
484 | { | |
485 | struct bfin_mac_local *lp = netdev_priv(dev); | |
486 | ||
487 | if (lp->phydev) | |
488 | return phy_ethtool_gset(lp->phydev, cmd); | |
489 | ||
490 | return -EINVAL; | |
491 | } | |
492 | ||
493 | static int | |
494 | bfin_mac_ethtool_setsettings(struct net_device *dev, struct ethtool_cmd *cmd) | |
495 | { | |
496 | struct bfin_mac_local *lp = netdev_priv(dev); | |
497 | ||
498 | if (!capable(CAP_NET_ADMIN)) | |
499 | return -EPERM; | |
500 | ||
501 | if (lp->phydev) | |
502 | return phy_ethtool_sset(lp->phydev, cmd); | |
503 | ||
504 | return -EINVAL; | |
505 | } | |
506 | ||
507 | static void bfin_mac_ethtool_getdrvinfo(struct net_device *dev, | |
508 | struct ethtool_drvinfo *info) | |
509 | { | |
510 | strcpy(info->driver, DRV_NAME); | |
511 | strcpy(info->version, DRV_VERSION); | |
512 | strcpy(info->fw_version, "N/A"); | |
c2313557 | 513 | strcpy(info->bus_info, dev_name(&dev->dev)); |
679dce39 BW |
514 | } |
515 | ||
53fd3f28 MH |
516 | static void bfin_mac_ethtool_getwol(struct net_device *dev, |
517 | struct ethtool_wolinfo *wolinfo) | |
518 | { | |
519 | struct bfin_mac_local *lp = netdev_priv(dev); | |
520 | ||
521 | wolinfo->supported = WAKE_MAGIC; | |
522 | wolinfo->wolopts = lp->wol; | |
523 | } | |
524 | ||
525 | static int bfin_mac_ethtool_setwol(struct net_device *dev, | |
526 | struct ethtool_wolinfo *wolinfo) | |
527 | { | |
528 | struct bfin_mac_local *lp = netdev_priv(dev); | |
529 | int rc; | |
530 | ||
531 | if (wolinfo->wolopts & (WAKE_MAGICSECURE | | |
532 | WAKE_UCAST | | |
533 | WAKE_MCAST | | |
534 | WAKE_BCAST | | |
535 | WAKE_ARP)) | |
536 | return -EOPNOTSUPP; | |
537 | ||
538 | lp->wol = wolinfo->wolopts; | |
539 | ||
540 | if (lp->wol && !lp->irq_wake_requested) { | |
541 | /* register wake irq handler */ | |
542 | rc = request_irq(IRQ_MAC_WAKEDET, bfin_mac_wake_interrupt, | |
543 | IRQF_DISABLED, "EMAC_WAKE", dev); | |
544 | if (rc) | |
545 | return rc; | |
546 | lp->irq_wake_requested = true; | |
547 | } | |
548 | ||
549 | if (!lp->wol && lp->irq_wake_requested) { | |
550 | free_irq(IRQ_MAC_WAKEDET, dev); | |
551 | lp->irq_wake_requested = false; | |
552 | } | |
553 | ||
554 | /* Make sure the PHY driver doesn't suspend */ | |
555 | device_init_wakeup(&dev->dev, lp->wol); | |
556 | ||
557 | return 0; | |
558 | } | |
559 | ||
0fc0b732 | 560 | static const struct ethtool_ops bfin_mac_ethtool_ops = { |
679dce39 BW |
561 | .get_settings = bfin_mac_ethtool_getsettings, |
562 | .set_settings = bfin_mac_ethtool_setsettings, | |
563 | .get_link = ethtool_op_get_link, | |
564 | .get_drvinfo = bfin_mac_ethtool_getdrvinfo, | |
53fd3f28 MH |
565 | .get_wol = bfin_mac_ethtool_getwol, |
566 | .set_wol = bfin_mac_ethtool_setwol, | |
679dce39 BW |
567 | }; |
568 | ||
4ae5a3ad BW |
569 | /**************************************************************************/ |
570 | void setup_system_regs(struct net_device *dev) | |
571 | { | |
572 | unsigned short sysctl; | |
573 | ||
574 | /* | |
575 | * Odd word alignment for Receive Frame DMA word | |
576 | * Configure checksum support and rcve frame word alignment | |
577 | */ | |
578 | sysctl = bfin_read_EMAC_SYSCTL(); | |
812a9de7 | 579 | sysctl |= RXDWA; |
4ae5a3ad | 580 | #if defined(BFIN_MAC_CSUM_OFFLOAD) |
812a9de7 | 581 | sysctl |= RXCKS; |
4ae5a3ad | 582 | #else |
812a9de7 | 583 | sysctl &= ~RXCKS; |
4ae5a3ad BW |
584 | #endif |
585 | bfin_write_EMAC_SYSCTL(sysctl); | |
e190d6b1 BW |
586 | |
587 | bfin_write_EMAC_MMC_CTL(RSTC | CROLL); | |
588 | ||
589 | /* Initialize the TX DMA channel registers */ | |
590 | bfin_write_DMA2_X_COUNT(0); | |
591 | bfin_write_DMA2_X_MODIFY(4); | |
592 | bfin_write_DMA2_Y_COUNT(0); | |
593 | bfin_write_DMA2_Y_MODIFY(0); | |
594 | ||
595 | /* Initialize the RX DMA channel registers */ | |
596 | bfin_write_DMA1_X_COUNT(0); | |
597 | bfin_write_DMA1_X_MODIFY(4); | |
598 | bfin_write_DMA1_Y_COUNT(0); | |
599 | bfin_write_DMA1_Y_MODIFY(0); | |
600 | } | |
601 | ||
73f83182 | 602 | static void setup_mac_addr(u8 *mac_addr) |
e190d6b1 BW |
603 | { |
604 | u32 addr_low = le32_to_cpu(*(__le32 *) & mac_addr[0]); | |
605 | u16 addr_hi = le16_to_cpu(*(__le16 *) & mac_addr[4]); | |
606 | ||
607 | /* this depends on a little-endian machine */ | |
608 | bfin_write_EMAC_ADDRLO(addr_low); | |
609 | bfin_write_EMAC_ADDRHI(addr_hi); | |
610 | } | |
611 | ||
7ef0a7ee | 612 | static int bfin_mac_set_mac_address(struct net_device *dev, void *p) |
73f83182 AL |
613 | { |
614 | struct sockaddr *addr = p; | |
615 | if (netif_running(dev)) | |
616 | return -EBUSY; | |
617 | memcpy(dev->dev_addr, addr->sa_data, dev->addr_len); | |
618 | setup_mac_addr(dev->dev_addr); | |
619 | return 0; | |
620 | } | |
621 | ||
fe92afed BS |
622 | #ifdef CONFIG_BFIN_MAC_USE_HWSTAMP |
623 | #define bfin_mac_hwtstamp_is_none(cfg) ((cfg) == HWTSTAMP_FILTER_NONE) | |
624 | ||
625 | static int bfin_mac_hwtstamp_ioctl(struct net_device *netdev, | |
626 | struct ifreq *ifr, int cmd) | |
627 | { | |
628 | struct hwtstamp_config config; | |
629 | struct bfin_mac_local *lp = netdev_priv(netdev); | |
630 | u16 ptpctl; | |
631 | u32 ptpfv1, ptpfv2, ptpfv3, ptpfoff; | |
632 | ||
633 | if (copy_from_user(&config, ifr->ifr_data, sizeof(config))) | |
634 | return -EFAULT; | |
635 | ||
636 | pr_debug("%s config flag:0x%x, tx_type:0x%x, rx_filter:0x%x\n", | |
637 | __func__, config.flags, config.tx_type, config.rx_filter); | |
638 | ||
639 | /* reserved for future extensions */ | |
640 | if (config.flags) | |
641 | return -EINVAL; | |
642 | ||
643 | if ((config.tx_type != HWTSTAMP_TX_OFF) && | |
644 | (config.tx_type != HWTSTAMP_TX_ON)) | |
645 | return -ERANGE; | |
646 | ||
647 | ptpctl = bfin_read_EMAC_PTP_CTL(); | |
648 | ||
649 | switch (config.rx_filter) { | |
650 | case HWTSTAMP_FILTER_NONE: | |
651 | /* | |
652 | * Dont allow any timestamping | |
653 | */ | |
654 | ptpfv3 = 0xFFFFFFFF; | |
655 | bfin_write_EMAC_PTP_FV3(ptpfv3); | |
656 | break; | |
657 | case HWTSTAMP_FILTER_PTP_V1_L4_EVENT: | |
658 | case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: | |
659 | case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: | |
660 | /* | |
661 | * Clear the five comparison mask bits (bits[12:8]) in EMAC_PTP_CTL) | |
662 | * to enable all the field matches. | |
663 | */ | |
664 | ptpctl &= ~0x1F00; | |
665 | bfin_write_EMAC_PTP_CTL(ptpctl); | |
666 | /* | |
667 | * Keep the default values of the EMAC_PTP_FOFF register. | |
668 | */ | |
669 | ptpfoff = 0x4A24170C; | |
670 | bfin_write_EMAC_PTP_FOFF(ptpfoff); | |
671 | /* | |
672 | * Keep the default values of the EMAC_PTP_FV1 and EMAC_PTP_FV2 | |
673 | * registers. | |
674 | */ | |
675 | ptpfv1 = 0x11040800; | |
676 | bfin_write_EMAC_PTP_FV1(ptpfv1); | |
677 | ptpfv2 = 0x0140013F; | |
678 | bfin_write_EMAC_PTP_FV2(ptpfv2); | |
679 | /* | |
680 | * The default value (0xFFFC) allows the timestamping of both | |
681 | * received Sync messages and Delay_Req messages. | |
682 | */ | |
683 | ptpfv3 = 0xFFFFFFFC; | |
684 | bfin_write_EMAC_PTP_FV3(ptpfv3); | |
685 | ||
686 | config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT; | |
687 | break; | |
688 | case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: | |
689 | case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: | |
690 | case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: | |
691 | /* Clear all five comparison mask bits (bits[12:8]) in the | |
692 | * EMAC_PTP_CTL register to enable all the field matches. | |
693 | */ | |
694 | ptpctl &= ~0x1F00; | |
695 | bfin_write_EMAC_PTP_CTL(ptpctl); | |
696 | /* | |
697 | * Keep the default values of the EMAC_PTP_FOFF register, except set | |
698 | * the PTPCOF field to 0x2A. | |
699 | */ | |
700 | ptpfoff = 0x2A24170C; | |
701 | bfin_write_EMAC_PTP_FOFF(ptpfoff); | |
702 | /* | |
703 | * Keep the default values of the EMAC_PTP_FV1 and EMAC_PTP_FV2 | |
704 | * registers. | |
705 | */ | |
706 | ptpfv1 = 0x11040800; | |
707 | bfin_write_EMAC_PTP_FV1(ptpfv1); | |
708 | ptpfv2 = 0x0140013F; | |
709 | bfin_write_EMAC_PTP_FV2(ptpfv2); | |
710 | /* | |
711 | * To allow the timestamping of Pdelay_Req and Pdelay_Resp, set | |
712 | * the value to 0xFFF0. | |
713 | */ | |
714 | ptpfv3 = 0xFFFFFFF0; | |
715 | bfin_write_EMAC_PTP_FV3(ptpfv3); | |
716 | ||
717 | config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_EVENT; | |
718 | break; | |
719 | case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: | |
720 | case HWTSTAMP_FILTER_PTP_V2_L2_SYNC: | |
721 | case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ: | |
722 | /* | |
723 | * Clear bits 8 and 12 of the EMAC_PTP_CTL register to enable only the | |
724 | * EFTM and PTPCM field comparison. | |
725 | */ | |
726 | ptpctl &= ~0x1100; | |
727 | bfin_write_EMAC_PTP_CTL(ptpctl); | |
728 | /* | |
729 | * Keep the default values of all the fields of the EMAC_PTP_FOFF | |
730 | * register, except set the PTPCOF field to 0x0E. | |
731 | */ | |
732 | ptpfoff = 0x0E24170C; | |
733 | bfin_write_EMAC_PTP_FOFF(ptpfoff); | |
734 | /* | |
735 | * Program bits [15:0] of the EMAC_PTP_FV1 register to 0x88F7, which | |
736 | * corresponds to PTP messages on the MAC layer. | |
737 | */ | |
738 | ptpfv1 = 0x110488F7; | |
739 | bfin_write_EMAC_PTP_FV1(ptpfv1); | |
740 | ptpfv2 = 0x0140013F; | |
741 | bfin_write_EMAC_PTP_FV2(ptpfv2); | |
742 | /* | |
743 | * To allow the timestamping of Pdelay_Req and Pdelay_Resp | |
744 | * messages, set the value to 0xFFF0. | |
745 | */ | |
746 | ptpfv3 = 0xFFFFFFF0; | |
747 | bfin_write_EMAC_PTP_FV3(ptpfv3); | |
748 | ||
749 | config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L2_EVENT; | |
750 | break; | |
751 | default: | |
752 | return -ERANGE; | |
753 | } | |
754 | ||
755 | if (config.tx_type == HWTSTAMP_TX_OFF && | |
756 | bfin_mac_hwtstamp_is_none(config.rx_filter)) { | |
757 | ptpctl &= ~PTP_EN; | |
758 | bfin_write_EMAC_PTP_CTL(ptpctl); | |
759 | ||
760 | SSYNC(); | |
761 | } else { | |
762 | ptpctl |= PTP_EN; | |
763 | bfin_write_EMAC_PTP_CTL(ptpctl); | |
764 | ||
765 | /* | |
766 | * clear any existing timestamp | |
767 | */ | |
768 | bfin_read_EMAC_PTP_RXSNAPLO(); | |
769 | bfin_read_EMAC_PTP_RXSNAPHI(); | |
770 | ||
771 | bfin_read_EMAC_PTP_TXSNAPLO(); | |
772 | bfin_read_EMAC_PTP_TXSNAPHI(); | |
773 | ||
774 | /* | |
775 | * Set registers so that rollover occurs soon to test this. | |
776 | */ | |
777 | bfin_write_EMAC_PTP_TIMELO(0x00000000); | |
778 | bfin_write_EMAC_PTP_TIMEHI(0xFF800000); | |
779 | ||
780 | SSYNC(); | |
781 | ||
782 | lp->compare.last_update = 0; | |
783 | timecounter_init(&lp->clock, | |
784 | &lp->cycles, | |
785 | ktime_to_ns(ktime_get_real())); | |
786 | timecompare_update(&lp->compare, 0); | |
787 | } | |
788 | ||
789 | lp->stamp_cfg = config; | |
790 | return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ? | |
791 | -EFAULT : 0; | |
792 | } | |
793 | ||
794 | static void bfin_dump_hwtamp(char *s, ktime_t *hw, ktime_t *ts, struct timecompare *cmp) | |
795 | { | |
796 | ktime_t sys = ktime_get_real(); | |
797 | ||
798 | pr_debug("%s %s hardware:%d,%d transform system:%d,%d system:%d,%d, cmp:%lld, %lld\n", | |
799 | __func__, s, hw->tv.sec, hw->tv.nsec, ts->tv.sec, ts->tv.nsec, sys.tv.sec, | |
800 | sys.tv.nsec, cmp->offset, cmp->skew); | |
801 | } | |
802 | ||
803 | static void bfin_tx_hwtstamp(struct net_device *netdev, struct sk_buff *skb) | |
804 | { | |
805 | struct bfin_mac_local *lp = netdev_priv(netdev); | |
806 | union skb_shared_tx *shtx = skb_tx(skb); | |
807 | ||
808 | if (shtx->hardware) { | |
809 | int timeout_cnt = MAX_TIMEOUT_CNT; | |
810 | ||
811 | /* When doing time stamping, keep the connection to the socket | |
812 | * a while longer | |
813 | */ | |
814 | shtx->in_progress = 1; | |
815 | ||
816 | /* | |
817 | * The timestamping is done at the EMAC module's MII/RMII interface | |
818 | * when the module sees the Start of Frame of an event message packet. This | |
819 | * interface is the closest possible place to the physical Ethernet transmission | |
820 | * medium, providing the best timing accuracy. | |
821 | */ | |
822 | while ((!(bfin_read_EMAC_PTP_ISTAT() & TXTL)) && (--timeout_cnt)) | |
823 | udelay(1); | |
824 | if (timeout_cnt == 0) | |
825 | printk(KERN_ERR DRV_NAME | |
826 | ": fails to timestamp the TX packet\n"); | |
827 | else { | |
828 | struct skb_shared_hwtstamps shhwtstamps; | |
829 | u64 ns; | |
830 | u64 regval; | |
831 | ||
832 | regval = bfin_read_EMAC_PTP_TXSNAPLO(); | |
833 | regval |= (u64)bfin_read_EMAC_PTP_TXSNAPHI() << 32; | |
834 | memset(&shhwtstamps, 0, sizeof(shhwtstamps)); | |
835 | ns = timecounter_cyc2time(&lp->clock, | |
836 | regval); | |
837 | timecompare_update(&lp->compare, ns); | |
838 | shhwtstamps.hwtstamp = ns_to_ktime(ns); | |
839 | shhwtstamps.syststamp = | |
840 | timecompare_transform(&lp->compare, ns); | |
841 | skb_tstamp_tx(skb, &shhwtstamps); | |
842 | ||
843 | bfin_dump_hwtamp("TX", &shhwtstamps.hwtstamp, &shhwtstamps.syststamp, &lp->compare); | |
844 | } | |
845 | } | |
846 | } | |
847 | ||
848 | static void bfin_rx_hwtstamp(struct net_device *netdev, struct sk_buff *skb) | |
849 | { | |
850 | struct bfin_mac_local *lp = netdev_priv(netdev); | |
851 | u32 valid; | |
852 | u64 regval, ns; | |
853 | struct skb_shared_hwtstamps *shhwtstamps; | |
854 | ||
855 | if (bfin_mac_hwtstamp_is_none(lp->stamp_cfg.rx_filter)) | |
856 | return; | |
857 | ||
858 | valid = bfin_read_EMAC_PTP_ISTAT() & RXEL; | |
859 | if (!valid) | |
860 | return; | |
861 | ||
862 | shhwtstamps = skb_hwtstamps(skb); | |
863 | ||
864 | regval = bfin_read_EMAC_PTP_RXSNAPLO(); | |
865 | regval |= (u64)bfin_read_EMAC_PTP_RXSNAPHI() << 32; | |
866 | ns = timecounter_cyc2time(&lp->clock, regval); | |
867 | timecompare_update(&lp->compare, ns); | |
868 | memset(shhwtstamps, 0, sizeof(*shhwtstamps)); | |
869 | shhwtstamps->hwtstamp = ns_to_ktime(ns); | |
870 | shhwtstamps->syststamp = timecompare_transform(&lp->compare, ns); | |
871 | ||
872 | bfin_dump_hwtamp("RX", &shhwtstamps->hwtstamp, &shhwtstamps->syststamp, &lp->compare); | |
873 | } | |
874 | ||
875 | /* | |
876 | * bfin_read_clock - read raw cycle counter (to be used by time counter) | |
877 | */ | |
878 | static cycle_t bfin_read_clock(const struct cyclecounter *tc) | |
879 | { | |
880 | u64 stamp; | |
881 | ||
882 | stamp = bfin_read_EMAC_PTP_TIMELO(); | |
883 | stamp |= (u64)bfin_read_EMAC_PTP_TIMEHI() << 32ULL; | |
884 | ||
885 | return stamp; | |
886 | } | |
887 | ||
888 | #define PTP_CLK 25000000 | |
889 | ||
890 | static void bfin_mac_hwtstamp_init(struct net_device *netdev) | |
891 | { | |
892 | struct bfin_mac_local *lp = netdev_priv(netdev); | |
893 | u64 append; | |
894 | ||
895 | /* Initialize hardware timer */ | |
896 | append = PTP_CLK * (1ULL << 32); | |
897 | do_div(append, get_sclk()); | |
898 | bfin_write_EMAC_PTP_ADDEND((u32)append); | |
899 | ||
900 | memset(&lp->cycles, 0, sizeof(lp->cycles)); | |
901 | lp->cycles.read = bfin_read_clock; | |
902 | lp->cycles.mask = CLOCKSOURCE_MASK(64); | |
903 | lp->cycles.mult = 1000000000 / PTP_CLK; | |
904 | lp->cycles.shift = 0; | |
905 | ||
906 | /* Synchronize our NIC clock against system wall clock */ | |
907 | memset(&lp->compare, 0, sizeof(lp->compare)); | |
908 | lp->compare.source = &lp->clock; | |
909 | lp->compare.target = ktime_get_real; | |
910 | lp->compare.num_samples = 10; | |
911 | ||
912 | /* Initialize hwstamp config */ | |
913 | lp->stamp_cfg.rx_filter = HWTSTAMP_FILTER_NONE; | |
914 | lp->stamp_cfg.tx_type = HWTSTAMP_TX_OFF; | |
915 | } | |
916 | ||
917 | #else | |
918 | # define bfin_mac_hwtstamp_is_none(cfg) 0 | |
919 | # define bfin_mac_hwtstamp_init(dev) | |
920 | # define bfin_mac_hwtstamp_ioctl(dev, ifr, cmd) (-EOPNOTSUPP) | |
921 | # define bfin_rx_hwtstamp(dev, skb) | |
922 | # define bfin_tx_hwtstamp(dev, skb) | |
923 | #endif | |
924 | ||
4fcc3d34 SZ |
925 | static inline void _tx_reclaim_skb(void) |
926 | { | |
927 | do { | |
928 | tx_list_head->desc_a.config &= ~DMAEN; | |
929 | tx_list_head->status.status_word = 0; | |
930 | if (tx_list_head->skb) { | |
931 | dev_kfree_skb(tx_list_head->skb); | |
932 | tx_list_head->skb = NULL; | |
933 | } | |
934 | tx_list_head = tx_list_head->next; | |
935 | ||
936 | } while (tx_list_head->status.status_word != 0); | |
937 | } | |
938 | ||
939 | static void tx_reclaim_skb(struct bfin_mac_local *lp) | |
e190d6b1 BW |
940 | { |
941 | int timeout_cnt = MAX_TIMEOUT_CNT; | |
942 | ||
4fcc3d34 SZ |
943 | if (tx_list_head->status.status_word != 0) |
944 | _tx_reclaim_skb(); | |
e190d6b1 | 945 | |
4fcc3d34 | 946 | if (current_tx_ptr->next == tx_list_head) { |
e190d6b1 | 947 | while (tx_list_head->status.status_word == 0) { |
4fcc3d34 | 948 | /* slow down polling to avoid too many queue stop. */ |
015dac88 | 949 | udelay(10); |
4fcc3d34 SZ |
950 | /* reclaim skb if DMA is not running. */ |
951 | if (!(bfin_read_DMA2_IRQ_STATUS() & DMA_RUN)) | |
952 | break; | |
953 | if (timeout_cnt-- < 0) | |
e190d6b1 | 954 | break; |
e190d6b1 | 955 | } |
4fcc3d34 SZ |
956 | |
957 | if (timeout_cnt >= 0) | |
958 | _tx_reclaim_skb(); | |
959 | else | |
960 | netif_stop_queue(lp->ndev); | |
e190d6b1 BW |
961 | } |
962 | ||
4fcc3d34 SZ |
963 | if (current_tx_ptr->next != tx_list_head && |
964 | netif_queue_stopped(lp->ndev)) | |
965 | netif_wake_queue(lp->ndev); | |
966 | ||
967 | if (tx_list_head != current_tx_ptr) { | |
968 | /* shorten the timer interval if tx queue is stopped */ | |
969 | if (netif_queue_stopped(lp->ndev)) | |
970 | lp->tx_reclaim_timer.expires = | |
971 | jiffies + (TX_RECLAIM_JIFFIES >> 4); | |
972 | else | |
973 | lp->tx_reclaim_timer.expires = | |
974 | jiffies + TX_RECLAIM_JIFFIES; | |
975 | ||
976 | mod_timer(&lp->tx_reclaim_timer, | |
977 | lp->tx_reclaim_timer.expires); | |
978 | } | |
e190d6b1 | 979 | |
e190d6b1 | 980 | return; |
4fcc3d34 | 981 | } |
e190d6b1 | 982 | |
4fcc3d34 SZ |
983 | static void tx_reclaim_skb_timeout(unsigned long lp) |
984 | { | |
985 | tx_reclaim_skb((struct bfin_mac_local *)lp); | |
e190d6b1 BW |
986 | } |
987 | ||
7ef0a7ee | 988 | static int bfin_mac_hard_start_xmit(struct sk_buff *skb, |
e190d6b1 BW |
989 | struct net_device *dev) |
990 | { | |
4fcc3d34 | 991 | struct bfin_mac_local *lp = netdev_priv(dev); |
a50c0c05 | 992 | u16 *data; |
015dac88 | 993 | u32 data_align = (unsigned long)(skb->data) & 0x3; |
fe92afed BS |
994 | union skb_shared_tx *shtx = skb_tx(skb); |
995 | ||
e190d6b1 BW |
996 | current_tx_ptr->skb = skb; |
997 | ||
015dac88 MH |
998 | if (data_align == 0x2) { |
999 | /* move skb->data to current_tx_ptr payload */ | |
1000 | data = (u16 *)(skb->data) - 1; | |
fe92afed BS |
1001 | *data = (u16)(skb->len); |
1002 | /* | |
1003 | * When transmitting an Ethernet packet, the PTP_TSYNC module requires | |
1004 | * a DMA_Length_Word field associated with the packet. The lower 12 bits | |
1005 | * of this field are the length of the packet payload in bytes and the higher | |
1006 | * 4 bits are the timestamping enable field. | |
1007 | */ | |
1008 | if (shtx->hardware) | |
1009 | *data |= 0x1000; | |
1010 | ||
015dac88 MH |
1011 | current_tx_ptr->desc_a.start_addr = (u32)data; |
1012 | /* this is important! */ | |
1013 | blackfin_dcache_flush_range((u32)data, | |
1014 | (u32)((u8 *)data + skb->len + 4)); | |
e190d6b1 | 1015 | } else { |
015dac88 | 1016 | *((u16 *)(current_tx_ptr->packet)) = (u16)(skb->len); |
fe92afed BS |
1017 | /* enable timestamping for the sent packet */ |
1018 | if (shtx->hardware) | |
1019 | *((u16 *)(current_tx_ptr->packet)) |= 0x1000; | |
015dac88 MH |
1020 | memcpy((u8 *)(current_tx_ptr->packet + 2), skb->data, |
1021 | skb->len); | |
1022 | current_tx_ptr->desc_a.start_addr = | |
1023 | (u32)current_tx_ptr->packet; | |
015dac88 MH |
1024 | blackfin_dcache_flush_range( |
1025 | (u32)current_tx_ptr->packet, | |
1026 | (u32)(current_tx_ptr->packet + skb->len + 2)); | |
e190d6b1 BW |
1027 | } |
1028 | ||
805a8ab3 SZ |
1029 | /* make sure the internal data buffers in the core are drained |
1030 | * so that the DMA descriptors are completely written when the | |
1031 | * DMA engine goes to fetch them below | |
1032 | */ | |
1033 | SSYNC(); | |
1034 | ||
4fcc3d34 SZ |
1035 | /* always clear status buffer before start tx dma */ |
1036 | current_tx_ptr->status.status_word = 0; | |
1037 | ||
e190d6b1 BW |
1038 | /* enable this packet's dma */ |
1039 | current_tx_ptr->desc_a.config |= DMAEN; | |
1040 | ||
1041 | /* tx dma is running, just return */ | |
015dac88 | 1042 | if (bfin_read_DMA2_IRQ_STATUS() & DMA_RUN) |
e190d6b1 BW |
1043 | goto out; |
1044 | ||
1045 | /* tx dma is not running */ | |
1046 | bfin_write_DMA2_NEXT_DESC_PTR(&(current_tx_ptr->desc_a)); | |
1047 | /* dma enabled, read from memory, size is 6 */ | |
1048 | bfin_write_DMA2_CONFIG(current_tx_ptr->desc_a.config); | |
1049 | /* Turn on the EMAC tx */ | |
1050 | bfin_write_EMAC_OPMODE(bfin_read_EMAC_OPMODE() | TE); | |
1051 | ||
1052 | out: | |
fe92afed BS |
1053 | bfin_tx_hwtstamp(dev, skb); |
1054 | ||
e190d6b1 | 1055 | current_tx_ptr = current_tx_ptr->next; |
09f75cd7 JG |
1056 | dev->stats.tx_packets++; |
1057 | dev->stats.tx_bytes += (skb->len); | |
4fcc3d34 SZ |
1058 | |
1059 | tx_reclaim_skb(lp); | |
1060 | ||
6ed10654 | 1061 | return NETDEV_TX_OK; |
e190d6b1 BW |
1062 | } |
1063 | ||
ad2864d8 | 1064 | #define IP_HEADER_OFF 0 |
ec497b32 PM |
1065 | #define RX_ERROR_MASK (RX_LONG | RX_ALIGN | RX_CRC | RX_LEN | \ |
1066 | RX_FRAG | RX_ADDR | RX_DMAO | RX_PHY | RX_LATE | RX_RANGE) | |
1067 | ||
7ef0a7ee | 1068 | static void bfin_mac_rx(struct net_device *dev) |
e190d6b1 BW |
1069 | { |
1070 | struct sk_buff *skb, *new_skb; | |
e190d6b1 | 1071 | unsigned short len; |
fe92afed | 1072 | struct bfin_mac_local *lp __maybe_unused = netdev_priv(dev); |
ad2864d8 SZ |
1073 | #if defined(BFIN_MAC_CSUM_OFFLOAD) |
1074 | unsigned int i; | |
1075 | unsigned char fcs[ETH_FCS_LEN + 1]; | |
1076 | #endif | |
e190d6b1 | 1077 | |
ec497b32 PM |
1078 | /* check if frame status word reports an error condition |
1079 | * we which case we simply drop the packet | |
1080 | */ | |
1081 | if (current_rx_ptr->status.status_word & RX_ERROR_MASK) { | |
1082 | printk(KERN_NOTICE DRV_NAME | |
1083 | ": rx: receive error - packet dropped\n"); | |
1084 | dev->stats.rx_dropped++; | |
1085 | goto out; | |
1086 | } | |
1087 | ||
e190d6b1 BW |
1088 | /* allocate a new skb for next time receive */ |
1089 | skb = current_rx_ptr->skb; | |
fe92afed | 1090 | |
015dac88 | 1091 | new_skb = dev_alloc_skb(PKT_BUF_SZ + NET_IP_ALIGN); |
e190d6b1 BW |
1092 | if (!new_skb) { |
1093 | printk(KERN_NOTICE DRV_NAME | |
1094 | ": rx: low on mem - packet dropped\n"); | |
09f75cd7 | 1095 | dev->stats.rx_dropped++; |
e190d6b1 BW |
1096 | goto out; |
1097 | } | |
1098 | /* reserve 2 bytes for RXDWA padding */ | |
015dac88 | 1099 | skb_reserve(new_skb, NET_IP_ALIGN); |
6e01d1a4 AD |
1100 | /* Invidate the data cache of skb->data range when it is write back |
1101 | * cache. It will prevent overwritting the new data from DMA | |
1102 | */ | |
1103 | blackfin_dcache_invalidate_range((unsigned long)new_skb->head, | |
1104 | (unsigned long)new_skb->end); | |
1105 | ||
f6e1e4f3 SZ |
1106 | current_rx_ptr->skb = new_skb; |
1107 | current_rx_ptr->desc_a.start_addr = (unsigned long)new_skb->data - 2; | |
1108 | ||
e190d6b1 | 1109 | len = (unsigned short)((current_rx_ptr->status.status_word) & RX_FRLEN); |
ad2864d8 SZ |
1110 | /* Deduce Ethernet FCS length from Ethernet payload length */ |
1111 | len -= ETH_FCS_LEN; | |
e190d6b1 | 1112 | skb_put(skb, len); |
e190d6b1 | 1113 | |
e190d6b1 | 1114 | skb->protocol = eth_type_trans(skb, dev); |
fe92afed BS |
1115 | |
1116 | bfin_rx_hwtstamp(dev, skb); | |
1117 | ||
e190d6b1 | 1118 | #if defined(BFIN_MAC_CSUM_OFFLOAD) |
ad2864d8 SZ |
1119 | /* Checksum offloading only works for IPv4 packets with the standard IP header |
1120 | * length of 20 bytes, because the blackfin MAC checksum calculation is | |
1121 | * based on that assumption. We must NOT use the calculated checksum if our | |
1122 | * IP version or header break that assumption. | |
1123 | */ | |
1124 | if (skb->data[IP_HEADER_OFF] == 0x45) { | |
1125 | skb->csum = current_rx_ptr->status.ip_payload_csum; | |
1126 | /* | |
1127 | * Deduce Ethernet FCS from hardware generated IP payload checksum. | |
1128 | * IP checksum is based on 16-bit one's complement algorithm. | |
1129 | * To deduce a value from checksum is equal to add its inversion. | |
1130 | * If the IP payload len is odd, the inversed FCS should also | |
1131 | * begin from odd address and leave first byte zero. | |
1132 | */ | |
1133 | if (skb->len % 2) { | |
1134 | fcs[0] = 0; | |
1135 | for (i = 0; i < ETH_FCS_LEN; i++) | |
1136 | fcs[i + 1] = ~skb->data[skb->len + i]; | |
1137 | skb->csum = csum_partial(fcs, ETH_FCS_LEN + 1, skb->csum); | |
1138 | } else { | |
1139 | for (i = 0; i < ETH_FCS_LEN; i++) | |
1140 | fcs[i] = ~skb->data[skb->len + i]; | |
1141 | skb->csum = csum_partial(fcs, ETH_FCS_LEN, skb->csum); | |
1142 | } | |
1143 | skb->ip_summed = CHECKSUM_COMPLETE; | |
1144 | } | |
e190d6b1 BW |
1145 | #endif |
1146 | ||
1147 | netif_rx(skb); | |
09f75cd7 JG |
1148 | dev->stats.rx_packets++; |
1149 | dev->stats.rx_bytes += len; | |
ec497b32 | 1150 | out: |
e190d6b1 BW |
1151 | current_rx_ptr->status.status_word = 0x00000000; |
1152 | current_rx_ptr = current_rx_ptr->next; | |
e190d6b1 BW |
1153 | } |
1154 | ||
1155 | /* interrupt routine to handle rx and error signal */ | |
7ef0a7ee | 1156 | static irqreturn_t bfin_mac_interrupt(int irq, void *dev_id) |
e190d6b1 BW |
1157 | { |
1158 | struct net_device *dev = dev_id; | |
1159 | int number = 0; | |
1160 | ||
1161 | get_one_packet: | |
1162 | if (current_rx_ptr->status.status_word == 0) { | |
1163 | /* no more new packet received */ | |
1164 | if (number == 0) { | |
1165 | if (current_rx_ptr->next->status.status_word != 0) { | |
1166 | current_rx_ptr = current_rx_ptr->next; | |
1167 | goto real_rx; | |
1168 | } | |
1169 | } | |
1170 | bfin_write_DMA1_IRQ_STATUS(bfin_read_DMA1_IRQ_STATUS() | | |
1171 | DMA_DONE | DMA_ERR); | |
1172 | return IRQ_HANDLED; | |
1173 | } | |
1174 | ||
1175 | real_rx: | |
7ef0a7ee | 1176 | bfin_mac_rx(dev); |
e190d6b1 BW |
1177 | number++; |
1178 | goto get_one_packet; | |
1179 | } | |
1180 | ||
1181 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
7ef0a7ee | 1182 | static void bfin_mac_poll(struct net_device *dev) |
e190d6b1 | 1183 | { |
4fcc3d34 SZ |
1184 | struct bfin_mac_local *lp = netdev_priv(dev); |
1185 | ||
e190d6b1 | 1186 | disable_irq(IRQ_MAC_RX); |
7ef0a7ee | 1187 | bfin_mac_interrupt(IRQ_MAC_RX, dev); |
4fcc3d34 | 1188 | tx_reclaim_skb(lp); |
e190d6b1 BW |
1189 | enable_irq(IRQ_MAC_RX); |
1190 | } | |
1191 | #endif /* CONFIG_NET_POLL_CONTROLLER */ | |
1192 | ||
7ef0a7ee | 1193 | static void bfin_mac_disable(void) |
e190d6b1 BW |
1194 | { |
1195 | unsigned int opmode; | |
1196 | ||
1197 | opmode = bfin_read_EMAC_OPMODE(); | |
1198 | opmode &= (~RE); | |
1199 | opmode &= (~TE); | |
1200 | /* Turn off the EMAC */ | |
1201 | bfin_write_EMAC_OPMODE(opmode); | |
1202 | } | |
1203 | ||
1204 | /* | |
1205 | * Enable Interrupts, Receive, and Transmit | |
1206 | */ | |
2bfa0f0c | 1207 | static int bfin_mac_enable(void) |
e190d6b1 | 1208 | { |
2bfa0f0c | 1209 | int ret; |
e190d6b1 BW |
1210 | u32 opmode; |
1211 | ||
b39d66a8 | 1212 | pr_debug("%s: %s\n", DRV_NAME, __func__); |
e190d6b1 BW |
1213 | |
1214 | /* Set RX DMA */ | |
1215 | bfin_write_DMA1_NEXT_DESC_PTR(&(rx_list_head->desc_a)); | |
1216 | bfin_write_DMA1_CONFIG(rx_list_head->desc_a.config); | |
1217 | ||
1218 | /* Wait MII done */ | |
2bfa0f0c MF |
1219 | ret = bfin_mdio_poll(); |
1220 | if (ret) | |
1221 | return ret; | |
e190d6b1 BW |
1222 | |
1223 | /* We enable only RX here */ | |
1224 | /* ASTP : Enable Automatic Pad Stripping | |
1225 | PR : Promiscuous Mode for test | |
1226 | PSF : Receive frames with total length less than 64 bytes. | |
1227 | FDMODE : Full Duplex Mode | |
1228 | LB : Internal Loopback for test | |
1229 | RE : Receiver Enable */ | |
1230 | opmode = bfin_read_EMAC_OPMODE(); | |
1231 | if (opmode & FDMODE) | |
1232 | opmode |= PSF; | |
1233 | else | |
1234 | opmode |= DRO | DC | PSF; | |
1235 | opmode |= RE; | |
1236 | ||
1237 | #if defined(CONFIG_BFIN_MAC_RMII) | |
1238 | opmode |= RMII; /* For Now only 100MBit are supported */ | |
6893ff1c | 1239 | #if (defined(CONFIG_BF537) || defined(CONFIG_BF536)) && CONFIG_BF_REV_0_2 |
e190d6b1 BW |
1240 | opmode |= TE; |
1241 | #endif | |
1242 | #endif | |
1243 | /* Turn on the EMAC rx */ | |
1244 | bfin_write_EMAC_OPMODE(opmode); | |
2bfa0f0c MF |
1245 | |
1246 | return 0; | |
e190d6b1 BW |
1247 | } |
1248 | ||
1249 | /* Our watchdog timed out. Called by the networking layer */ | |
7ef0a7ee | 1250 | static void bfin_mac_timeout(struct net_device *dev) |
e190d6b1 | 1251 | { |
4fcc3d34 SZ |
1252 | struct bfin_mac_local *lp = netdev_priv(dev); |
1253 | ||
b39d66a8 | 1254 | pr_debug("%s: %s\n", dev->name, __func__); |
e190d6b1 | 1255 | |
7ef0a7ee | 1256 | bfin_mac_disable(); |
e190d6b1 | 1257 | |
4fcc3d34 SZ |
1258 | del_timer(&lp->tx_reclaim_timer); |
1259 | ||
1260 | /* reset tx queue and free skb */ | |
1261 | while (tx_list_head != current_tx_ptr) { | |
1262 | tx_list_head->desc_a.config &= ~DMAEN; | |
1263 | tx_list_head->status.status_word = 0; | |
1264 | if (tx_list_head->skb) { | |
1265 | dev_kfree_skb(tx_list_head->skb); | |
1266 | tx_list_head->skb = NULL; | |
1267 | } | |
1268 | tx_list_head = tx_list_head->next; | |
1269 | } | |
1270 | ||
1271 | if (netif_queue_stopped(lp->ndev)) | |
1272 | netif_wake_queue(lp->ndev); | |
e190d6b1 | 1273 | |
7ef0a7ee | 1274 | bfin_mac_enable(); |
e190d6b1 BW |
1275 | |
1276 | /* We can accept TX packets again */ | |
1ae5dc34 | 1277 | dev->trans_start = jiffies; /* prevent tx timeout */ |
e190d6b1 BW |
1278 | netif_wake_queue(dev); |
1279 | } | |
1280 | ||
7ef0a7ee | 1281 | static void bfin_mac_multicast_hash(struct net_device *dev) |
775919bc AW |
1282 | { |
1283 | u32 emac_hashhi, emac_hashlo; | |
22bedad3 | 1284 | struct netdev_hw_addr *ha; |
775919bc | 1285 | char *addrs; |
775919bc AW |
1286 | u32 crc; |
1287 | ||
1288 | emac_hashhi = emac_hashlo = 0; | |
1289 | ||
22bedad3 JP |
1290 | netdev_for_each_mc_addr(ha, dev) { |
1291 | addrs = ha->addr; | |
775919bc AW |
1292 | |
1293 | /* skip non-multicast addresses */ | |
1294 | if (!(*addrs & 1)) | |
1295 | continue; | |
1296 | ||
1297 | crc = ether_crc(ETH_ALEN, addrs); | |
1298 | crc >>= 26; | |
1299 | ||
1300 | if (crc & 0x20) | |
1301 | emac_hashhi |= 1 << (crc & 0x1f); | |
1302 | else | |
1303 | emac_hashlo |= 1 << (crc & 0x1f); | |
1304 | } | |
1305 | ||
1306 | bfin_write_EMAC_HASHHI(emac_hashhi); | |
1307 | bfin_write_EMAC_HASHLO(emac_hashlo); | |
775919bc AW |
1308 | } |
1309 | ||
e190d6b1 BW |
1310 | /* |
1311 | * This routine will, depending on the values passed to it, | |
1312 | * either make it accept multicast packets, go into | |
1313 | * promiscuous mode (for TCPDUMP and cousins) or accept | |
1314 | * a select set of multicast packets | |
1315 | */ | |
7ef0a7ee | 1316 | static void bfin_mac_set_multicast_list(struct net_device *dev) |
e190d6b1 BW |
1317 | { |
1318 | u32 sysctl; | |
1319 | ||
1320 | if (dev->flags & IFF_PROMISC) { | |
1321 | printk(KERN_INFO "%s: set to promisc mode\n", dev->name); | |
1322 | sysctl = bfin_read_EMAC_OPMODE(); | |
c0da776b | 1323 | sysctl |= PR; |
e190d6b1 | 1324 | bfin_write_EMAC_OPMODE(sysctl); |
775919bc | 1325 | } else if (dev->flags & IFF_ALLMULTI) { |
e190d6b1 BW |
1326 | /* accept all multicast */ |
1327 | sysctl = bfin_read_EMAC_OPMODE(); | |
1328 | sysctl |= PAM; | |
1329 | bfin_write_EMAC_OPMODE(sysctl); | |
4cd24eaf | 1330 | } else if (!netdev_mc_empty(dev)) { |
775919bc AW |
1331 | /* set up multicast hash table */ |
1332 | sysctl = bfin_read_EMAC_OPMODE(); | |
1333 | sysctl |= HM; | |
1334 | bfin_write_EMAC_OPMODE(sysctl); | |
7ef0a7ee | 1335 | bfin_mac_multicast_hash(dev); |
e190d6b1 BW |
1336 | } else { |
1337 | /* clear promisc or multicast mode */ | |
1338 | sysctl = bfin_read_EMAC_OPMODE(); | |
1339 | sysctl &= ~(RAF | PAM); | |
1340 | bfin_write_EMAC_OPMODE(sysctl); | |
1341 | } | |
1342 | } | |
1343 | ||
fe92afed BS |
1344 | static int bfin_mac_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd) |
1345 | { | |
1346 | switch (cmd) { | |
1347 | case SIOCSHWTSTAMP: | |
1348 | return bfin_mac_hwtstamp_ioctl(netdev, ifr, cmd); | |
1349 | default: | |
1350 | return -EOPNOTSUPP; | |
1351 | } | |
1352 | } | |
1353 | ||
e190d6b1 BW |
1354 | /* |
1355 | * this puts the device in an inactive state | |
1356 | */ | |
7ef0a7ee | 1357 | static void bfin_mac_shutdown(struct net_device *dev) |
e190d6b1 BW |
1358 | { |
1359 | /* Turn off the EMAC */ | |
1360 | bfin_write_EMAC_OPMODE(0x00000000); | |
1361 | /* Turn off the EMAC RX DMA */ | |
1362 | bfin_write_DMA1_CONFIG(0x0000); | |
1363 | bfin_write_DMA2_CONFIG(0x0000); | |
1364 | } | |
1365 | ||
1366 | /* | |
1367 | * Open and Initialize the interface | |
1368 | * | |
1369 | * Set up everything, reset the card, etc.. | |
1370 | */ | |
7ef0a7ee | 1371 | static int bfin_mac_open(struct net_device *dev) |
e190d6b1 | 1372 | { |
7ef0a7ee | 1373 | struct bfin_mac_local *lp = netdev_priv(dev); |
2bfa0f0c | 1374 | int ret; |
b39d66a8 | 1375 | pr_debug("%s: %s\n", dev->name, __func__); |
e190d6b1 BW |
1376 | |
1377 | /* | |
1378 | * Check that the address is valid. If its not, refuse | |
1379 | * to bring the device up. The user must specify an | |
1380 | * address using ifconfig eth0 hw ether xx:xx:xx:xx:xx:xx | |
1381 | */ | |
1382 | if (!is_valid_ether_addr(dev->dev_addr)) { | |
1383 | printk(KERN_WARNING DRV_NAME ": no valid ethernet hw addr\n"); | |
1384 | return -EINVAL; | |
1385 | } | |
1386 | ||
1387 | /* initial rx and tx list */ | |
2bfa0f0c MF |
1388 | ret = desc_list_init(); |
1389 | if (ret) | |
1390 | return ret; | |
e190d6b1 | 1391 | |
4ae5a3ad | 1392 | phy_start(lp->phydev); |
136492b2 | 1393 | phy_write(lp->phydev, MII_BMCR, BMCR_RESET); |
e190d6b1 | 1394 | setup_system_regs(dev); |
ee02fee8 | 1395 | setup_mac_addr(dev->dev_addr); |
2bfa0f0c | 1396 | |
7ef0a7ee | 1397 | bfin_mac_disable(); |
2bfa0f0c MF |
1398 | ret = bfin_mac_enable(); |
1399 | if (ret) | |
1400 | return ret; | |
e190d6b1 | 1401 | pr_debug("hardware init finished\n"); |
2bfa0f0c | 1402 | |
e190d6b1 BW |
1403 | netif_start_queue(dev); |
1404 | netif_carrier_on(dev); | |
1405 | ||
1406 | return 0; | |
1407 | } | |
1408 | ||
1409 | /* | |
e190d6b1 BW |
1410 | * this makes the board clean up everything that it can |
1411 | * and not talk to the outside world. Caused by | |
1412 | * an 'ifconfig ethX down' | |
1413 | */ | |
7ef0a7ee | 1414 | static int bfin_mac_close(struct net_device *dev) |
e190d6b1 | 1415 | { |
7ef0a7ee | 1416 | struct bfin_mac_local *lp = netdev_priv(dev); |
b39d66a8 | 1417 | pr_debug("%s: %s\n", dev->name, __func__); |
e190d6b1 BW |
1418 | |
1419 | netif_stop_queue(dev); | |
1420 | netif_carrier_off(dev); | |
1421 | ||
4ae5a3ad | 1422 | phy_stop(lp->phydev); |
136492b2 | 1423 | phy_write(lp->phydev, MII_BMCR, BMCR_PDOWN); |
4ae5a3ad | 1424 | |
e190d6b1 | 1425 | /* clear everything */ |
7ef0a7ee | 1426 | bfin_mac_shutdown(dev); |
e190d6b1 BW |
1427 | |
1428 | /* free the rx/tx buffers */ | |
1429 | desc_list_free(); | |
1430 | ||
1431 | return 0; | |
1432 | } | |
1433 | ||
b63dc8fe MF |
1434 | static const struct net_device_ops bfin_mac_netdev_ops = { |
1435 | .ndo_open = bfin_mac_open, | |
1436 | .ndo_stop = bfin_mac_close, | |
1437 | .ndo_start_xmit = bfin_mac_hard_start_xmit, | |
1438 | .ndo_set_mac_address = bfin_mac_set_mac_address, | |
1439 | .ndo_tx_timeout = bfin_mac_timeout, | |
1440 | .ndo_set_multicast_list = bfin_mac_set_multicast_list, | |
fe92afed | 1441 | .ndo_do_ioctl = bfin_mac_ioctl, |
b63dc8fe MF |
1442 | .ndo_validate_addr = eth_validate_addr, |
1443 | .ndo_change_mtu = eth_change_mtu, | |
1444 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
1445 | .ndo_poll_controller = bfin_mac_poll, | |
1446 | #endif | |
1447 | }; | |
1448 | ||
d7b843d3 | 1449 | static int __devinit bfin_mac_probe(struct platform_device *pdev) |
e190d6b1 | 1450 | { |
7ef0a7ee BW |
1451 | struct net_device *ndev; |
1452 | struct bfin_mac_local *lp; | |
080c8255 GY |
1453 | struct platform_device *pd; |
1454 | int rc; | |
7ef0a7ee BW |
1455 | |
1456 | ndev = alloc_etherdev(sizeof(struct bfin_mac_local)); | |
1457 | if (!ndev) { | |
1458 | dev_err(&pdev->dev, "Cannot allocate net device!\n"); | |
1459 | return -ENOMEM; | |
1460 | } | |
1461 | ||
1462 | SET_NETDEV_DEV(ndev, &pdev->dev); | |
1463 | platform_set_drvdata(pdev, ndev); | |
1464 | lp = netdev_priv(ndev); | |
4fcc3d34 | 1465 | lp->ndev = ndev; |
e190d6b1 BW |
1466 | |
1467 | /* Grab the MAC address in the MAC */ | |
7ef0a7ee BW |
1468 | *(__le32 *) (&(ndev->dev_addr[0])) = cpu_to_le32(bfin_read_EMAC_ADDRLO()); |
1469 | *(__le16 *) (&(ndev->dev_addr[4])) = cpu_to_le16((u16) bfin_read_EMAC_ADDRHI()); | |
e190d6b1 BW |
1470 | |
1471 | /* probe mac */ | |
1472 | /*todo: how to proble? which is revision_register */ | |
1473 | bfin_write_EMAC_ADDRLO(0x12345678); | |
1474 | if (bfin_read_EMAC_ADDRLO() != 0x12345678) { | |
7ef0a7ee BW |
1475 | dev_err(&pdev->dev, "Cannot detect Blackfin on-chip ethernet MAC controller!\n"); |
1476 | rc = -ENODEV; | |
1477 | goto out_err_probe_mac; | |
e190d6b1 BW |
1478 | } |
1479 | ||
e190d6b1 | 1480 | |
7ef0a7ee BW |
1481 | /* |
1482 | * Is it valid? (Did bootloader initialize it?) | |
1483 | * Grab the MAC from the board somehow | |
1484 | * this is done in the arch/blackfin/mach-bfxxx/boards/eth_mac.c | |
1485 | */ | |
1486 | if (!is_valid_ether_addr(ndev->dev_addr)) | |
1487 | bfin_get_ether_addr(ndev->dev_addr); | |
1488 | ||
e190d6b1 | 1489 | /* If still not valid, get a random one */ |
7ef0a7ee BW |
1490 | if (!is_valid_ether_addr(ndev->dev_addr)) |
1491 | random_ether_addr(ndev->dev_addr); | |
e190d6b1 | 1492 | |
7ef0a7ee | 1493 | setup_mac_addr(ndev->dev_addr); |
e190d6b1 | 1494 | |
080c8255 GY |
1495 | if (!pdev->dev.platform_data) { |
1496 | dev_err(&pdev->dev, "Cannot get platform device bfin_mii_bus!\n"); | |
1497 | rc = -ENODEV; | |
1498 | goto out_err_probe_mac; | |
7ef0a7ee | 1499 | } |
080c8255 GY |
1500 | pd = pdev->dev.platform_data; |
1501 | lp->mii_bus = platform_get_drvdata(pd); | |
0e995cd3 SZ |
1502 | if (!lp->mii_bus) { |
1503 | dev_err(&pdev->dev, "Cannot get mii_bus!\n"); | |
1504 | rc = -ENODEV; | |
1505 | goto out_err_mii_bus_probe; | |
1506 | } | |
080c8255 | 1507 | lp->mii_bus->priv = ndev; |
4ae5a3ad | 1508 | |
7ef0a7ee BW |
1509 | rc = mii_probe(ndev); |
1510 | if (rc) { | |
1511 | dev_err(&pdev->dev, "MII Probe failed!\n"); | |
1512 | goto out_err_mii_probe; | |
1513 | } | |
4ae5a3ad | 1514 | |
e190d6b1 | 1515 | /* Fill in the fields of the device structure with ethernet values. */ |
7ef0a7ee BW |
1516 | ether_setup(ndev); |
1517 | ||
149da651 | 1518 | ndev->netdev_ops = &bfin_mac_netdev_ops; |
679dce39 | 1519 | ndev->ethtool_ops = &bfin_mac_ethtool_ops; |
e190d6b1 | 1520 | |
4fcc3d34 SZ |
1521 | init_timer(&lp->tx_reclaim_timer); |
1522 | lp->tx_reclaim_timer.data = (unsigned long)lp; | |
1523 | lp->tx_reclaim_timer.function = tx_reclaim_skb_timeout; | |
1524 | ||
e190d6b1 BW |
1525 | spin_lock_init(&lp->lock); |
1526 | ||
1527 | /* now, enable interrupts */ | |
1528 | /* register irq handler */ | |
7ef0a7ee | 1529 | rc = request_irq(IRQ_MAC_RX, bfin_mac_interrupt, |
91a455f0 | 1530 | IRQF_DISABLED, "EMAC_RX", ndev); |
7ef0a7ee BW |
1531 | if (rc) { |
1532 | dev_err(&pdev->dev, "Cannot request Blackfin MAC RX IRQ!\n"); | |
1533 | rc = -EBUSY; | |
1534 | goto out_err_request_irq; | |
e190d6b1 BW |
1535 | } |
1536 | ||
7ef0a7ee BW |
1537 | rc = register_netdev(ndev); |
1538 | if (rc) { | |
1539 | dev_err(&pdev->dev, "Cannot register net device!\n"); | |
1540 | goto out_err_reg_ndev; | |
e190d6b1 BW |
1541 | } |
1542 | ||
fe92afed BS |
1543 | bfin_mac_hwtstamp_init(ndev); |
1544 | ||
7ef0a7ee BW |
1545 | /* now, print out the card info, in a short format.. */ |
1546 | dev_info(&pdev->dev, "%s, Version %s\n", DRV_DESC, DRV_VERSION); | |
e190d6b1 | 1547 | |
7ef0a7ee | 1548 | return 0; |
e190d6b1 | 1549 | |
7ef0a7ee BW |
1550 | out_err_reg_ndev: |
1551 | free_irq(IRQ_MAC_RX, ndev); | |
1552 | out_err_request_irq: | |
1553 | out_err_mii_probe: | |
298cf9be | 1554 | mdiobus_unregister(lp->mii_bus); |
298cf9be | 1555 | mdiobus_free(lp->mii_bus); |
0e995cd3 | 1556 | out_err_mii_bus_probe: |
7ef0a7ee | 1557 | peripheral_free_list(pin_req); |
7ef0a7ee BW |
1558 | out_err_probe_mac: |
1559 | platform_set_drvdata(pdev, NULL); | |
1560 | free_netdev(ndev); | |
e190d6b1 | 1561 | |
7ef0a7ee | 1562 | return rc; |
e190d6b1 BW |
1563 | } |
1564 | ||
d7b843d3 | 1565 | static int __devexit bfin_mac_remove(struct platform_device *pdev) |
e190d6b1 BW |
1566 | { |
1567 | struct net_device *ndev = platform_get_drvdata(pdev); | |
7ef0a7ee | 1568 | struct bfin_mac_local *lp = netdev_priv(ndev); |
e190d6b1 BW |
1569 | |
1570 | platform_set_drvdata(pdev, NULL); | |
1571 | ||
080c8255 | 1572 | lp->mii_bus->priv = NULL; |
7ef0a7ee | 1573 | |
e190d6b1 BW |
1574 | unregister_netdev(ndev); |
1575 | ||
1576 | free_irq(IRQ_MAC_RX, ndev); | |
1577 | ||
1578 | free_netdev(ndev); | |
1579 | ||
7ef0a7ee | 1580 | peripheral_free_list(pin_req); |
e190d6b1 BW |
1581 | |
1582 | return 0; | |
1583 | } | |
1584 | ||
496a34c2 BW |
1585 | #ifdef CONFIG_PM |
1586 | static int bfin_mac_suspend(struct platform_device *pdev, pm_message_t mesg) | |
e190d6b1 | 1587 | { |
496a34c2 | 1588 | struct net_device *net_dev = platform_get_drvdata(pdev); |
53fd3f28 | 1589 | struct bfin_mac_local *lp = netdev_priv(net_dev); |
496a34c2 | 1590 | |
53fd3f28 MH |
1591 | if (lp->wol) { |
1592 | bfin_write_EMAC_OPMODE((bfin_read_EMAC_OPMODE() & ~TE) | RE); | |
1593 | bfin_write_EMAC_WKUP_CTL(MPKE); | |
1594 | enable_irq_wake(IRQ_MAC_WAKEDET); | |
1595 | } else { | |
1596 | if (netif_running(net_dev)) | |
1597 | bfin_mac_close(net_dev); | |
1598 | } | |
496a34c2 | 1599 | |
e190d6b1 BW |
1600 | return 0; |
1601 | } | |
1602 | ||
1603 | static int bfin_mac_resume(struct platform_device *pdev) | |
1604 | { | |
496a34c2 | 1605 | struct net_device *net_dev = platform_get_drvdata(pdev); |
53fd3f28 | 1606 | struct bfin_mac_local *lp = netdev_priv(net_dev); |
496a34c2 | 1607 | |
53fd3f28 MH |
1608 | if (lp->wol) { |
1609 | bfin_write_EMAC_OPMODE(bfin_read_EMAC_OPMODE() | TE); | |
1610 | bfin_write_EMAC_WKUP_CTL(0); | |
1611 | disable_irq_wake(IRQ_MAC_WAKEDET); | |
1612 | } else { | |
1613 | if (netif_running(net_dev)) | |
1614 | bfin_mac_open(net_dev); | |
1615 | } | |
496a34c2 | 1616 | |
e190d6b1 BW |
1617 | return 0; |
1618 | } | |
496a34c2 BW |
1619 | #else |
1620 | #define bfin_mac_suspend NULL | |
1621 | #define bfin_mac_resume NULL | |
1622 | #endif /* CONFIG_PM */ | |
e190d6b1 | 1623 | |
080c8255 GY |
1624 | static int __devinit bfin_mii_bus_probe(struct platform_device *pdev) |
1625 | { | |
1626 | struct mii_bus *miibus; | |
1627 | int rc, i; | |
1628 | ||
1629 | /* | |
1630 | * We are setting up a network card, | |
1631 | * so set the GPIO pins to Ethernet mode | |
1632 | */ | |
1633 | rc = peripheral_request_list(pin_req, DRV_NAME); | |
1634 | if (rc) { | |
1635 | dev_err(&pdev->dev, "Requesting peripherals failed!\n"); | |
1636 | return rc; | |
1637 | } | |
1638 | ||
1639 | rc = -ENOMEM; | |
1640 | miibus = mdiobus_alloc(); | |
1641 | if (miibus == NULL) | |
1642 | goto out_err_alloc; | |
1643 | miibus->read = bfin_mdiobus_read; | |
1644 | miibus->write = bfin_mdiobus_write; | |
1645 | miibus->reset = bfin_mdiobus_reset; | |
1646 | ||
1647 | miibus->parent = &pdev->dev; | |
1648 | miibus->name = "bfin_mii_bus"; | |
1649 | snprintf(miibus->id, MII_BUS_ID_SIZE, "0"); | |
1650 | miibus->irq = kmalloc(sizeof(int)*PHY_MAX_ADDR, GFP_KERNEL); | |
1651 | if (miibus->irq == NULL) | |
1652 | goto out_err_alloc; | |
1653 | for (i = 0; i < PHY_MAX_ADDR; ++i) | |
1654 | miibus->irq[i] = PHY_POLL; | |
1655 | ||
1656 | rc = mdiobus_register(miibus); | |
1657 | if (rc) { | |
1658 | dev_err(&pdev->dev, "Cannot register MDIO bus!\n"); | |
1659 | goto out_err_mdiobus_register; | |
1660 | } | |
1661 | ||
1662 | platform_set_drvdata(pdev, miibus); | |
1663 | return 0; | |
1664 | ||
1665 | out_err_mdiobus_register: | |
7f267de4 | 1666 | kfree(miibus->irq); |
080c8255 GY |
1667 | mdiobus_free(miibus); |
1668 | out_err_alloc: | |
1669 | peripheral_free_list(pin_req); | |
1670 | ||
1671 | return rc; | |
1672 | } | |
1673 | ||
1674 | static int __devexit bfin_mii_bus_remove(struct platform_device *pdev) | |
1675 | { | |
1676 | struct mii_bus *miibus = platform_get_drvdata(pdev); | |
1677 | platform_set_drvdata(pdev, NULL); | |
1678 | mdiobus_unregister(miibus); | |
7f267de4 | 1679 | kfree(miibus->irq); |
080c8255 GY |
1680 | mdiobus_free(miibus); |
1681 | peripheral_free_list(pin_req); | |
1682 | return 0; | |
1683 | } | |
1684 | ||
1685 | static struct platform_driver bfin_mii_bus_driver = { | |
1686 | .probe = bfin_mii_bus_probe, | |
1687 | .remove = __devexit_p(bfin_mii_bus_remove), | |
1688 | .driver = { | |
1689 | .name = "bfin_mii_bus", | |
1690 | .owner = THIS_MODULE, | |
1691 | }, | |
1692 | }; | |
1693 | ||
e190d6b1 BW |
1694 | static struct platform_driver bfin_mac_driver = { |
1695 | .probe = bfin_mac_probe, | |
d7b843d3 | 1696 | .remove = __devexit_p(bfin_mac_remove), |
e190d6b1 BW |
1697 | .resume = bfin_mac_resume, |
1698 | .suspend = bfin_mac_suspend, | |
1699 | .driver = { | |
72abb461 KS |
1700 | .name = DRV_NAME, |
1701 | .owner = THIS_MODULE, | |
1702 | }, | |
e190d6b1 BW |
1703 | }; |
1704 | ||
1705 | static int __init bfin_mac_init(void) | |
1706 | { | |
080c8255 GY |
1707 | int ret; |
1708 | ret = platform_driver_register(&bfin_mii_bus_driver); | |
1709 | if (!ret) | |
1710 | return platform_driver_register(&bfin_mac_driver); | |
1711 | return -ENODEV; | |
e190d6b1 BW |
1712 | } |
1713 | ||
1714 | module_init(bfin_mac_init); | |
1715 | ||
1716 | static void __exit bfin_mac_cleanup(void) | |
1717 | { | |
1718 | platform_driver_unregister(&bfin_mac_driver); | |
080c8255 | 1719 | platform_driver_unregister(&bfin_mii_bus_driver); |
e190d6b1 BW |
1720 | } |
1721 | ||
1722 | module_exit(bfin_mac_cleanup); | |
72abb461 | 1723 |