Commit | Line | Data |
---|---|---|
e190d6b1 | 1 | /* |
2fb9d6f5 | 2 | * Blackfin On-Chip MAC Driver |
e190d6b1 | 3 | * |
2fb9d6f5 | 4 | * Copyright 2004-2007 Analog Devices Inc. |
e190d6b1 | 5 | * |
2fb9d6f5 | 6 | * Enter bugs at http://blackfin.uclinux.org/ |
e190d6b1 | 7 | * |
2fb9d6f5 | 8 | * Licensed under the GPL-2 or later. |
e190d6b1 BW |
9 | */ |
10 | ||
11 | #include <linux/init.h> | |
12 | #include <linux/module.h> | |
13 | #include <linux/kernel.h> | |
14 | #include <linux/sched.h> | |
15 | #include <linux/slab.h> | |
16 | #include <linux/delay.h> | |
17 | #include <linux/timer.h> | |
18 | #include <linux/errno.h> | |
19 | #include <linux/irq.h> | |
20 | #include <linux/io.h> | |
21 | #include <linux/ioport.h> | |
22 | #include <linux/crc32.h> | |
23 | #include <linux/device.h> | |
24 | #include <linux/spinlock.h> | |
25 | #include <linux/ethtool.h> | |
26 | #include <linux/mii.h> | |
4ae5a3ad | 27 | #include <linux/phy.h> |
e190d6b1 BW |
28 | #include <linux/netdevice.h> |
29 | #include <linux/etherdevice.h> | |
30 | #include <linux/skbuff.h> | |
e190d6b1 | 31 | #include <linux/platform_device.h> |
e190d6b1 BW |
32 | |
33 | #include <asm/dma.h> | |
34 | #include <linux/dma-mapping.h> | |
35 | ||
36 | #include <asm/blackfin.h> | |
37 | #include <asm/cacheflush.h> | |
38 | #include <asm/portmux.h> | |
39 | ||
40 | #include "bfin_mac.h" | |
41 | ||
42 | #define DRV_NAME "bfin_mac" | |
43 | #define DRV_VERSION "1.1" | |
44 | #define DRV_AUTHOR "Bryan Wu, Luke Yang" | |
7ef0a7ee | 45 | #define DRV_DESC "Blackfin on-chip Ethernet MAC driver" |
e190d6b1 BW |
46 | |
47 | MODULE_AUTHOR(DRV_AUTHOR); | |
48 | MODULE_LICENSE("GPL"); | |
49 | MODULE_DESCRIPTION(DRV_DESC); | |
72abb461 | 50 | MODULE_ALIAS("platform:bfin_mac"); |
e190d6b1 BW |
51 | |
52 | #if defined(CONFIG_BFIN_MAC_USE_L1) | |
53 | # define bfin_mac_alloc(dma_handle, size) l1_data_sram_zalloc(size) | |
54 | # define bfin_mac_free(dma_handle, ptr) l1_data_sram_free(ptr) | |
55 | #else | |
56 | # define bfin_mac_alloc(dma_handle, size) \ | |
57 | dma_alloc_coherent(NULL, size, dma_handle, GFP_KERNEL) | |
58 | # define bfin_mac_free(dma_handle, ptr) \ | |
59 | dma_free_coherent(NULL, sizeof(*ptr), ptr, dma_handle) | |
60 | #endif | |
61 | ||
62 | #define PKT_BUF_SZ 1580 | |
63 | ||
64 | #define MAX_TIMEOUT_CNT 500 | |
65 | ||
66 | /* pointers to maintain transmit list */ | |
67 | static struct net_dma_desc_tx *tx_list_head; | |
68 | static struct net_dma_desc_tx *tx_list_tail; | |
69 | static struct net_dma_desc_rx *rx_list_head; | |
70 | static struct net_dma_desc_rx *rx_list_tail; | |
71 | static struct net_dma_desc_rx *current_rx_ptr; | |
72 | static struct net_dma_desc_tx *current_tx_ptr; | |
73 | static struct net_dma_desc_tx *tx_desc; | |
74 | static struct net_dma_desc_rx *rx_desc; | |
75 | ||
7ef0a7ee BW |
76 | #if defined(CONFIG_BFIN_MAC_RMII) |
77 | static u16 pin_req[] = P_RMII0; | |
78 | #else | |
79 | static u16 pin_req[] = P_MII0; | |
80 | #endif | |
81 | ||
82 | static void bfin_mac_disable(void); | |
83 | static void bfin_mac_enable(void); | |
4ae5a3ad | 84 | |
e190d6b1 BW |
85 | static void desc_list_free(void) |
86 | { | |
87 | struct net_dma_desc_rx *r; | |
88 | struct net_dma_desc_tx *t; | |
89 | int i; | |
90 | #if !defined(CONFIG_BFIN_MAC_USE_L1) | |
91 | dma_addr_t dma_handle = 0; | |
92 | #endif | |
93 | ||
94 | if (tx_desc) { | |
95 | t = tx_list_head; | |
96 | for (i = 0; i < CONFIG_BFIN_TX_DESC_NUM; i++) { | |
97 | if (t) { | |
98 | if (t->skb) { | |
99 | dev_kfree_skb(t->skb); | |
100 | t->skb = NULL; | |
101 | } | |
102 | t = t->next; | |
103 | } | |
104 | } | |
105 | bfin_mac_free(dma_handle, tx_desc); | |
106 | } | |
107 | ||
108 | if (rx_desc) { | |
109 | r = rx_list_head; | |
110 | for (i = 0; i < CONFIG_BFIN_RX_DESC_NUM; i++) { | |
111 | if (r) { | |
112 | if (r->skb) { | |
113 | dev_kfree_skb(r->skb); | |
114 | r->skb = NULL; | |
115 | } | |
116 | r = r->next; | |
117 | } | |
118 | } | |
119 | bfin_mac_free(dma_handle, rx_desc); | |
120 | } | |
121 | } | |
122 | ||
123 | static int desc_list_init(void) | |
124 | { | |
125 | int i; | |
126 | struct sk_buff *new_skb; | |
127 | #if !defined(CONFIG_BFIN_MAC_USE_L1) | |
128 | /* | |
129 | * This dma_handle is useless in Blackfin dma_alloc_coherent(). | |
130 | * The real dma handler is the return value of dma_alloc_coherent(). | |
131 | */ | |
132 | dma_addr_t dma_handle; | |
133 | #endif | |
134 | ||
135 | tx_desc = bfin_mac_alloc(&dma_handle, | |
136 | sizeof(struct net_dma_desc_tx) * | |
137 | CONFIG_BFIN_TX_DESC_NUM); | |
138 | if (tx_desc == NULL) | |
139 | goto init_error; | |
140 | ||
141 | rx_desc = bfin_mac_alloc(&dma_handle, | |
142 | sizeof(struct net_dma_desc_rx) * | |
143 | CONFIG_BFIN_RX_DESC_NUM); | |
144 | if (rx_desc == NULL) | |
145 | goto init_error; | |
146 | ||
147 | /* init tx_list */ | |
148 | tx_list_head = tx_list_tail = tx_desc; | |
149 | ||
150 | for (i = 0; i < CONFIG_BFIN_TX_DESC_NUM; i++) { | |
151 | struct net_dma_desc_tx *t = tx_desc + i; | |
152 | struct dma_descriptor *a = &(t->desc_a); | |
153 | struct dma_descriptor *b = &(t->desc_b); | |
154 | ||
155 | /* | |
156 | * disable DMA | |
157 | * read from memory WNR = 0 | |
158 | * wordsize is 32 bits | |
159 | * 6 half words is desc size | |
160 | * large desc flow | |
161 | */ | |
162 | a->config = WDSIZE_32 | NDSIZE_6 | DMAFLOW_LARGE; | |
163 | a->start_addr = (unsigned long)t->packet; | |
164 | a->x_count = 0; | |
165 | a->next_dma_desc = b; | |
166 | ||
167 | /* | |
168 | * enabled DMA | |
169 | * write to memory WNR = 1 | |
170 | * wordsize is 32 bits | |
171 | * disable interrupt | |
172 | * 6 half words is desc size | |
173 | * large desc flow | |
174 | */ | |
175 | b->config = DMAEN | WNR | WDSIZE_32 | NDSIZE_6 | DMAFLOW_LARGE; | |
176 | b->start_addr = (unsigned long)(&(t->status)); | |
177 | b->x_count = 0; | |
178 | ||
179 | t->skb = NULL; | |
180 | tx_list_tail->desc_b.next_dma_desc = a; | |
181 | tx_list_tail->next = t; | |
182 | tx_list_tail = t; | |
183 | } | |
184 | tx_list_tail->next = tx_list_head; /* tx_list is a circle */ | |
185 | tx_list_tail->desc_b.next_dma_desc = &(tx_list_head->desc_a); | |
186 | current_tx_ptr = tx_list_head; | |
187 | ||
188 | /* init rx_list */ | |
189 | rx_list_head = rx_list_tail = rx_desc; | |
190 | ||
191 | for (i = 0; i < CONFIG_BFIN_RX_DESC_NUM; i++) { | |
192 | struct net_dma_desc_rx *r = rx_desc + i; | |
193 | struct dma_descriptor *a = &(r->desc_a); | |
194 | struct dma_descriptor *b = &(r->desc_b); | |
195 | ||
196 | /* allocate a new skb for next time receive */ | |
197 | new_skb = dev_alloc_skb(PKT_BUF_SZ + 2); | |
198 | if (!new_skb) { | |
199 | printk(KERN_NOTICE DRV_NAME | |
200 | ": init: low on mem - packet dropped\n"); | |
201 | goto init_error; | |
202 | } | |
203 | skb_reserve(new_skb, 2); | |
204 | r->skb = new_skb; | |
205 | ||
206 | /* | |
207 | * enabled DMA | |
208 | * write to memory WNR = 1 | |
209 | * wordsize is 32 bits | |
210 | * disable interrupt | |
211 | * 6 half words is desc size | |
212 | * large desc flow | |
213 | */ | |
214 | a->config = DMAEN | WNR | WDSIZE_32 | NDSIZE_6 | DMAFLOW_LARGE; | |
215 | /* since RXDWA is enabled */ | |
216 | a->start_addr = (unsigned long)new_skb->data - 2; | |
217 | a->x_count = 0; | |
218 | a->next_dma_desc = b; | |
219 | ||
220 | /* | |
221 | * enabled DMA | |
222 | * write to memory WNR = 1 | |
223 | * wordsize is 32 bits | |
224 | * enable interrupt | |
225 | * 6 half words is desc size | |
226 | * large desc flow | |
227 | */ | |
228 | b->config = DMAEN | WNR | WDSIZE_32 | DI_EN | | |
229 | NDSIZE_6 | DMAFLOW_LARGE; | |
230 | b->start_addr = (unsigned long)(&(r->status)); | |
231 | b->x_count = 0; | |
232 | ||
233 | rx_list_tail->desc_b.next_dma_desc = a; | |
234 | rx_list_tail->next = r; | |
235 | rx_list_tail = r; | |
236 | } | |
237 | rx_list_tail->next = rx_list_head; /* rx_list is a circle */ | |
238 | rx_list_tail->desc_b.next_dma_desc = &(rx_list_head->desc_a); | |
239 | current_rx_ptr = rx_list_head; | |
240 | ||
241 | return 0; | |
242 | ||
243 | init_error: | |
244 | desc_list_free(); | |
245 | printk(KERN_ERR DRV_NAME ": kmalloc failed\n"); | |
246 | return -ENOMEM; | |
247 | } | |
248 | ||
249 | ||
250 | /*---PHY CONTROL AND CONFIGURATION-----------------------------------------*/ | |
251 | ||
4ae5a3ad BW |
252 | /* |
253 | * MII operations | |
254 | */ | |
e190d6b1 | 255 | /* Wait until the previous MDC/MDIO transaction has completed */ |
4ae5a3ad | 256 | static void mdio_poll(void) |
e190d6b1 BW |
257 | { |
258 | int timeout_cnt = MAX_TIMEOUT_CNT; | |
259 | ||
260 | /* poll the STABUSY bit */ | |
261 | while ((bfin_read_EMAC_STAADD()) & STABUSY) { | |
6db9e461 | 262 | udelay(1); |
e190d6b1 BW |
263 | if (timeout_cnt-- < 0) { |
264 | printk(KERN_ERR DRV_NAME | |
265 | ": wait MDC/MDIO transaction to complete timeout\n"); | |
266 | break; | |
267 | } | |
268 | } | |
269 | } | |
270 | ||
271 | /* Read an off-chip register in a PHY through the MDC/MDIO port */ | |
4ae5a3ad | 272 | static int mdiobus_read(struct mii_bus *bus, int phy_addr, int regnum) |
e190d6b1 | 273 | { |
4ae5a3ad BW |
274 | mdio_poll(); |
275 | ||
e190d6b1 | 276 | /* read mode */ |
4ae5a3ad BW |
277 | bfin_write_EMAC_STAADD(SET_PHYAD((u16) phy_addr) | |
278 | SET_REGAD((u16) regnum) | | |
e190d6b1 | 279 | STABUSY); |
e190d6b1 | 280 | |
4ae5a3ad BW |
281 | mdio_poll(); |
282 | ||
283 | return (int) bfin_read_EMAC_STADAT(); | |
e190d6b1 BW |
284 | } |
285 | ||
286 | /* Write an off-chip register in a PHY through the MDC/MDIO port */ | |
4ae5a3ad BW |
287 | static int mdiobus_write(struct mii_bus *bus, int phy_addr, int regnum, |
288 | u16 value) | |
e190d6b1 | 289 | { |
4ae5a3ad BW |
290 | mdio_poll(); |
291 | ||
292 | bfin_write_EMAC_STADAT((u32) value); | |
e190d6b1 BW |
293 | |
294 | /* write mode */ | |
4ae5a3ad BW |
295 | bfin_write_EMAC_STAADD(SET_PHYAD((u16) phy_addr) | |
296 | SET_REGAD((u16) regnum) | | |
e190d6b1 BW |
297 | STAOP | |
298 | STABUSY); | |
299 | ||
4ae5a3ad BW |
300 | mdio_poll(); |
301 | ||
302 | return 0; | |
e190d6b1 BW |
303 | } |
304 | ||
4ae5a3ad | 305 | static int mdiobus_reset(struct mii_bus *bus) |
e190d6b1 | 306 | { |
4ae5a3ad | 307 | return 0; |
e190d6b1 BW |
308 | } |
309 | ||
7ef0a7ee | 310 | static void bfin_mac_adjust_link(struct net_device *dev) |
e190d6b1 | 311 | { |
7ef0a7ee | 312 | struct bfin_mac_local *lp = netdev_priv(dev); |
4ae5a3ad BW |
313 | struct phy_device *phydev = lp->phydev; |
314 | unsigned long flags; | |
315 | int new_state = 0; | |
316 | ||
317 | spin_lock_irqsave(&lp->lock, flags); | |
318 | if (phydev->link) { | |
319 | /* Now we make sure that we can be in full duplex mode. | |
320 | * If not, we operate in half-duplex mode. */ | |
321 | if (phydev->duplex != lp->old_duplex) { | |
322 | u32 opmode = bfin_read_EMAC_OPMODE(); | |
323 | new_state = 1; | |
324 | ||
325 | if (phydev->duplex) | |
326 | opmode |= FDMODE; | |
327 | else | |
328 | opmode &= ~(FDMODE); | |
329 | ||
330 | bfin_write_EMAC_OPMODE(opmode); | |
331 | lp->old_duplex = phydev->duplex; | |
332 | } | |
e190d6b1 | 333 | |
4ae5a3ad BW |
334 | if (phydev->speed != lp->old_speed) { |
335 | #if defined(CONFIG_BFIN_MAC_RMII) | |
336 | u32 opmode = bfin_read_EMAC_OPMODE(); | |
4ae5a3ad BW |
337 | switch (phydev->speed) { |
338 | case 10: | |
339 | opmode |= RMII_10; | |
340 | break; | |
341 | case 100: | |
342 | opmode &= ~(RMII_10); | |
343 | break; | |
344 | default: | |
345 | printk(KERN_WARNING | |
346 | "%s: Ack! Speed (%d) is not 10/100!\n", | |
347 | DRV_NAME, phydev->speed); | |
348 | break; | |
349 | } | |
350 | bfin_write_EMAC_OPMODE(opmode); | |
4ae5a3ad | 351 | #endif |
e190d6b1 | 352 | |
4ae5a3ad BW |
353 | new_state = 1; |
354 | lp->old_speed = phydev->speed; | |
355 | } | |
e190d6b1 | 356 | |
4ae5a3ad BW |
357 | if (!lp->old_link) { |
358 | new_state = 1; | |
359 | lp->old_link = 1; | |
360 | netif_schedule(dev); | |
361 | } | |
362 | } else if (lp->old_link) { | |
363 | new_state = 1; | |
364 | lp->old_link = 0; | |
365 | lp->old_speed = 0; | |
366 | lp->old_duplex = -1; | |
e190d6b1 BW |
367 | } |
368 | ||
4ae5a3ad BW |
369 | if (new_state) { |
370 | u32 opmode = bfin_read_EMAC_OPMODE(); | |
371 | phy_print_status(phydev); | |
372 | pr_debug("EMAC_OPMODE = 0x%08x\n", opmode); | |
e190d6b1 | 373 | } |
4ae5a3ad BW |
374 | |
375 | spin_unlock_irqrestore(&lp->lock, flags); | |
e190d6b1 BW |
376 | } |
377 | ||
7cc8f381 BW |
378 | /* MDC = 2.5 MHz */ |
379 | #define MDC_CLK 2500000 | |
380 | ||
4ae5a3ad | 381 | static int mii_probe(struct net_device *dev) |
e190d6b1 | 382 | { |
7ef0a7ee | 383 | struct bfin_mac_local *lp = netdev_priv(dev); |
4ae5a3ad BW |
384 | struct phy_device *phydev = NULL; |
385 | unsigned short sysctl; | |
386 | int i; | |
7cc8f381 | 387 | u32 sclk, mdc_div; |
e190d6b1 | 388 | |
4ae5a3ad | 389 | /* Enable PHY output early */ |
e190d6b1 BW |
390 | if (!(bfin_read_VR_CTL() & PHYCLKOE)) |
391 | bfin_write_VR_CTL(bfin_read_VR_CTL() | PHYCLKOE); | |
392 | ||
7cc8f381 BW |
393 | sclk = get_sclk(); |
394 | mdc_div = ((sclk / MDC_CLK) / 2) - 1; | |
395 | ||
4ae5a3ad | 396 | sysctl = bfin_read_EMAC_SYSCTL(); |
9dc7f30e | 397 | sysctl = (sysctl & ~MDCDIV) | SET_MDCDIV(mdc_div); |
e190d6b1 | 398 | bfin_write_EMAC_SYSCTL(sysctl); |
e190d6b1 | 399 | |
4ae5a3ad BW |
400 | /* search for connect PHY device */ |
401 | for (i = 0; i < PHY_MAX_ADDR; i++) { | |
402 | struct phy_device *const tmp_phydev = lp->mii_bus.phy_map[i]; | |
e190d6b1 | 403 | |
4ae5a3ad BW |
404 | if (!tmp_phydev) |
405 | continue; /* no PHY here... */ | |
e190d6b1 | 406 | |
4ae5a3ad BW |
407 | phydev = tmp_phydev; |
408 | break; /* found it */ | |
409 | } | |
410 | ||
411 | /* now we are supposed to have a proper phydev, to attach to... */ | |
412 | if (!phydev) { | |
413 | printk(KERN_INFO "%s: Don't found any phy device at all\n", | |
414 | dev->name); | |
415 | return -ENODEV; | |
e190d6b1 BW |
416 | } |
417 | ||
418 | #if defined(CONFIG_BFIN_MAC_RMII) | |
7ef0a7ee | 419 | phydev = phy_connect(dev, phydev->dev.bus_id, &bfin_mac_adjust_link, 0, |
4ae5a3ad BW |
420 | PHY_INTERFACE_MODE_RMII); |
421 | #else | |
7ef0a7ee | 422 | phydev = phy_connect(dev, phydev->dev.bus_id, &bfin_mac_adjust_link, 0, |
4ae5a3ad | 423 | PHY_INTERFACE_MODE_MII); |
e190d6b1 BW |
424 | #endif |
425 | ||
4ae5a3ad BW |
426 | if (IS_ERR(phydev)) { |
427 | printk(KERN_ERR "%s: Could not attach to PHY\n", dev->name); | |
428 | return PTR_ERR(phydev); | |
429 | } | |
430 | ||
431 | /* mask with MAC supported features */ | |
432 | phydev->supported &= (SUPPORTED_10baseT_Half | |
433 | | SUPPORTED_10baseT_Full | |
434 | | SUPPORTED_100baseT_Half | |
435 | | SUPPORTED_100baseT_Full | |
436 | | SUPPORTED_Autoneg | |
437 | | SUPPORTED_Pause | SUPPORTED_Asym_Pause | |
438 | | SUPPORTED_MII | |
439 | | SUPPORTED_TP); | |
440 | ||
441 | phydev->advertising = phydev->supported; | |
442 | ||
443 | lp->old_link = 0; | |
444 | lp->old_speed = 0; | |
445 | lp->old_duplex = -1; | |
446 | lp->phydev = phydev; | |
447 | ||
448 | printk(KERN_INFO "%s: attached PHY driver [%s] " | |
7cc8f381 BW |
449 | "(mii_bus:phy_addr=%s, irq=%d, mdc_clk=%dHz(mdc_div=%d)" |
450 | "@sclk=%dMHz)\n", | |
451 | DRV_NAME, phydev->drv->name, phydev->dev.bus_id, phydev->irq, | |
452 | MDC_CLK, mdc_div, sclk/1000000); | |
4ae5a3ad BW |
453 | |
454 | return 0; | |
455 | } | |
456 | ||
457 | /**************************************************************************/ | |
458 | void setup_system_regs(struct net_device *dev) | |
459 | { | |
460 | unsigned short sysctl; | |
461 | ||
462 | /* | |
463 | * Odd word alignment for Receive Frame DMA word | |
464 | * Configure checksum support and rcve frame word alignment | |
465 | */ | |
466 | sysctl = bfin_read_EMAC_SYSCTL(); | |
467 | #if defined(BFIN_MAC_CSUM_OFFLOAD) | |
468 | sysctl |= RXDWA | RXCKS; | |
469 | #else | |
470 | sysctl |= RXDWA; | |
471 | #endif | |
472 | bfin_write_EMAC_SYSCTL(sysctl); | |
e190d6b1 BW |
473 | |
474 | bfin_write_EMAC_MMC_CTL(RSTC | CROLL); | |
475 | ||
476 | /* Initialize the TX DMA channel registers */ | |
477 | bfin_write_DMA2_X_COUNT(0); | |
478 | bfin_write_DMA2_X_MODIFY(4); | |
479 | bfin_write_DMA2_Y_COUNT(0); | |
480 | bfin_write_DMA2_Y_MODIFY(0); | |
481 | ||
482 | /* Initialize the RX DMA channel registers */ | |
483 | bfin_write_DMA1_X_COUNT(0); | |
484 | bfin_write_DMA1_X_MODIFY(4); | |
485 | bfin_write_DMA1_Y_COUNT(0); | |
486 | bfin_write_DMA1_Y_MODIFY(0); | |
487 | } | |
488 | ||
73f83182 | 489 | static void setup_mac_addr(u8 *mac_addr) |
e190d6b1 BW |
490 | { |
491 | u32 addr_low = le32_to_cpu(*(__le32 *) & mac_addr[0]); | |
492 | u16 addr_hi = le16_to_cpu(*(__le16 *) & mac_addr[4]); | |
493 | ||
494 | /* this depends on a little-endian machine */ | |
495 | bfin_write_EMAC_ADDRLO(addr_low); | |
496 | bfin_write_EMAC_ADDRHI(addr_hi); | |
497 | } | |
498 | ||
7ef0a7ee | 499 | static int bfin_mac_set_mac_address(struct net_device *dev, void *p) |
73f83182 AL |
500 | { |
501 | struct sockaddr *addr = p; | |
502 | if (netif_running(dev)) | |
503 | return -EBUSY; | |
504 | memcpy(dev->dev_addr, addr->sa_data, dev->addr_len); | |
505 | setup_mac_addr(dev->dev_addr); | |
506 | return 0; | |
507 | } | |
508 | ||
e190d6b1 BW |
509 | static void adjust_tx_list(void) |
510 | { | |
511 | int timeout_cnt = MAX_TIMEOUT_CNT; | |
512 | ||
513 | if (tx_list_head->status.status_word != 0 | |
514 | && current_tx_ptr != tx_list_head) { | |
515 | goto adjust_head; /* released something, just return; */ | |
516 | } | |
517 | ||
518 | /* | |
519 | * if nothing released, check wait condition | |
520 | * current's next can not be the head, | |
521 | * otherwise the dma will not stop as we want | |
522 | */ | |
523 | if (current_tx_ptr->next->next == tx_list_head) { | |
524 | while (tx_list_head->status.status_word == 0) { | |
6db9e461 | 525 | mdelay(1); |
e190d6b1 BW |
526 | if (tx_list_head->status.status_word != 0 |
527 | || !(bfin_read_DMA2_IRQ_STATUS() & 0x08)) { | |
528 | goto adjust_head; | |
529 | } | |
530 | if (timeout_cnt-- < 0) { | |
531 | printk(KERN_ERR DRV_NAME | |
532 | ": wait for adjust tx list head timeout\n"); | |
533 | break; | |
534 | } | |
535 | } | |
536 | if (tx_list_head->status.status_word != 0) { | |
537 | goto adjust_head; | |
538 | } | |
539 | } | |
540 | ||
541 | return; | |
542 | ||
543 | adjust_head: | |
544 | do { | |
545 | tx_list_head->desc_a.config &= ~DMAEN; | |
546 | tx_list_head->status.status_word = 0; | |
547 | if (tx_list_head->skb) { | |
548 | dev_kfree_skb(tx_list_head->skb); | |
549 | tx_list_head->skb = NULL; | |
550 | } else { | |
551 | printk(KERN_ERR DRV_NAME | |
552 | ": no sk_buff in a transmitted frame!\n"); | |
553 | } | |
554 | tx_list_head = tx_list_head->next; | |
555 | } while (tx_list_head->status.status_word != 0 | |
556 | && current_tx_ptr != tx_list_head); | |
557 | return; | |
558 | ||
559 | } | |
560 | ||
7ef0a7ee | 561 | static int bfin_mac_hard_start_xmit(struct sk_buff *skb, |
e190d6b1 BW |
562 | struct net_device *dev) |
563 | { | |
e190d6b1 BW |
564 | unsigned int data; |
565 | ||
566 | current_tx_ptr->skb = skb; | |
567 | ||
568 | /* | |
569 | * Is skb->data always 16-bit aligned? | |
570 | * Do we need to memcpy((char *)(tail->packet + 2), skb->data, len)? | |
571 | */ | |
572 | if ((((unsigned int)(skb->data)) & 0x02) == 2) { | |
573 | /* move skb->data to current_tx_ptr payload */ | |
574 | data = (unsigned int)(skb->data) - 2; | |
575 | *((unsigned short *)data) = (unsigned short)(skb->len); | |
576 | current_tx_ptr->desc_a.start_addr = (unsigned long)data; | |
577 | /* this is important! */ | |
578 | blackfin_dcache_flush_range(data, (data + (skb->len)) + 2); | |
579 | ||
580 | } else { | |
581 | *((unsigned short *)(current_tx_ptr->packet)) = | |
582 | (unsigned short)(skb->len); | |
583 | memcpy((char *)(current_tx_ptr->packet + 2), skb->data, | |
584 | (skb->len)); | |
585 | current_tx_ptr->desc_a.start_addr = | |
586 | (unsigned long)current_tx_ptr->packet; | |
587 | if (current_tx_ptr->status.status_word != 0) | |
588 | current_tx_ptr->status.status_word = 0; | |
589 | blackfin_dcache_flush_range((unsigned int)current_tx_ptr-> | |
590 | packet, | |
591 | (unsigned int)(current_tx_ptr-> | |
592 | packet + skb->len) + | |
593 | 2); | |
594 | } | |
595 | ||
596 | /* enable this packet's dma */ | |
597 | current_tx_ptr->desc_a.config |= DMAEN; | |
598 | ||
599 | /* tx dma is running, just return */ | |
600 | if (bfin_read_DMA2_IRQ_STATUS() & 0x08) | |
601 | goto out; | |
602 | ||
603 | /* tx dma is not running */ | |
604 | bfin_write_DMA2_NEXT_DESC_PTR(&(current_tx_ptr->desc_a)); | |
605 | /* dma enabled, read from memory, size is 6 */ | |
606 | bfin_write_DMA2_CONFIG(current_tx_ptr->desc_a.config); | |
607 | /* Turn on the EMAC tx */ | |
608 | bfin_write_EMAC_OPMODE(bfin_read_EMAC_OPMODE() | TE); | |
609 | ||
610 | out: | |
611 | adjust_tx_list(); | |
612 | current_tx_ptr = current_tx_ptr->next; | |
613 | dev->trans_start = jiffies; | |
09f75cd7 JG |
614 | dev->stats.tx_packets++; |
615 | dev->stats.tx_bytes += (skb->len); | |
e190d6b1 BW |
616 | return 0; |
617 | } | |
618 | ||
7ef0a7ee | 619 | static void bfin_mac_rx(struct net_device *dev) |
e190d6b1 BW |
620 | { |
621 | struct sk_buff *skb, *new_skb; | |
e190d6b1 BW |
622 | unsigned short len; |
623 | ||
624 | /* allocate a new skb for next time receive */ | |
625 | skb = current_rx_ptr->skb; | |
626 | new_skb = dev_alloc_skb(PKT_BUF_SZ + 2); | |
627 | if (!new_skb) { | |
628 | printk(KERN_NOTICE DRV_NAME | |
629 | ": rx: low on mem - packet dropped\n"); | |
09f75cd7 | 630 | dev->stats.rx_dropped++; |
e190d6b1 BW |
631 | goto out; |
632 | } | |
633 | /* reserve 2 bytes for RXDWA padding */ | |
634 | skb_reserve(new_skb, 2); | |
635 | current_rx_ptr->skb = new_skb; | |
636 | current_rx_ptr->desc_a.start_addr = (unsigned long)new_skb->data - 2; | |
637 | ||
6e01d1a4 AD |
638 | /* Invidate the data cache of skb->data range when it is write back |
639 | * cache. It will prevent overwritting the new data from DMA | |
640 | */ | |
641 | blackfin_dcache_invalidate_range((unsigned long)new_skb->head, | |
642 | (unsigned long)new_skb->end); | |
643 | ||
e190d6b1 BW |
644 | len = (unsigned short)((current_rx_ptr->status.status_word) & RX_FRLEN); |
645 | skb_put(skb, len); | |
646 | blackfin_dcache_invalidate_range((unsigned long)skb->head, | |
647 | (unsigned long)skb->tail); | |
648 | ||
649 | dev->last_rx = jiffies; | |
650 | skb->dev = dev; | |
651 | skb->protocol = eth_type_trans(skb, dev); | |
652 | #if defined(BFIN_MAC_CSUM_OFFLOAD) | |
653 | skb->csum = current_rx_ptr->status.ip_payload_csum; | |
00ff49a9 | 654 | skb->ip_summed = CHECKSUM_COMPLETE; |
e190d6b1 BW |
655 | #endif |
656 | ||
657 | netif_rx(skb); | |
09f75cd7 JG |
658 | dev->stats.rx_packets++; |
659 | dev->stats.rx_bytes += len; | |
e190d6b1 BW |
660 | current_rx_ptr->status.status_word = 0x00000000; |
661 | current_rx_ptr = current_rx_ptr->next; | |
662 | ||
663 | out: | |
664 | return; | |
665 | } | |
666 | ||
667 | /* interrupt routine to handle rx and error signal */ | |
7ef0a7ee | 668 | static irqreturn_t bfin_mac_interrupt(int irq, void *dev_id) |
e190d6b1 BW |
669 | { |
670 | struct net_device *dev = dev_id; | |
671 | int number = 0; | |
672 | ||
673 | get_one_packet: | |
674 | if (current_rx_ptr->status.status_word == 0) { | |
675 | /* no more new packet received */ | |
676 | if (number == 0) { | |
677 | if (current_rx_ptr->next->status.status_word != 0) { | |
678 | current_rx_ptr = current_rx_ptr->next; | |
679 | goto real_rx; | |
680 | } | |
681 | } | |
682 | bfin_write_DMA1_IRQ_STATUS(bfin_read_DMA1_IRQ_STATUS() | | |
683 | DMA_DONE | DMA_ERR); | |
684 | return IRQ_HANDLED; | |
685 | } | |
686 | ||
687 | real_rx: | |
7ef0a7ee | 688 | bfin_mac_rx(dev); |
e190d6b1 BW |
689 | number++; |
690 | goto get_one_packet; | |
691 | } | |
692 | ||
693 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
7ef0a7ee | 694 | static void bfin_mac_poll(struct net_device *dev) |
e190d6b1 BW |
695 | { |
696 | disable_irq(IRQ_MAC_RX); | |
7ef0a7ee | 697 | bfin_mac_interrupt(IRQ_MAC_RX, dev); |
e190d6b1 BW |
698 | enable_irq(IRQ_MAC_RX); |
699 | } | |
700 | #endif /* CONFIG_NET_POLL_CONTROLLER */ | |
701 | ||
7ef0a7ee | 702 | static void bfin_mac_disable(void) |
e190d6b1 BW |
703 | { |
704 | unsigned int opmode; | |
705 | ||
706 | opmode = bfin_read_EMAC_OPMODE(); | |
707 | opmode &= (~RE); | |
708 | opmode &= (~TE); | |
709 | /* Turn off the EMAC */ | |
710 | bfin_write_EMAC_OPMODE(opmode); | |
711 | } | |
712 | ||
713 | /* | |
714 | * Enable Interrupts, Receive, and Transmit | |
715 | */ | |
7ef0a7ee | 716 | static void bfin_mac_enable(void) |
e190d6b1 BW |
717 | { |
718 | u32 opmode; | |
719 | ||
4ae5a3ad | 720 | pr_debug("%s: %s\n", DRV_NAME, __FUNCTION__); |
e190d6b1 BW |
721 | |
722 | /* Set RX DMA */ | |
723 | bfin_write_DMA1_NEXT_DESC_PTR(&(rx_list_head->desc_a)); | |
724 | bfin_write_DMA1_CONFIG(rx_list_head->desc_a.config); | |
725 | ||
726 | /* Wait MII done */ | |
4ae5a3ad | 727 | mdio_poll(); |
e190d6b1 BW |
728 | |
729 | /* We enable only RX here */ | |
730 | /* ASTP : Enable Automatic Pad Stripping | |
731 | PR : Promiscuous Mode for test | |
732 | PSF : Receive frames with total length less than 64 bytes. | |
733 | FDMODE : Full Duplex Mode | |
734 | LB : Internal Loopback for test | |
735 | RE : Receiver Enable */ | |
736 | opmode = bfin_read_EMAC_OPMODE(); | |
737 | if (opmode & FDMODE) | |
738 | opmode |= PSF; | |
739 | else | |
740 | opmode |= DRO | DC | PSF; | |
741 | opmode |= RE; | |
742 | ||
743 | #if defined(CONFIG_BFIN_MAC_RMII) | |
744 | opmode |= RMII; /* For Now only 100MBit are supported */ | |
6893ff1c | 745 | #if (defined(CONFIG_BF537) || defined(CONFIG_BF536)) && CONFIG_BF_REV_0_2 |
e190d6b1 BW |
746 | opmode |= TE; |
747 | #endif | |
748 | #endif | |
749 | /* Turn on the EMAC rx */ | |
750 | bfin_write_EMAC_OPMODE(opmode); | |
e190d6b1 BW |
751 | } |
752 | ||
753 | /* Our watchdog timed out. Called by the networking layer */ | |
7ef0a7ee | 754 | static void bfin_mac_timeout(struct net_device *dev) |
e190d6b1 BW |
755 | { |
756 | pr_debug("%s: %s\n", dev->name, __FUNCTION__); | |
757 | ||
7ef0a7ee | 758 | bfin_mac_disable(); |
e190d6b1 BW |
759 | |
760 | /* reset tx queue */ | |
761 | tx_list_tail = tx_list_head->next; | |
762 | ||
7ef0a7ee | 763 | bfin_mac_enable(); |
e190d6b1 BW |
764 | |
765 | /* We can accept TX packets again */ | |
766 | dev->trans_start = jiffies; | |
767 | netif_wake_queue(dev); | |
768 | } | |
769 | ||
7ef0a7ee | 770 | static void bfin_mac_multicast_hash(struct net_device *dev) |
775919bc AW |
771 | { |
772 | u32 emac_hashhi, emac_hashlo; | |
773 | struct dev_mc_list *dmi = dev->mc_list; | |
774 | char *addrs; | |
775 | int i; | |
776 | u32 crc; | |
777 | ||
778 | emac_hashhi = emac_hashlo = 0; | |
779 | ||
780 | for (i = 0; i < dev->mc_count; i++) { | |
781 | addrs = dmi->dmi_addr; | |
782 | dmi = dmi->next; | |
783 | ||
784 | /* skip non-multicast addresses */ | |
785 | if (!(*addrs & 1)) | |
786 | continue; | |
787 | ||
788 | crc = ether_crc(ETH_ALEN, addrs); | |
789 | crc >>= 26; | |
790 | ||
791 | if (crc & 0x20) | |
792 | emac_hashhi |= 1 << (crc & 0x1f); | |
793 | else | |
794 | emac_hashlo |= 1 << (crc & 0x1f); | |
795 | } | |
796 | ||
797 | bfin_write_EMAC_HASHHI(emac_hashhi); | |
798 | bfin_write_EMAC_HASHLO(emac_hashlo); | |
799 | ||
800 | return; | |
801 | } | |
802 | ||
e190d6b1 BW |
803 | /* |
804 | * This routine will, depending on the values passed to it, | |
805 | * either make it accept multicast packets, go into | |
806 | * promiscuous mode (for TCPDUMP and cousins) or accept | |
807 | * a select set of multicast packets | |
808 | */ | |
7ef0a7ee | 809 | static void bfin_mac_set_multicast_list(struct net_device *dev) |
e190d6b1 BW |
810 | { |
811 | u32 sysctl; | |
812 | ||
813 | if (dev->flags & IFF_PROMISC) { | |
814 | printk(KERN_INFO "%s: set to promisc mode\n", dev->name); | |
815 | sysctl = bfin_read_EMAC_OPMODE(); | |
816 | sysctl |= RAF; | |
817 | bfin_write_EMAC_OPMODE(sysctl); | |
775919bc | 818 | } else if (dev->flags & IFF_ALLMULTI) { |
e190d6b1 BW |
819 | /* accept all multicast */ |
820 | sysctl = bfin_read_EMAC_OPMODE(); | |
821 | sysctl |= PAM; | |
822 | bfin_write_EMAC_OPMODE(sysctl); | |
775919bc AW |
823 | } else if (dev->mc_count) { |
824 | /* set up multicast hash table */ | |
825 | sysctl = bfin_read_EMAC_OPMODE(); | |
826 | sysctl |= HM; | |
827 | bfin_write_EMAC_OPMODE(sysctl); | |
7ef0a7ee | 828 | bfin_mac_multicast_hash(dev); |
e190d6b1 BW |
829 | } else { |
830 | /* clear promisc or multicast mode */ | |
831 | sysctl = bfin_read_EMAC_OPMODE(); | |
832 | sysctl &= ~(RAF | PAM); | |
833 | bfin_write_EMAC_OPMODE(sysctl); | |
834 | } | |
835 | } | |
836 | ||
837 | /* | |
838 | * this puts the device in an inactive state | |
839 | */ | |
7ef0a7ee | 840 | static void bfin_mac_shutdown(struct net_device *dev) |
e190d6b1 BW |
841 | { |
842 | /* Turn off the EMAC */ | |
843 | bfin_write_EMAC_OPMODE(0x00000000); | |
844 | /* Turn off the EMAC RX DMA */ | |
845 | bfin_write_DMA1_CONFIG(0x0000); | |
846 | bfin_write_DMA2_CONFIG(0x0000); | |
847 | } | |
848 | ||
849 | /* | |
850 | * Open and Initialize the interface | |
851 | * | |
852 | * Set up everything, reset the card, etc.. | |
853 | */ | |
7ef0a7ee | 854 | static int bfin_mac_open(struct net_device *dev) |
e190d6b1 | 855 | { |
7ef0a7ee | 856 | struct bfin_mac_local *lp = netdev_priv(dev); |
4af4b840 | 857 | int retval; |
e190d6b1 BW |
858 | pr_debug("%s: %s\n", dev->name, __FUNCTION__); |
859 | ||
860 | /* | |
861 | * Check that the address is valid. If its not, refuse | |
862 | * to bring the device up. The user must specify an | |
863 | * address using ifconfig eth0 hw ether xx:xx:xx:xx:xx:xx | |
864 | */ | |
865 | if (!is_valid_ether_addr(dev->dev_addr)) { | |
866 | printk(KERN_WARNING DRV_NAME ": no valid ethernet hw addr\n"); | |
867 | return -EINVAL; | |
868 | } | |
869 | ||
870 | /* initial rx and tx list */ | |
4af4b840 MH |
871 | retval = desc_list_init(); |
872 | ||
873 | if (retval) | |
874 | return retval; | |
e190d6b1 | 875 | |
4ae5a3ad | 876 | phy_start(lp->phydev); |
136492b2 | 877 | phy_write(lp->phydev, MII_BMCR, BMCR_RESET); |
e190d6b1 | 878 | setup_system_regs(dev); |
7ef0a7ee BW |
879 | bfin_mac_disable(); |
880 | bfin_mac_enable(); | |
e190d6b1 BW |
881 | pr_debug("hardware init finished\n"); |
882 | netif_start_queue(dev); | |
883 | netif_carrier_on(dev); | |
884 | ||
885 | return 0; | |
886 | } | |
887 | ||
888 | /* | |
889 | * | |
890 | * this makes the board clean up everything that it can | |
891 | * and not talk to the outside world. Caused by | |
892 | * an 'ifconfig ethX down' | |
893 | */ | |
7ef0a7ee | 894 | static int bfin_mac_close(struct net_device *dev) |
e190d6b1 | 895 | { |
7ef0a7ee | 896 | struct bfin_mac_local *lp = netdev_priv(dev); |
e190d6b1 BW |
897 | pr_debug("%s: %s\n", dev->name, __FUNCTION__); |
898 | ||
899 | netif_stop_queue(dev); | |
900 | netif_carrier_off(dev); | |
901 | ||
4ae5a3ad | 902 | phy_stop(lp->phydev); |
136492b2 | 903 | phy_write(lp->phydev, MII_BMCR, BMCR_PDOWN); |
4ae5a3ad | 904 | |
e190d6b1 | 905 | /* clear everything */ |
7ef0a7ee | 906 | bfin_mac_shutdown(dev); |
e190d6b1 BW |
907 | |
908 | /* free the rx/tx buffers */ | |
909 | desc_list_free(); | |
910 | ||
911 | return 0; | |
912 | } | |
913 | ||
7ef0a7ee | 914 | static int __init bfin_mac_probe(struct platform_device *pdev) |
e190d6b1 | 915 | { |
7ef0a7ee BW |
916 | struct net_device *ndev; |
917 | struct bfin_mac_local *lp; | |
918 | int rc, i; | |
919 | ||
920 | ndev = alloc_etherdev(sizeof(struct bfin_mac_local)); | |
921 | if (!ndev) { | |
922 | dev_err(&pdev->dev, "Cannot allocate net device!\n"); | |
923 | return -ENOMEM; | |
924 | } | |
925 | ||
926 | SET_NETDEV_DEV(ndev, &pdev->dev); | |
927 | platform_set_drvdata(pdev, ndev); | |
928 | lp = netdev_priv(ndev); | |
e190d6b1 BW |
929 | |
930 | /* Grab the MAC address in the MAC */ | |
7ef0a7ee BW |
931 | *(__le32 *) (&(ndev->dev_addr[0])) = cpu_to_le32(bfin_read_EMAC_ADDRLO()); |
932 | *(__le16 *) (&(ndev->dev_addr[4])) = cpu_to_le16((u16) bfin_read_EMAC_ADDRHI()); | |
e190d6b1 BW |
933 | |
934 | /* probe mac */ | |
935 | /*todo: how to proble? which is revision_register */ | |
936 | bfin_write_EMAC_ADDRLO(0x12345678); | |
937 | if (bfin_read_EMAC_ADDRLO() != 0x12345678) { | |
7ef0a7ee BW |
938 | dev_err(&pdev->dev, "Cannot detect Blackfin on-chip ethernet MAC controller!\n"); |
939 | rc = -ENODEV; | |
940 | goto out_err_probe_mac; | |
e190d6b1 BW |
941 | } |
942 | ||
943 | /* set the GPIO pins to Ethernet mode */ | |
7ef0a7ee BW |
944 | rc = peripheral_request_list(pin_req, DRV_NAME); |
945 | if (rc) { | |
946 | dev_err(&pdev->dev, "Requesting peripherals failed!\n"); | |
947 | rc = -EFAULT; | |
948 | goto out_err_setup_pin_mux; | |
e190d6b1 BW |
949 | } |
950 | ||
7ef0a7ee BW |
951 | /* |
952 | * Is it valid? (Did bootloader initialize it?) | |
953 | * Grab the MAC from the board somehow | |
954 | * this is done in the arch/blackfin/mach-bfxxx/boards/eth_mac.c | |
955 | */ | |
956 | if (!is_valid_ether_addr(ndev->dev_addr)) | |
957 | bfin_get_ether_addr(ndev->dev_addr); | |
958 | ||
e190d6b1 | 959 | /* If still not valid, get a random one */ |
7ef0a7ee BW |
960 | if (!is_valid_ether_addr(ndev->dev_addr)) |
961 | random_ether_addr(ndev->dev_addr); | |
e190d6b1 | 962 | |
7ef0a7ee | 963 | setup_mac_addr(ndev->dev_addr); |
e190d6b1 | 964 | |
4ae5a3ad | 965 | /* MDIO bus initial */ |
7ef0a7ee | 966 | lp->mii_bus.priv = ndev; |
4ae5a3ad BW |
967 | lp->mii_bus.read = mdiobus_read; |
968 | lp->mii_bus.write = mdiobus_write; | |
969 | lp->mii_bus.reset = mdiobus_reset; | |
970 | lp->mii_bus.name = "bfin_mac_mdio"; | |
9d9326d3 | 971 | snprintf(lp->mii_bus.id, MII_BUS_ID_SIZE, "0"); |
4ae5a3ad BW |
972 | lp->mii_bus.irq = kmalloc(sizeof(int)*PHY_MAX_ADDR, GFP_KERNEL); |
973 | for (i = 0; i < PHY_MAX_ADDR; ++i) | |
974 | lp->mii_bus.irq[i] = PHY_POLL; | |
975 | ||
7ef0a7ee BW |
976 | rc = mdiobus_register(&lp->mii_bus); |
977 | if (rc) { | |
978 | dev_err(&pdev->dev, "Cannot register MDIO bus!\n"); | |
979 | goto out_err_mdiobus_register; | |
980 | } | |
4ae5a3ad | 981 | |
7ef0a7ee BW |
982 | rc = mii_probe(ndev); |
983 | if (rc) { | |
984 | dev_err(&pdev->dev, "MII Probe failed!\n"); | |
985 | goto out_err_mii_probe; | |
986 | } | |
4ae5a3ad | 987 | |
e190d6b1 | 988 | /* Fill in the fields of the device structure with ethernet values. */ |
7ef0a7ee BW |
989 | ether_setup(ndev); |
990 | ||
991 | ndev->open = bfin_mac_open; | |
992 | ndev->stop = bfin_mac_close; | |
993 | ndev->hard_start_xmit = bfin_mac_hard_start_xmit; | |
994 | ndev->set_mac_address = bfin_mac_set_mac_address; | |
995 | ndev->tx_timeout = bfin_mac_timeout; | |
996 | ndev->set_multicast_list = bfin_mac_set_multicast_list; | |
e190d6b1 | 997 | #ifdef CONFIG_NET_POLL_CONTROLLER |
7ef0a7ee | 998 | ndev->poll_controller = bfin_mac_poll; |
e190d6b1 BW |
999 | #endif |
1000 | ||
e190d6b1 BW |
1001 | spin_lock_init(&lp->lock); |
1002 | ||
1003 | /* now, enable interrupts */ | |
1004 | /* register irq handler */ | |
7ef0a7ee BW |
1005 | rc = request_irq(IRQ_MAC_RX, bfin_mac_interrupt, |
1006 | IRQF_DISABLED | IRQF_SHARED, "EMAC_RX", ndev); | |
1007 | if (rc) { | |
1008 | dev_err(&pdev->dev, "Cannot request Blackfin MAC RX IRQ!\n"); | |
1009 | rc = -EBUSY; | |
1010 | goto out_err_request_irq; | |
e190d6b1 BW |
1011 | } |
1012 | ||
7ef0a7ee BW |
1013 | rc = register_netdev(ndev); |
1014 | if (rc) { | |
1015 | dev_err(&pdev->dev, "Cannot register net device!\n"); | |
1016 | goto out_err_reg_ndev; | |
e190d6b1 BW |
1017 | } |
1018 | ||
7ef0a7ee BW |
1019 | /* now, print out the card info, in a short format.. */ |
1020 | dev_info(&pdev->dev, "%s, Version %s\n", DRV_DESC, DRV_VERSION); | |
e190d6b1 | 1021 | |
7ef0a7ee | 1022 | return 0; |
e190d6b1 | 1023 | |
7ef0a7ee BW |
1024 | out_err_reg_ndev: |
1025 | free_irq(IRQ_MAC_RX, ndev); | |
1026 | out_err_request_irq: | |
1027 | out_err_mii_probe: | |
1028 | mdiobus_unregister(&lp->mii_bus); | |
1029 | out_err_mdiobus_register: | |
1030 | peripheral_free_list(pin_req); | |
1031 | out_err_setup_pin_mux: | |
1032 | out_err_probe_mac: | |
1033 | platform_set_drvdata(pdev, NULL); | |
1034 | free_netdev(ndev); | |
e190d6b1 | 1035 | |
7ef0a7ee | 1036 | return rc; |
e190d6b1 BW |
1037 | } |
1038 | ||
1039 | static int bfin_mac_remove(struct platform_device *pdev) | |
1040 | { | |
1041 | struct net_device *ndev = platform_get_drvdata(pdev); | |
7ef0a7ee | 1042 | struct bfin_mac_local *lp = netdev_priv(ndev); |
e190d6b1 BW |
1043 | |
1044 | platform_set_drvdata(pdev, NULL); | |
1045 | ||
7ef0a7ee BW |
1046 | mdiobus_unregister(&lp->mii_bus); |
1047 | ||
e190d6b1 BW |
1048 | unregister_netdev(ndev); |
1049 | ||
1050 | free_irq(IRQ_MAC_RX, ndev); | |
1051 | ||
1052 | free_netdev(ndev); | |
1053 | ||
7ef0a7ee | 1054 | peripheral_free_list(pin_req); |
e190d6b1 BW |
1055 | |
1056 | return 0; | |
1057 | } | |
1058 | ||
496a34c2 BW |
1059 | #ifdef CONFIG_PM |
1060 | static int bfin_mac_suspend(struct platform_device *pdev, pm_message_t mesg) | |
e190d6b1 | 1061 | { |
496a34c2 BW |
1062 | struct net_device *net_dev = platform_get_drvdata(pdev); |
1063 | ||
1064 | if (netif_running(net_dev)) | |
7ef0a7ee | 1065 | bfin_mac_close(net_dev); |
496a34c2 | 1066 | |
e190d6b1 BW |
1067 | return 0; |
1068 | } | |
1069 | ||
1070 | static int bfin_mac_resume(struct platform_device *pdev) | |
1071 | { | |
496a34c2 BW |
1072 | struct net_device *net_dev = platform_get_drvdata(pdev); |
1073 | ||
1074 | if (netif_running(net_dev)) | |
7ef0a7ee | 1075 | bfin_mac_open(net_dev); |
496a34c2 | 1076 | |
e190d6b1 BW |
1077 | return 0; |
1078 | } | |
496a34c2 BW |
1079 | #else |
1080 | #define bfin_mac_suspend NULL | |
1081 | #define bfin_mac_resume NULL | |
1082 | #endif /* CONFIG_PM */ | |
e190d6b1 BW |
1083 | |
1084 | static struct platform_driver bfin_mac_driver = { | |
1085 | .probe = bfin_mac_probe, | |
1086 | .remove = bfin_mac_remove, | |
1087 | .resume = bfin_mac_resume, | |
1088 | .suspend = bfin_mac_suspend, | |
1089 | .driver = { | |
72abb461 KS |
1090 | .name = DRV_NAME, |
1091 | .owner = THIS_MODULE, | |
1092 | }, | |
e190d6b1 BW |
1093 | }; |
1094 | ||
1095 | static int __init bfin_mac_init(void) | |
1096 | { | |
1097 | return platform_driver_register(&bfin_mac_driver); | |
1098 | } | |
1099 | ||
1100 | module_init(bfin_mac_init); | |
1101 | ||
1102 | static void __exit bfin_mac_cleanup(void) | |
1103 | { | |
1104 | platform_driver_unregister(&bfin_mac_driver); | |
1105 | } | |
1106 | ||
1107 | module_exit(bfin_mac_cleanup); | |
72abb461 | 1108 |