Commit | Line | Data |
---|---|---|
e190d6b1 | 1 | /* |
2fb9d6f5 | 2 | * Blackfin On-Chip MAC Driver |
e190d6b1 | 3 | * |
2fb9d6f5 | 4 | * Copyright 2004-2007 Analog Devices Inc. |
e190d6b1 | 5 | * |
2fb9d6f5 | 6 | * Enter bugs at http://blackfin.uclinux.org/ |
e190d6b1 | 7 | * |
2fb9d6f5 | 8 | * Licensed under the GPL-2 or later. |
e190d6b1 BW |
9 | */ |
10 | ||
11 | #include <linux/init.h> | |
12 | #include <linux/module.h> | |
13 | #include <linux/kernel.h> | |
14 | #include <linux/sched.h> | |
15 | #include <linux/slab.h> | |
16 | #include <linux/delay.h> | |
17 | #include <linux/timer.h> | |
18 | #include <linux/errno.h> | |
19 | #include <linux/irq.h> | |
20 | #include <linux/io.h> | |
21 | #include <linux/ioport.h> | |
22 | #include <linux/crc32.h> | |
23 | #include <linux/device.h> | |
24 | #include <linux/spinlock.h> | |
e190d6b1 | 25 | #include <linux/mii.h> |
4ae5a3ad | 26 | #include <linux/phy.h> |
e190d6b1 BW |
27 | #include <linux/netdevice.h> |
28 | #include <linux/etherdevice.h> | |
679dce39 | 29 | #include <linux/ethtool.h> |
e190d6b1 | 30 | #include <linux/skbuff.h> |
e190d6b1 | 31 | #include <linux/platform_device.h> |
e190d6b1 BW |
32 | |
33 | #include <asm/dma.h> | |
34 | #include <linux/dma-mapping.h> | |
35 | ||
fe92afed | 36 | #include <asm/div64.h> |
98f672ca | 37 | #include <asm/dpmc.h> |
e190d6b1 BW |
38 | #include <asm/blackfin.h> |
39 | #include <asm/cacheflush.h> | |
40 | #include <asm/portmux.h> | |
41 | ||
42 | #include "bfin_mac.h" | |
43 | ||
44 | #define DRV_NAME "bfin_mac" | |
45 | #define DRV_VERSION "1.1" | |
46 | #define DRV_AUTHOR "Bryan Wu, Luke Yang" | |
7ef0a7ee | 47 | #define DRV_DESC "Blackfin on-chip Ethernet MAC driver" |
e190d6b1 BW |
48 | |
49 | MODULE_AUTHOR(DRV_AUTHOR); | |
50 | MODULE_LICENSE("GPL"); | |
51 | MODULE_DESCRIPTION(DRV_DESC); | |
72abb461 | 52 | MODULE_ALIAS("platform:bfin_mac"); |
e190d6b1 BW |
53 | |
54 | #if defined(CONFIG_BFIN_MAC_USE_L1) | |
55 | # define bfin_mac_alloc(dma_handle, size) l1_data_sram_zalloc(size) | |
56 | # define bfin_mac_free(dma_handle, ptr) l1_data_sram_free(ptr) | |
57 | #else | |
58 | # define bfin_mac_alloc(dma_handle, size) \ | |
59 | dma_alloc_coherent(NULL, size, dma_handle, GFP_KERNEL) | |
60 | # define bfin_mac_free(dma_handle, ptr) \ | |
61 | dma_free_coherent(NULL, sizeof(*ptr), ptr, dma_handle) | |
62 | #endif | |
63 | ||
64 | #define PKT_BUF_SZ 1580 | |
65 | ||
66 | #define MAX_TIMEOUT_CNT 500 | |
67 | ||
68 | /* pointers to maintain transmit list */ | |
69 | static struct net_dma_desc_tx *tx_list_head; | |
70 | static struct net_dma_desc_tx *tx_list_tail; | |
71 | static struct net_dma_desc_rx *rx_list_head; | |
72 | static struct net_dma_desc_rx *rx_list_tail; | |
73 | static struct net_dma_desc_rx *current_rx_ptr; | |
74 | static struct net_dma_desc_tx *current_tx_ptr; | |
75 | static struct net_dma_desc_tx *tx_desc; | |
76 | static struct net_dma_desc_rx *rx_desc; | |
77 | ||
7ef0a7ee BW |
78 | #if defined(CONFIG_BFIN_MAC_RMII) |
79 | static u16 pin_req[] = P_RMII0; | |
80 | #else | |
81 | static u16 pin_req[] = P_MII0; | |
82 | #endif | |
83 | ||
84 | static void bfin_mac_disable(void); | |
85 | static void bfin_mac_enable(void); | |
4ae5a3ad | 86 | |
e190d6b1 BW |
87 | static void desc_list_free(void) |
88 | { | |
89 | struct net_dma_desc_rx *r; | |
90 | struct net_dma_desc_tx *t; | |
91 | int i; | |
92 | #if !defined(CONFIG_BFIN_MAC_USE_L1) | |
93 | dma_addr_t dma_handle = 0; | |
94 | #endif | |
95 | ||
96 | if (tx_desc) { | |
97 | t = tx_list_head; | |
98 | for (i = 0; i < CONFIG_BFIN_TX_DESC_NUM; i++) { | |
99 | if (t) { | |
100 | if (t->skb) { | |
101 | dev_kfree_skb(t->skb); | |
102 | t->skb = NULL; | |
103 | } | |
104 | t = t->next; | |
105 | } | |
106 | } | |
107 | bfin_mac_free(dma_handle, tx_desc); | |
108 | } | |
109 | ||
110 | if (rx_desc) { | |
111 | r = rx_list_head; | |
112 | for (i = 0; i < CONFIG_BFIN_RX_DESC_NUM; i++) { | |
113 | if (r) { | |
114 | if (r->skb) { | |
115 | dev_kfree_skb(r->skb); | |
116 | r->skb = NULL; | |
117 | } | |
118 | r = r->next; | |
119 | } | |
120 | } | |
121 | bfin_mac_free(dma_handle, rx_desc); | |
122 | } | |
123 | } | |
124 | ||
125 | static int desc_list_init(void) | |
126 | { | |
127 | int i; | |
128 | struct sk_buff *new_skb; | |
129 | #if !defined(CONFIG_BFIN_MAC_USE_L1) | |
130 | /* | |
131 | * This dma_handle is useless in Blackfin dma_alloc_coherent(). | |
132 | * The real dma handler is the return value of dma_alloc_coherent(). | |
133 | */ | |
134 | dma_addr_t dma_handle; | |
135 | #endif | |
136 | ||
137 | tx_desc = bfin_mac_alloc(&dma_handle, | |
138 | sizeof(struct net_dma_desc_tx) * | |
139 | CONFIG_BFIN_TX_DESC_NUM); | |
140 | if (tx_desc == NULL) | |
141 | goto init_error; | |
142 | ||
143 | rx_desc = bfin_mac_alloc(&dma_handle, | |
144 | sizeof(struct net_dma_desc_rx) * | |
145 | CONFIG_BFIN_RX_DESC_NUM); | |
146 | if (rx_desc == NULL) | |
147 | goto init_error; | |
148 | ||
149 | /* init tx_list */ | |
150 | tx_list_head = tx_list_tail = tx_desc; | |
151 | ||
152 | for (i = 0; i < CONFIG_BFIN_TX_DESC_NUM; i++) { | |
153 | struct net_dma_desc_tx *t = tx_desc + i; | |
154 | struct dma_descriptor *a = &(t->desc_a); | |
155 | struct dma_descriptor *b = &(t->desc_b); | |
156 | ||
157 | /* | |
158 | * disable DMA | |
159 | * read from memory WNR = 0 | |
160 | * wordsize is 32 bits | |
161 | * 6 half words is desc size | |
162 | * large desc flow | |
163 | */ | |
164 | a->config = WDSIZE_32 | NDSIZE_6 | DMAFLOW_LARGE; | |
165 | a->start_addr = (unsigned long)t->packet; | |
166 | a->x_count = 0; | |
167 | a->next_dma_desc = b; | |
168 | ||
169 | /* | |
170 | * enabled DMA | |
171 | * write to memory WNR = 1 | |
172 | * wordsize is 32 bits | |
173 | * disable interrupt | |
174 | * 6 half words is desc size | |
175 | * large desc flow | |
176 | */ | |
177 | b->config = DMAEN | WNR | WDSIZE_32 | NDSIZE_6 | DMAFLOW_LARGE; | |
178 | b->start_addr = (unsigned long)(&(t->status)); | |
179 | b->x_count = 0; | |
180 | ||
181 | t->skb = NULL; | |
182 | tx_list_tail->desc_b.next_dma_desc = a; | |
183 | tx_list_tail->next = t; | |
184 | tx_list_tail = t; | |
185 | } | |
186 | tx_list_tail->next = tx_list_head; /* tx_list is a circle */ | |
187 | tx_list_tail->desc_b.next_dma_desc = &(tx_list_head->desc_a); | |
188 | current_tx_ptr = tx_list_head; | |
189 | ||
190 | /* init rx_list */ | |
191 | rx_list_head = rx_list_tail = rx_desc; | |
192 | ||
193 | for (i = 0; i < CONFIG_BFIN_RX_DESC_NUM; i++) { | |
194 | struct net_dma_desc_rx *r = rx_desc + i; | |
195 | struct dma_descriptor *a = &(r->desc_a); | |
196 | struct dma_descriptor *b = &(r->desc_b); | |
197 | ||
198 | /* allocate a new skb for next time receive */ | |
015dac88 | 199 | new_skb = dev_alloc_skb(PKT_BUF_SZ + NET_IP_ALIGN); |
e190d6b1 BW |
200 | if (!new_skb) { |
201 | printk(KERN_NOTICE DRV_NAME | |
202 | ": init: low on mem - packet dropped\n"); | |
203 | goto init_error; | |
204 | } | |
015dac88 | 205 | skb_reserve(new_skb, NET_IP_ALIGN); |
f6e1e4f3 SZ |
206 | /* Invidate the data cache of skb->data range when it is write back |
207 | * cache. It will prevent overwritting the new data from DMA | |
208 | */ | |
209 | blackfin_dcache_invalidate_range((unsigned long)new_skb->head, | |
210 | (unsigned long)new_skb->end); | |
e190d6b1 BW |
211 | r->skb = new_skb; |
212 | ||
213 | /* | |
214 | * enabled DMA | |
215 | * write to memory WNR = 1 | |
216 | * wordsize is 32 bits | |
217 | * disable interrupt | |
218 | * 6 half words is desc size | |
219 | * large desc flow | |
220 | */ | |
221 | a->config = DMAEN | WNR | WDSIZE_32 | NDSIZE_6 | DMAFLOW_LARGE; | |
222 | /* since RXDWA is enabled */ | |
223 | a->start_addr = (unsigned long)new_skb->data - 2; | |
224 | a->x_count = 0; | |
225 | a->next_dma_desc = b; | |
226 | ||
227 | /* | |
228 | * enabled DMA | |
229 | * write to memory WNR = 1 | |
230 | * wordsize is 32 bits | |
231 | * enable interrupt | |
232 | * 6 half words is desc size | |
233 | * large desc flow | |
234 | */ | |
235 | b->config = DMAEN | WNR | WDSIZE_32 | DI_EN | | |
236 | NDSIZE_6 | DMAFLOW_LARGE; | |
237 | b->start_addr = (unsigned long)(&(r->status)); | |
238 | b->x_count = 0; | |
239 | ||
240 | rx_list_tail->desc_b.next_dma_desc = a; | |
241 | rx_list_tail->next = r; | |
242 | rx_list_tail = r; | |
243 | } | |
244 | rx_list_tail->next = rx_list_head; /* rx_list is a circle */ | |
245 | rx_list_tail->desc_b.next_dma_desc = &(rx_list_head->desc_a); | |
246 | current_rx_ptr = rx_list_head; | |
247 | ||
248 | return 0; | |
249 | ||
250 | init_error: | |
251 | desc_list_free(); | |
252 | printk(KERN_ERR DRV_NAME ": kmalloc failed\n"); | |
253 | return -ENOMEM; | |
254 | } | |
255 | ||
256 | ||
257 | /*---PHY CONTROL AND CONFIGURATION-----------------------------------------*/ | |
258 | ||
4ae5a3ad BW |
259 | /* |
260 | * MII operations | |
261 | */ | |
e190d6b1 | 262 | /* Wait until the previous MDC/MDIO transaction has completed */ |
0ed0563e | 263 | static void bfin_mdio_poll(void) |
e190d6b1 BW |
264 | { |
265 | int timeout_cnt = MAX_TIMEOUT_CNT; | |
266 | ||
267 | /* poll the STABUSY bit */ | |
268 | while ((bfin_read_EMAC_STAADD()) & STABUSY) { | |
6db9e461 | 269 | udelay(1); |
e190d6b1 BW |
270 | if (timeout_cnt-- < 0) { |
271 | printk(KERN_ERR DRV_NAME | |
272 | ": wait MDC/MDIO transaction to complete timeout\n"); | |
273 | break; | |
274 | } | |
275 | } | |
276 | } | |
277 | ||
278 | /* Read an off-chip register in a PHY through the MDC/MDIO port */ | |
0ed0563e | 279 | static int bfin_mdiobus_read(struct mii_bus *bus, int phy_addr, int regnum) |
e190d6b1 | 280 | { |
0ed0563e | 281 | bfin_mdio_poll(); |
4ae5a3ad | 282 | |
e190d6b1 | 283 | /* read mode */ |
4ae5a3ad BW |
284 | bfin_write_EMAC_STAADD(SET_PHYAD((u16) phy_addr) | |
285 | SET_REGAD((u16) regnum) | | |
e190d6b1 | 286 | STABUSY); |
e190d6b1 | 287 | |
0ed0563e | 288 | bfin_mdio_poll(); |
4ae5a3ad BW |
289 | |
290 | return (int) bfin_read_EMAC_STADAT(); | |
e190d6b1 BW |
291 | } |
292 | ||
293 | /* Write an off-chip register in a PHY through the MDC/MDIO port */ | |
0ed0563e AB |
294 | static int bfin_mdiobus_write(struct mii_bus *bus, int phy_addr, int regnum, |
295 | u16 value) | |
e190d6b1 | 296 | { |
0ed0563e | 297 | bfin_mdio_poll(); |
4ae5a3ad BW |
298 | |
299 | bfin_write_EMAC_STADAT((u32) value); | |
e190d6b1 BW |
300 | |
301 | /* write mode */ | |
4ae5a3ad BW |
302 | bfin_write_EMAC_STAADD(SET_PHYAD((u16) phy_addr) | |
303 | SET_REGAD((u16) regnum) | | |
e190d6b1 BW |
304 | STAOP | |
305 | STABUSY); | |
306 | ||
0ed0563e | 307 | bfin_mdio_poll(); |
4ae5a3ad BW |
308 | |
309 | return 0; | |
e190d6b1 BW |
310 | } |
311 | ||
0ed0563e | 312 | static int bfin_mdiobus_reset(struct mii_bus *bus) |
e190d6b1 | 313 | { |
4ae5a3ad | 314 | return 0; |
e190d6b1 BW |
315 | } |
316 | ||
7ef0a7ee | 317 | static void bfin_mac_adjust_link(struct net_device *dev) |
e190d6b1 | 318 | { |
7ef0a7ee | 319 | struct bfin_mac_local *lp = netdev_priv(dev); |
4ae5a3ad BW |
320 | struct phy_device *phydev = lp->phydev; |
321 | unsigned long flags; | |
322 | int new_state = 0; | |
323 | ||
324 | spin_lock_irqsave(&lp->lock, flags); | |
325 | if (phydev->link) { | |
326 | /* Now we make sure that we can be in full duplex mode. | |
327 | * If not, we operate in half-duplex mode. */ | |
328 | if (phydev->duplex != lp->old_duplex) { | |
329 | u32 opmode = bfin_read_EMAC_OPMODE(); | |
330 | new_state = 1; | |
331 | ||
332 | if (phydev->duplex) | |
333 | opmode |= FDMODE; | |
334 | else | |
335 | opmode &= ~(FDMODE); | |
336 | ||
337 | bfin_write_EMAC_OPMODE(opmode); | |
338 | lp->old_duplex = phydev->duplex; | |
339 | } | |
e190d6b1 | 340 | |
4ae5a3ad BW |
341 | if (phydev->speed != lp->old_speed) { |
342 | #if defined(CONFIG_BFIN_MAC_RMII) | |
343 | u32 opmode = bfin_read_EMAC_OPMODE(); | |
4ae5a3ad BW |
344 | switch (phydev->speed) { |
345 | case 10: | |
346 | opmode |= RMII_10; | |
347 | break; | |
348 | case 100: | |
349 | opmode &= ~(RMII_10); | |
350 | break; | |
351 | default: | |
352 | printk(KERN_WARNING | |
353 | "%s: Ack! Speed (%d) is not 10/100!\n", | |
354 | DRV_NAME, phydev->speed); | |
355 | break; | |
356 | } | |
357 | bfin_write_EMAC_OPMODE(opmode); | |
4ae5a3ad | 358 | #endif |
e190d6b1 | 359 | |
4ae5a3ad BW |
360 | new_state = 1; |
361 | lp->old_speed = phydev->speed; | |
362 | } | |
e190d6b1 | 363 | |
4ae5a3ad BW |
364 | if (!lp->old_link) { |
365 | new_state = 1; | |
366 | lp->old_link = 1; | |
4ae5a3ad BW |
367 | } |
368 | } else if (lp->old_link) { | |
369 | new_state = 1; | |
370 | lp->old_link = 0; | |
371 | lp->old_speed = 0; | |
372 | lp->old_duplex = -1; | |
e190d6b1 BW |
373 | } |
374 | ||
4ae5a3ad BW |
375 | if (new_state) { |
376 | u32 opmode = bfin_read_EMAC_OPMODE(); | |
377 | phy_print_status(phydev); | |
378 | pr_debug("EMAC_OPMODE = 0x%08x\n", opmode); | |
e190d6b1 | 379 | } |
4ae5a3ad BW |
380 | |
381 | spin_unlock_irqrestore(&lp->lock, flags); | |
e190d6b1 BW |
382 | } |
383 | ||
7cc8f381 BW |
384 | /* MDC = 2.5 MHz */ |
385 | #define MDC_CLK 2500000 | |
386 | ||
4ae5a3ad | 387 | static int mii_probe(struct net_device *dev) |
e190d6b1 | 388 | { |
7ef0a7ee | 389 | struct bfin_mac_local *lp = netdev_priv(dev); |
4ae5a3ad BW |
390 | struct phy_device *phydev = NULL; |
391 | unsigned short sysctl; | |
392 | int i; | |
7cc8f381 | 393 | u32 sclk, mdc_div; |
e190d6b1 | 394 | |
4ae5a3ad | 395 | /* Enable PHY output early */ |
98f672ca MF |
396 | if (!(bfin_read_VR_CTL() & CLKBUFOE)) |
397 | bfin_write_VR_CTL(bfin_read_VR_CTL() | CLKBUFOE); | |
e190d6b1 | 398 | |
7cc8f381 BW |
399 | sclk = get_sclk(); |
400 | mdc_div = ((sclk / MDC_CLK) / 2) - 1; | |
401 | ||
4ae5a3ad | 402 | sysctl = bfin_read_EMAC_SYSCTL(); |
9dc7f30e | 403 | sysctl = (sysctl & ~MDCDIV) | SET_MDCDIV(mdc_div); |
e190d6b1 | 404 | bfin_write_EMAC_SYSCTL(sysctl); |
e190d6b1 | 405 | |
4ae5a3ad BW |
406 | /* search for connect PHY device */ |
407 | for (i = 0; i < PHY_MAX_ADDR; i++) { | |
298cf9be | 408 | struct phy_device *const tmp_phydev = lp->mii_bus->phy_map[i]; |
e190d6b1 | 409 | |
4ae5a3ad BW |
410 | if (!tmp_phydev) |
411 | continue; /* no PHY here... */ | |
e190d6b1 | 412 | |
4ae5a3ad BW |
413 | phydev = tmp_phydev; |
414 | break; /* found it */ | |
415 | } | |
416 | ||
417 | /* now we are supposed to have a proper phydev, to attach to... */ | |
418 | if (!phydev) { | |
419 | printk(KERN_INFO "%s: Don't found any phy device at all\n", | |
420 | dev->name); | |
421 | return -ENODEV; | |
e190d6b1 BW |
422 | } |
423 | ||
424 | #if defined(CONFIG_BFIN_MAC_RMII) | |
c2313557 KS |
425 | phydev = phy_connect(dev, dev_name(&phydev->dev), &bfin_mac_adjust_link, |
426 | 0, PHY_INTERFACE_MODE_RMII); | |
4ae5a3ad | 427 | #else |
c2313557 KS |
428 | phydev = phy_connect(dev, dev_name(&phydev->dev), &bfin_mac_adjust_link, |
429 | 0, PHY_INTERFACE_MODE_MII); | |
e190d6b1 BW |
430 | #endif |
431 | ||
4ae5a3ad BW |
432 | if (IS_ERR(phydev)) { |
433 | printk(KERN_ERR "%s: Could not attach to PHY\n", dev->name); | |
434 | return PTR_ERR(phydev); | |
435 | } | |
436 | ||
437 | /* mask with MAC supported features */ | |
438 | phydev->supported &= (SUPPORTED_10baseT_Half | |
439 | | SUPPORTED_10baseT_Full | |
440 | | SUPPORTED_100baseT_Half | |
441 | | SUPPORTED_100baseT_Full | |
442 | | SUPPORTED_Autoneg | |
443 | | SUPPORTED_Pause | SUPPORTED_Asym_Pause | |
444 | | SUPPORTED_MII | |
445 | | SUPPORTED_TP); | |
446 | ||
447 | phydev->advertising = phydev->supported; | |
448 | ||
449 | lp->old_link = 0; | |
450 | lp->old_speed = 0; | |
451 | lp->old_duplex = -1; | |
452 | lp->phydev = phydev; | |
453 | ||
454 | printk(KERN_INFO "%s: attached PHY driver [%s] " | |
7cc8f381 BW |
455 | "(mii_bus:phy_addr=%s, irq=%d, mdc_clk=%dHz(mdc_div=%d)" |
456 | "@sclk=%dMHz)\n", | |
c2313557 | 457 | DRV_NAME, phydev->drv->name, dev_name(&phydev->dev), phydev->irq, |
7cc8f381 | 458 | MDC_CLK, mdc_div, sclk/1000000); |
4ae5a3ad BW |
459 | |
460 | return 0; | |
461 | } | |
462 | ||
679dce39 BW |
463 | /* |
464 | * Ethtool support | |
465 | */ | |
466 | ||
53fd3f28 MH |
467 | /* |
468 | * interrupt routine for magic packet wakeup | |
469 | */ | |
470 | static irqreturn_t bfin_mac_wake_interrupt(int irq, void *dev_id) | |
471 | { | |
472 | return IRQ_HANDLED; | |
473 | } | |
474 | ||
679dce39 BW |
475 | static int |
476 | bfin_mac_ethtool_getsettings(struct net_device *dev, struct ethtool_cmd *cmd) | |
477 | { | |
478 | struct bfin_mac_local *lp = netdev_priv(dev); | |
479 | ||
480 | if (lp->phydev) | |
481 | return phy_ethtool_gset(lp->phydev, cmd); | |
482 | ||
483 | return -EINVAL; | |
484 | } | |
485 | ||
486 | static int | |
487 | bfin_mac_ethtool_setsettings(struct net_device *dev, struct ethtool_cmd *cmd) | |
488 | { | |
489 | struct bfin_mac_local *lp = netdev_priv(dev); | |
490 | ||
491 | if (!capable(CAP_NET_ADMIN)) | |
492 | return -EPERM; | |
493 | ||
494 | if (lp->phydev) | |
495 | return phy_ethtool_sset(lp->phydev, cmd); | |
496 | ||
497 | return -EINVAL; | |
498 | } | |
499 | ||
500 | static void bfin_mac_ethtool_getdrvinfo(struct net_device *dev, | |
501 | struct ethtool_drvinfo *info) | |
502 | { | |
503 | strcpy(info->driver, DRV_NAME); | |
504 | strcpy(info->version, DRV_VERSION); | |
505 | strcpy(info->fw_version, "N/A"); | |
c2313557 | 506 | strcpy(info->bus_info, dev_name(&dev->dev)); |
679dce39 BW |
507 | } |
508 | ||
53fd3f28 MH |
509 | static void bfin_mac_ethtool_getwol(struct net_device *dev, |
510 | struct ethtool_wolinfo *wolinfo) | |
511 | { | |
512 | struct bfin_mac_local *lp = netdev_priv(dev); | |
513 | ||
514 | wolinfo->supported = WAKE_MAGIC; | |
515 | wolinfo->wolopts = lp->wol; | |
516 | } | |
517 | ||
518 | static int bfin_mac_ethtool_setwol(struct net_device *dev, | |
519 | struct ethtool_wolinfo *wolinfo) | |
520 | { | |
521 | struct bfin_mac_local *lp = netdev_priv(dev); | |
522 | int rc; | |
523 | ||
524 | if (wolinfo->wolopts & (WAKE_MAGICSECURE | | |
525 | WAKE_UCAST | | |
526 | WAKE_MCAST | | |
527 | WAKE_BCAST | | |
528 | WAKE_ARP)) | |
529 | return -EOPNOTSUPP; | |
530 | ||
531 | lp->wol = wolinfo->wolopts; | |
532 | ||
533 | if (lp->wol && !lp->irq_wake_requested) { | |
534 | /* register wake irq handler */ | |
535 | rc = request_irq(IRQ_MAC_WAKEDET, bfin_mac_wake_interrupt, | |
536 | IRQF_DISABLED, "EMAC_WAKE", dev); | |
537 | if (rc) | |
538 | return rc; | |
539 | lp->irq_wake_requested = true; | |
540 | } | |
541 | ||
542 | if (!lp->wol && lp->irq_wake_requested) { | |
543 | free_irq(IRQ_MAC_WAKEDET, dev); | |
544 | lp->irq_wake_requested = false; | |
545 | } | |
546 | ||
547 | /* Make sure the PHY driver doesn't suspend */ | |
548 | device_init_wakeup(&dev->dev, lp->wol); | |
549 | ||
550 | return 0; | |
551 | } | |
552 | ||
0fc0b732 | 553 | static const struct ethtool_ops bfin_mac_ethtool_ops = { |
679dce39 BW |
554 | .get_settings = bfin_mac_ethtool_getsettings, |
555 | .set_settings = bfin_mac_ethtool_setsettings, | |
556 | .get_link = ethtool_op_get_link, | |
557 | .get_drvinfo = bfin_mac_ethtool_getdrvinfo, | |
53fd3f28 MH |
558 | .get_wol = bfin_mac_ethtool_getwol, |
559 | .set_wol = bfin_mac_ethtool_setwol, | |
679dce39 BW |
560 | }; |
561 | ||
4ae5a3ad BW |
562 | /**************************************************************************/ |
563 | void setup_system_regs(struct net_device *dev) | |
564 | { | |
565 | unsigned short sysctl; | |
566 | ||
567 | /* | |
568 | * Odd word alignment for Receive Frame DMA word | |
569 | * Configure checksum support and rcve frame word alignment | |
570 | */ | |
571 | sysctl = bfin_read_EMAC_SYSCTL(); | |
812a9de7 | 572 | sysctl |= RXDWA; |
4ae5a3ad | 573 | #if defined(BFIN_MAC_CSUM_OFFLOAD) |
812a9de7 | 574 | sysctl |= RXCKS; |
4ae5a3ad | 575 | #else |
812a9de7 | 576 | sysctl &= ~RXCKS; |
4ae5a3ad BW |
577 | #endif |
578 | bfin_write_EMAC_SYSCTL(sysctl); | |
e190d6b1 BW |
579 | |
580 | bfin_write_EMAC_MMC_CTL(RSTC | CROLL); | |
581 | ||
582 | /* Initialize the TX DMA channel registers */ | |
583 | bfin_write_DMA2_X_COUNT(0); | |
584 | bfin_write_DMA2_X_MODIFY(4); | |
585 | bfin_write_DMA2_Y_COUNT(0); | |
586 | bfin_write_DMA2_Y_MODIFY(0); | |
587 | ||
588 | /* Initialize the RX DMA channel registers */ | |
589 | bfin_write_DMA1_X_COUNT(0); | |
590 | bfin_write_DMA1_X_MODIFY(4); | |
591 | bfin_write_DMA1_Y_COUNT(0); | |
592 | bfin_write_DMA1_Y_MODIFY(0); | |
593 | } | |
594 | ||
73f83182 | 595 | static void setup_mac_addr(u8 *mac_addr) |
e190d6b1 BW |
596 | { |
597 | u32 addr_low = le32_to_cpu(*(__le32 *) & mac_addr[0]); | |
598 | u16 addr_hi = le16_to_cpu(*(__le16 *) & mac_addr[4]); | |
599 | ||
600 | /* this depends on a little-endian machine */ | |
601 | bfin_write_EMAC_ADDRLO(addr_low); | |
602 | bfin_write_EMAC_ADDRHI(addr_hi); | |
603 | } | |
604 | ||
7ef0a7ee | 605 | static int bfin_mac_set_mac_address(struct net_device *dev, void *p) |
73f83182 AL |
606 | { |
607 | struct sockaddr *addr = p; | |
608 | if (netif_running(dev)) | |
609 | return -EBUSY; | |
610 | memcpy(dev->dev_addr, addr->sa_data, dev->addr_len); | |
611 | setup_mac_addr(dev->dev_addr); | |
612 | return 0; | |
613 | } | |
614 | ||
fe92afed BS |
615 | #ifdef CONFIG_BFIN_MAC_USE_HWSTAMP |
616 | #define bfin_mac_hwtstamp_is_none(cfg) ((cfg) == HWTSTAMP_FILTER_NONE) | |
617 | ||
618 | static int bfin_mac_hwtstamp_ioctl(struct net_device *netdev, | |
619 | struct ifreq *ifr, int cmd) | |
620 | { | |
621 | struct hwtstamp_config config; | |
622 | struct bfin_mac_local *lp = netdev_priv(netdev); | |
623 | u16 ptpctl; | |
624 | u32 ptpfv1, ptpfv2, ptpfv3, ptpfoff; | |
625 | ||
626 | if (copy_from_user(&config, ifr->ifr_data, sizeof(config))) | |
627 | return -EFAULT; | |
628 | ||
629 | pr_debug("%s config flag:0x%x, tx_type:0x%x, rx_filter:0x%x\n", | |
630 | __func__, config.flags, config.tx_type, config.rx_filter); | |
631 | ||
632 | /* reserved for future extensions */ | |
633 | if (config.flags) | |
634 | return -EINVAL; | |
635 | ||
636 | if ((config.tx_type != HWTSTAMP_TX_OFF) && | |
637 | (config.tx_type != HWTSTAMP_TX_ON)) | |
638 | return -ERANGE; | |
639 | ||
640 | ptpctl = bfin_read_EMAC_PTP_CTL(); | |
641 | ||
642 | switch (config.rx_filter) { | |
643 | case HWTSTAMP_FILTER_NONE: | |
644 | /* | |
645 | * Dont allow any timestamping | |
646 | */ | |
647 | ptpfv3 = 0xFFFFFFFF; | |
648 | bfin_write_EMAC_PTP_FV3(ptpfv3); | |
649 | break; | |
650 | case HWTSTAMP_FILTER_PTP_V1_L4_EVENT: | |
651 | case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: | |
652 | case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: | |
653 | /* | |
654 | * Clear the five comparison mask bits (bits[12:8]) in EMAC_PTP_CTL) | |
655 | * to enable all the field matches. | |
656 | */ | |
657 | ptpctl &= ~0x1F00; | |
658 | bfin_write_EMAC_PTP_CTL(ptpctl); | |
659 | /* | |
660 | * Keep the default values of the EMAC_PTP_FOFF register. | |
661 | */ | |
662 | ptpfoff = 0x4A24170C; | |
663 | bfin_write_EMAC_PTP_FOFF(ptpfoff); | |
664 | /* | |
665 | * Keep the default values of the EMAC_PTP_FV1 and EMAC_PTP_FV2 | |
666 | * registers. | |
667 | */ | |
668 | ptpfv1 = 0x11040800; | |
669 | bfin_write_EMAC_PTP_FV1(ptpfv1); | |
670 | ptpfv2 = 0x0140013F; | |
671 | bfin_write_EMAC_PTP_FV2(ptpfv2); | |
672 | /* | |
673 | * The default value (0xFFFC) allows the timestamping of both | |
674 | * received Sync messages and Delay_Req messages. | |
675 | */ | |
676 | ptpfv3 = 0xFFFFFFFC; | |
677 | bfin_write_EMAC_PTP_FV3(ptpfv3); | |
678 | ||
679 | config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT; | |
680 | break; | |
681 | case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: | |
682 | case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: | |
683 | case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: | |
684 | /* Clear all five comparison mask bits (bits[12:8]) in the | |
685 | * EMAC_PTP_CTL register to enable all the field matches. | |
686 | */ | |
687 | ptpctl &= ~0x1F00; | |
688 | bfin_write_EMAC_PTP_CTL(ptpctl); | |
689 | /* | |
690 | * Keep the default values of the EMAC_PTP_FOFF register, except set | |
691 | * the PTPCOF field to 0x2A. | |
692 | */ | |
693 | ptpfoff = 0x2A24170C; | |
694 | bfin_write_EMAC_PTP_FOFF(ptpfoff); | |
695 | /* | |
696 | * Keep the default values of the EMAC_PTP_FV1 and EMAC_PTP_FV2 | |
697 | * registers. | |
698 | */ | |
699 | ptpfv1 = 0x11040800; | |
700 | bfin_write_EMAC_PTP_FV1(ptpfv1); | |
701 | ptpfv2 = 0x0140013F; | |
702 | bfin_write_EMAC_PTP_FV2(ptpfv2); | |
703 | /* | |
704 | * To allow the timestamping of Pdelay_Req and Pdelay_Resp, set | |
705 | * the value to 0xFFF0. | |
706 | */ | |
707 | ptpfv3 = 0xFFFFFFF0; | |
708 | bfin_write_EMAC_PTP_FV3(ptpfv3); | |
709 | ||
710 | config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_EVENT; | |
711 | break; | |
712 | case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: | |
713 | case HWTSTAMP_FILTER_PTP_V2_L2_SYNC: | |
714 | case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ: | |
715 | /* | |
716 | * Clear bits 8 and 12 of the EMAC_PTP_CTL register to enable only the | |
717 | * EFTM and PTPCM field comparison. | |
718 | */ | |
719 | ptpctl &= ~0x1100; | |
720 | bfin_write_EMAC_PTP_CTL(ptpctl); | |
721 | /* | |
722 | * Keep the default values of all the fields of the EMAC_PTP_FOFF | |
723 | * register, except set the PTPCOF field to 0x0E. | |
724 | */ | |
725 | ptpfoff = 0x0E24170C; | |
726 | bfin_write_EMAC_PTP_FOFF(ptpfoff); | |
727 | /* | |
728 | * Program bits [15:0] of the EMAC_PTP_FV1 register to 0x88F7, which | |
729 | * corresponds to PTP messages on the MAC layer. | |
730 | */ | |
731 | ptpfv1 = 0x110488F7; | |
732 | bfin_write_EMAC_PTP_FV1(ptpfv1); | |
733 | ptpfv2 = 0x0140013F; | |
734 | bfin_write_EMAC_PTP_FV2(ptpfv2); | |
735 | /* | |
736 | * To allow the timestamping of Pdelay_Req and Pdelay_Resp | |
737 | * messages, set the value to 0xFFF0. | |
738 | */ | |
739 | ptpfv3 = 0xFFFFFFF0; | |
740 | bfin_write_EMAC_PTP_FV3(ptpfv3); | |
741 | ||
742 | config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L2_EVENT; | |
743 | break; | |
744 | default: | |
745 | return -ERANGE; | |
746 | } | |
747 | ||
748 | if (config.tx_type == HWTSTAMP_TX_OFF && | |
749 | bfin_mac_hwtstamp_is_none(config.rx_filter)) { | |
750 | ptpctl &= ~PTP_EN; | |
751 | bfin_write_EMAC_PTP_CTL(ptpctl); | |
752 | ||
753 | SSYNC(); | |
754 | } else { | |
755 | ptpctl |= PTP_EN; | |
756 | bfin_write_EMAC_PTP_CTL(ptpctl); | |
757 | ||
758 | /* | |
759 | * clear any existing timestamp | |
760 | */ | |
761 | bfin_read_EMAC_PTP_RXSNAPLO(); | |
762 | bfin_read_EMAC_PTP_RXSNAPHI(); | |
763 | ||
764 | bfin_read_EMAC_PTP_TXSNAPLO(); | |
765 | bfin_read_EMAC_PTP_TXSNAPHI(); | |
766 | ||
767 | /* | |
768 | * Set registers so that rollover occurs soon to test this. | |
769 | */ | |
770 | bfin_write_EMAC_PTP_TIMELO(0x00000000); | |
771 | bfin_write_EMAC_PTP_TIMEHI(0xFF800000); | |
772 | ||
773 | SSYNC(); | |
774 | ||
775 | lp->compare.last_update = 0; | |
776 | timecounter_init(&lp->clock, | |
777 | &lp->cycles, | |
778 | ktime_to_ns(ktime_get_real())); | |
779 | timecompare_update(&lp->compare, 0); | |
780 | } | |
781 | ||
782 | lp->stamp_cfg = config; | |
783 | return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ? | |
784 | -EFAULT : 0; | |
785 | } | |
786 | ||
787 | static void bfin_dump_hwtamp(char *s, ktime_t *hw, ktime_t *ts, struct timecompare *cmp) | |
788 | { | |
789 | ktime_t sys = ktime_get_real(); | |
790 | ||
791 | pr_debug("%s %s hardware:%d,%d transform system:%d,%d system:%d,%d, cmp:%lld, %lld\n", | |
792 | __func__, s, hw->tv.sec, hw->tv.nsec, ts->tv.sec, ts->tv.nsec, sys.tv.sec, | |
793 | sys.tv.nsec, cmp->offset, cmp->skew); | |
794 | } | |
795 | ||
796 | static void bfin_tx_hwtstamp(struct net_device *netdev, struct sk_buff *skb) | |
797 | { | |
798 | struct bfin_mac_local *lp = netdev_priv(netdev); | |
799 | union skb_shared_tx *shtx = skb_tx(skb); | |
800 | ||
801 | if (shtx->hardware) { | |
802 | int timeout_cnt = MAX_TIMEOUT_CNT; | |
803 | ||
804 | /* When doing time stamping, keep the connection to the socket | |
805 | * a while longer | |
806 | */ | |
807 | shtx->in_progress = 1; | |
808 | ||
809 | /* | |
810 | * The timestamping is done at the EMAC module's MII/RMII interface | |
811 | * when the module sees the Start of Frame of an event message packet. This | |
812 | * interface is the closest possible place to the physical Ethernet transmission | |
813 | * medium, providing the best timing accuracy. | |
814 | */ | |
815 | while ((!(bfin_read_EMAC_PTP_ISTAT() & TXTL)) && (--timeout_cnt)) | |
816 | udelay(1); | |
817 | if (timeout_cnt == 0) | |
818 | printk(KERN_ERR DRV_NAME | |
819 | ": fails to timestamp the TX packet\n"); | |
820 | else { | |
821 | struct skb_shared_hwtstamps shhwtstamps; | |
822 | u64 ns; | |
823 | u64 regval; | |
824 | ||
825 | regval = bfin_read_EMAC_PTP_TXSNAPLO(); | |
826 | regval |= (u64)bfin_read_EMAC_PTP_TXSNAPHI() << 32; | |
827 | memset(&shhwtstamps, 0, sizeof(shhwtstamps)); | |
828 | ns = timecounter_cyc2time(&lp->clock, | |
829 | regval); | |
830 | timecompare_update(&lp->compare, ns); | |
831 | shhwtstamps.hwtstamp = ns_to_ktime(ns); | |
832 | shhwtstamps.syststamp = | |
833 | timecompare_transform(&lp->compare, ns); | |
834 | skb_tstamp_tx(skb, &shhwtstamps); | |
835 | ||
836 | bfin_dump_hwtamp("TX", &shhwtstamps.hwtstamp, &shhwtstamps.syststamp, &lp->compare); | |
837 | } | |
838 | } | |
839 | } | |
840 | ||
841 | static void bfin_rx_hwtstamp(struct net_device *netdev, struct sk_buff *skb) | |
842 | { | |
843 | struct bfin_mac_local *lp = netdev_priv(netdev); | |
844 | u32 valid; | |
845 | u64 regval, ns; | |
846 | struct skb_shared_hwtstamps *shhwtstamps; | |
847 | ||
848 | if (bfin_mac_hwtstamp_is_none(lp->stamp_cfg.rx_filter)) | |
849 | return; | |
850 | ||
851 | valid = bfin_read_EMAC_PTP_ISTAT() & RXEL; | |
852 | if (!valid) | |
853 | return; | |
854 | ||
855 | shhwtstamps = skb_hwtstamps(skb); | |
856 | ||
857 | regval = bfin_read_EMAC_PTP_RXSNAPLO(); | |
858 | regval |= (u64)bfin_read_EMAC_PTP_RXSNAPHI() << 32; | |
859 | ns = timecounter_cyc2time(&lp->clock, regval); | |
860 | timecompare_update(&lp->compare, ns); | |
861 | memset(shhwtstamps, 0, sizeof(*shhwtstamps)); | |
862 | shhwtstamps->hwtstamp = ns_to_ktime(ns); | |
863 | shhwtstamps->syststamp = timecompare_transform(&lp->compare, ns); | |
864 | ||
865 | bfin_dump_hwtamp("RX", &shhwtstamps->hwtstamp, &shhwtstamps->syststamp, &lp->compare); | |
866 | } | |
867 | ||
868 | /* | |
869 | * bfin_read_clock - read raw cycle counter (to be used by time counter) | |
870 | */ | |
871 | static cycle_t bfin_read_clock(const struct cyclecounter *tc) | |
872 | { | |
873 | u64 stamp; | |
874 | ||
875 | stamp = bfin_read_EMAC_PTP_TIMELO(); | |
876 | stamp |= (u64)bfin_read_EMAC_PTP_TIMEHI() << 32ULL; | |
877 | ||
878 | return stamp; | |
879 | } | |
880 | ||
881 | #define PTP_CLK 25000000 | |
882 | ||
883 | static void bfin_mac_hwtstamp_init(struct net_device *netdev) | |
884 | { | |
885 | struct bfin_mac_local *lp = netdev_priv(netdev); | |
886 | u64 append; | |
887 | ||
888 | /* Initialize hardware timer */ | |
889 | append = PTP_CLK * (1ULL << 32); | |
890 | do_div(append, get_sclk()); | |
891 | bfin_write_EMAC_PTP_ADDEND((u32)append); | |
892 | ||
893 | memset(&lp->cycles, 0, sizeof(lp->cycles)); | |
894 | lp->cycles.read = bfin_read_clock; | |
895 | lp->cycles.mask = CLOCKSOURCE_MASK(64); | |
896 | lp->cycles.mult = 1000000000 / PTP_CLK; | |
897 | lp->cycles.shift = 0; | |
898 | ||
899 | /* Synchronize our NIC clock against system wall clock */ | |
900 | memset(&lp->compare, 0, sizeof(lp->compare)); | |
901 | lp->compare.source = &lp->clock; | |
902 | lp->compare.target = ktime_get_real; | |
903 | lp->compare.num_samples = 10; | |
904 | ||
905 | /* Initialize hwstamp config */ | |
906 | lp->stamp_cfg.rx_filter = HWTSTAMP_FILTER_NONE; | |
907 | lp->stamp_cfg.tx_type = HWTSTAMP_TX_OFF; | |
908 | } | |
909 | ||
910 | #else | |
911 | # define bfin_mac_hwtstamp_is_none(cfg) 0 | |
912 | # define bfin_mac_hwtstamp_init(dev) | |
913 | # define bfin_mac_hwtstamp_ioctl(dev, ifr, cmd) (-EOPNOTSUPP) | |
914 | # define bfin_rx_hwtstamp(dev, skb) | |
915 | # define bfin_tx_hwtstamp(dev, skb) | |
916 | #endif | |
917 | ||
e190d6b1 BW |
918 | static void adjust_tx_list(void) |
919 | { | |
920 | int timeout_cnt = MAX_TIMEOUT_CNT; | |
921 | ||
8e95a202 JP |
922 | if (tx_list_head->status.status_word != 0 && |
923 | current_tx_ptr != tx_list_head) { | |
e190d6b1 BW |
924 | goto adjust_head; /* released something, just return; */ |
925 | } | |
926 | ||
927 | /* | |
928 | * if nothing released, check wait condition | |
929 | * current's next can not be the head, | |
930 | * otherwise the dma will not stop as we want | |
931 | */ | |
932 | if (current_tx_ptr->next->next == tx_list_head) { | |
933 | while (tx_list_head->status.status_word == 0) { | |
015dac88 | 934 | udelay(10); |
8e95a202 JP |
935 | if (tx_list_head->status.status_word != 0 || |
936 | !(bfin_read_DMA2_IRQ_STATUS() & DMA_RUN)) { | |
e190d6b1 BW |
937 | goto adjust_head; |
938 | } | |
939 | if (timeout_cnt-- < 0) { | |
940 | printk(KERN_ERR DRV_NAME | |
941 | ": wait for adjust tx list head timeout\n"); | |
942 | break; | |
943 | } | |
944 | } | |
945 | if (tx_list_head->status.status_word != 0) { | |
946 | goto adjust_head; | |
947 | } | |
948 | } | |
949 | ||
950 | return; | |
951 | ||
952 | adjust_head: | |
953 | do { | |
954 | tx_list_head->desc_a.config &= ~DMAEN; | |
955 | tx_list_head->status.status_word = 0; | |
956 | if (tx_list_head->skb) { | |
957 | dev_kfree_skb(tx_list_head->skb); | |
958 | tx_list_head->skb = NULL; | |
959 | } else { | |
960 | printk(KERN_ERR DRV_NAME | |
961 | ": no sk_buff in a transmitted frame!\n"); | |
962 | } | |
963 | tx_list_head = tx_list_head->next; | |
8e95a202 JP |
964 | } while (tx_list_head->status.status_word != 0 && |
965 | current_tx_ptr != tx_list_head); | |
e190d6b1 BW |
966 | return; |
967 | ||
968 | } | |
969 | ||
7ef0a7ee | 970 | static int bfin_mac_hard_start_xmit(struct sk_buff *skb, |
e190d6b1 BW |
971 | struct net_device *dev) |
972 | { | |
a50c0c05 | 973 | u16 *data; |
015dac88 | 974 | u32 data_align = (unsigned long)(skb->data) & 0x3; |
fe92afed BS |
975 | union skb_shared_tx *shtx = skb_tx(skb); |
976 | ||
e190d6b1 BW |
977 | current_tx_ptr->skb = skb; |
978 | ||
015dac88 MH |
979 | if (data_align == 0x2) { |
980 | /* move skb->data to current_tx_ptr payload */ | |
981 | data = (u16 *)(skb->data) - 1; | |
fe92afed BS |
982 | *data = (u16)(skb->len); |
983 | /* | |
984 | * When transmitting an Ethernet packet, the PTP_TSYNC module requires | |
985 | * a DMA_Length_Word field associated with the packet. The lower 12 bits | |
986 | * of this field are the length of the packet payload in bytes and the higher | |
987 | * 4 bits are the timestamping enable field. | |
988 | */ | |
989 | if (shtx->hardware) | |
990 | *data |= 0x1000; | |
991 | ||
015dac88 MH |
992 | current_tx_ptr->desc_a.start_addr = (u32)data; |
993 | /* this is important! */ | |
994 | blackfin_dcache_flush_range((u32)data, | |
995 | (u32)((u8 *)data + skb->len + 4)); | |
e190d6b1 | 996 | } else { |
015dac88 | 997 | *((u16 *)(current_tx_ptr->packet)) = (u16)(skb->len); |
fe92afed BS |
998 | /* enable timestamping for the sent packet */ |
999 | if (shtx->hardware) | |
1000 | *((u16 *)(current_tx_ptr->packet)) |= 0x1000; | |
015dac88 MH |
1001 | memcpy((u8 *)(current_tx_ptr->packet + 2), skb->data, |
1002 | skb->len); | |
1003 | current_tx_ptr->desc_a.start_addr = | |
1004 | (u32)current_tx_ptr->packet; | |
1005 | if (current_tx_ptr->status.status_word != 0) | |
1006 | current_tx_ptr->status.status_word = 0; | |
1007 | blackfin_dcache_flush_range( | |
1008 | (u32)current_tx_ptr->packet, | |
1009 | (u32)(current_tx_ptr->packet + skb->len + 2)); | |
e190d6b1 BW |
1010 | } |
1011 | ||
805a8ab3 SZ |
1012 | /* make sure the internal data buffers in the core are drained |
1013 | * so that the DMA descriptors are completely written when the | |
1014 | * DMA engine goes to fetch them below | |
1015 | */ | |
1016 | SSYNC(); | |
1017 | ||
e190d6b1 BW |
1018 | /* enable this packet's dma */ |
1019 | current_tx_ptr->desc_a.config |= DMAEN; | |
1020 | ||
1021 | /* tx dma is running, just return */ | |
015dac88 | 1022 | if (bfin_read_DMA2_IRQ_STATUS() & DMA_RUN) |
e190d6b1 BW |
1023 | goto out; |
1024 | ||
1025 | /* tx dma is not running */ | |
1026 | bfin_write_DMA2_NEXT_DESC_PTR(&(current_tx_ptr->desc_a)); | |
1027 | /* dma enabled, read from memory, size is 6 */ | |
1028 | bfin_write_DMA2_CONFIG(current_tx_ptr->desc_a.config); | |
1029 | /* Turn on the EMAC tx */ | |
1030 | bfin_write_EMAC_OPMODE(bfin_read_EMAC_OPMODE() | TE); | |
1031 | ||
1032 | out: | |
1033 | adjust_tx_list(); | |
fe92afed BS |
1034 | |
1035 | bfin_tx_hwtstamp(dev, skb); | |
1036 | ||
e190d6b1 | 1037 | current_tx_ptr = current_tx_ptr->next; |
09f75cd7 JG |
1038 | dev->stats.tx_packets++; |
1039 | dev->stats.tx_bytes += (skb->len); | |
6ed10654 | 1040 | return NETDEV_TX_OK; |
e190d6b1 BW |
1041 | } |
1042 | ||
ad2864d8 | 1043 | #define IP_HEADER_OFF 0 |
ec497b32 PM |
1044 | #define RX_ERROR_MASK (RX_LONG | RX_ALIGN | RX_CRC | RX_LEN | \ |
1045 | RX_FRAG | RX_ADDR | RX_DMAO | RX_PHY | RX_LATE | RX_RANGE) | |
1046 | ||
7ef0a7ee | 1047 | static void bfin_mac_rx(struct net_device *dev) |
e190d6b1 BW |
1048 | { |
1049 | struct sk_buff *skb, *new_skb; | |
e190d6b1 | 1050 | unsigned short len; |
fe92afed | 1051 | struct bfin_mac_local *lp __maybe_unused = netdev_priv(dev); |
ad2864d8 SZ |
1052 | #if defined(BFIN_MAC_CSUM_OFFLOAD) |
1053 | unsigned int i; | |
1054 | unsigned char fcs[ETH_FCS_LEN + 1]; | |
1055 | #endif | |
e190d6b1 | 1056 | |
ec497b32 PM |
1057 | /* check if frame status word reports an error condition |
1058 | * we which case we simply drop the packet | |
1059 | */ | |
1060 | if (current_rx_ptr->status.status_word & RX_ERROR_MASK) { | |
1061 | printk(KERN_NOTICE DRV_NAME | |
1062 | ": rx: receive error - packet dropped\n"); | |
1063 | dev->stats.rx_dropped++; | |
1064 | goto out; | |
1065 | } | |
1066 | ||
e190d6b1 BW |
1067 | /* allocate a new skb for next time receive */ |
1068 | skb = current_rx_ptr->skb; | |
fe92afed | 1069 | |
015dac88 | 1070 | new_skb = dev_alloc_skb(PKT_BUF_SZ + NET_IP_ALIGN); |
e190d6b1 BW |
1071 | if (!new_skb) { |
1072 | printk(KERN_NOTICE DRV_NAME | |
1073 | ": rx: low on mem - packet dropped\n"); | |
09f75cd7 | 1074 | dev->stats.rx_dropped++; |
e190d6b1 BW |
1075 | goto out; |
1076 | } | |
1077 | /* reserve 2 bytes for RXDWA padding */ | |
015dac88 | 1078 | skb_reserve(new_skb, NET_IP_ALIGN); |
6e01d1a4 AD |
1079 | /* Invidate the data cache of skb->data range when it is write back |
1080 | * cache. It will prevent overwritting the new data from DMA | |
1081 | */ | |
1082 | blackfin_dcache_invalidate_range((unsigned long)new_skb->head, | |
1083 | (unsigned long)new_skb->end); | |
1084 | ||
f6e1e4f3 SZ |
1085 | current_rx_ptr->skb = new_skb; |
1086 | current_rx_ptr->desc_a.start_addr = (unsigned long)new_skb->data - 2; | |
1087 | ||
e190d6b1 | 1088 | len = (unsigned short)((current_rx_ptr->status.status_word) & RX_FRLEN); |
ad2864d8 SZ |
1089 | /* Deduce Ethernet FCS length from Ethernet payload length */ |
1090 | len -= ETH_FCS_LEN; | |
e190d6b1 | 1091 | skb_put(skb, len); |
e190d6b1 | 1092 | |
e190d6b1 | 1093 | skb->protocol = eth_type_trans(skb, dev); |
fe92afed BS |
1094 | |
1095 | bfin_rx_hwtstamp(dev, skb); | |
1096 | ||
e190d6b1 | 1097 | #if defined(BFIN_MAC_CSUM_OFFLOAD) |
ad2864d8 SZ |
1098 | /* Checksum offloading only works for IPv4 packets with the standard IP header |
1099 | * length of 20 bytes, because the blackfin MAC checksum calculation is | |
1100 | * based on that assumption. We must NOT use the calculated checksum if our | |
1101 | * IP version or header break that assumption. | |
1102 | */ | |
1103 | if (skb->data[IP_HEADER_OFF] == 0x45) { | |
1104 | skb->csum = current_rx_ptr->status.ip_payload_csum; | |
1105 | /* | |
1106 | * Deduce Ethernet FCS from hardware generated IP payload checksum. | |
1107 | * IP checksum is based on 16-bit one's complement algorithm. | |
1108 | * To deduce a value from checksum is equal to add its inversion. | |
1109 | * If the IP payload len is odd, the inversed FCS should also | |
1110 | * begin from odd address and leave first byte zero. | |
1111 | */ | |
1112 | if (skb->len % 2) { | |
1113 | fcs[0] = 0; | |
1114 | for (i = 0; i < ETH_FCS_LEN; i++) | |
1115 | fcs[i + 1] = ~skb->data[skb->len + i]; | |
1116 | skb->csum = csum_partial(fcs, ETH_FCS_LEN + 1, skb->csum); | |
1117 | } else { | |
1118 | for (i = 0; i < ETH_FCS_LEN; i++) | |
1119 | fcs[i] = ~skb->data[skb->len + i]; | |
1120 | skb->csum = csum_partial(fcs, ETH_FCS_LEN, skb->csum); | |
1121 | } | |
1122 | skb->ip_summed = CHECKSUM_COMPLETE; | |
1123 | } | |
e190d6b1 BW |
1124 | #endif |
1125 | ||
1126 | netif_rx(skb); | |
09f75cd7 JG |
1127 | dev->stats.rx_packets++; |
1128 | dev->stats.rx_bytes += len; | |
ec497b32 | 1129 | out: |
e190d6b1 BW |
1130 | current_rx_ptr->status.status_word = 0x00000000; |
1131 | current_rx_ptr = current_rx_ptr->next; | |
e190d6b1 BW |
1132 | } |
1133 | ||
1134 | /* interrupt routine to handle rx and error signal */ | |
7ef0a7ee | 1135 | static irqreturn_t bfin_mac_interrupt(int irq, void *dev_id) |
e190d6b1 BW |
1136 | { |
1137 | struct net_device *dev = dev_id; | |
1138 | int number = 0; | |
1139 | ||
1140 | get_one_packet: | |
1141 | if (current_rx_ptr->status.status_word == 0) { | |
1142 | /* no more new packet received */ | |
1143 | if (number == 0) { | |
1144 | if (current_rx_ptr->next->status.status_word != 0) { | |
1145 | current_rx_ptr = current_rx_ptr->next; | |
1146 | goto real_rx; | |
1147 | } | |
1148 | } | |
1149 | bfin_write_DMA1_IRQ_STATUS(bfin_read_DMA1_IRQ_STATUS() | | |
1150 | DMA_DONE | DMA_ERR); | |
1151 | return IRQ_HANDLED; | |
1152 | } | |
1153 | ||
1154 | real_rx: | |
7ef0a7ee | 1155 | bfin_mac_rx(dev); |
e190d6b1 BW |
1156 | number++; |
1157 | goto get_one_packet; | |
1158 | } | |
1159 | ||
1160 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
7ef0a7ee | 1161 | static void bfin_mac_poll(struct net_device *dev) |
e190d6b1 BW |
1162 | { |
1163 | disable_irq(IRQ_MAC_RX); | |
7ef0a7ee | 1164 | bfin_mac_interrupt(IRQ_MAC_RX, dev); |
e190d6b1 BW |
1165 | enable_irq(IRQ_MAC_RX); |
1166 | } | |
1167 | #endif /* CONFIG_NET_POLL_CONTROLLER */ | |
1168 | ||
7ef0a7ee | 1169 | static void bfin_mac_disable(void) |
e190d6b1 BW |
1170 | { |
1171 | unsigned int opmode; | |
1172 | ||
1173 | opmode = bfin_read_EMAC_OPMODE(); | |
1174 | opmode &= (~RE); | |
1175 | opmode &= (~TE); | |
1176 | /* Turn off the EMAC */ | |
1177 | bfin_write_EMAC_OPMODE(opmode); | |
1178 | } | |
1179 | ||
1180 | /* | |
1181 | * Enable Interrupts, Receive, and Transmit | |
1182 | */ | |
7ef0a7ee | 1183 | static void bfin_mac_enable(void) |
e190d6b1 BW |
1184 | { |
1185 | u32 opmode; | |
1186 | ||
b39d66a8 | 1187 | pr_debug("%s: %s\n", DRV_NAME, __func__); |
e190d6b1 BW |
1188 | |
1189 | /* Set RX DMA */ | |
1190 | bfin_write_DMA1_NEXT_DESC_PTR(&(rx_list_head->desc_a)); | |
1191 | bfin_write_DMA1_CONFIG(rx_list_head->desc_a.config); | |
1192 | ||
1193 | /* Wait MII done */ | |
0ed0563e | 1194 | bfin_mdio_poll(); |
e190d6b1 BW |
1195 | |
1196 | /* We enable only RX here */ | |
1197 | /* ASTP : Enable Automatic Pad Stripping | |
1198 | PR : Promiscuous Mode for test | |
1199 | PSF : Receive frames with total length less than 64 bytes. | |
1200 | FDMODE : Full Duplex Mode | |
1201 | LB : Internal Loopback for test | |
1202 | RE : Receiver Enable */ | |
1203 | opmode = bfin_read_EMAC_OPMODE(); | |
1204 | if (opmode & FDMODE) | |
1205 | opmode |= PSF; | |
1206 | else | |
1207 | opmode |= DRO | DC | PSF; | |
1208 | opmode |= RE; | |
1209 | ||
1210 | #if defined(CONFIG_BFIN_MAC_RMII) | |
1211 | opmode |= RMII; /* For Now only 100MBit are supported */ | |
6893ff1c | 1212 | #if (defined(CONFIG_BF537) || defined(CONFIG_BF536)) && CONFIG_BF_REV_0_2 |
e190d6b1 BW |
1213 | opmode |= TE; |
1214 | #endif | |
1215 | #endif | |
1216 | /* Turn on the EMAC rx */ | |
1217 | bfin_write_EMAC_OPMODE(opmode); | |
e190d6b1 BW |
1218 | } |
1219 | ||
1220 | /* Our watchdog timed out. Called by the networking layer */ | |
7ef0a7ee | 1221 | static void bfin_mac_timeout(struct net_device *dev) |
e190d6b1 | 1222 | { |
b39d66a8 | 1223 | pr_debug("%s: %s\n", dev->name, __func__); |
e190d6b1 | 1224 | |
7ef0a7ee | 1225 | bfin_mac_disable(); |
e190d6b1 BW |
1226 | |
1227 | /* reset tx queue */ | |
1228 | tx_list_tail = tx_list_head->next; | |
1229 | ||
7ef0a7ee | 1230 | bfin_mac_enable(); |
e190d6b1 BW |
1231 | |
1232 | /* We can accept TX packets again */ | |
1ae5dc34 | 1233 | dev->trans_start = jiffies; /* prevent tx timeout */ |
e190d6b1 BW |
1234 | netif_wake_queue(dev); |
1235 | } | |
1236 | ||
7ef0a7ee | 1237 | static void bfin_mac_multicast_hash(struct net_device *dev) |
775919bc AW |
1238 | { |
1239 | u32 emac_hashhi, emac_hashlo; | |
22bedad3 | 1240 | struct netdev_hw_addr *ha; |
775919bc | 1241 | char *addrs; |
775919bc AW |
1242 | u32 crc; |
1243 | ||
1244 | emac_hashhi = emac_hashlo = 0; | |
1245 | ||
22bedad3 JP |
1246 | netdev_for_each_mc_addr(ha, dev) { |
1247 | addrs = ha->addr; | |
775919bc AW |
1248 | |
1249 | /* skip non-multicast addresses */ | |
1250 | if (!(*addrs & 1)) | |
1251 | continue; | |
1252 | ||
1253 | crc = ether_crc(ETH_ALEN, addrs); | |
1254 | crc >>= 26; | |
1255 | ||
1256 | if (crc & 0x20) | |
1257 | emac_hashhi |= 1 << (crc & 0x1f); | |
1258 | else | |
1259 | emac_hashlo |= 1 << (crc & 0x1f); | |
1260 | } | |
1261 | ||
1262 | bfin_write_EMAC_HASHHI(emac_hashhi); | |
1263 | bfin_write_EMAC_HASHLO(emac_hashlo); | |
775919bc AW |
1264 | } |
1265 | ||
e190d6b1 BW |
1266 | /* |
1267 | * This routine will, depending on the values passed to it, | |
1268 | * either make it accept multicast packets, go into | |
1269 | * promiscuous mode (for TCPDUMP and cousins) or accept | |
1270 | * a select set of multicast packets | |
1271 | */ | |
7ef0a7ee | 1272 | static void bfin_mac_set_multicast_list(struct net_device *dev) |
e190d6b1 BW |
1273 | { |
1274 | u32 sysctl; | |
1275 | ||
1276 | if (dev->flags & IFF_PROMISC) { | |
1277 | printk(KERN_INFO "%s: set to promisc mode\n", dev->name); | |
1278 | sysctl = bfin_read_EMAC_OPMODE(); | |
c0da776b | 1279 | sysctl |= PR; |
e190d6b1 | 1280 | bfin_write_EMAC_OPMODE(sysctl); |
775919bc | 1281 | } else if (dev->flags & IFF_ALLMULTI) { |
e190d6b1 BW |
1282 | /* accept all multicast */ |
1283 | sysctl = bfin_read_EMAC_OPMODE(); | |
1284 | sysctl |= PAM; | |
1285 | bfin_write_EMAC_OPMODE(sysctl); | |
4cd24eaf | 1286 | } else if (!netdev_mc_empty(dev)) { |
775919bc AW |
1287 | /* set up multicast hash table */ |
1288 | sysctl = bfin_read_EMAC_OPMODE(); | |
1289 | sysctl |= HM; | |
1290 | bfin_write_EMAC_OPMODE(sysctl); | |
7ef0a7ee | 1291 | bfin_mac_multicast_hash(dev); |
e190d6b1 BW |
1292 | } else { |
1293 | /* clear promisc or multicast mode */ | |
1294 | sysctl = bfin_read_EMAC_OPMODE(); | |
1295 | sysctl &= ~(RAF | PAM); | |
1296 | bfin_write_EMAC_OPMODE(sysctl); | |
1297 | } | |
1298 | } | |
1299 | ||
fe92afed BS |
1300 | static int bfin_mac_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd) |
1301 | { | |
1302 | switch (cmd) { | |
1303 | case SIOCSHWTSTAMP: | |
1304 | return bfin_mac_hwtstamp_ioctl(netdev, ifr, cmd); | |
1305 | default: | |
1306 | return -EOPNOTSUPP; | |
1307 | } | |
1308 | } | |
1309 | ||
e190d6b1 BW |
1310 | /* |
1311 | * this puts the device in an inactive state | |
1312 | */ | |
7ef0a7ee | 1313 | static void bfin_mac_shutdown(struct net_device *dev) |
e190d6b1 BW |
1314 | { |
1315 | /* Turn off the EMAC */ | |
1316 | bfin_write_EMAC_OPMODE(0x00000000); | |
1317 | /* Turn off the EMAC RX DMA */ | |
1318 | bfin_write_DMA1_CONFIG(0x0000); | |
1319 | bfin_write_DMA2_CONFIG(0x0000); | |
1320 | } | |
1321 | ||
1322 | /* | |
1323 | * Open and Initialize the interface | |
1324 | * | |
1325 | * Set up everything, reset the card, etc.. | |
1326 | */ | |
7ef0a7ee | 1327 | static int bfin_mac_open(struct net_device *dev) |
e190d6b1 | 1328 | { |
7ef0a7ee | 1329 | struct bfin_mac_local *lp = netdev_priv(dev); |
4af4b840 | 1330 | int retval; |
b39d66a8 | 1331 | pr_debug("%s: %s\n", dev->name, __func__); |
e190d6b1 BW |
1332 | |
1333 | /* | |
1334 | * Check that the address is valid. If its not, refuse | |
1335 | * to bring the device up. The user must specify an | |
1336 | * address using ifconfig eth0 hw ether xx:xx:xx:xx:xx:xx | |
1337 | */ | |
1338 | if (!is_valid_ether_addr(dev->dev_addr)) { | |
1339 | printk(KERN_WARNING DRV_NAME ": no valid ethernet hw addr\n"); | |
1340 | return -EINVAL; | |
1341 | } | |
1342 | ||
1343 | /* initial rx and tx list */ | |
4af4b840 MH |
1344 | retval = desc_list_init(); |
1345 | ||
1346 | if (retval) | |
1347 | return retval; | |
e190d6b1 | 1348 | |
4ae5a3ad | 1349 | phy_start(lp->phydev); |
136492b2 | 1350 | phy_write(lp->phydev, MII_BMCR, BMCR_RESET); |
e190d6b1 | 1351 | setup_system_regs(dev); |
ee02fee8 | 1352 | setup_mac_addr(dev->dev_addr); |
7ef0a7ee BW |
1353 | bfin_mac_disable(); |
1354 | bfin_mac_enable(); | |
e190d6b1 BW |
1355 | pr_debug("hardware init finished\n"); |
1356 | netif_start_queue(dev); | |
1357 | netif_carrier_on(dev); | |
1358 | ||
1359 | return 0; | |
1360 | } | |
1361 | ||
1362 | /* | |
e190d6b1 BW |
1363 | * this makes the board clean up everything that it can |
1364 | * and not talk to the outside world. Caused by | |
1365 | * an 'ifconfig ethX down' | |
1366 | */ | |
7ef0a7ee | 1367 | static int bfin_mac_close(struct net_device *dev) |
e190d6b1 | 1368 | { |
7ef0a7ee | 1369 | struct bfin_mac_local *lp = netdev_priv(dev); |
b39d66a8 | 1370 | pr_debug("%s: %s\n", dev->name, __func__); |
e190d6b1 BW |
1371 | |
1372 | netif_stop_queue(dev); | |
1373 | netif_carrier_off(dev); | |
1374 | ||
4ae5a3ad | 1375 | phy_stop(lp->phydev); |
136492b2 | 1376 | phy_write(lp->phydev, MII_BMCR, BMCR_PDOWN); |
4ae5a3ad | 1377 | |
e190d6b1 | 1378 | /* clear everything */ |
7ef0a7ee | 1379 | bfin_mac_shutdown(dev); |
e190d6b1 BW |
1380 | |
1381 | /* free the rx/tx buffers */ | |
1382 | desc_list_free(); | |
1383 | ||
1384 | return 0; | |
1385 | } | |
1386 | ||
b63dc8fe MF |
1387 | static const struct net_device_ops bfin_mac_netdev_ops = { |
1388 | .ndo_open = bfin_mac_open, | |
1389 | .ndo_stop = bfin_mac_close, | |
1390 | .ndo_start_xmit = bfin_mac_hard_start_xmit, | |
1391 | .ndo_set_mac_address = bfin_mac_set_mac_address, | |
1392 | .ndo_tx_timeout = bfin_mac_timeout, | |
1393 | .ndo_set_multicast_list = bfin_mac_set_multicast_list, | |
fe92afed | 1394 | .ndo_do_ioctl = bfin_mac_ioctl, |
b63dc8fe MF |
1395 | .ndo_validate_addr = eth_validate_addr, |
1396 | .ndo_change_mtu = eth_change_mtu, | |
1397 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
1398 | .ndo_poll_controller = bfin_mac_poll, | |
1399 | #endif | |
1400 | }; | |
1401 | ||
d7b843d3 | 1402 | static int __devinit bfin_mac_probe(struct platform_device *pdev) |
e190d6b1 | 1403 | { |
7ef0a7ee BW |
1404 | struct net_device *ndev; |
1405 | struct bfin_mac_local *lp; | |
080c8255 GY |
1406 | struct platform_device *pd; |
1407 | int rc; | |
7ef0a7ee BW |
1408 | |
1409 | ndev = alloc_etherdev(sizeof(struct bfin_mac_local)); | |
1410 | if (!ndev) { | |
1411 | dev_err(&pdev->dev, "Cannot allocate net device!\n"); | |
1412 | return -ENOMEM; | |
1413 | } | |
1414 | ||
1415 | SET_NETDEV_DEV(ndev, &pdev->dev); | |
1416 | platform_set_drvdata(pdev, ndev); | |
1417 | lp = netdev_priv(ndev); | |
e190d6b1 BW |
1418 | |
1419 | /* Grab the MAC address in the MAC */ | |
7ef0a7ee BW |
1420 | *(__le32 *) (&(ndev->dev_addr[0])) = cpu_to_le32(bfin_read_EMAC_ADDRLO()); |
1421 | *(__le16 *) (&(ndev->dev_addr[4])) = cpu_to_le16((u16) bfin_read_EMAC_ADDRHI()); | |
e190d6b1 BW |
1422 | |
1423 | /* probe mac */ | |
1424 | /*todo: how to proble? which is revision_register */ | |
1425 | bfin_write_EMAC_ADDRLO(0x12345678); | |
1426 | if (bfin_read_EMAC_ADDRLO() != 0x12345678) { | |
7ef0a7ee BW |
1427 | dev_err(&pdev->dev, "Cannot detect Blackfin on-chip ethernet MAC controller!\n"); |
1428 | rc = -ENODEV; | |
1429 | goto out_err_probe_mac; | |
e190d6b1 BW |
1430 | } |
1431 | ||
e190d6b1 | 1432 | |
7ef0a7ee BW |
1433 | /* |
1434 | * Is it valid? (Did bootloader initialize it?) | |
1435 | * Grab the MAC from the board somehow | |
1436 | * this is done in the arch/blackfin/mach-bfxxx/boards/eth_mac.c | |
1437 | */ | |
1438 | if (!is_valid_ether_addr(ndev->dev_addr)) | |
1439 | bfin_get_ether_addr(ndev->dev_addr); | |
1440 | ||
e190d6b1 | 1441 | /* If still not valid, get a random one */ |
7ef0a7ee BW |
1442 | if (!is_valid_ether_addr(ndev->dev_addr)) |
1443 | random_ether_addr(ndev->dev_addr); | |
e190d6b1 | 1444 | |
7ef0a7ee | 1445 | setup_mac_addr(ndev->dev_addr); |
e190d6b1 | 1446 | |
080c8255 GY |
1447 | if (!pdev->dev.platform_data) { |
1448 | dev_err(&pdev->dev, "Cannot get platform device bfin_mii_bus!\n"); | |
1449 | rc = -ENODEV; | |
1450 | goto out_err_probe_mac; | |
7ef0a7ee | 1451 | } |
080c8255 GY |
1452 | pd = pdev->dev.platform_data; |
1453 | lp->mii_bus = platform_get_drvdata(pd); | |
1454 | lp->mii_bus->priv = ndev; | |
4ae5a3ad | 1455 | |
7ef0a7ee BW |
1456 | rc = mii_probe(ndev); |
1457 | if (rc) { | |
1458 | dev_err(&pdev->dev, "MII Probe failed!\n"); | |
1459 | goto out_err_mii_probe; | |
1460 | } | |
4ae5a3ad | 1461 | |
e190d6b1 | 1462 | /* Fill in the fields of the device structure with ethernet values. */ |
7ef0a7ee BW |
1463 | ether_setup(ndev); |
1464 | ||
149da651 | 1465 | ndev->netdev_ops = &bfin_mac_netdev_ops; |
679dce39 | 1466 | ndev->ethtool_ops = &bfin_mac_ethtool_ops; |
e190d6b1 | 1467 | |
e190d6b1 BW |
1468 | spin_lock_init(&lp->lock); |
1469 | ||
1470 | /* now, enable interrupts */ | |
1471 | /* register irq handler */ | |
7ef0a7ee | 1472 | rc = request_irq(IRQ_MAC_RX, bfin_mac_interrupt, |
91a455f0 | 1473 | IRQF_DISABLED, "EMAC_RX", ndev); |
7ef0a7ee BW |
1474 | if (rc) { |
1475 | dev_err(&pdev->dev, "Cannot request Blackfin MAC RX IRQ!\n"); | |
1476 | rc = -EBUSY; | |
1477 | goto out_err_request_irq; | |
e190d6b1 BW |
1478 | } |
1479 | ||
7ef0a7ee BW |
1480 | rc = register_netdev(ndev); |
1481 | if (rc) { | |
1482 | dev_err(&pdev->dev, "Cannot register net device!\n"); | |
1483 | goto out_err_reg_ndev; | |
e190d6b1 BW |
1484 | } |
1485 | ||
fe92afed BS |
1486 | bfin_mac_hwtstamp_init(ndev); |
1487 | ||
7ef0a7ee BW |
1488 | /* now, print out the card info, in a short format.. */ |
1489 | dev_info(&pdev->dev, "%s, Version %s\n", DRV_DESC, DRV_VERSION); | |
e190d6b1 | 1490 | |
7ef0a7ee | 1491 | return 0; |
e190d6b1 | 1492 | |
7ef0a7ee BW |
1493 | out_err_reg_ndev: |
1494 | free_irq(IRQ_MAC_RX, ndev); | |
1495 | out_err_request_irq: | |
1496 | out_err_mii_probe: | |
298cf9be | 1497 | mdiobus_unregister(lp->mii_bus); |
298cf9be | 1498 | mdiobus_free(lp->mii_bus); |
7ef0a7ee | 1499 | peripheral_free_list(pin_req); |
7ef0a7ee BW |
1500 | out_err_probe_mac: |
1501 | platform_set_drvdata(pdev, NULL); | |
1502 | free_netdev(ndev); | |
e190d6b1 | 1503 | |
7ef0a7ee | 1504 | return rc; |
e190d6b1 BW |
1505 | } |
1506 | ||
d7b843d3 | 1507 | static int __devexit bfin_mac_remove(struct platform_device *pdev) |
e190d6b1 BW |
1508 | { |
1509 | struct net_device *ndev = platform_get_drvdata(pdev); | |
7ef0a7ee | 1510 | struct bfin_mac_local *lp = netdev_priv(ndev); |
e190d6b1 BW |
1511 | |
1512 | platform_set_drvdata(pdev, NULL); | |
1513 | ||
080c8255 | 1514 | lp->mii_bus->priv = NULL; |
7ef0a7ee | 1515 | |
e190d6b1 BW |
1516 | unregister_netdev(ndev); |
1517 | ||
1518 | free_irq(IRQ_MAC_RX, ndev); | |
1519 | ||
1520 | free_netdev(ndev); | |
1521 | ||
7ef0a7ee | 1522 | peripheral_free_list(pin_req); |
e190d6b1 BW |
1523 | |
1524 | return 0; | |
1525 | } | |
1526 | ||
496a34c2 BW |
1527 | #ifdef CONFIG_PM |
1528 | static int bfin_mac_suspend(struct platform_device *pdev, pm_message_t mesg) | |
e190d6b1 | 1529 | { |
496a34c2 | 1530 | struct net_device *net_dev = platform_get_drvdata(pdev); |
53fd3f28 | 1531 | struct bfin_mac_local *lp = netdev_priv(net_dev); |
496a34c2 | 1532 | |
53fd3f28 MH |
1533 | if (lp->wol) { |
1534 | bfin_write_EMAC_OPMODE((bfin_read_EMAC_OPMODE() & ~TE) | RE); | |
1535 | bfin_write_EMAC_WKUP_CTL(MPKE); | |
1536 | enable_irq_wake(IRQ_MAC_WAKEDET); | |
1537 | } else { | |
1538 | if (netif_running(net_dev)) | |
1539 | bfin_mac_close(net_dev); | |
1540 | } | |
496a34c2 | 1541 | |
e190d6b1 BW |
1542 | return 0; |
1543 | } | |
1544 | ||
1545 | static int bfin_mac_resume(struct platform_device *pdev) | |
1546 | { | |
496a34c2 | 1547 | struct net_device *net_dev = platform_get_drvdata(pdev); |
53fd3f28 | 1548 | struct bfin_mac_local *lp = netdev_priv(net_dev); |
496a34c2 | 1549 | |
53fd3f28 MH |
1550 | if (lp->wol) { |
1551 | bfin_write_EMAC_OPMODE(bfin_read_EMAC_OPMODE() | TE); | |
1552 | bfin_write_EMAC_WKUP_CTL(0); | |
1553 | disable_irq_wake(IRQ_MAC_WAKEDET); | |
1554 | } else { | |
1555 | if (netif_running(net_dev)) | |
1556 | bfin_mac_open(net_dev); | |
1557 | } | |
496a34c2 | 1558 | |
e190d6b1 BW |
1559 | return 0; |
1560 | } | |
496a34c2 BW |
1561 | #else |
1562 | #define bfin_mac_suspend NULL | |
1563 | #define bfin_mac_resume NULL | |
1564 | #endif /* CONFIG_PM */ | |
e190d6b1 | 1565 | |
080c8255 GY |
1566 | static int __devinit bfin_mii_bus_probe(struct platform_device *pdev) |
1567 | { | |
1568 | struct mii_bus *miibus; | |
1569 | int rc, i; | |
1570 | ||
1571 | /* | |
1572 | * We are setting up a network card, | |
1573 | * so set the GPIO pins to Ethernet mode | |
1574 | */ | |
1575 | rc = peripheral_request_list(pin_req, DRV_NAME); | |
1576 | if (rc) { | |
1577 | dev_err(&pdev->dev, "Requesting peripherals failed!\n"); | |
1578 | return rc; | |
1579 | } | |
1580 | ||
1581 | rc = -ENOMEM; | |
1582 | miibus = mdiobus_alloc(); | |
1583 | if (miibus == NULL) | |
1584 | goto out_err_alloc; | |
1585 | miibus->read = bfin_mdiobus_read; | |
1586 | miibus->write = bfin_mdiobus_write; | |
1587 | miibus->reset = bfin_mdiobus_reset; | |
1588 | ||
1589 | miibus->parent = &pdev->dev; | |
1590 | miibus->name = "bfin_mii_bus"; | |
1591 | snprintf(miibus->id, MII_BUS_ID_SIZE, "0"); | |
1592 | miibus->irq = kmalloc(sizeof(int)*PHY_MAX_ADDR, GFP_KERNEL); | |
1593 | if (miibus->irq == NULL) | |
1594 | goto out_err_alloc; | |
1595 | for (i = 0; i < PHY_MAX_ADDR; ++i) | |
1596 | miibus->irq[i] = PHY_POLL; | |
1597 | ||
1598 | rc = mdiobus_register(miibus); | |
1599 | if (rc) { | |
1600 | dev_err(&pdev->dev, "Cannot register MDIO bus!\n"); | |
1601 | goto out_err_mdiobus_register; | |
1602 | } | |
1603 | ||
1604 | platform_set_drvdata(pdev, miibus); | |
1605 | return 0; | |
1606 | ||
1607 | out_err_mdiobus_register: | |
1608 | mdiobus_free(miibus); | |
1609 | out_err_alloc: | |
1610 | peripheral_free_list(pin_req); | |
1611 | ||
1612 | return rc; | |
1613 | } | |
1614 | ||
1615 | static int __devexit bfin_mii_bus_remove(struct platform_device *pdev) | |
1616 | { | |
1617 | struct mii_bus *miibus = platform_get_drvdata(pdev); | |
1618 | platform_set_drvdata(pdev, NULL); | |
1619 | mdiobus_unregister(miibus); | |
1620 | mdiobus_free(miibus); | |
1621 | peripheral_free_list(pin_req); | |
1622 | return 0; | |
1623 | } | |
1624 | ||
1625 | static struct platform_driver bfin_mii_bus_driver = { | |
1626 | .probe = bfin_mii_bus_probe, | |
1627 | .remove = __devexit_p(bfin_mii_bus_remove), | |
1628 | .driver = { | |
1629 | .name = "bfin_mii_bus", | |
1630 | .owner = THIS_MODULE, | |
1631 | }, | |
1632 | }; | |
1633 | ||
e190d6b1 BW |
1634 | static struct platform_driver bfin_mac_driver = { |
1635 | .probe = bfin_mac_probe, | |
d7b843d3 | 1636 | .remove = __devexit_p(bfin_mac_remove), |
e190d6b1 BW |
1637 | .resume = bfin_mac_resume, |
1638 | .suspend = bfin_mac_suspend, | |
1639 | .driver = { | |
72abb461 KS |
1640 | .name = DRV_NAME, |
1641 | .owner = THIS_MODULE, | |
1642 | }, | |
e190d6b1 BW |
1643 | }; |
1644 | ||
1645 | static int __init bfin_mac_init(void) | |
1646 | { | |
080c8255 GY |
1647 | int ret; |
1648 | ret = platform_driver_register(&bfin_mii_bus_driver); | |
1649 | if (!ret) | |
1650 | return platform_driver_register(&bfin_mac_driver); | |
1651 | return -ENODEV; | |
e190d6b1 BW |
1652 | } |
1653 | ||
1654 | module_init(bfin_mac_init); | |
1655 | ||
1656 | static void __exit bfin_mac_cleanup(void) | |
1657 | { | |
1658 | platform_driver_unregister(&bfin_mac_driver); | |
080c8255 | 1659 | platform_driver_unregister(&bfin_mii_bus_driver); |
e190d6b1 BW |
1660 | } |
1661 | ||
1662 | module_exit(bfin_mac_cleanup); | |
72abb461 | 1663 |