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[PATCH] bnx2: update firmware for 5708
[deliverable/linux.git] / drivers / net / bnx2.c
CommitLineData
b6016b76
MC		 1/* bnx2.c: Broadcom NX2 network driver.
2 *
3 * Copyright (c) 2004, 2005 Broadcom Corporation
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
8 *
9 * Written by: Michael Chan (mchan@broadcom.com)
10 */
11
12#include "bnx2.h"
13#include "bnx2_fw.h"
14
15#define DRV_MODULE_NAME "bnx2"
16#define PFX DRV_MODULE_NAME ": "
c921e4c4
MC		 17#define DRV_MODULE_VERSION "1.2.21"
18#define DRV_MODULE_RELDATE "September 7, 2005"
b6016b76
MC		 19
20#define RUN_AT(x) (jiffies + (x))
21
22/* Time in jiffies before concluding the transmitter is hung. */
23#define TX_TIMEOUT (5*HZ)
24
25static char version[] __devinitdata =
26 "Broadcom NetXtreme II Gigabit Ethernet Driver " DRV_MODULE_NAME " v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
27
28MODULE_AUTHOR("Michael Chan <mchan@broadcom.com>");
29MODULE_DESCRIPTION("Broadcom NetXtreme II BCM5706 Driver");
30MODULE_LICENSE("GPL");
31MODULE_VERSION(DRV_MODULE_VERSION);
32
33static int disable_msi = 0;
34
35module_param(disable_msi, int, 0);
36MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)");
37
38typedef enum {
39 BCM5706 = 0,
40 NC370T,
41 NC370I,
42 BCM5706S,
43 NC370F,
5b0c76ad
MC		 44 BCM5708,
45 BCM5708S,
b6016b76
MC		 46} board_t;
47
48/* indexed by board_t, above */
49static struct {
50 char *name;
51} board_info[] __devinitdata = {
52 { "Broadcom NetXtreme II BCM5706 1000Base-T" },
53 { "HP NC370T Multifunction Gigabit Server Adapter" },
54 { "HP NC370i Multifunction Gigabit Server Adapter" },
55 { "Broadcom NetXtreme II BCM5706 1000Base-SX" },
56 { "HP NC370F Multifunction Gigabit Server Adapter" },
5b0c76ad
MC		 57 { "Broadcom NetXtreme II BCM5708 1000Base-T" },
58 { "Broadcom NetXtreme II BCM5708 1000Base-SX" },
b6016b76
MC		 59 };
60
61static struct pci_device_id bnx2_pci_tbl[] = {
62 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706,
63 PCI_VENDOR_ID_HP, 0x3101, 0, 0, NC370T },
64 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706,
65 PCI_VENDOR_ID_HP, 0x3106, 0, 0, NC370I },
66 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706,
67 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5706 },
5b0c76ad
MC		 68 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5708,
69 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5708 },
b6016b76
MC		 70 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706S,
71 PCI_VENDOR_ID_HP, 0x3102, 0, 0, NC370F },
72 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706S,
73 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5706S },
5b0c76ad
MC		 74 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5708S,
75 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5708S },
b6016b76
MC		 76 { 0, }
77};
78
79static struct flash_spec flash_table[] =
80{
81 /* Slow EEPROM */
82 {0x00000000, 0x40030380, 0x009f0081, 0xa184a053, 0xaf000400,
83 1, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE,
84 SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE,
85 "EEPROM - slow"},
86 /* Fast EEPROM */
87 {0x02000000, 0x62008380, 0x009f0081, 0xa184a053, 0xaf000400,
88 1, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE,
89 SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE,
90 "EEPROM - fast"},
91 /* ATMEL AT45DB011B (buffered flash) */
92 {0x02000003, 0x6e008173, 0x00570081, 0x68848353, 0xaf000400,
93 1, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
94 BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE,
95 "Buffered flash"},
96 /* Saifun SA25F005 (non-buffered flash) */
97 /* strap, cfg1, & write1 need updates */
98 {0x01000003, 0x5f008081, 0x00050081, 0x03840253, 0xaf020406,
99 0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
100 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE,
101 "Non-buffered flash (64kB)"},
102 /* Saifun SA25F010 (non-buffered flash) */
103 /* strap, cfg1, & write1 need updates */
104 {0x00000001, 0x47008081, 0x00050081, 0x03840253, 0xaf020406,
105 0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
106 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*2,
107 "Non-buffered flash (128kB)"},
108 /* Saifun SA25F020 (non-buffered flash) */
109 /* strap, cfg1, & write1 need updates */
110 {0x00000003, 0x4f008081, 0x00050081, 0x03840253, 0xaf020406,
111 0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
112 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*4,
113 "Non-buffered flash (256kB)"},
114};
115
116MODULE_DEVICE_TABLE(pci, bnx2_pci_tbl);
117
e89bbf10
MC		 118static inline u32 bnx2_tx_avail(struct bnx2 *bp)
119{
120 u32 diff = TX_RING_IDX(bp->tx_prod) - TX_RING_IDX(bp->tx_cons);
121
122 if (diff > MAX_TX_DESC_CNT)
123 diff = (diff & MAX_TX_DESC_CNT) - 1;
124 return (bp->tx_ring_size - diff);
125}
126
b6016b76
MC		 127static u32
128bnx2_reg_rd_ind(struct bnx2 *bp, u32 offset)
129{
130 REG_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, offset);
131 return (REG_RD(bp, BNX2_PCICFG_REG_WINDOW));
132}
133
134static void
135bnx2_reg_wr_ind(struct bnx2 *bp, u32 offset, u32 val)
136{
137 REG_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, offset);
138 REG_WR(bp, BNX2_PCICFG_REG_WINDOW, val);
139}
140
141static void
142bnx2_ctx_wr(struct bnx2 *bp, u32 cid_addr, u32 offset, u32 val)
143{
144 offset += cid_addr;
145 REG_WR(bp, BNX2_CTX_DATA_ADR, offset);
146 REG_WR(bp, BNX2_CTX_DATA, val);
147}
148
149static int
150bnx2_read_phy(struct bnx2 *bp, u32 reg, u32 *val)
151{
152 u32 val1;
153 int i, ret;
154
155 if (bp->phy_flags & PHY_INT_MODE_AUTO_POLLING_FLAG) {
156 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
157 val1 &= ~BNX2_EMAC_MDIO_MODE_AUTO_POLL;
158
159 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
160 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
161
162 udelay(40);
163 }
164
165 val1 = (bp->phy_addr << 21) | (reg << 16) |
166 BNX2_EMAC_MDIO_COMM_COMMAND_READ | BNX2_EMAC_MDIO_COMM_DISEXT |
167 BNX2_EMAC_MDIO_COMM_START_BUSY;
168 REG_WR(bp, BNX2_EMAC_MDIO_COMM, val1);
169
170 for (i = 0; i < 50; i++) {
171 udelay(10);
172
173 val1 = REG_RD(bp, BNX2_EMAC_MDIO_COMM);
174 if (!(val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)) {
175 udelay(5);
176
177 val1 = REG_RD(bp, BNX2_EMAC_MDIO_COMM);
178 val1 &= BNX2_EMAC_MDIO_COMM_DATA;
179
180 break;
181 }
182 }
183
184 if (val1 & BNX2_EMAC_MDIO_COMM_START_BUSY) {
185 *val = 0x0;
186 ret = -EBUSY;
187 }
188 else {
189 *val = val1;
190 ret = 0;
191 }
192
193 if (bp->phy_flags & PHY_INT_MODE_AUTO_POLLING_FLAG) {
194 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
195 val1 |= BNX2_EMAC_MDIO_MODE_AUTO_POLL;
196
197 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
198 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
199
200 udelay(40);
201 }
202
203 return ret;
204}
205
206static int
207bnx2_write_phy(struct bnx2 *bp, u32 reg, u32 val)
208{
209 u32 val1;
210 int i, ret;
211
212 if (bp->phy_flags & PHY_INT_MODE_AUTO_POLLING_FLAG) {
213 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
214 val1 &= ~BNX2_EMAC_MDIO_MODE_AUTO_POLL;
215
216 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
217 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
218
219 udelay(40);
220 }
221
222 val1 = (bp->phy_addr << 21) | (reg << 16) | val |
223 BNX2_EMAC_MDIO_COMM_COMMAND_WRITE |
224 BNX2_EMAC_MDIO_COMM_START_BUSY | BNX2_EMAC_MDIO_COMM_DISEXT;
225 REG_WR(bp, BNX2_EMAC_MDIO_COMM, val1);
226
227 for (i = 0; i < 50; i++) {
228 udelay(10);
229
230 val1 = REG_RD(bp, BNX2_EMAC_MDIO_COMM);
231 if (!(val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)) {
232 udelay(5);
233 break;
234 }
235 }
236
237 if (val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)
238 ret = -EBUSY;
239 else
240 ret = 0;
241
242 if (bp->phy_flags & PHY_INT_MODE_AUTO_POLLING_FLAG) {
243 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
244 val1 |= BNX2_EMAC_MDIO_MODE_AUTO_POLL;
245
246 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
247 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
248
249 udelay(40);
250 }
251
252 return ret;
253}
254
255static void
256bnx2_disable_int(struct bnx2 *bp)
257{
258 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
259 BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
260 REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD);
261}
262
263static void
264bnx2_enable_int(struct bnx2 *bp)
265{
266 u32 val;
267
268 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
269 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID | bp->last_status_idx);
270
271 val = REG_RD(bp, BNX2_HC_COMMAND);
272 REG_WR(bp, BNX2_HC_COMMAND, val | BNX2_HC_COMMAND_COAL_NOW);
273}
274
275static void
276bnx2_disable_int_sync(struct bnx2 *bp)
277{
278 atomic_inc(&bp->intr_sem);
279 bnx2_disable_int(bp);
280 synchronize_irq(bp->pdev->irq);
281}
282
283static void
284bnx2_netif_stop(struct bnx2 *bp)
285{
286 bnx2_disable_int_sync(bp);
287 if (netif_running(bp->dev)) {
288 netif_poll_disable(bp->dev);
289 netif_tx_disable(bp->dev);
290 bp->dev->trans_start = jiffies; /* prevent tx timeout */
291 }
292}
293
294static void
295bnx2_netif_start(struct bnx2 *bp)
296{
297 if (atomic_dec_and_test(&bp->intr_sem)) {
298 if (netif_running(bp->dev)) {
299 netif_wake_queue(bp->dev);
300 netif_poll_enable(bp->dev);
301 bnx2_enable_int(bp);
302 }
303 }
304}
305
306static void
307bnx2_free_mem(struct bnx2 *bp)
308{
309 if (bp->stats_blk) {
310 pci_free_consistent(bp->pdev, sizeof(struct statistics_block),
311 bp->stats_blk, bp->stats_blk_mapping);
312 bp->stats_blk = NULL;
313 }
314 if (bp->status_blk) {
315 pci_free_consistent(bp->pdev, sizeof(struct status_block),
316 bp->status_blk, bp->status_blk_mapping);
317 bp->status_blk = NULL;
318 }
319 if (bp->tx_desc_ring) {
320 pci_free_consistent(bp->pdev,
321 sizeof(struct tx_bd) * TX_DESC_CNT,
322 bp->tx_desc_ring, bp->tx_desc_mapping);
323 bp->tx_desc_ring = NULL;
324 }
b4558ea9
JJ		 325 kfree(bp->tx_buf_ring);
326 bp->tx_buf_ring = NULL;
b6016b76
MC		 327 if (bp->rx_desc_ring) {
328 pci_free_consistent(bp->pdev,
329 sizeof(struct rx_bd) * RX_DESC_CNT,
330 bp->rx_desc_ring, bp->rx_desc_mapping);
331 bp->rx_desc_ring = NULL;
332 }
b4558ea9
JJ		 333 kfree(bp->rx_buf_ring);
334 bp->rx_buf_ring = NULL;
b6016b76
MC		 335}
336
337static int
338bnx2_alloc_mem(struct bnx2 *bp)
339{
340 bp->tx_buf_ring = kmalloc(sizeof(struct sw_bd) * TX_DESC_CNT,
341 GFP_KERNEL);
342 if (bp->tx_buf_ring == NULL)
343 return -ENOMEM;
344
345 memset(bp->tx_buf_ring, 0, sizeof(struct sw_bd) * TX_DESC_CNT);
346 bp->tx_desc_ring = pci_alloc_consistent(bp->pdev,
347 sizeof(struct tx_bd) *
348 TX_DESC_CNT,
349 &bp->tx_desc_mapping);
350 if (bp->tx_desc_ring == NULL)
351 goto alloc_mem_err;
352
353 bp->rx_buf_ring = kmalloc(sizeof(struct sw_bd) * RX_DESC_CNT,
354 GFP_KERNEL);
355 if (bp->rx_buf_ring == NULL)
356 goto alloc_mem_err;
357
358 memset(bp->rx_buf_ring, 0, sizeof(struct sw_bd) * RX_DESC_CNT);
359 bp->rx_desc_ring = pci_alloc_consistent(bp->pdev,
360 sizeof(struct rx_bd) *
361 RX_DESC_CNT,
362 &bp->rx_desc_mapping);
363 if (bp->rx_desc_ring == NULL)
364 goto alloc_mem_err;
365
366 bp->status_blk = pci_alloc_consistent(bp->pdev,
367 sizeof(struct status_block),
368 &bp->status_blk_mapping);
369 if (bp->status_blk == NULL)
370 goto alloc_mem_err;
371
372 memset(bp->status_blk, 0, sizeof(struct status_block));
373
374 bp->stats_blk = pci_alloc_consistent(bp->pdev,
375 sizeof(struct statistics_block),
376 &bp->stats_blk_mapping);
377 if (bp->stats_blk == NULL)
378 goto alloc_mem_err;
379
380 memset(bp->stats_blk, 0, sizeof(struct statistics_block));
381
382 return 0;
383
384alloc_mem_err:
385 bnx2_free_mem(bp);
386 return -ENOMEM;
387}
388
389static void
390bnx2_report_link(struct bnx2 *bp)
391{
392 if (bp->link_up) {
393 netif_carrier_on(bp->dev);
394 printk(KERN_INFO PFX "%s NIC Link is Up, ", bp->dev->name);
395
396 printk("%d Mbps ", bp->line_speed);
397
398 if (bp->duplex == DUPLEX_FULL)
399 printk("full duplex");
400 else
401 printk("half duplex");
402
403 if (bp->flow_ctrl) {
404 if (bp->flow_ctrl & FLOW_CTRL_RX) {
405 printk(", receive ");
406 if (bp->flow_ctrl & FLOW_CTRL_TX)
407 printk("& transmit ");
408 }
409 else {
410 printk(", transmit ");
411 }
412 printk("flow control ON");
413 }
414 printk("\n");
415 }
416 else {
417 netif_carrier_off(bp->dev);
418 printk(KERN_ERR PFX "%s NIC Link is Down\n", bp->dev->name);
419 }
420}
421
422static void
423bnx2_resolve_flow_ctrl(struct bnx2 *bp)
424{
425 u32 local_adv, remote_adv;
426
427 bp->flow_ctrl = 0;
428 if ((bp->autoneg & (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) !=
429 (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) {
430
431 if (bp->duplex == DUPLEX_FULL) {
432 bp->flow_ctrl = bp->req_flow_ctrl;
433 }
434 return;
435 }
436
437 if (bp->duplex != DUPLEX_FULL) {
438 return;
439 }
440
5b0c76ad
MC		 441 if ((bp->phy_flags & PHY_SERDES_FLAG) &&
442 (CHIP_NUM(bp) == CHIP_NUM_5708)) {
443 u32 val;
444
445 bnx2_read_phy(bp, BCM5708S_1000X_STAT1, &val);
446 if (val & BCM5708S_1000X_STAT1_TX_PAUSE)
447 bp->flow_ctrl |= FLOW_CTRL_TX;
448 if (val & BCM5708S_1000X_STAT1_RX_PAUSE)
449 bp->flow_ctrl |= FLOW_CTRL_RX;
450 return;
451 }
452
b6016b76
MC		 453 bnx2_read_phy(bp, MII_ADVERTISE, &local_adv);
454 bnx2_read_phy(bp, MII_LPA, &remote_adv);
455
456 if (bp->phy_flags & PHY_SERDES_FLAG) {
457 u32 new_local_adv = 0;
458 u32 new_remote_adv = 0;
459
460 if (local_adv & ADVERTISE_1000XPAUSE)
461 new_local_adv |= ADVERTISE_PAUSE_CAP;
462 if (local_adv & ADVERTISE_1000XPSE_ASYM)
463 new_local_adv |= ADVERTISE_PAUSE_ASYM;
464 if (remote_adv & ADVERTISE_1000XPAUSE)
465 new_remote_adv |= ADVERTISE_PAUSE_CAP;
466 if (remote_adv & ADVERTISE_1000XPSE_ASYM)
467 new_remote_adv |= ADVERTISE_PAUSE_ASYM;
468
469 local_adv = new_local_adv;
470 remote_adv = new_remote_adv;
471 }
472
473 /* See Table 28B-3 of 802.3ab-1999 spec. */
474 if (local_adv & ADVERTISE_PAUSE_CAP) {
475 if(local_adv & ADVERTISE_PAUSE_ASYM) {
476 if (remote_adv & ADVERTISE_PAUSE_CAP) {
477 bp->flow_ctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
478 }
479 else if (remote_adv & ADVERTISE_PAUSE_ASYM) {
480 bp->flow_ctrl = FLOW_CTRL_RX;
481 }
482 }
483 else {
484 if (remote_adv & ADVERTISE_PAUSE_CAP) {
485 bp->flow_ctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
486 }
487 }
488 }
489 else if (local_adv & ADVERTISE_PAUSE_ASYM) {
490 if ((remote_adv & ADVERTISE_PAUSE_CAP) &&
491 (remote_adv & ADVERTISE_PAUSE_ASYM)) {
492
493 bp->flow_ctrl = FLOW_CTRL_TX;
494 }
495 }
496}
497
498static int
5b0c76ad
MC		 499bnx2_5708s_linkup(struct bnx2 *bp)
500{
501 u32 val;
502
503 bp->link_up = 1;
504 bnx2_read_phy(bp, BCM5708S_1000X_STAT1, &val);
505 switch (val & BCM5708S_1000X_STAT1_SPEED_MASK) {
506 case BCM5708S_1000X_STAT1_SPEED_10:
507 bp->line_speed = SPEED_10;
508 break;
509 case BCM5708S_1000X_STAT1_SPEED_100:
510 bp->line_speed = SPEED_100;
511 break;
512 case BCM5708S_1000X_STAT1_SPEED_1G:
513 bp->line_speed = SPEED_1000;
514 break;
515 case BCM5708S_1000X_STAT1_SPEED_2G5:
516 bp->line_speed = SPEED_2500;
517 break;
518 }
519 if (val & BCM5708S_1000X_STAT1_FD)
520 bp->duplex = DUPLEX_FULL;
521 else
522 bp->duplex = DUPLEX_HALF;
523
524 return 0;
525}
526
527static int
528bnx2_5706s_linkup(struct bnx2 *bp)
b6016b76
MC		 529{
530 u32 bmcr, local_adv, remote_adv, common;
531
532 bp->link_up = 1;
533 bp->line_speed = SPEED_1000;
534
535 bnx2_read_phy(bp, MII_BMCR, &bmcr);
536 if (bmcr & BMCR_FULLDPLX) {
537 bp->duplex = DUPLEX_FULL;
538 }
539 else {
540 bp->duplex = DUPLEX_HALF;
541 }
542
543 if (!(bmcr & BMCR_ANENABLE)) {
544 return 0;
545 }
546
547 bnx2_read_phy(bp, MII_ADVERTISE, &local_adv);
548 bnx2_read_phy(bp, MII_LPA, &remote_adv);
549
550 common = local_adv & remote_adv;
551 if (common & (ADVERTISE_1000XHALF | ADVERTISE_1000XFULL)) {
552
553 if (common & ADVERTISE_1000XFULL) {
554 bp->duplex = DUPLEX_FULL;
555 }
556 else {
557 bp->duplex = DUPLEX_HALF;
558 }
559 }
560
561 return 0;
562}
563
564static int
565bnx2_copper_linkup(struct bnx2 *bp)
566{
567 u32 bmcr;
568
569 bnx2_read_phy(bp, MII_BMCR, &bmcr);
570 if (bmcr & BMCR_ANENABLE) {
571 u32 local_adv, remote_adv, common;
572
573 bnx2_read_phy(bp, MII_CTRL1000, &local_adv);
574 bnx2_read_phy(bp, MII_STAT1000, &remote_adv);
575
576 common = local_adv & (remote_adv >> 2);
577 if (common & ADVERTISE_1000FULL) {
578 bp->line_speed = SPEED_1000;
579 bp->duplex = DUPLEX_FULL;
580 }
581 else if (common & ADVERTISE_1000HALF) {
582 bp->line_speed = SPEED_1000;
583 bp->duplex = DUPLEX_HALF;
584 }
585 else {
586 bnx2_read_phy(bp, MII_ADVERTISE, &local_adv);
587 bnx2_read_phy(bp, MII_LPA, &remote_adv);
588
589 common = local_adv & remote_adv;
590 if (common & ADVERTISE_100FULL) {
591 bp->line_speed = SPEED_100;
592 bp->duplex = DUPLEX_FULL;
593 }
594 else if (common & ADVERTISE_100HALF) {
595 bp->line_speed = SPEED_100;
596 bp->duplex = DUPLEX_HALF;
597 }
598 else if (common & ADVERTISE_10FULL) {
599 bp->line_speed = SPEED_10;
600 bp->duplex = DUPLEX_FULL;
601 }
602 else if (common & ADVERTISE_10HALF) {
603 bp->line_speed = SPEED_10;
604 bp->duplex = DUPLEX_HALF;
605 }
606 else {
607 bp->line_speed = 0;
608 bp->link_up = 0;
609 }
610 }
611 }
612 else {
613 if (bmcr & BMCR_SPEED100) {
614 bp->line_speed = SPEED_100;
615 }
616 else {
617 bp->line_speed = SPEED_10;
618 }
619 if (bmcr & BMCR_FULLDPLX) {
620 bp->duplex = DUPLEX_FULL;
621 }
622 else {
623 bp->duplex = DUPLEX_HALF;
624 }
625 }
626
627 return 0;
628}
629
630static int
631bnx2_set_mac_link(struct bnx2 *bp)
632{
633 u32 val;
634
635 REG_WR(bp, BNX2_EMAC_TX_LENGTHS, 0x2620);
636 if (bp->link_up && (bp->line_speed == SPEED_1000) &&
637 (bp->duplex == DUPLEX_HALF)) {
638 REG_WR(bp, BNX2_EMAC_TX_LENGTHS, 0x26ff);
639 }
640
641 /* Configure the EMAC mode register. */
642 val = REG_RD(bp, BNX2_EMAC_MODE);
643
644 val &= ~(BNX2_EMAC_MODE_PORT | BNX2_EMAC_MODE_HALF_DUPLEX |
5b0c76ad
MC		 645 BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK |
646 BNX2_EMAC_MODE_25G);
b6016b76
MC		 647
648 if (bp->link_up) {
5b0c76ad
MC		 649 switch (bp->line_speed) {
650 case SPEED_10:
651 if (CHIP_NUM(bp) == CHIP_NUM_5708) {
652 val |= BNX2_EMAC_MODE_PORT_MII_10;
653 break;
654 }
655 /* fall through */
656 case SPEED_100:
657 val |= BNX2_EMAC_MODE_PORT_MII;
658 break;
659 case SPEED_2500:
660 val |= BNX2_EMAC_MODE_25G;
661 /* fall through */
662 case SPEED_1000:
663 val |= BNX2_EMAC_MODE_PORT_GMII;
664 break;
665 }
b6016b76
MC		 666 }
667 else {
668 val |= BNX2_EMAC_MODE_PORT_GMII;
669 }
670
671 /* Set the MAC to operate in the appropriate duplex mode. */
672 if (bp->duplex == DUPLEX_HALF)
673 val |= BNX2_EMAC_MODE_HALF_DUPLEX;
674 REG_WR(bp, BNX2_EMAC_MODE, val);
675
676 /* Enable/disable rx PAUSE. */
677 bp->rx_mode &= ~BNX2_EMAC_RX_MODE_FLOW_EN;
678
679 if (bp->flow_ctrl & FLOW_CTRL_RX)
680 bp->rx_mode |= BNX2_EMAC_RX_MODE_FLOW_EN;
681 REG_WR(bp, BNX2_EMAC_RX_MODE, bp->rx_mode);
682
683 /* Enable/disable tx PAUSE. */
684 val = REG_RD(bp, BNX2_EMAC_TX_MODE);
685 val &= ~BNX2_EMAC_TX_MODE_FLOW_EN;
686
687 if (bp->flow_ctrl & FLOW_CTRL_TX)
688 val |= BNX2_EMAC_TX_MODE_FLOW_EN;
689 REG_WR(bp, BNX2_EMAC_TX_MODE, val);
690
691 /* Acknowledge the interrupt. */
692 REG_WR(bp, BNX2_EMAC_STATUS, BNX2_EMAC_STATUS_LINK_CHANGE);
693
694 return 0;
695}
696
697static int
698bnx2_set_link(struct bnx2 *bp)
699{
700 u32 bmsr;
701 u8 link_up;
702
703 if (bp->loopback == MAC_LOOPBACK) {
704 bp->link_up = 1;
705 return 0;
706 }
707
708 link_up = bp->link_up;
709
710 bnx2_read_phy(bp, MII_BMSR, &bmsr);
711 bnx2_read_phy(bp, MII_BMSR, &bmsr);
712
713 if ((bp->phy_flags & PHY_SERDES_FLAG) &&
714 (CHIP_NUM(bp) == CHIP_NUM_5706)) {
715 u32 val;
716
717 val = REG_RD(bp, BNX2_EMAC_STATUS);
718 if (val & BNX2_EMAC_STATUS_LINK)
719 bmsr |= BMSR_LSTATUS;
720 else
721 bmsr &= ~BMSR_LSTATUS;
722 }
723
724 if (bmsr & BMSR_LSTATUS) {
725 bp->link_up = 1;
726
727 if (bp->phy_flags & PHY_SERDES_FLAG) {
5b0c76ad
MC		 728 if (CHIP_NUM(bp) == CHIP_NUM_5706)
729 bnx2_5706s_linkup(bp);
730 else if (CHIP_NUM(bp) == CHIP_NUM_5708)
731 bnx2_5708s_linkup(bp);
b6016b76
MC		 732 }
733 else {
734 bnx2_copper_linkup(bp);
735 }
736 bnx2_resolve_flow_ctrl(bp);
737 }
738 else {
739 if ((bp->phy_flags & PHY_SERDES_FLAG) &&
740 (bp->autoneg & AUTONEG_SPEED)) {
741
742 u32 bmcr;
743
744 bnx2_read_phy(bp, MII_BMCR, &bmcr);
745 if (!(bmcr & BMCR_ANENABLE)) {
746 bnx2_write_phy(bp, MII_BMCR, bmcr |
747 BMCR_ANENABLE);
748 }
749 }
750 bp->phy_flags &= ~PHY_PARALLEL_DETECT_FLAG;
751 bp->link_up = 0;
752 }
753
754 if (bp->link_up != link_up) {
755 bnx2_report_link(bp);
756 }
757
758 bnx2_set_mac_link(bp);
759
760 return 0;
761}
762
763static int
764bnx2_reset_phy(struct bnx2 *bp)
765{
766 int i;
767 u32 reg;
768
769 bnx2_write_phy(bp, MII_BMCR, BMCR_RESET);
770
771#define PHY_RESET_MAX_WAIT 100
772 for (i = 0; i < PHY_RESET_MAX_WAIT; i++) {
773 udelay(10);
774
775 bnx2_read_phy(bp, MII_BMCR, &reg);
776 if (!(reg & BMCR_RESET)) {
777 udelay(20);
778 break;
779 }
780 }
781 if (i == PHY_RESET_MAX_WAIT) {
782 return -EBUSY;
783 }
784 return 0;
785}
786
787static u32
788bnx2_phy_get_pause_adv(struct bnx2 *bp)
789{
790 u32 adv = 0;
791
792 if ((bp->req_flow_ctrl & (FLOW_CTRL_RX | FLOW_CTRL_TX)) ==
793 (FLOW_CTRL_RX | FLOW_CTRL_TX)) {
794
795 if (bp->phy_flags & PHY_SERDES_FLAG) {
796 adv = ADVERTISE_1000XPAUSE;
797 }
798 else {
799 adv = ADVERTISE_PAUSE_CAP;
800 }
801 }
802 else if (bp->req_flow_ctrl & FLOW_CTRL_TX) {
803 if (bp->phy_flags & PHY_SERDES_FLAG) {
804 adv = ADVERTISE_1000XPSE_ASYM;
805 }
806 else {
807 adv = ADVERTISE_PAUSE_ASYM;
808 }
809 }
810 else if (bp->req_flow_ctrl & FLOW_CTRL_RX) {
811 if (bp->phy_flags & PHY_SERDES_FLAG) {
812 adv = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
813 }
814 else {
815 adv = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
816 }
817 }
818 return adv;
819}
820
821static int
822bnx2_setup_serdes_phy(struct bnx2 *bp)
823{
5b0c76ad 824 u32 adv, bmcr, up1;
b6016b76
MC		 825 u32 new_adv = 0;
826
827 if (!(bp->autoneg & AUTONEG_SPEED)) {
828 u32 new_bmcr;
5b0c76ad
MC		 829 int force_link_down = 0;
830
831 if (CHIP_NUM(bp) == CHIP_NUM_5708) {
832 bnx2_read_phy(bp, BCM5708S_UP1, &up1);
833 if (up1 & BCM5708S_UP1_2G5) {
834 up1 &= ~BCM5708S_UP1_2G5;
835 bnx2_write_phy(bp, BCM5708S_UP1, up1);
836 force_link_down = 1;
837 }
838 }
839
840 bnx2_read_phy(bp, MII_ADVERTISE, &adv);
841 adv &= ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF);
b6016b76
MC		 842
843 bnx2_read_phy(bp, MII_BMCR, &bmcr);
844 new_bmcr = bmcr & ~BMCR_ANENABLE;
845 new_bmcr |= BMCR_SPEED1000;
846 if (bp->req_duplex == DUPLEX_FULL) {
5b0c76ad 847 adv |= ADVERTISE_1000XFULL;
b6016b76
MC		 848 new_bmcr |= BMCR_FULLDPLX;
849 }
850 else {
5b0c76ad 851 adv |= ADVERTISE_1000XHALF;
b6016b76
MC		 852 new_bmcr &= ~BMCR_FULLDPLX;
853 }
5b0c76ad 854 if ((new_bmcr != bmcr) || (force_link_down)) {
b6016b76
MC		 855 /* Force a link down visible on the other side */
856 if (bp->link_up) {
5b0c76ad
MC		 857 bnx2_write_phy(bp, MII_ADVERTISE, adv &
858 ~(ADVERTISE_1000XFULL |
859 ADVERTISE_1000XHALF));
b6016b76
MC		 860 bnx2_write_phy(bp, MII_BMCR, bmcr |
861 BMCR_ANRESTART | BMCR_ANENABLE);
862
863 bp->link_up = 0;
864 netif_carrier_off(bp->dev);
5b0c76ad 865 bnx2_write_phy(bp, MII_BMCR, new_bmcr);
b6016b76 866 }
5b0c76ad 867 bnx2_write_phy(bp, MII_ADVERTISE, adv);
b6016b76
MC		 868 bnx2_write_phy(bp, MII_BMCR, new_bmcr);
869 }
870 return 0;
871 }
872
5b0c76ad
MC		 873 if (bp->phy_flags & PHY_2_5G_CAPABLE_FLAG) {
874 bnx2_read_phy(bp, BCM5708S_UP1, &up1);
875 up1 |= BCM5708S_UP1_2G5;
876 bnx2_write_phy(bp, BCM5708S_UP1, up1);
877 }
878
b6016b76
MC		 879 if (bp->advertising & ADVERTISED_1000baseT_Full)
880 new_adv |= ADVERTISE_1000XFULL;
881
882 new_adv |= bnx2_phy_get_pause_adv(bp);
883
884 bnx2_read_phy(bp, MII_ADVERTISE, &adv);
885 bnx2_read_phy(bp, MII_BMCR, &bmcr);
886
887 bp->serdes_an_pending = 0;
888 if ((adv != new_adv) || ((bmcr & BMCR_ANENABLE) == 0)) {
889 /* Force a link down visible on the other side */
890 if (bp->link_up) {
891 int i;
892
893 bnx2_write_phy(bp, MII_BMCR, BMCR_LOOPBACK);
894 for (i = 0; i < 110; i++) {
895 udelay(100);
896 }
897 }
898
899 bnx2_write_phy(bp, MII_ADVERTISE, new_adv);
900 bnx2_write_phy(bp, MII_BMCR, bmcr | BMCR_ANRESTART |
901 BMCR_ANENABLE);
cd339a0e
MC		 902 if (CHIP_NUM(bp) == CHIP_NUM_5706) {
903 /* Speed up link-up time when the link partner
904 * does not autonegotiate which is very common
905 * in blade servers. Some blade servers use
906 * IPMI for kerboard input and it's important
907 * to minimize link disruptions. Autoneg. involves
908 * exchanging base pages plus 3 next pages and
909 * normally completes in about 120 msec.
910 */
911 bp->current_interval = SERDES_AN_TIMEOUT;
912 bp->serdes_an_pending = 1;
913 mod_timer(&bp->timer, jiffies + bp->current_interval);
914 }
b6016b76
MC		 915 }
916
917 return 0;
918}
919
920#define ETHTOOL_ALL_FIBRE_SPEED \
921 (ADVERTISED_1000baseT_Full)
922
923#define ETHTOOL_ALL_COPPER_SPEED \
924 (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full | \
925 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full | \
926 ADVERTISED_1000baseT_Full)
927
928#define PHY_ALL_10_100_SPEED (ADVERTISE_10HALF | ADVERTISE_10FULL | \
929 ADVERTISE_100HALF | ADVERTISE_100FULL | ADVERTISE_CSMA)
930
931#define PHY_ALL_1000_SPEED (ADVERTISE_1000HALF | ADVERTISE_1000FULL)
932
933static int
934bnx2_setup_copper_phy(struct bnx2 *bp)
935{
936 u32 bmcr;
937 u32 new_bmcr;
938
939 bnx2_read_phy(bp, MII_BMCR, &bmcr);
940
941 if (bp->autoneg & AUTONEG_SPEED) {
942 u32 adv_reg, adv1000_reg;
943 u32 new_adv_reg = 0;
944 u32 new_adv1000_reg = 0;
945
946 bnx2_read_phy(bp, MII_ADVERTISE, &adv_reg);
947 adv_reg &= (PHY_ALL_10_100_SPEED | ADVERTISE_PAUSE_CAP |
948 ADVERTISE_PAUSE_ASYM);
949
950 bnx2_read_phy(bp, MII_CTRL1000, &adv1000_reg);
951 adv1000_reg &= PHY_ALL_1000_SPEED;
952
953 if (bp->advertising & ADVERTISED_10baseT_Half)
954 new_adv_reg |= ADVERTISE_10HALF;
955 if (bp->advertising & ADVERTISED_10baseT_Full)
956 new_adv_reg |= ADVERTISE_10FULL;
957 if (bp->advertising & ADVERTISED_100baseT_Half)
958 new_adv_reg |= ADVERTISE_100HALF;
959 if (bp->advertising & ADVERTISED_100baseT_Full)
960 new_adv_reg |= ADVERTISE_100FULL;
961 if (bp->advertising & ADVERTISED_1000baseT_Full)
962 new_adv1000_reg |= ADVERTISE_1000FULL;
963
964 new_adv_reg |= ADVERTISE_CSMA;
965
966 new_adv_reg |= bnx2_phy_get_pause_adv(bp);
967
968 if ((adv1000_reg != new_adv1000_reg) ||
969 (adv_reg != new_adv_reg) ||
970 ((bmcr & BMCR_ANENABLE) == 0)) {
971
972 bnx2_write_phy(bp, MII_ADVERTISE, new_adv_reg);
973 bnx2_write_phy(bp, MII_CTRL1000, new_adv1000_reg);
974 bnx2_write_phy(bp, MII_BMCR, BMCR_ANRESTART |
975 BMCR_ANENABLE);
976 }
977 else if (bp->link_up) {
978 /* Flow ctrl may have changed from auto to forced */
979 /* or vice-versa. */
980
981 bnx2_resolve_flow_ctrl(bp);
982 bnx2_set_mac_link(bp);
983 }
984 return 0;
985 }
986
987 new_bmcr = 0;
988 if (bp->req_line_speed == SPEED_100) {
989 new_bmcr |= BMCR_SPEED100;
990 }
991 if (bp->req_duplex == DUPLEX_FULL) {
992 new_bmcr |= BMCR_FULLDPLX;
993 }
994 if (new_bmcr != bmcr) {
995 u32 bmsr;
996 int i = 0;
997
998 bnx2_read_phy(bp, MII_BMSR, &bmsr);
999 bnx2_read_phy(bp, MII_BMSR, &bmsr);
1000
1001 if (bmsr & BMSR_LSTATUS) {
1002 /* Force link down */
1003 bnx2_write_phy(bp, MII_BMCR, BMCR_LOOPBACK);
1004 do {
1005 udelay(100);
1006 bnx2_read_phy(bp, MII_BMSR, &bmsr);
1007 bnx2_read_phy(bp, MII_BMSR, &bmsr);
1008 i++;
1009 } while ((bmsr & BMSR_LSTATUS) && (i < 620));
1010 }
1011
1012 bnx2_write_phy(bp, MII_BMCR, new_bmcr);
1013
1014 /* Normally, the new speed is setup after the link has
1015 * gone down and up again. In some cases, link will not go
1016 * down so we need to set up the new speed here.
1017 */
1018 if (bmsr & BMSR_LSTATUS) {
1019 bp->line_speed = bp->req_line_speed;
1020 bp->duplex = bp->req_duplex;
1021 bnx2_resolve_flow_ctrl(bp);
1022 bnx2_set_mac_link(bp);
1023 }
1024 }
1025 return 0;
1026}
1027
1028static int
1029bnx2_setup_phy(struct bnx2 *bp)
1030{
1031 if (bp->loopback == MAC_LOOPBACK)
1032 return 0;
1033
1034 if (bp->phy_flags & PHY_SERDES_FLAG) {
1035 return (bnx2_setup_serdes_phy(bp));
1036 }
1037 else {
1038 return (bnx2_setup_copper_phy(bp));
1039 }
1040}
1041
1042static int
5b0c76ad
MC		 1043bnx2_init_5708s_phy(struct bnx2 *bp)
1044{
1045 u32 val;
1046
1047 bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG3);
1048 bnx2_write_phy(bp, BCM5708S_DIG_3_0, BCM5708S_DIG_3_0_USE_IEEE);
1049 bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG);
1050
1051 bnx2_read_phy(bp, BCM5708S_1000X_CTL1, &val);
1052 val |= BCM5708S_1000X_CTL1_FIBER_MODE | BCM5708S_1000X_CTL1_AUTODET_EN;
1053 bnx2_write_phy(bp, BCM5708S_1000X_CTL1, val);
1054
1055 bnx2_read_phy(bp, BCM5708S_1000X_CTL2, &val);
1056 val |= BCM5708S_1000X_CTL2_PLLEL_DET_EN;
1057 bnx2_write_phy(bp, BCM5708S_1000X_CTL2, val);
1058
1059 if (bp->phy_flags & PHY_2_5G_CAPABLE_FLAG) {
1060 bnx2_read_phy(bp, BCM5708S_UP1, &val);
1061 val |= BCM5708S_UP1_2G5;
1062 bnx2_write_phy(bp, BCM5708S_UP1, val);
1063 }
1064
1065 if ((CHIP_ID(bp) == CHIP_ID_5708_A0) ||
1066 (CHIP_ID(bp) == CHIP_ID_5708_B0)) {
1067 /* increase tx signal amplitude */
1068 bnx2_write_phy(bp, BCM5708S_BLK_ADDR,
1069 BCM5708S_BLK_ADDR_TX_MISC);
1070 bnx2_read_phy(bp, BCM5708S_TX_ACTL1, &val);
1071 val &= ~BCM5708S_TX_ACTL1_DRIVER_VCM;
1072 bnx2_write_phy(bp, BCM5708S_TX_ACTL1, val);
1073 bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG);
1074 }
1075
1076 val = REG_RD_IND(bp, HOST_VIEW_SHMEM_BASE + BNX2_PORT_HW_CFG_CONFIG) &
1077 BNX2_PORT_HW_CFG_CFG_TXCTL3_MASK;
1078
1079 if (val) {
1080 u32 is_backplane;
1081
1082 is_backplane = REG_RD_IND(bp, HOST_VIEW_SHMEM_BASE +
1083 BNX2_SHARED_HW_CFG_CONFIG);
1084 if (is_backplane & BNX2_SHARED_HW_CFG_PHY_BACKPLANE) {
1085 bnx2_write_phy(bp, BCM5708S_BLK_ADDR,
1086 BCM5708S_BLK_ADDR_TX_MISC);
1087 bnx2_write_phy(bp, BCM5708S_TX_ACTL3, val);
1088 bnx2_write_phy(bp, BCM5708S_BLK_ADDR,
1089 BCM5708S_BLK_ADDR_DIG);
1090 }
1091 }
1092 return 0;
1093}
1094
1095static int
1096bnx2_init_5706s_phy(struct bnx2 *bp)
b6016b76
MC		 1097{
1098 bp->phy_flags &= ~PHY_PARALLEL_DETECT_FLAG;
1099
1100 if (CHIP_NUM(bp) == CHIP_NUM_5706) {
1101 REG_WR(bp, BNX2_MISC_UNUSED0, 0x300);
1102 }
1103
1104 if (bp->dev->mtu > 1500) {
1105 u32 val;
1106
1107 /* Set extended packet length bit */
1108 bnx2_write_phy(bp, 0x18, 0x7);
1109 bnx2_read_phy(bp, 0x18, &val);
1110 bnx2_write_phy(bp, 0x18, (val & 0xfff8) | 0x4000);
1111
1112 bnx2_write_phy(bp, 0x1c, 0x6c00);
1113 bnx2_read_phy(bp, 0x1c, &val);
1114 bnx2_write_phy(bp, 0x1c, (val & 0x3ff) | 0xec02);
1115 }
1116 else {
1117 u32 val;
1118
1119 bnx2_write_phy(bp, 0x18, 0x7);
1120 bnx2_read_phy(bp, 0x18, &val);
1121 bnx2_write_phy(bp, 0x18, val & ~0x4007);
1122
1123 bnx2_write_phy(bp, 0x1c, 0x6c00);
1124 bnx2_read_phy(bp, 0x1c, &val);
1125 bnx2_write_phy(bp, 0x1c, (val & 0x3fd) | 0xec00);
1126 }
1127
1128 return 0;
1129}
1130
1131static int
1132bnx2_init_copper_phy(struct bnx2 *bp)
1133{
5b0c76ad
MC		 1134 u32 val;
1135
b6016b76
MC		 1136 bp->phy_flags |= PHY_CRC_FIX_FLAG;
1137
1138 if (bp->phy_flags & PHY_CRC_FIX_FLAG) {
1139 bnx2_write_phy(bp, 0x18, 0x0c00);
1140 bnx2_write_phy(bp, 0x17, 0x000a);
1141 bnx2_write_phy(bp, 0x15, 0x310b);
1142 bnx2_write_phy(bp, 0x17, 0x201f);
1143 bnx2_write_phy(bp, 0x15, 0x9506);
1144 bnx2_write_phy(bp, 0x17, 0x401f);
1145 bnx2_write_phy(bp, 0x15, 0x14e2);
1146 bnx2_write_phy(bp, 0x18, 0x0400);
1147 }
1148
1149 if (bp->dev->mtu > 1500) {
b6016b76
MC		 1150 /* Set extended packet length bit */
1151 bnx2_write_phy(bp, 0x18, 0x7);
1152 bnx2_read_phy(bp, 0x18, &val);
1153 bnx2_write_phy(bp, 0x18, val | 0x4000);
1154
1155 bnx2_read_phy(bp, 0x10, &val);
1156 bnx2_write_phy(bp, 0x10, val | 0x1);
1157 }
1158 else {
b6016b76
MC		 1159 bnx2_write_phy(bp, 0x18, 0x7);
1160 bnx2_read_phy(bp, 0x18, &val);
1161 bnx2_write_phy(bp, 0x18, val & ~0x4007);
1162
1163 bnx2_read_phy(bp, 0x10, &val);
1164 bnx2_write_phy(bp, 0x10, val & ~0x1);
1165 }
1166
5b0c76ad
MC		 1167 /* ethernet@wirespeed */
1168 bnx2_write_phy(bp, 0x18, 0x7007);
1169 bnx2_read_phy(bp, 0x18, &val);
1170 bnx2_write_phy(bp, 0x18, val | (1 << 15) | (1 << 4));
b6016b76
MC		 1171 return 0;
1172}
1173
1174
1175static int
1176bnx2_init_phy(struct bnx2 *bp)
1177{
1178 u32 val;
1179 int rc = 0;
1180
1181 bp->phy_flags &= ~PHY_INT_MODE_MASK_FLAG;
1182 bp->phy_flags |= PHY_INT_MODE_LINK_READY_FLAG;
1183
1184 REG_WR(bp, BNX2_EMAC_ATTENTION_ENA, BNX2_EMAC_ATTENTION_ENA_LINK);
1185
1186 bnx2_reset_phy(bp);
1187
1188 bnx2_read_phy(bp, MII_PHYSID1, &val);
1189 bp->phy_id = val << 16;
1190 bnx2_read_phy(bp, MII_PHYSID2, &val);
1191 bp->phy_id |= val & 0xffff;
1192
1193 if (bp->phy_flags & PHY_SERDES_FLAG) {
5b0c76ad
MC		 1194 if (CHIP_NUM(bp) == CHIP_NUM_5706)
1195 rc = bnx2_init_5706s_phy(bp);
1196 else if (CHIP_NUM(bp) == CHIP_NUM_5708)
1197 rc = bnx2_init_5708s_phy(bp);
b6016b76
MC		 1198 }
1199 else {
1200 rc = bnx2_init_copper_phy(bp);
1201 }
1202
1203 bnx2_setup_phy(bp);
1204
1205 return rc;
1206}
1207
1208static int
1209bnx2_set_mac_loopback(struct bnx2 *bp)
1210{
1211 u32 mac_mode;
1212
1213 mac_mode = REG_RD(bp, BNX2_EMAC_MODE);
1214 mac_mode &= ~BNX2_EMAC_MODE_PORT;
1215 mac_mode |= BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK;
1216 REG_WR(bp, BNX2_EMAC_MODE, mac_mode);
1217 bp->link_up = 1;
1218 return 0;
1219}
1220
1221static int
1222bnx2_fw_sync(struct bnx2 *bp, u32 msg_data)
1223{
1224 int i;
1225 u32 val;
1226
1227 if (bp->fw_timed_out)
1228 return -EBUSY;
1229
1230 bp->fw_wr_seq++;
1231 msg_data |= bp->fw_wr_seq;
1232
1233 REG_WR_IND(bp, HOST_VIEW_SHMEM_BASE + BNX2_DRV_MB, msg_data);
1234
1235 /* wait for an acknowledgement. */
1236 for (i = 0; i < (FW_ACK_TIME_OUT_MS * 1000)/5; i++) {
1237 udelay(5);
1238
1239 val = REG_RD_IND(bp, HOST_VIEW_SHMEM_BASE + BNX2_FW_MB);
1240
1241 if ((val & BNX2_FW_MSG_ACK) == (msg_data & BNX2_DRV_MSG_SEQ))
1242 break;
1243 }
1244
1245 /* If we timed out, inform the firmware that this is the case. */
1246 if (((val & BNX2_FW_MSG_ACK) != (msg_data & BNX2_DRV_MSG_SEQ)) &&
1247 ((msg_data & BNX2_DRV_MSG_DATA) != BNX2_DRV_MSG_DATA_WAIT0)) {
1248
1249 msg_data &= ~BNX2_DRV_MSG_CODE;
1250 msg_data |= BNX2_DRV_MSG_CODE_FW_TIMEOUT;
1251
1252 REG_WR_IND(bp, HOST_VIEW_SHMEM_BASE + BNX2_DRV_MB, msg_data);
1253
1254 bp->fw_timed_out = 1;
1255
1256 return -EBUSY;
1257 }
1258
1259 return 0;
1260}
1261
1262static void
1263bnx2_init_context(struct bnx2 *bp)
1264{
1265 u32 vcid;
1266
1267 vcid = 96;
1268 while (vcid) {
1269 u32 vcid_addr, pcid_addr, offset;
1270
1271 vcid--;
1272
1273 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
1274 u32 new_vcid;
1275
1276 vcid_addr = GET_PCID_ADDR(vcid);
1277 if (vcid & 0x8) {
1278 new_vcid = 0x60 + (vcid & 0xf0) + (vcid & 0x7);
1279 }
1280 else {
1281 new_vcid = vcid;
1282 }
1283 pcid_addr = GET_PCID_ADDR(new_vcid);
1284 }
1285 else {
1286 vcid_addr = GET_CID_ADDR(vcid);
1287 pcid_addr = vcid_addr;
1288 }
1289
1290 REG_WR(bp, BNX2_CTX_VIRT_ADDR, 0x00);
1291 REG_WR(bp, BNX2_CTX_PAGE_TBL, pcid_addr);
1292
1293 /* Zero out the context. */
1294 for (offset = 0; offset < PHY_CTX_SIZE; offset += 4) {
1295 CTX_WR(bp, 0x00, offset, 0);
1296 }
1297
1298 REG_WR(bp, BNX2_CTX_VIRT_ADDR, vcid_addr);
1299 REG_WR(bp, BNX2_CTX_PAGE_TBL, pcid_addr);
1300 }
1301}
1302
1303static int
1304bnx2_alloc_bad_rbuf(struct bnx2 *bp)
1305{
1306 u16 *good_mbuf;
1307 u32 good_mbuf_cnt;
1308 u32 val;
1309
1310 good_mbuf = kmalloc(512 * sizeof(u16), GFP_KERNEL);
1311 if (good_mbuf == NULL) {
1312 printk(KERN_ERR PFX "Failed to allocate memory in "
1313 "bnx2_alloc_bad_rbuf\n");
1314 return -ENOMEM;
1315 }
1316
1317 REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS,
1318 BNX2_MISC_ENABLE_SET_BITS_RX_MBUF_ENABLE);
1319
1320 good_mbuf_cnt = 0;
1321
1322 /* Allocate a bunch of mbufs and save the good ones in an array. */
1323 val = REG_RD_IND(bp, BNX2_RBUF_STATUS1);
1324 while (val & BNX2_RBUF_STATUS1_FREE_COUNT) {
1325 REG_WR_IND(bp, BNX2_RBUF_COMMAND, BNX2_RBUF_COMMAND_ALLOC_REQ);
1326
1327 val = REG_RD_IND(bp, BNX2_RBUF_FW_BUF_ALLOC);
1328
1329 val &= BNX2_RBUF_FW_BUF_ALLOC_VALUE;
1330
1331 /* The addresses with Bit 9 set are bad memory blocks. */
1332 if (!(val & (1 << 9))) {
1333 good_mbuf[good_mbuf_cnt] = (u16) val;
1334 good_mbuf_cnt++;
1335 }
1336
1337 val = REG_RD_IND(bp, BNX2_RBUF_STATUS1);
1338 }
1339
1340 /* Free the good ones back to the mbuf pool thus discarding
1341 * all the bad ones. */
1342 while (good_mbuf_cnt) {
1343 good_mbuf_cnt--;
1344
1345 val = good_mbuf[good_mbuf_cnt];
1346 val = (val << 9) | val | 1;
1347
1348 REG_WR_IND(bp, BNX2_RBUF_FW_BUF_FREE, val);
1349 }
1350 kfree(good_mbuf);
1351 return 0;
1352}
1353
1354static void
1355bnx2_set_mac_addr(struct bnx2 *bp)
1356{
1357 u32 val;
1358 u8 *mac_addr = bp->dev->dev_addr;
1359
1360 val = (mac_addr[0] << 8) | mac_addr[1];
1361
1362 REG_WR(bp, BNX2_EMAC_MAC_MATCH0, val);
1363
1364 val = (mac_addr[2] << 24) | (mac_addr[3] << 16) |
1365 (mac_addr[4] << 8) | mac_addr[5];
1366
1367 REG_WR(bp, BNX2_EMAC_MAC_MATCH1, val);
1368}
1369
1370static inline int
1371bnx2_alloc_rx_skb(struct bnx2 *bp, u16 index)
1372{
1373 struct sk_buff *skb;
1374 struct sw_bd *rx_buf = &bp->rx_buf_ring[index];
1375 dma_addr_t mapping;
1376 struct rx_bd *rxbd = &bp->rx_desc_ring[index];
1377 unsigned long align;
1378
1379 skb = dev_alloc_skb(bp->rx_buf_size);
1380 if (skb == NULL) {
1381 return -ENOMEM;
1382 }
1383
1384 if (unlikely((align = (unsigned long) skb->data & 0x7))) {
1385 skb_reserve(skb, 8 - align);
1386 }
1387
1388 skb->dev = bp->dev;
1389 mapping = pci_map_single(bp->pdev, skb->data, bp->rx_buf_use_size,
1390 PCI_DMA_FROMDEVICE);
1391
1392 rx_buf->skb = skb;
1393 pci_unmap_addr_set(rx_buf, mapping, mapping);
1394
1395 rxbd->rx_bd_haddr_hi = (u64) mapping >> 32;
1396 rxbd->rx_bd_haddr_lo = (u64) mapping & 0xffffffff;
1397
1398 bp->rx_prod_bseq += bp->rx_buf_use_size;
1399
1400 return 0;
1401}
1402
1403static void
1404bnx2_phy_int(struct bnx2 *bp)
1405{
1406 u32 new_link_state, old_link_state;
1407
1408 new_link_state = bp->status_blk->status_attn_bits &
1409 STATUS_ATTN_BITS_LINK_STATE;
1410 old_link_state = bp->status_blk->status_attn_bits_ack &
1411 STATUS_ATTN_BITS_LINK_STATE;
1412 if (new_link_state != old_link_state) {
1413 if (new_link_state) {
1414 REG_WR(bp, BNX2_PCICFG_STATUS_BIT_SET_CMD,
1415 STATUS_ATTN_BITS_LINK_STATE);
1416 }
1417 else {
1418 REG_WR(bp, BNX2_PCICFG_STATUS_BIT_CLEAR_CMD,
1419 STATUS_ATTN_BITS_LINK_STATE);
1420 }
1421 bnx2_set_link(bp);
1422 }
1423}
1424
1425static void
1426bnx2_tx_int(struct bnx2 *bp)
1427{
1428 u16 hw_cons, sw_cons, sw_ring_cons;
1429 int tx_free_bd = 0;
1430
1431 hw_cons = bp->status_blk->status_tx_quick_consumer_index0;
1432 if ((hw_cons & MAX_TX_DESC_CNT) == MAX_TX_DESC_CNT) {
1433 hw_cons++;
1434 }
1435 sw_cons = bp->tx_cons;
1436
1437 while (sw_cons != hw_cons) {
1438 struct sw_bd *tx_buf;
1439 struct sk_buff *skb;
1440 int i, last;
1441
1442 sw_ring_cons = TX_RING_IDX(sw_cons);
1443
1444 tx_buf = &bp->tx_buf_ring[sw_ring_cons];
1445 skb = tx_buf->skb;
1446#ifdef BCM_TSO
1447 /* partial BD completions possible with TSO packets */
1448 if (skb_shinfo(skb)->tso_size) {
1449 u16 last_idx, last_ring_idx;
1450
1451 last_idx = sw_cons +
1452 skb_shinfo(skb)->nr_frags + 1;
1453 last_ring_idx = sw_ring_cons +
1454 skb_shinfo(skb)->nr_frags + 1;
1455 if (unlikely(last_ring_idx >= MAX_TX_DESC_CNT)) {
1456 last_idx++;
1457 }
1458 if (((s16) ((s16) last_idx - (s16) hw_cons)) > 0) {
1459 break;
1460 }
1461 }
1462#endif
1463 pci_unmap_single(bp->pdev, pci_unmap_addr(tx_buf, mapping),
1464 skb_headlen(skb), PCI_DMA_TODEVICE);
1465
1466 tx_buf->skb = NULL;
1467 last = skb_shinfo(skb)->nr_frags;
1468
1469 for (i = 0; i < last; i++) {
1470 sw_cons = NEXT_TX_BD(sw_cons);
1471
1472 pci_unmap_page(bp->pdev,
1473 pci_unmap_addr(
1474 &bp->tx_buf_ring[TX_RING_IDX(sw_cons)],
1475 mapping),
1476 skb_shinfo(skb)->frags[i].size,
1477 PCI_DMA_TODEVICE);
1478 }
1479
1480 sw_cons = NEXT_TX_BD(sw_cons);
1481
1482 tx_free_bd += last + 1;
1483
1484 dev_kfree_skb_irq(skb);
1485
1486 hw_cons = bp->status_blk->status_tx_quick_consumer_index0;
1487 if ((hw_cons & MAX_TX_DESC_CNT) == MAX_TX_DESC_CNT) {
1488 hw_cons++;
1489 }
1490 }
1491
e89bbf10 1492 bp->tx_cons = sw_cons;
b6016b76
MC		 1493
1494 if (unlikely(netif_queue_stopped(bp->dev))) {
c770a65c 1495 spin_lock(&bp->tx_lock);
b6016b76 1496 if ((netif_queue_stopped(bp->dev)) &&
e89bbf10 1497 (bnx2_tx_avail(bp) > MAX_SKB_FRAGS)) {
b6016b76
MC		 1498
1499 netif_wake_queue(bp->dev);
1500 }
c770a65c 1501 spin_unlock(&bp->tx_lock);
b6016b76 1502 }
b6016b76
MC		 1503}
1504
1505static inline void
1506bnx2_reuse_rx_skb(struct bnx2 *bp, struct sk_buff *skb,
1507 u16 cons, u16 prod)
1508{
1509 struct sw_bd *cons_rx_buf = &bp->rx_buf_ring[cons];
1510 struct sw_bd *prod_rx_buf = &bp->rx_buf_ring[prod];
1511 struct rx_bd *cons_bd = &bp->rx_desc_ring[cons];
1512 struct rx_bd *prod_bd = &bp->rx_desc_ring[prod];
1513
1514 pci_dma_sync_single_for_device(bp->pdev,
1515 pci_unmap_addr(cons_rx_buf, mapping),
1516 bp->rx_offset + RX_COPY_THRESH, PCI_DMA_FROMDEVICE);
1517
1518 prod_rx_buf->skb = cons_rx_buf->skb;
1519 pci_unmap_addr_set(prod_rx_buf, mapping,
1520 pci_unmap_addr(cons_rx_buf, mapping));
1521
1522 memcpy(prod_bd, cons_bd, 8);
1523
1524 bp->rx_prod_bseq += bp->rx_buf_use_size;
1525
1526}
1527
1528static int
1529bnx2_rx_int(struct bnx2 *bp, int budget)
1530{
1531 u16 hw_cons, sw_cons, sw_ring_cons, sw_prod, sw_ring_prod;
1532 struct l2_fhdr *rx_hdr;
1533 int rx_pkt = 0;
1534
1535 hw_cons = bp->status_blk->status_rx_quick_consumer_index0;
1536 if ((hw_cons & MAX_RX_DESC_CNT) == MAX_RX_DESC_CNT) {
1537 hw_cons++;
1538 }
1539 sw_cons = bp->rx_cons;
1540 sw_prod = bp->rx_prod;
1541
1542 /* Memory barrier necessary as speculative reads of the rx
1543 * buffer can be ahead of the index in the status block
1544 */
1545 rmb();
1546 while (sw_cons != hw_cons) {
1547 unsigned int len;
1548 u16 status;
1549 struct sw_bd *rx_buf;
1550 struct sk_buff *skb;
1551
1552 sw_ring_cons = RX_RING_IDX(sw_cons);
1553 sw_ring_prod = RX_RING_IDX(sw_prod);
1554
1555 rx_buf = &bp->rx_buf_ring[sw_ring_cons];
1556 skb = rx_buf->skb;
1557 pci_dma_sync_single_for_cpu(bp->pdev,
1558 pci_unmap_addr(rx_buf, mapping),
1559 bp->rx_offset + RX_COPY_THRESH, PCI_DMA_FROMDEVICE);
1560
1561 rx_hdr = (struct l2_fhdr *) skb->data;
1562 len = rx_hdr->l2_fhdr_pkt_len - 4;
1563
1564 if (rx_hdr->l2_fhdr_errors &
1565 (L2_FHDR_ERRORS_BAD_CRC |
1566 L2_FHDR_ERRORS_PHY_DECODE |
1567 L2_FHDR_ERRORS_ALIGNMENT |
1568 L2_FHDR_ERRORS_TOO_SHORT |
1569 L2_FHDR_ERRORS_GIANT_FRAME)) {
1570
1571 goto reuse_rx;
1572 }
1573
1574 /* Since we don't have a jumbo ring, copy small packets
1575 * if mtu > 1500
1576 */
1577 if ((bp->dev->mtu > 1500) && (len <= RX_COPY_THRESH)) {
1578 struct sk_buff *new_skb;
1579
1580 new_skb = dev_alloc_skb(len + 2);
1581 if (new_skb == NULL)
1582 goto reuse_rx;
1583
1584 /* aligned copy */
1585 memcpy(new_skb->data,
1586 skb->data + bp->rx_offset - 2,
1587 len + 2);
1588
1589 skb_reserve(new_skb, 2);
1590 skb_put(new_skb, len);
1591 new_skb->dev = bp->dev;
1592
1593 bnx2_reuse_rx_skb(bp, skb,
1594 sw_ring_cons, sw_ring_prod);
1595
1596 skb = new_skb;
1597 }
1598 else if (bnx2_alloc_rx_skb(bp, sw_ring_prod) == 0) {
1599 pci_unmap_single(bp->pdev,
1600 pci_unmap_addr(rx_buf, mapping),
1601 bp->rx_buf_use_size, PCI_DMA_FROMDEVICE);
1602
1603 skb_reserve(skb, bp->rx_offset);
1604 skb_put(skb, len);
1605 }
1606 else {
1607reuse_rx:
1608 bnx2_reuse_rx_skb(bp, skb,
1609 sw_ring_cons, sw_ring_prod);
1610 goto next_rx;
1611 }
1612
1613 skb->protocol = eth_type_trans(skb, bp->dev);
1614
1615 if ((len > (bp->dev->mtu + ETH_HLEN)) &&
1616 (htons(skb->protocol) != 0x8100)) {
1617
1618 dev_kfree_skb_irq(skb);
1619 goto next_rx;
1620
1621 }
1622
1623 status = rx_hdr->l2_fhdr_status;
1624 skb->ip_summed = CHECKSUM_NONE;
1625 if (bp->rx_csum &&
1626 (status & (L2_FHDR_STATUS_TCP_SEGMENT |
1627 L2_FHDR_STATUS_UDP_DATAGRAM))) {
1628
1629 u16 cksum = rx_hdr->l2_fhdr_tcp_udp_xsum;
1630
1631 if (cksum == 0xffff)
1632 skb->ip_summed = CHECKSUM_UNNECESSARY;
1633 }
1634
1635#ifdef BCM_VLAN
1636 if ((status & L2_FHDR_STATUS_L2_VLAN_TAG) && (bp->vlgrp != 0)) {
1637 vlan_hwaccel_receive_skb(skb, bp->vlgrp,
1638 rx_hdr->l2_fhdr_vlan_tag);
1639 }
1640 else
1641#endif
1642 netif_receive_skb(skb);
1643
1644 bp->dev->last_rx = jiffies;
1645 rx_pkt++;
1646
1647next_rx:
1648 rx_buf->skb = NULL;
1649
1650 sw_cons = NEXT_RX_BD(sw_cons);
1651 sw_prod = NEXT_RX_BD(sw_prod);
1652
1653 if ((rx_pkt == budget))
1654 break;
1655 }
1656 bp->rx_cons = sw_cons;
1657 bp->rx_prod = sw_prod;
1658
1659 REG_WR16(bp, MB_RX_CID_ADDR + BNX2_L2CTX_HOST_BDIDX, sw_prod);
1660
1661 REG_WR(bp, MB_RX_CID_ADDR + BNX2_L2CTX_HOST_BSEQ, bp->rx_prod_bseq);
1662
1663 mmiowb();
1664
1665 return rx_pkt;
1666
1667}
1668
1669/* MSI ISR - The only difference between this and the INTx ISR
1670 * is that the MSI interrupt is always serviced.
1671 */
1672static irqreturn_t
1673bnx2_msi(int irq, void *dev_instance, struct pt_regs *regs)
1674{
1675 struct net_device *dev = dev_instance;
1676 struct bnx2 *bp = dev->priv;
1677
c921e4c4 1678 prefetch(bp->status_blk);
b6016b76
MC		 1679 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
1680 BNX2_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM |
1681 BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
1682
1683 /* Return here if interrupt is disabled. */
73eef4cd
MC		 1684 if (unlikely(atomic_read(&bp->intr_sem) != 0))
1685 return IRQ_HANDLED;
b6016b76 1686
73eef4cd 1687 netif_rx_schedule(dev);
b6016b76 1688
73eef4cd 1689 return IRQ_HANDLED;
b6016b76
MC		 1690}
1691
1692static irqreturn_t
1693bnx2_interrupt(int irq, void *dev_instance, struct pt_regs *regs)
1694{
1695 struct net_device *dev = dev_instance;
1696 struct bnx2 *bp = dev->priv;
1697
1698 /* When using INTx, it is possible for the interrupt to arrive
1699 * at the CPU before the status block posted prior to the
1700 * interrupt. Reading a register will flush the status block.
1701 * When using MSI, the MSI message will always complete after
1702 * the status block write.
1703 */
c921e4c4 1704 if ((bp->status_blk->status_idx == bp->last_status_idx) &&
b6016b76
MC		 1705 (REG_RD(bp, BNX2_PCICFG_MISC_STATUS) &
1706 BNX2_PCICFG_MISC_STATUS_INTA_VALUE))
73eef4cd 1707 return IRQ_NONE;
b6016b76
MC		 1708
1709 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
1710 BNX2_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM |
1711 BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
1712
1713 /* Return here if interrupt is shared and is disabled. */
73eef4cd
MC		 1714 if (unlikely(atomic_read(&bp->intr_sem) != 0))
1715 return IRQ_HANDLED;
b6016b76 1716
73eef4cd 1717 netif_rx_schedule(dev);
b6016b76 1718
73eef4cd 1719 return IRQ_HANDLED;
b6016b76
MC		 1720}
1721
1722static int
1723bnx2_poll(struct net_device *dev, int *budget)
1724{
1725 struct bnx2 *bp = dev->priv;
1726 int rx_done = 1;
1727
1728 bp->last_status_idx = bp->status_blk->status_idx;
1729
1730 rmb();
1731 if ((bp->status_blk->status_attn_bits &
1732 STATUS_ATTN_BITS_LINK_STATE) !=
1733 (bp->status_blk->status_attn_bits_ack &
1734 STATUS_ATTN_BITS_LINK_STATE)) {
1735
c770a65c 1736 spin_lock(&bp->phy_lock);
b6016b76 1737 bnx2_phy_int(bp);
c770a65c 1738 spin_unlock(&bp->phy_lock);
b6016b76
MC		 1739 }
1740
1741 if (bp->status_blk->status_tx_quick_consumer_index0 != bp->tx_cons) {
1742 bnx2_tx_int(bp);
1743 }
1744
1745 if (bp->status_blk->status_rx_quick_consumer_index0 != bp->rx_cons) {
1746 int orig_budget = *budget;
1747 int work_done;
1748
1749 if (orig_budget > dev->quota)
1750 orig_budget = dev->quota;
1751
1752 work_done = bnx2_rx_int(bp, orig_budget);
1753 *budget -= work_done;
1754 dev->quota -= work_done;
1755
1756 if (work_done >= orig_budget) {
1757 rx_done = 0;
1758 }
1759 }
1760
1761 if (rx_done) {
1762 netif_rx_complete(dev);
1763 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
1764 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
1765 bp->last_status_idx);
1766 return 0;
1767 }
1768
1769 return 1;
1770}
1771
1772/* Called with rtnl_lock from vlan functions and also dev->xmit_lock
1773 * from set_multicast.
1774 */
1775static void
1776bnx2_set_rx_mode(struct net_device *dev)
1777{
1778 struct bnx2 *bp = dev->priv;
1779 u32 rx_mode, sort_mode;
1780 int i;
b6016b76 1781
c770a65c 1782 spin_lock_bh(&bp->phy_lock);
b6016b76
MC		 1783
1784 rx_mode = bp->rx_mode & ~(BNX2_EMAC_RX_MODE_PROMISCUOUS |
1785 BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG);
1786 sort_mode = 1 | BNX2_RPM_SORT_USER0_BC_EN;
1787#ifdef BCM_VLAN
1788 if (!bp->vlgrp) {
1789 rx_mode |= BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG;
1790 }
1791#else
1792 rx_mode |= BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG;
1793#endif
1794 if (dev->flags & IFF_PROMISC) {
1795 /* Promiscuous mode. */
1796 rx_mode |= BNX2_EMAC_RX_MODE_PROMISCUOUS;
1797 sort_mode |= BNX2_RPM_SORT_USER0_PROM_EN;
1798 }
1799 else if (dev->flags & IFF_ALLMULTI) {
1800 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
1801 REG_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),
1802 0xffffffff);
1803 }
1804 sort_mode |= BNX2_RPM_SORT_USER0_MC_EN;
1805 }
1806 else {
1807 /* Accept one or more multicast(s). */
1808 struct dev_mc_list *mclist;
1809 u32 mc_filter[NUM_MC_HASH_REGISTERS];
1810 u32 regidx;
1811 u32 bit;
1812 u32 crc;
1813
1814 memset(mc_filter, 0, 4 * NUM_MC_HASH_REGISTERS);
1815
1816 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
1817 i++, mclist = mclist->next) {
1818
1819 crc = ether_crc_le(ETH_ALEN, mclist->dmi_addr);
1820 bit = crc & 0xff;
1821 regidx = (bit & 0xe0) >> 5;
1822 bit &= 0x1f;
1823 mc_filter[regidx] |= (1 << bit);
1824 }
1825
1826 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
1827 REG_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),
1828 mc_filter[i]);
1829 }
1830
1831 sort_mode |= BNX2_RPM_SORT_USER0_MC_HSH_EN;
1832 }
1833
1834 if (rx_mode != bp->rx_mode) {
1835 bp->rx_mode = rx_mode;
1836 REG_WR(bp, BNX2_EMAC_RX_MODE, rx_mode);
1837 }
1838
1839 REG_WR(bp, BNX2_RPM_SORT_USER0, 0x0);
1840 REG_WR(bp, BNX2_RPM_SORT_USER0, sort_mode);
1841 REG_WR(bp, BNX2_RPM_SORT_USER0, sort_mode | BNX2_RPM_SORT_USER0_ENA);
1842
c770a65c 1843 spin_unlock_bh(&bp->phy_lock);
b6016b76
MC		 1844}
1845
1846static void
1847load_rv2p_fw(struct bnx2 *bp, u32 *rv2p_code, u32 rv2p_code_len,
1848 u32 rv2p_proc)
1849{
1850 int i;
1851 u32 val;
1852
1853
1854 for (i = 0; i < rv2p_code_len; i += 8) {
1855 REG_WR(bp, BNX2_RV2P_INSTR_HIGH, *rv2p_code);
1856 rv2p_code++;
1857 REG_WR(bp, BNX2_RV2P_INSTR_LOW, *rv2p_code);
1858 rv2p_code++;
1859
1860 if (rv2p_proc == RV2P_PROC1) {
1861 val = (i / 8) | BNX2_RV2P_PROC1_ADDR_CMD_RDWR;
1862 REG_WR(bp, BNX2_RV2P_PROC1_ADDR_CMD, val);
1863 }
1864 else {
1865 val = (i / 8) | BNX2_RV2P_PROC2_ADDR_CMD_RDWR;
1866 REG_WR(bp, BNX2_RV2P_PROC2_ADDR_CMD, val);
1867 }
1868 }
1869
1870 /* Reset the processor, un-stall is done later. */
1871 if (rv2p_proc == RV2P_PROC1) {
1872 REG_WR(bp, BNX2_RV2P_COMMAND, BNX2_RV2P_COMMAND_PROC1_RESET);
1873 }
1874 else {
1875 REG_WR(bp, BNX2_RV2P_COMMAND, BNX2_RV2P_COMMAND_PROC2_RESET);
1876 }
1877}
1878
1879static void
1880load_cpu_fw(struct bnx2 *bp, struct cpu_reg *cpu_reg, struct fw_info *fw)
1881{
1882 u32 offset;
1883 u32 val;
1884
1885 /* Halt the CPU. */
1886 val = REG_RD_IND(bp, cpu_reg->mode);
1887 val |= cpu_reg->mode_value_halt;
1888 REG_WR_IND(bp, cpu_reg->mode, val);
1889 REG_WR_IND(bp, cpu_reg->state, cpu_reg->state_value_clear);
1890
1891 /* Load the Text area. */
1892 offset = cpu_reg->spad_base + (fw->text_addr - cpu_reg->mips_view_base);
1893 if (fw->text) {
1894 int j;
1895
1896 for (j = 0; j < (fw->text_len / 4); j++, offset += 4) {
1897 REG_WR_IND(bp, offset, fw->text[j]);
1898 }
1899 }
1900
1901 /* Load the Data area. */
1902 offset = cpu_reg->spad_base + (fw->data_addr - cpu_reg->mips_view_base);
1903 if (fw->data) {
1904 int j;
1905
1906 for (j = 0; j < (fw->data_len / 4); j++, offset += 4) {
1907 REG_WR_IND(bp, offset, fw->data[j]);
1908 }
1909 }
1910
1911 /* Load the SBSS area. */
1912 offset = cpu_reg->spad_base + (fw->sbss_addr - cpu_reg->mips_view_base);
1913 if (fw->sbss) {
1914 int j;
1915
1916 for (j = 0; j < (fw->sbss_len / 4); j++, offset += 4) {
1917 REG_WR_IND(bp, offset, fw->sbss[j]);
1918 }
1919 }
1920
1921 /* Load the BSS area. */
1922 offset = cpu_reg->spad_base + (fw->bss_addr - cpu_reg->mips_view_base);
1923 if (fw->bss) {
1924 int j;
1925
1926 for (j = 0; j < (fw->bss_len/4); j++, offset += 4) {
1927 REG_WR_IND(bp, offset, fw->bss[j]);
1928 }
1929 }
1930
1931 /* Load the Read-Only area. */
1932 offset = cpu_reg->spad_base +
1933 (fw->rodata_addr - cpu_reg->mips_view_base);
1934 if (fw->rodata) {
1935 int j;
1936
1937 for (j = 0; j < (fw->rodata_len / 4); j++, offset += 4) {
1938 REG_WR_IND(bp, offset, fw->rodata[j]);
1939 }
1940 }
1941
1942 /* Clear the pre-fetch instruction. */
1943 REG_WR_IND(bp, cpu_reg->inst, 0);
1944 REG_WR_IND(bp, cpu_reg->pc, fw->start_addr);
1945
1946 /* Start the CPU. */
1947 val = REG_RD_IND(bp, cpu_reg->mode);
1948 val &= ~cpu_reg->mode_value_halt;
1949 REG_WR_IND(bp, cpu_reg->state, cpu_reg->state_value_clear);
1950 REG_WR_IND(bp, cpu_reg->mode, val);
1951}
1952
1953static void
1954bnx2_init_cpus(struct bnx2 *bp)
1955{
1956 struct cpu_reg cpu_reg;
1957 struct fw_info fw;
1958
1959 /* Initialize the RV2P processor. */
1960 load_rv2p_fw(bp, bnx2_rv2p_proc1, sizeof(bnx2_rv2p_proc1), RV2P_PROC1);
1961 load_rv2p_fw(bp, bnx2_rv2p_proc2, sizeof(bnx2_rv2p_proc2), RV2P_PROC2);
1962
1963 /* Initialize the RX Processor. */
1964 cpu_reg.mode = BNX2_RXP_CPU_MODE;
1965 cpu_reg.mode_value_halt = BNX2_RXP_CPU_MODE_SOFT_HALT;
1966 cpu_reg.mode_value_sstep = BNX2_RXP_CPU_MODE_STEP_ENA;
1967 cpu_reg.state = BNX2_RXP_CPU_STATE;
1968 cpu_reg.state_value_clear = 0xffffff;
1969 cpu_reg.gpr0 = BNX2_RXP_CPU_REG_FILE;
1970 cpu_reg.evmask = BNX2_RXP_CPU_EVENT_MASK;
1971 cpu_reg.pc = BNX2_RXP_CPU_PROGRAM_COUNTER;
1972 cpu_reg.inst = BNX2_RXP_CPU_INSTRUCTION;
1973 cpu_reg.bp = BNX2_RXP_CPU_HW_BREAKPOINT;
1974 cpu_reg.spad_base = BNX2_RXP_SCRATCH;
1975 cpu_reg.mips_view_base = 0x8000000;
1976
1977 fw.ver_major = bnx2_RXP_b06FwReleaseMajor;
1978 fw.ver_minor = bnx2_RXP_b06FwReleaseMinor;
1979 fw.ver_fix = bnx2_RXP_b06FwReleaseFix;
1980 fw.start_addr = bnx2_RXP_b06FwStartAddr;
1981
1982 fw.text_addr = bnx2_RXP_b06FwTextAddr;
1983 fw.text_len = bnx2_RXP_b06FwTextLen;
1984 fw.text_index = 0;
1985 fw.text = bnx2_RXP_b06FwText;
1986
1987 fw.data_addr = bnx2_RXP_b06FwDataAddr;
1988 fw.data_len = bnx2_RXP_b06FwDataLen;
1989 fw.data_index = 0;
1990 fw.data = bnx2_RXP_b06FwData;
1991
1992 fw.sbss_addr = bnx2_RXP_b06FwSbssAddr;
1993 fw.sbss_len = bnx2_RXP_b06FwSbssLen;
1994 fw.sbss_index = 0;
1995 fw.sbss = bnx2_RXP_b06FwSbss;
1996
1997 fw.bss_addr = bnx2_RXP_b06FwBssAddr;
1998 fw.bss_len = bnx2_RXP_b06FwBssLen;
1999 fw.bss_index = 0;
2000 fw.bss = bnx2_RXP_b06FwBss;
2001
2002 fw.rodata_addr = bnx2_RXP_b06FwRodataAddr;
2003 fw.rodata_len = bnx2_RXP_b06FwRodataLen;
2004 fw.rodata_index = 0;
2005 fw.rodata = bnx2_RXP_b06FwRodata;
2006
2007 load_cpu_fw(bp, &cpu_reg, &fw);
2008
2009 /* Initialize the TX Processor. */
2010 cpu_reg.mode = BNX2_TXP_CPU_MODE;
2011 cpu_reg.mode_value_halt = BNX2_TXP_CPU_MODE_SOFT_HALT;
2012 cpu_reg.mode_value_sstep = BNX2_TXP_CPU_MODE_STEP_ENA;
2013 cpu_reg.state = BNX2_TXP_CPU_STATE;
2014 cpu_reg.state_value_clear = 0xffffff;
2015 cpu_reg.gpr0 = BNX2_TXP_CPU_REG_FILE;
2016 cpu_reg.evmask = BNX2_TXP_CPU_EVENT_MASK;
2017 cpu_reg.pc = BNX2_TXP_CPU_PROGRAM_COUNTER;
2018 cpu_reg.inst = BNX2_TXP_CPU_INSTRUCTION;
2019 cpu_reg.bp = BNX2_TXP_CPU_HW_BREAKPOINT;
2020 cpu_reg.spad_base = BNX2_TXP_SCRATCH;
2021 cpu_reg.mips_view_base = 0x8000000;
2022
2023 fw.ver_major = bnx2_TXP_b06FwReleaseMajor;
2024 fw.ver_minor = bnx2_TXP_b06FwReleaseMinor;
2025 fw.ver_fix = bnx2_TXP_b06FwReleaseFix;
2026 fw.start_addr = bnx2_TXP_b06FwStartAddr;
2027
2028 fw.text_addr = bnx2_TXP_b06FwTextAddr;
2029 fw.text_len = bnx2_TXP_b06FwTextLen;
2030 fw.text_index = 0;
2031 fw.text = bnx2_TXP_b06FwText;
2032
2033 fw.data_addr = bnx2_TXP_b06FwDataAddr;
2034 fw.data_len = bnx2_TXP_b06FwDataLen;
2035 fw.data_index = 0;
2036 fw.data = bnx2_TXP_b06FwData;
2037
2038 fw.sbss_addr = bnx2_TXP_b06FwSbssAddr;
2039 fw.sbss_len = bnx2_TXP_b06FwSbssLen;
2040 fw.sbss_index = 0;
2041 fw.sbss = bnx2_TXP_b06FwSbss;
2042
2043 fw.bss_addr = bnx2_TXP_b06FwBssAddr;
2044 fw.bss_len = bnx2_TXP_b06FwBssLen;
2045 fw.bss_index = 0;
2046 fw.bss = bnx2_TXP_b06FwBss;
2047
2048 fw.rodata_addr = bnx2_TXP_b06FwRodataAddr;
2049 fw.rodata_len = bnx2_TXP_b06FwRodataLen;
2050 fw.rodata_index = 0;
2051 fw.rodata = bnx2_TXP_b06FwRodata;
2052
2053 load_cpu_fw(bp, &cpu_reg, &fw);
2054
2055 /* Initialize the TX Patch-up Processor. */
2056 cpu_reg.mode = BNX2_TPAT_CPU_MODE;
2057 cpu_reg.mode_value_halt = BNX2_TPAT_CPU_MODE_SOFT_HALT;
2058 cpu_reg.mode_value_sstep = BNX2_TPAT_CPU_MODE_STEP_ENA;
2059 cpu_reg.state = BNX2_TPAT_CPU_STATE;
2060 cpu_reg.state_value_clear = 0xffffff;
2061 cpu_reg.gpr0 = BNX2_TPAT_CPU_REG_FILE;
2062 cpu_reg.evmask = BNX2_TPAT_CPU_EVENT_MASK;
2063 cpu_reg.pc = BNX2_TPAT_CPU_PROGRAM_COUNTER;
2064 cpu_reg.inst = BNX2_TPAT_CPU_INSTRUCTION;
2065 cpu_reg.bp = BNX2_TPAT_CPU_HW_BREAKPOINT;
2066 cpu_reg.spad_base = BNX2_TPAT_SCRATCH;
2067 cpu_reg.mips_view_base = 0x8000000;
2068
2069 fw.ver_major = bnx2_TPAT_b06FwReleaseMajor;
2070 fw.ver_minor = bnx2_TPAT_b06FwReleaseMinor;
2071 fw.ver_fix = bnx2_TPAT_b06FwReleaseFix;
2072 fw.start_addr = bnx2_TPAT_b06FwStartAddr;
2073
2074 fw.text_addr = bnx2_TPAT_b06FwTextAddr;
2075 fw.text_len = bnx2_TPAT_b06FwTextLen;
2076 fw.text_index = 0;
2077 fw.text = bnx2_TPAT_b06FwText;
2078
2079 fw.data_addr = bnx2_TPAT_b06FwDataAddr;
2080 fw.data_len = bnx2_TPAT_b06FwDataLen;
2081 fw.data_index = 0;
2082 fw.data = bnx2_TPAT_b06FwData;
2083
2084 fw.sbss_addr = bnx2_TPAT_b06FwSbssAddr;
2085 fw.sbss_len = bnx2_TPAT_b06FwSbssLen;
2086 fw.sbss_index = 0;
2087 fw.sbss = bnx2_TPAT_b06FwSbss;
2088
2089 fw.bss_addr = bnx2_TPAT_b06FwBssAddr;
2090 fw.bss_len = bnx2_TPAT_b06FwBssLen;
2091 fw.bss_index = 0;
2092 fw.bss = bnx2_TPAT_b06FwBss;
2093
2094 fw.rodata_addr = bnx2_TPAT_b06FwRodataAddr;
2095 fw.rodata_len = bnx2_TPAT_b06FwRodataLen;
2096 fw.rodata_index = 0;
2097 fw.rodata = bnx2_TPAT_b06FwRodata;
2098
2099 load_cpu_fw(bp, &cpu_reg, &fw);
2100
2101 /* Initialize the Completion Processor. */
2102 cpu_reg.mode = BNX2_COM_CPU_MODE;
2103 cpu_reg.mode_value_halt = BNX2_COM_CPU_MODE_SOFT_HALT;
2104 cpu_reg.mode_value_sstep = BNX2_COM_CPU_MODE_STEP_ENA;
2105 cpu_reg.state = BNX2_COM_CPU_STATE;
2106 cpu_reg.state_value_clear = 0xffffff;
2107 cpu_reg.gpr0 = BNX2_COM_CPU_REG_FILE;
2108 cpu_reg.evmask = BNX2_COM_CPU_EVENT_MASK;
2109 cpu_reg.pc = BNX2_COM_CPU_PROGRAM_COUNTER;
2110 cpu_reg.inst = BNX2_COM_CPU_INSTRUCTION;
2111 cpu_reg.bp = BNX2_COM_CPU_HW_BREAKPOINT;
2112 cpu_reg.spad_base = BNX2_COM_SCRATCH;
2113 cpu_reg.mips_view_base = 0x8000000;
2114
2115 fw.ver_major = bnx2_COM_b06FwReleaseMajor;
2116 fw.ver_minor = bnx2_COM_b06FwReleaseMinor;
2117 fw.ver_fix = bnx2_COM_b06FwReleaseFix;
2118 fw.start_addr = bnx2_COM_b06FwStartAddr;
2119
2120 fw.text_addr = bnx2_COM_b06FwTextAddr;
2121 fw.text_len = bnx2_COM_b06FwTextLen;
2122 fw.text_index = 0;
2123 fw.text = bnx2_COM_b06FwText;
2124
2125 fw.data_addr = bnx2_COM_b06FwDataAddr;
2126 fw.data_len = bnx2_COM_b06FwDataLen;
2127 fw.data_index = 0;
2128 fw.data = bnx2_COM_b06FwData;
2129
2130 fw.sbss_addr = bnx2_COM_b06FwSbssAddr;
2131 fw.sbss_len = bnx2_COM_b06FwSbssLen;
2132 fw.sbss_index = 0;
2133 fw.sbss = bnx2_COM_b06FwSbss;
2134
2135 fw.bss_addr = bnx2_COM_b06FwBssAddr;
2136 fw.bss_len = bnx2_COM_b06FwBssLen;
2137 fw.bss_index = 0;
2138 fw.bss = bnx2_COM_b06FwBss;
2139
2140 fw.rodata_addr = bnx2_COM_b06FwRodataAddr;
2141 fw.rodata_len = bnx2_COM_b06FwRodataLen;
2142 fw.rodata_index = 0;
2143 fw.rodata = bnx2_COM_b06FwRodata;
2144
2145 load_cpu_fw(bp, &cpu_reg, &fw);
2146
2147}
2148
2149static int
829ca9a3 2150bnx2_set_power_state(struct bnx2 *bp, pci_power_t state)
b6016b76
MC		 2151{
2152 u16 pmcsr;
2153
2154 pci_read_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL, &pmcsr);
2155
2156 switch (state) {
829ca9a3 2157 case PCI_D0: {
b6016b76
MC		 2158 u32 val;
2159
2160 pci_write_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL,
2161 (pmcsr & ~PCI_PM_CTRL_STATE_MASK) |
2162 PCI_PM_CTRL_PME_STATUS);
2163
2164 if (pmcsr & PCI_PM_CTRL_STATE_MASK)
2165 /* delay required during transition out of D3hot */
2166 msleep(20);
2167
2168 val = REG_RD(bp, BNX2_EMAC_MODE);
2169 val |= BNX2_EMAC_MODE_MPKT_RCVD | BNX2_EMAC_MODE_ACPI_RCVD;
2170 val &= ~BNX2_EMAC_MODE_MPKT;
2171 REG_WR(bp, BNX2_EMAC_MODE, val);
2172
2173 val = REG_RD(bp, BNX2_RPM_CONFIG);
2174 val &= ~BNX2_RPM_CONFIG_ACPI_ENA;
2175 REG_WR(bp, BNX2_RPM_CONFIG, val);
2176 break;
2177 }
829ca9a3 2178 case PCI_D3hot: {
b6016b76
MC		 2179 int i;
2180 u32 val, wol_msg;
2181
2182 if (bp->wol) {
2183 u32 advertising;
2184 u8 autoneg;
2185
2186 autoneg = bp->autoneg;
2187 advertising = bp->advertising;
2188
2189 bp->autoneg = AUTONEG_SPEED;
2190 bp->advertising = ADVERTISED_10baseT_Half |
2191 ADVERTISED_10baseT_Full |
2192 ADVERTISED_100baseT_Half |
2193 ADVERTISED_100baseT_Full |
2194 ADVERTISED_Autoneg;
2195
2196 bnx2_setup_copper_phy(bp);
2197
2198 bp->autoneg = autoneg;
2199 bp->advertising = advertising;
2200
2201 bnx2_set_mac_addr(bp);
2202
2203 val = REG_RD(bp, BNX2_EMAC_MODE);
2204
2205 /* Enable port mode. */
2206 val &= ~BNX2_EMAC_MODE_PORT;
2207 val |= BNX2_EMAC_MODE_PORT_MII |
2208 BNX2_EMAC_MODE_MPKT_RCVD |
2209 BNX2_EMAC_MODE_ACPI_RCVD |
2210 BNX2_EMAC_MODE_FORCE_LINK |
2211 BNX2_EMAC_MODE_MPKT;
2212
2213 REG_WR(bp, BNX2_EMAC_MODE, val);
2214
2215 /* receive all multicast */
2216 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
2217 REG_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),
2218 0xffffffff);
2219 }
2220 REG_WR(bp, BNX2_EMAC_RX_MODE,
2221 BNX2_EMAC_RX_MODE_SORT_MODE);
2222
2223 val = 1 | BNX2_RPM_SORT_USER0_BC_EN |
2224 BNX2_RPM_SORT_USER0_MC_EN;
2225 REG_WR(bp, BNX2_RPM_SORT_USER0, 0x0);
2226 REG_WR(bp, BNX2_RPM_SORT_USER0, val);
2227 REG_WR(bp, BNX2_RPM_SORT_USER0, val |
2228 BNX2_RPM_SORT_USER0_ENA);
2229
2230 /* Need to enable EMAC and RPM for WOL. */
2231 REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS,
2232 BNX2_MISC_ENABLE_SET_BITS_RX_PARSER_MAC_ENABLE |
2233 BNX2_MISC_ENABLE_SET_BITS_TX_HEADER_Q_ENABLE |
2234 BNX2_MISC_ENABLE_SET_BITS_EMAC_ENABLE);
2235
2236 val = REG_RD(bp, BNX2_RPM_CONFIG);
2237 val &= ~BNX2_RPM_CONFIG_ACPI_ENA;
2238 REG_WR(bp, BNX2_RPM_CONFIG, val);
2239
2240 wol_msg = BNX2_DRV_MSG_CODE_SUSPEND_WOL;
2241 }
2242 else {
2243 wol_msg = BNX2_DRV_MSG_CODE_SUSPEND_NO_WOL;
2244 }
2245
2246 bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT3 | wol_msg);
2247
2248 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
2249 if ((CHIP_ID(bp) == CHIP_ID_5706_A0) ||
2250 (CHIP_ID(bp) == CHIP_ID_5706_A1)) {
2251
2252 if (bp->wol)
2253 pmcsr |= 3;
2254 }
2255 else {
2256 pmcsr |= 3;
2257 }
2258 if (bp->wol) {
2259 pmcsr |= PCI_PM_CTRL_PME_ENABLE;
2260 }
2261 pci_write_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL,
2262 pmcsr);
2263
2264 /* No more memory access after this point until
2265 * device is brought back to D0.
2266 */
2267 udelay(50);
2268 break;
2269 }
2270 default:
2271 return -EINVAL;
2272 }
2273 return 0;
2274}
2275
2276static int
2277bnx2_acquire_nvram_lock(struct bnx2 *bp)
2278{
2279 u32 val;
2280 int j;
2281
2282 /* Request access to the flash interface. */
2283 REG_WR(bp, BNX2_NVM_SW_ARB, BNX2_NVM_SW_ARB_ARB_REQ_SET2);
2284 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
2285 val = REG_RD(bp, BNX2_NVM_SW_ARB);
2286 if (val & BNX2_NVM_SW_ARB_ARB_ARB2)
2287 break;
2288
2289 udelay(5);
2290 }
2291
2292 if (j >= NVRAM_TIMEOUT_COUNT)
2293 return -EBUSY;
2294
2295 return 0;
2296}
2297
2298static int
2299bnx2_release_nvram_lock(struct bnx2 *bp)
2300{
2301 int j;
2302 u32 val;
2303
2304 /* Relinquish nvram interface. */
2305 REG_WR(bp, BNX2_NVM_SW_ARB, BNX2_NVM_SW_ARB_ARB_REQ_CLR2);
2306
2307 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
2308 val = REG_RD(bp, BNX2_NVM_SW_ARB);
2309 if (!(val & BNX2_NVM_SW_ARB_ARB_ARB2))
2310 break;
2311
2312 udelay(5);
2313 }
2314
2315 if (j >= NVRAM_TIMEOUT_COUNT)
2316 return -EBUSY;
2317
2318 return 0;
2319}
2320
2321
2322static int
2323bnx2_enable_nvram_write(struct bnx2 *bp)
2324{
2325 u32 val;
2326
2327 val = REG_RD(bp, BNX2_MISC_CFG);
2328 REG_WR(bp, BNX2_MISC_CFG, val | BNX2_MISC_CFG_NVM_WR_EN_PCI);
2329
2330 if (!bp->flash_info->buffered) {
2331 int j;
2332
2333 REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
2334 REG_WR(bp, BNX2_NVM_COMMAND,
2335 BNX2_NVM_COMMAND_WREN | BNX2_NVM_COMMAND_DOIT);
2336
2337 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
2338 udelay(5);
2339
2340 val = REG_RD(bp, BNX2_NVM_COMMAND);
2341 if (val & BNX2_NVM_COMMAND_DONE)
2342 break;
2343 }
2344
2345 if (j >= NVRAM_TIMEOUT_COUNT)
2346 return -EBUSY;
2347 }
2348 return 0;
2349}
2350
2351static void
2352bnx2_disable_nvram_write(struct bnx2 *bp)
2353{
2354 u32 val;
2355
2356 val = REG_RD(bp, BNX2_MISC_CFG);
2357 REG_WR(bp, BNX2_MISC_CFG, val & ~BNX2_MISC_CFG_NVM_WR_EN);
2358}
2359
2360
2361static void
2362bnx2_enable_nvram_access(struct bnx2 *bp)
2363{
2364 u32 val;
2365
2366 val = REG_RD(bp, BNX2_NVM_ACCESS_ENABLE);
2367 /* Enable both bits, even on read. */
2368 REG_WR(bp, BNX2_NVM_ACCESS_ENABLE,
2369 val | BNX2_NVM_ACCESS_ENABLE_EN | BNX2_NVM_ACCESS_ENABLE_WR_EN);
2370}
2371
2372static void
2373bnx2_disable_nvram_access(struct bnx2 *bp)
2374{
2375 u32 val;
2376
2377 val = REG_RD(bp, BNX2_NVM_ACCESS_ENABLE);
2378 /* Disable both bits, even after read. */
2379 REG_WR(bp, BNX2_NVM_ACCESS_ENABLE,
2380 val & ~(BNX2_NVM_ACCESS_ENABLE_EN |
2381 BNX2_NVM_ACCESS_ENABLE_WR_EN));
2382}
2383
2384static int
2385bnx2_nvram_erase_page(struct bnx2 *bp, u32 offset)
2386{
2387 u32 cmd;
2388 int j;
2389
2390 if (bp->flash_info->buffered)
2391 /* Buffered flash, no erase needed */
2392 return 0;
2393
2394 /* Build an erase command */
2395 cmd = BNX2_NVM_COMMAND_ERASE | BNX2_NVM_COMMAND_WR |
2396 BNX2_NVM_COMMAND_DOIT;
2397
2398 /* Need to clear DONE bit separately. */
2399 REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
2400
2401 /* Address of the NVRAM to read from. */
2402 REG_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);
2403
2404 /* Issue an erase command. */
2405 REG_WR(bp, BNX2_NVM_COMMAND, cmd);
2406
2407 /* Wait for completion. */
2408 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
2409 u32 val;
2410
2411 udelay(5);
2412
2413 val = REG_RD(bp, BNX2_NVM_COMMAND);
2414 if (val & BNX2_NVM_COMMAND_DONE)
2415 break;
2416 }
2417
2418 if (j >= NVRAM_TIMEOUT_COUNT)
2419 return -EBUSY;
2420
2421 return 0;
2422}
2423
2424static int
2425bnx2_nvram_read_dword(struct bnx2 *bp, u32 offset, u8 *ret_val, u32 cmd_flags)
2426{
2427 u32 cmd;
2428 int j;
2429
2430 /* Build the command word. */
2431 cmd = BNX2_NVM_COMMAND_DOIT | cmd_flags;
2432
2433 /* Calculate an offset of a buffered flash. */
2434 if (bp->flash_info->buffered) {
2435 offset = ((offset / bp->flash_info->page_size) <<
2436 bp->flash_info->page_bits) +
2437 (offset % bp->flash_info->page_size);
2438 }
2439
2440 /* Need to clear DONE bit separately. */
2441 REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
2442
2443 /* Address of the NVRAM to read from. */
2444 REG_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);
2445
2446 /* Issue a read command. */
2447 REG_WR(bp, BNX2_NVM_COMMAND, cmd);
2448
2449 /* Wait for completion. */
2450 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
2451 u32 val;
2452
2453 udelay(5);
2454
2455 val = REG_RD(bp, BNX2_NVM_COMMAND);
2456 if (val & BNX2_NVM_COMMAND_DONE) {
2457 val = REG_RD(bp, BNX2_NVM_READ);
2458
2459 val = be32_to_cpu(val);
2460 memcpy(ret_val, &val, 4);
2461 break;
2462 }
2463 }
2464 if (j >= NVRAM_TIMEOUT_COUNT)
2465 return -EBUSY;
2466
2467 return 0;
2468}
2469
2470
2471static int
2472bnx2_nvram_write_dword(struct bnx2 *bp, u32 offset, u8 *val, u32 cmd_flags)
2473{
2474 u32 cmd, val32;
2475 int j;
2476
2477 /* Build the command word. */
2478 cmd = BNX2_NVM_COMMAND_DOIT | BNX2_NVM_COMMAND_WR | cmd_flags;
2479
2480 /* Calculate an offset of a buffered flash. */
2481 if (bp->flash_info->buffered) {
2482 offset = ((offset / bp->flash_info->page_size) <<
2483 bp->flash_info->page_bits) +
2484 (offset % bp->flash_info->page_size);
2485 }
2486
2487 /* Need to clear DONE bit separately. */
2488 REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
2489
2490 memcpy(&val32, val, 4);
2491 val32 = cpu_to_be32(val32);
2492
2493 /* Write the data. */
2494 REG_WR(bp, BNX2_NVM_WRITE, val32);
2495
2496 /* Address of the NVRAM to write to. */
2497 REG_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);
2498
2499 /* Issue the write command. */
2500 REG_WR(bp, BNX2_NVM_COMMAND, cmd);
2501
2502 /* Wait for completion. */
2503 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
2504 udelay(5);
2505
2506 if (REG_RD(bp, BNX2_NVM_COMMAND) & BNX2_NVM_COMMAND_DONE)
2507 break;
2508 }
2509 if (j >= NVRAM_TIMEOUT_COUNT)
2510 return -EBUSY;
2511
2512 return 0;
2513}
2514
2515static int
2516bnx2_init_nvram(struct bnx2 *bp)
2517{
2518 u32 val;
2519 int j, entry_count, rc;
2520 struct flash_spec *flash;
2521
2522 /* Determine the selected interface. */
2523 val = REG_RD(bp, BNX2_NVM_CFG1);
2524
2525 entry_count = sizeof(flash_table) / sizeof(struct flash_spec);
2526
2527 rc = 0;
2528 if (val & 0x40000000) {
2529
2530 /* Flash interface has been reconfigured */
2531 for (j = 0, flash = &flash_table[0]; j < entry_count;
2532 j++, flash++) {
2533
2534 if (val == flash->config1) {
2535 bp->flash_info = flash;
2536 break;
2537 }
2538 }
2539 }
2540 else {
2541 /* Not yet been reconfigured */
2542
2543 for (j = 0, flash = &flash_table[0]; j < entry_count;
2544 j++, flash++) {
2545
2546 if ((val & FLASH_STRAP_MASK) == flash->strapping) {
2547 bp->flash_info = flash;
2548
2549 /* Request access to the flash interface. */
2550 if ((rc = bnx2_acquire_nvram_lock(bp)) != 0)
2551 return rc;
2552
2553 /* Enable access to flash interface */
2554 bnx2_enable_nvram_access(bp);
2555
2556 /* Reconfigure the flash interface */
2557 REG_WR(bp, BNX2_NVM_CFG1, flash->config1);
2558 REG_WR(bp, BNX2_NVM_CFG2, flash->config2);
2559 REG_WR(bp, BNX2_NVM_CFG3, flash->config3);
2560 REG_WR(bp, BNX2_NVM_WRITE1, flash->write1);
2561
2562 /* Disable access to flash interface */
2563 bnx2_disable_nvram_access(bp);
2564 bnx2_release_nvram_lock(bp);
2565
2566 break;
2567 }
2568 }
2569 } /* if (val & 0x40000000) */
2570
2571 if (j == entry_count) {
2572 bp->flash_info = NULL;
2573 printk(KERN_ALERT "Unknown flash/EEPROM type.\n");
2574 rc = -ENODEV;
2575 }
2576
2577 return rc;
2578}
2579
2580static int
2581bnx2_nvram_read(struct bnx2 *bp, u32 offset, u8 *ret_buf,
2582 int buf_size)
2583{
2584 int rc = 0;
2585 u32 cmd_flags, offset32, len32, extra;
2586
2587 if (buf_size == 0)
2588 return 0;
2589
2590 /* Request access to the flash interface. */
2591 if ((rc = bnx2_acquire_nvram_lock(bp)) != 0)
2592 return rc;
2593
2594 /* Enable access to flash interface */
2595 bnx2_enable_nvram_access(bp);
2596
2597 len32 = buf_size;
2598 offset32 = offset;
2599 extra = 0;
2600
2601 cmd_flags = 0;
2602
2603 if (offset32 & 3) {
2604 u8 buf[4];
2605 u32 pre_len;
2606
2607 offset32 &= ~3;
2608 pre_len = 4 - (offset & 3);
2609
2610 if (pre_len >= len32) {
2611 pre_len = len32;
2612 cmd_flags = BNX2_NVM_COMMAND_FIRST |
2613 BNX2_NVM_COMMAND_LAST;
2614 }
2615 else {
2616 cmd_flags = BNX2_NVM_COMMAND_FIRST;
2617 }
2618
2619 rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags);
2620
2621 if (rc)
2622 return rc;
2623
2624 memcpy(ret_buf, buf + (offset & 3), pre_len);
2625
2626 offset32 += 4;
2627 ret_buf += pre_len;
2628 len32 -= pre_len;
2629 }
2630 if (len32 & 3) {
2631 extra = 4 - (len32 & 3);
2632 len32 = (len32 + 4) & ~3;
2633 }
2634
2635 if (len32 == 4) {
2636 u8 buf[4];
2637
2638 if (cmd_flags)
2639 cmd_flags = BNX2_NVM_COMMAND_LAST;
2640 else
2641 cmd_flags = BNX2_NVM_COMMAND_FIRST |
2642 BNX2_NVM_COMMAND_LAST;
2643
2644 rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags);
2645
2646 memcpy(ret_buf, buf, 4 - extra);
2647 }
2648 else if (len32 > 0) {
2649 u8 buf[4];
2650
2651 /* Read the first word. */
2652 if (cmd_flags)
2653 cmd_flags = 0;
2654 else
2655 cmd_flags = BNX2_NVM_COMMAND_FIRST;
2656
2657 rc = bnx2_nvram_read_dword(bp, offset32, ret_buf, cmd_flags);
2658
2659 /* Advance to the next dword. */
2660 offset32 += 4;
2661 ret_buf += 4;
2662 len32 -= 4;
2663
2664 while (len32 > 4 && rc == 0) {
2665 rc = bnx2_nvram_read_dword(bp, offset32, ret_buf, 0);
2666
2667 /* Advance to the next dword. */
2668 offset32 += 4;
2669 ret_buf += 4;
2670 len32 -= 4;
2671 }
2672
2673 if (rc)
2674 return rc;
2675
2676 cmd_flags = BNX2_NVM_COMMAND_LAST;
2677 rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags);
2678
2679 memcpy(ret_buf, buf, 4 - extra);
2680 }
2681
2682 /* Disable access to flash interface */
2683 bnx2_disable_nvram_access(bp);
2684
2685 bnx2_release_nvram_lock(bp);
2686
2687 return rc;
2688}
2689
2690static int
2691bnx2_nvram_write(struct bnx2 *bp, u32 offset, u8 *data_buf,
2692 int buf_size)
2693{
2694 u32 written, offset32, len32;
2695 u8 *buf, start[4], end[4];
2696 int rc = 0;
2697 int align_start, align_end;
2698
2699 buf = data_buf;
2700 offset32 = offset;
2701 len32 = buf_size;
2702 align_start = align_end = 0;
2703
2704 if ((align_start = (offset32 & 3))) {
2705 offset32 &= ~3;
2706 len32 += align_start;
2707 if ((rc = bnx2_nvram_read(bp, offset32, start, 4)))
2708 return rc;
2709 }
2710
2711 if (len32 & 3) {
2712 if ((len32 > 4) || !align_start) {
2713 align_end = 4 - (len32 & 3);
2714 len32 += align_end;
2715 if ((rc = bnx2_nvram_read(bp, offset32 + len32 - 4,
2716 end, 4))) {
2717 return rc;
2718 }
2719 }
2720 }
2721
2722 if (align_start || align_end) {
2723 buf = kmalloc(len32, GFP_KERNEL);
2724 if (buf == 0)
2725 return -ENOMEM;
2726 if (align_start) {
2727 memcpy(buf, start, 4);
2728 }
2729 if (align_end) {
2730 memcpy(buf + len32 - 4, end, 4);
2731 }
2732 memcpy(buf + align_start, data_buf, buf_size);
2733 }
2734
2735 written = 0;
2736 while ((written < len32) && (rc == 0)) {
2737 u32 page_start, page_end, data_start, data_end;
2738 u32 addr, cmd_flags;
2739 int i;
2740 u8 flash_buffer[264];
2741
2742 /* Find the page_start addr */
2743 page_start = offset32 + written;
2744 page_start -= (page_start % bp->flash_info->page_size);
2745 /* Find the page_end addr */
2746 page_end = page_start + bp->flash_info->page_size;
2747 /* Find the data_start addr */
2748 data_start = (written == 0) ? offset32 : page_start;
2749 /* Find the data_end addr */
2750 data_end = (page_end > offset32 + len32) ?
2751 (offset32 + len32) : page_end;
2752
2753 /* Request access to the flash interface. */
2754 if ((rc = bnx2_acquire_nvram_lock(bp)) != 0)
2755 goto nvram_write_end;
2756
2757 /* Enable access to flash interface */
2758 bnx2_enable_nvram_access(bp);
2759
2760 cmd_flags = BNX2_NVM_COMMAND_FIRST;
2761 if (bp->flash_info->buffered == 0) {
2762 int j;
2763
2764 /* Read the whole page into the buffer
2765 * (non-buffer flash only) */
2766 for (j = 0; j < bp->flash_info->page_size; j += 4) {
2767 if (j == (bp->flash_info->page_size - 4)) {
2768 cmd_flags |= BNX2_NVM_COMMAND_LAST;
2769 }
2770 rc = bnx2_nvram_read_dword(bp,
2771 page_start + j,
2772 &flash_buffer[j],
2773 cmd_flags);
2774
2775 if (rc)
2776 goto nvram_write_end;
2777
2778 cmd_flags = 0;
2779 }
2780 }
2781
2782 /* Enable writes to flash interface (unlock write-protect) */
2783 if ((rc = bnx2_enable_nvram_write(bp)) != 0)
2784 goto nvram_write_end;
2785
2786 /* Erase the page */
2787 if ((rc = bnx2_nvram_erase_page(bp, page_start)) != 0)
2788 goto nvram_write_end;
2789
2790 /* Re-enable the write again for the actual write */
2791 bnx2_enable_nvram_write(bp);
2792
2793 /* Loop to write back the buffer data from page_start to
2794 * data_start */
2795 i = 0;
2796 if (bp->flash_info->buffered == 0) {
2797 for (addr = page_start; addr < data_start;
2798 addr += 4, i += 4) {
2799
2800 rc = bnx2_nvram_write_dword(bp, addr,
2801 &flash_buffer[i], cmd_flags);
2802
2803 if (rc != 0)
2804 goto nvram_write_end;
2805
2806 cmd_flags = 0;
2807 }
2808 }
2809
2810 /* Loop to write the new data from data_start to data_end */
2811 for (addr = data_start; addr < data_end; addr += 4, i++) {
2812 if ((addr == page_end - 4) ||
2813 ((bp->flash_info->buffered) &&
2814 (addr == data_end - 4))) {
2815
2816 cmd_flags |= BNX2_NVM_COMMAND_LAST;
2817 }
2818 rc = bnx2_nvram_write_dword(bp, addr, buf,
2819 cmd_flags);
2820
2821 if (rc != 0)
2822 goto nvram_write_end;
2823
2824 cmd_flags = 0;
2825 buf += 4;
2826 }
2827
2828 /* Loop to write back the buffer data from data_end
2829 * to page_end */
2830 if (bp->flash_info->buffered == 0) {
2831 for (addr = data_end; addr < page_end;
2832 addr += 4, i += 4) {
2833
2834 if (addr == page_end-4) {
2835 cmd_flags = BNX2_NVM_COMMAND_LAST;
2836 }
2837 rc = bnx2_nvram_write_dword(bp, addr,
2838 &flash_buffer[i], cmd_flags);
2839
2840 if (rc != 0)
2841 goto nvram_write_end;
2842
2843 cmd_flags = 0;
2844 }
2845 }
2846
2847 /* Disable writes to flash interface (lock write-protect) */
2848 bnx2_disable_nvram_write(bp);
2849
2850 /* Disable access to flash interface */
2851 bnx2_disable_nvram_access(bp);
2852 bnx2_release_nvram_lock(bp);
2853
2854 /* Increment written */
2855 written += data_end - data_start;
2856 }
2857
2858nvram_write_end:
2859 if (align_start || align_end)
2860 kfree(buf);
2861 return rc;
2862}
2863
2864static int
2865bnx2_reset_chip(struct bnx2 *bp, u32 reset_code)
2866{
2867 u32 val;
2868 int i, rc = 0;
2869
2870 /* Wait for the current PCI transaction to complete before
2871 * issuing a reset. */
2872 REG_WR(bp, BNX2_MISC_ENABLE_CLR_BITS,
2873 BNX2_MISC_ENABLE_CLR_BITS_TX_DMA_ENABLE |
2874 BNX2_MISC_ENABLE_CLR_BITS_DMA_ENGINE_ENABLE |
2875 BNX2_MISC_ENABLE_CLR_BITS_RX_DMA_ENABLE |
2876 BNX2_MISC_ENABLE_CLR_BITS_HOST_COALESCE_ENABLE);
2877 val = REG_RD(bp, BNX2_MISC_ENABLE_CLR_BITS);
2878 udelay(5);
2879
2880 /* Deposit a driver reset signature so the firmware knows that
2881 * this is a soft reset. */
2882 REG_WR_IND(bp, HOST_VIEW_SHMEM_BASE + BNX2_DRV_RESET_SIGNATURE,
2883 BNX2_DRV_RESET_SIGNATURE_MAGIC);
2884
2885 bp->fw_timed_out = 0;
2886
2887 /* Wait for the firmware to tell us it is ok to issue a reset. */
2888 bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT0 | reset_code);
2889
2890 /* Do a dummy read to force the chip to complete all current transaction
2891 * before we issue a reset. */
2892 val = REG_RD(bp, BNX2_MISC_ID);
2893
2894 val = BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |
2895 BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
2896 BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP;
2897
2898 /* Chip reset. */
2899 REG_WR(bp, BNX2_PCICFG_MISC_CONFIG, val);
2900
2901 if ((CHIP_ID(bp) == CHIP_ID_5706_A0) ||
2902 (CHIP_ID(bp) == CHIP_ID_5706_A1))
2903 msleep(15);
2904
2905 /* Reset takes approximate 30 usec */
2906 for (i = 0; i < 10; i++) {
2907 val = REG_RD(bp, BNX2_PCICFG_MISC_CONFIG);
2908 if ((val & (BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |
2909 BNX2_PCICFG_MISC_CONFIG_CORE_RST_BSY)) == 0) {
2910 break;
2911 }
2912 udelay(10);
2913 }
2914
2915 if (val & (BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |
2916 BNX2_PCICFG_MISC_CONFIG_CORE_RST_BSY)) {
2917 printk(KERN_ERR PFX "Chip reset did not complete\n");
2918 return -EBUSY;
2919 }
2920
2921 /* Make sure byte swapping is properly configured. */
2922 val = REG_RD(bp, BNX2_PCI_SWAP_DIAG0);
2923 if (val != 0x01020304) {
2924 printk(KERN_ERR PFX "Chip not in correct endian mode\n");
2925 return -ENODEV;
2926 }
2927
2928 bp->fw_timed_out = 0;
2929
2930 /* Wait for the firmware to finish its initialization. */
2931 bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT1 | reset_code);
2932
2933 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
2934 /* Adjust the voltage regular to two steps lower. The default
2935 * of this register is 0x0000000e. */
2936 REG_WR(bp, BNX2_MISC_VREG_CONTROL, 0x000000fa);
2937
2938 /* Remove bad rbuf memory from the free pool. */
2939 rc = bnx2_alloc_bad_rbuf(bp);
2940 }
2941
2942 return rc;
2943}
2944
2945static int
2946bnx2_init_chip(struct bnx2 *bp)
2947{
2948 u32 val;
2949
2950 /* Make sure the interrupt is not active. */
2951 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
2952
2953 val = BNX2_DMA_CONFIG_DATA_BYTE_SWAP |
2954 BNX2_DMA_CONFIG_DATA_WORD_SWAP |
2955#ifdef __BIG_ENDIAN
2956 BNX2_DMA_CONFIG_CNTL_BYTE_SWAP |
2957#endif
2958 BNX2_DMA_CONFIG_CNTL_WORD_SWAP |
2959 DMA_READ_CHANS << 12 |
2960 DMA_WRITE_CHANS << 16;
2961
2962 val |= (0x2 << 20) | (1 << 11);
2963
2964 if ((bp->flags & PCIX_FLAG) && (bp->bus_speed_mhz = 133))
2965 val |= (1 << 23);
2966
2967 if ((CHIP_NUM(bp) == CHIP_NUM_5706) &&
2968 (CHIP_ID(bp) != CHIP_ID_5706_A0) && !(bp->flags & PCIX_FLAG))
2969 val |= BNX2_DMA_CONFIG_CNTL_PING_PONG_DMA;
2970
2971 REG_WR(bp, BNX2_DMA_CONFIG, val);
2972
2973 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
2974 val = REG_RD(bp, BNX2_TDMA_CONFIG);
2975 val |= BNX2_TDMA_CONFIG_ONE_DMA;
2976 REG_WR(bp, BNX2_TDMA_CONFIG, val);
2977 }
2978
2979 if (bp->flags & PCIX_FLAG) {
2980 u16 val16;
2981
2982 pci_read_config_word(bp->pdev, bp->pcix_cap + PCI_X_CMD,
2983 &val16);
2984 pci_write_config_word(bp->pdev, bp->pcix_cap + PCI_X_CMD,
2985 val16 & ~PCI_X_CMD_ERO);
2986 }
2987
2988 REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS,
2989 BNX2_MISC_ENABLE_SET_BITS_HOST_COALESCE_ENABLE |
2990 BNX2_MISC_ENABLE_STATUS_BITS_RX_V2P_ENABLE |
2991 BNX2_MISC_ENABLE_STATUS_BITS_CONTEXT_ENABLE);
2992
2993 /* Initialize context mapping and zero out the quick contexts. The
2994 * context block must have already been enabled. */
2995 bnx2_init_context(bp);
2996
2997 bnx2_init_cpus(bp);
2998 bnx2_init_nvram(bp);
2999
3000 bnx2_set_mac_addr(bp);
3001
3002 val = REG_RD(bp, BNX2_MQ_CONFIG);
3003 val &= ~BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE;
3004 val |= BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE_256;
3005 REG_WR(bp, BNX2_MQ_CONFIG, val);
3006
3007 val = 0x10000 + (MAX_CID_CNT * MB_KERNEL_CTX_SIZE);
3008 REG_WR(bp, BNX2_MQ_KNL_BYP_WIND_START, val);
3009 REG_WR(bp, BNX2_MQ_KNL_WIND_END, val);
3010
3011 val = (BCM_PAGE_BITS - 8) << 24;
3012 REG_WR(bp, BNX2_RV2P_CONFIG, val);
3013
3014 /* Configure page size. */
3015 val = REG_RD(bp, BNX2_TBDR_CONFIG);
3016 val &= ~BNX2_TBDR_CONFIG_PAGE_SIZE;
3017 val |= (BCM_PAGE_BITS - 8) << 24 | 0x40;
3018 REG_WR(bp, BNX2_TBDR_CONFIG, val);
3019
3020 val = bp->mac_addr[0] +
3021 (bp->mac_addr[1] << 8) +
3022 (bp->mac_addr[2] << 16) +
3023 bp->mac_addr[3] +
3024 (bp->mac_addr[4] << 8) +
3025 (bp->mac_addr[5] << 16);
3026 REG_WR(bp, BNX2_EMAC_BACKOFF_SEED, val);
3027
3028 /* Program the MTU. Also include 4 bytes for CRC32. */
3029 val = bp->dev->mtu + ETH_HLEN + 4;
3030 if (val > (MAX_ETHERNET_PACKET_SIZE + 4))
3031 val |= BNX2_EMAC_RX_MTU_SIZE_JUMBO_ENA;
3032 REG_WR(bp, BNX2_EMAC_RX_MTU_SIZE, val);
3033
3034 bp->last_status_idx = 0;
3035 bp->rx_mode = BNX2_EMAC_RX_MODE_SORT_MODE;
3036
3037 /* Set up how to generate a link change interrupt. */
3038 REG_WR(bp, BNX2_EMAC_ATTENTION_ENA, BNX2_EMAC_ATTENTION_ENA_LINK);
3039
3040 REG_WR(bp, BNX2_HC_STATUS_ADDR_L,
3041 (u64) bp->status_blk_mapping & 0xffffffff);
3042 REG_WR(bp, BNX2_HC_STATUS_ADDR_H, (u64) bp->status_blk_mapping >> 32);
3043
3044 REG_WR(bp, BNX2_HC_STATISTICS_ADDR_L,
3045 (u64) bp->stats_blk_mapping & 0xffffffff);
3046 REG_WR(bp, BNX2_HC_STATISTICS_ADDR_H,
3047 (u64) bp->stats_blk_mapping >> 32);
3048
3049 REG_WR(bp, BNX2_HC_TX_QUICK_CONS_TRIP,
3050 (bp->tx_quick_cons_trip_int << 16) | bp->tx_quick_cons_trip);
3051
3052 REG_WR(bp, BNX2_HC_RX_QUICK_CONS_TRIP,
3053 (bp->rx_quick_cons_trip_int << 16) | bp->rx_quick_cons_trip);
3054
3055 REG_WR(bp, BNX2_HC_COMP_PROD_TRIP,
3056 (bp->comp_prod_trip_int << 16) | bp->comp_prod_trip);
3057
3058 REG_WR(bp, BNX2_HC_TX_TICKS, (bp->tx_ticks_int << 16) | bp->tx_ticks);
3059
3060 REG_WR(bp, BNX2_HC_RX_TICKS, (bp->rx_ticks_int << 16) | bp->rx_ticks);
3061
3062 REG_WR(bp, BNX2_HC_COM_TICKS,
3063 (bp->com_ticks_int << 16) | bp->com_ticks);
3064
3065 REG_WR(bp, BNX2_HC_CMD_TICKS,
3066 (bp->cmd_ticks_int << 16) | bp->cmd_ticks);
3067
3068 REG_WR(bp, BNX2_HC_STATS_TICKS, bp->stats_ticks & 0xffff00);
3069 REG_WR(bp, BNX2_HC_STAT_COLLECT_TICKS, 0xbb8); /* 3ms */
3070
3071 if (CHIP_ID(bp) == CHIP_ID_5706_A1)
3072 REG_WR(bp, BNX2_HC_CONFIG, BNX2_HC_CONFIG_COLLECT_STATS);
3073 else {
3074 REG_WR(bp, BNX2_HC_CONFIG, BNX2_HC_CONFIG_RX_TMR_MODE |
3075 BNX2_HC_CONFIG_TX_TMR_MODE |
3076 BNX2_HC_CONFIG_COLLECT_STATS);
3077 }
3078
3079 /* Clear internal stats counters. */
3080 REG_WR(bp, BNX2_HC_COMMAND, BNX2_HC_COMMAND_CLR_STAT_NOW);
3081
3082 REG_WR(bp, BNX2_HC_ATTN_BITS_ENABLE, STATUS_ATTN_BITS_LINK_STATE);
3083
3084 /* Initialize the receive filter. */
3085 bnx2_set_rx_mode(bp->dev);
3086
3087 bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT2 | BNX2_DRV_MSG_CODE_RESET);
3088
3089 REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS, 0x5ffffff);
3090 REG_RD(bp, BNX2_MISC_ENABLE_SET_BITS);
3091
3092 udelay(20);
3093
3094 return 0;
3095}
3096
3097
3098static void
3099bnx2_init_tx_ring(struct bnx2 *bp)
3100{
3101 struct tx_bd *txbd;
3102 u32 val;
3103
3104 txbd = &bp->tx_desc_ring[MAX_TX_DESC_CNT];
3105
3106 txbd->tx_bd_haddr_hi = (u64) bp->tx_desc_mapping >> 32;
3107 txbd->tx_bd_haddr_lo = (u64) bp->tx_desc_mapping & 0xffffffff;
3108
3109 bp->tx_prod = 0;
3110 bp->tx_cons = 0;
3111 bp->tx_prod_bseq = 0;
b6016b76
MC		 3112
3113 val = BNX2_L2CTX_TYPE_TYPE_L2;
3114 val |= BNX2_L2CTX_TYPE_SIZE_L2;
3115 CTX_WR(bp, GET_CID_ADDR(TX_CID), BNX2_L2CTX_TYPE, val);
3116
3117 val = BNX2_L2CTX_CMD_TYPE_TYPE_L2;
3118 val |= 8 << 16;
3119 CTX_WR(bp, GET_CID_ADDR(TX_CID), BNX2_L2CTX_CMD_TYPE, val);
3120
3121 val = (u64) bp->tx_desc_mapping >> 32;
3122 CTX_WR(bp, GET_CID_ADDR(TX_CID), BNX2_L2CTX_TBDR_BHADDR_HI, val);
3123
3124 val = (u64) bp->tx_desc_mapping & 0xffffffff;
3125 CTX_WR(bp, GET_CID_ADDR(TX_CID), BNX2_L2CTX_TBDR_BHADDR_LO, val);
3126}
3127
3128static void
3129bnx2_init_rx_ring(struct bnx2 *bp)
3130{
3131 struct rx_bd *rxbd;
3132 int i;
3133 u16 prod, ring_prod;
3134 u32 val;
3135
3136 /* 8 for CRC and VLAN */
3137 bp->rx_buf_use_size = bp->dev->mtu + ETH_HLEN + bp->rx_offset + 8;
3138 /* 8 for alignment */
3139 bp->rx_buf_size = bp->rx_buf_use_size + 8;
3140
3141 ring_prod = prod = bp->rx_prod = 0;
3142 bp->rx_cons = 0;
3143 bp->rx_prod_bseq = 0;
3144
3145 rxbd = &bp->rx_desc_ring[0];
3146 for (i = 0; i < MAX_RX_DESC_CNT; i++, rxbd++) {
3147 rxbd->rx_bd_len = bp->rx_buf_use_size;
3148 rxbd->rx_bd_flags = RX_BD_FLAGS_START | RX_BD_FLAGS_END;
3149 }
3150
3151 rxbd->rx_bd_haddr_hi = (u64) bp->rx_desc_mapping >> 32;
3152 rxbd->rx_bd_haddr_lo = (u64) bp->rx_desc_mapping & 0xffffffff;
3153
3154 val = BNX2_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE;
3155 val |= BNX2_L2CTX_CTX_TYPE_SIZE_L2;
3156 val |= 0x02 << 8;
3157 CTX_WR(bp, GET_CID_ADDR(RX_CID), BNX2_L2CTX_CTX_TYPE, val);
3158
3159 val = (u64) bp->rx_desc_mapping >> 32;
3160 CTX_WR(bp, GET_CID_ADDR(RX_CID), BNX2_L2CTX_NX_BDHADDR_HI, val);
3161
3162 val = (u64) bp->rx_desc_mapping & 0xffffffff;
3163 CTX_WR(bp, GET_CID_ADDR(RX_CID), BNX2_L2CTX_NX_BDHADDR_LO, val);
3164
3165 for ( ;ring_prod < bp->rx_ring_size; ) {
3166 if (bnx2_alloc_rx_skb(bp, ring_prod) < 0) {
3167 break;
3168 }
3169 prod = NEXT_RX_BD(prod);
3170 ring_prod = RX_RING_IDX(prod);
3171 }
3172 bp->rx_prod = prod;
3173
3174 REG_WR16(bp, MB_RX_CID_ADDR + BNX2_L2CTX_HOST_BDIDX, prod);
3175
3176 REG_WR(bp, MB_RX_CID_ADDR + BNX2_L2CTX_HOST_BSEQ, bp->rx_prod_bseq);
3177}
3178
3179static void
3180bnx2_free_tx_skbs(struct bnx2 *bp)
3181{
3182 int i;
3183
3184 if (bp->tx_buf_ring == NULL)
3185 return;
3186
3187 for (i = 0; i < TX_DESC_CNT; ) {
3188 struct sw_bd *tx_buf = &bp->tx_buf_ring[i];
3189 struct sk_buff *skb = tx_buf->skb;
3190 int j, last;
3191
3192 if (skb == NULL) {
3193 i++;
3194 continue;
3195 }
3196
3197 pci_unmap_single(bp->pdev, pci_unmap_addr(tx_buf, mapping),
3198 skb_headlen(skb), PCI_DMA_TODEVICE);
3199
3200 tx_buf->skb = NULL;
3201
3202 last = skb_shinfo(skb)->nr_frags;
3203 for (j = 0; j < last; j++) {
3204 tx_buf = &bp->tx_buf_ring[i + j + 1];
3205 pci_unmap_page(bp->pdev,
3206 pci_unmap_addr(tx_buf, mapping),
3207 skb_shinfo(skb)->frags[j].size,
3208 PCI_DMA_TODEVICE);
3209 }
3210 dev_kfree_skb_any(skb);
3211 i += j + 1;
3212 }
3213
3214}
3215
3216static void
3217bnx2_free_rx_skbs(struct bnx2 *bp)
3218{
3219 int i;
3220
3221 if (bp->rx_buf_ring == NULL)
3222 return;
3223
3224 for (i = 0; i < RX_DESC_CNT; i++) {
3225 struct sw_bd *rx_buf = &bp->rx_buf_ring[i];
3226 struct sk_buff *skb = rx_buf->skb;
3227
3228 if (skb == 0)
3229 continue;
3230
3231 pci_unmap_single(bp->pdev, pci_unmap_addr(rx_buf, mapping),
3232 bp->rx_buf_use_size, PCI_DMA_FROMDEVICE);
3233
3234 rx_buf->skb = NULL;
3235
3236 dev_kfree_skb_any(skb);
3237 }
3238}
3239
3240static void
3241bnx2_free_skbs(struct bnx2 *bp)
3242{
3243 bnx2_free_tx_skbs(bp);
3244 bnx2_free_rx_skbs(bp);
3245}
3246
3247static int
3248bnx2_reset_nic(struct bnx2 *bp, u32 reset_code)
3249{
3250 int rc;
3251
3252 rc = bnx2_reset_chip(bp, reset_code);
3253 bnx2_free_skbs(bp);
3254 if (rc)
3255 return rc;
3256
3257 bnx2_init_chip(bp);
3258 bnx2_init_tx_ring(bp);
3259 bnx2_init_rx_ring(bp);
3260 return 0;
3261}
3262
3263static int
3264bnx2_init_nic(struct bnx2 *bp)
3265{
3266 int rc;
3267
3268 if ((rc = bnx2_reset_nic(bp, BNX2_DRV_MSG_CODE_RESET)) != 0)
3269 return rc;
3270
3271 bnx2_init_phy(bp);
3272 bnx2_set_link(bp);
3273 return 0;
3274}
3275
3276static int
3277bnx2_test_registers(struct bnx2 *bp)
3278{
3279 int ret;
3280 int i;
3281 static struct {
3282 u16 offset;
3283 u16 flags;
3284 u32 rw_mask;
3285 u32 ro_mask;
3286 } reg_tbl[] = {
3287 { 0x006c, 0, 0x00000000, 0x0000003f },
3288 { 0x0090, 0, 0xffffffff, 0x00000000 },
3289 { 0x0094, 0, 0x00000000, 0x00000000 },
3290
3291 { 0x0404, 0, 0x00003f00, 0x00000000 },
3292 { 0x0418, 0, 0x00000000, 0xffffffff },
3293 { 0x041c, 0, 0x00000000, 0xffffffff },
3294 { 0x0420, 0, 0x00000000, 0x80ffffff },
3295 { 0x0424, 0, 0x00000000, 0x00000000 },
3296 { 0x0428, 0, 0x00000000, 0x00000001 },
3297 { 0x0450, 0, 0x00000000, 0x0000ffff },
3298 { 0x0454, 0, 0x00000000, 0xffffffff },
3299 { 0x0458, 0, 0x00000000, 0xffffffff },
3300
3301 { 0x0808, 0, 0x00000000, 0xffffffff },
3302 { 0x0854, 0, 0x00000000, 0xffffffff },
3303 { 0x0868, 0, 0x00000000, 0x77777777 },
3304 { 0x086c, 0, 0x00000000, 0x77777777 },
3305 { 0x0870, 0, 0x00000000, 0x77777777 },
3306 { 0x0874, 0, 0x00000000, 0x77777777 },
3307
3308 { 0x0c00, 0, 0x00000000, 0x00000001 },
3309 { 0x0c04, 0, 0x00000000, 0x03ff0001 },
3310 { 0x0c08, 0, 0x0f0ff073, 0x00000000 },
3311 { 0x0c0c, 0, 0x00ffffff, 0x00000000 },
3312 { 0x0c30, 0, 0x00000000, 0xffffffff },
3313 { 0x0c34, 0, 0x00000000, 0xffffffff },
3314 { 0x0c38, 0, 0x00000000, 0xffffffff },
3315 { 0x0c3c, 0, 0x00000000, 0xffffffff },
3316 { 0x0c40, 0, 0x00000000, 0xffffffff },
3317 { 0x0c44, 0, 0x00000000, 0xffffffff },
3318 { 0x0c48, 0, 0x00000000, 0x0007ffff },
3319 { 0x0c4c, 0, 0x00000000, 0xffffffff },
3320 { 0x0c50, 0, 0x00000000, 0xffffffff },
3321 { 0x0c54, 0, 0x00000000, 0xffffffff },
3322 { 0x0c58, 0, 0x00000000, 0xffffffff },
3323 { 0x0c5c, 0, 0x00000000, 0xffffffff },
3324 { 0x0c60, 0, 0x00000000, 0xffffffff },
3325 { 0x0c64, 0, 0x00000000, 0xffffffff },
3326 { 0x0c68, 0, 0x00000000, 0xffffffff },
3327 { 0x0c6c, 0, 0x00000000, 0xffffffff },
3328 { 0x0c70, 0, 0x00000000, 0xffffffff },
3329 { 0x0c74, 0, 0x00000000, 0xffffffff },
3330 { 0x0c78, 0, 0x00000000, 0xffffffff },
3331 { 0x0c7c, 0, 0x00000000, 0xffffffff },
3332 { 0x0c80, 0, 0x00000000, 0xffffffff },
3333 { 0x0c84, 0, 0x00000000, 0xffffffff },
3334 { 0x0c88, 0, 0x00000000, 0xffffffff },
3335 { 0x0c8c, 0, 0x00000000, 0xffffffff },
3336 { 0x0c90, 0, 0x00000000, 0xffffffff },
3337 { 0x0c94, 0, 0x00000000, 0xffffffff },
3338 { 0x0c98, 0, 0x00000000, 0xffffffff },
3339 { 0x0c9c, 0, 0x00000000, 0xffffffff },
3340 { 0x0ca0, 0, 0x00000000, 0xffffffff },
3341 { 0x0ca4, 0, 0x00000000, 0xffffffff },
3342 { 0x0ca8, 0, 0x00000000, 0x0007ffff },
3343 { 0x0cac, 0, 0x00000000, 0xffffffff },
3344 { 0x0cb0, 0, 0x00000000, 0xffffffff },
3345 { 0x0cb4, 0, 0x00000000, 0xffffffff },
3346 { 0x0cb8, 0, 0x00000000, 0xffffffff },
3347 { 0x0cbc, 0, 0x00000000, 0xffffffff },
3348 { 0x0cc0, 0, 0x00000000, 0xffffffff },
3349 { 0x0cc4, 0, 0x00000000, 0xffffffff },
3350 { 0x0cc8, 0, 0x00000000, 0xffffffff },
3351 { 0x0ccc, 0, 0x00000000, 0xffffffff },
3352 { 0x0cd0, 0, 0x00000000, 0xffffffff },
3353 { 0x0cd4, 0, 0x00000000, 0xffffffff },
3354 { 0x0cd8, 0, 0x00000000, 0xffffffff },
3355 { 0x0cdc, 0, 0x00000000, 0xffffffff },
3356 { 0x0ce0, 0, 0x00000000, 0xffffffff },
3357 { 0x0ce4, 0, 0x00000000, 0xffffffff },
3358 { 0x0ce8, 0, 0x00000000, 0xffffffff },
3359 { 0x0cec, 0, 0x00000000, 0xffffffff },
3360 { 0x0cf0, 0, 0x00000000, 0xffffffff },
3361 { 0x0cf4, 0, 0x00000000, 0xffffffff },
3362 { 0x0cf8, 0, 0x00000000, 0xffffffff },
3363 { 0x0cfc, 0, 0x00000000, 0xffffffff },
3364 { 0x0d00, 0, 0x00000000, 0xffffffff },
3365 { 0x0d04, 0, 0x00000000, 0xffffffff },
3366
3367 { 0x1000, 0, 0x00000000, 0x00000001 },
3368 { 0x1004, 0, 0x00000000, 0x000f0001 },
3369 { 0x1044, 0, 0x00000000, 0xffc003ff },
3370 { 0x1080, 0, 0x00000000, 0x0001ffff },
3371 { 0x1084, 0, 0x00000000, 0xffffffff },
3372 { 0x1088, 0, 0x00000000, 0xffffffff },
3373 { 0x108c, 0, 0x00000000, 0xffffffff },
3374 { 0x1090, 0, 0x00000000, 0xffffffff },
3375 { 0x1094, 0, 0x00000000, 0xffffffff },
3376 { 0x1098, 0, 0x00000000, 0xffffffff },
3377 { 0x109c, 0, 0x00000000, 0xffffffff },
3378 { 0x10a0, 0, 0x00000000, 0xffffffff },
3379
3380 { 0x1408, 0, 0x01c00800, 0x00000000 },
3381 { 0x149c, 0, 0x8000ffff, 0x00000000 },
3382 { 0x14a8, 0, 0x00000000, 0x000001ff },
5b0c76ad 3383 { 0x14ac, 0, 0x0fffffff, 0x10000000 },
b6016b76
MC		 3384 { 0x14b0, 0, 0x00000002, 0x00000001 },
3385 { 0x14b8, 0, 0x00000000, 0x00000000 },
3386 { 0x14c0, 0, 0x00000000, 0x00000009 },
3387 { 0x14c4, 0, 0x00003fff, 0x00000000 },
3388 { 0x14cc, 0, 0x00000000, 0x00000001 },
3389 { 0x14d0, 0, 0xffffffff, 0x00000000 },
3390 { 0x1500, 0, 0x00000000, 0xffffffff },
3391 { 0x1504, 0, 0x00000000, 0xffffffff },
3392 { 0x1508, 0, 0x00000000, 0xffffffff },
3393 { 0x150c, 0, 0x00000000, 0xffffffff },
3394 { 0x1510, 0, 0x00000000, 0xffffffff },
3395 { 0x1514, 0, 0x00000000, 0xffffffff },
3396 { 0x1518, 0, 0x00000000, 0xffffffff },
3397 { 0x151c, 0, 0x00000000, 0xffffffff },
3398 { 0x1520, 0, 0x00000000, 0xffffffff },
3399 { 0x1524, 0, 0x00000000, 0xffffffff },
3400 { 0x1528, 0, 0x00000000, 0xffffffff },
3401 { 0x152c, 0, 0x00000000, 0xffffffff },
3402 { 0x1530, 0, 0x00000000, 0xffffffff },
3403 { 0x1534, 0, 0x00000000, 0xffffffff },
3404 { 0x1538, 0, 0x00000000, 0xffffffff },
3405 { 0x153c, 0, 0x00000000, 0xffffffff },
3406 { 0x1540, 0, 0x00000000, 0xffffffff },
3407 { 0x1544, 0, 0x00000000, 0xffffffff },
3408 { 0x1548, 0, 0x00000000, 0xffffffff },
3409 { 0x154c, 0, 0x00000000, 0xffffffff },
3410 { 0x1550, 0, 0x00000000, 0xffffffff },
3411 { 0x1554, 0, 0x00000000, 0xffffffff },
3412 { 0x1558, 0, 0x00000000, 0xffffffff },
3413 { 0x1600, 0, 0x00000000, 0xffffffff },
3414 { 0x1604, 0, 0x00000000, 0xffffffff },
3415 { 0x1608, 0, 0x00000000, 0xffffffff },
3416 { 0x160c, 0, 0x00000000, 0xffffffff },
3417 { 0x1610, 0, 0x00000000, 0xffffffff },
3418 { 0x1614, 0, 0x00000000, 0xffffffff },
3419 { 0x1618, 0, 0x00000000, 0xffffffff },
3420 { 0x161c, 0, 0x00000000, 0xffffffff },
3421 { 0x1620, 0, 0x00000000, 0xffffffff },
3422 { 0x1624, 0, 0x00000000, 0xffffffff },
3423 { 0x1628, 0, 0x00000000, 0xffffffff },
3424 { 0x162c, 0, 0x00000000, 0xffffffff },
3425 { 0x1630, 0, 0x00000000, 0xffffffff },
3426 { 0x1634, 0, 0x00000000, 0xffffffff },
3427 { 0x1638, 0, 0x00000000, 0xffffffff },
3428 { 0x163c, 0, 0x00000000, 0xffffffff },
3429 { 0x1640, 0, 0x00000000, 0xffffffff },
3430 { 0x1644, 0, 0x00000000, 0xffffffff },
3431 { 0x1648, 0, 0x00000000, 0xffffffff },
3432 { 0x164c, 0, 0x00000000, 0xffffffff },
3433 { 0x1650, 0, 0x00000000, 0xffffffff },
3434 { 0x1654, 0, 0x00000000, 0xffffffff },
3435
3436 { 0x1800, 0, 0x00000000, 0x00000001 },
3437 { 0x1804, 0, 0x00000000, 0x00000003 },
3438 { 0x1840, 0, 0x00000000, 0xffffffff },
3439 { 0x1844, 0, 0x00000000, 0xffffffff },
3440 { 0x1848, 0, 0x00000000, 0xffffffff },
3441 { 0x184c, 0, 0x00000000, 0xffffffff },
3442 { 0x1850, 0, 0x00000000, 0xffffffff },
3443 { 0x1900, 0, 0x7ffbffff, 0x00000000 },
3444 { 0x1904, 0, 0xffffffff, 0x00000000 },
3445 { 0x190c, 0, 0xffffffff, 0x00000000 },
3446 { 0x1914, 0, 0xffffffff, 0x00000000 },
3447 { 0x191c, 0, 0xffffffff, 0x00000000 },
3448 { 0x1924, 0, 0xffffffff, 0x00000000 },
3449 { 0x192c, 0, 0xffffffff, 0x00000000 },
3450 { 0x1934, 0, 0xffffffff, 0x00000000 },
3451 { 0x193c, 0, 0xffffffff, 0x00000000 },
3452 { 0x1944, 0, 0xffffffff, 0x00000000 },
3453 { 0x194c, 0, 0xffffffff, 0x00000000 },
3454 { 0x1954, 0, 0xffffffff, 0x00000000 },
3455 { 0x195c, 0, 0xffffffff, 0x00000000 },
3456 { 0x1964, 0, 0xffffffff, 0x00000000 },
3457 { 0x196c, 0, 0xffffffff, 0x00000000 },
3458 { 0x1974, 0, 0xffffffff, 0x00000000 },
3459 { 0x197c, 0, 0xffffffff, 0x00000000 },
3460 { 0x1980, 0, 0x0700ffff, 0x00000000 },
3461
3462 { 0x1c00, 0, 0x00000000, 0x00000001 },
3463 { 0x1c04, 0, 0x00000000, 0x00000003 },
3464 { 0x1c08, 0, 0x0000000f, 0x00000000 },
3465 { 0x1c40, 0, 0x00000000, 0xffffffff },
3466 { 0x1c44, 0, 0x00000000, 0xffffffff },
3467 { 0x1c48, 0, 0x00000000, 0xffffffff },
3468 { 0x1c4c, 0, 0x00000000, 0xffffffff },
3469 { 0x1c50, 0, 0x00000000, 0xffffffff },
3470 { 0x1d00, 0, 0x7ffbffff, 0x00000000 },
3471 { 0x1d04, 0, 0xffffffff, 0x00000000 },
3472 { 0x1d0c, 0, 0xffffffff, 0x00000000 },
3473 { 0x1d14, 0, 0xffffffff, 0x00000000 },
3474 { 0x1d1c, 0, 0xffffffff, 0x00000000 },
3475 { 0x1d24, 0, 0xffffffff, 0x00000000 },
3476 { 0x1d2c, 0, 0xffffffff, 0x00000000 },
3477 { 0x1d34, 0, 0xffffffff, 0x00000000 },
3478 { 0x1d3c, 0, 0xffffffff, 0x00000000 },
3479 { 0x1d44, 0, 0xffffffff, 0x00000000 },
3480 { 0x1d4c, 0, 0xffffffff, 0x00000000 },
3481 { 0x1d54, 0, 0xffffffff, 0x00000000 },
3482 { 0x1d5c, 0, 0xffffffff, 0x00000000 },
3483 { 0x1d64, 0, 0xffffffff, 0x00000000 },
3484 { 0x1d6c, 0, 0xffffffff, 0x00000000 },
3485 { 0x1d74, 0, 0xffffffff, 0x00000000 },
3486 { 0x1d7c, 0, 0xffffffff, 0x00000000 },
3487 { 0x1d80, 0, 0x0700ffff, 0x00000000 },
3488
3489 { 0x2004, 0, 0x00000000, 0x0337000f },
3490 { 0x2008, 0, 0xffffffff, 0x00000000 },
3491 { 0x200c, 0, 0xffffffff, 0x00000000 },
3492 { 0x2010, 0, 0xffffffff, 0x00000000 },
3493 { 0x2014, 0, 0x801fff80, 0x00000000 },
3494 { 0x2018, 0, 0x000003ff, 0x00000000 },
3495
3496 { 0x2800, 0, 0x00000000, 0x00000001 },
3497 { 0x2804, 0, 0x00000000, 0x00003f01 },
3498 { 0x2808, 0, 0x0f3f3f03, 0x00000000 },
3499 { 0x2810, 0, 0xffff0000, 0x00000000 },
3500 { 0x2814, 0, 0xffff0000, 0x00000000 },
3501 { 0x2818, 0, 0xffff0000, 0x00000000 },
3502 { 0x281c, 0, 0xffff0000, 0x00000000 },
3503 { 0x2834, 0, 0xffffffff, 0x00000000 },
3504 { 0x2840, 0, 0x00000000, 0xffffffff },
3505 { 0x2844, 0, 0x00000000, 0xffffffff },
3506 { 0x2848, 0, 0xffffffff, 0x00000000 },
3507 { 0x284c, 0, 0xf800f800, 0x07ff07ff },
3508
3509 { 0x2c00, 0, 0x00000000, 0x00000011 },
3510 { 0x2c04, 0, 0x00000000, 0x00030007 },
3511
3512 { 0x3000, 0, 0x00000000, 0x00000001 },
3513 { 0x3004, 0, 0x00000000, 0x007007ff },
3514 { 0x3008, 0, 0x00000003, 0x00000000 },
3515 { 0x300c, 0, 0xffffffff, 0x00000000 },
3516 { 0x3010, 0, 0xffffffff, 0x00000000 },
3517 { 0x3014, 0, 0xffffffff, 0x00000000 },
3518 { 0x3034, 0, 0xffffffff, 0x00000000 },
3519 { 0x3038, 0, 0xffffffff, 0x00000000 },
3520 { 0x3050, 0, 0x00000001, 0x00000000 },
3521
3522 { 0x3c00, 0, 0x00000000, 0x00000001 },
3523 { 0x3c04, 0, 0x00000000, 0x00070000 },
3524 { 0x3c08, 0, 0x00007f71, 0x07f00000 },
3525 { 0x3c0c, 0, 0x1f3ffffc, 0x00000000 },
3526 { 0x3c10, 0, 0xffffffff, 0x00000000 },
3527 { 0x3c14, 0, 0x00000000, 0xffffffff },
3528 { 0x3c18, 0, 0x00000000, 0xffffffff },
3529 { 0x3c1c, 0, 0xfffff000, 0x00000000 },
3530 { 0x3c20, 0, 0xffffff00, 0x00000000 },
3531 { 0x3c24, 0, 0xffffffff, 0x00000000 },
3532 { 0x3c28, 0, 0xffffffff, 0x00000000 },
3533 { 0x3c2c, 0, 0xffffffff, 0x00000000 },
3534 { 0x3c30, 0, 0xffffffff, 0x00000000 },
3535 { 0x3c34, 0, 0xffffffff, 0x00000000 },
3536 { 0x3c38, 0, 0xffffffff, 0x00000000 },
3537 { 0x3c3c, 0, 0xffffffff, 0x00000000 },
3538 { 0x3c40, 0, 0xffffffff, 0x00000000 },
3539 { 0x3c44, 0, 0xffffffff, 0x00000000 },
3540 { 0x3c48, 0, 0xffffffff, 0x00000000 },
3541 { 0x3c4c, 0, 0xffffffff, 0x00000000 },
3542 { 0x3c50, 0, 0xffffffff, 0x00000000 },
3543 { 0x3c54, 0, 0xffffffff, 0x00000000 },
3544 { 0x3c58, 0, 0xffffffff, 0x00000000 },
3545 { 0x3c5c, 0, 0xffffffff, 0x00000000 },
3546 { 0x3c60, 0, 0xffffffff, 0x00000000 },
3547 { 0x3c64, 0, 0xffffffff, 0x00000000 },
3548 { 0x3c68, 0, 0xffffffff, 0x00000000 },
3549 { 0x3c6c, 0, 0xffffffff, 0x00000000 },
3550 { 0x3c70, 0, 0xffffffff, 0x00000000 },
3551 { 0x3c74, 0, 0x0000003f, 0x00000000 },
3552 { 0x3c78, 0, 0x00000000, 0x00000000 },
3553 { 0x3c7c, 0, 0x00000000, 0x00000000 },
3554 { 0x3c80, 0, 0x3fffffff, 0x00000000 },
3555 { 0x3c84, 0, 0x0000003f, 0x00000000 },
3556 { 0x3c88, 0, 0x00000000, 0xffffffff },
3557 { 0x3c8c, 0, 0x00000000, 0xffffffff },
3558
3559 { 0x4000, 0, 0x00000000, 0x00000001 },
3560 { 0x4004, 0, 0x00000000, 0x00030000 },
3561 { 0x4008, 0, 0x00000ff0, 0x00000000 },
3562 { 0x400c, 0, 0xffffffff, 0x00000000 },
3563 { 0x4088, 0, 0x00000000, 0x00070303 },
3564
3565 { 0x4400, 0, 0x00000000, 0x00000001 },
3566 { 0x4404, 0, 0x00000000, 0x00003f01 },
3567 { 0x4408, 0, 0x7fff00ff, 0x00000000 },
3568 { 0x440c, 0, 0xffffffff, 0x00000000 },
3569 { 0x4410, 0, 0xffff, 0x0000 },
3570 { 0x4414, 0, 0xffff, 0x0000 },
3571 { 0x4418, 0, 0xffff, 0x0000 },
3572 { 0x441c, 0, 0xffff, 0x0000 },
3573 { 0x4428, 0, 0xffffffff, 0x00000000 },
3574 { 0x442c, 0, 0xffffffff, 0x00000000 },
3575 { 0x4430, 0, 0xffffffff, 0x00000000 },
3576 { 0x4434, 0, 0xffffffff, 0x00000000 },
3577 { 0x4438, 0, 0xffffffff, 0x00000000 },
3578 { 0x443c, 0, 0xffffffff, 0x00000000 },
3579 { 0x4440, 0, 0xffffffff, 0x00000000 },
3580 { 0x4444, 0, 0xffffffff, 0x00000000 },
3581
3582 { 0x4c00, 0, 0x00000000, 0x00000001 },
3583 { 0x4c04, 0, 0x00000000, 0x0000003f },
3584 { 0x4c08, 0, 0xffffffff, 0x00000000 },
3585 { 0x4c0c, 0, 0x0007fc00, 0x00000000 },
3586 { 0x4c10, 0, 0x80003fe0, 0x00000000 },
3587 { 0x4c14, 0, 0xffffffff, 0x00000000 },
3588 { 0x4c44, 0, 0x00000000, 0x9fff9fff },
3589 { 0x4c48, 0, 0x00000000, 0xb3009fff },
3590 { 0x4c4c, 0, 0x00000000, 0x77f33b30 },
3591 { 0x4c50, 0, 0x00000000, 0xffffffff },
3592
3593 { 0x5004, 0, 0x00000000, 0x0000007f },
3594 { 0x5008, 0, 0x0f0007ff, 0x00000000 },
3595 { 0x500c, 0, 0xf800f800, 0x07ff07ff },
3596
3597 { 0x5400, 0, 0x00000008, 0x00000001 },
3598 { 0x5404, 0, 0x00000000, 0x0000003f },
3599 { 0x5408, 0, 0x0000001f, 0x00000000 },
3600 { 0x540c, 0, 0xffffffff, 0x00000000 },
3601 { 0x5410, 0, 0xffffffff, 0x00000000 },
3602 { 0x5414, 0, 0x0000ffff, 0x00000000 },
3603 { 0x5418, 0, 0x0000ffff, 0x00000000 },
3604 { 0x541c, 0, 0x0000ffff, 0x00000000 },
3605 { 0x5420, 0, 0x0000ffff, 0x00000000 },
3606 { 0x5428, 0, 0x000000ff, 0x00000000 },
3607 { 0x542c, 0, 0xff00ffff, 0x00000000 },
3608 { 0x5430, 0, 0x001fff80, 0x00000000 },
3609 { 0x5438, 0, 0xffffffff, 0x00000000 },
3610 { 0x543c, 0, 0xffffffff, 0x00000000 },
3611 { 0x5440, 0, 0xf800f800, 0x07ff07ff },
3612
3613 { 0x5c00, 0, 0x00000000, 0x00000001 },
3614 { 0x5c04, 0, 0x00000000, 0x0003000f },
3615 { 0x5c08, 0, 0x00000003, 0x00000000 },
3616 { 0x5c0c, 0, 0x0000fff8, 0x00000000 },
3617 { 0x5c10, 0, 0x00000000, 0xffffffff },
3618 { 0x5c80, 0, 0x00000000, 0x0f7113f1 },
3619 { 0x5c84, 0, 0x00000000, 0x0000f333 },
3620 { 0x5c88, 0, 0x00000000, 0x00077373 },
3621 { 0x5c8c, 0, 0x00000000, 0x0007f737 },
3622
3623 { 0x6808, 0, 0x0000ff7f, 0x00000000 },
3624 { 0x680c, 0, 0xffffffff, 0x00000000 },
3625 { 0x6810, 0, 0xffffffff, 0x00000000 },
3626 { 0x6814, 0, 0xffffffff, 0x00000000 },
3627 { 0x6818, 0, 0xffffffff, 0x00000000 },
3628 { 0x681c, 0, 0xffffffff, 0x00000000 },
3629 { 0x6820, 0, 0x00ff00ff, 0x00000000 },
3630 { 0x6824, 0, 0x00ff00ff, 0x00000000 },
3631 { 0x6828, 0, 0x00ff00ff, 0x00000000 },
3632 { 0x682c, 0, 0x03ff03ff, 0x00000000 },
3633 { 0x6830, 0, 0x03ff03ff, 0x00000000 },
3634 { 0x6834, 0, 0x03ff03ff, 0x00000000 },
3635 { 0x6838, 0, 0x03ff03ff, 0x00000000 },
3636 { 0x683c, 0, 0x0000ffff, 0x00000000 },
3637 { 0x6840, 0, 0x00000ff0, 0x00000000 },
3638 { 0x6844, 0, 0x00ffff00, 0x00000000 },
3639 { 0x684c, 0, 0xffffffff, 0x00000000 },
3640 { 0x6850, 0, 0x7f7f7f7f, 0x00000000 },
3641 { 0x6854, 0, 0x7f7f7f7f, 0x00000000 },
3642 { 0x6858, 0, 0x7f7f7f7f, 0x00000000 },
3643 { 0x685c, 0, 0x7f7f7f7f, 0x00000000 },
3644 { 0x6908, 0, 0x00000000, 0x0001ff0f },
3645 { 0x690c, 0, 0x00000000, 0x0ffe00f0 },
3646
3647 { 0xffff, 0, 0x00000000, 0x00000000 },
3648 };
3649
3650 ret = 0;
3651 for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
3652 u32 offset, rw_mask, ro_mask, save_val, val;
3653
3654 offset = (u32) reg_tbl[i].offset;
3655 rw_mask = reg_tbl[i].rw_mask;
3656 ro_mask = reg_tbl[i].ro_mask;
3657
14ab9b86 3658 save_val = readl(bp->regview + offset);
b6016b76 3659
14ab9b86 3660 writel(0, bp->regview + offset);
b6016b76 3661
14ab9b86 3662 val = readl(bp->regview + offset);
b6016b76
MC		 3663 if ((val & rw_mask) != 0) {
3664 goto reg_test_err;
3665 }
3666
3667 if ((val & ro_mask) != (save_val & ro_mask)) {
3668 goto reg_test_err;
3669 }
3670
14ab9b86 3671 writel(0xffffffff, bp->regview + offset);
b6016b76 3672
14ab9b86 3673 val = readl(bp->regview + offset);
b6016b76
MC		 3674 if ((val & rw_mask) != rw_mask) {
3675 goto reg_test_err;
3676 }
3677
3678 if ((val & ro_mask) != (save_val & ro_mask)) {
3679 goto reg_test_err;
3680 }
3681
14ab9b86 3682 writel(save_val, bp->regview + offset);
b6016b76
MC		 3683 continue;
3684
3685reg_test_err:
14ab9b86 3686 writel(save_val, bp->regview + offset);
b6016b76
MC		 3687 ret = -ENODEV;
3688 break;
3689 }
3690 return ret;
3691}
3692
3693static int
3694bnx2_do_mem_test(struct bnx2 *bp, u32 start, u32 size)
3695{
3696 static u32 test_pattern[] = { 0x00000000, 0xffffffff, 0x55555555,
3697 0xaaaaaaaa , 0xaa55aa55, 0x55aa55aa };
3698 int i;
3699
3700 for (i = 0; i < sizeof(test_pattern) / 4; i++) {
3701 u32 offset;
3702
3703 for (offset = 0; offset < size; offset += 4) {
3704
3705 REG_WR_IND(bp, start + offset, test_pattern[i]);
3706
3707 if (REG_RD_IND(bp, start + offset) !=
3708 test_pattern[i]) {
3709 return -ENODEV;
3710 }
3711 }
3712 }
3713 return 0;
3714}
3715
3716static int
3717bnx2_test_memory(struct bnx2 *bp)
3718{
3719 int ret = 0;
3720 int i;
3721 static struct {
3722 u32 offset;
3723 u32 len;
3724 } mem_tbl[] = {
3725 { 0x60000, 0x4000 },
5b0c76ad 3726 { 0xa0000, 0x3000 },
b6016b76
MC		 3727 { 0xe0000, 0x4000 },
3728 { 0x120000, 0x4000 },
3729 { 0x1a0000, 0x4000 },
3730 { 0x160000, 0x4000 },
3731 { 0xffffffff, 0 },
3732 };
3733
3734 for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
3735 if ((ret = bnx2_do_mem_test(bp, mem_tbl[i].offset,
3736 mem_tbl[i].len)) != 0) {
3737 return ret;
3738 }
3739 }
3740
3741 return ret;
3742}
3743
3744static int
3745bnx2_test_loopback(struct bnx2 *bp)
3746{
3747 unsigned int pkt_size, num_pkts, i;
3748 struct sk_buff *skb, *rx_skb;
3749 unsigned char *packet;
3750 u16 rx_start_idx, rx_idx, send_idx;
3751 u32 send_bseq, val;
3752 dma_addr_t map;
3753 struct tx_bd *txbd;
3754 struct sw_bd *rx_buf;
3755 struct l2_fhdr *rx_hdr;
3756 int ret = -ENODEV;
3757
3758 if (!netif_running(bp->dev))
3759 return -ENODEV;
3760
3761 bp->loopback = MAC_LOOPBACK;
3762 bnx2_reset_nic(bp, BNX2_DRV_MSG_CODE_DIAG);
3763 bnx2_set_mac_loopback(bp);
3764
3765 pkt_size = 1514;
3766 skb = dev_alloc_skb(pkt_size);
3767 packet = skb_put(skb, pkt_size);
3768 memcpy(packet, bp->mac_addr, 6);
3769 memset(packet + 6, 0x0, 8);
3770 for (i = 14; i < pkt_size; i++)
3771 packet[i] = (unsigned char) (i & 0xff);
3772
3773 map = pci_map_single(bp->pdev, skb->data, pkt_size,
3774 PCI_DMA_TODEVICE);
3775
3776 val = REG_RD(bp, BNX2_HC_COMMAND);
3777 REG_WR(bp, BNX2_HC_COMMAND, val | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
3778 REG_RD(bp, BNX2_HC_COMMAND);
3779
3780 udelay(5);
3781 rx_start_idx = bp->status_blk->status_rx_quick_consumer_index0;
3782
3783 send_idx = 0;
3784 send_bseq = 0;
3785 num_pkts = 0;
3786
3787 txbd = &bp->tx_desc_ring[send_idx];
3788
3789 txbd->tx_bd_haddr_hi = (u64) map >> 32;
3790 txbd->tx_bd_haddr_lo = (u64) map & 0xffffffff;
3791 txbd->tx_bd_mss_nbytes = pkt_size;
3792 txbd->tx_bd_vlan_tag_flags = TX_BD_FLAGS_START | TX_BD_FLAGS_END;
3793
3794 num_pkts++;
3795 send_idx = NEXT_TX_BD(send_idx);
3796
3797 send_bseq += pkt_size;
3798
3799 REG_WR16(bp, MB_TX_CID_ADDR + BNX2_L2CTX_TX_HOST_BIDX, send_idx);
3800 REG_WR(bp, MB_TX_CID_ADDR + BNX2_L2CTX_TX_HOST_BSEQ, send_bseq);
3801
3802
3803 udelay(100);
3804
3805 val = REG_RD(bp, BNX2_HC_COMMAND);
3806 REG_WR(bp, BNX2_HC_COMMAND, val | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
3807 REG_RD(bp, BNX2_HC_COMMAND);
3808
3809 udelay(5);
3810
3811 pci_unmap_single(bp->pdev, map, pkt_size, PCI_DMA_TODEVICE);
3812 dev_kfree_skb_irq(skb);
3813
3814 if (bp->status_blk->status_tx_quick_consumer_index0 != send_idx) {
3815 goto loopback_test_done;
3816 }
3817
3818 rx_idx = bp->status_blk->status_rx_quick_consumer_index0;
3819 if (rx_idx != rx_start_idx + num_pkts) {
3820 goto loopback_test_done;
3821 }
3822
3823 rx_buf = &bp->rx_buf_ring[rx_start_idx];
3824 rx_skb = rx_buf->skb;
3825
3826 rx_hdr = (struct l2_fhdr *) rx_skb->data;
3827 skb_reserve(rx_skb, bp->rx_offset);
3828
3829 pci_dma_sync_single_for_cpu(bp->pdev,
3830 pci_unmap_addr(rx_buf, mapping),
3831 bp->rx_buf_size, PCI_DMA_FROMDEVICE);
3832
3833 if (rx_hdr->l2_fhdr_errors &
3834 (L2_FHDR_ERRORS_BAD_CRC |
3835 L2_FHDR_ERRORS_PHY_DECODE |
3836 L2_FHDR_ERRORS_ALIGNMENT |
3837 L2_FHDR_ERRORS_TOO_SHORT |
3838 L2_FHDR_ERRORS_GIANT_FRAME)) {
3839
3840 goto loopback_test_done;
3841 }
3842
3843 if ((rx_hdr->l2_fhdr_pkt_len - 4) != pkt_size) {
3844 goto loopback_test_done;
3845 }
3846
3847 for (i = 14; i < pkt_size; i++) {
3848 if (*(rx_skb->data + i) != (unsigned char) (i & 0xff)) {
3849 goto loopback_test_done;
3850 }
3851 }
3852
3853 ret = 0;
3854
3855loopback_test_done:
3856 bp->loopback = 0;
3857 return ret;
3858}
3859
3860#define NVRAM_SIZE 0x200
3861#define CRC32_RESIDUAL 0xdebb20e3
3862
3863static int
3864bnx2_test_nvram(struct bnx2 *bp)
3865{
3866 u32 buf[NVRAM_SIZE / 4];
3867 u8 *data = (u8 *) buf;
3868 int rc = 0;
3869 u32 magic, csum;
3870
3871 if ((rc = bnx2_nvram_read(bp, 0, data, 4)) != 0)
3872 goto test_nvram_done;
3873
3874 magic = be32_to_cpu(buf[0]);
3875 if (magic != 0x669955aa) {
3876 rc = -ENODEV;
3877 goto test_nvram_done;
3878 }
3879
3880 if ((rc = bnx2_nvram_read(bp, 0x100, data, NVRAM_SIZE)) != 0)
3881 goto test_nvram_done;
3882
3883 csum = ether_crc_le(0x100, data);
3884 if (csum != CRC32_RESIDUAL) {
3885 rc = -ENODEV;
3886 goto test_nvram_done;
3887 }
3888
3889 csum = ether_crc_le(0x100, data + 0x100);
3890 if (csum != CRC32_RESIDUAL) {
3891 rc = -ENODEV;
3892 }
3893
3894test_nvram_done:
3895 return rc;
3896}
3897
3898static int
3899bnx2_test_link(struct bnx2 *bp)
3900{
3901 u32 bmsr;
3902
c770a65c 3903 spin_lock_bh(&bp->phy_lock);
b6016b76
MC		 3904 bnx2_read_phy(bp, MII_BMSR, &bmsr);
3905 bnx2_read_phy(bp, MII_BMSR, &bmsr);
c770a65c 3906 spin_unlock_bh(&bp->phy_lock);
b6016b76
MC		 3907
3908 if (bmsr & BMSR_LSTATUS) {
3909 return 0;
3910 }
3911 return -ENODEV;
3912}
3913
3914static int
3915bnx2_test_intr(struct bnx2 *bp)
3916{
3917 int i;
3918 u32 val;
3919 u16 status_idx;
3920
3921 if (!netif_running(bp->dev))
3922 return -ENODEV;
3923
3924 status_idx = REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD) & 0xffff;
3925
3926 /* This register is not touched during run-time. */
3927 val = REG_RD(bp, BNX2_HC_COMMAND);
3928 REG_WR(bp, BNX2_HC_COMMAND, val | BNX2_HC_COMMAND_COAL_NOW);
3929 REG_RD(bp, BNX2_HC_COMMAND);
3930
3931 for (i = 0; i < 10; i++) {
3932 if ((REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD) & 0xffff) !=
3933 status_idx) {
3934
3935 break;
3936 }
3937
3938 msleep_interruptible(10);
3939 }
3940 if (i < 10)
3941 return 0;
3942
3943 return -ENODEV;
3944}
3945
3946static void
3947bnx2_timer(unsigned long data)
3948{
3949 struct bnx2 *bp = (struct bnx2 *) data;
3950 u32 msg;
3951
cd339a0e
MC		 3952 if (!netif_running(bp->dev))
3953 return;
3954
b6016b76
MC		 3955 if (atomic_read(&bp->intr_sem) != 0)
3956 goto bnx2_restart_timer;
3957
3958 msg = (u32) ++bp->fw_drv_pulse_wr_seq;
3959 REG_WR_IND(bp, HOST_VIEW_SHMEM_BASE + BNX2_DRV_PULSE_MB, msg);
3960
3961 if ((bp->phy_flags & PHY_SERDES_FLAG) &&
3962 (CHIP_NUM(bp) == CHIP_NUM_5706)) {
b6016b76 3963
c770a65c 3964 spin_lock(&bp->phy_lock);
b6016b76
MC		 3965 if (bp->serdes_an_pending) {
3966 bp->serdes_an_pending--;
3967 }
3968 else if ((bp->link_up == 0) && (bp->autoneg & AUTONEG_SPEED)) {
3969 u32 bmcr;
3970
cd339a0e
MC		 3971 bp->current_interval = bp->timer_interval;
3972
b6016b76
MC		 3973 bnx2_read_phy(bp, MII_BMCR, &bmcr);
3974
3975 if (bmcr & BMCR_ANENABLE) {
3976 u32 phy1, phy2;
3977
3978 bnx2_write_phy(bp, 0x1c, 0x7c00);
3979 bnx2_read_phy(bp, 0x1c, &phy1);
3980
3981 bnx2_write_phy(bp, 0x17, 0x0f01);
3982 bnx2_read_phy(bp, 0x15, &phy2);
3983 bnx2_write_phy(bp, 0x17, 0x0f01);
3984 bnx2_read_phy(bp, 0x15, &phy2);
3985
3986 if ((phy1 & 0x10) && /* SIGNAL DETECT */
3987 !(phy2 & 0x20)) { /* no CONFIG */
3988
3989 bmcr &= ~BMCR_ANENABLE;
3990 bmcr |= BMCR_SPEED1000 |
3991 BMCR_FULLDPLX;
3992 bnx2_write_phy(bp, MII_BMCR, bmcr);
3993 bp->phy_flags |=
3994 PHY_PARALLEL_DETECT_FLAG;
3995 }
3996 }
3997 }
3998 else if ((bp->link_up) && (bp->autoneg & AUTONEG_SPEED) &&
3999 (bp->phy_flags & PHY_PARALLEL_DETECT_FLAG)) {
4000 u32 phy2;
4001
4002 bnx2_write_phy(bp, 0x17, 0x0f01);
4003 bnx2_read_phy(bp, 0x15, &phy2);
4004 if (phy2 & 0x20) {
4005 u32 bmcr;
4006
4007 bnx2_read_phy(bp, MII_BMCR, &bmcr);
4008 bmcr |= BMCR_ANENABLE;
4009 bnx2_write_phy(bp, MII_BMCR, bmcr);
4010
4011 bp->phy_flags &= ~PHY_PARALLEL_DETECT_FLAG;
4012
4013 }
4014 }
cd339a0e
MC		 4015 else
4016 bp->current_interval = bp->timer_interval;
b6016b76 4017
c770a65c 4018 spin_unlock(&bp->phy_lock);
b6016b76
MC		 4019 }
4020
4021bnx2_restart_timer:
cd339a0e 4022 mod_timer(&bp->timer, jiffies + bp->current_interval);
b6016b76
MC		 4023}
4024
4025/* Called with rtnl_lock */
4026static int
4027bnx2_open(struct net_device *dev)
4028{
4029 struct bnx2 *bp = dev->priv;
4030 int rc;
4031
829ca9a3 4032 bnx2_set_power_state(bp, PCI_D0);
b6016b76
MC		 4033 bnx2_disable_int(bp);
4034
4035 rc = bnx2_alloc_mem(bp);
4036 if (rc)
4037 return rc;
4038
4039 if ((CHIP_ID(bp) != CHIP_ID_5706_A0) &&
4040 (CHIP_ID(bp) != CHIP_ID_5706_A1) &&
4041 !disable_msi) {
4042
4043 if (pci_enable_msi(bp->pdev) == 0) {
4044 bp->flags |= USING_MSI_FLAG;
4045 rc = request_irq(bp->pdev->irq, bnx2_msi, 0, dev->name,
4046 dev);
4047 }
4048 else {
4049 rc = request_irq(bp->pdev->irq, bnx2_interrupt,
4050 SA_SHIRQ, dev->name, dev);
4051 }
4052 }
4053 else {
4054 rc = request_irq(bp->pdev->irq, bnx2_interrupt, SA_SHIRQ,
4055 dev->name, dev);
4056 }
4057 if (rc) {
4058 bnx2_free_mem(bp);
4059 return rc;
4060 }
4061
4062 rc = bnx2_init_nic(bp);
4063
4064 if (rc) {
4065 free_irq(bp->pdev->irq, dev);
4066 if (bp->flags & USING_MSI_FLAG) {
4067 pci_disable_msi(bp->pdev);
4068 bp->flags &= ~USING_MSI_FLAG;
4069 }
4070 bnx2_free_skbs(bp);
4071 bnx2_free_mem(bp);
4072 return rc;
4073 }
4074
cd339a0e 4075 mod_timer(&bp->timer, jiffies + bp->current_interval);
b6016b76
MC		 4076
4077 atomic_set(&bp->intr_sem, 0);
4078
4079 bnx2_enable_int(bp);
4080
4081 if (bp->flags & USING_MSI_FLAG) {
4082 /* Test MSI to make sure it is working
4083 * If MSI test fails, go back to INTx mode
4084 */
4085 if (bnx2_test_intr(bp) != 0) {
4086 printk(KERN_WARNING PFX "%s: No interrupt was generated"
4087 " using MSI, switching to INTx mode. Please"
4088 " report this failure to the PCI maintainer"
4089 " and include system chipset information.\n",
4090 bp->dev->name);
4091
4092 bnx2_disable_int(bp);
4093 free_irq(bp->pdev->irq, dev);
4094 pci_disable_msi(bp->pdev);
4095 bp->flags &= ~USING_MSI_FLAG;
4096
4097 rc = bnx2_init_nic(bp);
4098
4099 if (!rc) {
4100 rc = request_irq(bp->pdev->irq, bnx2_interrupt,
4101 SA_SHIRQ, dev->name, dev);
4102 }
4103 if (rc) {
4104 bnx2_free_skbs(bp);
4105 bnx2_free_mem(bp);
4106 del_timer_sync(&bp->timer);
4107 return rc;
4108 }
4109 bnx2_enable_int(bp);
4110 }
4111 }
4112 if (bp->flags & USING_MSI_FLAG) {
4113 printk(KERN_INFO PFX "%s: using MSI\n", dev->name);
4114 }
4115
4116 netif_start_queue(dev);
4117
4118 return 0;
4119}
4120
4121static void
4122bnx2_reset_task(void *data)
4123{
4124 struct bnx2 *bp = data;
4125
afdc08b9
MC		 4126 if (!netif_running(bp->dev))
4127 return;
4128
4129 bp->in_reset_task = 1;
b6016b76
MC		 4130 bnx2_netif_stop(bp);
4131
4132 bnx2_init_nic(bp);
4133
4134 atomic_set(&bp->intr_sem, 1);
4135 bnx2_netif_start(bp);
afdc08b9 4136 bp->in_reset_task = 0;
b6016b76
MC		 4137}
4138
4139static void
4140bnx2_tx_timeout(struct net_device *dev)
4141{
4142 struct bnx2 *bp = dev->priv;
4143
4144 /* This allows the netif to be shutdown gracefully before resetting */
4145 schedule_work(&bp->reset_task);
4146}
4147
4148#ifdef BCM_VLAN
4149/* Called with rtnl_lock */
4150static void
4151bnx2_vlan_rx_register(struct net_device *dev, struct vlan_group *vlgrp)
4152{
4153 struct bnx2 *bp = dev->priv;
4154
4155 bnx2_netif_stop(bp);
4156
4157 bp->vlgrp = vlgrp;
4158 bnx2_set_rx_mode(dev);
4159
4160 bnx2_netif_start(bp);
4161}
4162
4163/* Called with rtnl_lock */
4164static void
4165bnx2_vlan_rx_kill_vid(struct net_device *dev, uint16_t vid)
4166{
4167 struct bnx2 *bp = dev->priv;
4168
4169 bnx2_netif_stop(bp);
4170
4171 if (bp->vlgrp)
4172 bp->vlgrp->vlan_devices[vid] = NULL;
4173 bnx2_set_rx_mode(dev);
4174
4175 bnx2_netif_start(bp);
4176}
4177#endif
4178
4179/* Called with dev->xmit_lock.
4180 * hard_start_xmit is pseudo-lockless - a lock is only required when
4181 * the tx queue is full. This way, we get the benefit of lockless
4182 * operations most of the time without the complexities to handle
4183 * netif_stop_queue/wake_queue race conditions.
4184 */
4185static int
4186bnx2_start_xmit(struct sk_buff *skb, struct net_device *dev)
4187{
4188 struct bnx2 *bp = dev->priv;
4189 dma_addr_t mapping;
4190 struct tx_bd *txbd;
4191 struct sw_bd *tx_buf;
4192 u32 len, vlan_tag_flags, last_frag, mss;
4193 u16 prod, ring_prod;
4194 int i;
4195
e89bbf10 4196 if (unlikely(bnx2_tx_avail(bp) < (skb_shinfo(skb)->nr_frags + 1))) {
b6016b76
MC		 4197 netif_stop_queue(dev);
4198 printk(KERN_ERR PFX "%s: BUG! Tx ring full when queue awake!\n",
4199 dev->name);
4200
4201 return NETDEV_TX_BUSY;
4202 }
4203 len = skb_headlen(skb);
4204 prod = bp->tx_prod;
4205 ring_prod = TX_RING_IDX(prod);
4206
4207 vlan_tag_flags = 0;
4208 if (skb->ip_summed == CHECKSUM_HW) {
4209 vlan_tag_flags |= TX_BD_FLAGS_TCP_UDP_CKSUM;
4210 }
4211
4212 if (bp->vlgrp != 0 && vlan_tx_tag_present(skb)) {
4213 vlan_tag_flags |=
4214 (TX_BD_FLAGS_VLAN_TAG | (vlan_tx_tag_get(skb) << 16));
4215 }
4216#ifdef BCM_TSO
4217 if ((mss = skb_shinfo(skb)->tso_size) &&
4218 (skb->len > (bp->dev->mtu + ETH_HLEN))) {
4219 u32 tcp_opt_len, ip_tcp_len;
4220
4221 if (skb_header_cloned(skb) &&
4222 pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
4223 dev_kfree_skb(skb);
4224 return NETDEV_TX_OK;
4225 }
4226
4227 tcp_opt_len = ((skb->h.th->doff - 5) * 4);
4228 vlan_tag_flags |= TX_BD_FLAGS_SW_LSO;
4229
4230 tcp_opt_len = 0;
4231 if (skb->h.th->doff > 5) {
4232 tcp_opt_len = (skb->h.th->doff - 5) << 2;
4233 }
4234 ip_tcp_len = (skb->nh.iph->ihl << 2) + sizeof(struct tcphdr);
4235
4236 skb->nh.iph->check = 0;
4237 skb->nh.iph->tot_len = ntohs(mss + ip_tcp_len + tcp_opt_len);
4238 skb->h.th->check =
4239 ~csum_tcpudp_magic(skb->nh.iph->saddr,
4240 skb->nh.iph->daddr,
4241 0, IPPROTO_TCP, 0);
4242
4243 if (tcp_opt_len || (skb->nh.iph->ihl > 5)) {
4244 vlan_tag_flags |= ((skb->nh.iph->ihl - 5) +
4245 (tcp_opt_len >> 2)) << 8;
4246 }
4247 }
4248 else
4249#endif
4250 {
4251 mss = 0;
4252 }
4253
4254 mapping = pci_map_single(bp->pdev, skb->data, len, PCI_DMA_TODEVICE);
4255
4256 tx_buf = &bp->tx_buf_ring[ring_prod];
4257 tx_buf->skb = skb;
4258 pci_unmap_addr_set(tx_buf, mapping, mapping);
4259
4260 txbd = &bp->tx_desc_ring[ring_prod];
4261
4262 txbd->tx_bd_haddr_hi = (u64) mapping >> 32;
4263 txbd->tx_bd_haddr_lo = (u64) mapping & 0xffffffff;
4264 txbd->tx_bd_mss_nbytes = len | (mss << 16);
4265 txbd->tx_bd_vlan_tag_flags = vlan_tag_flags | TX_BD_FLAGS_START;
4266
4267 last_frag = skb_shinfo(skb)->nr_frags;
4268
4269 for (i = 0; i < last_frag; i++) {
4270 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
4271
4272 prod = NEXT_TX_BD(prod);
4273 ring_prod = TX_RING_IDX(prod);
4274 txbd = &bp->tx_desc_ring[ring_prod];
4275
4276 len = frag->size;
4277 mapping = pci_map_page(bp->pdev, frag->page, frag->page_offset,
4278 len, PCI_DMA_TODEVICE);
4279 pci_unmap_addr_set(&bp->tx_buf_ring[ring_prod],
4280 mapping, mapping);
4281
4282 txbd->tx_bd_haddr_hi = (u64) mapping >> 32;
4283 txbd->tx_bd_haddr_lo = (u64) mapping & 0xffffffff;
4284 txbd->tx_bd_mss_nbytes = len | (mss << 16);
4285 txbd->tx_bd_vlan_tag_flags = vlan_tag_flags;
4286
4287 }
4288 txbd->tx_bd_vlan_tag_flags |= TX_BD_FLAGS_END;
4289
4290 prod = NEXT_TX_BD(prod);
4291 bp->tx_prod_bseq += skb->len;
4292
b6016b76
MC		 4293 REG_WR16(bp, MB_TX_CID_ADDR + BNX2_L2CTX_TX_HOST_BIDX, prod);
4294 REG_WR(bp, MB_TX_CID_ADDR + BNX2_L2CTX_TX_HOST_BSEQ, bp->tx_prod_bseq);
4295
4296 mmiowb();
4297
4298 bp->tx_prod = prod;
4299 dev->trans_start = jiffies;
4300
e89bbf10 4301 if (unlikely(bnx2_tx_avail(bp) <= MAX_SKB_FRAGS)) {
c770a65c 4302 spin_lock(&bp->tx_lock);
e89bbf10
MC		 4303 netif_stop_queue(dev);
4304
4305 if (bnx2_tx_avail(bp) > MAX_SKB_FRAGS)
4306 netif_wake_queue(dev);
c770a65c 4307 spin_unlock(&bp->tx_lock);
b6016b76
MC		 4308 }
4309
4310 return NETDEV_TX_OK;
4311}
4312
4313/* Called with rtnl_lock */
4314static int
4315bnx2_close(struct net_device *dev)
4316{
4317 struct bnx2 *bp = dev->priv;
4318 u32 reset_code;
4319
afdc08b9
MC		 4320 /* Calling flush_scheduled_work() may deadlock because
4321 * linkwatch_event() may be on the workqueue and it will try to get
4322 * the rtnl_lock which we are holding.
4323 */
4324 while (bp->in_reset_task)
4325 msleep(1);
4326
b6016b76
MC		 4327 bnx2_netif_stop(bp);
4328 del_timer_sync(&bp->timer);
4329 if (bp->wol)
4330 reset_code = BNX2_DRV_MSG_CODE_SUSPEND_WOL;
4331 else
4332 reset_code = BNX2_DRV_MSG_CODE_SUSPEND_NO_WOL;
4333 bnx2_reset_chip(bp, reset_code);
4334 free_irq(bp->pdev->irq, dev);
4335 if (bp->flags & USING_MSI_FLAG) {
4336 pci_disable_msi(bp->pdev);
4337 bp->flags &= ~USING_MSI_FLAG;
4338 }
4339 bnx2_free_skbs(bp);
4340 bnx2_free_mem(bp);
4341 bp->link_up = 0;
4342 netif_carrier_off(bp->dev);
829ca9a3 4343 bnx2_set_power_state(bp, PCI_D3hot);
b6016b76
MC		 4344 return 0;
4345}
4346
4347#define GET_NET_STATS64(ctr) \
4348 (unsigned long) ((unsigned long) (ctr##_hi) << 32) + \
4349 (unsigned long) (ctr##_lo)
4350
4351#define GET_NET_STATS32(ctr) \
4352 (ctr##_lo)
4353
4354#if (BITS_PER_LONG == 64)
4355#define GET_NET_STATS GET_NET_STATS64
4356#else
4357#define GET_NET_STATS GET_NET_STATS32
4358#endif
4359
4360static struct net_device_stats *
4361bnx2_get_stats(struct net_device *dev)
4362{
4363 struct bnx2 *bp = dev->priv;
4364 struct statistics_block *stats_blk = bp->stats_blk;
4365 struct net_device_stats *net_stats = &bp->net_stats;
4366
4367 if (bp->stats_blk == NULL) {
4368 return net_stats;
4369 }
4370 net_stats->rx_packets =
4371 GET_NET_STATS(stats_blk->stat_IfHCInUcastPkts) +
4372 GET_NET_STATS(stats_blk->stat_IfHCInMulticastPkts) +
4373 GET_NET_STATS(stats_blk->stat_IfHCInBroadcastPkts);
4374
4375 net_stats->tx_packets =
4376 GET_NET_STATS(stats_blk->stat_IfHCOutUcastPkts) +
4377 GET_NET_STATS(stats_blk->stat_IfHCOutMulticastPkts) +
4378 GET_NET_STATS(stats_blk->stat_IfHCOutBroadcastPkts);
4379
4380 net_stats->rx_bytes =
4381 GET_NET_STATS(stats_blk->stat_IfHCInOctets);
4382
4383 net_stats->tx_bytes =
4384 GET_NET_STATS(stats_blk->stat_IfHCOutOctets);
4385
4386 net_stats->multicast =
4387 GET_NET_STATS(stats_blk->stat_IfHCOutMulticastPkts);
4388
4389 net_stats->collisions =
4390 (unsigned long) stats_blk->stat_EtherStatsCollisions;
4391
4392 net_stats->rx_length_errors =
4393 (unsigned long) (stats_blk->stat_EtherStatsUndersizePkts +
4394 stats_blk->stat_EtherStatsOverrsizePkts);
4395
4396 net_stats->rx_over_errors =
4397 (unsigned long) stats_blk->stat_IfInMBUFDiscards;
4398
4399 net_stats->rx_frame_errors =
4400 (unsigned long) stats_blk->stat_Dot3StatsAlignmentErrors;
4401
4402 net_stats->rx_crc_errors =
4403 (unsigned long) stats_blk->stat_Dot3StatsFCSErrors;
4404
4405 net_stats->rx_errors = net_stats->rx_length_errors +
4406 net_stats->rx_over_errors + net_stats->rx_frame_errors +
4407 net_stats->rx_crc_errors;
4408
4409 net_stats->tx_aborted_errors =
4410 (unsigned long) (stats_blk->stat_Dot3StatsExcessiveCollisions +
4411 stats_blk->stat_Dot3StatsLateCollisions);
4412
5b0c76ad
MC		 4413 if ((CHIP_NUM(bp) == CHIP_NUM_5706) ||
4414 (CHIP_ID(bp) == CHIP_ID_5708_A0))
b6016b76
MC		 4415 net_stats->tx_carrier_errors = 0;
4416 else {
4417 net_stats->tx_carrier_errors =
4418 (unsigned long)
4419 stats_blk->stat_Dot3StatsCarrierSenseErrors;
4420 }
4421
4422 net_stats->tx_errors =
4423 (unsigned long)
4424 stats_blk->stat_emac_tx_stat_dot3statsinternalmactransmiterrors
4425 +
4426 net_stats->tx_aborted_errors +
4427 net_stats->tx_carrier_errors;
4428
4429 return net_stats;
4430}
4431
4432/* All ethtool functions called with rtnl_lock */
4433
4434static int
4435bnx2_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
4436{
4437 struct bnx2 *bp = dev->priv;
4438
4439 cmd->supported = SUPPORTED_Autoneg;
4440 if (bp->phy_flags & PHY_SERDES_FLAG) {
4441 cmd->supported |= SUPPORTED_1000baseT_Full |
4442 SUPPORTED_FIBRE;
4443
4444 cmd->port = PORT_FIBRE;
4445 }
4446 else {
4447 cmd->supported |= SUPPORTED_10baseT_Half |
4448 SUPPORTED_10baseT_Full |
4449 SUPPORTED_100baseT_Half |
4450 SUPPORTED_100baseT_Full |
4451 SUPPORTED_1000baseT_Full |
4452 SUPPORTED_TP;
4453
4454 cmd->port = PORT_TP;
4455 }
4456
4457 cmd->advertising = bp->advertising;
4458
4459 if (bp->autoneg & AUTONEG_SPEED) {
4460 cmd->autoneg = AUTONEG_ENABLE;
4461 }
4462 else {
4463 cmd->autoneg = AUTONEG_DISABLE;
4464 }
4465
4466 if (netif_carrier_ok(dev)) {
4467 cmd->speed = bp->line_speed;
4468 cmd->duplex = bp->duplex;
4469 }
4470 else {
4471 cmd->speed = -1;
4472 cmd->duplex = -1;
4473 }
4474
4475 cmd->transceiver = XCVR_INTERNAL;
4476 cmd->phy_address = bp->phy_addr;
4477
4478 return 0;
4479}
4480
4481static int
4482bnx2_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
4483{
4484 struct bnx2 *bp = dev->priv;
4485 u8 autoneg = bp->autoneg;
4486 u8 req_duplex = bp->req_duplex;
4487 u16 req_line_speed = bp->req_line_speed;
4488 u32 advertising = bp->advertising;
4489
4490 if (cmd->autoneg == AUTONEG_ENABLE) {
4491 autoneg |= AUTONEG_SPEED;
4492
4493 cmd->advertising &= ETHTOOL_ALL_COPPER_SPEED;
4494
4495 /* allow advertising 1 speed */
4496 if ((cmd->advertising == ADVERTISED_10baseT_Half) ||
4497 (cmd->advertising == ADVERTISED_10baseT_Full) ||
4498 (cmd->advertising == ADVERTISED_100baseT_Half) ||
4499 (cmd->advertising == ADVERTISED_100baseT_Full)) {
4500
4501 if (bp->phy_flags & PHY_SERDES_FLAG)
4502 return -EINVAL;
4503
4504 advertising = cmd->advertising;
4505
4506 }
4507 else if (cmd->advertising == ADVERTISED_1000baseT_Full) {
4508 advertising = cmd->advertising;
4509 }
4510 else if (cmd->advertising == ADVERTISED_1000baseT_Half) {
4511 return -EINVAL;
4512 }
4513 else {
4514 if (bp->phy_flags & PHY_SERDES_FLAG) {
4515 advertising = ETHTOOL_ALL_FIBRE_SPEED;
4516 }
4517 else {
4518 advertising = ETHTOOL_ALL_COPPER_SPEED;
4519 }
4520 }
4521 advertising |= ADVERTISED_Autoneg;
4522 }
4523 else {
4524 if (bp->phy_flags & PHY_SERDES_FLAG) {
4525 if ((cmd->speed != SPEED_1000) ||
4526 (cmd->duplex != DUPLEX_FULL)) {
4527 return -EINVAL;
4528 }
4529 }
4530 else if (cmd->speed == SPEED_1000) {
4531 return -EINVAL;
4532 }
4533 autoneg &= ~AUTONEG_SPEED;
4534 req_line_speed = cmd->speed;
4535 req_duplex = cmd->duplex;
4536 advertising = 0;
4537 }
4538
4539 bp->autoneg = autoneg;
4540 bp->advertising = advertising;
4541 bp->req_line_speed = req_line_speed;
4542 bp->req_duplex = req_duplex;
4543
c770a65c 4544 spin_lock_bh(&bp->phy_lock);
b6016b76
MC		 4545
4546 bnx2_setup_phy(bp);
4547
c770a65c 4548 spin_unlock_bh(&bp->phy_lock);
b6016b76
MC		 4549
4550 return 0;
4551}
4552
4553static void
4554bnx2_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
4555{
4556 struct bnx2 *bp = dev->priv;
4557
4558 strcpy(info->driver, DRV_MODULE_NAME);
4559 strcpy(info->version, DRV_MODULE_VERSION);
4560 strcpy(info->bus_info, pci_name(bp->pdev));
4561 info->fw_version[0] = ((bp->fw_ver & 0xff000000) >> 24) + '0';
4562 info->fw_version[2] = ((bp->fw_ver & 0xff0000) >> 16) + '0';
4563 info->fw_version[4] = ((bp->fw_ver & 0xff00) >> 8) + '0';
4564 info->fw_version[6] = (bp->fw_ver & 0xff) + '0';
4565 info->fw_version[1] = info->fw_version[3] = info->fw_version[5] = '.';
4566 info->fw_version[7] = 0;
4567}
4568
4569static void
4570bnx2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
4571{
4572 struct bnx2 *bp = dev->priv;
4573
4574 if (bp->flags & NO_WOL_FLAG) {
4575 wol->supported = 0;
4576 wol->wolopts = 0;
4577 }
4578 else {
4579 wol->supported = WAKE_MAGIC;
4580 if (bp->wol)
4581 wol->wolopts = WAKE_MAGIC;
4582 else
4583 wol->wolopts = 0;
4584 }
4585 memset(&wol->sopass, 0, sizeof(wol->sopass));
4586}
4587
4588static int
4589bnx2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
4590{
4591 struct bnx2 *bp = dev->priv;
4592
4593 if (wol->wolopts & ~WAKE_MAGIC)
4594 return -EINVAL;
4595
4596 if (wol->wolopts & WAKE_MAGIC) {
4597 if (bp->flags & NO_WOL_FLAG)
4598 return -EINVAL;
4599
4600 bp->wol = 1;
4601 }
4602 else {
4603 bp->wol = 0;
4604 }
4605 return 0;
4606}
4607
4608static int
4609bnx2_nway_reset(struct net_device *dev)
4610{
4611 struct bnx2 *bp = dev->priv;
4612 u32 bmcr;
4613
4614 if (!(bp->autoneg & AUTONEG_SPEED)) {
4615 return -EINVAL;
4616 }
4617
c770a65c 4618 spin_lock_bh(&bp->phy_lock);
b6016b76
MC		 4619
4620 /* Force a link down visible on the other side */
4621 if (bp->phy_flags & PHY_SERDES_FLAG) {
4622 bnx2_write_phy(bp, MII_BMCR, BMCR_LOOPBACK);
c770a65c 4623 spin_unlock_bh(&bp->phy_lock);
b6016b76
MC		 4624
4625 msleep(20);
4626
c770a65c 4627 spin_lock_bh(&bp->phy_lock);
b6016b76 4628 if (CHIP_NUM(bp) == CHIP_NUM_5706) {
cd339a0e
MC		 4629 bp->current_interval = SERDES_AN_TIMEOUT;
4630 bp->serdes_an_pending = 1;
4631 mod_timer(&bp->timer, jiffies + bp->current_interval);
b6016b76
MC		 4632 }
4633 }
4634
4635 bnx2_read_phy(bp, MII_BMCR, &bmcr);
4636 bmcr &= ~BMCR_LOOPBACK;
4637 bnx2_write_phy(bp, MII_BMCR, bmcr | BMCR_ANRESTART | BMCR_ANENABLE);
4638
c770a65c 4639 spin_unlock_bh(&bp->phy_lock);
b6016b76
MC		 4640
4641 return 0;
4642}
4643
4644static int
4645bnx2_get_eeprom_len(struct net_device *dev)
4646{
4647 struct bnx2 *bp = dev->priv;
4648
4649 if (bp->flash_info == 0)
4650 return 0;
4651
4652 return (int) bp->flash_info->total_size;
4653}
4654
4655static int
4656bnx2_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
4657 u8 *eebuf)
4658{
4659 struct bnx2 *bp = dev->priv;
4660 int rc;
4661
4662 if (eeprom->offset > bp->flash_info->total_size)
4663 return -EINVAL;
4664
4665 if ((eeprom->offset + eeprom->len) > bp->flash_info->total_size)
4666 eeprom->len = bp->flash_info->total_size - eeprom->offset;
4667
4668 rc = bnx2_nvram_read(bp, eeprom->offset, eebuf, eeprom->len);
4669
4670 return rc;
4671}
4672
4673static int
4674bnx2_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
4675 u8 *eebuf)
4676{
4677 struct bnx2 *bp = dev->priv;
4678 int rc;
4679
4680 if (eeprom->offset > bp->flash_info->total_size)
4681 return -EINVAL;
4682
4683 if ((eeprom->offset + eeprom->len) > bp->flash_info->total_size)
4684 eeprom->len = bp->flash_info->total_size - eeprom->offset;
4685
4686 rc = bnx2_nvram_write(bp, eeprom->offset, eebuf, eeprom->len);
4687
4688 return rc;
4689}
4690
4691static int
4692bnx2_get_coalesce(struct net_device *dev, struct ethtool_coalesce *coal)
4693{
4694 struct bnx2 *bp = dev->priv;
4695
4696 memset(coal, 0, sizeof(struct ethtool_coalesce));
4697
4698 coal->rx_coalesce_usecs = bp->rx_ticks;
4699 coal->rx_max_coalesced_frames = bp->rx_quick_cons_trip;
4700 coal->rx_coalesce_usecs_irq = bp->rx_ticks_int;
4701 coal->rx_max_coalesced_frames_irq = bp->rx_quick_cons_trip_int;
4702
4703 coal->tx_coalesce_usecs = bp->tx_ticks;
4704 coal->tx_max_coalesced_frames = bp->tx_quick_cons_trip;
4705 coal->tx_coalesce_usecs_irq = bp->tx_ticks_int;
4706 coal->tx_max_coalesced_frames_irq = bp->tx_quick_cons_trip_int;
4707
4708 coal->stats_block_coalesce_usecs = bp->stats_ticks;
4709
4710 return 0;
4711}
4712
4713static int
4714bnx2_set_coalesce(struct net_device *dev, struct ethtool_coalesce *coal)
4715{
4716 struct bnx2 *bp = dev->priv;
4717
4718 bp->rx_ticks = (u16) coal->rx_coalesce_usecs;
4719 if (bp->rx_ticks > 0x3ff) bp->rx_ticks = 0x3ff;
4720
4721 bp->rx_quick_cons_trip = (u16) coal->rx_max_coalesced_frames;
4722 if (bp->rx_quick_cons_trip > 0xff) bp->rx_quick_cons_trip = 0xff;
4723
4724 bp->rx_ticks_int = (u16) coal->rx_coalesce_usecs_irq;
4725 if (bp->rx_ticks_int > 0x3ff) bp->rx_ticks_int = 0x3ff;
4726
4727 bp->rx_quick_cons_trip_int = (u16) coal->rx_max_coalesced_frames_irq;
4728 if (bp->rx_quick_cons_trip_int > 0xff)
4729 bp->rx_quick_cons_trip_int = 0xff;
4730
4731 bp->tx_ticks = (u16) coal->tx_coalesce_usecs;
4732 if (bp->tx_ticks > 0x3ff) bp->tx_ticks = 0x3ff;
4733
4734 bp->tx_quick_cons_trip = (u16) coal->tx_max_coalesced_frames;
4735 if (bp->tx_quick_cons_trip > 0xff) bp->tx_quick_cons_trip = 0xff;
4736
4737 bp->tx_ticks_int = (u16) coal->tx_coalesce_usecs_irq;
4738 if (bp->tx_ticks_int > 0x3ff) bp->tx_ticks_int = 0x3ff;
4739
4740 bp->tx_quick_cons_trip_int = (u16) coal->tx_max_coalesced_frames_irq;
4741 if (bp->tx_quick_cons_trip_int > 0xff) bp->tx_quick_cons_trip_int =
4742 0xff;
4743
4744 bp->stats_ticks = coal->stats_block_coalesce_usecs;
4745 if (bp->stats_ticks > 0xffff00) bp->stats_ticks = 0xffff00;
4746 bp->stats_ticks &= 0xffff00;
4747
4748 if (netif_running(bp->dev)) {
4749 bnx2_netif_stop(bp);
4750 bnx2_init_nic(bp);
4751 bnx2_netif_start(bp);
4752 }
4753
4754 return 0;
4755}
4756
4757static void
4758bnx2_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
4759{
4760 struct bnx2 *bp = dev->priv;
4761
4762 ering->rx_max_pending = MAX_RX_DESC_CNT;
4763 ering->rx_mini_max_pending = 0;
4764 ering->rx_jumbo_max_pending = 0;
4765
4766 ering->rx_pending = bp->rx_ring_size;
4767 ering->rx_mini_pending = 0;
4768 ering->rx_jumbo_pending = 0;
4769
4770 ering->tx_max_pending = MAX_TX_DESC_CNT;
4771 ering->tx_pending = bp->tx_ring_size;
4772}
4773
4774static int
4775bnx2_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
4776{
4777 struct bnx2 *bp = dev->priv;
4778
4779 if ((ering->rx_pending > MAX_RX_DESC_CNT) ||
4780 (ering->tx_pending > MAX_TX_DESC_CNT) ||
4781 (ering->tx_pending <= MAX_SKB_FRAGS)) {
4782
4783 return -EINVAL;
4784 }
4785 bp->rx_ring_size = ering->rx_pending;
4786 bp->tx_ring_size = ering->tx_pending;
4787
4788 if (netif_running(bp->dev)) {
4789 bnx2_netif_stop(bp);
4790 bnx2_init_nic(bp);
4791 bnx2_netif_start(bp);
4792 }
4793
4794 return 0;
4795}
4796
4797static void
4798bnx2_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
4799{
4800 struct bnx2 *bp = dev->priv;
4801
4802 epause->autoneg = ((bp->autoneg & AUTONEG_FLOW_CTRL) != 0);
4803 epause->rx_pause = ((bp->flow_ctrl & FLOW_CTRL_RX) != 0);
4804 epause->tx_pause = ((bp->flow_ctrl & FLOW_CTRL_TX) != 0);
4805}
4806
4807static int
4808bnx2_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
4809{
4810 struct bnx2 *bp = dev->priv;
4811
4812 bp->req_flow_ctrl = 0;
4813 if (epause->rx_pause)
4814 bp->req_flow_ctrl |= FLOW_CTRL_RX;
4815 if (epause->tx_pause)
4816 bp->req_flow_ctrl |= FLOW_CTRL_TX;
4817
4818 if (epause->autoneg) {
4819 bp->autoneg |= AUTONEG_FLOW_CTRL;
4820 }
4821 else {
4822 bp->autoneg &= ~AUTONEG_FLOW_CTRL;
4823 }
4824
c770a65c 4825 spin_lock_bh(&bp->phy_lock);
b6016b76
MC		 4826
4827 bnx2_setup_phy(bp);
4828
c770a65c 4829 spin_unlock_bh(&bp->phy_lock);
b6016b76
MC		 4830
4831 return 0;
4832}
4833
4834static u32
4835bnx2_get_rx_csum(struct net_device *dev)
4836{
4837 struct bnx2 *bp = dev->priv;
4838
4839 return bp->rx_csum;
4840}
4841
4842static int
4843bnx2_set_rx_csum(struct net_device *dev, u32 data)
4844{
4845 struct bnx2 *bp = dev->priv;
4846
4847 bp->rx_csum = data;
4848 return 0;
4849}
4850
4851#define BNX2_NUM_STATS 45
4852
14ab9b86 4853static struct {
b6016b76
MC		 4854 char string[ETH_GSTRING_LEN];
4855} bnx2_stats_str_arr[BNX2_NUM_STATS] = {
4856 { "rx_bytes" },
4857 { "rx_error_bytes" },
4858 { "tx_bytes" },
4859 { "tx_error_bytes" },
4860 { "rx_ucast_packets" },
4861 { "rx_mcast_packets" },
4862 { "rx_bcast_packets" },
4863 { "tx_ucast_packets" },
4864 { "tx_mcast_packets" },
4865 { "tx_bcast_packets" },
4866 { "tx_mac_errors" },
4867 { "tx_carrier_errors" },
4868 { "rx_crc_errors" },
4869 { "rx_align_errors" },
4870 { "tx_single_collisions" },
4871 { "tx_multi_collisions" },
4872 { "tx_deferred" },
4873 { "tx_excess_collisions" },
4874 { "tx_late_collisions" },
4875 { "tx_total_collisions" },
4876 { "rx_fragments" },
4877 { "rx_jabbers" },
4878 { "rx_undersize_packets" },
4879 { "rx_oversize_packets" },
4880 { "rx_64_byte_packets" },
4881 { "rx_65_to_127_byte_packets" },
4882 { "rx_128_to_255_byte_packets" },
4883 { "rx_256_to_511_byte_packets" },
4884 { "rx_512_to_1023_byte_packets" },
4885 { "rx_1024_to_1522_byte_packets" },
4886 { "rx_1523_to_9022_byte_packets" },
4887 { "tx_64_byte_packets" },
4888 { "tx_65_to_127_byte_packets" },
4889 { "tx_128_to_255_byte_packets" },
4890 { "tx_256_to_511_byte_packets" },
4891 { "tx_512_to_1023_byte_packets" },
4892 { "tx_1024_to_1522_byte_packets" },
4893 { "tx_1523_to_9022_byte_packets" },
4894 { "rx_xon_frames" },
4895 { "rx_xoff_frames" },
4896 { "tx_xon_frames" },
4897 { "tx_xoff_frames" },
4898 { "rx_mac_ctrl_frames" },
4899 { "rx_filtered_packets" },
4900 { "rx_discards" },
4901};
4902
4903#define STATS_OFFSET32(offset_name) (offsetof(struct statistics_block, offset_name) / 4)
4904
14ab9b86 4905static unsigned long bnx2_stats_offset_arr[BNX2_NUM_STATS] = {
b6016b76
MC		 4906 STATS_OFFSET32(stat_IfHCInOctets_hi),
4907 STATS_OFFSET32(stat_IfHCInBadOctets_hi),
4908 STATS_OFFSET32(stat_IfHCOutOctets_hi),
4909 STATS_OFFSET32(stat_IfHCOutBadOctets_hi),
4910 STATS_OFFSET32(stat_IfHCInUcastPkts_hi),
4911 STATS_OFFSET32(stat_IfHCInMulticastPkts_hi),
4912 STATS_OFFSET32(stat_IfHCInBroadcastPkts_hi),
4913 STATS_OFFSET32(stat_IfHCOutUcastPkts_hi),
4914 STATS_OFFSET32(stat_IfHCOutMulticastPkts_hi),
4915 STATS_OFFSET32(stat_IfHCOutBroadcastPkts_hi),
4916 STATS_OFFSET32(stat_emac_tx_stat_dot3statsinternalmactransmiterrors),
4917 STATS_OFFSET32(stat_Dot3StatsCarrierSenseErrors),
4918 STATS_OFFSET32(stat_Dot3StatsFCSErrors),
4919 STATS_OFFSET32(stat_Dot3StatsAlignmentErrors),
4920 STATS_OFFSET32(stat_Dot3StatsSingleCollisionFrames),
4921 STATS_OFFSET32(stat_Dot3StatsMultipleCollisionFrames),
4922 STATS_OFFSET32(stat_Dot3StatsDeferredTransmissions),
4923 STATS_OFFSET32(stat_Dot3StatsExcessiveCollisions),
4924 STATS_OFFSET32(stat_Dot3StatsLateCollisions),
4925 STATS_OFFSET32(stat_EtherStatsCollisions),
4926 STATS_OFFSET32(stat_EtherStatsFragments),
4927 STATS_OFFSET32(stat_EtherStatsJabbers),
4928 STATS_OFFSET32(stat_EtherStatsUndersizePkts),
4929 STATS_OFFSET32(stat_EtherStatsOverrsizePkts),
4930 STATS_OFFSET32(stat_EtherStatsPktsRx64Octets),
4931 STATS_OFFSET32(stat_EtherStatsPktsRx65Octetsto127Octets),
4932 STATS_OFFSET32(stat_EtherStatsPktsRx128Octetsto255Octets),
4933 STATS_OFFSET32(stat_EtherStatsPktsRx256Octetsto511Octets),
4934 STATS_OFFSET32(stat_EtherStatsPktsRx512Octetsto1023Octets),
4935 STATS_OFFSET32(stat_EtherStatsPktsRx1024Octetsto1522Octets),
4936 STATS_OFFSET32(stat_EtherStatsPktsRx1523Octetsto9022Octets),
4937 STATS_OFFSET32(stat_EtherStatsPktsTx64Octets),
4938 STATS_OFFSET32(stat_EtherStatsPktsTx65Octetsto127Octets),
4939 STATS_OFFSET32(stat_EtherStatsPktsTx128Octetsto255Octets),
4940 STATS_OFFSET32(stat_EtherStatsPktsTx256Octetsto511Octets),
4941 STATS_OFFSET32(stat_EtherStatsPktsTx512Octetsto1023Octets),
4942 STATS_OFFSET32(stat_EtherStatsPktsTx1024Octetsto1522Octets),
4943 STATS_OFFSET32(stat_EtherStatsPktsTx1523Octetsto9022Octets),
4944 STATS_OFFSET32(stat_XonPauseFramesReceived),
4945 STATS_OFFSET32(stat_XoffPauseFramesReceived),
4946 STATS_OFFSET32(stat_OutXonSent),
4947 STATS_OFFSET32(stat_OutXoffSent),
4948 STATS_OFFSET32(stat_MacControlFramesReceived),
4949 STATS_OFFSET32(stat_IfInFramesL2FilterDiscards),
4950 STATS_OFFSET32(stat_IfInMBUFDiscards),
4951};
4952
4953/* stat_IfHCInBadOctets and stat_Dot3StatsCarrierSenseErrors are
4954 * skipped because of errata.
4955 */
14ab9b86 4956static u8 bnx2_5706_stats_len_arr[BNX2_NUM_STATS] = {
b6016b76
MC		 4957 8,0,8,8,8,8,8,8,8,8,
4958 4,0,4,4,4,4,4,4,4,4,
4959 4,4,4,4,4,4,4,4,4,4,
4960 4,4,4,4,4,4,4,4,4,4,
4961 4,4,4,4,4,
4962};
4963
5b0c76ad
MC		 4964static u8 bnx2_5708_stats_len_arr[BNX2_NUM_STATS] = {
4965 8,0,8,8,8,8,8,8,8,8,
4966 4,4,4,4,4,4,4,4,4,4,
4967 4,4,4,4,4,4,4,4,4,4,
4968 4,4,4,4,4,4,4,4,4,4,
4969 4,4,4,4,4,
4970};
4971
b6016b76
MC		 4972#define BNX2_NUM_TESTS 6
4973
14ab9b86 4974static struct {
b6016b76
MC		 4975 char string[ETH_GSTRING_LEN];
4976} bnx2_tests_str_arr[BNX2_NUM_TESTS] = {
4977 { "register_test (offline)" },
4978 { "memory_test (offline)" },
4979 { "loopback_test (offline)" },
4980 { "nvram_test (online)" },
4981 { "interrupt_test (online)" },
4982 { "link_test (online)" },
4983};
4984
4985static int
4986bnx2_self_test_count(struct net_device *dev)
4987{
4988 return BNX2_NUM_TESTS;
4989}
4990
4991static void
4992bnx2_self_test(struct net_device *dev, struct ethtool_test *etest, u64 *buf)
4993{
4994 struct bnx2 *bp = dev->priv;
4995
4996 memset(buf, 0, sizeof(u64) * BNX2_NUM_TESTS);
4997 if (etest->flags & ETH_TEST_FL_OFFLINE) {
4998 bnx2_netif_stop(bp);
4999 bnx2_reset_chip(bp, BNX2_DRV_MSG_CODE_DIAG);
5000 bnx2_free_skbs(bp);
5001
5002 if (bnx2_test_registers(bp) != 0) {
5003 buf[0] = 1;
5004 etest->flags |= ETH_TEST_FL_FAILED;
5005 }
5006 if (bnx2_test_memory(bp) != 0) {
5007 buf[1] = 1;
5008 etest->flags |= ETH_TEST_FL_FAILED;
5009 }
5010 if (bnx2_test_loopback(bp) != 0) {
5011 buf[2] = 1;
5012 etest->flags |= ETH_TEST_FL_FAILED;
5013 }
5014
5015 if (!netif_running(bp->dev)) {
5016 bnx2_reset_chip(bp, BNX2_DRV_MSG_CODE_RESET);
5017 }
5018 else {
5019 bnx2_init_nic(bp);
5020 bnx2_netif_start(bp);
5021 }
5022
5023 /* wait for link up */
5024 msleep_interruptible(3000);
5025 if ((!bp->link_up) && !(bp->phy_flags & PHY_SERDES_FLAG))
5026 msleep_interruptible(4000);
5027 }
5028
5029 if (bnx2_test_nvram(bp) != 0) {
5030 buf[3] = 1;
5031 etest->flags |= ETH_TEST_FL_FAILED;
5032 }
5033 if (bnx2_test_intr(bp) != 0) {
5034 buf[4] = 1;
5035 etest->flags |= ETH_TEST_FL_FAILED;
5036 }
5037
5038 if (bnx2_test_link(bp) != 0) {
5039 buf[5] = 1;
5040 etest->flags |= ETH_TEST_FL_FAILED;
5041
5042 }
5043}
5044
5045static void
5046bnx2_get_strings(struct net_device *dev, u32 stringset, u8 *buf)
5047{
5048 switch (stringset) {
5049 case ETH_SS_STATS:
5050 memcpy(buf, bnx2_stats_str_arr,
5051 sizeof(bnx2_stats_str_arr));
5052 break;
5053 case ETH_SS_TEST:
5054 memcpy(buf, bnx2_tests_str_arr,
5055 sizeof(bnx2_tests_str_arr));
5056 break;
5057 }
5058}
5059
5060static int
5061bnx2_get_stats_count(struct net_device *dev)
5062{
5063 return BNX2_NUM_STATS;
5064}
5065
5066static void
5067bnx2_get_ethtool_stats(struct net_device *dev,
5068 struct ethtool_stats *stats, u64 *buf)
5069{
5070 struct bnx2 *bp = dev->priv;
5071 int i;
5072 u32 *hw_stats = (u32 *) bp->stats_blk;
14ab9b86 5073 u8 *stats_len_arr = NULL;
b6016b76
MC		 5074
5075 if (hw_stats == NULL) {
5076 memset(buf, 0, sizeof(u64) * BNX2_NUM_STATS);
5077 return;
5078 }
5079
5b0c76ad
MC		 5080 if ((CHIP_ID(bp) == CHIP_ID_5706_A0) ||
5081 (CHIP_ID(bp) == CHIP_ID_5706_A1) ||
5082 (CHIP_ID(bp) == CHIP_ID_5706_A2) ||
5083 (CHIP_ID(bp) == CHIP_ID_5708_A0))
b6016b76 5084 stats_len_arr = bnx2_5706_stats_len_arr;
5b0c76ad
MC		 5085 else
5086 stats_len_arr = bnx2_5708_stats_len_arr;
b6016b76
MC		 5087
5088 for (i = 0; i < BNX2_NUM_STATS; i++) {
5089 if (stats_len_arr[i] == 0) {
5090 /* skip this counter */
5091 buf[i] = 0;
5092 continue;
5093 }
5094 if (stats_len_arr[i] == 4) {
5095 /* 4-byte counter */
5096 buf[i] = (u64)
5097 *(hw_stats + bnx2_stats_offset_arr[i]);
5098 continue;
5099 }
5100 /* 8-byte counter */
5101 buf[i] = (((u64) *(hw_stats +
5102 bnx2_stats_offset_arr[i])) << 32) +
5103 *(hw_stats + bnx2_stats_offset_arr[i] + 1);
5104 }
5105}
5106
5107static int
5108bnx2_phys_id(struct net_device *dev, u32 data)
5109{
5110 struct bnx2 *bp = dev->priv;
5111 int i;
5112 u32 save;
5113
5114 if (data == 0)
5115 data = 2;
5116
5117 save = REG_RD(bp, BNX2_MISC_CFG);
5118 REG_WR(bp, BNX2_MISC_CFG, BNX2_MISC_CFG_LEDMODE_MAC);
5119
5120 for (i = 0; i < (data * 2); i++) {
5121 if ((i % 2) == 0) {
5122 REG_WR(bp, BNX2_EMAC_LED, BNX2_EMAC_LED_OVERRIDE);
5123 }
5124 else {
5125 REG_WR(bp, BNX2_EMAC_LED, BNX2_EMAC_LED_OVERRIDE |
5126 BNX2_EMAC_LED_1000MB_OVERRIDE |
5127 BNX2_EMAC_LED_100MB_OVERRIDE |
5128 BNX2_EMAC_LED_10MB_OVERRIDE |
5129 BNX2_EMAC_LED_TRAFFIC_OVERRIDE |
5130 BNX2_EMAC_LED_TRAFFIC);
5131 }
5132 msleep_interruptible(500);
5133 if (signal_pending(current))
5134 break;
5135 }
5136 REG_WR(bp, BNX2_EMAC_LED, 0);
5137 REG_WR(bp, BNX2_MISC_CFG, save);
5138 return 0;
5139}
5140
5141static struct ethtool_ops bnx2_ethtool_ops = {
5142 .get_settings = bnx2_get_settings,
5143 .set_settings = bnx2_set_settings,
5144 .get_drvinfo = bnx2_get_drvinfo,
5145 .get_wol = bnx2_get_wol,
5146 .set_wol = bnx2_set_wol,
5147 .nway_reset = bnx2_nway_reset,
5148 .get_link = ethtool_op_get_link,
5149 .get_eeprom_len = bnx2_get_eeprom_len,
5150 .get_eeprom = bnx2_get_eeprom,
5151 .set_eeprom = bnx2_set_eeprom,
5152 .get_coalesce = bnx2_get_coalesce,
5153 .set_coalesce = bnx2_set_coalesce,
5154 .get_ringparam = bnx2_get_ringparam,
5155 .set_ringparam = bnx2_set_ringparam,
5156 .get_pauseparam = bnx2_get_pauseparam,
5157 .set_pauseparam = bnx2_set_pauseparam,
5158 .get_rx_csum = bnx2_get_rx_csum,
5159 .set_rx_csum = bnx2_set_rx_csum,
5160 .get_tx_csum = ethtool_op_get_tx_csum,
5161 .set_tx_csum = ethtool_op_set_tx_csum,
5162 .get_sg = ethtool_op_get_sg,
5163 .set_sg = ethtool_op_set_sg,
5164#ifdef BCM_TSO
5165 .get_tso = ethtool_op_get_tso,
5166 .set_tso = ethtool_op_set_tso,
5167#endif
5168 .self_test_count = bnx2_self_test_count,
5169 .self_test = bnx2_self_test,
5170 .get_strings = bnx2_get_strings,
5171 .phys_id = bnx2_phys_id,
5172 .get_stats_count = bnx2_get_stats_count,
5173 .get_ethtool_stats = bnx2_get_ethtool_stats,
24b8e05d 5174 .get_perm_addr = ethtool_op_get_perm_addr,
b6016b76
MC		 5175};
5176
5177/* Called with rtnl_lock */
5178static int
5179bnx2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
5180{
14ab9b86 5181 struct mii_ioctl_data *data = if_mii(ifr);
b6016b76
MC		 5182 struct bnx2 *bp = dev->priv;
5183 int err;
5184
5185 switch(cmd) {
5186 case SIOCGMIIPHY:
5187 data->phy_id = bp->phy_addr;
5188
5189 /* fallthru */
5190 case SIOCGMIIREG: {
5191 u32 mii_regval;
5192
c770a65c 5193 spin_lock_bh(&bp->phy_lock);
b6016b76 5194 err = bnx2_read_phy(bp, data->reg_num & 0x1f, &mii_regval);
c770a65c 5195 spin_unlock_bh(&bp->phy_lock);
b6016b76
MC		 5196
5197 data->val_out = mii_regval;
5198
5199 return err;
5200 }
5201
5202 case SIOCSMIIREG:
5203 if (!capable(CAP_NET_ADMIN))
5204 return -EPERM;
5205
c770a65c 5206 spin_lock_bh(&bp->phy_lock);
b6016b76 5207 err = bnx2_write_phy(bp, data->reg_num & 0x1f, data->val_in);
c770a65c 5208 spin_unlock_bh(&bp->phy_lock);
b6016b76
MC		 5209
5210 return err;
5211
5212 default:
5213 /* do nothing */
5214 break;
5215 }
5216 return -EOPNOTSUPP;
5217}
5218
5219/* Called with rtnl_lock */
5220static int
5221bnx2_change_mac_addr(struct net_device *dev, void *p)
5222{
5223 struct sockaddr *addr = p;
5224 struct bnx2 *bp = dev->priv;
5225
73eef4cd
MC		 5226 if (!is_valid_ether_addr(addr->sa_data))
5227 return -EINVAL;
5228
b6016b76
MC		 5229 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
5230 if (netif_running(dev))
5231 bnx2_set_mac_addr(bp);
5232
5233 return 0;
5234}
5235
5236/* Called with rtnl_lock */
5237static int
5238bnx2_change_mtu(struct net_device *dev, int new_mtu)
5239{
5240 struct bnx2 *bp = dev->priv;
5241
5242 if (((new_mtu + ETH_HLEN) > MAX_ETHERNET_JUMBO_PACKET_SIZE) ||
5243 ((new_mtu + ETH_HLEN) < MIN_ETHERNET_PACKET_SIZE))
5244 return -EINVAL;
5245
5246 dev->mtu = new_mtu;
5247 if (netif_running(dev)) {
5248 bnx2_netif_stop(bp);
5249
5250 bnx2_init_nic(bp);
5251
5252 bnx2_netif_start(bp);
5253 }
5254 return 0;
5255}
5256
5257#if defined(HAVE_POLL_CONTROLLER) || defined(CONFIG_NET_POLL_CONTROLLER)
5258static void
5259poll_bnx2(struct net_device *dev)
5260{
5261 struct bnx2 *bp = dev->priv;
5262
5263 disable_irq(bp->pdev->irq);
5264 bnx2_interrupt(bp->pdev->irq, dev, NULL);
5265 enable_irq(bp->pdev->irq);
5266}
5267#endif
5268
5269static int __devinit
5270bnx2_init_board(struct pci_dev *pdev, struct net_device *dev)
5271{
5272 struct bnx2 *bp;
5273 unsigned long mem_len;
5274 int rc;
5275 u32 reg;
5276
5277 SET_MODULE_OWNER(dev);
5278 SET_NETDEV_DEV(dev, &pdev->dev);
5279 bp = dev->priv;
5280
5281 bp->flags = 0;
5282 bp->phy_flags = 0;
5283
5284 /* enable device (incl. PCI PM wakeup), and bus-mastering */
5285 rc = pci_enable_device(pdev);
5286 if (rc) {
5287 printk(KERN_ERR PFX "Cannot enable PCI device, aborting.");
5288 goto err_out;
5289 }
5290
5291 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
5292 printk(KERN_ERR PFX "Cannot find PCI device base address, "
5293 "aborting.\n");
5294 rc = -ENODEV;
5295 goto err_out_disable;
5296 }
5297
5298 rc = pci_request_regions(pdev, DRV_MODULE_NAME);
5299 if (rc) {
5300 printk(KERN_ERR PFX "Cannot obtain PCI resources, aborting.\n");
5301 goto err_out_disable;
5302 }
5303
5304 pci_set_master(pdev);
5305
5306 bp->pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
5307 if (bp->pm_cap == 0) {
5308 printk(KERN_ERR PFX "Cannot find power management capability, "
5309 "aborting.\n");
5310 rc = -EIO;
5311 goto err_out_release;
5312 }
5313
5314 bp->pcix_cap = pci_find_capability(pdev, PCI_CAP_ID_PCIX);
5315 if (bp->pcix_cap == 0) {
5316 printk(KERN_ERR PFX "Cannot find PCIX capability, aborting.\n");
5317 rc = -EIO;
5318 goto err_out_release;
5319 }
5320
5321 if (pci_set_dma_mask(pdev, DMA_64BIT_MASK) == 0) {
5322 bp->flags |= USING_DAC_FLAG;
5323 if (pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK) != 0) {
5324 printk(KERN_ERR PFX "pci_set_consistent_dma_mask "
5325 "failed, aborting.\n");
5326 rc = -EIO;
5327 goto err_out_release;
5328 }
5329 }
5330 else if (pci_set_dma_mask(pdev, DMA_32BIT_MASK) != 0) {
5331 printk(KERN_ERR PFX "System does not support DMA, aborting.\n");
5332 rc = -EIO;
5333 goto err_out_release;
5334 }
5335
5336 bp->dev = dev;
5337 bp->pdev = pdev;
5338
5339 spin_lock_init(&bp->phy_lock);
5340 spin_lock_init(&bp->tx_lock);
5341 INIT_WORK(&bp->reset_task, bnx2_reset_task, bp);
5342
5343 dev->base_addr = dev->mem_start = pci_resource_start(pdev, 0);
5344 mem_len = MB_GET_CID_ADDR(17);
5345 dev->mem_end = dev->mem_start + mem_len;
5346 dev->irq = pdev->irq;
5347
5348 bp->regview = ioremap_nocache(dev->base_addr, mem_len);
5349
5350 if (!bp->regview) {
5351 printk(KERN_ERR PFX "Cannot map register space, aborting.\n");
5352 rc = -ENOMEM;
5353 goto err_out_release;
5354 }
5355
5356 /* Configure byte swap and enable write to the reg_window registers.
5357 * Rely on CPU to do target byte swapping on big endian systems
5358 * The chip's target access swapping will not swap all accesses
5359 */
5360 pci_write_config_dword(bp->pdev, BNX2_PCICFG_MISC_CONFIG,
5361 BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
5362 BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP);
5363
829ca9a3 5364 bnx2_set_power_state(bp, PCI_D0);
b6016b76
MC		 5365
5366 bp->chip_id = REG_RD(bp, BNX2_MISC_ID);
5367
b6016b76
MC		 5368 /* Get bus information. */
5369 reg = REG_RD(bp, BNX2_PCICFG_MISC_STATUS);
5370 if (reg & BNX2_PCICFG_MISC_STATUS_PCIX_DET) {
5371 u32 clkreg;
5372
5373 bp->flags |= PCIX_FLAG;
5374
5375 clkreg = REG_RD(bp, BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS);
5376
5377 clkreg &= BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET;
5378 switch (clkreg) {
5379 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ:
5380 bp->bus_speed_mhz = 133;
5381 break;
5382
5383 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ:
5384 bp->bus_speed_mhz = 100;
5385 break;
5386
5387 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ:
5388 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ:
5389 bp->bus_speed_mhz = 66;
5390 break;
5391
5392 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ:
5393 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ:
5394 bp->bus_speed_mhz = 50;
5395 break;
5396
5397 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_LOW:
5398 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ:
5399 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ:
5400 bp->bus_speed_mhz = 33;
5401 break;
5402 }
5403 }
5404 else {
5405 if (reg & BNX2_PCICFG_MISC_STATUS_M66EN)
5406 bp->bus_speed_mhz = 66;
5407 else
5408 bp->bus_speed_mhz = 33;
5409 }
5410
5411 if (reg & BNX2_PCICFG_MISC_STATUS_32BIT_DET)
5412 bp->flags |= PCI_32BIT_FLAG;
5413
5414 /* 5706A0 may falsely detect SERR and PERR. */
5415 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
5416 reg = REG_RD(bp, PCI_COMMAND);
5417 reg &= ~(PCI_COMMAND_SERR | PCI_COMMAND_PARITY);
5418 REG_WR(bp, PCI_COMMAND, reg);
5419 }
5420 else if ((CHIP_ID(bp) == CHIP_ID_5706_A1) &&
5421 !(bp->flags & PCIX_FLAG)) {
5422
5423 printk(KERN_ERR PFX "5706 A1 can only be used in a PCIX bus, "
5424 "aborting.\n");
5425 goto err_out_unmap;
5426 }
5427
5428 bnx2_init_nvram(bp);
5429
5430 /* Get the permanent MAC address. First we need to make sure the
5431 * firmware is actually running.
5432 */
5433 reg = REG_RD_IND(bp, HOST_VIEW_SHMEM_BASE + BNX2_DEV_INFO_SIGNATURE);
5434
5435 if ((reg & BNX2_DEV_INFO_SIGNATURE_MAGIC_MASK) !=
5436 BNX2_DEV_INFO_SIGNATURE_MAGIC) {
5437 printk(KERN_ERR PFX "Firmware not running, aborting.\n");
5438 rc = -ENODEV;
5439 goto err_out_unmap;
5440 }
5441
5442 bp->fw_ver = REG_RD_IND(bp, HOST_VIEW_SHMEM_BASE +
5443 BNX2_DEV_INFO_BC_REV);
5444
5445 reg = REG_RD_IND(bp, HOST_VIEW_SHMEM_BASE + BNX2_PORT_HW_CFG_MAC_UPPER);
5446 bp->mac_addr[0] = (u8) (reg >> 8);
5447 bp->mac_addr[1] = (u8) reg;
5448
5449 reg = REG_RD_IND(bp, HOST_VIEW_SHMEM_BASE + BNX2_PORT_HW_CFG_MAC_LOWER);
5450 bp->mac_addr[2] = (u8) (reg >> 24);
5451 bp->mac_addr[3] = (u8) (reg >> 16);
5452 bp->mac_addr[4] = (u8) (reg >> 8);
5453 bp->mac_addr[5] = (u8) reg;
5454
5455 bp->tx_ring_size = MAX_TX_DESC_CNT;
5456 bp->rx_ring_size = 100;
5457
5458 bp->rx_csum = 1;
5459
5460 bp->rx_offset = sizeof(struct l2_fhdr) + 2;
5461
5462 bp->tx_quick_cons_trip_int = 20;
5463 bp->tx_quick_cons_trip = 20;
5464 bp->tx_ticks_int = 80;
5465 bp->tx_ticks = 80;
5466
5467 bp->rx_quick_cons_trip_int = 6;
5468 bp->rx_quick_cons_trip = 6;
5469 bp->rx_ticks_int = 18;
5470 bp->rx_ticks = 18;
5471
5472 bp->stats_ticks = 1000000 & 0xffff00;
5473
5474 bp->timer_interval = HZ;
cd339a0e 5475 bp->current_interval = HZ;
b6016b76 5476
5b0c76ad
MC		 5477 bp->phy_addr = 1;
5478
b6016b76
MC		 5479 /* Disable WOL support if we are running on a SERDES chip. */
5480 if (CHIP_BOND_ID(bp) & CHIP_BOND_ID_SERDES_BIT) {
5481 bp->phy_flags |= PHY_SERDES_FLAG;
5482 bp->flags |= NO_WOL_FLAG;
5b0c76ad
MC		 5483 if (CHIP_NUM(bp) == CHIP_NUM_5708) {
5484 bp->phy_addr = 2;
5485 reg = REG_RD_IND(bp, HOST_VIEW_SHMEM_BASE +
5486 BNX2_SHARED_HW_CFG_CONFIG);
5487 if (reg & BNX2_SHARED_HW_CFG_PHY_2_5G)
5488 bp->phy_flags |= PHY_2_5G_CAPABLE_FLAG;
5489 }
b6016b76
MC		 5490 }
5491
5492 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
5493 bp->tx_quick_cons_trip_int =
5494 bp->tx_quick_cons_trip;
5495 bp->tx_ticks_int = bp->tx_ticks;
5496 bp->rx_quick_cons_trip_int =
5497 bp->rx_quick_cons_trip;
5498 bp->rx_ticks_int = bp->rx_ticks;
5499 bp->comp_prod_trip_int = bp->comp_prod_trip;
5500 bp->com_ticks_int = bp->com_ticks;
5501 bp->cmd_ticks_int = bp->cmd_ticks;
5502 }
5503
5504 bp->autoneg = AUTONEG_SPEED | AUTONEG_FLOW_CTRL;
5505 bp->req_line_speed = 0;
5506 if (bp->phy_flags & PHY_SERDES_FLAG) {
5507 bp->advertising = ETHTOOL_ALL_FIBRE_SPEED | ADVERTISED_Autoneg;
cd339a0e
MC		 5508
5509 reg = REG_RD_IND(bp, HOST_VIEW_SHMEM_BASE +
5510 BNX2_PORT_HW_CFG_CONFIG);
5511 reg &= BNX2_PORT_HW_CFG_CFG_DFLT_LINK_MASK;
5512 if (reg == BNX2_PORT_HW_CFG_CFG_DFLT_LINK_1G) {
5513 bp->autoneg = 0;
5514 bp->req_line_speed = bp->line_speed = SPEED_1000;
5515 bp->req_duplex = DUPLEX_FULL;
5516 }
b6016b76
MC		 5517 }
5518 else {
5519 bp->advertising = ETHTOOL_ALL_COPPER_SPEED | ADVERTISED_Autoneg;
5520 }
5521
5522 bp->req_flow_ctrl = FLOW_CTRL_RX | FLOW_CTRL_TX;
5523
cd339a0e
MC		 5524 init_timer(&bp->timer);
5525 bp->timer.expires = RUN_AT(bp->timer_interval);
5526 bp->timer.data = (unsigned long) bp;
5527 bp->timer.function = bnx2_timer;
5528
b6016b76
MC		 5529 return 0;
5530
5531err_out_unmap:
5532 if (bp->regview) {
5533 iounmap(bp->regview);
73eef4cd 5534 bp->regview = NULL;
b6016b76
MC		 5535 }
5536
5537err_out_release:
5538 pci_release_regions(pdev);
5539
5540err_out_disable:
5541 pci_disable_device(pdev);
5542 pci_set_drvdata(pdev, NULL);
5543
5544err_out:
5545 return rc;
5546}
5547
5548static int __devinit
5549bnx2_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
5550{
5551 static int version_printed = 0;
5552 struct net_device *dev = NULL;
5553 struct bnx2 *bp;
5554 int rc, i;
5555
5556 if (version_printed++ == 0)
5557 printk(KERN_INFO "%s", version);
5558
5559 /* dev zeroed in init_etherdev */
5560 dev = alloc_etherdev(sizeof(*bp));
5561
5562 if (!dev)
5563 return -ENOMEM;
5564
5565 rc = bnx2_init_board(pdev, dev);
5566 if (rc < 0) {
5567 free_netdev(dev);
5568 return rc;
5569 }
5570
5571 dev->open = bnx2_open;
5572 dev->hard_start_xmit = bnx2_start_xmit;
5573 dev->stop = bnx2_close;
5574 dev->get_stats = bnx2_get_stats;
5575 dev->set_multicast_list = bnx2_set_rx_mode;
5576 dev->do_ioctl = bnx2_ioctl;
5577 dev->set_mac_address = bnx2_change_mac_addr;
5578 dev->change_mtu = bnx2_change_mtu;
5579 dev->tx_timeout = bnx2_tx_timeout;
5580 dev->watchdog_timeo = TX_TIMEOUT;
5581#ifdef BCM_VLAN
5582 dev->vlan_rx_register = bnx2_vlan_rx_register;
5583 dev->vlan_rx_kill_vid = bnx2_vlan_rx_kill_vid;
5584#endif
5585 dev->poll = bnx2_poll;
5586 dev->ethtool_ops = &bnx2_ethtool_ops;
5587 dev->weight = 64;
5588
5589 bp = dev->priv;
5590
5591#if defined(HAVE_POLL_CONTROLLER) || defined(CONFIG_NET_POLL_CONTROLLER)
5592 dev->poll_controller = poll_bnx2;
5593#endif
5594
5595 if ((rc = register_netdev(dev))) {
5596 printk(KERN_ERR PFX "Cannot register net device\n");
5597 if (bp->regview)
5598 iounmap(bp->regview);
5599 pci_release_regions(pdev);
5600 pci_disable_device(pdev);
5601 pci_set_drvdata(pdev, NULL);
5602 free_netdev(dev);
5603 return rc;
5604 }
5605
5606 pci_set_drvdata(pdev, dev);
5607
5608 memcpy(dev->dev_addr, bp->mac_addr, 6);
24b8e05d 5609 memcpy(dev->perm_addr, bp->mac_addr, 6);
b6016b76
MC		 5610 bp->name = board_info[ent->driver_data].name,
5611 printk(KERN_INFO "%s: %s (%c%d) PCI%s %s %dMHz found at mem %lx, "
5612 "IRQ %d, ",
5613 dev->name,
5614 bp->name,
5615 ((CHIP_ID(bp) & 0xf000) >> 12) + 'A',
5616 ((CHIP_ID(bp) & 0x0ff0) >> 4),
5617 ((bp->flags & PCIX_FLAG) ? "-X" : ""),
5618 ((bp->flags & PCI_32BIT_FLAG) ? "32-bit" : "64-bit"),
5619 bp->bus_speed_mhz,
5620 dev->base_addr,
5621 bp->pdev->irq);
5622
5623 printk("node addr ");
5624 for (i = 0; i < 6; i++)
5625 printk("%2.2x", dev->dev_addr[i]);
5626 printk("\n");
5627
5628 dev->features |= NETIF_F_SG;
5629 if (bp->flags & USING_DAC_FLAG)
5630 dev->features |= NETIF_F_HIGHDMA;
5631 dev->features |= NETIF_F_IP_CSUM;
5632#ifdef BCM_VLAN
5633 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
5634#endif
5635#ifdef BCM_TSO
5636 dev->features |= NETIF_F_TSO;
5637#endif
5638
5639 netif_carrier_off(bp->dev);
5640
5641 return 0;
5642}
5643
5644static void __devexit
5645bnx2_remove_one(struct pci_dev *pdev)
5646{
5647 struct net_device *dev = pci_get_drvdata(pdev);
5648 struct bnx2 *bp = dev->priv;
5649
afdc08b9
MC		 5650 flush_scheduled_work();
5651
b6016b76
MC		 5652 unregister_netdev(dev);
5653
5654 if (bp->regview)
5655 iounmap(bp->regview);
5656
5657 free_netdev(dev);
5658 pci_release_regions(pdev);
5659 pci_disable_device(pdev);
5660 pci_set_drvdata(pdev, NULL);
5661}
5662
5663static int
829ca9a3 5664bnx2_suspend(struct pci_dev *pdev, pm_message_t state)
b6016b76
MC		 5665{
5666 struct net_device *dev = pci_get_drvdata(pdev);
5667 struct bnx2 *bp = dev->priv;
5668 u32 reset_code;
5669
5670 if (!netif_running(dev))
5671 return 0;
5672
5673 bnx2_netif_stop(bp);
5674 netif_device_detach(dev);
5675 del_timer_sync(&bp->timer);
5676 if (bp->wol)
5677 reset_code = BNX2_DRV_MSG_CODE_SUSPEND_WOL;
5678 else
5679 reset_code = BNX2_DRV_MSG_CODE_SUSPEND_NO_WOL;
5680 bnx2_reset_chip(bp, reset_code);
5681 bnx2_free_skbs(bp);
829ca9a3 5682 bnx2_set_power_state(bp, pci_choose_state(pdev, state));
b6016b76
MC		 5683 return 0;
5684}
5685
5686static int
5687bnx2_resume(struct pci_dev *pdev)
5688{
5689 struct net_device *dev = pci_get_drvdata(pdev);
5690 struct bnx2 *bp = dev->priv;
5691
5692 if (!netif_running(dev))
5693 return 0;
5694
829ca9a3 5695 bnx2_set_power_state(bp, PCI_D0);
b6016b76
MC		 5696 netif_device_attach(dev);
5697 bnx2_init_nic(bp);
5698 bnx2_netif_start(bp);
5699 return 0;
5700}
5701
5702static struct pci_driver bnx2_pci_driver = {
14ab9b86
PH		 5703 .name = DRV_MODULE_NAME,
5704 .id_table = bnx2_pci_tbl,
5705 .probe = bnx2_init_one,
5706 .remove = __devexit_p(bnx2_remove_one),
5707 .suspend = bnx2_suspend,
5708 .resume = bnx2_resume,
b6016b76
MC		 5709};
5710
5711static int __init bnx2_init(void)
5712{
5713 return pci_module_init(&bnx2_pci_driver);
5714}
5715
5716static void __exit bnx2_cleanup(void)
5717{
5718 pci_unregister_driver(&bnx2_pci_driver);
5719}
5720
5721module_init(bnx2_init);
5722module_exit(bnx2_cleanup);
5723
5724
5725
Linux kernel - Deliverables
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