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[deliverable/linux.git] / drivers / net / bnx2.c
CommitLineData
b6016b76
MC		 1/* bnx2.c: Broadcom NX2 network driver.
2 *
feebb331 3 * Copyright (c) 2004-2008 Broadcom Corporation
b6016b76
MC		 4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
8 *
9 * Written by: Michael Chan (mchan@broadcom.com)
10 */
11
f2a4f052
MC		 12
13#include <linux/module.h>
14#include <linux/moduleparam.h>
15
16#include <linux/kernel.h>
17#include <linux/timer.h>
18#include <linux/errno.h>
19#include <linux/ioport.h>
20#include <linux/slab.h>
21#include <linux/vmalloc.h>
22#include <linux/interrupt.h>
23#include <linux/pci.h>
24#include <linux/init.h>
25#include <linux/netdevice.h>
26#include <linux/etherdevice.h>
27#include <linux/skbuff.h>
28#include <linux/dma-mapping.h>
1977f032 29#include <linux/bitops.h>
f2a4f052
MC		 30#include <asm/io.h>
31#include <asm/irq.h>
32#include <linux/delay.h>
33#include <asm/byteorder.h>
c86a31f4 34#include <asm/page.h>
f2a4f052
MC		 35#include <linux/time.h>
36#include <linux/ethtool.h>
37#include <linux/mii.h>
38#ifdef NETIF_F_HW_VLAN_TX
39#include <linux/if_vlan.h>
40#define BCM_VLAN 1
41#endif
f2a4f052 42#include <net/ip.h>
de081fa5 43#include <net/tcp.h>
f2a4f052 44#include <net/checksum.h>
f2a4f052
MC		 45#include <linux/workqueue.h>
46#include <linux/crc32.h>
47#include <linux/prefetch.h>
29b12174 48#include <linux/cache.h>
fba9fe91 49#include <linux/zlib.h>
f2a4f052 50
b6016b76
MC		 51#include "bnx2.h"
52#include "bnx2_fw.h"
d43584c8 53#include "bnx2_fw2.h"
b6016b76 54
110d0ef9 55#define FW_BUF_SIZE 0x10000
b3448b0b 56
b6016b76
MC		 57#define DRV_MODULE_NAME "bnx2"
58#define PFX DRV_MODULE_NAME ": "
236ae640
MC		 59#define DRV_MODULE_VERSION "1.7.6"
60#define DRV_MODULE_RELDATE "May 16, 2008"
b6016b76
MC		 61
62#define RUN_AT(x) (jiffies + (x))
63
64/* Time in jiffies before concluding the transmitter is hung. */
65#define TX_TIMEOUT (5*HZ)
66
fefa8645 67static char version[] __devinitdata =
b6016b76
MC		 68 "Broadcom NetXtreme II Gigabit Ethernet Driver " DRV_MODULE_NAME " v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
69
70MODULE_AUTHOR("Michael Chan <mchan@broadcom.com>");
05d0f1cf 71MODULE_DESCRIPTION("Broadcom NetXtreme II BCM5706/5708 Driver");
b6016b76
MC		 72MODULE_LICENSE("GPL");
73MODULE_VERSION(DRV_MODULE_VERSION);
74
75static int disable_msi = 0;
76
77module_param(disable_msi, int, 0);
78MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)");
79
80typedef enum {
81 BCM5706 = 0,
82 NC370T,
83 NC370I,
84 BCM5706S,
85 NC370F,
5b0c76ad
MC		 86 BCM5708,
87 BCM5708S,
bac0dff6 88 BCM5709,
27a005b8 89 BCM5709S,
b6016b76
MC		 90} board_t;
91
92/* indexed by board_t, above */
fefa8645 93static struct {
b6016b76
MC		 94 char *name;
95} board_info[] __devinitdata = {
96 { "Broadcom NetXtreme II BCM5706 1000Base-T" },
97 { "HP NC370T Multifunction Gigabit Server Adapter" },
98 { "HP NC370i Multifunction Gigabit Server Adapter" },
99 { "Broadcom NetXtreme II BCM5706 1000Base-SX" },
100 { "HP NC370F Multifunction Gigabit Server Adapter" },
5b0c76ad
MC		 101 { "Broadcom NetXtreme II BCM5708 1000Base-T" },
102 { "Broadcom NetXtreme II BCM5708 1000Base-SX" },
bac0dff6 103 { "Broadcom NetXtreme II BCM5709 1000Base-T" },
27a005b8 104 { "Broadcom NetXtreme II BCM5709 1000Base-SX" },
b6016b76
MC		 105 };
106
107static struct pci_device_id bnx2_pci_tbl[] = {
108 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706,
109 PCI_VENDOR_ID_HP, 0x3101, 0, 0, NC370T },
110 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706,
111 PCI_VENDOR_ID_HP, 0x3106, 0, 0, NC370I },
112 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706,
113 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5706 },
5b0c76ad
MC		 114 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5708,
115 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5708 },
b6016b76
MC		 116 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706S,
117 PCI_VENDOR_ID_HP, 0x3102, 0, 0, NC370F },
118 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706S,
119 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5706S },
5b0c76ad
MC		 120 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5708S,
121 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5708S },
bac0dff6
MC		 122 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5709,
123 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5709 },
27a005b8
MC		 124 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5709S,
125 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5709S },
b6016b76
MC		 126 { 0, }
127};
128
129static struct flash_spec flash_table[] =
130{
e30372c9
MC		 131#define BUFFERED_FLAGS (BNX2_NV_BUFFERED | BNX2_NV_TRANSLATE)
132#define NONBUFFERED_FLAGS (BNX2_NV_WREN)
b6016b76 133 /* Slow EEPROM */
37137709 134 {0x00000000, 0x40830380, 0x009f0081, 0xa184a053, 0xaf000400,
e30372c9 135 BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE,
b6016b76
MC		 136 SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE,
137 "EEPROM - slow"},
37137709
MC		 138 /* Expansion entry 0001 */
139 {0x08000002, 0x4b808201, 0x00050081, 0x03840253, 0xaf020406,
e30372c9 140 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
37137709
MC		 141 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
142 "Entry 0001"},
b6016b76
MC		 143 /* Saifun SA25F010 (non-buffered flash) */
144 /* strap, cfg1, & write1 need updates */
37137709 145 {0x04000001, 0x47808201, 0x00050081, 0x03840253, 0xaf020406,
e30372c9 146 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
b6016b76
MC		 147 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*2,
148 "Non-buffered flash (128kB)"},
149 /* Saifun SA25F020 (non-buffered flash) */
150 /* strap, cfg1, & write1 need updates */
37137709 151 {0x0c000003, 0x4f808201, 0x00050081, 0x03840253, 0xaf020406,
e30372c9 152 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
b6016b76
MC		 153 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*4,
154 "Non-buffered flash (256kB)"},
37137709
MC		 155 /* Expansion entry 0100 */
156 {0x11000000, 0x53808201, 0x00050081, 0x03840253, 0xaf020406,
e30372c9 157 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
37137709
MC		 158 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
159 "Entry 0100"},
160 /* Entry 0101: ST M45PE10 (non-buffered flash, TetonII B0) */
6aa20a22 161 {0x19000002, 0x5b808201, 0x000500db, 0x03840253, 0xaf020406,
e30372c9 162 NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE,
37137709
MC		 163 ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*2,
164 "Entry 0101: ST M45PE10 (128kB non-bufferred)"},
165 /* Entry 0110: ST M45PE20 (non-buffered flash)*/
166 {0x15000001, 0x57808201, 0x000500db, 0x03840253, 0xaf020406,
e30372c9 167 NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE,
37137709
MC		 168 ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*4,
169 "Entry 0110: ST M45PE20 (256kB non-bufferred)"},
170 /* Saifun SA25F005 (non-buffered flash) */
171 /* strap, cfg1, & write1 need updates */
172 {0x1d000003, 0x5f808201, 0x00050081, 0x03840253, 0xaf020406,
e30372c9 173 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
37137709
MC		 174 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE,
175 "Non-buffered flash (64kB)"},
176 /* Fast EEPROM */
177 {0x22000000, 0x62808380, 0x009f0081, 0xa184a053, 0xaf000400,
e30372c9 178 BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE,
37137709
MC		 179 SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE,
180 "EEPROM - fast"},
181 /* Expansion entry 1001 */
182 {0x2a000002, 0x6b808201, 0x00050081, 0x03840253, 0xaf020406,
e30372c9 183 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
37137709
MC		 184 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
185 "Entry 1001"},
186 /* Expansion entry 1010 */
187 {0x26000001, 0x67808201, 0x00050081, 0x03840253, 0xaf020406,
e30372c9 188 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
37137709
MC		 189 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
190 "Entry 1010"},
191 /* ATMEL AT45DB011B (buffered flash) */
192 {0x2e000003, 0x6e808273, 0x00570081, 0x68848353, 0xaf000400,
e30372c9 193 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
37137709
MC		 194 BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE,
195 "Buffered flash (128kB)"},
196 /* Expansion entry 1100 */
197 {0x33000000, 0x73808201, 0x00050081, 0x03840253, 0xaf020406,
e30372c9 198 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
37137709
MC		 199 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
200 "Entry 1100"},
201 /* Expansion entry 1101 */
202 {0x3b000002, 0x7b808201, 0x00050081, 0x03840253, 0xaf020406,
e30372c9 203 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
37137709
MC		 204 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
205 "Entry 1101"},
206 /* Ateml Expansion entry 1110 */
207 {0x37000001, 0x76808273, 0x00570081, 0x68848353, 0xaf000400,
e30372c9 208 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
37137709
MC		 209 BUFFERED_FLASH_BYTE_ADDR_MASK, 0,
210 "Entry 1110 (Atmel)"},
211 /* ATMEL AT45DB021B (buffered flash) */
212 {0x3f000003, 0x7e808273, 0x00570081, 0x68848353, 0xaf000400,
e30372c9 213 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
37137709
MC		 214 BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE*2,
215 "Buffered flash (256kB)"},
b6016b76
MC		 216};
217
e30372c9
MC		 218static struct flash_spec flash_5709 = {
219 .flags = BNX2_NV_BUFFERED,
220 .page_bits = BCM5709_FLASH_PAGE_BITS,
221 .page_size = BCM5709_FLASH_PAGE_SIZE,
222 .addr_mask = BCM5709_FLASH_BYTE_ADDR_MASK,
223 .total_size = BUFFERED_FLASH_TOTAL_SIZE*2,
224 .name = "5709 Buffered flash (256kB)",
225};
226
b6016b76
MC		 227MODULE_DEVICE_TABLE(pci, bnx2_pci_tbl);
228
a550c99b 229static inline u32 bnx2_tx_avail(struct bnx2 *bp, struct bnx2_napi *bnapi)
e89bbf10 230{
2f8af120 231 u32 diff;
e89bbf10 232
2f8af120 233 smp_mb();
faac9c4b
MC		 234
235 /* The ring uses 256 indices for 255 entries, one of them
236 * needs to be skipped.
237 */
a550c99b 238 diff = bp->tx_prod - bnapi->tx_cons;
faac9c4b
MC		 239 if (unlikely(diff >= TX_DESC_CNT)) {
240 diff &= 0xffff;
241 if (diff == TX_DESC_CNT)
242 diff = MAX_TX_DESC_CNT;
243 }
e89bbf10
MC		 244 return (bp->tx_ring_size - diff);
245}
246
b6016b76
MC		 247static u32
248bnx2_reg_rd_ind(struct bnx2 *bp, u32 offset)
249{
1b8227c4
MC		 250 u32 val;
251
252 spin_lock_bh(&bp->indirect_lock);
b6016b76 253 REG_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, offset);
1b8227c4
MC		 254 val = REG_RD(bp, BNX2_PCICFG_REG_WINDOW);
255 spin_unlock_bh(&bp->indirect_lock);
256 return val;
b6016b76
MC		 257}
258
259static void
260bnx2_reg_wr_ind(struct bnx2 *bp, u32 offset, u32 val)
261{
1b8227c4 262 spin_lock_bh(&bp->indirect_lock);
b6016b76
MC		 263 REG_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, offset);
264 REG_WR(bp, BNX2_PCICFG_REG_WINDOW, val);
1b8227c4 265 spin_unlock_bh(&bp->indirect_lock);
b6016b76
MC		 266}
267
2726d6e1
MC		 268static void
269bnx2_shmem_wr(struct bnx2 *bp, u32 offset, u32 val)
270{
271 bnx2_reg_wr_ind(bp, bp->shmem_base + offset, val);
272}
273
274static u32
275bnx2_shmem_rd(struct bnx2 *bp, u32 offset)
276{
277 return (bnx2_reg_rd_ind(bp, bp->shmem_base + offset));
278}
279
b6016b76
MC		 280static void
281bnx2_ctx_wr(struct bnx2 *bp, u32 cid_addr, u32 offset, u32 val)
282{
283 offset += cid_addr;
1b8227c4 284 spin_lock_bh(&bp->indirect_lock);
59b47d8a
MC		 285 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
286 int i;
287
288 REG_WR(bp, BNX2_CTX_CTX_DATA, val);
289 REG_WR(bp, BNX2_CTX_CTX_CTRL,
290 offset | BNX2_CTX_CTX_CTRL_WRITE_REQ);
291 for (i = 0; i < 5; i++) {
292 u32 val;
293 val = REG_RD(bp, BNX2_CTX_CTX_CTRL);
294 if ((val & BNX2_CTX_CTX_CTRL_WRITE_REQ) == 0)
295 break;
296 udelay(5);
297 }
298 } else {
299 REG_WR(bp, BNX2_CTX_DATA_ADR, offset);
300 REG_WR(bp, BNX2_CTX_DATA, val);
301 }
1b8227c4 302 spin_unlock_bh(&bp->indirect_lock);
b6016b76
MC		 303}
304
305static int
306bnx2_read_phy(struct bnx2 *bp, u32 reg, u32 *val)
307{
308 u32 val1;
309 int i, ret;
310
583c28e5 311 if (bp->phy_flags & BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING) {
b6016b76
MC		 312 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
313 val1 &= ~BNX2_EMAC_MDIO_MODE_AUTO_POLL;
314
315 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
316 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
317
318 udelay(40);
319 }
320
321 val1 = (bp->phy_addr << 21) | (reg << 16) |
322 BNX2_EMAC_MDIO_COMM_COMMAND_READ | BNX2_EMAC_MDIO_COMM_DISEXT |
323 BNX2_EMAC_MDIO_COMM_START_BUSY;
324 REG_WR(bp, BNX2_EMAC_MDIO_COMM, val1);
325
326 for (i = 0; i < 50; i++) {
327 udelay(10);
328
329 val1 = REG_RD(bp, BNX2_EMAC_MDIO_COMM);
330 if (!(val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)) {
331 udelay(5);
332
333 val1 = REG_RD(bp, BNX2_EMAC_MDIO_COMM);
334 val1 &= BNX2_EMAC_MDIO_COMM_DATA;
335
336 break;
337 }
338 }
339
340 if (val1 & BNX2_EMAC_MDIO_COMM_START_BUSY) {
341 *val = 0x0;
342 ret = -EBUSY;
343 }
344 else {
345 *val = val1;
346 ret = 0;
347 }
348
583c28e5 349 if (bp->phy_flags & BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING) {
b6016b76
MC		 350 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
351 val1 |= BNX2_EMAC_MDIO_MODE_AUTO_POLL;
352
353 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
354 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
355
356 udelay(40);
357 }
358
359 return ret;
360}
361
362static int
363bnx2_write_phy(struct bnx2 *bp, u32 reg, u32 val)
364{
365 u32 val1;
366 int i, ret;
367
583c28e5 368 if (bp->phy_flags & BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING) {
b6016b76
MC		 369 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
370 val1 &= ~BNX2_EMAC_MDIO_MODE_AUTO_POLL;
371
372 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
373 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
374
375 udelay(40);
376 }
377
378 val1 = (bp->phy_addr << 21) | (reg << 16) | val |
379 BNX2_EMAC_MDIO_COMM_COMMAND_WRITE |
380 BNX2_EMAC_MDIO_COMM_START_BUSY | BNX2_EMAC_MDIO_COMM_DISEXT;
381 REG_WR(bp, BNX2_EMAC_MDIO_COMM, val1);
6aa20a22 382
b6016b76
MC		 383 for (i = 0; i < 50; i++) {
384 udelay(10);
385
386 val1 = REG_RD(bp, BNX2_EMAC_MDIO_COMM);
387 if (!(val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)) {
388 udelay(5);
389 break;
390 }
391 }
392
393 if (val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)
394 ret = -EBUSY;
395 else
396 ret = 0;
397
583c28e5 398 if (bp->phy_flags & BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING) {
b6016b76
MC		 399 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
400 val1 |= BNX2_EMAC_MDIO_MODE_AUTO_POLL;
401
402 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
403 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
404
405 udelay(40);
406 }
407
408 return ret;
409}
410
411static void
412bnx2_disable_int(struct bnx2 *bp)
413{
b4b36042
MC		 414 int i;
415 struct bnx2_napi *bnapi;
416
417 for (i = 0; i < bp->irq_nvecs; i++) {
418 bnapi = &bp->bnx2_napi[i];
419 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num |
420 BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
421 }
b6016b76
MC		 422 REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD);
423}
424
425static void
426bnx2_enable_int(struct bnx2 *bp)
427{
b4b36042
MC		 428 int i;
429 struct bnx2_napi *bnapi;
35efa7c1 430
b4b36042
MC		 431 for (i = 0; i < bp->irq_nvecs; i++) {
432 bnapi = &bp->bnx2_napi[i];
1269a8a6 433
b4b36042
MC		 434 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num |
435 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
436 BNX2_PCICFG_INT_ACK_CMD_MASK_INT |
437 bnapi->last_status_idx);
b6016b76 438
b4b36042
MC		 439 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num |
440 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
441 bnapi->last_status_idx);
442 }
bf5295bb 443 REG_WR(bp, BNX2_HC_COMMAND, bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW);
b6016b76
MC		 444}
445
446static void
447bnx2_disable_int_sync(struct bnx2 *bp)
448{
b4b36042
MC		 449 int i;
450
b6016b76
MC		 451 atomic_inc(&bp->intr_sem);
452 bnx2_disable_int(bp);
b4b36042
MC		 453 for (i = 0; i < bp->irq_nvecs; i++)
454 synchronize_irq(bp->irq_tbl[i].vector);
b6016b76
MC		 455}
456
35efa7c1
MC		 457static void
458bnx2_napi_disable(struct bnx2 *bp)
459{
b4b36042
MC		 460 int i;
461
462 for (i = 0; i < bp->irq_nvecs; i++)
463 napi_disable(&bp->bnx2_napi[i].napi);
35efa7c1
MC		 464}
465
466static void
467bnx2_napi_enable(struct bnx2 *bp)
468{
b4b36042
MC		 469 int i;
470
471 for (i = 0; i < bp->irq_nvecs; i++)
472 napi_enable(&bp->bnx2_napi[i].napi);
35efa7c1
MC		 473}
474
b6016b76
MC		 475static void
476bnx2_netif_stop(struct bnx2 *bp)
477{
478 bnx2_disable_int_sync(bp);
479 if (netif_running(bp->dev)) {
35efa7c1 480 bnx2_napi_disable(bp);
b6016b76
MC		 481 netif_tx_disable(bp->dev);
482 bp->dev->trans_start = jiffies; /* prevent tx timeout */
483 }
484}
485
486static void
487bnx2_netif_start(struct bnx2 *bp)
488{
489 if (atomic_dec_and_test(&bp->intr_sem)) {
490 if (netif_running(bp->dev)) {
491 netif_wake_queue(bp->dev);
35efa7c1 492 bnx2_napi_enable(bp);
b6016b76
MC		 493 bnx2_enable_int(bp);
494 }
495 }
496}
497
498static void
499bnx2_free_mem(struct bnx2 *bp)
500{
13daffa2
MC		 501 int i;
502
59b47d8a
MC		 503 for (i = 0; i < bp->ctx_pages; i++) {
504 if (bp->ctx_blk[i]) {
505 pci_free_consistent(bp->pdev, BCM_PAGE_SIZE,
506 bp->ctx_blk[i],
507 bp->ctx_blk_mapping[i]);
508 bp->ctx_blk[i] = NULL;
509 }
510 }
b6016b76 511 if (bp->status_blk) {
0f31f994 512 pci_free_consistent(bp->pdev, bp->status_stats_size,
b6016b76
MC		 513 bp->status_blk, bp->status_blk_mapping);
514 bp->status_blk = NULL;
0f31f994 515 bp->stats_blk = NULL;
b6016b76
MC		 516 }
517 if (bp->tx_desc_ring) {
e343d55c 518 pci_free_consistent(bp->pdev, TXBD_RING_SIZE,
b6016b76
MC		 519 bp->tx_desc_ring, bp->tx_desc_mapping);
520 bp->tx_desc_ring = NULL;
521 }
b4558ea9
JJ		 522 kfree(bp->tx_buf_ring);
523 bp->tx_buf_ring = NULL;
13daffa2
MC		 524 for (i = 0; i < bp->rx_max_ring; i++) {
525 if (bp->rx_desc_ring[i])
e343d55c 526 pci_free_consistent(bp->pdev, RXBD_RING_SIZE,
13daffa2
MC		 527 bp->rx_desc_ring[i],
528 bp->rx_desc_mapping[i]);
529 bp->rx_desc_ring[i] = NULL;
530 }
531 vfree(bp->rx_buf_ring);
b4558ea9 532 bp->rx_buf_ring = NULL;
47bf4246
MC		 533 for (i = 0; i < bp->rx_max_pg_ring; i++) {
534 if (bp->rx_pg_desc_ring[i])
535 pci_free_consistent(bp->pdev, RXBD_RING_SIZE,
536 bp->rx_pg_desc_ring[i],
537 bp->rx_pg_desc_mapping[i]);
538 bp->rx_pg_desc_ring[i] = NULL;
539 }
540 if (bp->rx_pg_ring)
541 vfree(bp->rx_pg_ring);
542 bp->rx_pg_ring = NULL;
b6016b76
MC		 543}
544
545static int
546bnx2_alloc_mem(struct bnx2 *bp)
547{
0f31f994 548 int i, status_blk_size;
13daffa2 549
e343d55c 550 bp->tx_buf_ring = kzalloc(SW_TXBD_RING_SIZE, GFP_KERNEL);
b6016b76
MC		 551 if (bp->tx_buf_ring == NULL)
552 return -ENOMEM;
553
e343d55c 554 bp->tx_desc_ring = pci_alloc_consistent(bp->pdev, TXBD_RING_SIZE,
b6016b76
MC		 555 &bp->tx_desc_mapping);
556 if (bp->tx_desc_ring == NULL)
557 goto alloc_mem_err;
558
e343d55c 559 bp->rx_buf_ring = vmalloc(SW_RXBD_RING_SIZE * bp->rx_max_ring);
b6016b76
MC		 560 if (bp->rx_buf_ring == NULL)
561 goto alloc_mem_err;
562
e343d55c 563 memset(bp->rx_buf_ring, 0, SW_RXBD_RING_SIZE * bp->rx_max_ring);
13daffa2
MC		 564
565 for (i = 0; i < bp->rx_max_ring; i++) {
566 bp->rx_desc_ring[i] =
e343d55c 567 pci_alloc_consistent(bp->pdev, RXBD_RING_SIZE,
13daffa2
MC		 568 &bp->rx_desc_mapping[i]);
569 if (bp->rx_desc_ring[i] == NULL)
570 goto alloc_mem_err;
571
572 }
b6016b76 573
47bf4246
MC		 574 if (bp->rx_pg_ring_size) {
575 bp->rx_pg_ring = vmalloc(SW_RXPG_RING_SIZE *
576 bp->rx_max_pg_ring);
577 if (bp->rx_pg_ring == NULL)
578 goto alloc_mem_err;
579
580 memset(bp->rx_pg_ring, 0, SW_RXPG_RING_SIZE *
581 bp->rx_max_pg_ring);
582 }
583
584 for (i = 0; i < bp->rx_max_pg_ring; i++) {
585 bp->rx_pg_desc_ring[i] =
586 pci_alloc_consistent(bp->pdev, RXBD_RING_SIZE,
587 &bp->rx_pg_desc_mapping[i]);
588 if (bp->rx_pg_desc_ring[i] == NULL)
589 goto alloc_mem_err;
590
591 }
592
0f31f994
MC		 593 /* Combine status and statistics blocks into one allocation. */
594 status_blk_size = L1_CACHE_ALIGN(sizeof(struct status_block));
f86e82fb 595 if (bp->flags & BNX2_FLAG_MSIX_CAP)
b4b36042
MC		 596 status_blk_size = L1_CACHE_ALIGN(BNX2_MAX_MSIX_HW_VEC *
597 BNX2_SBLK_MSIX_ALIGN_SIZE);
0f31f994
MC		 598 bp->status_stats_size = status_blk_size +
599 sizeof(struct statistics_block);
600
601 bp->status_blk = pci_alloc_consistent(bp->pdev, bp->status_stats_size,
b6016b76
MC		 602 &bp->status_blk_mapping);
603 if (bp->status_blk == NULL)
604 goto alloc_mem_err;
605
0f31f994 606 memset(bp->status_blk, 0, bp->status_stats_size);
b6016b76 607
b4b36042 608 bp->bnx2_napi[0].status_blk = bp->status_blk;
f86e82fb 609 if (bp->flags & BNX2_FLAG_MSIX_CAP) {
b4b36042
MC		 610 for (i = 1; i < BNX2_MAX_MSIX_VEC; i++) {
611 struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
612
57851d84 613 bnapi->status_blk_msix = (void *)
b4b36042
MC		 614 ((unsigned long) bp->status_blk +
615 BNX2_SBLK_MSIX_ALIGN_SIZE * i);
616 bnapi->int_num = i << 24;
617 }
618 }
35efa7c1 619
0f31f994
MC		 620 bp->stats_blk = (void *) ((unsigned long) bp->status_blk +
621 status_blk_size);
b6016b76 622
0f31f994 623 bp->stats_blk_mapping = bp->status_blk_mapping + status_blk_size;
b6016b76 624
59b47d8a
MC		 625 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
626 bp->ctx_pages = 0x2000 / BCM_PAGE_SIZE;
627 if (bp->ctx_pages == 0)
628 bp->ctx_pages = 1;
629 for (i = 0; i < bp->ctx_pages; i++) {
630 bp->ctx_blk[i] = pci_alloc_consistent(bp->pdev,
631 BCM_PAGE_SIZE,
632 &bp->ctx_blk_mapping[i]);
633 if (bp->ctx_blk[i] == NULL)
634 goto alloc_mem_err;
635 }
636 }
b6016b76
MC		 637 return 0;
638
639alloc_mem_err:
640 bnx2_free_mem(bp);
641 return -ENOMEM;
642}
643
e3648b3d
MC		 644static void
645bnx2_report_fw_link(struct bnx2 *bp)
646{
647 u32 fw_link_status = 0;
648
583c28e5 649 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
0d8a6571
MC		 650 return;
651
e3648b3d
MC		 652 if (bp->link_up) {
653 u32 bmsr;
654
655 switch (bp->line_speed) {
656 case SPEED_10:
657 if (bp->duplex == DUPLEX_HALF)
658 fw_link_status = BNX2_LINK_STATUS_10HALF;
659 else
660 fw_link_status = BNX2_LINK_STATUS_10FULL;
661 break;
662 case SPEED_100:
663 if (bp->duplex == DUPLEX_HALF)
664 fw_link_status = BNX2_LINK_STATUS_100HALF;
665 else
666 fw_link_status = BNX2_LINK_STATUS_100FULL;
667 break;
668 case SPEED_1000:
669 if (bp->duplex == DUPLEX_HALF)
670 fw_link_status = BNX2_LINK_STATUS_1000HALF;
671 else
672 fw_link_status = BNX2_LINK_STATUS_1000FULL;
673 break;
674 case SPEED_2500:
675 if (bp->duplex == DUPLEX_HALF)
676 fw_link_status = BNX2_LINK_STATUS_2500HALF;
677 else
678 fw_link_status = BNX2_LINK_STATUS_2500FULL;
679 break;
680 }
681
682 fw_link_status |= BNX2_LINK_STATUS_LINK_UP;
683
684 if (bp->autoneg) {
685 fw_link_status |= BNX2_LINK_STATUS_AN_ENABLED;
686
ca58c3af
MC		 687 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
688 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
e3648b3d
MC		 689
690 if (!(bmsr & BMSR_ANEGCOMPLETE) ||
583c28e5 691 bp->phy_flags & BNX2_PHY_FLAG_PARALLEL_DETECT)
e3648b3d
MC		 692 fw_link_status |= BNX2_LINK_STATUS_PARALLEL_DET;
693 else
694 fw_link_status |= BNX2_LINK_STATUS_AN_COMPLETE;
695 }
696 }
697 else
698 fw_link_status = BNX2_LINK_STATUS_LINK_DOWN;
699
2726d6e1 700 bnx2_shmem_wr(bp, BNX2_LINK_STATUS, fw_link_status);
e3648b3d
MC		 701}
702
9b1084b8
MC		 703static char *
704bnx2_xceiver_str(struct bnx2 *bp)
705{
706 return ((bp->phy_port == PORT_FIBRE) ? "SerDes" :
583c28e5 707 ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) ? "Remote Copper" :
9b1084b8
MC		 708 "Copper"));
709}
710
b6016b76
MC		 711static void
712bnx2_report_link(struct bnx2 *bp)
713{
714 if (bp->link_up) {
715 netif_carrier_on(bp->dev);
9b1084b8
MC		 716 printk(KERN_INFO PFX "%s NIC %s Link is Up, ", bp->dev->name,
717 bnx2_xceiver_str(bp));
b6016b76
MC		 718
719 printk("%d Mbps ", bp->line_speed);
720
721 if (bp->duplex == DUPLEX_FULL)
722 printk("full duplex");
723 else
724 printk("half duplex");
725
726 if (bp->flow_ctrl) {
727 if (bp->flow_ctrl & FLOW_CTRL_RX) {
728 printk(", receive ");
729 if (bp->flow_ctrl & FLOW_CTRL_TX)
730 printk("& transmit ");
731 }
732 else {
733 printk(", transmit ");
734 }
735 printk("flow control ON");
736 }
737 printk("\n");
738 }
739 else {
740 netif_carrier_off(bp->dev);
9b1084b8
MC		 741 printk(KERN_ERR PFX "%s NIC %s Link is Down\n", bp->dev->name,
742 bnx2_xceiver_str(bp));
b6016b76 743 }
e3648b3d
MC		 744
745 bnx2_report_fw_link(bp);
b6016b76
MC		 746}
747
748static void
749bnx2_resolve_flow_ctrl(struct bnx2 *bp)
750{
751 u32 local_adv, remote_adv;
752
753 bp->flow_ctrl = 0;
6aa20a22 754 if ((bp->autoneg & (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) !=
b6016b76
MC		 755 (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) {
756
757 if (bp->duplex == DUPLEX_FULL) {
758 bp->flow_ctrl = bp->req_flow_ctrl;
759 }
760 return;
761 }
762
763 if (bp->duplex != DUPLEX_FULL) {
764 return;
765 }
766
583c28e5 767 if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
5b0c76ad
MC		 768 (CHIP_NUM(bp) == CHIP_NUM_5708)) {
769 u32 val;
770
771 bnx2_read_phy(bp, BCM5708S_1000X_STAT1, &val);
772 if (val & BCM5708S_1000X_STAT1_TX_PAUSE)
773 bp->flow_ctrl |= FLOW_CTRL_TX;
774 if (val & BCM5708S_1000X_STAT1_RX_PAUSE)
775 bp->flow_ctrl |= FLOW_CTRL_RX;
776 return;
777 }
778
ca58c3af
MC		 779 bnx2_read_phy(bp, bp->mii_adv, &local_adv);
780 bnx2_read_phy(bp, bp->mii_lpa, &remote_adv);
b6016b76 781
583c28e5 782 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
b6016b76
MC		 783 u32 new_local_adv = 0;
784 u32 new_remote_adv = 0;
785
786 if (local_adv & ADVERTISE_1000XPAUSE)
787 new_local_adv |= ADVERTISE_PAUSE_CAP;
788 if (local_adv & ADVERTISE_1000XPSE_ASYM)
789 new_local_adv |= ADVERTISE_PAUSE_ASYM;
790 if (remote_adv & ADVERTISE_1000XPAUSE)
791 new_remote_adv |= ADVERTISE_PAUSE_CAP;
792 if (remote_adv & ADVERTISE_1000XPSE_ASYM)
793 new_remote_adv |= ADVERTISE_PAUSE_ASYM;
794
795 local_adv = new_local_adv;
796 remote_adv = new_remote_adv;
797 }
798
799 /* See Table 28B-3 of 802.3ab-1999 spec. */
800 if (local_adv & ADVERTISE_PAUSE_CAP) {
801 if(local_adv & ADVERTISE_PAUSE_ASYM) {
802 if (remote_adv & ADVERTISE_PAUSE_CAP) {
803 bp->flow_ctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
804 }
805 else if (remote_adv & ADVERTISE_PAUSE_ASYM) {
806 bp->flow_ctrl = FLOW_CTRL_RX;
807 }
808 }
809 else {
810 if (remote_adv & ADVERTISE_PAUSE_CAP) {
811 bp->flow_ctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
812 }
813 }
814 }
815 else if (local_adv & ADVERTISE_PAUSE_ASYM) {
816 if ((remote_adv & ADVERTISE_PAUSE_CAP) &&
817 (remote_adv & ADVERTISE_PAUSE_ASYM)) {
818
819 bp->flow_ctrl = FLOW_CTRL_TX;
820 }
821 }
822}
823
27a005b8
MC		 824static int
825bnx2_5709s_linkup(struct bnx2 *bp)
826{
827 u32 val, speed;
828
829 bp->link_up = 1;
830
831 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_GP_STATUS);
832 bnx2_read_phy(bp, MII_BNX2_GP_TOP_AN_STATUS1, &val);
833 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
834
835 if ((bp->autoneg & AUTONEG_SPEED) == 0) {
836 bp->line_speed = bp->req_line_speed;
837 bp->duplex = bp->req_duplex;
838 return 0;
839 }
840 speed = val & MII_BNX2_GP_TOP_AN_SPEED_MSK;
841 switch (speed) {
842 case MII_BNX2_GP_TOP_AN_SPEED_10:
843 bp->line_speed = SPEED_10;
844 break;
845 case MII_BNX2_GP_TOP_AN_SPEED_100:
846 bp->line_speed = SPEED_100;
847 break;
848 case MII_BNX2_GP_TOP_AN_SPEED_1G:
849 case MII_BNX2_GP_TOP_AN_SPEED_1GKV:
850 bp->line_speed = SPEED_1000;
851 break;
852 case MII_BNX2_GP_TOP_AN_SPEED_2_5G:
853 bp->line_speed = SPEED_2500;
854 break;
855 }
856 if (val & MII_BNX2_GP_TOP_AN_FD)
857 bp->duplex = DUPLEX_FULL;
858 else
859 bp->duplex = DUPLEX_HALF;
860 return 0;
861}
862
b6016b76 863static int
5b0c76ad
MC		 864bnx2_5708s_linkup(struct bnx2 *bp)
865{
866 u32 val;
867
868 bp->link_up = 1;
869 bnx2_read_phy(bp, BCM5708S_1000X_STAT1, &val);
870 switch (val & BCM5708S_1000X_STAT1_SPEED_MASK) {
871 case BCM5708S_1000X_STAT1_SPEED_10:
872 bp->line_speed = SPEED_10;
873 break;
874 case BCM5708S_1000X_STAT1_SPEED_100:
875 bp->line_speed = SPEED_100;
876 break;
877 case BCM5708S_1000X_STAT1_SPEED_1G:
878 bp->line_speed = SPEED_1000;
879 break;
880 case BCM5708S_1000X_STAT1_SPEED_2G5:
881 bp->line_speed = SPEED_2500;
882 break;
883 }
884 if (val & BCM5708S_1000X_STAT1_FD)
885 bp->duplex = DUPLEX_FULL;
886 else
887 bp->duplex = DUPLEX_HALF;
888
889 return 0;
890}
891
892static int
893bnx2_5706s_linkup(struct bnx2 *bp)
b6016b76
MC		 894{
895 u32 bmcr, local_adv, remote_adv, common;
896
897 bp->link_up = 1;
898 bp->line_speed = SPEED_1000;
899
ca58c3af 900 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
b6016b76
MC		 901 if (bmcr & BMCR_FULLDPLX) {
902 bp->duplex = DUPLEX_FULL;
903 }
904 else {
905 bp->duplex = DUPLEX_HALF;
906 }
907
908 if (!(bmcr & BMCR_ANENABLE)) {
909 return 0;
910 }
911
ca58c3af
MC		 912 bnx2_read_phy(bp, bp->mii_adv, &local_adv);
913 bnx2_read_phy(bp, bp->mii_lpa, &remote_adv);
b6016b76
MC		 914
915 common = local_adv & remote_adv;
916 if (common & (ADVERTISE_1000XHALF | ADVERTISE_1000XFULL)) {
917
918 if (common & ADVERTISE_1000XFULL) {
919 bp->duplex = DUPLEX_FULL;
920 }
921 else {
922 bp->duplex = DUPLEX_HALF;
923 }
924 }
925
926 return 0;
927}
928
929static int
930bnx2_copper_linkup(struct bnx2 *bp)
931{
932 u32 bmcr;
933
ca58c3af 934 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
b6016b76
MC		 935 if (bmcr & BMCR_ANENABLE) {
936 u32 local_adv, remote_adv, common;
937
938 bnx2_read_phy(bp, MII_CTRL1000, &local_adv);
939 bnx2_read_phy(bp, MII_STAT1000, &remote_adv);
940
941 common = local_adv & (remote_adv >> 2);
942 if (common & ADVERTISE_1000FULL) {
943 bp->line_speed = SPEED_1000;
944 bp->duplex = DUPLEX_FULL;
945 }
946 else if (common & ADVERTISE_1000HALF) {
947 bp->line_speed = SPEED_1000;
948 bp->duplex = DUPLEX_HALF;
949 }
950 else {
ca58c3af
MC		 951 bnx2_read_phy(bp, bp->mii_adv, &local_adv);
952 bnx2_read_phy(bp, bp->mii_lpa, &remote_adv);
b6016b76
MC		 953
954 common = local_adv & remote_adv;
955 if (common & ADVERTISE_100FULL) {
956 bp->line_speed = SPEED_100;
957 bp->duplex = DUPLEX_FULL;
958 }
959 else if (common & ADVERTISE_100HALF) {
960 bp->line_speed = SPEED_100;
961 bp->duplex = DUPLEX_HALF;
962 }
963 else if (common & ADVERTISE_10FULL) {
964 bp->line_speed = SPEED_10;
965 bp->duplex = DUPLEX_FULL;
966 }
967 else if (common & ADVERTISE_10HALF) {
968 bp->line_speed = SPEED_10;
969 bp->duplex = DUPLEX_HALF;
970 }
971 else {
972 bp->line_speed = 0;
973 bp->link_up = 0;
974 }
975 }
976 }
977 else {
978 if (bmcr & BMCR_SPEED100) {
979 bp->line_speed = SPEED_100;
980 }
981 else {
982 bp->line_speed = SPEED_10;
983 }
984 if (bmcr & BMCR_FULLDPLX) {
985 bp->duplex = DUPLEX_FULL;
986 }
987 else {
988 bp->duplex = DUPLEX_HALF;
989 }
990 }
991
992 return 0;
993}
994
83e3fc89
MC		 995static void
996bnx2_init_rx_context0(struct bnx2 *bp)
997{
998 u32 val, rx_cid_addr = GET_CID_ADDR(RX_CID);
999
1000 val = BNX2_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE;
1001 val |= BNX2_L2CTX_CTX_TYPE_SIZE_L2;
1002 val |= 0x02 << 8;
1003
1004 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
1005 u32 lo_water, hi_water;
1006
1007 if (bp->flow_ctrl & FLOW_CTRL_TX)
1008 lo_water = BNX2_L2CTX_LO_WATER_MARK_DEFAULT;
1009 else
1010 lo_water = BNX2_L2CTX_LO_WATER_MARK_DIS;
1011 if (lo_water >= bp->rx_ring_size)
1012 lo_water = 0;
1013
1014 hi_water = bp->rx_ring_size / 4;
1015
1016 if (hi_water <= lo_water)
1017 lo_water = 0;
1018
1019 hi_water /= BNX2_L2CTX_HI_WATER_MARK_SCALE;
1020 lo_water /= BNX2_L2CTX_LO_WATER_MARK_SCALE;
1021
1022 if (hi_water > 0xf)
1023 hi_water = 0xf;
1024 else if (hi_water == 0)
1025 lo_water = 0;
1026 val |= lo_water | (hi_water << BNX2_L2CTX_HI_WATER_MARK_SHIFT);
1027 }
1028 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_CTX_TYPE, val);
1029}
1030
b6016b76
MC		 1031static int
1032bnx2_set_mac_link(struct bnx2 *bp)
1033{
1034 u32 val;
1035
1036 REG_WR(bp, BNX2_EMAC_TX_LENGTHS, 0x2620);
1037 if (bp->link_up && (bp->line_speed == SPEED_1000) &&
1038 (bp->duplex == DUPLEX_HALF)) {
1039 REG_WR(bp, BNX2_EMAC_TX_LENGTHS, 0x26ff);
1040 }
1041
1042 /* Configure the EMAC mode register. */
1043 val = REG_RD(bp, BNX2_EMAC_MODE);
1044
1045 val &= ~(BNX2_EMAC_MODE_PORT | BNX2_EMAC_MODE_HALF_DUPLEX |
5b0c76ad 1046 BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK |
59b47d8a 1047 BNX2_EMAC_MODE_25G_MODE);
b6016b76
MC		 1048
1049 if (bp->link_up) {
5b0c76ad
MC		 1050 switch (bp->line_speed) {
1051 case SPEED_10:
59b47d8a
MC		 1052 if (CHIP_NUM(bp) != CHIP_NUM_5706) {
1053 val |= BNX2_EMAC_MODE_PORT_MII_10M;
5b0c76ad
MC		 1054 break;
1055 }
1056 /* fall through */
1057 case SPEED_100:
1058 val |= BNX2_EMAC_MODE_PORT_MII;
1059 break;
1060 case SPEED_2500:
59b47d8a 1061 val |= BNX2_EMAC_MODE_25G_MODE;
5b0c76ad
MC		 1062 /* fall through */
1063 case SPEED_1000:
1064 val |= BNX2_EMAC_MODE_PORT_GMII;
1065 break;
1066 }
b6016b76
MC		 1067 }
1068 else {
1069 val |= BNX2_EMAC_MODE_PORT_GMII;
1070 }
1071
1072 /* Set the MAC to operate in the appropriate duplex mode. */
1073 if (bp->duplex == DUPLEX_HALF)
1074 val |= BNX2_EMAC_MODE_HALF_DUPLEX;
1075 REG_WR(bp, BNX2_EMAC_MODE, val);
1076
1077 /* Enable/disable rx PAUSE. */
1078 bp->rx_mode &= ~BNX2_EMAC_RX_MODE_FLOW_EN;
1079
1080 if (bp->flow_ctrl & FLOW_CTRL_RX)
1081 bp->rx_mode |= BNX2_EMAC_RX_MODE_FLOW_EN;
1082 REG_WR(bp, BNX2_EMAC_RX_MODE, bp->rx_mode);
1083
1084 /* Enable/disable tx PAUSE. */
1085 val = REG_RD(bp, BNX2_EMAC_TX_MODE);
1086 val &= ~BNX2_EMAC_TX_MODE_FLOW_EN;
1087
1088 if (bp->flow_ctrl & FLOW_CTRL_TX)
1089 val |= BNX2_EMAC_TX_MODE_FLOW_EN;
1090 REG_WR(bp, BNX2_EMAC_TX_MODE, val);
1091
1092 /* Acknowledge the interrupt. */
1093 REG_WR(bp, BNX2_EMAC_STATUS, BNX2_EMAC_STATUS_LINK_CHANGE);
1094
83e3fc89
MC		 1095 if (CHIP_NUM(bp) == CHIP_NUM_5709)
1096 bnx2_init_rx_context0(bp);
1097
b6016b76
MC		 1098 return 0;
1099}
1100
27a005b8
MC		 1101static void
1102bnx2_enable_bmsr1(struct bnx2 *bp)
1103{
583c28e5 1104 if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
27a005b8
MC		 1105 (CHIP_NUM(bp) == CHIP_NUM_5709))
1106 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1107 MII_BNX2_BLK_ADDR_GP_STATUS);
1108}
1109
1110static void
1111bnx2_disable_bmsr1(struct bnx2 *bp)
1112{
583c28e5 1113 if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
27a005b8
MC		 1114 (CHIP_NUM(bp) == CHIP_NUM_5709))
1115 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1116 MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1117}
1118
605a9e20
MC		 1119static int
1120bnx2_test_and_enable_2g5(struct bnx2 *bp)
1121{
1122 u32 up1;
1123 int ret = 1;
1124
583c28e5 1125 if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))
605a9e20
MC		 1126 return 0;
1127
1128 if (bp->autoneg & AUTONEG_SPEED)
1129 bp->advertising |= ADVERTISED_2500baseX_Full;
1130
27a005b8
MC		 1131 if (CHIP_NUM(bp) == CHIP_NUM_5709)
1132 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_OVER1G);
1133
605a9e20
MC		 1134 bnx2_read_phy(bp, bp->mii_up1, &up1);
1135 if (!(up1 & BCM5708S_UP1_2G5)) {
1136 up1 |= BCM5708S_UP1_2G5;
1137 bnx2_write_phy(bp, bp->mii_up1, up1);
1138 ret = 0;
1139 }
1140
27a005b8
MC		 1141 if (CHIP_NUM(bp) == CHIP_NUM_5709)
1142 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1143 MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1144
605a9e20
MC		 1145 return ret;
1146}
1147
1148static int
1149bnx2_test_and_disable_2g5(struct bnx2 *bp)
1150{
1151 u32 up1;
1152 int ret = 0;
1153
583c28e5 1154 if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))
605a9e20
MC		 1155 return 0;
1156
27a005b8
MC		 1157 if (CHIP_NUM(bp) == CHIP_NUM_5709)
1158 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_OVER1G);
1159
605a9e20
MC		 1160 bnx2_read_phy(bp, bp->mii_up1, &up1);
1161 if (up1 & BCM5708S_UP1_2G5) {
1162 up1 &= ~BCM5708S_UP1_2G5;
1163 bnx2_write_phy(bp, bp->mii_up1, up1);
1164 ret = 1;
1165 }
1166
27a005b8
MC		 1167 if (CHIP_NUM(bp) == CHIP_NUM_5709)
1168 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1169 MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1170
605a9e20
MC		 1171 return ret;
1172}
1173
1174static void
1175bnx2_enable_forced_2g5(struct bnx2 *bp)
1176{
1177 u32 bmcr;
1178
583c28e5 1179 if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))
605a9e20
MC		 1180 return;
1181
27a005b8
MC		 1182 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
1183 u32 val;
1184
1185 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1186 MII_BNX2_BLK_ADDR_SERDES_DIG);
1187 bnx2_read_phy(bp, MII_BNX2_SERDES_DIG_MISC1, &val);
1188 val &= ~MII_BNX2_SD_MISC1_FORCE_MSK;
1189 val |= MII_BNX2_SD_MISC1_FORCE | MII_BNX2_SD_MISC1_FORCE_2_5G;
1190 bnx2_write_phy(bp, MII_BNX2_SERDES_DIG_MISC1, val);
1191
1192 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1193 MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1194 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1195
1196 } else if (CHIP_NUM(bp) == CHIP_NUM_5708) {
605a9e20
MC		 1197 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1198 bmcr |= BCM5708S_BMCR_FORCE_2500;
1199 }
1200
1201 if (bp->autoneg & AUTONEG_SPEED) {
1202 bmcr &= ~BMCR_ANENABLE;
1203 if (bp->req_duplex == DUPLEX_FULL)
1204 bmcr |= BMCR_FULLDPLX;
1205 }
1206 bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
1207}
1208
1209static void
1210bnx2_disable_forced_2g5(struct bnx2 *bp)
1211{
1212 u32 bmcr;
1213
583c28e5 1214 if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))
605a9e20
MC		 1215 return;
1216
27a005b8
MC		 1217 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
1218 u32 val;
1219
1220 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1221 MII_BNX2_BLK_ADDR_SERDES_DIG);
1222 bnx2_read_phy(bp, MII_BNX2_SERDES_DIG_MISC1, &val);
1223 val &= ~MII_BNX2_SD_MISC1_FORCE;
1224 bnx2_write_phy(bp, MII_BNX2_SERDES_DIG_MISC1, val);
1225
1226 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1227 MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1228 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1229
1230 } else if (CHIP_NUM(bp) == CHIP_NUM_5708) {
605a9e20
MC		 1231 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1232 bmcr &= ~BCM5708S_BMCR_FORCE_2500;
1233 }
1234
1235 if (bp->autoneg & AUTONEG_SPEED)
1236 bmcr |= BMCR_SPEED1000 | BMCR_ANENABLE | BMCR_ANRESTART;
1237 bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
1238}
1239
b2fadeae
MC		 1240static void
1241bnx2_5706s_force_link_dn(struct bnx2 *bp, int start)
1242{
1243 u32 val;
1244
1245 bnx2_write_phy(bp, MII_BNX2_DSP_ADDRESS, MII_EXPAND_SERDES_CTL);
1246 bnx2_read_phy(bp, MII_BNX2_DSP_RW_PORT, &val);
1247 if (start)
1248 bnx2_write_phy(bp, MII_BNX2_DSP_RW_PORT, val & 0xff0f);
1249 else
1250 bnx2_write_phy(bp, MII_BNX2_DSP_RW_PORT, val | 0xc0);
1251}
1252
b6016b76
MC		 1253static int
1254bnx2_set_link(struct bnx2 *bp)
1255{
1256 u32 bmsr;
1257 u8 link_up;
1258
80be4434 1259 if (bp->loopback == MAC_LOOPBACK || bp->loopback == PHY_LOOPBACK) {
b6016b76
MC		 1260 bp->link_up = 1;
1261 return 0;
1262 }
1263
583c28e5 1264 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
0d8a6571
MC		 1265 return 0;
1266
b6016b76
MC		 1267 link_up = bp->link_up;
1268
27a005b8
MC		 1269 bnx2_enable_bmsr1(bp);
1270 bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr);
1271 bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr);
1272 bnx2_disable_bmsr1(bp);
b6016b76 1273
583c28e5 1274 if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
b6016b76 1275 (CHIP_NUM(bp) == CHIP_NUM_5706)) {
a2724e25 1276 u32 val, an_dbg;
b6016b76 1277
583c28e5 1278 if (bp->phy_flags & BNX2_PHY_FLAG_FORCED_DOWN) {
b2fadeae 1279 bnx2_5706s_force_link_dn(bp, 0);
583c28e5 1280 bp->phy_flags &= ~BNX2_PHY_FLAG_FORCED_DOWN;
b2fadeae 1281 }
b6016b76 1282 val = REG_RD(bp, BNX2_EMAC_STATUS);
a2724e25
MC		 1283
1284 bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_AN_DBG);
1285 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &an_dbg);
1286 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &an_dbg);
1287
1288 if ((val & BNX2_EMAC_STATUS_LINK) &&
1289 !(an_dbg & MISC_SHDW_AN_DBG_NOSYNC))
b6016b76
MC		 1290 bmsr |= BMSR_LSTATUS;
1291 else
1292 bmsr &= ~BMSR_LSTATUS;
1293 }
1294
1295 if (bmsr & BMSR_LSTATUS) {
1296 bp->link_up = 1;
1297
583c28e5 1298 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
5b0c76ad
MC		 1299 if (CHIP_NUM(bp) == CHIP_NUM_5706)
1300 bnx2_5706s_linkup(bp);
1301 else if (CHIP_NUM(bp) == CHIP_NUM_5708)
1302 bnx2_5708s_linkup(bp);
27a005b8
MC		 1303 else if (CHIP_NUM(bp) == CHIP_NUM_5709)
1304 bnx2_5709s_linkup(bp);
b6016b76
MC		 1305 }
1306 else {
1307 bnx2_copper_linkup(bp);
1308 }
1309 bnx2_resolve_flow_ctrl(bp);
1310 }
1311 else {
583c28e5 1312 if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
605a9e20
MC		 1313 (bp->autoneg & AUTONEG_SPEED))
1314 bnx2_disable_forced_2g5(bp);
b6016b76 1315
583c28e5 1316 if (bp->phy_flags & BNX2_PHY_FLAG_PARALLEL_DETECT) {
b2fadeae
MC		 1317 u32 bmcr;
1318
1319 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1320 bmcr |= BMCR_ANENABLE;
1321 bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
1322
583c28e5 1323 bp->phy_flags &= ~BNX2_PHY_FLAG_PARALLEL_DETECT;
b2fadeae 1324 }
b6016b76
MC		 1325 bp->link_up = 0;
1326 }
1327
1328 if (bp->link_up != link_up) {
1329 bnx2_report_link(bp);
1330 }
1331
1332 bnx2_set_mac_link(bp);
1333
1334 return 0;
1335}
1336
1337static int
1338bnx2_reset_phy(struct bnx2 *bp)
1339{
1340 int i;
1341 u32 reg;
1342
ca58c3af 1343 bnx2_write_phy(bp, bp->mii_bmcr, BMCR_RESET);
b6016b76
MC		 1344
1345#define PHY_RESET_MAX_WAIT 100
1346 for (i = 0; i < PHY_RESET_MAX_WAIT; i++) {
1347 udelay(10);
1348
ca58c3af 1349 bnx2_read_phy(bp, bp->mii_bmcr, &reg);
b6016b76
MC		 1350 if (!(reg & BMCR_RESET)) {
1351 udelay(20);
1352 break;
1353 }
1354 }
1355 if (i == PHY_RESET_MAX_WAIT) {
1356 return -EBUSY;
1357 }
1358 return 0;
1359}
1360
1361static u32
1362bnx2_phy_get_pause_adv(struct bnx2 *bp)
1363{
1364 u32 adv = 0;
1365
1366 if ((bp->req_flow_ctrl & (FLOW_CTRL_RX | FLOW_CTRL_TX)) ==
1367 (FLOW_CTRL_RX | FLOW_CTRL_TX)) {
1368
583c28e5 1369 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
b6016b76
MC		 1370 adv = ADVERTISE_1000XPAUSE;
1371 }
1372 else {
1373 adv = ADVERTISE_PAUSE_CAP;
1374 }
1375 }
1376 else if (bp->req_flow_ctrl & FLOW_CTRL_TX) {
583c28e5 1377 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
b6016b76
MC		 1378 adv = ADVERTISE_1000XPSE_ASYM;
1379 }
1380 else {
1381 adv = ADVERTISE_PAUSE_ASYM;
1382 }
1383 }
1384 else if (bp->req_flow_ctrl & FLOW_CTRL_RX) {
583c28e5 1385 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
b6016b76
MC		 1386 adv = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
1387 }
1388 else {
1389 adv = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1390 }
1391 }
1392 return adv;
1393}
1394
0d8a6571
MC		 1395static int bnx2_fw_sync(struct bnx2 *, u32, int);
1396
b6016b76 1397static int
0d8a6571
MC		 1398bnx2_setup_remote_phy(struct bnx2 *bp, u8 port)
1399{
1400 u32 speed_arg = 0, pause_adv;
1401
1402 pause_adv = bnx2_phy_get_pause_adv(bp);
1403
1404 if (bp->autoneg & AUTONEG_SPEED) {
1405 speed_arg |= BNX2_NETLINK_SET_LINK_ENABLE_AUTONEG;
1406 if (bp->advertising & ADVERTISED_10baseT_Half)
1407 speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_10HALF;
1408 if (bp->advertising & ADVERTISED_10baseT_Full)
1409 speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_10FULL;
1410 if (bp->advertising & ADVERTISED_100baseT_Half)
1411 speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_100HALF;
1412 if (bp->advertising & ADVERTISED_100baseT_Full)
1413 speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_100FULL;
1414 if (bp->advertising & ADVERTISED_1000baseT_Full)
1415 speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_1GFULL;
1416 if (bp->advertising & ADVERTISED_2500baseX_Full)
1417 speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_2G5FULL;
1418 } else {
1419 if (bp->req_line_speed == SPEED_2500)
1420 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_2G5FULL;
1421 else if (bp->req_line_speed == SPEED_1000)
1422 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_1GFULL;
1423 else if (bp->req_line_speed == SPEED_100) {
1424 if (bp->req_duplex == DUPLEX_FULL)
1425 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_100FULL;
1426 else
1427 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_100HALF;
1428 } else if (bp->req_line_speed == SPEED_10) {
1429 if (bp->req_duplex == DUPLEX_FULL)
1430 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_10FULL;
1431 else
1432 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_10HALF;
1433 }
1434 }
1435
1436 if (pause_adv & (ADVERTISE_1000XPAUSE | ADVERTISE_PAUSE_CAP))
1437 speed_arg |= BNX2_NETLINK_SET_LINK_FC_SYM_PAUSE;
c26736ec 1438 if (pause_adv & (ADVERTISE_1000XPSE_ASYM | ADVERTISE_PAUSE_ASYM))
0d8a6571
MC		 1439 speed_arg |= BNX2_NETLINK_SET_LINK_FC_ASYM_PAUSE;
1440
1441 if (port == PORT_TP)
1442 speed_arg |= BNX2_NETLINK_SET_LINK_PHY_APP_REMOTE |
1443 BNX2_NETLINK_SET_LINK_ETH_AT_WIRESPEED;
1444
2726d6e1 1445 bnx2_shmem_wr(bp, BNX2_DRV_MB_ARG0, speed_arg);
0d8a6571
MC		 1446
1447 spin_unlock_bh(&bp->phy_lock);
1448 bnx2_fw_sync(bp, BNX2_DRV_MSG_CODE_CMD_SET_LINK, 0);
1449 spin_lock_bh(&bp->phy_lock);
1450
1451 return 0;
1452}
1453
1454static int
1455bnx2_setup_serdes_phy(struct bnx2 *bp, u8 port)
b6016b76 1456{
605a9e20 1457 u32 adv, bmcr;
b6016b76
MC		 1458 u32 new_adv = 0;
1459
583c28e5 1460 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
0d8a6571
MC		 1461 return (bnx2_setup_remote_phy(bp, port));
1462
b6016b76
MC		 1463 if (!(bp->autoneg & AUTONEG_SPEED)) {
1464 u32 new_bmcr;
5b0c76ad
MC		 1465 int force_link_down = 0;
1466
605a9e20
MC		 1467 if (bp->req_line_speed == SPEED_2500) {
1468 if (!bnx2_test_and_enable_2g5(bp))
1469 force_link_down = 1;
1470 } else if (bp->req_line_speed == SPEED_1000) {
1471 if (bnx2_test_and_disable_2g5(bp))
1472 force_link_down = 1;
1473 }
ca58c3af 1474 bnx2_read_phy(bp, bp->mii_adv, &adv);
80be4434
MC		 1475 adv &= ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF);
1476
ca58c3af 1477 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
605a9e20 1478 new_bmcr = bmcr & ~BMCR_ANENABLE;
80be4434 1479 new_bmcr |= BMCR_SPEED1000;
605a9e20 1480
27a005b8
MC		 1481 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
1482 if (bp->req_line_speed == SPEED_2500)
1483 bnx2_enable_forced_2g5(bp);
1484 else if (bp->req_line_speed == SPEED_1000) {
1485 bnx2_disable_forced_2g5(bp);
1486 new_bmcr &= ~0x2000;
1487 }
1488
1489 } else if (CHIP_NUM(bp) == CHIP_NUM_5708) {
605a9e20
MC		 1490 if (bp->req_line_speed == SPEED_2500)
1491 new_bmcr |= BCM5708S_BMCR_FORCE_2500;
1492 else
1493 new_bmcr = bmcr & ~BCM5708S_BMCR_FORCE_2500;
5b0c76ad
MC		 1494 }
1495
b6016b76 1496 if (bp->req_duplex == DUPLEX_FULL) {
5b0c76ad 1497 adv |= ADVERTISE_1000XFULL;
b6016b76
MC		 1498 new_bmcr |= BMCR_FULLDPLX;
1499 }
1500 else {
5b0c76ad 1501 adv |= ADVERTISE_1000XHALF;
b6016b76
MC		 1502 new_bmcr &= ~BMCR_FULLDPLX;
1503 }
5b0c76ad 1504 if ((new_bmcr != bmcr) || (force_link_down)) {
b6016b76
MC		 1505 /* Force a link down visible on the other side */
1506 if (bp->link_up) {
ca58c3af 1507 bnx2_write_phy(bp, bp->mii_adv, adv &
5b0c76ad
MC		 1508 ~(ADVERTISE_1000XFULL |
1509 ADVERTISE_1000XHALF));
ca58c3af 1510 bnx2_write_phy(bp, bp->mii_bmcr, bmcr |
b6016b76
MC		 1511 BMCR_ANRESTART | BMCR_ANENABLE);
1512
1513 bp->link_up = 0;
1514 netif_carrier_off(bp->dev);
ca58c3af 1515 bnx2_write_phy(bp, bp->mii_bmcr, new_bmcr);
80be4434 1516 bnx2_report_link(bp);
b6016b76 1517 }
ca58c3af
MC		 1518 bnx2_write_phy(bp, bp->mii_adv, adv);
1519 bnx2_write_phy(bp, bp->mii_bmcr, new_bmcr);
605a9e20
MC		 1520 } else {
1521 bnx2_resolve_flow_ctrl(bp);
1522 bnx2_set_mac_link(bp);
b6016b76
MC		 1523 }
1524 return 0;
1525 }
1526
605a9e20 1527 bnx2_test_and_enable_2g5(bp);
5b0c76ad 1528
b6016b76
MC		 1529 if (bp->advertising & ADVERTISED_1000baseT_Full)
1530 new_adv |= ADVERTISE_1000XFULL;
1531
1532 new_adv |= bnx2_phy_get_pause_adv(bp);
1533
ca58c3af
MC		 1534 bnx2_read_phy(bp, bp->mii_adv, &adv);
1535 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
b6016b76
MC		 1536
1537 bp->serdes_an_pending = 0;
1538 if ((adv != new_adv) || ((bmcr & BMCR_ANENABLE) == 0)) {
1539 /* Force a link down visible on the other side */
1540 if (bp->link_up) {
ca58c3af 1541 bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK);
80be4434
MC		 1542 spin_unlock_bh(&bp->phy_lock);
1543 msleep(20);
1544 spin_lock_bh(&bp->phy_lock);
b6016b76
MC		 1545 }
1546
ca58c3af
MC		 1547 bnx2_write_phy(bp, bp->mii_adv, new_adv);
1548 bnx2_write_phy(bp, bp->mii_bmcr, bmcr | BMCR_ANRESTART |
b6016b76 1549 BMCR_ANENABLE);
f8dd064e
MC		 1550 /* Speed up link-up time when the link partner
1551 * does not autonegotiate which is very common
1552 * in blade servers. Some blade servers use
1553 * IPMI for kerboard input and it's important
1554 * to minimize link disruptions. Autoneg. involves
1555 * exchanging base pages plus 3 next pages and
1556 * normally completes in about 120 msec.
1557 */
1558 bp->current_interval = SERDES_AN_TIMEOUT;
1559 bp->serdes_an_pending = 1;
1560 mod_timer(&bp->timer, jiffies + bp->current_interval);
605a9e20
MC		 1561 } else {
1562 bnx2_resolve_flow_ctrl(bp);
1563 bnx2_set_mac_link(bp);
b6016b76
MC		 1564 }
1565
1566 return 0;
1567}
1568
1569#define ETHTOOL_ALL_FIBRE_SPEED \
583c28e5 1570 (bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE) ? \
deaf391b
MC		 1571 (ADVERTISED_2500baseX_Full | ADVERTISED_1000baseT_Full) :\
1572 (ADVERTISED_1000baseT_Full)
b6016b76
MC		 1573
1574#define ETHTOOL_ALL_COPPER_SPEED \
1575 (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full | \
1576 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full | \
1577 ADVERTISED_1000baseT_Full)
1578
1579#define PHY_ALL_10_100_SPEED (ADVERTISE_10HALF | ADVERTISE_10FULL | \
1580 ADVERTISE_100HALF | ADVERTISE_100FULL | ADVERTISE_CSMA)
6aa20a22 1581
b6016b76
MC		 1582#define PHY_ALL_1000_SPEED (ADVERTISE_1000HALF | ADVERTISE_1000FULL)
1583
0d8a6571
MC		 1584static void
1585bnx2_set_default_remote_link(struct bnx2 *bp)
1586{
1587 u32 link;
1588
1589 if (bp->phy_port == PORT_TP)
2726d6e1 1590 link = bnx2_shmem_rd(bp, BNX2_RPHY_COPPER_LINK);
0d8a6571 1591 else
2726d6e1 1592 link = bnx2_shmem_rd(bp, BNX2_RPHY_SERDES_LINK);
0d8a6571
MC		 1593
1594 if (link & BNX2_NETLINK_SET_LINK_ENABLE_AUTONEG) {
1595 bp->req_line_speed = 0;
1596 bp->autoneg |= AUTONEG_SPEED;
1597 bp->advertising = ADVERTISED_Autoneg;
1598 if (link & BNX2_NETLINK_SET_LINK_SPEED_10HALF)
1599 bp->advertising |= ADVERTISED_10baseT_Half;
1600 if (link & BNX2_NETLINK_SET_LINK_SPEED_10FULL)
1601 bp->advertising |= ADVERTISED_10baseT_Full;
1602 if (link & BNX2_NETLINK_SET_LINK_SPEED_100HALF)
1603 bp->advertising |= ADVERTISED_100baseT_Half;
1604 if (link & BNX2_NETLINK_SET_LINK_SPEED_100FULL)
1605 bp->advertising |= ADVERTISED_100baseT_Full;
1606 if (link & BNX2_NETLINK_SET_LINK_SPEED_1GFULL)
1607 bp->advertising |= ADVERTISED_1000baseT_Full;
1608 if (link & BNX2_NETLINK_SET_LINK_SPEED_2G5FULL)
1609 bp->advertising |= ADVERTISED_2500baseX_Full;
1610 } else {
1611 bp->autoneg = 0;
1612 bp->advertising = 0;
1613 bp->req_duplex = DUPLEX_FULL;
1614 if (link & BNX2_NETLINK_SET_LINK_SPEED_10) {
1615 bp->req_line_speed = SPEED_10;
1616 if (link & BNX2_NETLINK_SET_LINK_SPEED_10HALF)
1617 bp->req_duplex = DUPLEX_HALF;
1618 }
1619 if (link & BNX2_NETLINK_SET_LINK_SPEED_100) {
1620 bp->req_line_speed = SPEED_100;
1621 if (link & BNX2_NETLINK_SET_LINK_SPEED_100HALF)
1622 bp->req_duplex = DUPLEX_HALF;
1623 }
1624 if (link & BNX2_NETLINK_SET_LINK_SPEED_1GFULL)
1625 bp->req_line_speed = SPEED_1000;
1626 if (link & BNX2_NETLINK_SET_LINK_SPEED_2G5FULL)
1627 bp->req_line_speed = SPEED_2500;
1628 }
1629}
1630
deaf391b
MC		 1631static void
1632bnx2_set_default_link(struct bnx2 *bp)
1633{
ab59859d
HH		 1634 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) {
1635 bnx2_set_default_remote_link(bp);
1636 return;
1637 }
0d8a6571 1638
deaf391b
MC		 1639 bp->autoneg = AUTONEG_SPEED | AUTONEG_FLOW_CTRL;
1640 bp->req_line_speed = 0;
583c28e5 1641 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
deaf391b
MC		 1642 u32 reg;
1643
1644 bp->advertising = ETHTOOL_ALL_FIBRE_SPEED | ADVERTISED_Autoneg;
1645
2726d6e1 1646 reg = bnx2_shmem_rd(bp, BNX2_PORT_HW_CFG_CONFIG);
deaf391b
MC		 1647 reg &= BNX2_PORT_HW_CFG_CFG_DFLT_LINK_MASK;
1648 if (reg == BNX2_PORT_HW_CFG_CFG_DFLT_LINK_1G) {
1649 bp->autoneg = 0;
1650 bp->req_line_speed = bp->line_speed = SPEED_1000;
1651 bp->req_duplex = DUPLEX_FULL;
1652 }
1653 } else
1654 bp->advertising = ETHTOOL_ALL_COPPER_SPEED | ADVERTISED_Autoneg;
1655}
1656
df149d70
MC		 1657static void
1658bnx2_send_heart_beat(struct bnx2 *bp)
1659{
1660 u32 msg;
1661 u32 addr;
1662
1663 spin_lock(&bp->indirect_lock);
1664 msg = (u32) (++bp->fw_drv_pulse_wr_seq & BNX2_DRV_PULSE_SEQ_MASK);
1665 addr = bp->shmem_base + BNX2_DRV_PULSE_MB;
1666 REG_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, addr);
1667 REG_WR(bp, BNX2_PCICFG_REG_WINDOW, msg);
1668 spin_unlock(&bp->indirect_lock);
1669}
1670
0d8a6571
MC		 1671static void
1672bnx2_remote_phy_event(struct bnx2 *bp)
1673{
1674 u32 msg;
1675 u8 link_up = bp->link_up;
1676 u8 old_port;
1677
2726d6e1 1678 msg = bnx2_shmem_rd(bp, BNX2_LINK_STATUS);
0d8a6571 1679
df149d70
MC		 1680 if (msg & BNX2_LINK_STATUS_HEART_BEAT_EXPIRED)
1681 bnx2_send_heart_beat(bp);
1682
1683 msg &= ~BNX2_LINK_STATUS_HEART_BEAT_EXPIRED;
1684
0d8a6571
MC		 1685 if ((msg & BNX2_LINK_STATUS_LINK_UP) == BNX2_LINK_STATUS_LINK_DOWN)
1686 bp->link_up = 0;
1687 else {
1688 u32 speed;
1689
1690 bp->link_up = 1;
1691 speed = msg & BNX2_LINK_STATUS_SPEED_MASK;
1692 bp->duplex = DUPLEX_FULL;
1693 switch (speed) {
1694 case BNX2_LINK_STATUS_10HALF:
1695 bp->duplex = DUPLEX_HALF;
1696 case BNX2_LINK_STATUS_10FULL:
1697 bp->line_speed = SPEED_10;
1698 break;
1699 case BNX2_LINK_STATUS_100HALF:
1700 bp->duplex = DUPLEX_HALF;
1701 case BNX2_LINK_STATUS_100BASE_T4:
1702 case BNX2_LINK_STATUS_100FULL:
1703 bp->line_speed = SPEED_100;
1704 break;
1705 case BNX2_LINK_STATUS_1000HALF:
1706 bp->duplex = DUPLEX_HALF;
1707 case BNX2_LINK_STATUS_1000FULL:
1708 bp->line_speed = SPEED_1000;
1709 break;
1710 case BNX2_LINK_STATUS_2500HALF:
1711 bp->duplex = DUPLEX_HALF;
1712 case BNX2_LINK_STATUS_2500FULL:
1713 bp->line_speed = SPEED_2500;
1714 break;
1715 default:
1716 bp->line_speed = 0;
1717 break;
1718 }
1719
0d8a6571
MC		 1720 bp->flow_ctrl = 0;
1721 if ((bp->autoneg & (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) !=
1722 (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) {
1723 if (bp->duplex == DUPLEX_FULL)
1724 bp->flow_ctrl = bp->req_flow_ctrl;
1725 } else {
1726 if (msg & BNX2_LINK_STATUS_TX_FC_ENABLED)
1727 bp->flow_ctrl |= FLOW_CTRL_TX;
1728 if (msg & BNX2_LINK_STATUS_RX_FC_ENABLED)
1729 bp->flow_ctrl |= FLOW_CTRL_RX;
1730 }
1731
1732 old_port = bp->phy_port;
1733 if (msg & BNX2_LINK_STATUS_SERDES_LINK)
1734 bp->phy_port = PORT_FIBRE;
1735 else
1736 bp->phy_port = PORT_TP;
1737
1738 if (old_port != bp->phy_port)
1739 bnx2_set_default_link(bp);
1740
0d8a6571
MC		 1741 }
1742 if (bp->link_up != link_up)
1743 bnx2_report_link(bp);
1744
1745 bnx2_set_mac_link(bp);
1746}
1747
1748static int
1749bnx2_set_remote_link(struct bnx2 *bp)
1750{
1751 u32 evt_code;
1752
2726d6e1 1753 evt_code = bnx2_shmem_rd(bp, BNX2_FW_EVT_CODE_MB);
0d8a6571
MC		 1754 switch (evt_code) {
1755 case BNX2_FW_EVT_CODE_LINK_EVENT:
1756 bnx2_remote_phy_event(bp);
1757 break;
1758 case BNX2_FW_EVT_CODE_SW_TIMER_EXPIRATION_EVENT:
1759 default:
df149d70 1760 bnx2_send_heart_beat(bp);
0d8a6571
MC		 1761 break;
1762 }
1763 return 0;
1764}
1765
b6016b76
MC		 1766static int
1767bnx2_setup_copper_phy(struct bnx2 *bp)
1768{
1769 u32 bmcr;
1770 u32 new_bmcr;
1771
ca58c3af 1772 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
b6016b76
MC		 1773
1774 if (bp->autoneg & AUTONEG_SPEED) {
1775 u32 adv_reg, adv1000_reg;
1776 u32 new_adv_reg = 0;
1777 u32 new_adv1000_reg = 0;
1778
ca58c3af 1779 bnx2_read_phy(bp, bp->mii_adv, &adv_reg);
b6016b76
MC		 1780 adv_reg &= (PHY_ALL_10_100_SPEED | ADVERTISE_PAUSE_CAP |
1781 ADVERTISE_PAUSE_ASYM);
1782
1783 bnx2_read_phy(bp, MII_CTRL1000, &adv1000_reg);
1784 adv1000_reg &= PHY_ALL_1000_SPEED;
1785
1786 if (bp->advertising & ADVERTISED_10baseT_Half)
1787 new_adv_reg |= ADVERTISE_10HALF;
1788 if (bp->advertising & ADVERTISED_10baseT_Full)
1789 new_adv_reg |= ADVERTISE_10FULL;
1790 if (bp->advertising & ADVERTISED_100baseT_Half)
1791 new_adv_reg |= ADVERTISE_100HALF;
1792 if (bp->advertising & ADVERTISED_100baseT_Full)
1793 new_adv_reg |= ADVERTISE_100FULL;
1794 if (bp->advertising & ADVERTISED_1000baseT_Full)
1795 new_adv1000_reg |= ADVERTISE_1000FULL;
6aa20a22 1796
b6016b76
MC		 1797 new_adv_reg |= ADVERTISE_CSMA;
1798
1799 new_adv_reg |= bnx2_phy_get_pause_adv(bp);
1800
1801 if ((adv1000_reg != new_adv1000_reg) ||
1802 (adv_reg != new_adv_reg) ||
1803 ((bmcr & BMCR_ANENABLE) == 0)) {
1804
ca58c3af 1805 bnx2_write_phy(bp, bp->mii_adv, new_adv_reg);
b6016b76 1806 bnx2_write_phy(bp, MII_CTRL1000, new_adv1000_reg);
ca58c3af 1807 bnx2_write_phy(bp, bp->mii_bmcr, BMCR_ANRESTART |
b6016b76
MC		 1808 BMCR_ANENABLE);
1809 }
1810 else if (bp->link_up) {
1811 /* Flow ctrl may have changed from auto to forced */
1812 /* or vice-versa. */
1813
1814 bnx2_resolve_flow_ctrl(bp);
1815 bnx2_set_mac_link(bp);
1816 }
1817 return 0;
1818 }
1819
1820 new_bmcr = 0;
1821 if (bp->req_line_speed == SPEED_100) {
1822 new_bmcr |= BMCR_SPEED100;
1823 }
1824 if (bp->req_duplex == DUPLEX_FULL) {
1825 new_bmcr |= BMCR_FULLDPLX;
1826 }
1827 if (new_bmcr != bmcr) {
1828 u32 bmsr;
b6016b76 1829
ca58c3af
MC		 1830 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
1831 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
6aa20a22 1832
b6016b76
MC		 1833 if (bmsr & BMSR_LSTATUS) {
1834 /* Force link down */
ca58c3af 1835 bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK);
a16dda0e
MC		 1836 spin_unlock_bh(&bp->phy_lock);
1837 msleep(50);
1838 spin_lock_bh(&bp->phy_lock);
1839
ca58c3af
MC		 1840 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
1841 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
b6016b76
MC		 1842 }
1843
ca58c3af 1844 bnx2_write_phy(bp, bp->mii_bmcr, new_bmcr);
b6016b76
MC		 1845
1846 /* Normally, the new speed is setup after the link has
1847 * gone down and up again. In some cases, link will not go
1848 * down so we need to set up the new speed here.
1849 */
1850 if (bmsr & BMSR_LSTATUS) {
1851 bp->line_speed = bp->req_line_speed;
1852 bp->duplex = bp->req_duplex;
1853 bnx2_resolve_flow_ctrl(bp);
1854 bnx2_set_mac_link(bp);
1855 }
27a005b8
MC		 1856 } else {
1857 bnx2_resolve_flow_ctrl(bp);
1858 bnx2_set_mac_link(bp);
b6016b76
MC		 1859 }
1860 return 0;
1861}
1862
1863static int
0d8a6571 1864bnx2_setup_phy(struct bnx2 *bp, u8 port)
b6016b76
MC		 1865{
1866 if (bp->loopback == MAC_LOOPBACK)
1867 return 0;
1868
583c28e5 1869 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
0d8a6571 1870 return (bnx2_setup_serdes_phy(bp, port));
b6016b76
MC		 1871 }
1872 else {
1873 return (bnx2_setup_copper_phy(bp));
1874 }
1875}
1876
27a005b8 1877static int
9a120bc5 1878bnx2_init_5709s_phy(struct bnx2 *bp, int reset_phy)
27a005b8
MC		 1879{
1880 u32 val;
1881
1882 bp->mii_bmcr = MII_BMCR + 0x10;
1883 bp->mii_bmsr = MII_BMSR + 0x10;
1884 bp->mii_bmsr1 = MII_BNX2_GP_TOP_AN_STATUS1;
1885 bp->mii_adv = MII_ADVERTISE + 0x10;
1886 bp->mii_lpa = MII_LPA + 0x10;
1887 bp->mii_up1 = MII_BNX2_OVER1G_UP1;
1888
1889 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_AER);
1890 bnx2_write_phy(bp, MII_BNX2_AER_AER, MII_BNX2_AER_AER_AN_MMD);
1891
1892 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
9a120bc5
MC		 1893 if (reset_phy)
1894 bnx2_reset_phy(bp);
27a005b8
MC		 1895
1896 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_SERDES_DIG);
1897
1898 bnx2_read_phy(bp, MII_BNX2_SERDES_DIG_1000XCTL1, &val);
1899 val &= ~MII_BNX2_SD_1000XCTL1_AUTODET;
1900 val |= MII_BNX2_SD_1000XCTL1_FIBER;
1901 bnx2_write_phy(bp, MII_BNX2_SERDES_DIG_1000XCTL1, val);
1902
1903 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_OVER1G);
1904 bnx2_read_phy(bp, MII_BNX2_OVER1G_UP1, &val);
583c28e5 1905 if (bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE)
27a005b8
MC		 1906 val |= BCM5708S_UP1_2G5;
1907 else
1908 val &= ~BCM5708S_UP1_2G5;
1909 bnx2_write_phy(bp, MII_BNX2_OVER1G_UP1, val);
1910
1911 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_BAM_NXTPG);
1912 bnx2_read_phy(bp, MII_BNX2_BAM_NXTPG_CTL, &val);
1913 val |= MII_BNX2_NXTPG_CTL_T2 | MII_BNX2_NXTPG_CTL_BAM;
1914 bnx2_write_phy(bp, MII_BNX2_BAM_NXTPG_CTL, val);
1915
1916 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_CL73_USERB0);
1917
1918 val = MII_BNX2_CL73_BAM_EN | MII_BNX2_CL73_BAM_STA_MGR_EN |
1919 MII_BNX2_CL73_BAM_NP_AFT_BP_EN;
1920 bnx2_write_phy(bp, MII_BNX2_CL73_BAM_CTL1, val);
1921
1922 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1923
1924 return 0;
1925}
1926
b6016b76 1927static int
9a120bc5 1928bnx2_init_5708s_phy(struct bnx2 *bp, int reset_phy)
5b0c76ad
MC		 1929{
1930 u32 val;
1931
9a120bc5
MC		 1932 if (reset_phy)
1933 bnx2_reset_phy(bp);
27a005b8
MC		 1934
1935 bp->mii_up1 = BCM5708S_UP1;
1936
5b0c76ad
MC		 1937 bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG3);
1938 bnx2_write_phy(bp, BCM5708S_DIG_3_0, BCM5708S_DIG_3_0_USE_IEEE);
1939 bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG);
1940
1941 bnx2_read_phy(bp, BCM5708S_1000X_CTL1, &val);
1942 val |= BCM5708S_1000X_CTL1_FIBER_MODE | BCM5708S_1000X_CTL1_AUTODET_EN;
1943 bnx2_write_phy(bp, BCM5708S_1000X_CTL1, val);
1944
1945 bnx2_read_phy(bp, BCM5708S_1000X_CTL2, &val);
1946 val |= BCM5708S_1000X_CTL2_PLLEL_DET_EN;
1947 bnx2_write_phy(bp, BCM5708S_1000X_CTL2, val);
1948
583c28e5 1949 if (bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE) {
5b0c76ad
MC		 1950 bnx2_read_phy(bp, BCM5708S_UP1, &val);
1951 val |= BCM5708S_UP1_2G5;
1952 bnx2_write_phy(bp, BCM5708S_UP1, val);
1953 }
1954
1955 if ((CHIP_ID(bp) == CHIP_ID_5708_A0) ||
dda1e390
MC		 1956 (CHIP_ID(bp) == CHIP_ID_5708_B0) ||
1957 (CHIP_ID(bp) == CHIP_ID_5708_B1)) {
5b0c76ad
MC		 1958 /* increase tx signal amplitude */
1959 bnx2_write_phy(bp, BCM5708S_BLK_ADDR,
1960 BCM5708S_BLK_ADDR_TX_MISC);
1961 bnx2_read_phy(bp, BCM5708S_TX_ACTL1, &val);
1962 val &= ~BCM5708S_TX_ACTL1_DRIVER_VCM;
1963 bnx2_write_phy(bp, BCM5708S_TX_ACTL1, val);
1964 bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG);
1965 }
1966
2726d6e1 1967 val = bnx2_shmem_rd(bp, BNX2_PORT_HW_CFG_CONFIG) &
5b0c76ad
MC		 1968 BNX2_PORT_HW_CFG_CFG_TXCTL3_MASK;
1969
1970 if (val) {
1971 u32 is_backplane;
1972
2726d6e1 1973 is_backplane = bnx2_shmem_rd(bp, BNX2_SHARED_HW_CFG_CONFIG);
5b0c76ad
MC		 1974 if (is_backplane & BNX2_SHARED_HW_CFG_PHY_BACKPLANE) {
1975 bnx2_write_phy(bp, BCM5708S_BLK_ADDR,
1976 BCM5708S_BLK_ADDR_TX_MISC);
1977 bnx2_write_phy(bp, BCM5708S_TX_ACTL3, val);
1978 bnx2_write_phy(bp, BCM5708S_BLK_ADDR,
1979 BCM5708S_BLK_ADDR_DIG);
1980 }
1981 }
1982 return 0;
1983}
1984
1985static int
9a120bc5 1986bnx2_init_5706s_phy(struct bnx2 *bp, int reset_phy)
b6016b76 1987{
9a120bc5
MC		 1988 if (reset_phy)
1989 bnx2_reset_phy(bp);
27a005b8 1990
583c28e5 1991 bp->phy_flags &= ~BNX2_PHY_FLAG_PARALLEL_DETECT;
b6016b76 1992
59b47d8a
MC		 1993 if (CHIP_NUM(bp) == CHIP_NUM_5706)
1994 REG_WR(bp, BNX2_MISC_GP_HW_CTL0, 0x300);
b6016b76
MC		 1995
1996 if (bp->dev->mtu > 1500) {
1997 u32 val;
1998
1999 /* Set extended packet length bit */
2000 bnx2_write_phy(bp, 0x18, 0x7);
2001 bnx2_read_phy(bp, 0x18, &val);
2002 bnx2_write_phy(bp, 0x18, (val & 0xfff8) | 0x4000);
2003
2004 bnx2_write_phy(bp, 0x1c, 0x6c00);
2005 bnx2_read_phy(bp, 0x1c, &val);
2006 bnx2_write_phy(bp, 0x1c, (val & 0x3ff) | 0xec02);
2007 }
2008 else {
2009 u32 val;
2010
2011 bnx2_write_phy(bp, 0x18, 0x7);
2012 bnx2_read_phy(bp, 0x18, &val);
2013 bnx2_write_phy(bp, 0x18, val & ~0x4007);
2014
2015 bnx2_write_phy(bp, 0x1c, 0x6c00);
2016 bnx2_read_phy(bp, 0x1c, &val);
2017 bnx2_write_phy(bp, 0x1c, (val & 0x3fd) | 0xec00);
2018 }
2019
2020 return 0;
2021}
2022
2023static int
9a120bc5 2024bnx2_init_copper_phy(struct bnx2 *bp, int reset_phy)
b6016b76 2025{
5b0c76ad
MC		 2026 u32 val;
2027
9a120bc5
MC		 2028 if (reset_phy)
2029 bnx2_reset_phy(bp);
27a005b8 2030
583c28e5 2031 if (bp->phy_flags & BNX2_PHY_FLAG_CRC_FIX) {
b6016b76
MC		 2032 bnx2_write_phy(bp, 0x18, 0x0c00);
2033 bnx2_write_phy(bp, 0x17, 0x000a);
2034 bnx2_write_phy(bp, 0x15, 0x310b);
2035 bnx2_write_phy(bp, 0x17, 0x201f);
2036 bnx2_write_phy(bp, 0x15, 0x9506);
2037 bnx2_write_phy(bp, 0x17, 0x401f);
2038 bnx2_write_phy(bp, 0x15, 0x14e2);
2039 bnx2_write_phy(bp, 0x18, 0x0400);
2040 }
2041
583c28e5 2042 if (bp->phy_flags & BNX2_PHY_FLAG_DIS_EARLY_DAC) {
b659f44e
MC		 2043 bnx2_write_phy(bp, MII_BNX2_DSP_ADDRESS,
2044 MII_BNX2_DSP_EXPAND_REG | 0x8);
2045 bnx2_read_phy(bp, MII_BNX2_DSP_RW_PORT, &val);
2046 val &= ~(1 << 8);
2047 bnx2_write_phy(bp, MII_BNX2_DSP_RW_PORT, val);
2048 }
2049
b6016b76 2050 if (bp->dev->mtu > 1500) {
b6016b76
MC		 2051 /* Set extended packet length bit */
2052 bnx2_write_phy(bp, 0x18, 0x7);
2053 bnx2_read_phy(bp, 0x18, &val);
2054 bnx2_write_phy(bp, 0x18, val | 0x4000);
2055
2056 bnx2_read_phy(bp, 0x10, &val);
2057 bnx2_write_phy(bp, 0x10, val | 0x1);
2058 }
2059 else {
b6016b76
MC		 2060 bnx2_write_phy(bp, 0x18, 0x7);
2061 bnx2_read_phy(bp, 0x18, &val);
2062 bnx2_write_phy(bp, 0x18, val & ~0x4007);
2063
2064 bnx2_read_phy(bp, 0x10, &val);
2065 bnx2_write_phy(bp, 0x10, val & ~0x1);
2066 }
2067
5b0c76ad
MC		 2068 /* ethernet@wirespeed */
2069 bnx2_write_phy(bp, 0x18, 0x7007);
2070 bnx2_read_phy(bp, 0x18, &val);
2071 bnx2_write_phy(bp, 0x18, val | (1 << 15) | (1 << 4));
b6016b76
MC		 2072 return 0;
2073}
2074
2075
2076static int
9a120bc5 2077bnx2_init_phy(struct bnx2 *bp, int reset_phy)
b6016b76
MC		 2078{
2079 u32 val;
2080 int rc = 0;
2081
583c28e5
MC		 2082 bp->phy_flags &= ~BNX2_PHY_FLAG_INT_MODE_MASK;
2083 bp->phy_flags |= BNX2_PHY_FLAG_INT_MODE_LINK_READY;
b6016b76 2084
ca58c3af
MC		 2085 bp->mii_bmcr = MII_BMCR;
2086 bp->mii_bmsr = MII_BMSR;
27a005b8 2087 bp->mii_bmsr1 = MII_BMSR;
ca58c3af
MC		 2088 bp->mii_adv = MII_ADVERTISE;
2089 bp->mii_lpa = MII_LPA;
2090
b6016b76
MC		 2091 REG_WR(bp, BNX2_EMAC_ATTENTION_ENA, BNX2_EMAC_ATTENTION_ENA_LINK);
2092
583c28e5 2093 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
0d8a6571
MC		 2094 goto setup_phy;
2095
b6016b76
MC		 2096 bnx2_read_phy(bp, MII_PHYSID1, &val);
2097 bp->phy_id = val << 16;
2098 bnx2_read_phy(bp, MII_PHYSID2, &val);
2099 bp->phy_id |= val & 0xffff;
2100
583c28e5 2101 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
5b0c76ad 2102 if (CHIP_NUM(bp) == CHIP_NUM_5706)
9a120bc5 2103 rc = bnx2_init_5706s_phy(bp, reset_phy);
5b0c76ad 2104 else if (CHIP_NUM(bp) == CHIP_NUM_5708)
9a120bc5 2105 rc = bnx2_init_5708s_phy(bp, reset_phy);
27a005b8 2106 else if (CHIP_NUM(bp) == CHIP_NUM_5709)
9a120bc5 2107 rc = bnx2_init_5709s_phy(bp, reset_phy);
b6016b76
MC		 2108 }
2109 else {
9a120bc5 2110 rc = bnx2_init_copper_phy(bp, reset_phy);
b6016b76
MC		 2111 }
2112
0d8a6571
MC		 2113setup_phy:
2114 if (!rc)
2115 rc = bnx2_setup_phy(bp, bp->phy_port);
b6016b76
MC		 2116
2117 return rc;
2118}
2119
2120static int
2121bnx2_set_mac_loopback(struct bnx2 *bp)
2122{
2123 u32 mac_mode;
2124
2125 mac_mode = REG_RD(bp, BNX2_EMAC_MODE);
2126 mac_mode &= ~BNX2_EMAC_MODE_PORT;
2127 mac_mode |= BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK;
2128 REG_WR(bp, BNX2_EMAC_MODE, mac_mode);
2129 bp->link_up = 1;
2130 return 0;
2131}
2132
bc5a0690
MC		 2133static int bnx2_test_link(struct bnx2 *);
2134
2135static int
2136bnx2_set_phy_loopback(struct bnx2 *bp)
2137{
2138 u32 mac_mode;
2139 int rc, i;
2140
2141 spin_lock_bh(&bp->phy_lock);
ca58c3af 2142 rc = bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK | BMCR_FULLDPLX |
bc5a0690
MC		 2143 BMCR_SPEED1000);
2144 spin_unlock_bh(&bp->phy_lock);
2145 if (rc)
2146 return rc;
2147
2148 for (i = 0; i < 10; i++) {
2149 if (bnx2_test_link(bp) == 0)
2150 break;
80be4434 2151 msleep(100);
bc5a0690
MC		 2152 }
2153
2154 mac_mode = REG_RD(bp, BNX2_EMAC_MODE);
2155 mac_mode &= ~(BNX2_EMAC_MODE_PORT | BNX2_EMAC_MODE_HALF_DUPLEX |
2156 BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK |
59b47d8a 2157 BNX2_EMAC_MODE_25G_MODE);
bc5a0690
MC		 2158
2159 mac_mode |= BNX2_EMAC_MODE_PORT_GMII;
2160 REG_WR(bp, BNX2_EMAC_MODE, mac_mode);
2161 bp->link_up = 1;
2162 return 0;
2163}
2164
b6016b76 2165static int
b090ae2b 2166bnx2_fw_sync(struct bnx2 *bp, u32 msg_data, int silent)
b6016b76
MC		 2167{
2168 int i;
2169 u32 val;
2170
b6016b76
MC		 2171 bp->fw_wr_seq++;
2172 msg_data |= bp->fw_wr_seq;
2173
2726d6e1 2174 bnx2_shmem_wr(bp, BNX2_DRV_MB, msg_data);
b6016b76
MC		 2175
2176 /* wait for an acknowledgement. */
b090ae2b
MC		 2177 for (i = 0; i < (FW_ACK_TIME_OUT_MS / 10); i++) {
2178 msleep(10);
b6016b76 2179
2726d6e1 2180 val = bnx2_shmem_rd(bp, BNX2_FW_MB);
b6016b76
MC		 2181
2182 if ((val & BNX2_FW_MSG_ACK) == (msg_data & BNX2_DRV_MSG_SEQ))
2183 break;
2184 }
b090ae2b
MC		 2185 if ((msg_data & BNX2_DRV_MSG_DATA) == BNX2_DRV_MSG_DATA_WAIT0)
2186 return 0;
b6016b76
MC		 2187
2188 /* If we timed out, inform the firmware that this is the case. */
b090ae2b
MC		 2189 if ((val & BNX2_FW_MSG_ACK) != (msg_data & BNX2_DRV_MSG_SEQ)) {
2190 if (!silent)
2191 printk(KERN_ERR PFX "fw sync timeout, reset code = "
2192 "%x\n", msg_data);
b6016b76
MC		 2193
2194 msg_data &= ~BNX2_DRV_MSG_CODE;
2195 msg_data |= BNX2_DRV_MSG_CODE_FW_TIMEOUT;
2196
2726d6e1 2197 bnx2_shmem_wr(bp, BNX2_DRV_MB, msg_data);
b6016b76 2198
b6016b76
MC		 2199 return -EBUSY;
2200 }
2201
b090ae2b
MC		 2202 if ((val & BNX2_FW_MSG_STATUS_MASK) != BNX2_FW_MSG_STATUS_OK)
2203 return -EIO;
2204
b6016b76
MC		 2205 return 0;
2206}
2207
59b47d8a
MC		 2208static int
2209bnx2_init_5709_context(struct bnx2 *bp)
2210{
2211 int i, ret = 0;
2212 u32 val;
2213
2214 val = BNX2_CTX_COMMAND_ENABLED | BNX2_CTX_COMMAND_MEM_INIT | (1 << 12);
2215 val |= (BCM_PAGE_BITS - 8) << 16;
2216 REG_WR(bp, BNX2_CTX_COMMAND, val);
641bdcd5
MC		 2217 for (i = 0; i < 10; i++) {
2218 val = REG_RD(bp, BNX2_CTX_COMMAND);
2219 if (!(val & BNX2_CTX_COMMAND_MEM_INIT))
2220 break;
2221 udelay(2);
2222 }
2223 if (val & BNX2_CTX_COMMAND_MEM_INIT)
2224 return -EBUSY;
2225
59b47d8a
MC		 2226 for (i = 0; i < bp->ctx_pages; i++) {
2227 int j;
2228
352f7687
MC		 2229 if (bp->ctx_blk[i])
2230 memset(bp->ctx_blk[i], 0, BCM_PAGE_SIZE);
2231 else
2232 return -ENOMEM;
2233
59b47d8a
MC		 2234 REG_WR(bp, BNX2_CTX_HOST_PAGE_TBL_DATA0,
2235 (bp->ctx_blk_mapping[i] & 0xffffffff) |
2236 BNX2_CTX_HOST_PAGE_TBL_DATA0_VALID);
2237 REG_WR(bp, BNX2_CTX_HOST_PAGE_TBL_DATA1,
2238 (u64) bp->ctx_blk_mapping[i] >> 32);
2239 REG_WR(bp, BNX2_CTX_HOST_PAGE_TBL_CTRL, i |
2240 BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ);
2241 for (j = 0; j < 10; j++) {
2242
2243 val = REG_RD(bp, BNX2_CTX_HOST_PAGE_TBL_CTRL);
2244 if (!(val & BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ))
2245 break;
2246 udelay(5);
2247 }
2248 if (val & BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ) {
2249 ret = -EBUSY;
2250 break;
2251 }
2252 }
2253 return ret;
2254}
2255
b6016b76
MC		 2256static void
2257bnx2_init_context(struct bnx2 *bp)
2258{
2259 u32 vcid;
2260
2261 vcid = 96;
2262 while (vcid) {
2263 u32 vcid_addr, pcid_addr, offset;
7947b20e 2264 int i;
b6016b76
MC		 2265
2266 vcid--;
2267
2268 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
2269 u32 new_vcid;
2270
2271 vcid_addr = GET_PCID_ADDR(vcid);
2272 if (vcid & 0x8) {
2273 new_vcid = 0x60 + (vcid & 0xf0) + (vcid & 0x7);
2274 }
2275 else {
2276 new_vcid = vcid;
2277 }
2278 pcid_addr = GET_PCID_ADDR(new_vcid);
2279 }
2280 else {
2281 vcid_addr = GET_CID_ADDR(vcid);
2282 pcid_addr = vcid_addr;
2283 }
2284
7947b20e
MC		 2285 for (i = 0; i < (CTX_SIZE / PHY_CTX_SIZE); i++) {
2286 vcid_addr += (i << PHY_CTX_SHIFT);
2287 pcid_addr += (i << PHY_CTX_SHIFT);
b6016b76 2288
5d5d0015 2289 REG_WR(bp, BNX2_CTX_VIRT_ADDR, vcid_addr);
7947b20e 2290 REG_WR(bp, BNX2_CTX_PAGE_TBL, pcid_addr);
b6016b76 2291
7947b20e
MC		 2292 /* Zero out the context. */
2293 for (offset = 0; offset < PHY_CTX_SIZE; offset += 4)
62a8313c 2294 bnx2_ctx_wr(bp, vcid_addr, offset, 0);
7947b20e 2295 }
b6016b76
MC		 2296 }
2297}
2298
2299static int
2300bnx2_alloc_bad_rbuf(struct bnx2 *bp)
2301{
2302 u16 *good_mbuf;
2303 u32 good_mbuf_cnt;
2304 u32 val;
2305
2306 good_mbuf = kmalloc(512 * sizeof(u16), GFP_KERNEL);
2307 if (good_mbuf == NULL) {
2308 printk(KERN_ERR PFX "Failed to allocate memory in "
2309 "bnx2_alloc_bad_rbuf\n");
2310 return -ENOMEM;
2311 }
2312
2313 REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS,
2314 BNX2_MISC_ENABLE_SET_BITS_RX_MBUF_ENABLE);
2315
2316 good_mbuf_cnt = 0;
2317
2318 /* Allocate a bunch of mbufs and save the good ones in an array. */
2726d6e1 2319 val = bnx2_reg_rd_ind(bp, BNX2_RBUF_STATUS1);
b6016b76 2320 while (val & BNX2_RBUF_STATUS1_FREE_COUNT) {
2726d6e1
MC		 2321 bnx2_reg_wr_ind(bp, BNX2_RBUF_COMMAND,
2322 BNX2_RBUF_COMMAND_ALLOC_REQ);
b6016b76 2323
2726d6e1 2324 val = bnx2_reg_rd_ind(bp, BNX2_RBUF_FW_BUF_ALLOC);
b6016b76
MC		 2325
2326 val &= BNX2_RBUF_FW_BUF_ALLOC_VALUE;
2327
2328 /* The addresses with Bit 9 set are bad memory blocks. */
2329 if (!(val & (1 << 9))) {
2330 good_mbuf[good_mbuf_cnt] = (u16) val;
2331 good_mbuf_cnt++;
2332 }
2333
2726d6e1 2334 val = bnx2_reg_rd_ind(bp, BNX2_RBUF_STATUS1);
b6016b76
MC		 2335 }
2336
2337 /* Free the good ones back to the mbuf pool thus discarding
2338 * all the bad ones. */
2339 while (good_mbuf_cnt) {
2340 good_mbuf_cnt--;
2341
2342 val = good_mbuf[good_mbuf_cnt];
2343 val = (val << 9) | val | 1;
2344
2726d6e1 2345 bnx2_reg_wr_ind(bp, BNX2_RBUF_FW_BUF_FREE, val);
b6016b76
MC		 2346 }
2347 kfree(good_mbuf);
2348 return 0;
2349}
2350
2351static void
6aa20a22 2352bnx2_set_mac_addr(struct bnx2 *bp)
b6016b76
MC		 2353{
2354 u32 val;
2355 u8 *mac_addr = bp->dev->dev_addr;
2356
2357 val = (mac_addr[0] << 8) | mac_addr[1];
2358
2359 REG_WR(bp, BNX2_EMAC_MAC_MATCH0, val);
2360
6aa20a22 2361 val = (mac_addr[2] << 24) | (mac_addr[3] << 16) |
b6016b76
MC		 2362 (mac_addr[4] << 8) | mac_addr[5];
2363
2364 REG_WR(bp, BNX2_EMAC_MAC_MATCH1, val);
2365}
2366
47bf4246
MC		 2367static inline int
2368bnx2_alloc_rx_page(struct bnx2 *bp, u16 index)
2369{
2370 dma_addr_t mapping;
2371 struct sw_pg *rx_pg = &bp->rx_pg_ring[index];
2372 struct rx_bd *rxbd =
2373 &bp->rx_pg_desc_ring[RX_RING(index)][RX_IDX(index)];
2374 struct page *page = alloc_page(GFP_ATOMIC);
2375
2376 if (!page)
2377 return -ENOMEM;
2378 mapping = pci_map_page(bp->pdev, page, 0, PAGE_SIZE,
2379 PCI_DMA_FROMDEVICE);
2380 rx_pg->page = page;
2381 pci_unmap_addr_set(rx_pg, mapping, mapping);
2382 rxbd->rx_bd_haddr_hi = (u64) mapping >> 32;
2383 rxbd->rx_bd_haddr_lo = (u64) mapping & 0xffffffff;
2384 return 0;
2385}
2386
2387static void
2388bnx2_free_rx_page(struct bnx2 *bp, u16 index)
2389{
2390 struct sw_pg *rx_pg = &bp->rx_pg_ring[index];
2391 struct page *page = rx_pg->page;
2392
2393 if (!page)
2394 return;
2395
2396 pci_unmap_page(bp->pdev, pci_unmap_addr(rx_pg, mapping), PAGE_SIZE,
2397 PCI_DMA_FROMDEVICE);
2398
2399 __free_page(page);
2400 rx_pg->page = NULL;
2401}
2402
b6016b76 2403static inline int
a1f60190 2404bnx2_alloc_rx_skb(struct bnx2 *bp, struct bnx2_napi *bnapi, u16 index)
b6016b76
MC		 2405{
2406 struct sk_buff *skb;
2407 struct sw_bd *rx_buf = &bp->rx_buf_ring[index];
2408 dma_addr_t mapping;
13daffa2 2409 struct rx_bd *rxbd = &bp->rx_desc_ring[RX_RING(index)][RX_IDX(index)];
b6016b76
MC		 2410 unsigned long align;
2411
932f3772 2412 skb = netdev_alloc_skb(bp->dev, bp->rx_buf_size);
b6016b76
MC		 2413 if (skb == NULL) {
2414 return -ENOMEM;
2415 }
2416
59b47d8a
MC		 2417 if (unlikely((align = (unsigned long) skb->data & (BNX2_RX_ALIGN - 1))))
2418 skb_reserve(skb, BNX2_RX_ALIGN - align);
b6016b76 2419
b6016b76
MC		 2420 mapping = pci_map_single(bp->pdev, skb->data, bp->rx_buf_use_size,
2421 PCI_DMA_FROMDEVICE);
2422
2423 rx_buf->skb = skb;
2424 pci_unmap_addr_set(rx_buf, mapping, mapping);
2425
2426 rxbd->rx_bd_haddr_hi = (u64) mapping >> 32;
2427 rxbd->rx_bd_haddr_lo = (u64) mapping & 0xffffffff;
2428
a1f60190 2429 bnapi->rx_prod_bseq += bp->rx_buf_use_size;
b6016b76
MC		 2430
2431 return 0;
2432}
2433
da3e4fbe 2434static int
35efa7c1 2435bnx2_phy_event_is_set(struct bnx2 *bp, struct bnx2_napi *bnapi, u32 event)
b6016b76 2436{
35efa7c1 2437 struct status_block *sblk = bnapi->status_blk;
b6016b76 2438 u32 new_link_state, old_link_state;
da3e4fbe 2439 int is_set = 1;
b6016b76 2440
da3e4fbe
MC		 2441 new_link_state = sblk->status_attn_bits & event;
2442 old_link_state = sblk->status_attn_bits_ack & event;
b6016b76 2443 if (new_link_state != old_link_state) {
da3e4fbe
MC		 2444 if (new_link_state)
2445 REG_WR(bp, BNX2_PCICFG_STATUS_BIT_SET_CMD, event);
2446 else
2447 REG_WR(bp, BNX2_PCICFG_STATUS_BIT_CLEAR_CMD, event);
2448 } else
2449 is_set = 0;
2450
2451 return is_set;
2452}
2453
2454static void
35efa7c1 2455bnx2_phy_int(struct bnx2 *bp, struct bnx2_napi *bnapi)
da3e4fbe 2456{
74ecc62d
MC		 2457 spin_lock(&bp->phy_lock);
2458
2459 if (bnx2_phy_event_is_set(bp, bnapi, STATUS_ATTN_BITS_LINK_STATE))
b6016b76 2460 bnx2_set_link(bp);
35efa7c1 2461 if (bnx2_phy_event_is_set(bp, bnapi, STATUS_ATTN_BITS_TIMER_ABORT))
0d8a6571
MC		 2462 bnx2_set_remote_link(bp);
2463
74ecc62d
MC		 2464 spin_unlock(&bp->phy_lock);
2465
b6016b76
MC		 2466}
2467
ead7270b 2468static inline u16
35efa7c1 2469bnx2_get_hw_tx_cons(struct bnx2_napi *bnapi)
ead7270b
MC		 2470{
2471 u16 cons;
2472
c76c0475
MC		 2473 if (bnapi->int_num == 0)
2474 cons = bnapi->status_blk->status_tx_quick_consumer_index0;
2475 else
2476 cons = bnapi->status_blk_msix->status_tx_quick_consumer_index;
ead7270b
MC		 2477
2478 if (unlikely((cons & MAX_TX_DESC_CNT) == MAX_TX_DESC_CNT))
2479 cons++;
2480 return cons;
2481}
2482
57851d84
MC		 2483static int
2484bnx2_tx_int(struct bnx2 *bp, struct bnx2_napi *bnapi, int budget)
b6016b76
MC		 2485{
2486 u16 hw_cons, sw_cons, sw_ring_cons;
57851d84 2487 int tx_pkt = 0;
b6016b76 2488
35efa7c1 2489 hw_cons = bnx2_get_hw_tx_cons(bnapi);
a550c99b 2490 sw_cons = bnapi->tx_cons;
b6016b76
MC		 2491
2492 while (sw_cons != hw_cons) {
2493 struct sw_bd *tx_buf;
2494 struct sk_buff *skb;
2495 int i, last;
2496
2497 sw_ring_cons = TX_RING_IDX(sw_cons);
2498
2499 tx_buf = &bp->tx_buf_ring[sw_ring_cons];
2500 skb = tx_buf->skb;
1d39ed56 2501
b6016b76 2502 /* partial BD completions possible with TSO packets */
89114afd 2503 if (skb_is_gso(skb)) {
b6016b76
MC		 2504 u16 last_idx, last_ring_idx;
2505
2506 last_idx = sw_cons +
2507 skb_shinfo(skb)->nr_frags + 1;
2508 last_ring_idx = sw_ring_cons +
2509 skb_shinfo(skb)->nr_frags + 1;
2510 if (unlikely(last_ring_idx >= MAX_TX_DESC_CNT)) {
2511 last_idx++;
2512 }
2513 if (((s16) ((s16) last_idx - (s16) hw_cons)) > 0) {
2514 break;
2515 }
2516 }
1d39ed56 2517
b6016b76
MC		 2518 pci_unmap_single(bp->pdev, pci_unmap_addr(tx_buf, mapping),
2519 skb_headlen(skb), PCI_DMA_TODEVICE);
2520
2521 tx_buf->skb = NULL;
2522 last = skb_shinfo(skb)->nr_frags;
2523
2524 for (i = 0; i < last; i++) {
2525 sw_cons = NEXT_TX_BD(sw_cons);
2526
2527 pci_unmap_page(bp->pdev,
2528 pci_unmap_addr(
2529 &bp->tx_buf_ring[TX_RING_IDX(sw_cons)],
2530 mapping),
2531 skb_shinfo(skb)->frags[i].size,
2532 PCI_DMA_TODEVICE);
2533 }
2534
2535 sw_cons = NEXT_TX_BD(sw_cons);
2536
745720e5 2537 dev_kfree_skb(skb);
57851d84
MC		 2538 tx_pkt++;
2539 if (tx_pkt == budget)
2540 break;
b6016b76 2541
35efa7c1 2542 hw_cons = bnx2_get_hw_tx_cons(bnapi);
b6016b76
MC		 2543 }
2544
a550c99b
MC		 2545 bnapi->hw_tx_cons = hw_cons;
2546 bnapi->tx_cons = sw_cons;
2f8af120
MC		 2547 /* Need to make the tx_cons update visible to bnx2_start_xmit()
2548 * before checking for netif_queue_stopped(). Without the
2549 * memory barrier, there is a small possibility that bnx2_start_xmit()
2550 * will miss it and cause the queue to be stopped forever.
2551 */
2552 smp_mb();
b6016b76 2553
2f8af120 2554 if (unlikely(netif_queue_stopped(bp->dev)) &&
a550c99b 2555 (bnx2_tx_avail(bp, bnapi) > bp->tx_wake_thresh)) {
2f8af120 2556 netif_tx_lock(bp->dev);
b6016b76 2557 if ((netif_queue_stopped(bp->dev)) &&
a550c99b 2558 (bnx2_tx_avail(bp, bnapi) > bp->tx_wake_thresh))
b6016b76 2559 netif_wake_queue(bp->dev);
2f8af120 2560 netif_tx_unlock(bp->dev);
b6016b76 2561 }
57851d84 2562 return tx_pkt;
b6016b76
MC		 2563}
2564
1db82f2a 2565static void
a1f60190
MC		 2566bnx2_reuse_rx_skb_pages(struct bnx2 *bp, struct bnx2_napi *bnapi,
2567 struct sk_buff *skb, int count)
1db82f2a
MC		 2568{
2569 struct sw_pg *cons_rx_pg, *prod_rx_pg;
2570 struct rx_bd *cons_bd, *prod_bd;
2571 dma_addr_t mapping;
2572 int i;
a1f60190
MC		 2573 u16 hw_prod = bnapi->rx_pg_prod, prod;
2574 u16 cons = bnapi->rx_pg_cons;
1db82f2a
MC		 2575
2576 for (i = 0; i < count; i++) {
2577 prod = RX_PG_RING_IDX(hw_prod);
2578
2579 prod_rx_pg = &bp->rx_pg_ring[prod];
2580 cons_rx_pg = &bp->rx_pg_ring[cons];
2581 cons_bd = &bp->rx_pg_desc_ring[RX_RING(cons)][RX_IDX(cons)];
2582 prod_bd = &bp->rx_pg_desc_ring[RX_RING(prod)][RX_IDX(prod)];
2583
2584 if (i == 0 && skb) {
2585 struct page *page;
2586 struct skb_shared_info *shinfo;
2587
2588 shinfo = skb_shinfo(skb);
2589 shinfo->nr_frags--;
2590 page = shinfo->frags[shinfo->nr_frags].page;
2591 shinfo->frags[shinfo->nr_frags].page = NULL;
2592 mapping = pci_map_page(bp->pdev, page, 0, PAGE_SIZE,
2593 PCI_DMA_FROMDEVICE);
2594 cons_rx_pg->page = page;
2595 pci_unmap_addr_set(cons_rx_pg, mapping, mapping);
2596 dev_kfree_skb(skb);
2597 }
2598 if (prod != cons) {
2599 prod_rx_pg->page = cons_rx_pg->page;
2600 cons_rx_pg->page = NULL;
2601 pci_unmap_addr_set(prod_rx_pg, mapping,
2602 pci_unmap_addr(cons_rx_pg, mapping));
2603
2604 prod_bd->rx_bd_haddr_hi = cons_bd->rx_bd_haddr_hi;
2605 prod_bd->rx_bd_haddr_lo = cons_bd->rx_bd_haddr_lo;
2606
2607 }
2608 cons = RX_PG_RING_IDX(NEXT_RX_BD(cons));
2609 hw_prod = NEXT_RX_BD(hw_prod);
2610 }
a1f60190
MC		 2611 bnapi->rx_pg_prod = hw_prod;
2612 bnapi->rx_pg_cons = cons;
1db82f2a
MC		 2613}
2614
b6016b76 2615static inline void
a1f60190 2616bnx2_reuse_rx_skb(struct bnx2 *bp, struct bnx2_napi *bnapi, struct sk_buff *skb,
b6016b76
MC		 2617 u16 cons, u16 prod)
2618{
236b6394
MC		 2619 struct sw_bd *cons_rx_buf, *prod_rx_buf;
2620 struct rx_bd *cons_bd, *prod_bd;
2621
2622 cons_rx_buf = &bp->rx_buf_ring[cons];
2623 prod_rx_buf = &bp->rx_buf_ring[prod];
b6016b76
MC		 2624
2625 pci_dma_sync_single_for_device(bp->pdev,
2626 pci_unmap_addr(cons_rx_buf, mapping),
601d3d18 2627 BNX2_RX_OFFSET + BNX2_RX_COPY_THRESH, PCI_DMA_FROMDEVICE);
b6016b76 2628
a1f60190 2629 bnapi->rx_prod_bseq += bp->rx_buf_use_size;
b6016b76 2630
236b6394 2631 prod_rx_buf->skb = skb;
b6016b76 2632
236b6394
MC		 2633 if (cons == prod)
2634 return;
b6016b76 2635
236b6394
MC		 2636 pci_unmap_addr_set(prod_rx_buf, mapping,
2637 pci_unmap_addr(cons_rx_buf, mapping));
2638
3fdfcc2c
MC		 2639 cons_bd = &bp->rx_desc_ring[RX_RING(cons)][RX_IDX(cons)];
2640 prod_bd = &bp->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)];
236b6394
MC		 2641 prod_bd->rx_bd_haddr_hi = cons_bd->rx_bd_haddr_hi;
2642 prod_bd->rx_bd_haddr_lo = cons_bd->rx_bd_haddr_lo;
b6016b76
MC		 2643}
2644
85833c62 2645static int
a1f60190
MC		 2646bnx2_rx_skb(struct bnx2 *bp, struct bnx2_napi *bnapi, struct sk_buff *skb,
2647 unsigned int len, unsigned int hdr_len, dma_addr_t dma_addr,
2648 u32 ring_idx)
85833c62
MC		 2649{
2650 int err;
2651 u16 prod = ring_idx & 0xffff;
2652
a1f60190 2653 err = bnx2_alloc_rx_skb(bp, bnapi, prod);
85833c62 2654 if (unlikely(err)) {
a1f60190 2655 bnx2_reuse_rx_skb(bp, bnapi, skb, (u16) (ring_idx >> 16), prod);
1db82f2a
MC		 2656 if (hdr_len) {
2657 unsigned int raw_len = len + 4;
2658 int pages = PAGE_ALIGN(raw_len - hdr_len) >> PAGE_SHIFT;
2659
a1f60190 2660 bnx2_reuse_rx_skb_pages(bp, bnapi, NULL, pages);
1db82f2a 2661 }
85833c62
MC		 2662 return err;
2663 }
2664
d89cb6af 2665 skb_reserve(skb, BNX2_RX_OFFSET);
85833c62
MC		 2666 pci_unmap_single(bp->pdev, dma_addr, bp->rx_buf_use_size,
2667 PCI_DMA_FROMDEVICE);
2668
1db82f2a
MC		 2669 if (hdr_len == 0) {
2670 skb_put(skb, len);
2671 return 0;
2672 } else {
2673 unsigned int i, frag_len, frag_size, pages;
2674 struct sw_pg *rx_pg;
a1f60190
MC		 2675 u16 pg_cons = bnapi->rx_pg_cons;
2676 u16 pg_prod = bnapi->rx_pg_prod;
1db82f2a
MC		 2677
2678 frag_size = len + 4 - hdr_len;
2679 pages = PAGE_ALIGN(frag_size) >> PAGE_SHIFT;
2680 skb_put(skb, hdr_len);
2681
2682 for (i = 0; i < pages; i++) {
2683 frag_len = min(frag_size, (unsigned int) PAGE_SIZE);
2684 if (unlikely(frag_len <= 4)) {
2685 unsigned int tail = 4 - frag_len;
2686
a1f60190
MC		 2687 bnapi->rx_pg_cons = pg_cons;
2688 bnapi->rx_pg_prod = pg_prod;
2689 bnx2_reuse_rx_skb_pages(bp, bnapi, NULL,
2690 pages - i);
1db82f2a
MC		 2691 skb->len -= tail;
2692 if (i == 0) {
2693 skb->tail -= tail;
2694 } else {
2695 skb_frag_t *frag =
2696 &skb_shinfo(skb)->frags[i - 1];
2697 frag->size -= tail;
2698 skb->data_len -= tail;
2699 skb->truesize -= tail;
2700 }
2701 return 0;
2702 }
2703 rx_pg = &bp->rx_pg_ring[pg_cons];
2704
2705 pci_unmap_page(bp->pdev, pci_unmap_addr(rx_pg, mapping),
2706 PAGE_SIZE, PCI_DMA_FROMDEVICE);
2707
2708 if (i == pages - 1)
2709 frag_len -= 4;
2710
2711 skb_fill_page_desc(skb, i, rx_pg->page, 0, frag_len);
2712 rx_pg->page = NULL;
2713
2714 err = bnx2_alloc_rx_page(bp, RX_PG_RING_IDX(pg_prod));
2715 if (unlikely(err)) {
a1f60190
MC		 2716 bnapi->rx_pg_cons = pg_cons;
2717 bnapi->rx_pg_prod = pg_prod;
2718 bnx2_reuse_rx_skb_pages(bp, bnapi, skb,
2719 pages - i);
1db82f2a
MC		 2720 return err;
2721 }
2722
2723 frag_size -= frag_len;
2724 skb->data_len += frag_len;
2725 skb->truesize += frag_len;
2726 skb->len += frag_len;
2727
2728 pg_prod = NEXT_RX_BD(pg_prod);
2729 pg_cons = RX_PG_RING_IDX(NEXT_RX_BD(pg_cons));
2730 }
a1f60190
MC		 2731 bnapi->rx_pg_prod = pg_prod;
2732 bnapi->rx_pg_cons = pg_cons;
1db82f2a 2733 }
85833c62
MC		 2734 return 0;
2735}
2736
c09c2627 2737static inline u16
35efa7c1 2738bnx2_get_hw_rx_cons(struct bnx2_napi *bnapi)
c09c2627 2739{
35efa7c1 2740 u16 cons = bnapi->status_blk->status_rx_quick_consumer_index0;
c09c2627
MC		 2741
2742 if (unlikely((cons & MAX_RX_DESC_CNT) == MAX_RX_DESC_CNT))
2743 cons++;
2744 return cons;
2745}
2746
b6016b76 2747static int
35efa7c1 2748bnx2_rx_int(struct bnx2 *bp, struct bnx2_napi *bnapi, int budget)
b6016b76
MC		 2749{
2750 u16 hw_cons, sw_cons, sw_ring_cons, sw_prod, sw_ring_prod;
2751 struct l2_fhdr *rx_hdr;
1db82f2a 2752 int rx_pkt = 0, pg_ring_used = 0;
b6016b76 2753
35efa7c1 2754 hw_cons = bnx2_get_hw_rx_cons(bnapi);
a1f60190
MC		 2755 sw_cons = bnapi->rx_cons;
2756 sw_prod = bnapi->rx_prod;
b6016b76
MC		 2757
2758 /* Memory barrier necessary as speculative reads of the rx
2759 * buffer can be ahead of the index in the status block
2760 */
2761 rmb();
2762 while (sw_cons != hw_cons) {
1db82f2a 2763 unsigned int len, hdr_len;
ade2bfe7 2764 u32 status;
b6016b76
MC		 2765 struct sw_bd *rx_buf;
2766 struct sk_buff *skb;
236b6394 2767 dma_addr_t dma_addr;
b6016b76
MC		 2768
2769 sw_ring_cons = RX_RING_IDX(sw_cons);
2770 sw_ring_prod = RX_RING_IDX(sw_prod);
2771
2772 rx_buf = &bp->rx_buf_ring[sw_ring_cons];
2773 skb = rx_buf->skb;
236b6394
MC		 2774
2775 rx_buf->skb = NULL;
2776
2777 dma_addr = pci_unmap_addr(rx_buf, mapping);
2778
2779 pci_dma_sync_single_for_cpu(bp->pdev, dma_addr,
601d3d18
BL		 2780 BNX2_RX_OFFSET + BNX2_RX_COPY_THRESH,
2781 PCI_DMA_FROMDEVICE);
b6016b76
MC		 2782
2783 rx_hdr = (struct l2_fhdr *) skb->data;
1db82f2a 2784 len = rx_hdr->l2_fhdr_pkt_len;
b6016b76 2785
ade2bfe7 2786 if ((status = rx_hdr->l2_fhdr_status) &
b6016b76
MC		 2787 (L2_FHDR_ERRORS_BAD_CRC |
2788 L2_FHDR_ERRORS_PHY_DECODE |
2789 L2_FHDR_ERRORS_ALIGNMENT |
2790 L2_FHDR_ERRORS_TOO_SHORT |
2791 L2_FHDR_ERRORS_GIANT_FRAME)) {
2792
a1f60190
MC		 2793 bnx2_reuse_rx_skb(bp, bnapi, skb, sw_ring_cons,
2794 sw_ring_prod);
85833c62 2795 goto next_rx;
b6016b76 2796 }
1db82f2a
MC		 2797 hdr_len = 0;
2798 if (status & L2_FHDR_STATUS_SPLIT) {
2799 hdr_len = rx_hdr->l2_fhdr_ip_xsum;
2800 pg_ring_used = 1;
2801 } else if (len > bp->rx_jumbo_thresh) {
2802 hdr_len = bp->rx_jumbo_thresh;
2803 pg_ring_used = 1;
2804 }
2805
2806 len -= 4;
b6016b76 2807
5d5d0015 2808 if (len <= bp->rx_copy_thresh) {
b6016b76
MC		 2809 struct sk_buff *new_skb;
2810
932f3772 2811 new_skb = netdev_alloc_skb(bp->dev, len + 2);
85833c62 2812 if (new_skb == NULL) {
a1f60190 2813 bnx2_reuse_rx_skb(bp, bnapi, skb, sw_ring_cons,
85833c62
MC		 2814 sw_ring_prod);
2815 goto next_rx;
2816 }
b6016b76
MC		 2817
2818 /* aligned copy */
d89cb6af
BL		 2819 skb_copy_from_linear_data_offset(skb,
2820 BNX2_RX_OFFSET - 2,
d626f62b 2821 new_skb->data, len + 2);
b6016b76
MC		 2822 skb_reserve(new_skb, 2);
2823 skb_put(new_skb, len);
b6016b76 2824
a1f60190 2825 bnx2_reuse_rx_skb(bp, bnapi, skb,
b6016b76
MC		 2826 sw_ring_cons, sw_ring_prod);
2827
2828 skb = new_skb;
a1f60190
MC		 2829 } else if (unlikely(bnx2_rx_skb(bp, bnapi, skb, len, hdr_len,
2830 dma_addr, (sw_ring_cons << 16) | sw_ring_prod)))
b6016b76 2831 goto next_rx;
b6016b76
MC		 2832
2833 skb->protocol = eth_type_trans(skb, bp->dev);
2834
2835 if ((len > (bp->dev->mtu + ETH_HLEN)) &&
d1e100ba 2836 (ntohs(skb->protocol) != 0x8100)) {
b6016b76 2837
745720e5 2838 dev_kfree_skb(skb);
b6016b76
MC		 2839 goto next_rx;
2840
2841 }
2842
b6016b76
MC		 2843 skb->ip_summed = CHECKSUM_NONE;
2844 if (bp->rx_csum &&
2845 (status & (L2_FHDR_STATUS_TCP_SEGMENT |
2846 L2_FHDR_STATUS_UDP_DATAGRAM))) {
2847
ade2bfe7
MC		 2848 if (likely((status & (L2_FHDR_ERRORS_TCP_XSUM |
2849 L2_FHDR_ERRORS_UDP_XSUM)) == 0))
b6016b76
MC		 2850 skb->ip_summed = CHECKSUM_UNNECESSARY;
2851 }
2852
2853#ifdef BCM_VLAN
79ea13ce 2854 if ((status & L2_FHDR_STATUS_L2_VLAN_TAG) && bp->vlgrp) {
b6016b76
MC		 2855 vlan_hwaccel_receive_skb(skb, bp->vlgrp,
2856 rx_hdr->l2_fhdr_vlan_tag);
2857 }
2858 else
2859#endif
2860 netif_receive_skb(skb);
2861
2862 bp->dev->last_rx = jiffies;
2863 rx_pkt++;
2864
2865next_rx:
b6016b76
MC		 2866 sw_cons = NEXT_RX_BD(sw_cons);
2867 sw_prod = NEXT_RX_BD(sw_prod);
2868
2869 if ((rx_pkt == budget))
2870 break;
f4e418f7
MC		 2871
2872 /* Refresh hw_cons to see if there is new work */
2873 if (sw_cons == hw_cons) {
35efa7c1 2874 hw_cons = bnx2_get_hw_rx_cons(bnapi);
f4e418f7
MC		 2875 rmb();
2876 }
b6016b76 2877 }
a1f60190
MC		 2878 bnapi->rx_cons = sw_cons;
2879 bnapi->rx_prod = sw_prod;
b6016b76 2880
1db82f2a
MC		 2881 if (pg_ring_used)
2882 REG_WR16(bp, MB_RX_CID_ADDR + BNX2_L2CTX_HOST_PG_BDIDX,
a1f60190 2883 bnapi->rx_pg_prod);
1db82f2a 2884
b6016b76
MC		 2885 REG_WR16(bp, MB_RX_CID_ADDR + BNX2_L2CTX_HOST_BDIDX, sw_prod);
2886
a1f60190 2887 REG_WR(bp, MB_RX_CID_ADDR + BNX2_L2CTX_HOST_BSEQ, bnapi->rx_prod_bseq);
b6016b76
MC		 2888
2889 mmiowb();
2890
2891 return rx_pkt;
2892
2893}
2894
2895/* MSI ISR - The only difference between this and the INTx ISR
2896 * is that the MSI interrupt is always serviced.
2897 */
2898static irqreturn_t
7d12e780 2899bnx2_msi(int irq, void *dev_instance)
b6016b76
MC		 2900{
2901 struct net_device *dev = dev_instance;
972ec0d4 2902 struct bnx2 *bp = netdev_priv(dev);
b4b36042 2903 struct bnx2_napi *bnapi = &bp->bnx2_napi[0];
b6016b76 2904
35efa7c1 2905 prefetch(bnapi->status_blk);
b6016b76
MC		 2906 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
2907 BNX2_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM |
2908 BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
2909
2910 /* Return here if interrupt is disabled. */
73eef4cd
MC		 2911 if (unlikely(atomic_read(&bp->intr_sem) != 0))
2912 return IRQ_HANDLED;
b6016b76 2913
35efa7c1 2914 netif_rx_schedule(dev, &bnapi->napi);
b6016b76 2915
73eef4cd 2916 return IRQ_HANDLED;
b6016b76
MC		 2917}
2918
8e6a72c4
MC		 2919static irqreturn_t
2920bnx2_msi_1shot(int irq, void *dev_instance)
2921{
2922 struct net_device *dev = dev_instance;
2923 struct bnx2 *bp = netdev_priv(dev);
b4b36042 2924 struct bnx2_napi *bnapi = &bp->bnx2_napi[0];
8e6a72c4 2925
35efa7c1 2926 prefetch(bnapi->status_blk);
8e6a72c4
MC		 2927
2928 /* Return here if interrupt is disabled. */
2929 if (unlikely(atomic_read(&bp->intr_sem) != 0))
2930 return IRQ_HANDLED;
2931
35efa7c1 2932 netif_rx_schedule(dev, &bnapi->napi);
8e6a72c4
MC		 2933
2934 return IRQ_HANDLED;
2935}
2936
b6016b76 2937static irqreturn_t
7d12e780 2938bnx2_interrupt(int irq, void *dev_instance)
b6016b76
MC		 2939{
2940 struct net_device *dev = dev_instance;
972ec0d4 2941 struct bnx2 *bp = netdev_priv(dev);
b4b36042 2942 struct bnx2_napi *bnapi = &bp->bnx2_napi[0];
35efa7c1 2943 struct status_block *sblk = bnapi->status_blk;
b6016b76
MC		 2944
2945 /* When using INTx, it is possible for the interrupt to arrive
2946 * at the CPU before the status block posted prior to the
2947 * interrupt. Reading a register will flush the status block.
2948 * When using MSI, the MSI message will always complete after
2949 * the status block write.
2950 */
35efa7c1 2951 if ((sblk->status_idx == bnapi->last_status_idx) &&
b6016b76
MC		 2952 (REG_RD(bp, BNX2_PCICFG_MISC_STATUS) &
2953 BNX2_PCICFG_MISC_STATUS_INTA_VALUE))
73eef4cd 2954 return IRQ_NONE;
b6016b76
MC		 2955
2956 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
2957 BNX2_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM |
2958 BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
2959
b8a7ce7b
MC		 2960 /* Read back to deassert IRQ immediately to avoid too many
2961 * spurious interrupts.
2962 */
2963 REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD);
2964
b6016b76 2965 /* Return here if interrupt is shared and is disabled. */
73eef4cd
MC		 2966 if (unlikely(atomic_read(&bp->intr_sem) != 0))
2967 return IRQ_HANDLED;
b6016b76 2968
35efa7c1
MC		 2969 if (netif_rx_schedule_prep(dev, &bnapi->napi)) {
2970 bnapi->last_status_idx = sblk->status_idx;
2971 __netif_rx_schedule(dev, &bnapi->napi);
b8a7ce7b 2972 }
b6016b76 2973
73eef4cd 2974 return IRQ_HANDLED;
b6016b76
MC		 2975}
2976
57851d84
MC		 2977static irqreturn_t
2978bnx2_tx_msix(int irq, void *dev_instance)
2979{
2980 struct net_device *dev = dev_instance;
2981 struct bnx2 *bp = netdev_priv(dev);
2982 struct bnx2_napi *bnapi = &bp->bnx2_napi[BNX2_TX_VEC];
2983
2984 prefetch(bnapi->status_blk_msix);
2985
2986 /* Return here if interrupt is disabled. */
2987 if (unlikely(atomic_read(&bp->intr_sem) != 0))
2988 return IRQ_HANDLED;
2989
2990 netif_rx_schedule(dev, &bnapi->napi);
2991 return IRQ_HANDLED;
2992}
2993
0d8a6571
MC		 2994#define STATUS_ATTN_EVENTS (STATUS_ATTN_BITS_LINK_STATE | \
2995 STATUS_ATTN_BITS_TIMER_ABORT)
da3e4fbe 2996
f4e418f7 2997static inline int
35efa7c1 2998bnx2_has_work(struct bnx2_napi *bnapi)
f4e418f7 2999{
1097f5e9 3000 struct status_block *sblk = bnapi->status_blk;
f4e418f7 3001
a1f60190 3002 if ((bnx2_get_hw_rx_cons(bnapi) != bnapi->rx_cons) ||
a550c99b 3003 (bnx2_get_hw_tx_cons(bnapi) != bnapi->hw_tx_cons))
f4e418f7
MC		 3004 return 1;
3005
da3e4fbe
MC		 3006 if ((sblk->status_attn_bits & STATUS_ATTN_EVENTS) !=
3007 (sblk->status_attn_bits_ack & STATUS_ATTN_EVENTS))
f4e418f7
MC		 3008 return 1;
3009
3010 return 0;
3011}
3012
57851d84
MC		 3013static int bnx2_tx_poll(struct napi_struct *napi, int budget)
3014{
3015 struct bnx2_napi *bnapi = container_of(napi, struct bnx2_napi, napi);
3016 struct bnx2 *bp = bnapi->bp;
3017 int work_done = 0;
3018 struct status_block_msix *sblk = bnapi->status_blk_msix;
3019
3020 do {
3021 work_done += bnx2_tx_int(bp, bnapi, budget - work_done);
3022 if (unlikely(work_done >= budget))
3023 return work_done;
3024
3025 bnapi->last_status_idx = sblk->status_idx;
3026 rmb();
3027 } while (bnx2_get_hw_tx_cons(bnapi) != bnapi->hw_tx_cons);
3028
3029 netif_rx_complete(bp->dev, napi);
3030 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num |
3031 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
3032 bnapi->last_status_idx);
3033 return work_done;
3034}
3035
35efa7c1
MC		 3036static int bnx2_poll_work(struct bnx2 *bp, struct bnx2_napi *bnapi,
3037 int work_done, int budget)
b6016b76 3038{
35efa7c1 3039 struct status_block *sblk = bnapi->status_blk;
da3e4fbe
MC		 3040 u32 status_attn_bits = sblk->status_attn_bits;
3041 u32 status_attn_bits_ack = sblk->status_attn_bits_ack;
b6016b76 3042
da3e4fbe
MC		 3043 if ((status_attn_bits & STATUS_ATTN_EVENTS) !=
3044 (status_attn_bits_ack & STATUS_ATTN_EVENTS)) {
b6016b76 3045
35efa7c1 3046 bnx2_phy_int(bp, bnapi);
bf5295bb
MC		 3047
3048 /* This is needed to take care of transient status
3049 * during link changes.
3050 */
3051 REG_WR(bp, BNX2_HC_COMMAND,
3052 bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
3053 REG_RD(bp, BNX2_HC_COMMAND);
b6016b76
MC		 3054 }
3055
a550c99b 3056 if (bnx2_get_hw_tx_cons(bnapi) != bnapi->hw_tx_cons)
57851d84 3057 bnx2_tx_int(bp, bnapi, 0);
b6016b76 3058
a1f60190 3059 if (bnx2_get_hw_rx_cons(bnapi) != bnapi->rx_cons)
35efa7c1 3060 work_done += bnx2_rx_int(bp, bnapi, budget - work_done);
6aa20a22 3061
6f535763
DM		 3062 return work_done;
3063}
3064
3065static int bnx2_poll(struct napi_struct *napi, int budget)
3066{
35efa7c1
MC		 3067 struct bnx2_napi *bnapi = container_of(napi, struct bnx2_napi, napi);
3068 struct bnx2 *bp = bnapi->bp;
6f535763 3069 int work_done = 0;
35efa7c1 3070 struct status_block *sblk = bnapi->status_blk;
6f535763
DM		 3071
3072 while (1) {
35efa7c1 3073 work_done = bnx2_poll_work(bp, bnapi, work_done, budget);
f4e418f7 3074
6f535763
DM		 3075 if (unlikely(work_done >= budget))
3076 break;
3077
35efa7c1 3078 /* bnapi->last_status_idx is used below to tell the hw how
6dee6421
MC		 3079 * much work has been processed, so we must read it before
3080 * checking for more work.
3081 */
35efa7c1 3082 bnapi->last_status_idx = sblk->status_idx;
6dee6421 3083 rmb();
35efa7c1 3084 if (likely(!bnx2_has_work(bnapi))) {
6f535763 3085 netif_rx_complete(bp->dev, napi);
f86e82fb 3086 if (likely(bp->flags & BNX2_FLAG_USING_MSI_OR_MSIX)) {
6f535763
DM		 3087 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
3088 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
35efa7c1 3089 bnapi->last_status_idx);
6dee6421 3090 break;
6f535763 3091 }
1269a8a6
MC		 3092 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
3093 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
6f535763 3094 BNX2_PCICFG_INT_ACK_CMD_MASK_INT |
35efa7c1 3095 bnapi->last_status_idx);
1269a8a6 3096
6f535763
DM		 3097 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
3098 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
35efa7c1 3099 bnapi->last_status_idx);
6f535763
DM		 3100 break;
3101 }
b6016b76
MC		 3102 }
3103
bea3348e 3104 return work_done;
b6016b76
MC		 3105}
3106
932ff279 3107/* Called with rtnl_lock from vlan functions and also netif_tx_lock
b6016b76
MC		 3108 * from set_multicast.
3109 */
3110static void
3111bnx2_set_rx_mode(struct net_device *dev)
3112{
972ec0d4 3113 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 3114 u32 rx_mode, sort_mode;
3115 int i;
b6016b76 3116
c770a65c 3117 spin_lock_bh(&bp->phy_lock);
b6016b76
MC		 3118
3119 rx_mode = bp->rx_mode & ~(BNX2_EMAC_RX_MODE_PROMISCUOUS |
3120 BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG);
3121 sort_mode = 1 | BNX2_RPM_SORT_USER0_BC_EN;
3122#ifdef BCM_VLAN
f86e82fb 3123 if (!bp->vlgrp && !(bp->flags & BNX2_FLAG_ASF_ENABLE))
b6016b76 3124 rx_mode |= BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG;
b6016b76 3125#else
f86e82fb 3126 if (!(bp->flags & BNX2_FLAG_ASF_ENABLE))
e29054f9 3127 rx_mode |= BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG;
b6016b76
MC		 3128#endif
3129 if (dev->flags & IFF_PROMISC) {
3130 /* Promiscuous mode. */
3131 rx_mode |= BNX2_EMAC_RX_MODE_PROMISCUOUS;
7510873d
MC		 3132 sort_mode |= BNX2_RPM_SORT_USER0_PROM_EN |
3133 BNX2_RPM_SORT_USER0_PROM_VLAN;
b6016b76
MC		 3134 }
3135 else if (dev->flags & IFF_ALLMULTI) {
3136 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
3137 REG_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),
3138 0xffffffff);
3139 }
3140 sort_mode |= BNX2_RPM_SORT_USER0_MC_EN;
3141 }
3142 else {
3143 /* Accept one or more multicast(s). */
3144 struct dev_mc_list *mclist;
3145 u32 mc_filter[NUM_MC_HASH_REGISTERS];
3146 u32 regidx;
3147 u32 bit;
3148 u32 crc;
3149
3150 memset(mc_filter, 0, 4 * NUM_MC_HASH_REGISTERS);
3151
3152 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
3153 i++, mclist = mclist->next) {
3154
3155 crc = ether_crc_le(ETH_ALEN, mclist->dmi_addr);
3156 bit = crc & 0xff;
3157 regidx = (bit & 0xe0) >> 5;
3158 bit &= 0x1f;
3159 mc_filter[regidx] |= (1 << bit);
3160 }
3161
3162 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
3163 REG_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),
3164 mc_filter[i]);
3165 }
3166
3167 sort_mode |= BNX2_RPM_SORT_USER0_MC_HSH_EN;
3168 }
3169
3170 if (rx_mode != bp->rx_mode) {
3171 bp->rx_mode = rx_mode;
3172 REG_WR(bp, BNX2_EMAC_RX_MODE, rx_mode);
3173 }
3174
3175 REG_WR(bp, BNX2_RPM_SORT_USER0, 0x0);
3176 REG_WR(bp, BNX2_RPM_SORT_USER0, sort_mode);
3177 REG_WR(bp, BNX2_RPM_SORT_USER0, sort_mode | BNX2_RPM_SORT_USER0_ENA);
3178
c770a65c 3179 spin_unlock_bh(&bp->phy_lock);
b6016b76
MC		 3180}
3181
3182static void
b491edd5 3183load_rv2p_fw(struct bnx2 *bp, __le32 *rv2p_code, u32 rv2p_code_len,
b6016b76
MC		 3184 u32 rv2p_proc)
3185{
3186 int i;
3187 u32 val;
3188
d25be1d3
MC		 3189 if (rv2p_proc == RV2P_PROC2 && CHIP_NUM(bp) == CHIP_NUM_5709) {
3190 val = le32_to_cpu(rv2p_code[XI_RV2P_PROC2_MAX_BD_PAGE_LOC]);
3191 val &= ~XI_RV2P_PROC2_BD_PAGE_SIZE_MSK;
3192 val |= XI_RV2P_PROC2_BD_PAGE_SIZE;
3193 rv2p_code[XI_RV2P_PROC2_MAX_BD_PAGE_LOC] = cpu_to_le32(val);
3194 }
b6016b76
MC		 3195
3196 for (i = 0; i < rv2p_code_len; i += 8) {
b491edd5 3197 REG_WR(bp, BNX2_RV2P_INSTR_HIGH, le32_to_cpu(*rv2p_code));
b6016b76 3198 rv2p_code++;
b491edd5 3199 REG_WR(bp, BNX2_RV2P_INSTR_LOW, le32_to_cpu(*rv2p_code));
b6016b76
MC		 3200 rv2p_code++;
3201
3202 if (rv2p_proc == RV2P_PROC1) {
3203 val = (i / 8) | BNX2_RV2P_PROC1_ADDR_CMD_RDWR;
3204 REG_WR(bp, BNX2_RV2P_PROC1_ADDR_CMD, val);
3205 }
3206 else {
3207 val = (i / 8) | BNX2_RV2P_PROC2_ADDR_CMD_RDWR;
3208 REG_WR(bp, BNX2_RV2P_PROC2_ADDR_CMD, val);
3209 }
3210 }
3211
3212 /* Reset the processor, un-stall is done later. */
3213 if (rv2p_proc == RV2P_PROC1) {
3214 REG_WR(bp, BNX2_RV2P_COMMAND, BNX2_RV2P_COMMAND_PROC1_RESET);
3215 }
3216 else {
3217 REG_WR(bp, BNX2_RV2P_COMMAND, BNX2_RV2P_COMMAND_PROC2_RESET);
3218 }
3219}
3220
af3ee519 3221static int
10343cca 3222load_cpu_fw(struct bnx2 *bp, const struct cpu_reg *cpu_reg, struct fw_info *fw)
b6016b76
MC		 3223{
3224 u32 offset;
3225 u32 val;
af3ee519 3226 int rc;
b6016b76
MC		 3227
3228 /* Halt the CPU. */
2726d6e1 3229 val = bnx2_reg_rd_ind(bp, cpu_reg->mode);
b6016b76 3230 val |= cpu_reg->mode_value_halt;
2726d6e1
MC		 3231 bnx2_reg_wr_ind(bp, cpu_reg->mode, val);
3232 bnx2_reg_wr_ind(bp, cpu_reg->state, cpu_reg->state_value_clear);
b6016b76
MC		 3233
3234 /* Load the Text area. */
3235 offset = cpu_reg->spad_base + (fw->text_addr - cpu_reg->mips_view_base);
af3ee519 3236 if (fw->gz_text) {
b6016b76
MC		 3237 int j;
3238
ea1f8d5c
MC		 3239 rc = zlib_inflate_blob(fw->text, FW_BUF_SIZE, fw->gz_text,
3240 fw->gz_text_len);
3241 if (rc < 0)
b3448b0b 3242 return rc;
ea1f8d5c 3243
b6016b76 3244 for (j = 0; j < (fw->text_len / 4); j++, offset += 4) {
2726d6e1 3245 bnx2_reg_wr_ind(bp, offset, le32_to_cpu(fw->text[j]));
b6016b76
MC		 3246 }
3247 }
3248
3249 /* Load the Data area. */
3250 offset = cpu_reg->spad_base + (fw->data_addr - cpu_reg->mips_view_base);
3251 if (fw->data) {
3252 int j;
3253
3254 for (j = 0; j < (fw->data_len / 4); j++, offset += 4) {
2726d6e1 3255 bnx2_reg_wr_ind(bp, offset, fw->data[j]);
b6016b76
MC		 3256 }
3257 }
3258
3259 /* Load the SBSS area. */
3260 offset = cpu_reg->spad_base + (fw->sbss_addr - cpu_reg->mips_view_base);
ea1f8d5c 3261 if (fw->sbss_len) {
b6016b76
MC		 3262 int j;
3263
3264 for (j = 0; j < (fw->sbss_len / 4); j++, offset += 4) {
2726d6e1 3265 bnx2_reg_wr_ind(bp, offset, 0);
b6016b76
MC		 3266 }
3267 }
3268
3269 /* Load the BSS area. */
3270 offset = cpu_reg->spad_base + (fw->bss_addr - cpu_reg->mips_view_base);
ea1f8d5c 3271 if (fw->bss_len) {
b6016b76
MC		 3272 int j;
3273
3274 for (j = 0; j < (fw->bss_len/4); j++, offset += 4) {
2726d6e1 3275 bnx2_reg_wr_ind(bp, offset, 0);
b6016b76
MC		 3276 }
3277 }
3278
3279 /* Load the Read-Only area. */
3280 offset = cpu_reg->spad_base +
3281 (fw->rodata_addr - cpu_reg->mips_view_base);
3282 if (fw->rodata) {
3283 int j;
3284
3285 for (j = 0; j < (fw->rodata_len / 4); j++, offset += 4) {
2726d6e1 3286 bnx2_reg_wr_ind(bp, offset, fw->rodata[j]);
b6016b76
MC		 3287 }
3288 }
3289
3290 /* Clear the pre-fetch instruction. */
2726d6e1
MC		 3291 bnx2_reg_wr_ind(bp, cpu_reg->inst, 0);
3292 bnx2_reg_wr_ind(bp, cpu_reg->pc, fw->start_addr);
b6016b76
MC		 3293
3294 /* Start the CPU. */
2726d6e1 3295 val = bnx2_reg_rd_ind(bp, cpu_reg->mode);
b6016b76 3296 val &= ~cpu_reg->mode_value_halt;
2726d6e1
MC		 3297 bnx2_reg_wr_ind(bp, cpu_reg->state, cpu_reg->state_value_clear);
3298 bnx2_reg_wr_ind(bp, cpu_reg->mode, val);
af3ee519
MC		 3299
3300 return 0;
b6016b76
MC		 3301}
3302
fba9fe91 3303static int
b6016b76
MC		 3304bnx2_init_cpus(struct bnx2 *bp)
3305{
af3ee519 3306 struct fw_info *fw;
110d0ef9
MC		 3307 int rc, rv2p_len;
3308 void *text, *rv2p;
b6016b76
MC		 3309
3310 /* Initialize the RV2P processor. */
b3448b0b
DV		 3311 text = vmalloc(FW_BUF_SIZE);
3312 if (!text)
3313 return -ENOMEM;
110d0ef9
MC		 3314 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
3315 rv2p = bnx2_xi_rv2p_proc1;
3316 rv2p_len = sizeof(bnx2_xi_rv2p_proc1);
3317 } else {
3318 rv2p = bnx2_rv2p_proc1;
3319 rv2p_len = sizeof(bnx2_rv2p_proc1);
3320 }
3321 rc = zlib_inflate_blob(text, FW_BUF_SIZE, rv2p, rv2p_len);
ea1f8d5c 3322 if (rc < 0)
fba9fe91 3323 goto init_cpu_err;
ea1f8d5c 3324
b3448b0b 3325 load_rv2p_fw(bp, text, rc /* == len */, RV2P_PROC1);
fba9fe91 3326
110d0ef9
MC		 3327 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
3328 rv2p = bnx2_xi_rv2p_proc2;
3329 rv2p_len = sizeof(bnx2_xi_rv2p_proc2);
3330 } else {
3331 rv2p = bnx2_rv2p_proc2;
3332 rv2p_len = sizeof(bnx2_rv2p_proc2);
3333 }
3334 rc = zlib_inflate_blob(text, FW_BUF_SIZE, rv2p, rv2p_len);
ea1f8d5c 3335 if (rc < 0)
fba9fe91 3336 goto init_cpu_err;
ea1f8d5c 3337
b3448b0b 3338 load_rv2p_fw(bp, text, rc /* == len */, RV2P_PROC2);
b6016b76
MC		 3339
3340 /* Initialize the RX Processor. */
d43584c8
MC		 3341 if (CHIP_NUM(bp) == CHIP_NUM_5709)
3342 fw = &bnx2_rxp_fw_09;
3343 else
3344 fw = &bnx2_rxp_fw_06;
fba9fe91 3345
ea1f8d5c 3346 fw->text = text;
10343cca 3347 rc = load_cpu_fw(bp, &cpu_reg_rxp, fw);
fba9fe91
MC		 3348 if (rc)
3349 goto init_cpu_err;
3350
b6016b76 3351 /* Initialize the TX Processor. */
d43584c8
MC		 3352 if (CHIP_NUM(bp) == CHIP_NUM_5709)
3353 fw = &bnx2_txp_fw_09;
3354 else
3355 fw = &bnx2_txp_fw_06;
fba9fe91 3356
ea1f8d5c 3357 fw->text = text;
10343cca 3358 rc = load_cpu_fw(bp, &cpu_reg_txp, fw);
fba9fe91
MC		 3359 if (rc)
3360 goto init_cpu_err;
3361
b6016b76 3362 /* Initialize the TX Patch-up Processor. */
d43584c8
MC		 3363 if (CHIP_NUM(bp) == CHIP_NUM_5709)
3364 fw = &bnx2_tpat_fw_09;
3365 else
3366 fw = &bnx2_tpat_fw_06;
fba9fe91 3367
ea1f8d5c 3368 fw->text = text;
10343cca 3369 rc = load_cpu_fw(bp, &cpu_reg_tpat, fw);
fba9fe91
MC		 3370 if (rc)
3371 goto init_cpu_err;
3372
b6016b76 3373 /* Initialize the Completion Processor. */
d43584c8
MC		 3374 if (CHIP_NUM(bp) == CHIP_NUM_5709)
3375 fw = &bnx2_com_fw_09;
3376 else
3377 fw = &bnx2_com_fw_06;
fba9fe91 3378
ea1f8d5c 3379 fw->text = text;
10343cca 3380 rc = load_cpu_fw(bp, &cpu_reg_com, fw);
fba9fe91
MC		 3381 if (rc)
3382 goto init_cpu_err;
3383
d43584c8 3384 /* Initialize the Command Processor. */
110d0ef9 3385 if (CHIP_NUM(bp) == CHIP_NUM_5709)
d43584c8 3386 fw = &bnx2_cp_fw_09;
110d0ef9
MC		 3387 else
3388 fw = &bnx2_cp_fw_06;
3389
3390 fw->text = text;
10343cca 3391 rc = load_cpu_fw(bp, &cpu_reg_cp, fw);
b6016b76 3392
fba9fe91 3393init_cpu_err:
ea1f8d5c 3394 vfree(text);
fba9fe91 3395 return rc;
b6016b76
MC		 3396}
3397
3398static int
829ca9a3 3399bnx2_set_power_state(struct bnx2 *bp, pci_power_t state)
b6016b76
MC		 3400{
3401 u16 pmcsr;
3402
3403 pci_read_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL, &pmcsr);
3404
3405 switch (state) {
829ca9a3 3406 case PCI_D0: {
b6016b76
MC		 3407 u32 val;
3408
3409 pci_write_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL,
3410 (pmcsr & ~PCI_PM_CTRL_STATE_MASK) |
3411 PCI_PM_CTRL_PME_STATUS);
3412
3413 if (pmcsr & PCI_PM_CTRL_STATE_MASK)
3414 /* delay required during transition out of D3hot */
3415 msleep(20);
3416
3417 val = REG_RD(bp, BNX2_EMAC_MODE);
3418 val |= BNX2_EMAC_MODE_MPKT_RCVD | BNX2_EMAC_MODE_ACPI_RCVD;
3419 val &= ~BNX2_EMAC_MODE_MPKT;
3420 REG_WR(bp, BNX2_EMAC_MODE, val);
3421
3422 val = REG_RD(bp, BNX2_RPM_CONFIG);
3423 val &= ~BNX2_RPM_CONFIG_ACPI_ENA;
3424 REG_WR(bp, BNX2_RPM_CONFIG, val);
3425 break;
3426 }
829ca9a3 3427 case PCI_D3hot: {
b6016b76
MC		 3428 int i;
3429 u32 val, wol_msg;
3430
3431 if (bp->wol) {
3432 u32 advertising;
3433 u8 autoneg;
3434
3435 autoneg = bp->autoneg;
3436 advertising = bp->advertising;
3437
239cd343
MC		 3438 if (bp->phy_port == PORT_TP) {
3439 bp->autoneg = AUTONEG_SPEED;
3440 bp->advertising = ADVERTISED_10baseT_Half |
3441 ADVERTISED_10baseT_Full |
3442 ADVERTISED_100baseT_Half |
3443 ADVERTISED_100baseT_Full |
3444 ADVERTISED_Autoneg;
3445 }
b6016b76 3446
239cd343
MC		 3447 spin_lock_bh(&bp->phy_lock);
3448 bnx2_setup_phy(bp, bp->phy_port);
3449 spin_unlock_bh(&bp->phy_lock);
b6016b76
MC		 3450
3451 bp->autoneg = autoneg;
3452 bp->advertising = advertising;
3453
3454 bnx2_set_mac_addr(bp);
3455
3456 val = REG_RD(bp, BNX2_EMAC_MODE);
3457
3458 /* Enable port mode. */
3459 val &= ~BNX2_EMAC_MODE_PORT;
239cd343 3460 val |= BNX2_EMAC_MODE_MPKT_RCVD |
b6016b76 3461 BNX2_EMAC_MODE_ACPI_RCVD |
b6016b76 3462 BNX2_EMAC_MODE_MPKT;
239cd343
MC		 3463 if (bp->phy_port == PORT_TP)
3464 val |= BNX2_EMAC_MODE_PORT_MII;
3465 else {
3466 val |= BNX2_EMAC_MODE_PORT_GMII;
3467 if (bp->line_speed == SPEED_2500)
3468 val |= BNX2_EMAC_MODE_25G_MODE;
3469 }
b6016b76
MC		 3470
3471 REG_WR(bp, BNX2_EMAC_MODE, val);
3472
3473 /* receive all multicast */
3474 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
3475 REG_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),
3476 0xffffffff);
3477 }
3478 REG_WR(bp, BNX2_EMAC_RX_MODE,
3479 BNX2_EMAC_RX_MODE_SORT_MODE);
3480
3481 val = 1 | BNX2_RPM_SORT_USER0_BC_EN |
3482 BNX2_RPM_SORT_USER0_MC_EN;
3483 REG_WR(bp, BNX2_RPM_SORT_USER0, 0x0);
3484 REG_WR(bp, BNX2_RPM_SORT_USER0, val);
3485 REG_WR(bp, BNX2_RPM_SORT_USER0, val |
3486 BNX2_RPM_SORT_USER0_ENA);
3487
3488 /* Need to enable EMAC and RPM for WOL. */
3489 REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS,
3490 BNX2_MISC_ENABLE_SET_BITS_RX_PARSER_MAC_ENABLE |
3491 BNX2_MISC_ENABLE_SET_BITS_TX_HEADER_Q_ENABLE |
3492 BNX2_MISC_ENABLE_SET_BITS_EMAC_ENABLE);
3493
3494 val = REG_RD(bp, BNX2_RPM_CONFIG);
3495 val &= ~BNX2_RPM_CONFIG_ACPI_ENA;
3496 REG_WR(bp, BNX2_RPM_CONFIG, val);
3497
3498 wol_msg = BNX2_DRV_MSG_CODE_SUSPEND_WOL;
3499 }
3500 else {
3501 wol_msg = BNX2_DRV_MSG_CODE_SUSPEND_NO_WOL;
3502 }
3503
f86e82fb 3504 if (!(bp->flags & BNX2_FLAG_NO_WOL))
dda1e390 3505 bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT3 | wol_msg, 0);
b6016b76
MC		 3506
3507 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
3508 if ((CHIP_ID(bp) == CHIP_ID_5706_A0) ||
3509 (CHIP_ID(bp) == CHIP_ID_5706_A1)) {
3510
3511 if (bp->wol)
3512 pmcsr |= 3;
3513 }
3514 else {
3515 pmcsr |= 3;
3516 }
3517 if (bp->wol) {
3518 pmcsr |= PCI_PM_CTRL_PME_ENABLE;
3519 }
3520 pci_write_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL,
3521 pmcsr);
3522
3523 /* No more memory access after this point until
3524 * device is brought back to D0.
3525 */
3526 udelay(50);
3527 break;
3528 }
3529 default:
3530 return -EINVAL;
3531 }
3532 return 0;
3533}
3534
3535static int
3536bnx2_acquire_nvram_lock(struct bnx2 *bp)
3537{
3538 u32 val;
3539 int j;
3540
3541 /* Request access to the flash interface. */
3542 REG_WR(bp, BNX2_NVM_SW_ARB, BNX2_NVM_SW_ARB_ARB_REQ_SET2);
3543 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
3544 val = REG_RD(bp, BNX2_NVM_SW_ARB);
3545 if (val & BNX2_NVM_SW_ARB_ARB_ARB2)
3546 break;
3547
3548 udelay(5);
3549 }
3550
3551 if (j >= NVRAM_TIMEOUT_COUNT)
3552 return -EBUSY;
3553
3554 return 0;
3555}
3556
3557static int
3558bnx2_release_nvram_lock(struct bnx2 *bp)
3559{
3560 int j;
3561 u32 val;
3562
3563 /* Relinquish nvram interface. */
3564 REG_WR(bp, BNX2_NVM_SW_ARB, BNX2_NVM_SW_ARB_ARB_REQ_CLR2);
3565
3566 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
3567 val = REG_RD(bp, BNX2_NVM_SW_ARB);
3568 if (!(val & BNX2_NVM_SW_ARB_ARB_ARB2))
3569 break;
3570
3571 udelay(5);
3572 }
3573
3574 if (j >= NVRAM_TIMEOUT_COUNT)
3575 return -EBUSY;
3576
3577 return 0;
3578}
3579
3580
3581static int
3582bnx2_enable_nvram_write(struct bnx2 *bp)
3583{
3584 u32 val;
3585
3586 val = REG_RD(bp, BNX2_MISC_CFG);
3587 REG_WR(bp, BNX2_MISC_CFG, val | BNX2_MISC_CFG_NVM_WR_EN_PCI);
3588
e30372c9 3589 if (bp->flash_info->flags & BNX2_NV_WREN) {
b6016b76
MC		 3590 int j;
3591
3592 REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
3593 REG_WR(bp, BNX2_NVM_COMMAND,
3594 BNX2_NVM_COMMAND_WREN | BNX2_NVM_COMMAND_DOIT);
3595
3596 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
3597 udelay(5);
3598
3599 val = REG_RD(bp, BNX2_NVM_COMMAND);
3600 if (val & BNX2_NVM_COMMAND_DONE)
3601 break;
3602 }
3603
3604 if (j >= NVRAM_TIMEOUT_COUNT)
3605 return -EBUSY;
3606 }
3607 return 0;
3608}
3609
3610static void
3611bnx2_disable_nvram_write(struct bnx2 *bp)
3612{
3613 u32 val;
3614
3615 val = REG_RD(bp, BNX2_MISC_CFG);
3616 REG_WR(bp, BNX2_MISC_CFG, val & ~BNX2_MISC_CFG_NVM_WR_EN);
3617}
3618
3619
3620static void
3621bnx2_enable_nvram_access(struct bnx2 *bp)
3622{
3623 u32 val;
3624
3625 val = REG_RD(bp, BNX2_NVM_ACCESS_ENABLE);
3626 /* Enable both bits, even on read. */
6aa20a22 3627 REG_WR(bp, BNX2_NVM_ACCESS_ENABLE,
b6016b76
MC		 3628 val | BNX2_NVM_ACCESS_ENABLE_EN | BNX2_NVM_ACCESS_ENABLE_WR_EN);
3629}
3630
3631static void
3632bnx2_disable_nvram_access(struct bnx2 *bp)
3633{
3634 u32 val;
3635
3636 val = REG_RD(bp, BNX2_NVM_ACCESS_ENABLE);
3637 /* Disable both bits, even after read. */
6aa20a22 3638 REG_WR(bp, BNX2_NVM_ACCESS_ENABLE,
b6016b76
MC		 3639 val & ~(BNX2_NVM_ACCESS_ENABLE_EN |
3640 BNX2_NVM_ACCESS_ENABLE_WR_EN));
3641}
3642
3643static int
3644bnx2_nvram_erase_page(struct bnx2 *bp, u32 offset)
3645{
3646 u32 cmd;
3647 int j;
3648
e30372c9 3649 if (bp->flash_info->flags & BNX2_NV_BUFFERED)
b6016b76
MC		 3650 /* Buffered flash, no erase needed */
3651 return 0;
3652
3653 /* Build an erase command */
3654 cmd = BNX2_NVM_COMMAND_ERASE | BNX2_NVM_COMMAND_WR |
3655 BNX2_NVM_COMMAND_DOIT;
3656
3657 /* Need to clear DONE bit separately. */
3658 REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
3659
3660 /* Address of the NVRAM to read from. */
3661 REG_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);
3662
3663 /* Issue an erase command. */
3664 REG_WR(bp, BNX2_NVM_COMMAND, cmd);
3665
3666 /* Wait for completion. */
3667 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
3668 u32 val;
3669
3670 udelay(5);
3671
3672 val = REG_RD(bp, BNX2_NVM_COMMAND);
3673 if (val & BNX2_NVM_COMMAND_DONE)
3674 break;
3675 }
3676
3677 if (j >= NVRAM_TIMEOUT_COUNT)
3678 return -EBUSY;
3679
3680 return 0;
3681}
3682
3683static int
3684bnx2_nvram_read_dword(struct bnx2 *bp, u32 offset, u8 *ret_val, u32 cmd_flags)
3685{
3686 u32 cmd;
3687 int j;
3688
3689 /* Build the command word. */
3690 cmd = BNX2_NVM_COMMAND_DOIT | cmd_flags;
3691
e30372c9
MC		 3692 /* Calculate an offset of a buffered flash, not needed for 5709. */
3693 if (bp->flash_info->flags & BNX2_NV_TRANSLATE) {
b6016b76
MC		 3694 offset = ((offset / bp->flash_info->page_size) <<
3695 bp->flash_info->page_bits) +
3696 (offset % bp->flash_info->page_size);
3697 }
3698
3699 /* Need to clear DONE bit separately. */
3700 REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
3701
3702 /* Address of the NVRAM to read from. */
3703 REG_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);
3704
3705 /* Issue a read command. */
3706 REG_WR(bp, BNX2_NVM_COMMAND, cmd);
3707
3708 /* Wait for completion. */
3709 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
3710 u32 val;
3711
3712 udelay(5);
3713
3714 val = REG_RD(bp, BNX2_NVM_COMMAND);
3715 if (val & BNX2_NVM_COMMAND_DONE) {
b491edd5
AV		 3716 __be32 v = cpu_to_be32(REG_RD(bp, BNX2_NVM_READ));
3717 memcpy(ret_val, &v, 4);
b6016b76
MC		 3718 break;
3719 }
3720 }
3721 if (j >= NVRAM_TIMEOUT_COUNT)
3722 return -EBUSY;
3723
3724 return 0;
3725}
3726
3727
3728static int
3729bnx2_nvram_write_dword(struct bnx2 *bp, u32 offset, u8 *val, u32 cmd_flags)
3730{
b491edd5
AV		 3731 u32 cmd;
3732 __be32 val32;
b6016b76
MC		 3733 int j;
3734
3735 /* Build the command word. */
3736 cmd = BNX2_NVM_COMMAND_DOIT | BNX2_NVM_COMMAND_WR | cmd_flags;
3737
e30372c9
MC		 3738 /* Calculate an offset of a buffered flash, not needed for 5709. */
3739 if (bp->flash_info->flags & BNX2_NV_TRANSLATE) {
b6016b76
MC		 3740 offset = ((offset / bp->flash_info->page_size) <<
3741 bp->flash_info->page_bits) +
3742 (offset % bp->flash_info->page_size);
3743 }
3744
3745 /* Need to clear DONE bit separately. */
3746 REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
3747
3748 memcpy(&val32, val, 4);
b6016b76
MC		 3749
3750 /* Write the data. */
b491edd5 3751 REG_WR(bp, BNX2_NVM_WRITE, be32_to_cpu(val32));
b6016b76
MC		 3752
3753 /* Address of the NVRAM to write to. */
3754 REG_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);
3755
3756 /* Issue the write command. */
3757 REG_WR(bp, BNX2_NVM_COMMAND, cmd);
3758
3759 /* Wait for completion. */
3760 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
3761 udelay(5);
3762
3763 if (REG_RD(bp, BNX2_NVM_COMMAND) & BNX2_NVM_COMMAND_DONE)
3764 break;
3765 }
3766 if (j >= NVRAM_TIMEOUT_COUNT)
3767 return -EBUSY;
3768
3769 return 0;
3770}
3771
3772static int
3773bnx2_init_nvram(struct bnx2 *bp)
3774{
3775 u32 val;
e30372c9 3776 int j, entry_count, rc = 0;
b6016b76
MC		 3777 struct flash_spec *flash;
3778
e30372c9
MC		 3779 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
3780 bp->flash_info = &flash_5709;
3781 goto get_flash_size;
3782 }
3783
b6016b76
MC		 3784 /* Determine the selected interface. */
3785 val = REG_RD(bp, BNX2_NVM_CFG1);
3786
ff8ac609 3787 entry_count = ARRAY_SIZE(flash_table);
b6016b76 3788
b6016b76
MC		 3789 if (val & 0x40000000) {
3790
3791 /* Flash interface has been reconfigured */
3792 for (j = 0, flash = &flash_table[0]; j < entry_count;
37137709
MC		 3793 j++, flash++) {
3794 if ((val & FLASH_BACKUP_STRAP_MASK) ==
3795 (flash->config1 & FLASH_BACKUP_STRAP_MASK)) {
b6016b76
MC		 3796 bp->flash_info = flash;
3797 break;
3798 }
3799 }
3800 }
3801 else {
37137709 3802 u32 mask;
b6016b76
MC		 3803 /* Not yet been reconfigured */
3804
37137709
MC		 3805 if (val & (1 << 23))
3806 mask = FLASH_BACKUP_STRAP_MASK;
3807 else
3808 mask = FLASH_STRAP_MASK;
3809
b6016b76
MC		 3810 for (j = 0, flash = &flash_table[0]; j < entry_count;
3811 j++, flash++) {
3812
37137709 3813 if ((val & mask) == (flash->strapping & mask)) {
b6016b76
MC		 3814 bp->flash_info = flash;
3815
3816 /* Request access to the flash interface. */
3817 if ((rc = bnx2_acquire_nvram_lock(bp)) != 0)
3818 return rc;
3819
3820 /* Enable access to flash interface */
3821 bnx2_enable_nvram_access(bp);
3822
3823 /* Reconfigure the flash interface */
3824 REG_WR(bp, BNX2_NVM_CFG1, flash->config1);
3825 REG_WR(bp, BNX2_NVM_CFG2, flash->config2);
3826 REG_WR(bp, BNX2_NVM_CFG3, flash->config3);
3827 REG_WR(bp, BNX2_NVM_WRITE1, flash->write1);
3828
3829 /* Disable access to flash interface */
3830 bnx2_disable_nvram_access(bp);
3831 bnx2_release_nvram_lock(bp);
3832
3833 break;
3834 }
3835 }
3836 } /* if (val & 0x40000000) */
3837
3838 if (j == entry_count) {
3839 bp->flash_info = NULL;
2f23c523 3840 printk(KERN_ALERT PFX "Unknown flash/EEPROM type.\n");
1122db71 3841 return -ENODEV;
b6016b76
MC		 3842 }
3843
e30372c9 3844get_flash_size:
2726d6e1 3845 val = bnx2_shmem_rd(bp, BNX2_SHARED_HW_CFG_CONFIG2);
1122db71
MC		 3846 val &= BNX2_SHARED_HW_CFG2_NVM_SIZE_MASK;
3847 if (val)
3848 bp->flash_size = val;
3849 else
3850 bp->flash_size = bp->flash_info->total_size;
3851
b6016b76
MC		 3852 return rc;
3853}
3854
3855static int
3856bnx2_nvram_read(struct bnx2 *bp, u32 offset, u8 *ret_buf,
3857 int buf_size)
3858{
3859 int rc = 0;
3860 u32 cmd_flags, offset32, len32, extra;
3861
3862 if (buf_size == 0)
3863 return 0;
3864
3865 /* Request access to the flash interface. */
3866 if ((rc = bnx2_acquire_nvram_lock(bp)) != 0)
3867 return rc;
3868
3869 /* Enable access to flash interface */
3870 bnx2_enable_nvram_access(bp);
3871
3872 len32 = buf_size;
3873 offset32 = offset;
3874 extra = 0;
3875
3876 cmd_flags = 0;
3877
3878 if (offset32 & 3) {
3879 u8 buf[4];
3880 u32 pre_len;
3881
3882 offset32 &= ~3;
3883 pre_len = 4 - (offset & 3);
3884
3885 if (pre_len >= len32) {
3886 pre_len = len32;
3887 cmd_flags = BNX2_NVM_COMMAND_FIRST |
3888 BNX2_NVM_COMMAND_LAST;
3889 }
3890 else {
3891 cmd_flags = BNX2_NVM_COMMAND_FIRST;
3892 }
3893
3894 rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags);
3895
3896 if (rc)
3897 return rc;
3898
3899 memcpy(ret_buf, buf + (offset & 3), pre_len);
3900
3901 offset32 += 4;
3902 ret_buf += pre_len;
3903 len32 -= pre_len;
3904 }
3905 if (len32 & 3) {
3906 extra = 4 - (len32 & 3);
3907 len32 = (len32 + 4) & ~3;
3908 }
3909
3910 if (len32 == 4) {
3911 u8 buf[4];
3912
3913 if (cmd_flags)
3914 cmd_flags = BNX2_NVM_COMMAND_LAST;
3915 else
3916 cmd_flags = BNX2_NVM_COMMAND_FIRST |
3917 BNX2_NVM_COMMAND_LAST;
3918
3919 rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags);
3920
3921 memcpy(ret_buf, buf, 4 - extra);
3922 }
3923 else if (len32 > 0) {
3924 u8 buf[4];
3925
3926 /* Read the first word. */
3927 if (cmd_flags)
3928 cmd_flags = 0;
3929 else
3930 cmd_flags = BNX2_NVM_COMMAND_FIRST;
3931
3932 rc = bnx2_nvram_read_dword(bp, offset32, ret_buf, cmd_flags);
3933
3934 /* Advance to the next dword. */
3935 offset32 += 4;
3936 ret_buf += 4;
3937 len32 -= 4;
3938
3939 while (len32 > 4 && rc == 0) {
3940 rc = bnx2_nvram_read_dword(bp, offset32, ret_buf, 0);
3941
3942 /* Advance to the next dword. */
3943 offset32 += 4;
3944 ret_buf += 4;
3945 len32 -= 4;
3946 }
3947
3948 if (rc)
3949 return rc;
3950
3951 cmd_flags = BNX2_NVM_COMMAND_LAST;
3952 rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags);
3953
3954 memcpy(ret_buf, buf, 4 - extra);
3955 }
3956
3957 /* Disable access to flash interface */
3958 bnx2_disable_nvram_access(bp);
3959
3960 bnx2_release_nvram_lock(bp);
3961
3962 return rc;
3963}
3964
3965static int
3966bnx2_nvram_write(struct bnx2 *bp, u32 offset, u8 *data_buf,
3967 int buf_size)
3968{
3969 u32 written, offset32, len32;
e6be763f 3970 u8 *buf, start[4], end[4], *align_buf = NULL, *flash_buffer = NULL;
b6016b76
MC		 3971 int rc = 0;
3972 int align_start, align_end;
3973
3974 buf = data_buf;
3975 offset32 = offset;
3976 len32 = buf_size;
3977 align_start = align_end = 0;
3978
3979 if ((align_start = (offset32 & 3))) {
3980 offset32 &= ~3;
c873879c
MC		 3981 len32 += align_start;
3982 if (len32 < 4)
3983 len32 = 4;
b6016b76
MC		 3984 if ((rc = bnx2_nvram_read(bp, offset32, start, 4)))
3985 return rc;
3986 }
3987
3988 if (len32 & 3) {
c873879c
MC		 3989 align_end = 4 - (len32 & 3);
3990 len32 += align_end;
3991 if ((rc = bnx2_nvram_read(bp, offset32 + len32 - 4, end, 4)))
3992 return rc;
b6016b76
MC		 3993 }
3994
3995 if (align_start || align_end) {
e6be763f
MC		 3996 align_buf = kmalloc(len32, GFP_KERNEL);
3997 if (align_buf == NULL)
b6016b76
MC		 3998 return -ENOMEM;
3999 if (align_start) {
e6be763f 4000 memcpy(align_buf, start, 4);
b6016b76
MC		 4001 }
4002 if (align_end) {
e6be763f 4003 memcpy(align_buf + len32 - 4, end, 4);
b6016b76 4004 }
e6be763f
MC		 4005 memcpy(align_buf + align_start, data_buf, buf_size);
4006 buf = align_buf;
b6016b76
MC		 4007 }
4008
e30372c9 4009 if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) {
ae181bc4
MC		 4010 flash_buffer = kmalloc(264, GFP_KERNEL);
4011 if (flash_buffer == NULL) {
4012 rc = -ENOMEM;
4013 goto nvram_write_end;
4014 }
4015 }
4016
b6016b76
MC		 4017 written = 0;
4018 while ((written < len32) && (rc == 0)) {
4019 u32 page_start, page_end, data_start, data_end;
4020 u32 addr, cmd_flags;
4021 int i;
b6016b76
MC		 4022
4023 /* Find the page_start addr */
4024 page_start = offset32 + written;
4025 page_start -= (page_start % bp->flash_info->page_size);
4026 /* Find the page_end addr */
4027 page_end = page_start + bp->flash_info->page_size;
4028 /* Find the data_start addr */
4029 data_start = (written == 0) ? offset32 : page_start;
4030 /* Find the data_end addr */
6aa20a22 4031 data_end = (page_end > offset32 + len32) ?
b6016b76
MC		 4032 (offset32 + len32) : page_end;
4033
4034 /* Request access to the flash interface. */
4035 if ((rc = bnx2_acquire_nvram_lock(bp)) != 0)
4036 goto nvram_write_end;
4037
4038 /* Enable access to flash interface */
4039 bnx2_enable_nvram_access(bp);
4040
4041 cmd_flags = BNX2_NVM_COMMAND_FIRST;
e30372c9 4042 if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) {
b6016b76
MC		 4043 int j;
4044
4045 /* Read the whole page into the buffer
4046 * (non-buffer flash only) */
4047 for (j = 0; j < bp->flash_info->page_size; j += 4) {
4048 if (j == (bp->flash_info->page_size - 4)) {
4049 cmd_flags |= BNX2_NVM_COMMAND_LAST;
4050 }
4051 rc = bnx2_nvram_read_dword(bp,
6aa20a22
JG		 4052 page_start + j,
4053 &flash_buffer[j],
b6016b76
MC		 4054 cmd_flags);
4055
4056 if (rc)
4057 goto nvram_write_end;
4058
4059 cmd_flags = 0;
4060 }
4061 }
4062
4063 /* Enable writes to flash interface (unlock write-protect) */
4064 if ((rc = bnx2_enable_nvram_write(bp)) != 0)
4065 goto nvram_write_end;
4066
b6016b76
MC		 4067 /* Loop to write back the buffer data from page_start to
4068 * data_start */
4069 i = 0;
e30372c9 4070 if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) {
c873879c
MC		 4071 /* Erase the page */
4072 if ((rc = bnx2_nvram_erase_page(bp, page_start)) != 0)
4073 goto nvram_write_end;
4074
4075 /* Re-enable the write again for the actual write */
4076 bnx2_enable_nvram_write(bp);
4077
b6016b76
MC		 4078 for (addr = page_start; addr < data_start;
4079 addr += 4, i += 4) {
6aa20a22 4080
b6016b76
MC		 4081 rc = bnx2_nvram_write_dword(bp, addr,
4082 &flash_buffer[i], cmd_flags);
4083
4084 if (rc != 0)
4085 goto nvram_write_end;
4086
4087 cmd_flags = 0;
4088 }
4089 }
4090
4091 /* Loop to write the new data from data_start to data_end */
bae25761 4092 for (addr = data_start; addr < data_end; addr += 4, i += 4) {
b6016b76 4093 if ((addr == page_end - 4) ||
e30372c9 4094 ((bp->flash_info->flags & BNX2_NV_BUFFERED) &&
b6016b76
MC		 4095 (addr == data_end - 4))) {
4096
4097 cmd_flags |= BNX2_NVM_COMMAND_LAST;
4098 }
4099 rc = bnx2_nvram_write_dword(bp, addr, buf,
4100 cmd_flags);
4101
4102 if (rc != 0)
4103 goto nvram_write_end;
4104
4105 cmd_flags = 0;
4106 buf += 4;
4107 }
4108
4109 /* Loop to write back the buffer data from data_end
4110 * to page_end */
e30372c9 4111 if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) {
b6016b76
MC		 4112 for (addr = data_end; addr < page_end;
4113 addr += 4, i += 4) {
6aa20a22 4114
b6016b76
MC		 4115 if (addr == page_end-4) {
4116 cmd_flags = BNX2_NVM_COMMAND_LAST;
4117 }
4118 rc = bnx2_nvram_write_dword(bp, addr,
4119 &flash_buffer[i], cmd_flags);
4120
4121 if (rc != 0)
4122 goto nvram_write_end;
4123
4124 cmd_flags = 0;
4125 }
4126 }
4127
4128 /* Disable writes to flash interface (lock write-protect) */
4129 bnx2_disable_nvram_write(bp);
4130
4131 /* Disable access to flash interface */
4132 bnx2_disable_nvram_access(bp);
4133 bnx2_release_nvram_lock(bp);
4134
4135 /* Increment written */
4136 written += data_end - data_start;
4137 }
4138
4139nvram_write_end:
e6be763f
MC		 4140 kfree(flash_buffer);
4141 kfree(align_buf);
b6016b76
MC		 4142 return rc;
4143}
4144
0d8a6571
MC		 4145static void
4146bnx2_init_remote_phy(struct bnx2 *bp)
4147{
4148 u32 val;
4149
583c28e5
MC		 4150 bp->phy_flags &= ~BNX2_PHY_FLAG_REMOTE_PHY_CAP;
4151 if (!(bp->phy_flags & BNX2_PHY_FLAG_SERDES))
0d8a6571
MC		 4152 return;
4153
2726d6e1 4154 val = bnx2_shmem_rd(bp, BNX2_FW_CAP_MB);
0d8a6571
MC		 4155 if ((val & BNX2_FW_CAP_SIGNATURE_MASK) != BNX2_FW_CAP_SIGNATURE)
4156 return;
4157
4158 if (val & BNX2_FW_CAP_REMOTE_PHY_CAPABLE) {
583c28e5 4159 bp->phy_flags |= BNX2_PHY_FLAG_REMOTE_PHY_CAP;
0d8a6571 4160
2726d6e1 4161 val = bnx2_shmem_rd(bp, BNX2_LINK_STATUS);
0d8a6571
MC		 4162 if (val & BNX2_LINK_STATUS_SERDES_LINK)
4163 bp->phy_port = PORT_FIBRE;
4164 else
4165 bp->phy_port = PORT_TP;
489310a4
MC		 4166
4167 if (netif_running(bp->dev)) {
4168 u32 sig;
4169
489310a4
MC		 4170 sig = BNX2_DRV_ACK_CAP_SIGNATURE |
4171 BNX2_FW_CAP_REMOTE_PHY_CAPABLE;
2726d6e1 4172 bnx2_shmem_wr(bp, BNX2_DRV_ACK_CAP_MB, sig);
489310a4 4173 }
0d8a6571
MC		 4174 }
4175}
4176
b4b36042
MC		 4177static void
4178bnx2_setup_msix_tbl(struct bnx2 *bp)
4179{
4180 REG_WR(bp, BNX2_PCI_GRC_WINDOW_ADDR, BNX2_PCI_GRC_WINDOW_ADDR_SEP_WIN);
4181
4182 REG_WR(bp, BNX2_PCI_GRC_WINDOW2_ADDR, BNX2_MSIX_TABLE_ADDR);
4183 REG_WR(bp, BNX2_PCI_GRC_WINDOW3_ADDR, BNX2_MSIX_PBA_ADDR);
4184}
4185
b6016b76
MC		 4186static int
4187bnx2_reset_chip(struct bnx2 *bp, u32 reset_code)
4188{
4189 u32 val;
4190 int i, rc = 0;
489310a4 4191 u8 old_port;
b6016b76
MC		 4192
4193 /* Wait for the current PCI transaction to complete before
4194 * issuing a reset. */
4195 REG_WR(bp, BNX2_MISC_ENABLE_CLR_BITS,
4196 BNX2_MISC_ENABLE_CLR_BITS_TX_DMA_ENABLE |
4197 BNX2_MISC_ENABLE_CLR_BITS_DMA_ENGINE_ENABLE |
4198 BNX2_MISC_ENABLE_CLR_BITS_RX_DMA_ENABLE |
4199 BNX2_MISC_ENABLE_CLR_BITS_HOST_COALESCE_ENABLE);
4200 val = REG_RD(bp, BNX2_MISC_ENABLE_CLR_BITS);
4201 udelay(5);
4202
b090ae2b
MC		 4203 /* Wait for the firmware to tell us it is ok to issue a reset. */
4204 bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT0 | reset_code, 1);
4205
b6016b76
MC		 4206 /* Deposit a driver reset signature so the firmware knows that
4207 * this is a soft reset. */
2726d6e1
MC		 4208 bnx2_shmem_wr(bp, BNX2_DRV_RESET_SIGNATURE,
4209 BNX2_DRV_RESET_SIGNATURE_MAGIC);
b6016b76 4210
b6016b76
MC		 4211 /* Do a dummy read to force the chip to complete all current transaction
4212 * before we issue a reset. */
4213 val = REG_RD(bp, BNX2_MISC_ID);
4214
234754d5
MC		 4215 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
4216 REG_WR(bp, BNX2_MISC_COMMAND, BNX2_MISC_COMMAND_SW_RESET);
4217 REG_RD(bp, BNX2_MISC_COMMAND);
4218 udelay(5);
b6016b76 4219
234754d5
MC		 4220 val = BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
4221 BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP;
b6016b76 4222
234754d5 4223 pci_write_config_dword(bp->pdev, BNX2_PCICFG_MISC_CONFIG, val);
b6016b76 4224
234754d5
MC		 4225 } else {
4226 val = BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |
4227 BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
4228 BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP;
4229
4230 /* Chip reset. */
4231 REG_WR(bp, BNX2_PCICFG_MISC_CONFIG, val);
4232
594a9dfa
MC		 4233 /* Reading back any register after chip reset will hang the
4234 * bus on 5706 A0 and A1. The msleep below provides plenty
4235 * of margin for write posting.
4236 */
234754d5 4237 if ((CHIP_ID(bp) == CHIP_ID_5706_A0) ||
8e545881
AV		 4238 (CHIP_ID(bp) == CHIP_ID_5706_A1))
4239 msleep(20);
b6016b76 4240
234754d5
MC		 4241 /* Reset takes approximate 30 usec */
4242 for (i = 0; i < 10; i++) {
4243 val = REG_RD(bp, BNX2_PCICFG_MISC_CONFIG);
4244 if ((val & (BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |
4245 BNX2_PCICFG_MISC_CONFIG_CORE_RST_BSY)) == 0)
4246 break;
4247 udelay(10);
4248 }
4249
4250 if (val & (BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |
4251 BNX2_PCICFG_MISC_CONFIG_CORE_RST_BSY)) {
4252 printk(KERN_ERR PFX "Chip reset did not complete\n");
4253 return -EBUSY;
4254 }
b6016b76
MC		 4255 }
4256
4257 /* Make sure byte swapping is properly configured. */
4258 val = REG_RD(bp, BNX2_PCI_SWAP_DIAG0);
4259 if (val != 0x01020304) {
4260 printk(KERN_ERR PFX "Chip not in correct endian mode\n");
4261 return -ENODEV;
4262 }
4263
b6016b76 4264 /* Wait for the firmware to finish its initialization. */
b090ae2b
MC		 4265 rc = bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT1 | reset_code, 0);
4266 if (rc)
4267 return rc;
b6016b76 4268
0d8a6571 4269 spin_lock_bh(&bp->phy_lock);
489310a4 4270 old_port = bp->phy_port;
0d8a6571 4271 bnx2_init_remote_phy(bp);
583c28e5
MC		 4272 if ((bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) &&
4273 old_port != bp->phy_port)
0d8a6571
MC		 4274 bnx2_set_default_remote_link(bp);
4275 spin_unlock_bh(&bp->phy_lock);
4276
b6016b76
MC		 4277 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
4278 /* Adjust the voltage regular to two steps lower. The default
4279 * of this register is 0x0000000e. */
4280 REG_WR(bp, BNX2_MISC_VREG_CONTROL, 0x000000fa);
4281
4282 /* Remove bad rbuf memory from the free pool. */
4283 rc = bnx2_alloc_bad_rbuf(bp);
4284 }
4285
f86e82fb 4286 if (bp->flags & BNX2_FLAG_USING_MSIX)
b4b36042
MC		 4287 bnx2_setup_msix_tbl(bp);
4288
b6016b76
MC		 4289 return rc;
4290}
4291
4292static int
4293bnx2_init_chip(struct bnx2 *bp)
4294{
4295 u32 val;
b4b36042 4296 int rc, i;
b6016b76
MC		 4297
4298 /* Make sure the interrupt is not active. */
4299 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
4300
4301 val = BNX2_DMA_CONFIG_DATA_BYTE_SWAP |
4302 BNX2_DMA_CONFIG_DATA_WORD_SWAP |
4303#ifdef __BIG_ENDIAN
6aa20a22 4304 BNX2_DMA_CONFIG_CNTL_BYTE_SWAP |
b6016b76 4305#endif
6aa20a22 4306 BNX2_DMA_CONFIG_CNTL_WORD_SWAP |
b6016b76
MC		 4307 DMA_READ_CHANS << 12 |
4308 DMA_WRITE_CHANS << 16;
4309
4310 val |= (0x2 << 20) | (1 << 11);
4311
f86e82fb 4312 if ((bp->flags & BNX2_FLAG_PCIX) && (bp->bus_speed_mhz == 133))
b6016b76
MC		 4313 val |= (1 << 23);
4314
4315 if ((CHIP_NUM(bp) == CHIP_NUM_5706) &&
f86e82fb 4316 (CHIP_ID(bp) != CHIP_ID_5706_A0) && !(bp->flags & BNX2_FLAG_PCIX))
b6016b76
MC		 4317 val |= BNX2_DMA_CONFIG_CNTL_PING_PONG_DMA;
4318
4319 REG_WR(bp, BNX2_DMA_CONFIG, val);
4320
4321 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
4322 val = REG_RD(bp, BNX2_TDMA_CONFIG);
4323 val |= BNX2_TDMA_CONFIG_ONE_DMA;
4324 REG_WR(bp, BNX2_TDMA_CONFIG, val);
4325 }
4326
f86e82fb 4327 if (bp->flags & BNX2_FLAG_PCIX) {
b6016b76
MC		 4328 u16 val16;
4329
4330 pci_read_config_word(bp->pdev, bp->pcix_cap + PCI_X_CMD,
4331 &val16);
4332 pci_write_config_word(bp->pdev, bp->pcix_cap + PCI_X_CMD,
4333 val16 & ~PCI_X_CMD_ERO);
4334 }
4335
4336 REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS,
4337 BNX2_MISC_ENABLE_SET_BITS_HOST_COALESCE_ENABLE |
4338 BNX2_MISC_ENABLE_STATUS_BITS_RX_V2P_ENABLE |
4339 BNX2_MISC_ENABLE_STATUS_BITS_CONTEXT_ENABLE);
4340
4341 /* Initialize context mapping and zero out the quick contexts. The
4342 * context block must have already been enabled. */
641bdcd5
MC		 4343 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
4344 rc = bnx2_init_5709_context(bp);
4345 if (rc)
4346 return rc;
4347 } else
59b47d8a 4348 bnx2_init_context(bp);
b6016b76 4349
fba9fe91
MC		 4350 if ((rc = bnx2_init_cpus(bp)) != 0)
4351 return rc;
4352
b6016b76
MC		 4353 bnx2_init_nvram(bp);
4354
4355 bnx2_set_mac_addr(bp);
4356
4357 val = REG_RD(bp, BNX2_MQ_CONFIG);
4358 val &= ~BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE;
4359 val |= BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE_256;
68c9f75a
MC		 4360 if (CHIP_ID(bp) == CHIP_ID_5709_A0 || CHIP_ID(bp) == CHIP_ID_5709_A1)
4361 val |= BNX2_MQ_CONFIG_HALT_DIS;
4362
b6016b76
MC		 4363 REG_WR(bp, BNX2_MQ_CONFIG, val);
4364
4365 val = 0x10000 + (MAX_CID_CNT * MB_KERNEL_CTX_SIZE);
4366 REG_WR(bp, BNX2_MQ_KNL_BYP_WIND_START, val);
4367 REG_WR(bp, BNX2_MQ_KNL_WIND_END, val);
4368
4369 val = (BCM_PAGE_BITS - 8) << 24;
4370 REG_WR(bp, BNX2_RV2P_CONFIG, val);
4371
4372 /* Configure page size. */
4373 val = REG_RD(bp, BNX2_TBDR_CONFIG);
4374 val &= ~BNX2_TBDR_CONFIG_PAGE_SIZE;
4375 val |= (BCM_PAGE_BITS - 8) << 24 | 0x40;
4376 REG_WR(bp, BNX2_TBDR_CONFIG, val);
4377
4378 val = bp->mac_addr[0] +
4379 (bp->mac_addr[1] << 8) +
4380 (bp->mac_addr[2] << 16) +
4381 bp->mac_addr[3] +
4382 (bp->mac_addr[4] << 8) +
4383 (bp->mac_addr[5] << 16);
4384 REG_WR(bp, BNX2_EMAC_BACKOFF_SEED, val);
4385
4386 /* Program the MTU. Also include 4 bytes for CRC32. */
4387 val = bp->dev->mtu + ETH_HLEN + 4;
4388 if (val > (MAX_ETHERNET_PACKET_SIZE + 4))
4389 val |= BNX2_EMAC_RX_MTU_SIZE_JUMBO_ENA;
4390 REG_WR(bp, BNX2_EMAC_RX_MTU_SIZE, val);
4391
b4b36042
MC		 4392 for (i = 0; i < BNX2_MAX_MSIX_VEC; i++)
4393 bp->bnx2_napi[i].last_status_idx = 0;
4394
b6016b76
MC		 4395 bp->rx_mode = BNX2_EMAC_RX_MODE_SORT_MODE;
4396
4397 /* Set up how to generate a link change interrupt. */
4398 REG_WR(bp, BNX2_EMAC_ATTENTION_ENA, BNX2_EMAC_ATTENTION_ENA_LINK);
4399
4400 REG_WR(bp, BNX2_HC_STATUS_ADDR_L,
4401 (u64) bp->status_blk_mapping & 0xffffffff);
4402 REG_WR(bp, BNX2_HC_STATUS_ADDR_H, (u64) bp->status_blk_mapping >> 32);
4403
4404 REG_WR(bp, BNX2_HC_STATISTICS_ADDR_L,
4405 (u64) bp->stats_blk_mapping & 0xffffffff);
4406 REG_WR(bp, BNX2_HC_STATISTICS_ADDR_H,
4407 (u64) bp->stats_blk_mapping >> 32);
4408
6aa20a22 4409 REG_WR(bp, BNX2_HC_TX_QUICK_CONS_TRIP,
b6016b76
MC		 4410 (bp->tx_quick_cons_trip_int << 16) | bp->tx_quick_cons_trip);
4411
4412 REG_WR(bp, BNX2_HC_RX_QUICK_CONS_TRIP,
4413 (bp->rx_quick_cons_trip_int << 16) | bp->rx_quick_cons_trip);
4414
4415 REG_WR(bp, BNX2_HC_COMP_PROD_TRIP,
4416 (bp->comp_prod_trip_int << 16) | bp->comp_prod_trip);
4417
4418 REG_WR(bp, BNX2_HC_TX_TICKS, (bp->tx_ticks_int << 16) | bp->tx_ticks);
4419
4420 REG_WR(bp, BNX2_HC_RX_TICKS, (bp->rx_ticks_int << 16) | bp->rx_ticks);
4421
4422 REG_WR(bp, BNX2_HC_COM_TICKS,
4423 (bp->com_ticks_int << 16) | bp->com_ticks);
4424
4425 REG_WR(bp, BNX2_HC_CMD_TICKS,
4426 (bp->cmd_ticks_int << 16) | bp->cmd_ticks);
4427
02537b06
MC		 4428 if (CHIP_NUM(bp) == CHIP_NUM_5708)
4429 REG_WR(bp, BNX2_HC_STATS_TICKS, 0);
4430 else
7ea6920e 4431 REG_WR(bp, BNX2_HC_STATS_TICKS, bp->stats_ticks);
b6016b76
MC		 4432 REG_WR(bp, BNX2_HC_STAT_COLLECT_TICKS, 0xbb8); /* 3ms */
4433
4434 if (CHIP_ID(bp) == CHIP_ID_5706_A1)
8e6a72c4 4435 val = BNX2_HC_CONFIG_COLLECT_STATS;
b6016b76 4436 else {
8e6a72c4
MC		 4437 val = BNX2_HC_CONFIG_RX_TMR_MODE | BNX2_HC_CONFIG_TX_TMR_MODE |
4438 BNX2_HC_CONFIG_COLLECT_STATS;
b6016b76
MC		 4439 }
4440
f86e82fb 4441 if (bp->flags & BNX2_FLAG_USING_MSIX) {
6f743ca0
MC		 4442 u32 base = ((BNX2_TX_VEC - 1) * BNX2_HC_SB_CONFIG_SIZE) +
4443 BNX2_HC_SB_CONFIG_1;
4444
c76c0475
MC		 4445 REG_WR(bp, BNX2_HC_MSIX_BIT_VECTOR,
4446 BNX2_HC_MSIX_BIT_VECTOR_VAL);
4447
6f743ca0 4448 REG_WR(bp, base,
c76c0475
MC		 4449 BNX2_HC_SB_CONFIG_1_TX_TMR_MODE |
4450 BNX2_HC_SB_CONFIG_1_ONE_SHOT);
4451
6f743ca0 4452 REG_WR(bp, base + BNX2_HC_TX_QUICK_CONS_TRIP_OFF,
c76c0475
MC		 4453 (bp->tx_quick_cons_trip_int << 16) |
4454 bp->tx_quick_cons_trip);
4455
6f743ca0 4456 REG_WR(bp, base + BNX2_HC_TX_TICKS_OFF,
c76c0475
MC		 4457 (bp->tx_ticks_int << 16) | bp->tx_ticks);
4458
4459 val |= BNX2_HC_CONFIG_SB_ADDR_INC_128B;
4460 }
4461
f86e82fb 4462 if (bp->flags & BNX2_FLAG_ONE_SHOT_MSI)
8e6a72c4
MC		 4463 val |= BNX2_HC_CONFIG_ONE_SHOT;
4464
4465 REG_WR(bp, BNX2_HC_CONFIG, val);
4466
b6016b76
MC		 4467 /* Clear internal stats counters. */
4468 REG_WR(bp, BNX2_HC_COMMAND, BNX2_HC_COMMAND_CLR_STAT_NOW);
4469
da3e4fbe 4470 REG_WR(bp, BNX2_HC_ATTN_BITS_ENABLE, STATUS_ATTN_EVENTS);
b6016b76
MC		 4471
4472 /* Initialize the receive filter. */
4473 bnx2_set_rx_mode(bp->dev);
4474
0aa38df7
MC		 4475 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
4476 val = REG_RD(bp, BNX2_MISC_NEW_CORE_CTL);
4477 val |= BNX2_MISC_NEW_CORE_CTL_DMA_ENABLE;
4478 REG_WR(bp, BNX2_MISC_NEW_CORE_CTL, val);
4479 }
b090ae2b
MC		 4480 rc = bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT2 | BNX2_DRV_MSG_CODE_RESET,
4481 0);
b6016b76 4482
df149d70 4483 REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS, BNX2_MISC_ENABLE_DEFAULT);
b6016b76
MC		 4484 REG_RD(bp, BNX2_MISC_ENABLE_SET_BITS);
4485
4486 udelay(20);
4487
bf5295bb
MC		 4488 bp->hc_cmd = REG_RD(bp, BNX2_HC_COMMAND);
4489
b090ae2b 4490 return rc;
b6016b76
MC		 4491}
4492
c76c0475
MC		 4493static void
4494bnx2_clear_ring_states(struct bnx2 *bp)
4495{
4496 struct bnx2_napi *bnapi;
4497 int i;
4498
4499 for (i = 0; i < BNX2_MAX_MSIX_VEC; i++) {
4500 bnapi = &bp->bnx2_napi[i];
4501
4502 bnapi->tx_cons = 0;
4503 bnapi->hw_tx_cons = 0;
4504 bnapi->rx_prod_bseq = 0;
4505 bnapi->rx_prod = 0;
4506 bnapi->rx_cons = 0;
4507 bnapi->rx_pg_prod = 0;
4508 bnapi->rx_pg_cons = 0;
4509 }
4510}
4511
59b47d8a
MC		 4512static void
4513bnx2_init_tx_context(struct bnx2 *bp, u32 cid)
4514{
4515 u32 val, offset0, offset1, offset2, offset3;
62a8313c 4516 u32 cid_addr = GET_CID_ADDR(cid);
59b47d8a
MC		 4517
4518 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
4519 offset0 = BNX2_L2CTX_TYPE_XI;
4520 offset1 = BNX2_L2CTX_CMD_TYPE_XI;
4521 offset2 = BNX2_L2CTX_TBDR_BHADDR_HI_XI;
4522 offset3 = BNX2_L2CTX_TBDR_BHADDR_LO_XI;
4523 } else {
4524 offset0 = BNX2_L2CTX_TYPE;
4525 offset1 = BNX2_L2CTX_CMD_TYPE;
4526 offset2 = BNX2_L2CTX_TBDR_BHADDR_HI;
4527 offset3 = BNX2_L2CTX_TBDR_BHADDR_LO;
4528 }
4529 val = BNX2_L2CTX_TYPE_TYPE_L2 | BNX2_L2CTX_TYPE_SIZE_L2;
62a8313c 4530 bnx2_ctx_wr(bp, cid_addr, offset0, val);
59b47d8a
MC		 4531
4532 val = BNX2_L2CTX_CMD_TYPE_TYPE_L2 | (8 << 16);
62a8313c 4533 bnx2_ctx_wr(bp, cid_addr, offset1, val);
59b47d8a
MC		 4534
4535 val = (u64) bp->tx_desc_mapping >> 32;
62a8313c 4536 bnx2_ctx_wr(bp, cid_addr, offset2, val);
59b47d8a
MC		 4537
4538 val = (u64) bp->tx_desc_mapping & 0xffffffff;
62a8313c 4539 bnx2_ctx_wr(bp, cid_addr, offset3, val);
59b47d8a 4540}
b6016b76
MC		 4541
4542static void
4543bnx2_init_tx_ring(struct bnx2 *bp)
4544{
4545 struct tx_bd *txbd;
c76c0475
MC		 4546 u32 cid = TX_CID;
4547 struct bnx2_napi *bnapi;
4548
4549 bp->tx_vec = 0;
f86e82fb 4550 if (bp->flags & BNX2_FLAG_USING_MSIX) {
c76c0475
MC		 4551 cid = TX_TSS_CID;
4552 bp->tx_vec = BNX2_TX_VEC;
4553 REG_WR(bp, BNX2_TSCH_TSS_CFG, BNX2_TX_INT_NUM |
4554 (TX_TSS_CID << 7));
4555 }
4556 bnapi = &bp->bnx2_napi[bp->tx_vec];
b6016b76 4557
2f8af120
MC		 4558 bp->tx_wake_thresh = bp->tx_ring_size / 2;
4559
b6016b76 4560 txbd = &bp->tx_desc_ring[MAX_TX_DESC_CNT];
6aa20a22 4561
b6016b76
MC		 4562 txbd->tx_bd_haddr_hi = (u64) bp->tx_desc_mapping >> 32;
4563 txbd->tx_bd_haddr_lo = (u64) bp->tx_desc_mapping & 0xffffffff;
4564
4565 bp->tx_prod = 0;
b6016b76 4566 bp->tx_prod_bseq = 0;
6aa20a22 4567
59b47d8a
MC		 4568 bp->tx_bidx_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_TX_HOST_BIDX;
4569 bp->tx_bseq_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_TX_HOST_BSEQ;
b6016b76 4570
59b47d8a 4571 bnx2_init_tx_context(bp, cid);
b6016b76
MC		 4572}
4573
4574static void
5d5d0015
MC		 4575bnx2_init_rxbd_rings(struct rx_bd *rx_ring[], dma_addr_t dma[], u32 buf_size,
4576 int num_rings)
b6016b76 4577{
b6016b76 4578 int i;
5d5d0015 4579 struct rx_bd *rxbd;
6aa20a22 4580
5d5d0015 4581 for (i = 0; i < num_rings; i++) {
13daffa2 4582 int j;
b6016b76 4583
5d5d0015 4584 rxbd = &rx_ring[i][0];
13daffa2 4585 for (j = 0; j < MAX_RX_DESC_CNT; j++, rxbd++) {
5d5d0015 4586 rxbd->rx_bd_len = buf_size;
13daffa2
MC		 4587 rxbd->rx_bd_flags = RX_BD_FLAGS_START | RX_BD_FLAGS_END;
4588 }
5d5d0015 4589 if (i == (num_rings - 1))
13daffa2
MC		 4590 j = 0;
4591 else
4592 j = i + 1;
5d5d0015
MC		 4593 rxbd->rx_bd_haddr_hi = (u64) dma[j] >> 32;
4594 rxbd->rx_bd_haddr_lo = (u64) dma[j] & 0xffffffff;
13daffa2 4595 }
5d5d0015
MC		 4596}
4597
4598static void
4599bnx2_init_rx_ring(struct bnx2 *bp)
4600{
4601 int i;
4602 u16 prod, ring_prod;
4603 u32 val, rx_cid_addr = GET_CID_ADDR(RX_CID);
b4b36042 4604 struct bnx2_napi *bnapi = &bp->bnx2_napi[0];
5d5d0015 4605
5d5d0015
MC		 4606 bnx2_init_rxbd_rings(bp->rx_desc_ring, bp->rx_desc_mapping,
4607 bp->rx_buf_use_size, bp->rx_max_ring);
4608
83e3fc89
MC		 4609 bnx2_init_rx_context0(bp);
4610
4611 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
4612 val = REG_RD(bp, BNX2_MQ_MAP_L2_5);
4613 REG_WR(bp, BNX2_MQ_MAP_L2_5, val | BNX2_MQ_MAP_L2_5_ARM);
4614 }
4615
62a8313c 4616 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_PG_BUF_SIZE, 0);
47bf4246
MC		 4617 if (bp->rx_pg_ring_size) {
4618 bnx2_init_rxbd_rings(bp->rx_pg_desc_ring,
4619 bp->rx_pg_desc_mapping,
4620 PAGE_SIZE, bp->rx_max_pg_ring);
4621 val = (bp->rx_buf_use_size << 16) | PAGE_SIZE;
62a8313c
MC		 4622 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_PG_BUF_SIZE, val);
4623 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_RBDC_KEY,
47bf4246
MC		 4624 BNX2_L2CTX_RBDC_JUMBO_KEY);
4625
4626 val = (u64) bp->rx_pg_desc_mapping[0] >> 32;
62a8313c 4627 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_PG_BDHADDR_HI, val);
47bf4246
MC		 4628
4629 val = (u64) bp->rx_pg_desc_mapping[0] & 0xffffffff;
62a8313c 4630 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_PG_BDHADDR_LO, val);
47bf4246
MC		 4631
4632 if (CHIP_NUM(bp) == CHIP_NUM_5709)
4633 REG_WR(bp, BNX2_MQ_MAP_L2_3, BNX2_MQ_MAP_L2_3_DEFAULT);
4634 }
b6016b76 4635
13daffa2 4636 val = (u64) bp->rx_desc_mapping[0] >> 32;
62a8313c 4637 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_BDHADDR_HI, val);
b6016b76 4638
13daffa2 4639 val = (u64) bp->rx_desc_mapping[0] & 0xffffffff;
62a8313c 4640 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_BDHADDR_LO, val);
b6016b76 4641
a1f60190 4642 ring_prod = prod = bnapi->rx_pg_prod;
47bf4246
MC		 4643 for (i = 0; i < bp->rx_pg_ring_size; i++) {
4644 if (bnx2_alloc_rx_page(bp, ring_prod) < 0)
4645 break;
4646 prod = NEXT_RX_BD(prod);
4647 ring_prod = RX_PG_RING_IDX(prod);
4648 }
a1f60190 4649 bnapi->rx_pg_prod = prod;
47bf4246 4650
a1f60190 4651 ring_prod = prod = bnapi->rx_prod;
236b6394 4652 for (i = 0; i < bp->rx_ring_size; i++) {
a1f60190 4653 if (bnx2_alloc_rx_skb(bp, bnapi, ring_prod) < 0) {
b6016b76
MC		 4654 break;
4655 }
4656 prod = NEXT_RX_BD(prod);
4657 ring_prod = RX_RING_IDX(prod);
4658 }
a1f60190 4659 bnapi->rx_prod = prod;
b6016b76 4660
a1f60190
MC		 4661 REG_WR16(bp, MB_RX_CID_ADDR + BNX2_L2CTX_HOST_PG_BDIDX,
4662 bnapi->rx_pg_prod);
b6016b76
MC		 4663 REG_WR16(bp, MB_RX_CID_ADDR + BNX2_L2CTX_HOST_BDIDX, prod);
4664
a1f60190 4665 REG_WR(bp, MB_RX_CID_ADDR + BNX2_L2CTX_HOST_BSEQ, bnapi->rx_prod_bseq);
b6016b76
MC		 4666}
4667
5d5d0015 4668static u32 bnx2_find_max_ring(u32 ring_size, u32 max_size)
13daffa2 4669{
5d5d0015 4670 u32 max, num_rings = 1;
13daffa2 4671
5d5d0015
MC		 4672 while (ring_size > MAX_RX_DESC_CNT) {
4673 ring_size -= MAX_RX_DESC_CNT;
13daffa2
MC		 4674 num_rings++;
4675 }
4676 /* round to next power of 2 */
5d5d0015 4677 max = max_size;
13daffa2
MC		 4678 while ((max & num_rings) == 0)
4679 max >>= 1;
4680
4681 if (num_rings != max)
4682 max <<= 1;
4683
5d5d0015
MC		 4684 return max;
4685}
4686
4687static void
4688bnx2_set_rx_ring_size(struct bnx2 *bp, u32 size)
4689{
84eaa187 4690 u32 rx_size, rx_space, jumbo_size;
5d5d0015
MC		 4691
4692 /* 8 for CRC and VLAN */
d89cb6af 4693 rx_size = bp->dev->mtu + ETH_HLEN + BNX2_RX_OFFSET + 8;
5d5d0015 4694
84eaa187
MC		 4695 rx_space = SKB_DATA_ALIGN(rx_size + BNX2_RX_ALIGN) + NET_SKB_PAD +
4696 sizeof(struct skb_shared_info);
4697
601d3d18 4698 bp->rx_copy_thresh = BNX2_RX_COPY_THRESH;
47bf4246
MC		 4699 bp->rx_pg_ring_size = 0;
4700 bp->rx_max_pg_ring = 0;
4701 bp->rx_max_pg_ring_idx = 0;
f86e82fb 4702 if ((rx_space > PAGE_SIZE) && !(bp->flags & BNX2_FLAG_JUMBO_BROKEN)) {
84eaa187
MC		 4703 int pages = PAGE_ALIGN(bp->dev->mtu - 40) >> PAGE_SHIFT;
4704
4705 jumbo_size = size * pages;
4706 if (jumbo_size > MAX_TOTAL_RX_PG_DESC_CNT)
4707 jumbo_size = MAX_TOTAL_RX_PG_DESC_CNT;
4708
4709 bp->rx_pg_ring_size = jumbo_size;
4710 bp->rx_max_pg_ring = bnx2_find_max_ring(jumbo_size,
4711 MAX_RX_PG_RINGS);
4712 bp->rx_max_pg_ring_idx = (bp->rx_max_pg_ring * RX_DESC_CNT) - 1;
601d3d18 4713 rx_size = BNX2_RX_COPY_THRESH + BNX2_RX_OFFSET;
84eaa187
MC		 4714 bp->rx_copy_thresh = 0;
4715 }
5d5d0015
MC		 4716
4717 bp->rx_buf_use_size = rx_size;
4718 /* hw alignment */
4719 bp->rx_buf_size = bp->rx_buf_use_size + BNX2_RX_ALIGN;
d89cb6af 4720 bp->rx_jumbo_thresh = rx_size - BNX2_RX_OFFSET;
5d5d0015
MC		 4721 bp->rx_ring_size = size;
4722 bp->rx_max_ring = bnx2_find_max_ring(size, MAX_RX_RINGS);
13daffa2
MC		 4723 bp->rx_max_ring_idx = (bp->rx_max_ring * RX_DESC_CNT) - 1;
4724}
4725
b6016b76
MC		 4726static void
4727bnx2_free_tx_skbs(struct bnx2 *bp)
4728{
4729 int i;
4730
4731 if (bp->tx_buf_ring == NULL)
4732 return;
4733
4734 for (i = 0; i < TX_DESC_CNT; ) {
4735 struct sw_bd *tx_buf = &bp->tx_buf_ring[i];
4736 struct sk_buff *skb = tx_buf->skb;
4737 int j, last;
4738
4739 if (skb == NULL) {
4740 i++;
4741 continue;
4742 }
4743
4744 pci_unmap_single(bp->pdev, pci_unmap_addr(tx_buf, mapping),
4745 skb_headlen(skb), PCI_DMA_TODEVICE);
4746
4747 tx_buf->skb = NULL;
4748
4749 last = skb_shinfo(skb)->nr_frags;
4750 for (j = 0; j < last; j++) {
4751 tx_buf = &bp->tx_buf_ring[i + j + 1];
4752 pci_unmap_page(bp->pdev,
4753 pci_unmap_addr(tx_buf, mapping),
4754 skb_shinfo(skb)->frags[j].size,
4755 PCI_DMA_TODEVICE);
4756 }
745720e5 4757 dev_kfree_skb(skb);
b6016b76
MC		 4758 i += j + 1;
4759 }
4760
4761}
4762
4763static void
4764bnx2_free_rx_skbs(struct bnx2 *bp)
4765{
4766 int i;
4767
4768 if (bp->rx_buf_ring == NULL)
4769 return;
4770
13daffa2 4771 for (i = 0; i < bp->rx_max_ring_idx; i++) {
b6016b76
MC		 4772 struct sw_bd *rx_buf = &bp->rx_buf_ring[i];
4773 struct sk_buff *skb = rx_buf->skb;
4774
05d0f1cf 4775 if (skb == NULL)
b6016b76
MC		 4776 continue;
4777
4778 pci_unmap_single(bp->pdev, pci_unmap_addr(rx_buf, mapping),
4779 bp->rx_buf_use_size, PCI_DMA_FROMDEVICE);
4780
4781 rx_buf->skb = NULL;
4782
745720e5 4783 dev_kfree_skb(skb);
b6016b76 4784 }
47bf4246
MC		 4785 for (i = 0; i < bp->rx_max_pg_ring_idx; i++)
4786 bnx2_free_rx_page(bp, i);
b6016b76
MC		 4787}
4788
4789static void
4790bnx2_free_skbs(struct bnx2 *bp)
4791{
4792 bnx2_free_tx_skbs(bp);
4793 bnx2_free_rx_skbs(bp);
4794}
4795
4796static int
4797bnx2_reset_nic(struct bnx2 *bp, u32 reset_code)
4798{
4799 int rc;
4800
4801 rc = bnx2_reset_chip(bp, reset_code);
4802 bnx2_free_skbs(bp);
4803 if (rc)
4804 return rc;
4805
fba9fe91
MC		 4806 if ((rc = bnx2_init_chip(bp)) != 0)
4807 return rc;
4808
c76c0475 4809 bnx2_clear_ring_states(bp);
b6016b76
MC		 4810 bnx2_init_tx_ring(bp);
4811 bnx2_init_rx_ring(bp);
4812 return 0;
4813}
4814
4815static int
9a120bc5 4816bnx2_init_nic(struct bnx2 *bp, int reset_phy)
b6016b76
MC		 4817{
4818 int rc;
4819
4820 if ((rc = bnx2_reset_nic(bp, BNX2_DRV_MSG_CODE_RESET)) != 0)
4821 return rc;
4822
80be4434 4823 spin_lock_bh(&bp->phy_lock);
9a120bc5 4824 bnx2_init_phy(bp, reset_phy);
b6016b76 4825 bnx2_set_link(bp);
543a827d
MC		 4826 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
4827 bnx2_remote_phy_event(bp);
0d8a6571 4828 spin_unlock_bh(&bp->phy_lock);
b6016b76
MC		 4829 return 0;
4830}
4831
4832static int
4833bnx2_test_registers(struct bnx2 *bp)
4834{
4835 int ret;
5bae30c9 4836 int i, is_5709;
f71e1309 4837 static const struct {
b6016b76
MC		 4838 u16 offset;
4839 u16 flags;
5bae30c9 4840#define BNX2_FL_NOT_5709 1
b6016b76
MC		 4841 u32 rw_mask;
4842 u32 ro_mask;
4843 } reg_tbl[] = {
4844 { 0x006c, 0, 0x00000000, 0x0000003f },
4845 { 0x0090, 0, 0xffffffff, 0x00000000 },
4846 { 0x0094, 0, 0x00000000, 0x00000000 },
4847
5bae30c9
MC		 4848 { 0x0404, BNX2_FL_NOT_5709, 0x00003f00, 0x00000000 },
4849 { 0x0418, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
4850 { 0x041c, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
4851 { 0x0420, BNX2_FL_NOT_5709, 0x00000000, 0x80ffffff },
4852 { 0x0424, BNX2_FL_NOT_5709, 0x00000000, 0x00000000 },
4853 { 0x0428, BNX2_FL_NOT_5709, 0x00000000, 0x00000001 },
4854 { 0x0450, BNX2_FL_NOT_5709, 0x00000000, 0x0000ffff },
4855 { 0x0454, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
4856 { 0x0458, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
4857
4858 { 0x0808, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
4859 { 0x0854, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
4860 { 0x0868, BNX2_FL_NOT_5709, 0x00000000, 0x77777777 },
4861 { 0x086c, BNX2_FL_NOT_5709, 0x00000000, 0x77777777 },
4862 { 0x0870, BNX2_FL_NOT_5709, 0x00000000, 0x77777777 },
4863 { 0x0874, BNX2_FL_NOT_5709, 0x00000000, 0x77777777 },
4864
4865 { 0x0c00, BNX2_FL_NOT_5709, 0x00000000, 0x00000001 },
4866 { 0x0c04, BNX2_FL_NOT_5709, 0x00000000, 0x03ff0001 },
4867 { 0x0c08, BNX2_FL_NOT_5709, 0x0f0ff073, 0x00000000 },
b6016b76
MC		 4868
4869 { 0x1000, 0, 0x00000000, 0x00000001 },
15b169cc 4870 { 0x1004, BNX2_FL_NOT_5709, 0x00000000, 0x000f0001 },
b6016b76
MC		 4871
4872 { 0x1408, 0, 0x01c00800, 0x00000000 },
4873 { 0x149c, 0, 0x8000ffff, 0x00000000 },
4874 { 0x14a8, 0, 0x00000000, 0x000001ff },
5b0c76ad 4875 { 0x14ac, 0, 0x0fffffff, 0x10000000 },
b6016b76
MC		 4876 { 0x14b0, 0, 0x00000002, 0x00000001 },
4877 { 0x14b8, 0, 0x00000000, 0x00000000 },
4878 { 0x14c0, 0, 0x00000000, 0x00000009 },
4879 { 0x14c4, 0, 0x00003fff, 0x00000000 },
4880 { 0x14cc, 0, 0x00000000, 0x00000001 },
4881 { 0x14d0, 0, 0xffffffff, 0x00000000 },
b6016b76
MC		 4882
4883 { 0x1800, 0, 0x00000000, 0x00000001 },
4884 { 0x1804, 0, 0x00000000, 0x00000003 },
b6016b76
MC		 4885
4886 { 0x2800, 0, 0x00000000, 0x00000001 },
4887 { 0x2804, 0, 0x00000000, 0x00003f01 },
4888 { 0x2808, 0, 0x0f3f3f03, 0x00000000 },
4889 { 0x2810, 0, 0xffff0000, 0x00000000 },
4890 { 0x2814, 0, 0xffff0000, 0x00000000 },
4891 { 0x2818, 0, 0xffff0000, 0x00000000 },
4892 { 0x281c, 0, 0xffff0000, 0x00000000 },
4893 { 0x2834, 0, 0xffffffff, 0x00000000 },
4894 { 0x2840, 0, 0x00000000, 0xffffffff },
4895 { 0x2844, 0, 0x00000000, 0xffffffff },
4896 { 0x2848, 0, 0xffffffff, 0x00000000 },
4897 { 0x284c, 0, 0xf800f800, 0x07ff07ff },
4898
4899 { 0x2c00, 0, 0x00000000, 0x00000011 },
4900 { 0x2c04, 0, 0x00000000, 0x00030007 },
4901
b6016b76
MC		 4902 { 0x3c00, 0, 0x00000000, 0x00000001 },
4903 { 0x3c04, 0, 0x00000000, 0x00070000 },
4904 { 0x3c08, 0, 0x00007f71, 0x07f00000 },
4905 { 0x3c0c, 0, 0x1f3ffffc, 0x00000000 },
4906 { 0x3c10, 0, 0xffffffff, 0x00000000 },
4907 { 0x3c14, 0, 0x00000000, 0xffffffff },
4908 { 0x3c18, 0, 0x00000000, 0xffffffff },
4909 { 0x3c1c, 0, 0xfffff000, 0x00000000 },
4910 { 0x3c20, 0, 0xffffff00, 0x00000000 },
b6016b76
MC		 4911
4912 { 0x5004, 0, 0x00000000, 0x0000007f },
4913 { 0x5008, 0, 0x0f0007ff, 0x00000000 },
b6016b76 4914
b6016b76
MC		 4915 { 0x5c00, 0, 0x00000000, 0x00000001 },
4916 { 0x5c04, 0, 0x00000000, 0x0003000f },
4917 { 0x5c08, 0, 0x00000003, 0x00000000 },
4918 { 0x5c0c, 0, 0x0000fff8, 0x00000000 },
4919 { 0x5c10, 0, 0x00000000, 0xffffffff },
4920 { 0x5c80, 0, 0x00000000, 0x0f7113f1 },
4921 { 0x5c84, 0, 0x00000000, 0x0000f333 },
4922 { 0x5c88, 0, 0x00000000, 0x00077373 },
4923 { 0x5c8c, 0, 0x00000000, 0x0007f737 },
4924
4925 { 0x6808, 0, 0x0000ff7f, 0x00000000 },
4926 { 0x680c, 0, 0xffffffff, 0x00000000 },
4927 { 0x6810, 0, 0xffffffff, 0x00000000 },
4928 { 0x6814, 0, 0xffffffff, 0x00000000 },
4929 { 0x6818, 0, 0xffffffff, 0x00000000 },
4930 { 0x681c, 0, 0xffffffff, 0x00000000 },
4931 { 0x6820, 0, 0x00ff00ff, 0x00000000 },
4932 { 0x6824, 0, 0x00ff00ff, 0x00000000 },
4933 { 0x6828, 0, 0x00ff00ff, 0x00000000 },
4934 { 0x682c, 0, 0x03ff03ff, 0x00000000 },
4935 { 0x6830, 0, 0x03ff03ff, 0x00000000 },
4936 { 0x6834, 0, 0x03ff03ff, 0x00000000 },
4937 { 0x6838, 0, 0x03ff03ff, 0x00000000 },
4938 { 0x683c, 0, 0x0000ffff, 0x00000000 },
4939 { 0x6840, 0, 0x00000ff0, 0x00000000 },
4940 { 0x6844, 0, 0x00ffff00, 0x00000000 },
4941 { 0x684c, 0, 0xffffffff, 0x00000000 },
4942 { 0x6850, 0, 0x7f7f7f7f, 0x00000000 },
4943 { 0x6854, 0, 0x7f7f7f7f, 0x00000000 },
4944 { 0x6858, 0, 0x7f7f7f7f, 0x00000000 },
4945 { 0x685c, 0, 0x7f7f7f7f, 0x00000000 },
4946 { 0x6908, 0, 0x00000000, 0x0001ff0f },
4947 { 0x690c, 0, 0x00000000, 0x0ffe00f0 },
4948
4949 { 0xffff, 0, 0x00000000, 0x00000000 },
4950 };
4951
4952 ret = 0;
5bae30c9
MC		 4953 is_5709 = 0;
4954 if (CHIP_NUM(bp) == CHIP_NUM_5709)
4955 is_5709 = 1;
4956
b6016b76
MC		 4957 for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
4958 u32 offset, rw_mask, ro_mask, save_val, val;
5bae30c9
MC		 4959 u16 flags = reg_tbl[i].flags;
4960
4961 if (is_5709 && (flags & BNX2_FL_NOT_5709))
4962 continue;
b6016b76
MC		 4963
4964 offset = (u32) reg_tbl[i].offset;
4965 rw_mask = reg_tbl[i].rw_mask;
4966 ro_mask = reg_tbl[i].ro_mask;
4967
14ab9b86 4968 save_val = readl(bp->regview + offset);
b6016b76 4969
14ab9b86 4970 writel(0, bp->regview + offset);
b6016b76 4971
14ab9b86 4972 val = readl(bp->regview + offset);
b6016b76
MC		 4973 if ((val & rw_mask) != 0) {
4974 goto reg_test_err;
4975 }
4976
4977 if ((val & ro_mask) != (save_val & ro_mask)) {
4978 goto reg_test_err;
4979 }
4980
14ab9b86 4981 writel(0xffffffff, bp->regview + offset);
b6016b76 4982
14ab9b86 4983 val = readl(bp->regview + offset);
b6016b76
MC		 4984 if ((val & rw_mask) != rw_mask) {
4985 goto reg_test_err;
4986 }
4987
4988 if ((val & ro_mask) != (save_val & ro_mask)) {
4989 goto reg_test_err;
4990 }
4991
14ab9b86 4992 writel(save_val, bp->regview + offset);
b6016b76
MC		 4993 continue;
4994
4995reg_test_err:
14ab9b86 4996 writel(save_val, bp->regview + offset);
b6016b76
MC		 4997 ret = -ENODEV;
4998 break;
4999 }
5000 return ret;
5001}
5002
5003static int
5004bnx2_do_mem_test(struct bnx2 *bp, u32 start, u32 size)
5005{
f71e1309 5006 static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0x55555555,
b6016b76
MC		 5007 0xaaaaaaaa , 0xaa55aa55, 0x55aa55aa };
5008 int i;
5009
5010 for (i = 0; i < sizeof(test_pattern) / 4; i++) {
5011 u32 offset;
5012
5013 for (offset = 0; offset < size; offset += 4) {
5014
2726d6e1 5015 bnx2_reg_wr_ind(bp, start + offset, test_pattern[i]);
b6016b76 5016
2726d6e1 5017 if (bnx2_reg_rd_ind(bp, start + offset) !=
b6016b76
MC		 5018 test_pattern[i]) {
5019 return -ENODEV;
5020 }
5021 }
5022 }
5023 return 0;
5024}
5025
5026static int
5027bnx2_test_memory(struct bnx2 *bp)
5028{
5029 int ret = 0;
5030 int i;
5bae30c9 5031 static struct mem_entry {
b6016b76
MC		 5032 u32 offset;
5033 u32 len;
5bae30c9 5034 } mem_tbl_5706[] = {
b6016b76 5035 { 0x60000, 0x4000 },
5b0c76ad 5036 { 0xa0000, 0x3000 },
b6016b76
MC		 5037 { 0xe0000, 0x4000 },
5038 { 0x120000, 0x4000 },
5039 { 0x1a0000, 0x4000 },
5040 { 0x160000, 0x4000 },
5041 { 0xffffffff, 0 },
5bae30c9
MC		 5042 },
5043 mem_tbl_5709[] = {
5044 { 0x60000, 0x4000 },
5045 { 0xa0000, 0x3000 },
5046 { 0xe0000, 0x4000 },
5047 { 0x120000, 0x4000 },
5048 { 0x1a0000, 0x4000 },
5049 { 0xffffffff, 0 },
b6016b76 5050 };
5bae30c9
MC		 5051 struct mem_entry *mem_tbl;
5052
5053 if (CHIP_NUM(bp) == CHIP_NUM_5709)
5054 mem_tbl = mem_tbl_5709;
5055 else
5056 mem_tbl = mem_tbl_5706;
b6016b76
MC		 5057
5058 for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
5059 if ((ret = bnx2_do_mem_test(bp, mem_tbl[i].offset,
5060 mem_tbl[i].len)) != 0) {
5061 return ret;
5062 }
5063 }
6aa20a22 5064
b6016b76
MC		 5065 return ret;
5066}
5067
bc5a0690
MC		 5068#define BNX2_MAC_LOOPBACK 0
5069#define BNX2_PHY_LOOPBACK 1
5070
b6016b76 5071static int
bc5a0690 5072bnx2_run_loopback(struct bnx2 *bp, int loopback_mode)
b6016b76
MC		 5073{
5074 unsigned int pkt_size, num_pkts, i;
5075 struct sk_buff *skb, *rx_skb;
5076 unsigned char *packet;
bc5a0690 5077 u16 rx_start_idx, rx_idx;
b6016b76
MC		 5078 dma_addr_t map;
5079 struct tx_bd *txbd;
5080 struct sw_bd *rx_buf;
5081 struct l2_fhdr *rx_hdr;
5082 int ret = -ENODEV;
c76c0475
MC		 5083 struct bnx2_napi *bnapi = &bp->bnx2_napi[0], *tx_napi;
5084
5085 tx_napi = bnapi;
f86e82fb 5086 if (bp->flags & BNX2_FLAG_USING_MSIX)
c76c0475 5087 tx_napi = &bp->bnx2_napi[BNX2_TX_VEC];
b6016b76 5088
bc5a0690
MC		 5089 if (loopback_mode == BNX2_MAC_LOOPBACK) {
5090 bp->loopback = MAC_LOOPBACK;
5091 bnx2_set_mac_loopback(bp);
5092 }
5093 else if (loopback_mode == BNX2_PHY_LOOPBACK) {
583c28e5 5094 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
489310a4
MC		 5095 return 0;
5096
80be4434 5097 bp->loopback = PHY_LOOPBACK;
bc5a0690
MC		 5098 bnx2_set_phy_loopback(bp);
5099 }
5100 else
5101 return -EINVAL;
b6016b76 5102
84eaa187 5103 pkt_size = min(bp->dev->mtu + ETH_HLEN, bp->rx_jumbo_thresh - 4);
932f3772 5104 skb = netdev_alloc_skb(bp->dev, pkt_size);
b6cbc3b6
JL		 5105 if (!skb)
5106 return -ENOMEM;
b6016b76 5107 packet = skb_put(skb, pkt_size);
6634292b 5108 memcpy(packet, bp->dev->dev_addr, 6);
b6016b76
MC		 5109 memset(packet + 6, 0x0, 8);
5110 for (i = 14; i < pkt_size; i++)
5111 packet[i] = (unsigned char) (i & 0xff);
5112
5113 map = pci_map_single(bp->pdev, skb->data, pkt_size,
5114 PCI_DMA_TODEVICE);
5115
bf5295bb
MC		 5116 REG_WR(bp, BNX2_HC_COMMAND,
5117 bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
5118
b6016b76
MC		 5119 REG_RD(bp, BNX2_HC_COMMAND);
5120
5121 udelay(5);
35efa7c1 5122 rx_start_idx = bnx2_get_hw_rx_cons(bnapi);
b6016b76 5123
b6016b76
MC		 5124 num_pkts = 0;
5125
bc5a0690 5126 txbd = &bp->tx_desc_ring[TX_RING_IDX(bp->tx_prod)];
b6016b76
MC		 5127
5128 txbd->tx_bd_haddr_hi = (u64) map >> 32;
5129 txbd->tx_bd_haddr_lo = (u64) map & 0xffffffff;
5130 txbd->tx_bd_mss_nbytes = pkt_size;
5131 txbd->tx_bd_vlan_tag_flags = TX_BD_FLAGS_START | TX_BD_FLAGS_END;
5132
5133 num_pkts++;
bc5a0690
MC		 5134 bp->tx_prod = NEXT_TX_BD(bp->tx_prod);
5135 bp->tx_prod_bseq += pkt_size;
b6016b76 5136
234754d5
MC		 5137 REG_WR16(bp, bp->tx_bidx_addr, bp->tx_prod);
5138 REG_WR(bp, bp->tx_bseq_addr, bp->tx_prod_bseq);
b6016b76
MC		 5139
5140 udelay(100);
5141
bf5295bb
MC		 5142 REG_WR(bp, BNX2_HC_COMMAND,
5143 bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
5144
b6016b76
MC		 5145 REG_RD(bp, BNX2_HC_COMMAND);
5146
5147 udelay(5);
5148
5149 pci_unmap_single(bp->pdev, map, pkt_size, PCI_DMA_TODEVICE);
745720e5 5150 dev_kfree_skb(skb);
b6016b76 5151
c76c0475 5152 if (bnx2_get_hw_tx_cons(tx_napi) != bp->tx_prod)
b6016b76 5153 goto loopback_test_done;
b6016b76 5154
35efa7c1 5155 rx_idx = bnx2_get_hw_rx_cons(bnapi);
b6016b76
MC		 5156 if (rx_idx != rx_start_idx + num_pkts) {
5157 goto loopback_test_done;
5158 }
5159
5160 rx_buf = &bp->rx_buf_ring[rx_start_idx];
5161 rx_skb = rx_buf->skb;
5162
5163 rx_hdr = (struct l2_fhdr *) rx_skb->data;
d89cb6af 5164 skb_reserve(rx_skb, BNX2_RX_OFFSET);
b6016b76
MC		 5165
5166 pci_dma_sync_single_for_cpu(bp->pdev,
5167 pci_unmap_addr(rx_buf, mapping),
5168 bp->rx_buf_size, PCI_DMA_FROMDEVICE);
5169
ade2bfe7 5170 if (rx_hdr->l2_fhdr_status &
b6016b76
MC		 5171 (L2_FHDR_ERRORS_BAD_CRC |
5172 L2_FHDR_ERRORS_PHY_DECODE |
5173 L2_FHDR_ERRORS_ALIGNMENT |
5174 L2_FHDR_ERRORS_TOO_SHORT |
5175 L2_FHDR_ERRORS_GIANT_FRAME)) {
5176
5177 goto loopback_test_done;
5178 }
5179
5180 if ((rx_hdr->l2_fhdr_pkt_len - 4) != pkt_size) {
5181 goto loopback_test_done;
5182 }
5183
5184 for (i = 14; i < pkt_size; i++) {
5185 if (*(rx_skb->data + i) != (unsigned char) (i & 0xff)) {
5186 goto loopback_test_done;
5187 }
5188 }
5189
5190 ret = 0;
5191
5192loopback_test_done:
5193 bp->loopback = 0;
5194 return ret;
5195}
5196
bc5a0690
MC		 5197#define BNX2_MAC_LOOPBACK_FAILED 1
5198#define BNX2_PHY_LOOPBACK_FAILED 2
5199#define BNX2_LOOPBACK_FAILED (BNX2_MAC_LOOPBACK_FAILED | \
5200 BNX2_PHY_LOOPBACK_FAILED)
5201
5202static int
5203bnx2_test_loopback(struct bnx2 *bp)
5204{
5205 int rc = 0;
5206
5207 if (!netif_running(bp->dev))
5208 return BNX2_LOOPBACK_FAILED;
5209
5210 bnx2_reset_nic(bp, BNX2_DRV_MSG_CODE_RESET);
5211 spin_lock_bh(&bp->phy_lock);
9a120bc5 5212 bnx2_init_phy(bp, 1);
bc5a0690
MC		 5213 spin_unlock_bh(&bp->phy_lock);
5214 if (bnx2_run_loopback(bp, BNX2_MAC_LOOPBACK))
5215 rc |= BNX2_MAC_LOOPBACK_FAILED;
5216 if (bnx2_run_loopback(bp, BNX2_PHY_LOOPBACK))
5217 rc |= BNX2_PHY_LOOPBACK_FAILED;
5218 return rc;
5219}
5220
b6016b76
MC		 5221#define NVRAM_SIZE 0x200
5222#define CRC32_RESIDUAL 0xdebb20e3
5223
5224static int
5225bnx2_test_nvram(struct bnx2 *bp)
5226{
b491edd5 5227 __be32 buf[NVRAM_SIZE / 4];
b6016b76
MC		 5228 u8 *data = (u8 *) buf;
5229 int rc = 0;
5230 u32 magic, csum;
5231
5232 if ((rc = bnx2_nvram_read(bp, 0, data, 4)) != 0)
5233 goto test_nvram_done;
5234
5235 magic = be32_to_cpu(buf[0]);
5236 if (magic != 0x669955aa) {
5237 rc = -ENODEV;
5238 goto test_nvram_done;
5239 }
5240
5241 if ((rc = bnx2_nvram_read(bp, 0x100, data, NVRAM_SIZE)) != 0)
5242 goto test_nvram_done;
5243
5244 csum = ether_crc_le(0x100, data);
5245 if (csum != CRC32_RESIDUAL) {
5246 rc = -ENODEV;
5247 goto test_nvram_done;
5248 }
5249
5250 csum = ether_crc_le(0x100, data + 0x100);
5251 if (csum != CRC32_RESIDUAL) {
5252 rc = -ENODEV;
5253 }
5254
5255test_nvram_done:
5256 return rc;
5257}
5258
5259static int
5260bnx2_test_link(struct bnx2 *bp)
5261{
5262 u32 bmsr;
5263
583c28e5 5264 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) {
489310a4
MC		 5265 if (bp->link_up)
5266 return 0;
5267 return -ENODEV;
5268 }
c770a65c 5269 spin_lock_bh(&bp->phy_lock);
27a005b8
MC		 5270 bnx2_enable_bmsr1(bp);
5271 bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr);
5272 bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr);
5273 bnx2_disable_bmsr1(bp);
c770a65c 5274 spin_unlock_bh(&bp->phy_lock);
6aa20a22 5275
b6016b76
MC		 5276 if (bmsr & BMSR_LSTATUS) {
5277 return 0;
5278 }
5279 return -ENODEV;
5280}
5281
5282static int
5283bnx2_test_intr(struct bnx2 *bp)
5284{
5285 int i;
b6016b76
MC		 5286 u16 status_idx;
5287
5288 if (!netif_running(bp->dev))
5289 return -ENODEV;
5290
5291 status_idx = REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD) & 0xffff;
5292
5293 /* This register is not touched during run-time. */
bf5295bb 5294 REG_WR(bp, BNX2_HC_COMMAND, bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW);
b6016b76
MC		 5295 REG_RD(bp, BNX2_HC_COMMAND);
5296
5297 for (i = 0; i < 10; i++) {
5298 if ((REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD) & 0xffff) !=
5299 status_idx) {
5300
5301 break;
5302 }
5303
5304 msleep_interruptible(10);
5305 }
5306 if (i < 10)
5307 return 0;
5308
5309 return -ENODEV;
5310}
5311
38ea3686 5312/* Determining link for parallel detection. */
b2fadeae
MC		 5313static int
5314bnx2_5706_serdes_has_link(struct bnx2 *bp)
5315{
5316 u32 mode_ctl, an_dbg, exp;
5317
38ea3686
MC		 5318 if (bp->phy_flags & BNX2_PHY_FLAG_NO_PARALLEL)
5319 return 0;
5320
b2fadeae
MC		 5321 bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_MODE_CTL);
5322 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &mode_ctl);
5323
5324 if (!(mode_ctl & MISC_SHDW_MODE_CTL_SIG_DET))
5325 return 0;
5326
5327 bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_AN_DBG);
5328 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &an_dbg);
5329 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &an_dbg);
5330
f3014c0c 5331 if (an_dbg & (MISC_SHDW_AN_DBG_NOSYNC | MISC_SHDW_AN_DBG_RUDI_INVALID))
b2fadeae
MC		 5332 return 0;
5333
5334 bnx2_write_phy(bp, MII_BNX2_DSP_ADDRESS, MII_EXPAND_REG1);
5335 bnx2_read_phy(bp, MII_BNX2_DSP_RW_PORT, &exp);
5336 bnx2_read_phy(bp, MII_BNX2_DSP_RW_PORT, &exp);
5337
5338 if (exp & MII_EXPAND_REG1_RUDI_C) /* receiving CONFIG */
5339 return 0;
5340
5341 return 1;
5342}
5343
b6016b76 5344static void
48b01e2d 5345bnx2_5706_serdes_timer(struct bnx2 *bp)
b6016b76 5346{
b2fadeae
MC		 5347 int check_link = 1;
5348
48b01e2d 5349 spin_lock(&bp->phy_lock);
b2fadeae 5350 if (bp->serdes_an_pending) {
48b01e2d 5351 bp->serdes_an_pending--;
b2fadeae
MC		 5352 check_link = 0;
5353 } else if ((bp->link_up == 0) && (bp->autoneg & AUTONEG_SPEED)) {
48b01e2d 5354 u32 bmcr;
b6016b76 5355
48b01e2d 5356 bp->current_interval = bp->timer_interval;
cd339a0e 5357
ca58c3af 5358 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
b6016b76 5359
48b01e2d 5360 if (bmcr & BMCR_ANENABLE) {
b2fadeae 5361 if (bnx2_5706_serdes_has_link(bp)) {
48b01e2d
MC		 5362 bmcr &= ~BMCR_ANENABLE;
5363 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
ca58c3af 5364 bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
583c28e5 5365 bp->phy_flags |= BNX2_PHY_FLAG_PARALLEL_DETECT;
48b01e2d 5366 }
b6016b76 5367 }
48b01e2d
MC		 5368 }
5369 else if ((bp->link_up) && (bp->autoneg & AUTONEG_SPEED) &&
583c28e5 5370 (bp->phy_flags & BNX2_PHY_FLAG_PARALLEL_DETECT)) {
48b01e2d 5371 u32 phy2;
b6016b76 5372
48b01e2d
MC		 5373 bnx2_write_phy(bp, 0x17, 0x0f01);
5374 bnx2_read_phy(bp, 0x15, &phy2);
5375 if (phy2 & 0x20) {
5376 u32 bmcr;
cd339a0e 5377
ca58c3af 5378 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
48b01e2d 5379 bmcr |= BMCR_ANENABLE;
ca58c3af 5380 bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
b6016b76 5381
583c28e5 5382 bp->phy_flags &= ~BNX2_PHY_FLAG_PARALLEL_DETECT;
48b01e2d
MC		 5383 }
5384 } else
5385 bp->current_interval = bp->timer_interval;
b6016b76 5386
a2724e25 5387 if (check_link) {
b2fadeae
MC		 5388 u32 val;
5389
5390 bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_AN_DBG);
5391 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &val);
5392 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &val);
5393
a2724e25
MC		 5394 if (bp->link_up && (val & MISC_SHDW_AN_DBG_NOSYNC)) {
5395 if (!(bp->phy_flags & BNX2_PHY_FLAG_FORCED_DOWN)) {
5396 bnx2_5706s_force_link_dn(bp, 1);
5397 bp->phy_flags |= BNX2_PHY_FLAG_FORCED_DOWN;
5398 } else
5399 bnx2_set_link(bp);
5400 } else if (!bp->link_up && !(val & MISC_SHDW_AN_DBG_NOSYNC))
5401 bnx2_set_link(bp);
b2fadeae 5402 }
48b01e2d
MC		 5403 spin_unlock(&bp->phy_lock);
5404}
b6016b76 5405
f8dd064e
MC		 5406static void
5407bnx2_5708_serdes_timer(struct bnx2 *bp)
5408{
583c28e5 5409 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
0d8a6571
MC		 5410 return;
5411
583c28e5 5412 if ((bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE) == 0) {
f8dd064e
MC		 5413 bp->serdes_an_pending = 0;
5414 return;
5415 }
b6016b76 5416
f8dd064e
MC		 5417 spin_lock(&bp->phy_lock);
5418 if (bp->serdes_an_pending)
5419 bp->serdes_an_pending--;
5420 else if ((bp->link_up == 0) && (bp->autoneg & AUTONEG_SPEED)) {
5421 u32 bmcr;
b6016b76 5422
ca58c3af 5423 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
f8dd064e 5424 if (bmcr & BMCR_ANENABLE) {
605a9e20 5425 bnx2_enable_forced_2g5(bp);
f8dd064e
MC		 5426 bp->current_interval = SERDES_FORCED_TIMEOUT;
5427 } else {
605a9e20 5428 bnx2_disable_forced_2g5(bp);
f8dd064e
MC		 5429 bp->serdes_an_pending = 2;
5430 bp->current_interval = bp->timer_interval;
b6016b76 5431 }
b6016b76 5432
f8dd064e
MC		 5433 } else
5434 bp->current_interval = bp->timer_interval;
b6016b76 5435
f8dd064e
MC		 5436 spin_unlock(&bp->phy_lock);
5437}
5438
48b01e2d
MC		 5439static void
5440bnx2_timer(unsigned long data)
5441{
5442 struct bnx2 *bp = (struct bnx2 *) data;
b6016b76 5443
48b01e2d
MC		 5444 if (!netif_running(bp->dev))
5445 return;
b6016b76 5446
48b01e2d
MC		 5447 if (atomic_read(&bp->intr_sem) != 0)
5448 goto bnx2_restart_timer;
b6016b76 5449
df149d70 5450 bnx2_send_heart_beat(bp);
b6016b76 5451
2726d6e1
MC		 5452 bp->stats_blk->stat_FwRxDrop =
5453 bnx2_reg_rd_ind(bp, BNX2_FW_RX_DROP_COUNT);
b6016b76 5454
02537b06
MC		 5455 /* workaround occasional corrupted counters */
5456 if (CHIP_NUM(bp) == CHIP_NUM_5708 && bp->stats_ticks)
5457 REG_WR(bp, BNX2_HC_COMMAND, bp->hc_cmd |
5458 BNX2_HC_COMMAND_STATS_NOW);
5459
583c28e5 5460 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
f8dd064e
MC		 5461 if (CHIP_NUM(bp) == CHIP_NUM_5706)
5462 bnx2_5706_serdes_timer(bp);
27a005b8 5463 else
f8dd064e 5464 bnx2_5708_serdes_timer(bp);
b6016b76
MC		 5465 }
5466
5467bnx2_restart_timer:
cd339a0e 5468 mod_timer(&bp->timer, jiffies + bp->current_interval);
b6016b76
MC		 5469}
5470
8e6a72c4
MC		 5471static int
5472bnx2_request_irq(struct bnx2 *bp)
5473{
5474 struct net_device *dev = bp->dev;
6d866ffc 5475 unsigned long flags;
b4b36042
MC		 5476 struct bnx2_irq *irq;
5477 int rc = 0, i;
8e6a72c4 5478
f86e82fb 5479 if (bp->flags & BNX2_FLAG_USING_MSI_OR_MSIX)
6d866ffc
MC		 5480 flags = 0;
5481 else
5482 flags = IRQF_SHARED;
b4b36042
MC		 5483
5484 for (i = 0; i < bp->irq_nvecs; i++) {
5485 irq = &bp->irq_tbl[i];
c76c0475 5486 rc = request_irq(irq->vector, irq->handler, flags, irq->name,
b4b36042
MC		 5487 dev);
5488 if (rc)
5489 break;
5490 irq->requested = 1;
5491 }
8e6a72c4
MC		 5492 return rc;
5493}
5494
5495static void
5496bnx2_free_irq(struct bnx2 *bp)
5497{
5498 struct net_device *dev = bp->dev;
b4b36042
MC		 5499 struct bnx2_irq *irq;
5500 int i;
8e6a72c4 5501
b4b36042
MC		 5502 for (i = 0; i < bp->irq_nvecs; i++) {
5503 irq = &bp->irq_tbl[i];
5504 if (irq->requested)
5505 free_irq(irq->vector, dev);
5506 irq->requested = 0;
6d866ffc 5507 }
f86e82fb 5508 if (bp->flags & BNX2_FLAG_USING_MSI)
b4b36042 5509 pci_disable_msi(bp->pdev);
f86e82fb 5510 else if (bp->flags & BNX2_FLAG_USING_MSIX)
b4b36042
MC		 5511 pci_disable_msix(bp->pdev);
5512
f86e82fb 5513 bp->flags &= ~(BNX2_FLAG_USING_MSI_OR_MSIX | BNX2_FLAG_ONE_SHOT_MSI);
b4b36042
MC		 5514}
5515
5516static void
5517bnx2_enable_msix(struct bnx2 *bp)
5518{
57851d84
MC		 5519 int i, rc;
5520 struct msix_entry msix_ent[BNX2_MAX_MSIX_VEC];
5521
b4b36042
MC		 5522 bnx2_setup_msix_tbl(bp);
5523 REG_WR(bp, BNX2_PCI_MSIX_CONTROL, BNX2_MAX_MSIX_HW_VEC - 1);
5524 REG_WR(bp, BNX2_PCI_MSIX_TBL_OFF_BIR, BNX2_PCI_GRC_WINDOW2_BASE);
5525 REG_WR(bp, BNX2_PCI_MSIX_PBA_OFF_BIT, BNX2_PCI_GRC_WINDOW3_BASE);
57851d84
MC		 5526
5527 for (i = 0; i < BNX2_MAX_MSIX_VEC; i++) {
5528 msix_ent[i].entry = i;
5529 msix_ent[i].vector = 0;
5530 }
5531
5532 rc = pci_enable_msix(bp->pdev, msix_ent, BNX2_MAX_MSIX_VEC);
5533 if (rc != 0)
5534 return;
5535
5536 bp->irq_tbl[BNX2_BASE_VEC].handler = bnx2_msi_1shot;
5537 bp->irq_tbl[BNX2_TX_VEC].handler = bnx2_tx_msix;
5538
5539 strcpy(bp->irq_tbl[BNX2_BASE_VEC].name, bp->dev->name);
5540 strcat(bp->irq_tbl[BNX2_BASE_VEC].name, "-base");
5541 strcpy(bp->irq_tbl[BNX2_TX_VEC].name, bp->dev->name);
5542 strcat(bp->irq_tbl[BNX2_TX_VEC].name, "-tx");
5543
5544 bp->irq_nvecs = BNX2_MAX_MSIX_VEC;
f86e82fb 5545 bp->flags |= BNX2_FLAG_USING_MSIX | BNX2_FLAG_ONE_SHOT_MSI;
57851d84
MC		 5546 for (i = 0; i < BNX2_MAX_MSIX_VEC; i++)
5547 bp->irq_tbl[i].vector = msix_ent[i].vector;
6d866ffc
MC		 5548}
5549
5550static void
5551bnx2_setup_int_mode(struct bnx2 *bp, int dis_msi)
5552{
5553 bp->irq_tbl[0].handler = bnx2_interrupt;
5554 strcpy(bp->irq_tbl[0].name, bp->dev->name);
b4b36042
MC		 5555 bp->irq_nvecs = 1;
5556 bp->irq_tbl[0].vector = bp->pdev->irq;
5557
f86e82fb 5558 if ((bp->flags & BNX2_FLAG_MSIX_CAP) && !dis_msi)
b4b36042 5559 bnx2_enable_msix(bp);
6d866ffc 5560
f86e82fb
DM		 5561 if ((bp->flags & BNX2_FLAG_MSI_CAP) && !dis_msi &&
5562 !(bp->flags & BNX2_FLAG_USING_MSIX)) {
6d866ffc 5563 if (pci_enable_msi(bp->pdev) == 0) {
f86e82fb 5564 bp->flags |= BNX2_FLAG_USING_MSI;
6d866ffc 5565 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
f86e82fb 5566 bp->flags |= BNX2_FLAG_ONE_SHOT_MSI;
6d866ffc
MC		 5567 bp->irq_tbl[0].handler = bnx2_msi_1shot;
5568 } else
5569 bp->irq_tbl[0].handler = bnx2_msi;
b4b36042
MC		 5570
5571 bp->irq_tbl[0].vector = bp->pdev->irq;
6d866ffc
MC		 5572 }
5573 }
8e6a72c4
MC		 5574}
5575
b6016b76
MC		 5576/* Called with rtnl_lock */
5577static int
5578bnx2_open(struct net_device *dev)
5579{
972ec0d4 5580 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 5581 int rc;
5582
1b2f922f
MC		 5583 netif_carrier_off(dev);
5584
829ca9a3 5585 bnx2_set_power_state(bp, PCI_D0);
b6016b76
MC		 5586 bnx2_disable_int(bp);
5587
5588 rc = bnx2_alloc_mem(bp);
5589 if (rc)
5590 return rc;
5591
6d866ffc 5592 bnx2_setup_int_mode(bp, disable_msi);
35efa7c1 5593 bnx2_napi_enable(bp);
8e6a72c4
MC		 5594 rc = bnx2_request_irq(bp);
5595
b6016b76 5596 if (rc) {
35efa7c1 5597 bnx2_napi_disable(bp);
b6016b76
MC		 5598 bnx2_free_mem(bp);
5599 return rc;
5600 }
5601
9a120bc5 5602 rc = bnx2_init_nic(bp, 1);
b6016b76
MC		 5603
5604 if (rc) {
35efa7c1 5605 bnx2_napi_disable(bp);
8e6a72c4 5606 bnx2_free_irq(bp);
b6016b76
MC		 5607 bnx2_free_skbs(bp);
5608 bnx2_free_mem(bp);
5609 return rc;
5610 }
6aa20a22 5611
cd339a0e 5612 mod_timer(&bp->timer, jiffies + bp->current_interval);
b6016b76
MC		 5613
5614 atomic_set(&bp->intr_sem, 0);
5615
5616 bnx2_enable_int(bp);
5617
f86e82fb 5618 if (bp->flags & BNX2_FLAG_USING_MSI) {
b6016b76
MC		 5619 /* Test MSI to make sure it is working
5620 * If MSI test fails, go back to INTx mode
5621 */
5622 if (bnx2_test_intr(bp) != 0) {
5623 printk(KERN_WARNING PFX "%s: No interrupt was generated"
5624 " using MSI, switching to INTx mode. Please"
5625 " report this failure to the PCI maintainer"
5626 " and include system chipset information.\n",
5627 bp->dev->name);
5628
5629 bnx2_disable_int(bp);
8e6a72c4 5630 bnx2_free_irq(bp);
b6016b76 5631
6d866ffc
MC		 5632 bnx2_setup_int_mode(bp, 1);
5633
9a120bc5 5634 rc = bnx2_init_nic(bp, 0);
b6016b76 5635
8e6a72c4
MC		 5636 if (!rc)
5637 rc = bnx2_request_irq(bp);
5638
b6016b76 5639 if (rc) {
35efa7c1 5640 bnx2_napi_disable(bp);
b6016b76
MC		 5641 bnx2_free_skbs(bp);
5642 bnx2_free_mem(bp);
5643 del_timer_sync(&bp->timer);
5644 return rc;
5645 }
5646 bnx2_enable_int(bp);
5647 }
5648 }
f86e82fb 5649 if (bp->flags & BNX2_FLAG_USING_MSI)
b6016b76 5650 printk(KERN_INFO PFX "%s: using MSI\n", dev->name);
f86e82fb 5651 else if (bp->flags & BNX2_FLAG_USING_MSIX)
57851d84 5652 printk(KERN_INFO PFX "%s: using MSIX\n", dev->name);
b6016b76
MC		 5653
5654 netif_start_queue(dev);
5655
5656 return 0;
5657}
5658
5659static void
c4028958 5660bnx2_reset_task(struct work_struct *work)
b6016b76 5661{
c4028958 5662 struct bnx2 *bp = container_of(work, struct bnx2, reset_task);
b6016b76 5663
afdc08b9
MC		 5664 if (!netif_running(bp->dev))
5665 return;
5666
b6016b76
MC		 5667 bnx2_netif_stop(bp);
5668
9a120bc5 5669 bnx2_init_nic(bp, 1);
b6016b76
MC		 5670
5671 atomic_set(&bp->intr_sem, 1);
5672 bnx2_netif_start(bp);
5673}
5674
5675static void
5676bnx2_tx_timeout(struct net_device *dev)
5677{
972ec0d4 5678 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 5679
5680 /* This allows the netif to be shutdown gracefully before resetting */
5681 schedule_work(&bp->reset_task);
5682}
5683
5684#ifdef BCM_VLAN
5685/* Called with rtnl_lock */
5686static void
5687bnx2_vlan_rx_register(struct net_device *dev, struct vlan_group *vlgrp)
5688{
972ec0d4 5689 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 5690
5691 bnx2_netif_stop(bp);
5692
5693 bp->vlgrp = vlgrp;
5694 bnx2_set_rx_mode(dev);
5695
5696 bnx2_netif_start(bp);
5697}
b6016b76
MC		 5698#endif
5699
932ff279 5700/* Called with netif_tx_lock.
2f8af120
MC		 5701 * bnx2_tx_int() runs without netif_tx_lock unless it needs to call
5702 * netif_wake_queue().
b6016b76
MC		 5703 */
5704static int
5705bnx2_start_xmit(struct sk_buff *skb, struct net_device *dev)
5706{
972ec0d4 5707 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 5708 dma_addr_t mapping;
5709 struct tx_bd *txbd;
5710 struct sw_bd *tx_buf;
5711 u32 len, vlan_tag_flags, last_frag, mss;
5712 u16 prod, ring_prod;
5713 int i;
57851d84 5714 struct bnx2_napi *bnapi = &bp->bnx2_napi[bp->tx_vec];
b6016b76 5715
a550c99b
MC		 5716 if (unlikely(bnx2_tx_avail(bp, bnapi) <
5717 (skb_shinfo(skb)->nr_frags + 1))) {
b6016b76
MC		 5718 netif_stop_queue(dev);
5719 printk(KERN_ERR PFX "%s: BUG! Tx ring full when queue awake!\n",
5720 dev->name);
5721
5722 return NETDEV_TX_BUSY;
5723 }
5724 len = skb_headlen(skb);
5725 prod = bp->tx_prod;
5726 ring_prod = TX_RING_IDX(prod);
5727
5728 vlan_tag_flags = 0;
84fa7933 5729 if (skb->ip_summed == CHECKSUM_PARTIAL) {
b6016b76
MC		 5730 vlan_tag_flags |= TX_BD_FLAGS_TCP_UDP_CKSUM;
5731 }
5732
79ea13ce 5733 if (bp->vlgrp && vlan_tx_tag_present(skb)) {
b6016b76
MC		 5734 vlan_tag_flags |=
5735 (TX_BD_FLAGS_VLAN_TAG | (vlan_tx_tag_get(skb) << 16));
5736 }
fde82055 5737 if ((mss = skb_shinfo(skb)->gso_size)) {
b6016b76 5738 u32 tcp_opt_len, ip_tcp_len;
eddc9ec5 5739 struct iphdr *iph;
b6016b76 5740
b6016b76
MC		 5741 vlan_tag_flags |= TX_BD_FLAGS_SW_LSO;
5742
4666f87a
MC		 5743 tcp_opt_len = tcp_optlen(skb);
5744
5745 if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6) {
5746 u32 tcp_off = skb_transport_offset(skb) -
5747 sizeof(struct ipv6hdr) - ETH_HLEN;
ab6a5bb6 5748
4666f87a
MC		 5749 vlan_tag_flags |= ((tcp_opt_len >> 2) << 8) |
5750 TX_BD_FLAGS_SW_FLAGS;
5751 if (likely(tcp_off == 0))
5752 vlan_tag_flags &= ~TX_BD_FLAGS_TCP6_OFF0_MSK;
5753 else {
5754 tcp_off >>= 3;
5755 vlan_tag_flags |= ((tcp_off & 0x3) <<
5756 TX_BD_FLAGS_TCP6_OFF0_SHL) |
5757 ((tcp_off & 0x10) <<
5758 TX_BD_FLAGS_TCP6_OFF4_SHL);
5759 mss |= (tcp_off & 0xc) << TX_BD_TCP6_OFF2_SHL;
5760 }
5761 } else {
5762 if (skb_header_cloned(skb) &&
5763 pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
5764 dev_kfree_skb(skb);
5765 return NETDEV_TX_OK;
5766 }
b6016b76 5767
4666f87a
MC		 5768 ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
5769
5770 iph = ip_hdr(skb);
5771 iph->check = 0;
5772 iph->tot_len = htons(mss + ip_tcp_len + tcp_opt_len);
5773 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
5774 iph->daddr, 0,
5775 IPPROTO_TCP,
5776 0);
5777 if (tcp_opt_len || (iph->ihl > 5)) {
5778 vlan_tag_flags |= ((iph->ihl - 5) +
5779 (tcp_opt_len >> 2)) << 8;
5780 }
b6016b76 5781 }
4666f87a 5782 } else
b6016b76 5783 mss = 0;
b6016b76
MC		 5784
5785 mapping = pci_map_single(bp->pdev, skb->data, len, PCI_DMA_TODEVICE);
6aa20a22 5786
b6016b76
MC		 5787 tx_buf = &bp->tx_buf_ring[ring_prod];
5788 tx_buf->skb = skb;
5789 pci_unmap_addr_set(tx_buf, mapping, mapping);
5790
5791 txbd = &bp->tx_desc_ring[ring_prod];
5792
5793 txbd->tx_bd_haddr_hi = (u64) mapping >> 32;
5794 txbd->tx_bd_haddr_lo = (u64) mapping & 0xffffffff;
5795 txbd->tx_bd_mss_nbytes = len | (mss << 16);
5796 txbd->tx_bd_vlan_tag_flags = vlan_tag_flags | TX_BD_FLAGS_START;
5797
5798 last_frag = skb_shinfo(skb)->nr_frags;
5799
5800 for (i = 0; i < last_frag; i++) {
5801 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5802
5803 prod = NEXT_TX_BD(prod);
5804 ring_prod = TX_RING_IDX(prod);
5805 txbd = &bp->tx_desc_ring[ring_prod];
5806
5807 len = frag->size;
5808 mapping = pci_map_page(bp->pdev, frag->page, frag->page_offset,
5809 len, PCI_DMA_TODEVICE);
5810 pci_unmap_addr_set(&bp->tx_buf_ring[ring_prod],
5811 mapping, mapping);
5812
5813 txbd->tx_bd_haddr_hi = (u64) mapping >> 32;
5814 txbd->tx_bd_haddr_lo = (u64) mapping & 0xffffffff;
5815 txbd->tx_bd_mss_nbytes = len | (mss << 16);
5816 txbd->tx_bd_vlan_tag_flags = vlan_tag_flags;
5817
5818 }
5819 txbd->tx_bd_vlan_tag_flags |= TX_BD_FLAGS_END;
5820
5821 prod = NEXT_TX_BD(prod);
5822 bp->tx_prod_bseq += skb->len;
5823
234754d5
MC		 5824 REG_WR16(bp, bp->tx_bidx_addr, prod);
5825 REG_WR(bp, bp->tx_bseq_addr, bp->tx_prod_bseq);
b6016b76
MC		 5826
5827 mmiowb();
5828
5829 bp->tx_prod = prod;
5830 dev->trans_start = jiffies;
5831
a550c99b 5832 if (unlikely(bnx2_tx_avail(bp, bnapi) <= MAX_SKB_FRAGS)) {
e89bbf10 5833 netif_stop_queue(dev);
a550c99b 5834 if (bnx2_tx_avail(bp, bnapi) > bp->tx_wake_thresh)
e89bbf10 5835 netif_wake_queue(dev);
b6016b76
MC		 5836 }
5837
5838 return NETDEV_TX_OK;
5839}
5840
5841/* Called with rtnl_lock */
5842static int
5843bnx2_close(struct net_device *dev)
5844{
972ec0d4 5845 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 5846 u32 reset_code;
5847
4bb073c0 5848 cancel_work_sync(&bp->reset_task);
afdc08b9 5849
bea3348e 5850 bnx2_disable_int_sync(bp);
35efa7c1 5851 bnx2_napi_disable(bp);
b6016b76 5852 del_timer_sync(&bp->timer);
f86e82fb 5853 if (bp->flags & BNX2_FLAG_NO_WOL)
6c4f095e 5854 reset_code = BNX2_DRV_MSG_CODE_UNLOAD_LNK_DN;
dda1e390 5855 else if (bp->wol)
b6016b76
MC		 5856 reset_code = BNX2_DRV_MSG_CODE_SUSPEND_WOL;
5857 else
5858 reset_code = BNX2_DRV_MSG_CODE_SUSPEND_NO_WOL;
5859 bnx2_reset_chip(bp, reset_code);
8e6a72c4 5860 bnx2_free_irq(bp);
b6016b76
MC		 5861 bnx2_free_skbs(bp);
5862 bnx2_free_mem(bp);
5863 bp->link_up = 0;
5864 netif_carrier_off(bp->dev);
829ca9a3 5865 bnx2_set_power_state(bp, PCI_D3hot);
b6016b76
MC		 5866 return 0;
5867}
5868
5869#define GET_NET_STATS64(ctr) \
5870 (unsigned long) ((unsigned long) (ctr##_hi) << 32) + \
5871 (unsigned long) (ctr##_lo)
5872
5873#define GET_NET_STATS32(ctr) \
5874 (ctr##_lo)
5875
5876#if (BITS_PER_LONG == 64)
5877#define GET_NET_STATS GET_NET_STATS64
5878#else
5879#define GET_NET_STATS GET_NET_STATS32
5880#endif
5881
5882static struct net_device_stats *
5883bnx2_get_stats(struct net_device *dev)
5884{
972ec0d4 5885 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 5886 struct statistics_block *stats_blk = bp->stats_blk;
5887 struct net_device_stats *net_stats = &bp->net_stats;
5888
5889 if (bp->stats_blk == NULL) {
5890 return net_stats;
5891 }
5892 net_stats->rx_packets =
5893 GET_NET_STATS(stats_blk->stat_IfHCInUcastPkts) +
5894 GET_NET_STATS(stats_blk->stat_IfHCInMulticastPkts) +
5895 GET_NET_STATS(stats_blk->stat_IfHCInBroadcastPkts);
5896
5897 net_stats->tx_packets =
5898 GET_NET_STATS(stats_blk->stat_IfHCOutUcastPkts) +
5899 GET_NET_STATS(stats_blk->stat_IfHCOutMulticastPkts) +
5900 GET_NET_STATS(stats_blk->stat_IfHCOutBroadcastPkts);
5901
5902 net_stats->rx_bytes =
5903 GET_NET_STATS(stats_blk->stat_IfHCInOctets);
5904
5905 net_stats->tx_bytes =
5906 GET_NET_STATS(stats_blk->stat_IfHCOutOctets);
5907
6aa20a22 5908 net_stats->multicast =
b6016b76
MC		 5909 GET_NET_STATS(stats_blk->stat_IfHCOutMulticastPkts);
5910
6aa20a22 5911 net_stats->collisions =
b6016b76
MC		 5912 (unsigned long) stats_blk->stat_EtherStatsCollisions;
5913
6aa20a22 5914 net_stats->rx_length_errors =
b6016b76
MC		 5915 (unsigned long) (stats_blk->stat_EtherStatsUndersizePkts +
5916 stats_blk->stat_EtherStatsOverrsizePkts);
5917
6aa20a22 5918 net_stats->rx_over_errors =
b6016b76
MC		 5919 (unsigned long) stats_blk->stat_IfInMBUFDiscards;
5920
6aa20a22 5921 net_stats->rx_frame_errors =
b6016b76
MC		 5922 (unsigned long) stats_blk->stat_Dot3StatsAlignmentErrors;
5923
6aa20a22 5924 net_stats->rx_crc_errors =
b6016b76
MC		 5925 (unsigned long) stats_blk->stat_Dot3StatsFCSErrors;
5926
5927 net_stats->rx_errors = net_stats->rx_length_errors +
5928 net_stats->rx_over_errors + net_stats->rx_frame_errors +
5929 net_stats->rx_crc_errors;
5930
5931 net_stats->tx_aborted_errors =
5932 (unsigned long) (stats_blk->stat_Dot3StatsExcessiveCollisions +
5933 stats_blk->stat_Dot3StatsLateCollisions);
5934
5b0c76ad
MC		 5935 if ((CHIP_NUM(bp) == CHIP_NUM_5706) ||
5936 (CHIP_ID(bp) == CHIP_ID_5708_A0))
b6016b76
MC		 5937 net_stats->tx_carrier_errors = 0;
5938 else {
5939 net_stats->tx_carrier_errors =
5940 (unsigned long)
5941 stats_blk->stat_Dot3StatsCarrierSenseErrors;
5942 }
5943
5944 net_stats->tx_errors =
6aa20a22 5945 (unsigned long)
b6016b76
MC		 5946 stats_blk->stat_emac_tx_stat_dot3statsinternalmactransmiterrors
5947 +
5948 net_stats->tx_aborted_errors +
5949 net_stats->tx_carrier_errors;
5950
cea94db9
MC		 5951 net_stats->rx_missed_errors =
5952 (unsigned long) (stats_blk->stat_IfInMBUFDiscards +
5953 stats_blk->stat_FwRxDrop);
5954
b6016b76
MC		 5955 return net_stats;
5956}
5957
5958/* All ethtool functions called with rtnl_lock */
5959
5960static int
5961bnx2_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
5962{
972ec0d4 5963 struct bnx2 *bp = netdev_priv(dev);
7b6b8347 5964 int support_serdes = 0, support_copper = 0;
b6016b76
MC		 5965
5966 cmd->supported = SUPPORTED_Autoneg;
583c28e5 5967 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) {
7b6b8347
MC		 5968 support_serdes = 1;
5969 support_copper = 1;
5970 } else if (bp->phy_port == PORT_FIBRE)
5971 support_serdes = 1;
5972 else
5973 support_copper = 1;
5974
5975 if (support_serdes) {
b6016b76
MC		 5976 cmd->supported |= SUPPORTED_1000baseT_Full |
5977 SUPPORTED_FIBRE;
583c28e5 5978 if (bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE)
605a9e20 5979 cmd->supported |= SUPPORTED_2500baseX_Full;
b6016b76 5980
b6016b76 5981 }
7b6b8347 5982 if (support_copper) {
b6016b76
MC		 5983 cmd->supported |= SUPPORTED_10baseT_Half |
5984 SUPPORTED_10baseT_Full |
5985 SUPPORTED_100baseT_Half |
5986 SUPPORTED_100baseT_Full |
5987 SUPPORTED_1000baseT_Full |
5988 SUPPORTED_TP;
5989
b6016b76
MC		 5990 }
5991
7b6b8347
MC		 5992 spin_lock_bh(&bp->phy_lock);
5993 cmd->port = bp->phy_port;
b6016b76
MC		 5994 cmd->advertising = bp->advertising;
5995
5996 if (bp->autoneg & AUTONEG_SPEED) {
5997 cmd->autoneg = AUTONEG_ENABLE;
5998 }
5999 else {
6000 cmd->autoneg = AUTONEG_DISABLE;
6001 }
6002
6003 if (netif_carrier_ok(dev)) {
6004 cmd->speed = bp->line_speed;
6005 cmd->duplex = bp->duplex;
6006 }
6007 else {
6008 cmd->speed = -1;
6009 cmd->duplex = -1;
6010 }
7b6b8347 6011 spin_unlock_bh(&bp->phy_lock);
b6016b76
MC		 6012
6013 cmd->transceiver = XCVR_INTERNAL;
6014 cmd->phy_address = bp->phy_addr;
6015
6016 return 0;
6017}
6aa20a22 6018
b6016b76
MC		 6019static int
6020bnx2_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
6021{
972ec0d4 6022 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 6023 u8 autoneg = bp->autoneg;
6024 u8 req_duplex = bp->req_duplex;
6025 u16 req_line_speed = bp->req_line_speed;
6026 u32 advertising = bp->advertising;
7b6b8347
MC		 6027 int err = -EINVAL;
6028
6029 spin_lock_bh(&bp->phy_lock);
6030
6031 if (cmd->port != PORT_TP && cmd->port != PORT_FIBRE)
6032 goto err_out_unlock;
6033
583c28e5
MC		 6034 if (cmd->port != bp->phy_port &&
6035 !(bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP))
7b6b8347 6036 goto err_out_unlock;
b6016b76
MC		 6037
6038 if (cmd->autoneg == AUTONEG_ENABLE) {
6039 autoneg |= AUTONEG_SPEED;
6040
6aa20a22 6041 cmd->advertising &= ETHTOOL_ALL_COPPER_SPEED;
b6016b76
MC		 6042
6043 /* allow advertising 1 speed */
6044 if ((cmd->advertising == ADVERTISED_10baseT_Half) ||
6045 (cmd->advertising == ADVERTISED_10baseT_Full) ||
6046 (cmd->advertising == ADVERTISED_100baseT_Half) ||
6047 (cmd->advertising == ADVERTISED_100baseT_Full)) {
6048
7b6b8347
MC		 6049 if (cmd->port == PORT_FIBRE)
6050 goto err_out_unlock;
b6016b76
MC		 6051
6052 advertising = cmd->advertising;
6053
27a005b8 6054 } else if (cmd->advertising == ADVERTISED_2500baseX_Full) {
583c28e5 6055 if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE) ||
7b6b8347
MC		 6056 (cmd->port == PORT_TP))
6057 goto err_out_unlock;
6058 } else if (cmd->advertising == ADVERTISED_1000baseT_Full)
b6016b76 6059 advertising = cmd->advertising;
7b6b8347
MC		 6060 else if (cmd->advertising == ADVERTISED_1000baseT_Half)
6061 goto err_out_unlock;
b6016b76 6062 else {
7b6b8347 6063 if (cmd->port == PORT_FIBRE)
b6016b76 6064 advertising = ETHTOOL_ALL_FIBRE_SPEED;
7b6b8347 6065 else
b6016b76 6066 advertising = ETHTOOL_ALL_COPPER_SPEED;
b6016b76
MC		 6067 }
6068 advertising |= ADVERTISED_Autoneg;
6069 }
6070 else {
7b6b8347 6071 if (cmd->port == PORT_FIBRE) {
80be4434
MC		 6072 if ((cmd->speed != SPEED_1000 &&
6073 cmd->speed != SPEED_2500) ||
6074 (cmd->duplex != DUPLEX_FULL))
7b6b8347 6075 goto err_out_unlock;
80be4434
MC		 6076
6077 if (cmd->speed == SPEED_2500 &&
583c28e5 6078 !(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))
7b6b8347 6079 goto err_out_unlock;
b6016b76 6080 }
7b6b8347
MC		 6081 else if (cmd->speed == SPEED_1000 || cmd->speed == SPEED_2500)
6082 goto err_out_unlock;
6083
b6016b76
MC		 6084 autoneg &= ~AUTONEG_SPEED;
6085 req_line_speed = cmd->speed;
6086 req_duplex = cmd->duplex;
6087 advertising = 0;
6088 }
6089
6090 bp->autoneg = autoneg;
6091 bp->advertising = advertising;
6092 bp->req_line_speed = req_line_speed;
6093 bp->req_duplex = req_duplex;
6094
7b6b8347 6095 err = bnx2_setup_phy(bp, cmd->port);
b6016b76 6096
7b6b8347 6097err_out_unlock:
c770a65c 6098 spin_unlock_bh(&bp->phy_lock);
b6016b76 6099
7b6b8347 6100 return err;
b6016b76
MC		 6101}
6102
6103static void
6104bnx2_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
6105{
972ec0d4 6106 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 6107
6108 strcpy(info->driver, DRV_MODULE_NAME);
6109 strcpy(info->version, DRV_MODULE_VERSION);
6110 strcpy(info->bus_info, pci_name(bp->pdev));
58fc2ea4 6111 strcpy(info->fw_version, bp->fw_version);
b6016b76
MC		 6112}
6113
244ac4f4
MC		 6114#define BNX2_REGDUMP_LEN (32 * 1024)
6115
6116static int
6117bnx2_get_regs_len(struct net_device *dev)
6118{
6119 return BNX2_REGDUMP_LEN;
6120}
6121
6122static void
6123bnx2_get_regs(struct net_device *dev, struct ethtool_regs *regs, void *_p)
6124{
6125 u32 *p = _p, i, offset;
6126 u8 *orig_p = _p;
6127 struct bnx2 *bp = netdev_priv(dev);
6128 u32 reg_boundaries[] = { 0x0000, 0x0098, 0x0400, 0x045c,
6129 0x0800, 0x0880, 0x0c00, 0x0c10,
6130 0x0c30, 0x0d08, 0x1000, 0x101c,
6131 0x1040, 0x1048, 0x1080, 0x10a4,
6132 0x1400, 0x1490, 0x1498, 0x14f0,
6133 0x1500, 0x155c, 0x1580, 0x15dc,
6134 0x1600, 0x1658, 0x1680, 0x16d8,
6135 0x1800, 0x1820, 0x1840, 0x1854,
6136 0x1880, 0x1894, 0x1900, 0x1984,
6137 0x1c00, 0x1c0c, 0x1c40, 0x1c54,
6138 0x1c80, 0x1c94, 0x1d00, 0x1d84,
6139 0x2000, 0x2030, 0x23c0, 0x2400,
6140 0x2800, 0x2820, 0x2830, 0x2850,
6141 0x2b40, 0x2c10, 0x2fc0, 0x3058,
6142 0x3c00, 0x3c94, 0x4000, 0x4010,
6143 0x4080, 0x4090, 0x43c0, 0x4458,
6144 0x4c00, 0x4c18, 0x4c40, 0x4c54,
6145 0x4fc0, 0x5010, 0x53c0, 0x5444,
6146 0x5c00, 0x5c18, 0x5c80, 0x5c90,
6147 0x5fc0, 0x6000, 0x6400, 0x6428,
6148 0x6800, 0x6848, 0x684c, 0x6860,
6149 0x6888, 0x6910, 0x8000 };
6150
6151 regs->version = 0;
6152
6153 memset(p, 0, BNX2_REGDUMP_LEN);
6154
6155 if (!netif_running(bp->dev))
6156 return;
6157
6158 i = 0;
6159 offset = reg_boundaries[0];
6160 p += offset;
6161 while (offset < BNX2_REGDUMP_LEN) {
6162 *p++ = REG_RD(bp, offset);
6163 offset += 4;
6164 if (offset == reg_boundaries[i + 1]) {
6165 offset = reg_boundaries[i + 2];
6166 p = (u32 *) (orig_p + offset);
6167 i += 2;
6168 }
6169 }
6170}
6171
b6016b76
MC		 6172static void
6173bnx2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
6174{
972ec0d4 6175 struct bnx2 *bp = netdev_priv(dev);
b6016b76 6176
f86e82fb 6177 if (bp->flags & BNX2_FLAG_NO_WOL) {
b6016b76
MC		 6178 wol->supported = 0;
6179 wol->wolopts = 0;
6180 }
6181 else {
6182 wol->supported = WAKE_MAGIC;
6183 if (bp->wol)
6184 wol->wolopts = WAKE_MAGIC;
6185 else
6186 wol->wolopts = 0;
6187 }
6188 memset(&wol->sopass, 0, sizeof(wol->sopass));
6189}
6190
6191static int
6192bnx2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
6193{
972ec0d4 6194 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 6195
6196 if (wol->wolopts & ~WAKE_MAGIC)
6197 return -EINVAL;
6198
6199 if (wol->wolopts & WAKE_MAGIC) {
f86e82fb 6200 if (bp->flags & BNX2_FLAG_NO_WOL)
b6016b76
MC		 6201 return -EINVAL;
6202
6203 bp->wol = 1;
6204 }
6205 else {
6206 bp->wol = 0;
6207 }
6208 return 0;
6209}
6210
6211static int
6212bnx2_nway_reset(struct net_device *dev)
6213{
972ec0d4 6214 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 6215 u32 bmcr;
6216
6217 if (!(bp->autoneg & AUTONEG_SPEED)) {
6218 return -EINVAL;
6219 }
6220
c770a65c 6221 spin_lock_bh(&bp->phy_lock);
b6016b76 6222
583c28e5 6223 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) {
7b6b8347
MC		 6224 int rc;
6225
6226 rc = bnx2_setup_remote_phy(bp, bp->phy_port);
6227 spin_unlock_bh(&bp->phy_lock);
6228 return rc;
6229 }
6230
b6016b76 6231 /* Force a link down visible on the other side */
583c28e5 6232 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
ca58c3af 6233 bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK);
c770a65c 6234 spin_unlock_bh(&bp->phy_lock);
b6016b76
MC		 6235
6236 msleep(20);
6237
c770a65c 6238 spin_lock_bh(&bp->phy_lock);
f8dd064e
MC		 6239
6240 bp->current_interval = SERDES_AN_TIMEOUT;
6241 bp->serdes_an_pending = 1;
6242 mod_timer(&bp->timer, jiffies + bp->current_interval);
b6016b76
MC		 6243 }
6244
ca58c3af 6245 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
b6016b76 6246 bmcr &= ~BMCR_LOOPBACK;
ca58c3af 6247 bnx2_write_phy(bp, bp->mii_bmcr, bmcr | BMCR_ANRESTART | BMCR_ANENABLE);
b6016b76 6248
c770a65c 6249 spin_unlock_bh(&bp->phy_lock);
b6016b76
MC		 6250
6251 return 0;
6252}
6253
6254static int
6255bnx2_get_eeprom_len(struct net_device *dev)
6256{
972ec0d4 6257 struct bnx2 *bp = netdev_priv(dev);
b6016b76 6258
1122db71 6259 if (bp->flash_info == NULL)
b6016b76
MC		 6260 return 0;
6261
1122db71 6262 return (int) bp->flash_size;
b6016b76
MC		 6263}
6264
6265static int
6266bnx2_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
6267 u8 *eebuf)
6268{
972ec0d4 6269 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 6270 int rc;
6271
1064e944 6272 /* parameters already validated in ethtool_get_eeprom */
b6016b76
MC		 6273
6274 rc = bnx2_nvram_read(bp, eeprom->offset, eebuf, eeprom->len);
6275
6276 return rc;
6277}
6278
6279static int
6280bnx2_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
6281 u8 *eebuf)
6282{
972ec0d4 6283 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 6284 int rc;
6285
1064e944 6286 /* parameters already validated in ethtool_set_eeprom */
b6016b76
MC		 6287
6288 rc = bnx2_nvram_write(bp, eeprom->offset, eebuf, eeprom->len);
6289
6290 return rc;
6291}
6292
6293static int
6294bnx2_get_coalesce(struct net_device *dev, struct ethtool_coalesce *coal)
6295{
972ec0d4 6296 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 6297
6298 memset(coal, 0, sizeof(struct ethtool_coalesce));
6299
6300 coal->rx_coalesce_usecs = bp->rx_ticks;
6301 coal->rx_max_coalesced_frames = bp->rx_quick_cons_trip;
6302 coal->rx_coalesce_usecs_irq = bp->rx_ticks_int;
6303 coal->rx_max_coalesced_frames_irq = bp->rx_quick_cons_trip_int;
6304
6305 coal->tx_coalesce_usecs = bp->tx_ticks;
6306 coal->tx_max_coalesced_frames = bp->tx_quick_cons_trip;
6307 coal->tx_coalesce_usecs_irq = bp->tx_ticks_int;
6308 coal->tx_max_coalesced_frames_irq = bp->tx_quick_cons_trip_int;
6309
6310 coal->stats_block_coalesce_usecs = bp->stats_ticks;
6311
6312 return 0;
6313}
6314
6315static int
6316bnx2_set_coalesce(struct net_device *dev, struct ethtool_coalesce *coal)
6317{
972ec0d4 6318 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 6319
6320 bp->rx_ticks = (u16) coal->rx_coalesce_usecs;
6321 if (bp->rx_ticks > 0x3ff) bp->rx_ticks = 0x3ff;
6322
6aa20a22 6323 bp->rx_quick_cons_trip = (u16) coal->rx_max_coalesced_frames;
b6016b76
MC		 6324 if (bp->rx_quick_cons_trip > 0xff) bp->rx_quick_cons_trip = 0xff;
6325
6326 bp->rx_ticks_int = (u16) coal->rx_coalesce_usecs_irq;
6327 if (bp->rx_ticks_int > 0x3ff) bp->rx_ticks_int = 0x3ff;
6328
6329 bp->rx_quick_cons_trip_int = (u16) coal->rx_max_coalesced_frames_irq;
6330 if (bp->rx_quick_cons_trip_int > 0xff)
6331 bp->rx_quick_cons_trip_int = 0xff;
6332
6333 bp->tx_ticks = (u16) coal->tx_coalesce_usecs;
6334 if (bp->tx_ticks > 0x3ff) bp->tx_ticks = 0x3ff;
6335
6336 bp->tx_quick_cons_trip = (u16) coal->tx_max_coalesced_frames;
6337 if (bp->tx_quick_cons_trip > 0xff) bp->tx_quick_cons_trip = 0xff;
6338
6339 bp->tx_ticks_int = (u16) coal->tx_coalesce_usecs_irq;
6340 if (bp->tx_ticks_int > 0x3ff) bp->tx_ticks_int = 0x3ff;
6341
6342 bp->tx_quick_cons_trip_int = (u16) coal->tx_max_coalesced_frames_irq;
6343 if (bp->tx_quick_cons_trip_int > 0xff) bp->tx_quick_cons_trip_int =
6344 0xff;
6345
6346 bp->stats_ticks = coal->stats_block_coalesce_usecs;
02537b06
MC		 6347 if (CHIP_NUM(bp) == CHIP_NUM_5708) {
6348 if (bp->stats_ticks != 0 && bp->stats_ticks != USEC_PER_SEC)
6349 bp->stats_ticks = USEC_PER_SEC;
6350 }
7ea6920e
MC		 6351 if (bp->stats_ticks > BNX2_HC_STATS_TICKS_HC_STAT_TICKS)
6352 bp->stats_ticks = BNX2_HC_STATS_TICKS_HC_STAT_TICKS;
6353 bp->stats_ticks &= BNX2_HC_STATS_TICKS_HC_STAT_TICKS;
b6016b76
MC		 6354
6355 if (netif_running(bp->dev)) {
6356 bnx2_netif_stop(bp);
9a120bc5 6357 bnx2_init_nic(bp, 0);
b6016b76
MC		 6358 bnx2_netif_start(bp);
6359 }
6360
6361 return 0;
6362}
6363
6364static void
6365bnx2_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
6366{
972ec0d4 6367 struct bnx2 *bp = netdev_priv(dev);
b6016b76 6368
13daffa2 6369 ering->rx_max_pending = MAX_TOTAL_RX_DESC_CNT;
b6016b76 6370 ering->rx_mini_max_pending = 0;
47bf4246 6371 ering->rx_jumbo_max_pending = MAX_TOTAL_RX_PG_DESC_CNT;
b6016b76
MC		 6372
6373 ering->rx_pending = bp->rx_ring_size;
6374 ering->rx_mini_pending = 0;
47bf4246 6375 ering->rx_jumbo_pending = bp->rx_pg_ring_size;
b6016b76
MC		 6376
6377 ering->tx_max_pending = MAX_TX_DESC_CNT;
6378 ering->tx_pending = bp->tx_ring_size;
6379}
6380
6381static int
5d5d0015 6382bnx2_change_ring_size(struct bnx2 *bp, u32 rx, u32 tx)
b6016b76 6383{
13daffa2
MC		 6384 if (netif_running(bp->dev)) {
6385 bnx2_netif_stop(bp);
6386 bnx2_reset_chip(bp, BNX2_DRV_MSG_CODE_RESET);
6387 bnx2_free_skbs(bp);
6388 bnx2_free_mem(bp);
6389 }
6390
5d5d0015
MC		 6391 bnx2_set_rx_ring_size(bp, rx);
6392 bp->tx_ring_size = tx;
b6016b76
MC		 6393
6394 if (netif_running(bp->dev)) {
13daffa2
MC		 6395 int rc;
6396
6397 rc = bnx2_alloc_mem(bp);
6398 if (rc)
6399 return rc;
9a120bc5 6400 bnx2_init_nic(bp, 0);
b6016b76
MC		 6401 bnx2_netif_start(bp);
6402 }
b6016b76
MC		 6403 return 0;
6404}
6405
5d5d0015
MC		 6406static int
6407bnx2_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
6408{
6409 struct bnx2 *bp = netdev_priv(dev);
6410 int rc;
6411
6412 if ((ering->rx_pending > MAX_TOTAL_RX_DESC_CNT) ||
6413 (ering->tx_pending > MAX_TX_DESC_CNT) ||
6414 (ering->tx_pending <= MAX_SKB_FRAGS)) {
6415
6416 return -EINVAL;
6417 }
6418 rc = bnx2_change_ring_size(bp, ering->rx_pending, ering->tx_pending);
6419 return rc;
6420}
6421
b6016b76
MC		 6422static void
6423bnx2_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
6424{
972ec0d4 6425 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 6426
6427 epause->autoneg = ((bp->autoneg & AUTONEG_FLOW_CTRL) != 0);
6428 epause->rx_pause = ((bp->flow_ctrl & FLOW_CTRL_RX) != 0);
6429 epause->tx_pause = ((bp->flow_ctrl & FLOW_CTRL_TX) != 0);
6430}
6431
6432static int
6433bnx2_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
6434{
972ec0d4 6435 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 6436
6437 bp->req_flow_ctrl = 0;
6438 if (epause->rx_pause)
6439 bp->req_flow_ctrl |= FLOW_CTRL_RX;
6440 if (epause->tx_pause)
6441 bp->req_flow_ctrl |= FLOW_CTRL_TX;
6442
6443 if (epause->autoneg) {
6444 bp->autoneg |= AUTONEG_FLOW_CTRL;
6445 }
6446 else {
6447 bp->autoneg &= ~AUTONEG_FLOW_CTRL;
6448 }
6449
c770a65c 6450 spin_lock_bh(&bp->phy_lock);
b6016b76 6451
0d8a6571 6452 bnx2_setup_phy(bp, bp->phy_port);
b6016b76 6453
c770a65c 6454 spin_unlock_bh(&bp->phy_lock);
b6016b76
MC		 6455
6456 return 0;
6457}
6458
6459static u32
6460bnx2_get_rx_csum(struct net_device *dev)
6461{
972ec0d4 6462 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 6463
6464 return bp->rx_csum;
6465}
6466
6467static int
6468bnx2_set_rx_csum(struct net_device *dev, u32 data)
6469{
972ec0d4 6470 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 6471
6472 bp->rx_csum = data;
6473 return 0;
6474}
6475
b11d6213
MC		 6476static int
6477bnx2_set_tso(struct net_device *dev, u32 data)
6478{
4666f87a
MC		 6479 struct bnx2 *bp = netdev_priv(dev);
6480
6481 if (data) {
b11d6213 6482 dev->features |= NETIF_F_TSO | NETIF_F_TSO_ECN;
4666f87a
MC		 6483 if (CHIP_NUM(bp) == CHIP_NUM_5709)
6484 dev->features |= NETIF_F_TSO6;
6485 } else
6486 dev->features &= ~(NETIF_F_TSO | NETIF_F_TSO6 |
6487 NETIF_F_TSO_ECN);
b11d6213
MC		 6488 return 0;
6489}
6490
cea94db9 6491#define BNX2_NUM_STATS 46
b6016b76 6492
14ab9b86 6493static struct {
b6016b76
MC		 6494 char string[ETH_GSTRING_LEN];
6495} bnx2_stats_str_arr[BNX2_NUM_STATS] = {
6496 { "rx_bytes" },
6497 { "rx_error_bytes" },
6498 { "tx_bytes" },
6499 { "tx_error_bytes" },
6500 { "rx_ucast_packets" },
6501 { "rx_mcast_packets" },
6502 { "rx_bcast_packets" },
6503 { "tx_ucast_packets" },
6504 { "tx_mcast_packets" },
6505 { "tx_bcast_packets" },
6506 { "tx_mac_errors" },
6507 { "tx_carrier_errors" },
6508 { "rx_crc_errors" },
6509 { "rx_align_errors" },
6510 { "tx_single_collisions" },
6511 { "tx_multi_collisions" },
6512 { "tx_deferred" },
6513 { "tx_excess_collisions" },
6514 { "tx_late_collisions" },
6515 { "tx_total_collisions" },
6516 { "rx_fragments" },
6517 { "rx_jabbers" },
6518 { "rx_undersize_packets" },
6519 { "rx_oversize_packets" },
6520 { "rx_64_byte_packets" },
6521 { "rx_65_to_127_byte_packets" },
6522 { "rx_128_to_255_byte_packets" },
6523 { "rx_256_to_511_byte_packets" },
6524 { "rx_512_to_1023_byte_packets" },
6525 { "rx_1024_to_1522_byte_packets" },
6526 { "rx_1523_to_9022_byte_packets" },
6527 { "tx_64_byte_packets" },
6528 { "tx_65_to_127_byte_packets" },
6529 { "tx_128_to_255_byte_packets" },
6530 { "tx_256_to_511_byte_packets" },
6531 { "tx_512_to_1023_byte_packets" },
6532 { "tx_1024_to_1522_byte_packets" },
6533 { "tx_1523_to_9022_byte_packets" },
6534 { "rx_xon_frames" },
6535 { "rx_xoff_frames" },
6536 { "tx_xon_frames" },
6537 { "tx_xoff_frames" },
6538 { "rx_mac_ctrl_frames" },
6539 { "rx_filtered_packets" },
6540 { "rx_discards" },
cea94db9 6541 { "rx_fw_discards" },
b6016b76
MC		 6542};
6543
6544#define STATS_OFFSET32(offset_name) (offsetof(struct statistics_block, offset_name) / 4)
6545
f71e1309 6546static const unsigned long bnx2_stats_offset_arr[BNX2_NUM_STATS] = {
b6016b76
MC		 6547 STATS_OFFSET32(stat_IfHCInOctets_hi),
6548 STATS_OFFSET32(stat_IfHCInBadOctets_hi),
6549 STATS_OFFSET32(stat_IfHCOutOctets_hi),
6550 STATS_OFFSET32(stat_IfHCOutBadOctets_hi),
6551 STATS_OFFSET32(stat_IfHCInUcastPkts_hi),
6552 STATS_OFFSET32(stat_IfHCInMulticastPkts_hi),
6553 STATS_OFFSET32(stat_IfHCInBroadcastPkts_hi),
6554 STATS_OFFSET32(stat_IfHCOutUcastPkts_hi),
6555 STATS_OFFSET32(stat_IfHCOutMulticastPkts_hi),
6556 STATS_OFFSET32(stat_IfHCOutBroadcastPkts_hi),
6557 STATS_OFFSET32(stat_emac_tx_stat_dot3statsinternalmactransmiterrors),
6aa20a22
JG		 6558 STATS_OFFSET32(stat_Dot3StatsCarrierSenseErrors),
6559 STATS_OFFSET32(stat_Dot3StatsFCSErrors),
6560 STATS_OFFSET32(stat_Dot3StatsAlignmentErrors),
6561 STATS_OFFSET32(stat_Dot3StatsSingleCollisionFrames),
6562 STATS_OFFSET32(stat_Dot3StatsMultipleCollisionFrames),
6563 STATS_OFFSET32(stat_Dot3StatsDeferredTransmissions),
6564 STATS_OFFSET32(stat_Dot3StatsExcessiveCollisions),
6565 STATS_OFFSET32(stat_Dot3StatsLateCollisions),
6566 STATS_OFFSET32(stat_EtherStatsCollisions),
6567 STATS_OFFSET32(stat_EtherStatsFragments),
6568 STATS_OFFSET32(stat_EtherStatsJabbers),
6569 STATS_OFFSET32(stat_EtherStatsUndersizePkts),
6570 STATS_OFFSET32(stat_EtherStatsOverrsizePkts),
6571 STATS_OFFSET32(stat_EtherStatsPktsRx64Octets),
6572 STATS_OFFSET32(stat_EtherStatsPktsRx65Octetsto127Octets),
6573 STATS_OFFSET32(stat_EtherStatsPktsRx128Octetsto255Octets),
6574 STATS_OFFSET32(stat_EtherStatsPktsRx256Octetsto511Octets),
6575 STATS_OFFSET32(stat_EtherStatsPktsRx512Octetsto1023Octets),
6576 STATS_OFFSET32(stat_EtherStatsPktsRx1024Octetsto1522Octets),
6577 STATS_OFFSET32(stat_EtherStatsPktsRx1523Octetsto9022Octets),
6578 STATS_OFFSET32(stat_EtherStatsPktsTx64Octets),
6579 STATS_OFFSET32(stat_EtherStatsPktsTx65Octetsto127Octets),
6580 STATS_OFFSET32(stat_EtherStatsPktsTx128Octetsto255Octets),
6581 STATS_OFFSET32(stat_EtherStatsPktsTx256Octetsto511Octets),
6582 STATS_OFFSET32(stat_EtherStatsPktsTx512Octetsto1023Octets),
6583 STATS_OFFSET32(stat_EtherStatsPktsTx1024Octetsto1522Octets),
6584 STATS_OFFSET32(stat_EtherStatsPktsTx1523Octetsto9022Octets),
6585 STATS_OFFSET32(stat_XonPauseFramesReceived),
6586 STATS_OFFSET32(stat_XoffPauseFramesReceived),
6587 STATS_OFFSET32(stat_OutXonSent),
6588 STATS_OFFSET32(stat_OutXoffSent),
6589 STATS_OFFSET32(stat_MacControlFramesReceived),
6590 STATS_OFFSET32(stat_IfInFramesL2FilterDiscards),
6591 STATS_OFFSET32(stat_IfInMBUFDiscards),
cea94db9 6592 STATS_OFFSET32(stat_FwRxDrop),
b6016b76
MC		 6593};
6594
6595/* stat_IfHCInBadOctets and stat_Dot3StatsCarrierSenseErrors are
6596 * skipped because of errata.
6aa20a22 6597 */
14ab9b86 6598static u8 bnx2_5706_stats_len_arr[BNX2_NUM_STATS] = {
b6016b76
MC		 6599 8,0,8,8,8,8,8,8,8,8,
6600 4,0,4,4,4,4,4,4,4,4,
6601 4,4,4,4,4,4,4,4,4,4,
6602 4,4,4,4,4,4,4,4,4,4,
cea94db9 6603 4,4,4,4,4,4,
b6016b76
MC		 6604};
6605
5b0c76ad
MC		 6606static u8 bnx2_5708_stats_len_arr[BNX2_NUM_STATS] = {
6607 8,0,8,8,8,8,8,8,8,8,
6608 4,4,4,4,4,4,4,4,4,4,
6609 4,4,4,4,4,4,4,4,4,4,
6610 4,4,4,4,4,4,4,4,4,4,
cea94db9 6611 4,4,4,4,4,4,
5b0c76ad
MC		 6612};
6613
b6016b76
MC		 6614#define BNX2_NUM_TESTS 6
6615
14ab9b86 6616static struct {
b6016b76
MC		 6617 char string[ETH_GSTRING_LEN];
6618} bnx2_tests_str_arr[BNX2_NUM_TESTS] = {
6619 { "register_test (offline)" },
6620 { "memory_test (offline)" },
6621 { "loopback_test (offline)" },
6622 { "nvram_test (online)" },
6623 { "interrupt_test (online)" },
6624 { "link_test (online)" },
6625};
6626
6627static int
b9f2c044 6628bnx2_get_sset_count(struct net_device *dev, int sset)
b6016b76 6629{
b9f2c044
JG		 6630 switch (sset) {
6631 case ETH_SS_TEST:
6632 return BNX2_NUM_TESTS;
6633 case ETH_SS_STATS:
6634 return BNX2_NUM_STATS;
6635 default:
6636 return -EOPNOTSUPP;
6637 }
b6016b76
MC		 6638}
6639
6640static void
6641bnx2_self_test(struct net_device *dev, struct ethtool_test *etest, u64 *buf)
6642{
972ec0d4 6643 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 6644
6645 memset(buf, 0, sizeof(u64) * BNX2_NUM_TESTS);
6646 if (etest->flags & ETH_TEST_FL_OFFLINE) {
80be4434
MC		 6647 int i;
6648
b6016b76
MC		 6649 bnx2_netif_stop(bp);
6650 bnx2_reset_chip(bp, BNX2_DRV_MSG_CODE_DIAG);
6651 bnx2_free_skbs(bp);
6652
6653 if (bnx2_test_registers(bp) != 0) {
6654 buf[0] = 1;
6655 etest->flags |= ETH_TEST_FL_FAILED;
6656 }
6657 if (bnx2_test_memory(bp) != 0) {
6658 buf[1] = 1;
6659 etest->flags |= ETH_TEST_FL_FAILED;
6660 }
bc5a0690 6661 if ((buf[2] = bnx2_test_loopback(bp)) != 0)
b6016b76 6662 etest->flags |= ETH_TEST_FL_FAILED;
b6016b76
MC		 6663
6664 if (!netif_running(bp->dev)) {
6665 bnx2_reset_chip(bp, BNX2_DRV_MSG_CODE_RESET);
6666 }
6667 else {
9a120bc5 6668 bnx2_init_nic(bp, 1);
b6016b76
MC		 6669 bnx2_netif_start(bp);
6670 }
6671
6672 /* wait for link up */
80be4434
MC		 6673 for (i = 0; i < 7; i++) {
6674 if (bp->link_up)
6675 break;
6676 msleep_interruptible(1000);
6677 }
b6016b76
MC		 6678 }
6679
6680 if (bnx2_test_nvram(bp) != 0) {
6681 buf[3] = 1;
6682 etest->flags |= ETH_TEST_FL_FAILED;
6683 }
6684 if (bnx2_test_intr(bp) != 0) {
6685 buf[4] = 1;
6686 etest->flags |= ETH_TEST_FL_FAILED;
6687 }
6688
6689 if (bnx2_test_link(bp) != 0) {
6690 buf[5] = 1;
6691 etest->flags |= ETH_TEST_FL_FAILED;
6692
6693 }
6694}
6695
6696static void
6697bnx2_get_strings(struct net_device *dev, u32 stringset, u8 *buf)
6698{
6699 switch (stringset) {
6700 case ETH_SS_STATS:
6701 memcpy(buf, bnx2_stats_str_arr,
6702 sizeof(bnx2_stats_str_arr));
6703 break;
6704 case ETH_SS_TEST:
6705 memcpy(buf, bnx2_tests_str_arr,
6706 sizeof(bnx2_tests_str_arr));
6707 break;
6708 }
6709}
6710
b6016b76
MC		 6711static void
6712bnx2_get_ethtool_stats(struct net_device *dev,
6713 struct ethtool_stats *stats, u64 *buf)
6714{
972ec0d4 6715 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 6716 int i;
6717 u32 *hw_stats = (u32 *) bp->stats_blk;
14ab9b86 6718 u8 *stats_len_arr = NULL;
b6016b76
MC		 6719
6720 if (hw_stats == NULL) {
6721 memset(buf, 0, sizeof(u64) * BNX2_NUM_STATS);
6722 return;
6723 }
6724
5b0c76ad
MC		 6725 if ((CHIP_ID(bp) == CHIP_ID_5706_A0) ||
6726 (CHIP_ID(bp) == CHIP_ID_5706_A1) ||
6727 (CHIP_ID(bp) == CHIP_ID_5706_A2) ||
6728 (CHIP_ID(bp) == CHIP_ID_5708_A0))
b6016b76 6729 stats_len_arr = bnx2_5706_stats_len_arr;
5b0c76ad
MC		 6730 else
6731 stats_len_arr = bnx2_5708_stats_len_arr;
b6016b76
MC		 6732
6733 for (i = 0; i < BNX2_NUM_STATS; i++) {
6734 if (stats_len_arr[i] == 0) {
6735 /* skip this counter */
6736 buf[i] = 0;
6737 continue;
6738 }
6739 if (stats_len_arr[i] == 4) {
6740 /* 4-byte counter */
6741 buf[i] = (u64)
6742 *(hw_stats + bnx2_stats_offset_arr[i]);
6743 continue;
6744 }
6745 /* 8-byte counter */
6746 buf[i] = (((u64) *(hw_stats +
6747 bnx2_stats_offset_arr[i])) << 32) +
6748 *(hw_stats + bnx2_stats_offset_arr[i] + 1);
6749 }
6750}
6751
6752static int
6753bnx2_phys_id(struct net_device *dev, u32 data)
6754{
972ec0d4 6755 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 6756 int i;
6757 u32 save;
6758
6759 if (data == 0)
6760 data = 2;
6761
6762 save = REG_RD(bp, BNX2_MISC_CFG);
6763 REG_WR(bp, BNX2_MISC_CFG, BNX2_MISC_CFG_LEDMODE_MAC);
6764
6765 for (i = 0; i < (data * 2); i++) {
6766 if ((i % 2) == 0) {
6767 REG_WR(bp, BNX2_EMAC_LED, BNX2_EMAC_LED_OVERRIDE);
6768 }
6769 else {
6770 REG_WR(bp, BNX2_EMAC_LED, BNX2_EMAC_LED_OVERRIDE |
6771 BNX2_EMAC_LED_1000MB_OVERRIDE |
6772 BNX2_EMAC_LED_100MB_OVERRIDE |
6773 BNX2_EMAC_LED_10MB_OVERRIDE |
6774 BNX2_EMAC_LED_TRAFFIC_OVERRIDE |
6775 BNX2_EMAC_LED_TRAFFIC);
6776 }
6777 msleep_interruptible(500);
6778 if (signal_pending(current))
6779 break;
6780 }
6781 REG_WR(bp, BNX2_EMAC_LED, 0);
6782 REG_WR(bp, BNX2_MISC_CFG, save);
6783 return 0;
6784}
6785
4666f87a
MC		 6786static int
6787bnx2_set_tx_csum(struct net_device *dev, u32 data)
6788{
6789 struct bnx2 *bp = netdev_priv(dev);
6790
6791 if (CHIP_NUM(bp) == CHIP_NUM_5709)
6460d948 6792 return (ethtool_op_set_tx_ipv6_csum(dev, data));
4666f87a
MC		 6793 else
6794 return (ethtool_op_set_tx_csum(dev, data));
6795}
6796
7282d491 6797static const struct ethtool_ops bnx2_ethtool_ops = {
b6016b76
MC		 6798 .get_settings = bnx2_get_settings,
6799 .set_settings = bnx2_set_settings,
6800 .get_drvinfo = bnx2_get_drvinfo,
244ac4f4
MC		 6801 .get_regs_len = bnx2_get_regs_len,
6802 .get_regs = bnx2_get_regs,
b6016b76
MC		 6803 .get_wol = bnx2_get_wol,
6804 .set_wol = bnx2_set_wol,
6805 .nway_reset = bnx2_nway_reset,
6806 .get_link = ethtool_op_get_link,
6807 .get_eeprom_len = bnx2_get_eeprom_len,
6808 .get_eeprom = bnx2_get_eeprom,
6809 .set_eeprom = bnx2_set_eeprom,
6810 .get_coalesce = bnx2_get_coalesce,
6811 .set_coalesce = bnx2_set_coalesce,
6812 .get_ringparam = bnx2_get_ringparam,
6813 .set_ringparam = bnx2_set_ringparam,
6814 .get_pauseparam = bnx2_get_pauseparam,
6815 .set_pauseparam = bnx2_set_pauseparam,
6816 .get_rx_csum = bnx2_get_rx_csum,
6817 .set_rx_csum = bnx2_set_rx_csum,
4666f87a 6818 .set_tx_csum = bnx2_set_tx_csum,
b6016b76 6819 .set_sg = ethtool_op_set_sg,
b11d6213 6820 .set_tso = bnx2_set_tso,
b6016b76
MC		 6821 .self_test = bnx2_self_test,
6822 .get_strings = bnx2_get_strings,
6823 .phys_id = bnx2_phys_id,
b6016b76 6824 .get_ethtool_stats = bnx2_get_ethtool_stats,
b9f2c044 6825 .get_sset_count = bnx2_get_sset_count,
b6016b76
MC		 6826};
6827
6828/* Called with rtnl_lock */
6829static int
6830bnx2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
6831{
14ab9b86 6832 struct mii_ioctl_data *data = if_mii(ifr);
972ec0d4 6833 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 6834 int err;
6835
6836 switch(cmd) {
6837 case SIOCGMIIPHY:
6838 data->phy_id = bp->phy_addr;
6839
6840 /* fallthru */
6841 case SIOCGMIIREG: {
6842 u32 mii_regval;
6843
583c28e5 6844 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
7b6b8347
MC		 6845 return -EOPNOTSUPP;
6846
dad3e452
MC		 6847 if (!netif_running(dev))
6848 return -EAGAIN;
6849
c770a65c 6850 spin_lock_bh(&bp->phy_lock);
b6016b76 6851 err = bnx2_read_phy(bp, data->reg_num & 0x1f, &mii_regval);
c770a65c 6852 spin_unlock_bh(&bp->phy_lock);
b6016b76
MC		 6853
6854 data->val_out = mii_regval;
6855
6856 return err;
6857 }
6858
6859 case SIOCSMIIREG:
6860 if (!capable(CAP_NET_ADMIN))
6861 return -EPERM;
6862
583c28e5 6863 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
7b6b8347
MC		 6864 return -EOPNOTSUPP;
6865
dad3e452
MC		 6866 if (!netif_running(dev))
6867 return -EAGAIN;
6868
c770a65c 6869 spin_lock_bh(&bp->phy_lock);
b6016b76 6870 err = bnx2_write_phy(bp, data->reg_num & 0x1f, data->val_in);
c770a65c 6871 spin_unlock_bh(&bp->phy_lock);
b6016b76
MC		 6872
6873 return err;
6874
6875 default:
6876 /* do nothing */
6877 break;
6878 }
6879 return -EOPNOTSUPP;
6880}
6881
6882/* Called with rtnl_lock */
6883static int
6884bnx2_change_mac_addr(struct net_device *dev, void *p)
6885{
6886 struct sockaddr *addr = p;
972ec0d4 6887 struct bnx2 *bp = netdev_priv(dev);
b6016b76 6888
73eef4cd
MC		 6889 if (!is_valid_ether_addr(addr->sa_data))
6890 return -EINVAL;
6891
b6016b76
MC		 6892 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
6893 if (netif_running(dev))
6894 bnx2_set_mac_addr(bp);
6895
6896 return 0;
6897}
6898
6899/* Called with rtnl_lock */
6900static int
6901bnx2_change_mtu(struct net_device *dev, int new_mtu)
6902{
972ec0d4 6903 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 6904
6905 if (((new_mtu + ETH_HLEN) > MAX_ETHERNET_JUMBO_PACKET_SIZE) ||
6906 ((new_mtu + ETH_HLEN) < MIN_ETHERNET_PACKET_SIZE))
6907 return -EINVAL;
6908
6909 dev->mtu = new_mtu;
5d5d0015 6910 return (bnx2_change_ring_size(bp, bp->rx_ring_size, bp->tx_ring_size));
b6016b76
MC		 6911}
6912
6913#if defined(HAVE_POLL_CONTROLLER) || defined(CONFIG_NET_POLL_CONTROLLER)
6914static void
6915poll_bnx2(struct net_device *dev)
6916{
972ec0d4 6917 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 6918
6919 disable_irq(bp->pdev->irq);
7d12e780 6920 bnx2_interrupt(bp->pdev->irq, dev);
b6016b76
MC		 6921 enable_irq(bp->pdev->irq);
6922}
6923#endif
6924
253c8b75
MC		 6925static void __devinit
6926bnx2_get_5709_media(struct bnx2 *bp)
6927{
6928 u32 val = REG_RD(bp, BNX2_MISC_DUAL_MEDIA_CTRL);
6929 u32 bond_id = val & BNX2_MISC_DUAL_MEDIA_CTRL_BOND_ID;
6930 u32 strap;
6931
6932 if (bond_id == BNX2_MISC_DUAL_MEDIA_CTRL_BOND_ID_C)
6933 return;
6934 else if (bond_id == BNX2_MISC_DUAL_MEDIA_CTRL_BOND_ID_S) {
583c28e5 6935 bp->phy_flags |= BNX2_PHY_FLAG_SERDES;
253c8b75
MC		 6936 return;
6937 }
6938
6939 if (val & BNX2_MISC_DUAL_MEDIA_CTRL_STRAP_OVERRIDE)
6940 strap = (val & BNX2_MISC_DUAL_MEDIA_CTRL_PHY_CTRL) >> 21;
6941 else
6942 strap = (val & BNX2_MISC_DUAL_MEDIA_CTRL_PHY_CTRL_STRAP) >> 8;
6943
6944 if (PCI_FUNC(bp->pdev->devfn) == 0) {
6945 switch (strap) {
6946 case 0x4:
6947 case 0x5:
6948 case 0x6:
583c28e5 6949 bp->phy_flags |= BNX2_PHY_FLAG_SERDES;
253c8b75
MC		 6950 return;
6951 }
6952 } else {
6953 switch (strap) {
6954 case 0x1:
6955 case 0x2:
6956 case 0x4:
583c28e5 6957 bp->phy_flags |= BNX2_PHY_FLAG_SERDES;
253c8b75
MC		 6958 return;
6959 }
6960 }
6961}
6962
883e5151
MC		 6963static void __devinit
6964bnx2_get_pci_speed(struct bnx2 *bp)
6965{
6966 u32 reg;
6967
6968 reg = REG_RD(bp, BNX2_PCICFG_MISC_STATUS);
6969 if (reg & BNX2_PCICFG_MISC_STATUS_PCIX_DET) {
6970 u32 clkreg;
6971
f86e82fb 6972 bp->flags |= BNX2_FLAG_PCIX;
883e5151
MC		 6973
6974 clkreg = REG_RD(bp, BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS);
6975
6976 clkreg &= BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET;
6977 switch (clkreg) {
6978 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ:
6979 bp->bus_speed_mhz = 133;
6980 break;
6981
6982 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ:
6983 bp->bus_speed_mhz = 100;
6984 break;
6985
6986 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ:
6987 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ:
6988 bp->bus_speed_mhz = 66;
6989 break;
6990
6991 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ:
6992 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ:
6993 bp->bus_speed_mhz = 50;
6994 break;
6995
6996 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_LOW:
6997 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ:
6998 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ:
6999 bp->bus_speed_mhz = 33;
7000 break;
7001 }
7002 }
7003 else {
7004 if (reg & BNX2_PCICFG_MISC_STATUS_M66EN)
7005 bp->bus_speed_mhz = 66;
7006 else
7007 bp->bus_speed_mhz = 33;
7008 }
7009
7010 if (reg & BNX2_PCICFG_MISC_STATUS_32BIT_DET)
f86e82fb 7011 bp->flags |= BNX2_FLAG_PCI_32BIT;
883e5151
MC		 7012
7013}
7014
b6016b76
MC		 7015static int __devinit
7016bnx2_init_board(struct pci_dev *pdev, struct net_device *dev)
7017{
7018 struct bnx2 *bp;
7019 unsigned long mem_len;
58fc2ea4 7020 int rc, i, j;
b6016b76 7021 u32 reg;
40453c83 7022 u64 dma_mask, persist_dma_mask;
b6016b76 7023
b6016b76 7024 SET_NETDEV_DEV(dev, &pdev->dev);
972ec0d4 7025 bp = netdev_priv(dev);
b6016b76
MC		 7026
7027 bp->flags = 0;
7028 bp->phy_flags = 0;
7029
7030 /* enable device (incl. PCI PM wakeup), and bus-mastering */
7031 rc = pci_enable_device(pdev);
7032 if (rc) {
898eb71c 7033 dev_err(&pdev->dev, "Cannot enable PCI device, aborting.\n");
b6016b76
MC		 7034 goto err_out;
7035 }
7036
7037 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
9b91cf9d 7038 dev_err(&pdev->dev,
2e8a538d 7039 "Cannot find PCI device base address, aborting.\n");
b6016b76
MC		 7040 rc = -ENODEV;
7041 goto err_out_disable;
7042 }
7043
7044 rc = pci_request_regions(pdev, DRV_MODULE_NAME);
7045 if (rc) {
9b91cf9d 7046 dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting.\n");
b6016b76
MC		 7047 goto err_out_disable;
7048 }
7049
7050 pci_set_master(pdev);
6ff2da49 7051 pci_save_state(pdev);
b6016b76
MC		 7052
7053 bp->pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
7054 if (bp->pm_cap == 0) {
9b91cf9d 7055 dev_err(&pdev->dev,
2e8a538d 7056 "Cannot find power management capability, aborting.\n");
b6016b76
MC		 7057 rc = -EIO;
7058 goto err_out_release;
7059 }
7060
b6016b76
MC		 7061 bp->dev = dev;
7062 bp->pdev = pdev;
7063
7064 spin_lock_init(&bp->phy_lock);
1b8227c4 7065 spin_lock_init(&bp->indirect_lock);
c4028958 7066 INIT_WORK(&bp->reset_task, bnx2_reset_task);
b6016b76
MC		 7067
7068 dev->base_addr = dev->mem_start = pci_resource_start(pdev, 0);
59b47d8a 7069 mem_len = MB_GET_CID_ADDR(TX_TSS_CID + 1);
b6016b76
MC		 7070 dev->mem_end = dev->mem_start + mem_len;
7071 dev->irq = pdev->irq;
7072
7073 bp->regview = ioremap_nocache(dev->base_addr, mem_len);
7074
7075 if (!bp->regview) {
9b91cf9d 7076 dev_err(&pdev->dev, "Cannot map register space, aborting.\n");
b6016b76
MC		 7077 rc = -ENOMEM;
7078 goto err_out_release;
7079 }
7080
7081 /* Configure byte swap and enable write to the reg_window registers.
7082 * Rely on CPU to do target byte swapping on big endian systems
7083 * The chip's target access swapping will not swap all accesses
7084 */
7085 pci_write_config_dword(bp->pdev, BNX2_PCICFG_MISC_CONFIG,
7086 BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
7087 BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP);
7088
829ca9a3 7089 bnx2_set_power_state(bp, PCI_D0);
b6016b76
MC		 7090
7091 bp->chip_id = REG_RD(bp, BNX2_MISC_ID);
7092
883e5151
MC		 7093 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
7094 if (pci_find_capability(pdev, PCI_CAP_ID_EXP) == 0) {
7095 dev_err(&pdev->dev,
7096 "Cannot find PCIE capability, aborting.\n");
7097 rc = -EIO;
7098 goto err_out_unmap;
7099 }
f86e82fb 7100 bp->flags |= BNX2_FLAG_PCIE;
2dd201d7 7101 if (CHIP_REV(bp) == CHIP_REV_Ax)
f86e82fb 7102 bp->flags |= BNX2_FLAG_JUMBO_BROKEN;
883e5151 7103 } else {
59b47d8a
MC		 7104 bp->pcix_cap = pci_find_capability(pdev, PCI_CAP_ID_PCIX);
7105 if (bp->pcix_cap == 0) {
7106 dev_err(&pdev->dev,
7107 "Cannot find PCIX capability, aborting.\n");
7108 rc = -EIO;
7109 goto err_out_unmap;
7110 }
7111 }
7112
b4b36042
MC		 7113 if (CHIP_NUM(bp) == CHIP_NUM_5709 && CHIP_REV(bp) != CHIP_REV_Ax) {
7114 if (pci_find_capability(pdev, PCI_CAP_ID_MSIX))
f86e82fb 7115 bp->flags |= BNX2_FLAG_MSIX_CAP;
b4b36042
MC		 7116 }
7117
8e6a72c4
MC		 7118 if (CHIP_ID(bp) != CHIP_ID_5706_A0 && CHIP_ID(bp) != CHIP_ID_5706_A1) {
7119 if (pci_find_capability(pdev, PCI_CAP_ID_MSI))
f86e82fb 7120 bp->flags |= BNX2_FLAG_MSI_CAP;
8e6a72c4
MC		 7121 }
7122
40453c83
MC		 7123 /* 5708 cannot support DMA addresses > 40-bit. */
7124 if (CHIP_NUM(bp) == CHIP_NUM_5708)
7125 persist_dma_mask = dma_mask = DMA_40BIT_MASK;
7126 else
7127 persist_dma_mask = dma_mask = DMA_64BIT_MASK;
7128
7129 /* Configure DMA attributes. */
7130 if (pci_set_dma_mask(pdev, dma_mask) == 0) {
7131 dev->features |= NETIF_F_HIGHDMA;
7132 rc = pci_set_consistent_dma_mask(pdev, persist_dma_mask);
7133 if (rc) {
7134 dev_err(&pdev->dev,
7135 "pci_set_consistent_dma_mask failed, aborting.\n");
7136 goto err_out_unmap;
7137 }
7138 } else if ((rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK)) != 0) {
7139 dev_err(&pdev->dev, "System does not support DMA, aborting.\n");
7140 goto err_out_unmap;
7141 }
7142
f86e82fb 7143 if (!(bp->flags & BNX2_FLAG_PCIE))
883e5151 7144 bnx2_get_pci_speed(bp);
b6016b76
MC		 7145
7146 /* 5706A0 may falsely detect SERR and PERR. */
7147 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
7148 reg = REG_RD(bp, PCI_COMMAND);
7149 reg &= ~(PCI_COMMAND_SERR | PCI_COMMAND_PARITY);
7150 REG_WR(bp, PCI_COMMAND, reg);
7151 }
7152 else if ((CHIP_ID(bp) == CHIP_ID_5706_A1) &&
f86e82fb 7153 !(bp->flags & BNX2_FLAG_PCIX)) {
b6016b76 7154
9b91cf9d 7155 dev_err(&pdev->dev,
2e8a538d 7156 "5706 A1 can only be used in a PCIX bus, aborting.\n");
b6016b76
MC		 7157 goto err_out_unmap;
7158 }
7159
7160 bnx2_init_nvram(bp);
7161
2726d6e1 7162 reg = bnx2_reg_rd_ind(bp, BNX2_SHM_HDR_SIGNATURE);
e3648b3d
MC		 7163
7164 if ((reg & BNX2_SHM_HDR_SIGNATURE_SIG_MASK) ==
24cb230b
MC		 7165 BNX2_SHM_HDR_SIGNATURE_SIG) {
7166 u32 off = PCI_FUNC(pdev->devfn) << 2;
7167
2726d6e1 7168 bp->shmem_base = bnx2_reg_rd_ind(bp, BNX2_SHM_HDR_ADDR_0 + off);
24cb230b 7169 } else
e3648b3d
MC		 7170 bp->shmem_base = HOST_VIEW_SHMEM_BASE;
7171
b6016b76
MC		 7172 /* Get the permanent MAC address. First we need to make sure the
7173 * firmware is actually running.
7174 */
2726d6e1 7175 reg = bnx2_shmem_rd(bp, BNX2_DEV_INFO_SIGNATURE);
b6016b76
MC		 7176
7177 if ((reg & BNX2_DEV_INFO_SIGNATURE_MAGIC_MASK) !=
7178 BNX2_DEV_INFO_SIGNATURE_MAGIC) {
9b91cf9d 7179 dev_err(&pdev->dev, "Firmware not running, aborting.\n");
b6016b76
MC		 7180 rc = -ENODEV;
7181 goto err_out_unmap;
7182 }
7183
2726d6e1 7184 reg = bnx2_shmem_rd(bp, BNX2_DEV_INFO_BC_REV);
58fc2ea4
MC		 7185 for (i = 0, j = 0; i < 3; i++) {
7186 u8 num, k, skip0;
7187
7188 num = (u8) (reg >> (24 - (i * 8)));
7189 for (k = 100, skip0 = 1; k >= 1; num %= k, k /= 10) {
7190 if (num >= k || !skip0 || k == 1) {
7191 bp->fw_version[j++] = (num / k) + '0';
7192 skip0 = 0;
7193 }
7194 }
7195 if (i != 2)
7196 bp->fw_version[j++] = '.';
7197 }
2726d6e1 7198 reg = bnx2_shmem_rd(bp, BNX2_PORT_FEATURE);
846f5c62
MC		 7199 if (reg & BNX2_PORT_FEATURE_WOL_ENABLED)
7200 bp->wol = 1;
7201
7202 if (reg & BNX2_PORT_FEATURE_ASF_ENABLED) {
f86e82fb 7203 bp->flags |= BNX2_FLAG_ASF_ENABLE;
c2d3db8c
MC		 7204
7205 for (i = 0; i < 30; i++) {
2726d6e1 7206 reg = bnx2_shmem_rd(bp, BNX2_BC_STATE_CONDITION);
c2d3db8c
MC		 7207 if (reg & BNX2_CONDITION_MFW_RUN_MASK)
7208 break;
7209 msleep(10);
7210 }
7211 }
2726d6e1 7212 reg = bnx2_shmem_rd(bp, BNX2_BC_STATE_CONDITION);
58fc2ea4
MC		 7213 reg &= BNX2_CONDITION_MFW_RUN_MASK;
7214 if (reg != BNX2_CONDITION_MFW_RUN_UNKNOWN &&
7215 reg != BNX2_CONDITION_MFW_RUN_NONE) {
7216 int i;
2726d6e1 7217 u32 addr = bnx2_shmem_rd(bp, BNX2_MFW_VER_PTR);
58fc2ea4
MC		 7218
7219 bp->fw_version[j++] = ' ';
7220 for (i = 0; i < 3; i++) {
2726d6e1 7221 reg = bnx2_reg_rd_ind(bp, addr + i * 4);
58fc2ea4
MC		 7222 reg = swab32(reg);
7223 memcpy(&bp->fw_version[j], &reg, 4);
7224 j += 4;
7225 }
7226 }
b6016b76 7227
2726d6e1 7228 reg = bnx2_shmem_rd(bp, BNX2_PORT_HW_CFG_MAC_UPPER);
b6016b76
MC		 7229 bp->mac_addr[0] = (u8) (reg >> 8);
7230 bp->mac_addr[1] = (u8) reg;
7231
2726d6e1 7232 reg = bnx2_shmem_rd(bp, BNX2_PORT_HW_CFG_MAC_LOWER);
b6016b76
MC		 7233 bp->mac_addr[2] = (u8) (reg >> 24);
7234 bp->mac_addr[3] = (u8) (reg >> 16);
7235 bp->mac_addr[4] = (u8) (reg >> 8);
7236 bp->mac_addr[5] = (u8) reg;
7237
7238 bp->tx_ring_size = MAX_TX_DESC_CNT;
932f3772 7239 bnx2_set_rx_ring_size(bp, 255);
b6016b76
MC		 7240
7241 bp->rx_csum = 1;
7242
b6016b76
MC		 7243 bp->tx_quick_cons_trip_int = 20;
7244 bp->tx_quick_cons_trip = 20;
7245 bp->tx_ticks_int = 80;
7246 bp->tx_ticks = 80;
6aa20a22 7247
b6016b76
MC		 7248 bp->rx_quick_cons_trip_int = 6;
7249 bp->rx_quick_cons_trip = 6;
7250 bp->rx_ticks_int = 18;
7251 bp->rx_ticks = 18;
7252
7ea6920e 7253 bp->stats_ticks = USEC_PER_SEC & BNX2_HC_STATS_TICKS_HC_STAT_TICKS;
b6016b76
MC		 7254
7255 bp->timer_interval = HZ;
cd339a0e 7256 bp->current_interval = HZ;
b6016b76 7257
5b0c76ad
MC		 7258 bp->phy_addr = 1;
7259
b6016b76 7260 /* Disable WOL support if we are running on a SERDES chip. */
253c8b75
MC		 7261 if (CHIP_NUM(bp) == CHIP_NUM_5709)
7262 bnx2_get_5709_media(bp);
7263 else if (CHIP_BOND_ID(bp) & CHIP_BOND_ID_SERDES_BIT)
583c28e5 7264 bp->phy_flags |= BNX2_PHY_FLAG_SERDES;
bac0dff6 7265
0d8a6571 7266 bp->phy_port = PORT_TP;
583c28e5 7267 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
0d8a6571 7268 bp->phy_port = PORT_FIBRE;
2726d6e1 7269 reg = bnx2_shmem_rd(bp, BNX2_SHARED_HW_CFG_CONFIG);
846f5c62 7270 if (!(reg & BNX2_SHARED_HW_CFG_GIG_LINK_ON_VAUX)) {
f86e82fb 7271 bp->flags |= BNX2_FLAG_NO_WOL;
846f5c62
MC		 7272 bp->wol = 0;
7273 }
38ea3686
MC		 7274 if (CHIP_NUM(bp) == CHIP_NUM_5706) {
7275 /* Don't do parallel detect on this board because of
7276 * some board problems. The link will not go down
7277 * if we do parallel detect.
7278 */
7279 if (pdev->subsystem_vendor == PCI_VENDOR_ID_HP &&
7280 pdev->subsystem_device == 0x310c)
7281 bp->phy_flags |= BNX2_PHY_FLAG_NO_PARALLEL;
7282 } else {
5b0c76ad 7283 bp->phy_addr = 2;
5b0c76ad 7284 if (reg & BNX2_SHARED_HW_CFG_PHY_2_5G)
583c28e5 7285 bp->phy_flags |= BNX2_PHY_FLAG_2_5G_CAPABLE;
5b0c76ad 7286 }
0d8a6571
MC		 7287 bnx2_init_remote_phy(bp);
7288
261dd5ca
MC		 7289 } else if (CHIP_NUM(bp) == CHIP_NUM_5706 ||
7290 CHIP_NUM(bp) == CHIP_NUM_5708)
583c28e5 7291 bp->phy_flags |= BNX2_PHY_FLAG_CRC_FIX;
fb0c18bd
MC		 7292 else if (CHIP_NUM(bp) == CHIP_NUM_5709 &&
7293 (CHIP_REV(bp) == CHIP_REV_Ax ||
7294 CHIP_REV(bp) == CHIP_REV_Bx))
583c28e5 7295 bp->phy_flags |= BNX2_PHY_FLAG_DIS_EARLY_DAC;
b6016b76 7296
16088272
MC		 7297 if ((CHIP_ID(bp) == CHIP_ID_5708_A0) ||
7298 (CHIP_ID(bp) == CHIP_ID_5708_B0) ||
846f5c62 7299 (CHIP_ID(bp) == CHIP_ID_5708_B1)) {
f86e82fb 7300 bp->flags |= BNX2_FLAG_NO_WOL;
846f5c62
MC		 7301 bp->wol = 0;
7302 }
dda1e390 7303
b6016b76
MC		 7304 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
7305 bp->tx_quick_cons_trip_int =
7306 bp->tx_quick_cons_trip;
7307 bp->tx_ticks_int = bp->tx_ticks;
7308 bp->rx_quick_cons_trip_int =
7309 bp->rx_quick_cons_trip;
7310 bp->rx_ticks_int = bp->rx_ticks;
7311 bp->comp_prod_trip_int = bp->comp_prod_trip;
7312 bp->com_ticks_int = bp->com_ticks;
7313 bp->cmd_ticks_int = bp->cmd_ticks;
7314 }
7315
f9317a40
MC		 7316 /* Disable MSI on 5706 if AMD 8132 bridge is found.
7317 *
7318 * MSI is defined to be 32-bit write. The 5706 does 64-bit MSI writes
7319 * with byte enables disabled on the unused 32-bit word. This is legal
7320 * but causes problems on the AMD 8132 which will eventually stop
7321 * responding after a while.
7322 *
7323 * AMD believes this incompatibility is unique to the 5706, and
88187dfa 7324 * prefers to locally disable MSI rather than globally disabling it.
f9317a40
MC		 7325 */
7326 if (CHIP_NUM(bp) == CHIP_NUM_5706 && disable_msi == 0) {
7327 struct pci_dev *amd_8132 = NULL;
7328
7329 while ((amd_8132 = pci_get_device(PCI_VENDOR_ID_AMD,
7330 PCI_DEVICE_ID_AMD_8132_BRIDGE,
7331 amd_8132))) {
f9317a40 7332
44c10138
AK		 7333 if (amd_8132->revision >= 0x10 &&
7334 amd_8132->revision <= 0x13) {
f9317a40
MC		 7335 disable_msi = 1;
7336 pci_dev_put(amd_8132);
7337 break;
7338 }
7339 }
7340 }
7341
deaf391b 7342 bnx2_set_default_link(bp);
b6016b76
MC		 7343 bp->req_flow_ctrl = FLOW_CTRL_RX | FLOW_CTRL_TX;
7344
cd339a0e
MC		 7345 init_timer(&bp->timer);
7346 bp->timer.expires = RUN_AT(bp->timer_interval);
7347 bp->timer.data = (unsigned long) bp;
7348 bp->timer.function = bnx2_timer;
7349
b6016b76
MC		 7350 return 0;
7351
7352err_out_unmap:
7353 if (bp->regview) {
7354 iounmap(bp->regview);
73eef4cd 7355 bp->regview = NULL;
b6016b76
MC		 7356 }
7357
7358err_out_release:
7359 pci_release_regions(pdev);
7360
7361err_out_disable:
7362 pci_disable_device(pdev);
7363 pci_set_drvdata(pdev, NULL);
7364
7365err_out:
7366 return rc;
7367}
7368
883e5151
MC		 7369static char * __devinit
7370bnx2_bus_string(struct bnx2 *bp, char *str)
7371{
7372 char *s = str;
7373
f86e82fb 7374 if (bp->flags & BNX2_FLAG_PCIE) {
883e5151
MC		 7375 s += sprintf(s, "PCI Express");
7376 } else {
7377 s += sprintf(s, "PCI");
f86e82fb 7378 if (bp->flags & BNX2_FLAG_PCIX)
883e5151 7379 s += sprintf(s, "-X");
f86e82fb 7380 if (bp->flags & BNX2_FLAG_PCI_32BIT)
883e5151
MC		 7381 s += sprintf(s, " 32-bit");
7382 else
7383 s += sprintf(s, " 64-bit");
7384 s += sprintf(s, " %dMHz", bp->bus_speed_mhz);
7385 }
7386 return str;
7387}
7388
2ba582b7 7389static void __devinit
35efa7c1
MC		 7390bnx2_init_napi(struct bnx2 *bp)
7391{
b4b36042
MC		 7392 int i;
7393 struct bnx2_napi *bnapi;
35efa7c1 7394
b4b36042
MC		 7395 for (i = 0; i < BNX2_MAX_MSIX_VEC; i++) {
7396 bnapi = &bp->bnx2_napi[i];
7397 bnapi->bp = bp;
7398 }
7399 netif_napi_add(bp->dev, &bp->bnx2_napi[0].napi, bnx2_poll, 64);
57851d84
MC		 7400 netif_napi_add(bp->dev, &bp->bnx2_napi[BNX2_TX_VEC].napi, bnx2_tx_poll,
7401 64);
35efa7c1
MC		 7402}
7403
b6016b76
MC		 7404static int __devinit
7405bnx2_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
7406{
7407 static int version_printed = 0;
7408 struct net_device *dev = NULL;
7409 struct bnx2 *bp;
0795af57 7410 int rc;
883e5151 7411 char str[40];
0795af57 7412 DECLARE_MAC_BUF(mac);
b6016b76
MC		 7413
7414 if (version_printed++ == 0)
7415 printk(KERN_INFO "%s", version);
7416
7417 /* dev zeroed in init_etherdev */
7418 dev = alloc_etherdev(sizeof(*bp));
7419
7420 if (!dev)
7421 return -ENOMEM;
7422
7423 rc = bnx2_init_board(pdev, dev);
7424 if (rc < 0) {
7425 free_netdev(dev);
7426 return rc;
7427 }
7428
7429 dev->open = bnx2_open;
7430 dev->hard_start_xmit = bnx2_start_xmit;
7431 dev->stop = bnx2_close;
7432 dev->get_stats = bnx2_get_stats;
7433 dev->set_multicast_list = bnx2_set_rx_mode;
7434 dev->do_ioctl = bnx2_ioctl;
7435 dev->set_mac_address = bnx2_change_mac_addr;
7436 dev->change_mtu = bnx2_change_mtu;
7437 dev->tx_timeout = bnx2_tx_timeout;
7438 dev->watchdog_timeo = TX_TIMEOUT;
7439#ifdef BCM_VLAN
7440 dev->vlan_rx_register = bnx2_vlan_rx_register;
b6016b76 7441#endif
b6016b76 7442 dev->ethtool_ops = &bnx2_ethtool_ops;
b6016b76 7443
972ec0d4 7444 bp = netdev_priv(dev);
35efa7c1 7445 bnx2_init_napi(bp);
b6016b76
MC		 7446
7447#if defined(HAVE_POLL_CONTROLLER) || defined(CONFIG_NET_POLL_CONTROLLER)
7448 dev->poll_controller = poll_bnx2;
7449#endif
7450
1b2f922f
MC		 7451 pci_set_drvdata(pdev, dev);
7452
7453 memcpy(dev->dev_addr, bp->mac_addr, 6);
7454 memcpy(dev->perm_addr, bp->mac_addr, 6);
7455 bp->name = board_info[ent->driver_data].name;
7456
d212f87b 7457 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
4666f87a 7458 if (CHIP_NUM(bp) == CHIP_NUM_5709)
d212f87b
SH		 7459 dev->features |= NETIF_F_IPV6_CSUM;
7460
1b2f922f
MC		 7461#ifdef BCM_VLAN
7462 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
7463#endif
7464 dev->features |= NETIF_F_TSO | NETIF_F_TSO_ECN;
4666f87a
MC		 7465 if (CHIP_NUM(bp) == CHIP_NUM_5709)
7466 dev->features |= NETIF_F_TSO6;
1b2f922f 7467
b6016b76 7468 if ((rc = register_netdev(dev))) {
9b91cf9d 7469 dev_err(&pdev->dev, "Cannot register net device\n");
b6016b76
MC		 7470 if (bp->regview)
7471 iounmap(bp->regview);
7472 pci_release_regions(pdev);
7473 pci_disable_device(pdev);
7474 pci_set_drvdata(pdev, NULL);
7475 free_netdev(dev);
7476 return rc;
7477 }
7478
883e5151 7479 printk(KERN_INFO "%s: %s (%c%d) %s found at mem %lx, "
0795af57 7480 "IRQ %d, node addr %s\n",
b6016b76
MC		 7481 dev->name,
7482 bp->name,
7483 ((CHIP_ID(bp) & 0xf000) >> 12) + 'A',
7484 ((CHIP_ID(bp) & 0x0ff0) >> 4),
883e5151 7485 bnx2_bus_string(bp, str),
b6016b76 7486 dev->base_addr,
0795af57 7487 bp->pdev->irq, print_mac(mac, dev->dev_addr));
b6016b76 7488
b6016b76
MC		 7489 return 0;
7490}
7491
7492static void __devexit
7493bnx2_remove_one(struct pci_dev *pdev)
7494{
7495 struct net_device *dev = pci_get_drvdata(pdev);
972ec0d4 7496 struct bnx2 *bp = netdev_priv(dev);
b6016b76 7497
afdc08b9
MC		 7498 flush_scheduled_work();
7499
b6016b76
MC		 7500 unregister_netdev(dev);
7501
7502 if (bp->regview)
7503 iounmap(bp->regview);
7504
7505 free_netdev(dev);
7506 pci_release_regions(pdev);
7507 pci_disable_device(pdev);
7508 pci_set_drvdata(pdev, NULL);
7509}
7510
7511static int
829ca9a3 7512bnx2_suspend(struct pci_dev *pdev, pm_message_t state)
b6016b76
MC		 7513{
7514 struct net_device *dev = pci_get_drvdata(pdev);
972ec0d4 7515 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 7516 u32 reset_code;
7517
6caebb02
MC		 7518 /* PCI register 4 needs to be saved whether netif_running() or not.
7519 * MSI address and data need to be saved if using MSI and
7520 * netif_running().
7521 */
7522 pci_save_state(pdev);
b6016b76
MC		 7523 if (!netif_running(dev))
7524 return 0;
7525
1d60290f 7526 flush_scheduled_work();
b6016b76
MC		 7527 bnx2_netif_stop(bp);
7528 netif_device_detach(dev);
7529 del_timer_sync(&bp->timer);
f86e82fb 7530 if (bp->flags & BNX2_FLAG_NO_WOL)
6c4f095e 7531 reset_code = BNX2_DRV_MSG_CODE_UNLOAD_LNK_DN;
dda1e390 7532 else if (bp->wol)
b6016b76
MC		 7533 reset_code = BNX2_DRV_MSG_CODE_SUSPEND_WOL;
7534 else
7535 reset_code = BNX2_DRV_MSG_CODE_SUSPEND_NO_WOL;
7536 bnx2_reset_chip(bp, reset_code);
7537 bnx2_free_skbs(bp);
829ca9a3 7538 bnx2_set_power_state(bp, pci_choose_state(pdev, state));
b6016b76
MC		 7539 return 0;
7540}
7541
7542static int
7543bnx2_resume(struct pci_dev *pdev)
7544{
7545 struct net_device *dev = pci_get_drvdata(pdev);
972ec0d4 7546 struct bnx2 *bp = netdev_priv(dev);
b6016b76 7547
6caebb02 7548 pci_restore_state(pdev);
b6016b76
MC		 7549 if (!netif_running(dev))
7550 return 0;
7551
829ca9a3 7552 bnx2_set_power_state(bp, PCI_D0);
b6016b76 7553 netif_device_attach(dev);
9a120bc5 7554 bnx2_init_nic(bp, 1);
b6016b76
MC		 7555 bnx2_netif_start(bp);
7556 return 0;
7557}
7558
6ff2da49
WX		 7559/**
7560 * bnx2_io_error_detected - called when PCI error is detected
7561 * @pdev: Pointer to PCI device
7562 * @state: The current pci connection state
7563 *
7564 * This function is called after a PCI bus error affecting
7565 * this device has been detected.
7566 */
7567static pci_ers_result_t bnx2_io_error_detected(struct pci_dev *pdev,
7568 pci_channel_state_t state)
7569{
7570 struct net_device *dev = pci_get_drvdata(pdev);
7571 struct bnx2 *bp = netdev_priv(dev);
7572
7573 rtnl_lock();
7574 netif_device_detach(dev);
7575
7576 if (netif_running(dev)) {
7577 bnx2_netif_stop(bp);
7578 del_timer_sync(&bp->timer);
7579 bnx2_reset_nic(bp, BNX2_DRV_MSG_CODE_RESET);
7580 }
7581
7582 pci_disable_device(pdev);
7583 rtnl_unlock();
7584
7585 /* Request a slot slot reset. */
7586 return PCI_ERS_RESULT_NEED_RESET;
7587}
7588
7589/**
7590 * bnx2_io_slot_reset - called after the pci bus has been reset.
7591 * @pdev: Pointer to PCI device
7592 *
7593 * Restart the card from scratch, as if from a cold-boot.
7594 */
7595static pci_ers_result_t bnx2_io_slot_reset(struct pci_dev *pdev)
7596{
7597 struct net_device *dev = pci_get_drvdata(pdev);
7598 struct bnx2 *bp = netdev_priv(dev);
7599
7600 rtnl_lock();
7601 if (pci_enable_device(pdev)) {
7602 dev_err(&pdev->dev,
7603 "Cannot re-enable PCI device after reset.\n");
7604 rtnl_unlock();
7605 return PCI_ERS_RESULT_DISCONNECT;
7606 }
7607 pci_set_master(pdev);
7608 pci_restore_state(pdev);
7609
7610 if (netif_running(dev)) {
7611 bnx2_set_power_state(bp, PCI_D0);
7612 bnx2_init_nic(bp, 1);
7613 }
7614
7615 rtnl_unlock();
7616 return PCI_ERS_RESULT_RECOVERED;
7617}
7618
7619/**
7620 * bnx2_io_resume - called when traffic can start flowing again.
7621 * @pdev: Pointer to PCI device
7622 *
7623 * This callback is called when the error recovery driver tells us that
7624 * its OK to resume normal operation.
7625 */
7626static void bnx2_io_resume(struct pci_dev *pdev)
7627{
7628 struct net_device *dev = pci_get_drvdata(pdev);
7629 struct bnx2 *bp = netdev_priv(dev);
7630
7631 rtnl_lock();
7632 if (netif_running(dev))
7633 bnx2_netif_start(bp);
7634
7635 netif_device_attach(dev);
7636 rtnl_unlock();
7637}
7638
7639static struct pci_error_handlers bnx2_err_handler = {
7640 .error_detected = bnx2_io_error_detected,
7641 .slot_reset = bnx2_io_slot_reset,
7642 .resume = bnx2_io_resume,
7643};
7644
b6016b76 7645static struct pci_driver bnx2_pci_driver = {
14ab9b86
PH		 7646 .name = DRV_MODULE_NAME,
7647 .id_table = bnx2_pci_tbl,
7648 .probe = bnx2_init_one,
7649 .remove = __devexit_p(bnx2_remove_one),
7650 .suspend = bnx2_suspend,
7651 .resume = bnx2_resume,
6ff2da49 7652 .err_handler = &bnx2_err_handler,
b6016b76
MC		 7653};
7654
7655static int __init bnx2_init(void)
7656{
29917620 7657 return pci_register_driver(&bnx2_pci_driver);
b6016b76
MC		 7658}
7659
7660static void __exit bnx2_cleanup(void)
7661{
7662 pci_unregister_driver(&bnx2_pci_driver);
7663}
7664
7665module_init(bnx2_init);
7666module_exit(bnx2_cleanup);
7667
7668
7669
Linux kernel - Deliverables
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