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irda: Add irda_skb_cb qdisc related padding
[deliverable/linux.git] / drivers / net / bnx2.c
CommitLineData
b6016b76
MC		 1/* bnx2.c: Broadcom NX2 network driver.
2 *
feebb331 3 * Copyright (c) 2004-2008 Broadcom Corporation
b6016b76
MC		 4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
8 *
9 * Written by: Michael Chan (mchan@broadcom.com)
10 */
11
f2a4f052
MC		 12
13#include <linux/module.h>
14#include <linux/moduleparam.h>
15
16#include <linux/kernel.h>
17#include <linux/timer.h>
18#include <linux/errno.h>
19#include <linux/ioport.h>
20#include <linux/slab.h>
21#include <linux/vmalloc.h>
22#include <linux/interrupt.h>
23#include <linux/pci.h>
24#include <linux/init.h>
25#include <linux/netdevice.h>
26#include <linux/etherdevice.h>
27#include <linux/skbuff.h>
28#include <linux/dma-mapping.h>
1977f032 29#include <linux/bitops.h>
f2a4f052
MC		 30#include <asm/io.h>
31#include <asm/irq.h>
32#include <linux/delay.h>
33#include <asm/byteorder.h>
c86a31f4 34#include <asm/page.h>
f2a4f052
MC		 35#include <linux/time.h>
36#include <linux/ethtool.h>
37#include <linux/mii.h>
f2a4f052 38#include <linux/if_vlan.h>
08013fa3 39#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
f2a4f052
MC		 40#define BCM_VLAN 1
41#endif
f2a4f052 42#include <net/ip.h>
de081fa5 43#include <net/tcp.h>
f2a4f052 44#include <net/checksum.h>
f2a4f052
MC		 45#include <linux/workqueue.h>
46#include <linux/crc32.h>
47#include <linux/prefetch.h>
29b12174 48#include <linux/cache.h>
fba9fe91 49#include <linux/zlib.h>
706bf240 50#include <linux/log2.h>
f2a4f052 51
b6016b76
MC		 52#include "bnx2.h"
53#include "bnx2_fw.h"
d43584c8 54#include "bnx2_fw2.h"
b6016b76 55
110d0ef9 56#define FW_BUF_SIZE 0x10000
b3448b0b 57
b6016b76
MC		 58#define DRV_MODULE_NAME "bnx2"
59#define PFX DRV_MODULE_NAME ": "
ec7e6fab
MC		 60#define DRV_MODULE_VERSION "1.8.1"
61#define DRV_MODULE_RELDATE "Oct 7, 2008"
b6016b76
MC		 62
63#define RUN_AT(x) (jiffies + (x))
64
65/* Time in jiffies before concluding the transmitter is hung. */
66#define TX_TIMEOUT (5*HZ)
67
fefa8645 68static char version[] __devinitdata =
b6016b76
MC		 69 "Broadcom NetXtreme II Gigabit Ethernet Driver " DRV_MODULE_NAME " v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
70
71MODULE_AUTHOR("Michael Chan <mchan@broadcom.com>");
453a9c6e 72MODULE_DESCRIPTION("Broadcom NetXtreme II BCM5706/5708/5709/5716 Driver");
b6016b76
MC		 73MODULE_LICENSE("GPL");
74MODULE_VERSION(DRV_MODULE_VERSION);
75
76static int disable_msi = 0;
77
78module_param(disable_msi, int, 0);
79MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)");
80
81typedef enum {
82 BCM5706 = 0,
83 NC370T,
84 NC370I,
85 BCM5706S,
86 NC370F,
5b0c76ad
MC		 87 BCM5708,
88 BCM5708S,
bac0dff6 89 BCM5709,
27a005b8 90 BCM5709S,
7bb0a04f 91 BCM5716,
b6016b76
MC		 92} board_t;
93
94/* indexed by board_t, above */
fefa8645 95static struct {
b6016b76
MC		 96 char *name;
97} board_info[] __devinitdata = {
98 { "Broadcom NetXtreme II BCM5706 1000Base-T" },
99 { "HP NC370T Multifunction Gigabit Server Adapter" },
100 { "HP NC370i Multifunction Gigabit Server Adapter" },
101 { "Broadcom NetXtreme II BCM5706 1000Base-SX" },
102 { "HP NC370F Multifunction Gigabit Server Adapter" },
5b0c76ad
MC		 103 { "Broadcom NetXtreme II BCM5708 1000Base-T" },
104 { "Broadcom NetXtreme II BCM5708 1000Base-SX" },
bac0dff6 105 { "Broadcom NetXtreme II BCM5709 1000Base-T" },
27a005b8 106 { "Broadcom NetXtreme II BCM5709 1000Base-SX" },
7bb0a04f 107 { "Broadcom NetXtreme II BCM5716 1000Base-T" },
b6016b76
MC		 108 };
109
7bb0a04f 110static DEFINE_PCI_DEVICE_TABLE(bnx2_pci_tbl) = {
b6016b76
MC		 111 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706,
112 PCI_VENDOR_ID_HP, 0x3101, 0, 0, NC370T },
113 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706,
114 PCI_VENDOR_ID_HP, 0x3106, 0, 0, NC370I },
115 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706,
116 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5706 },
5b0c76ad
MC		 117 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5708,
118 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5708 },
b6016b76
MC		 119 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706S,
120 PCI_VENDOR_ID_HP, 0x3102, 0, 0, NC370F },
121 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706S,
122 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5706S },
5b0c76ad
MC		 123 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5708S,
124 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5708S },
bac0dff6
MC		 125 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5709,
126 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5709 },
27a005b8
MC		 127 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5709S,
128 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5709S },
7bb0a04f
MC		 129 { PCI_VENDOR_ID_BROADCOM, 0x163b,
130 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5716 },
b6016b76
MC		 131 { 0, }
132};
133
134static struct flash_spec flash_table[] =
135{
e30372c9
MC		 136#define BUFFERED_FLAGS (BNX2_NV_BUFFERED | BNX2_NV_TRANSLATE)
137#define NONBUFFERED_FLAGS (BNX2_NV_WREN)
b6016b76 138 /* Slow EEPROM */
37137709 139 {0x00000000, 0x40830380, 0x009f0081, 0xa184a053, 0xaf000400,
e30372c9 140 BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE,
b6016b76
MC		 141 SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE,
142 "EEPROM - slow"},
37137709
MC		 143 /* Expansion entry 0001 */
144 {0x08000002, 0x4b808201, 0x00050081, 0x03840253, 0xaf020406,
e30372c9 145 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
37137709
MC		 146 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
147 "Entry 0001"},
b6016b76
MC		 148 /* Saifun SA25F010 (non-buffered flash) */
149 /* strap, cfg1, & write1 need updates */
37137709 150 {0x04000001, 0x47808201, 0x00050081, 0x03840253, 0xaf020406,
e30372c9 151 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
b6016b76
MC		 152 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*2,
153 "Non-buffered flash (128kB)"},
154 /* Saifun SA25F020 (non-buffered flash) */
155 /* strap, cfg1, & write1 need updates */
37137709 156 {0x0c000003, 0x4f808201, 0x00050081, 0x03840253, 0xaf020406,
e30372c9 157 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
b6016b76
MC		 158 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*4,
159 "Non-buffered flash (256kB)"},
37137709
MC		 160 /* Expansion entry 0100 */
161 {0x11000000, 0x53808201, 0x00050081, 0x03840253, 0xaf020406,
e30372c9 162 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
37137709
MC		 163 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
164 "Entry 0100"},
165 /* Entry 0101: ST M45PE10 (non-buffered flash, TetonII B0) */
6aa20a22 166 {0x19000002, 0x5b808201, 0x000500db, 0x03840253, 0xaf020406,
e30372c9 167 NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE,
37137709
MC		 168 ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*2,
169 "Entry 0101: ST M45PE10 (128kB non-bufferred)"},
170 /* Entry 0110: ST M45PE20 (non-buffered flash)*/
171 {0x15000001, 0x57808201, 0x000500db, 0x03840253, 0xaf020406,
e30372c9 172 NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE,
37137709
MC		 173 ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*4,
174 "Entry 0110: ST M45PE20 (256kB non-bufferred)"},
175 /* Saifun SA25F005 (non-buffered flash) */
176 /* strap, cfg1, & write1 need updates */
177 {0x1d000003, 0x5f808201, 0x00050081, 0x03840253, 0xaf020406,
e30372c9 178 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
37137709
MC		 179 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE,
180 "Non-buffered flash (64kB)"},
181 /* Fast EEPROM */
182 {0x22000000, 0x62808380, 0x009f0081, 0xa184a053, 0xaf000400,
e30372c9 183 BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE,
37137709
MC		 184 SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE,
185 "EEPROM - fast"},
186 /* Expansion entry 1001 */
187 {0x2a000002, 0x6b808201, 0x00050081, 0x03840253, 0xaf020406,
e30372c9 188 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
37137709
MC		 189 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
190 "Entry 1001"},
191 /* Expansion entry 1010 */
192 {0x26000001, 0x67808201, 0x00050081, 0x03840253, 0xaf020406,
e30372c9 193 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
37137709
MC		 194 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
195 "Entry 1010"},
196 /* ATMEL AT45DB011B (buffered flash) */
197 {0x2e000003, 0x6e808273, 0x00570081, 0x68848353, 0xaf000400,
e30372c9 198 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
37137709
MC		 199 BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE,
200 "Buffered flash (128kB)"},
201 /* Expansion entry 1100 */
202 {0x33000000, 0x73808201, 0x00050081, 0x03840253, 0xaf020406,
e30372c9 203 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
37137709
MC		 204 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
205 "Entry 1100"},
206 /* Expansion entry 1101 */
207 {0x3b000002, 0x7b808201, 0x00050081, 0x03840253, 0xaf020406,
e30372c9 208 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
37137709
MC		 209 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
210 "Entry 1101"},
211 /* Ateml Expansion entry 1110 */
212 {0x37000001, 0x76808273, 0x00570081, 0x68848353, 0xaf000400,
e30372c9 213 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
37137709
MC		 214 BUFFERED_FLASH_BYTE_ADDR_MASK, 0,
215 "Entry 1110 (Atmel)"},
216 /* ATMEL AT45DB021B (buffered flash) */
217 {0x3f000003, 0x7e808273, 0x00570081, 0x68848353, 0xaf000400,
e30372c9 218 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
37137709
MC		 219 BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE*2,
220 "Buffered flash (256kB)"},
b6016b76
MC		 221};
222
e30372c9
MC		 223static struct flash_spec flash_5709 = {
224 .flags = BNX2_NV_BUFFERED,
225 .page_bits = BCM5709_FLASH_PAGE_BITS,
226 .page_size = BCM5709_FLASH_PAGE_SIZE,
227 .addr_mask = BCM5709_FLASH_BYTE_ADDR_MASK,
228 .total_size = BUFFERED_FLASH_TOTAL_SIZE*2,
229 .name = "5709 Buffered flash (256kB)",
230};
231
b6016b76
MC		 232MODULE_DEVICE_TABLE(pci, bnx2_pci_tbl);
233
35e9010b 234static inline u32 bnx2_tx_avail(struct bnx2 *bp, struct bnx2_tx_ring_info *txr)
e89bbf10 235{
2f8af120 236 u32 diff;
e89bbf10 237
2f8af120 238 smp_mb();
faac9c4b
MC		 239
240 /* The ring uses 256 indices for 255 entries, one of them
241 * needs to be skipped.
242 */
35e9010b 243 diff = txr->tx_prod - txr->tx_cons;
faac9c4b
MC		 244 if (unlikely(diff >= TX_DESC_CNT)) {
245 diff &= 0xffff;
246 if (diff == TX_DESC_CNT)
247 diff = MAX_TX_DESC_CNT;
248 }
e89bbf10
MC		 249 return (bp->tx_ring_size - diff);
250}
251
b6016b76
MC		 252static u32
253bnx2_reg_rd_ind(struct bnx2 *bp, u32 offset)
254{
1b8227c4
MC		 255 u32 val;
256
257 spin_lock_bh(&bp->indirect_lock);
b6016b76 258 REG_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, offset);
1b8227c4
MC		 259 val = REG_RD(bp, BNX2_PCICFG_REG_WINDOW);
260 spin_unlock_bh(&bp->indirect_lock);
261 return val;
b6016b76
MC		 262}
263
264static void
265bnx2_reg_wr_ind(struct bnx2 *bp, u32 offset, u32 val)
266{
1b8227c4 267 spin_lock_bh(&bp->indirect_lock);
b6016b76
MC		 268 REG_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, offset);
269 REG_WR(bp, BNX2_PCICFG_REG_WINDOW, val);
1b8227c4 270 spin_unlock_bh(&bp->indirect_lock);
b6016b76
MC		 271}
272
2726d6e1
MC		 273static void
274bnx2_shmem_wr(struct bnx2 *bp, u32 offset, u32 val)
275{
276 bnx2_reg_wr_ind(bp, bp->shmem_base + offset, val);
277}
278
279static u32
280bnx2_shmem_rd(struct bnx2 *bp, u32 offset)
281{
282 return (bnx2_reg_rd_ind(bp, bp->shmem_base + offset));
283}
284
b6016b76
MC		 285static void
286bnx2_ctx_wr(struct bnx2 *bp, u32 cid_addr, u32 offset, u32 val)
287{
288 offset += cid_addr;
1b8227c4 289 spin_lock_bh(&bp->indirect_lock);
59b47d8a
MC		 290 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
291 int i;
292
293 REG_WR(bp, BNX2_CTX_CTX_DATA, val);
294 REG_WR(bp, BNX2_CTX_CTX_CTRL,
295 offset | BNX2_CTX_CTX_CTRL_WRITE_REQ);
296 for (i = 0; i < 5; i++) {
59b47d8a
MC		 297 val = REG_RD(bp, BNX2_CTX_CTX_CTRL);
298 if ((val & BNX2_CTX_CTX_CTRL_WRITE_REQ) == 0)
299 break;
300 udelay(5);
301 }
302 } else {
303 REG_WR(bp, BNX2_CTX_DATA_ADR, offset);
304 REG_WR(bp, BNX2_CTX_DATA, val);
305 }
1b8227c4 306 spin_unlock_bh(&bp->indirect_lock);
b6016b76
MC		 307}
308
309static int
310bnx2_read_phy(struct bnx2 *bp, u32 reg, u32 *val)
311{
312 u32 val1;
313 int i, ret;
314
583c28e5 315 if (bp->phy_flags & BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING) {
b6016b76
MC		 316 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
317 val1 &= ~BNX2_EMAC_MDIO_MODE_AUTO_POLL;
318
319 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
320 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
321
322 udelay(40);
323 }
324
325 val1 = (bp->phy_addr << 21) | (reg << 16) |
326 BNX2_EMAC_MDIO_COMM_COMMAND_READ | BNX2_EMAC_MDIO_COMM_DISEXT |
327 BNX2_EMAC_MDIO_COMM_START_BUSY;
328 REG_WR(bp, BNX2_EMAC_MDIO_COMM, val1);
329
330 for (i = 0; i < 50; i++) {
331 udelay(10);
332
333 val1 = REG_RD(bp, BNX2_EMAC_MDIO_COMM);
334 if (!(val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)) {
335 udelay(5);
336
337 val1 = REG_RD(bp, BNX2_EMAC_MDIO_COMM);
338 val1 &= BNX2_EMAC_MDIO_COMM_DATA;
339
340 break;
341 }
342 }
343
344 if (val1 & BNX2_EMAC_MDIO_COMM_START_BUSY) {
345 *val = 0x0;
346 ret = -EBUSY;
347 }
348 else {
349 *val = val1;
350 ret = 0;
351 }
352
583c28e5 353 if (bp->phy_flags & BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING) {
b6016b76
MC		 354 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
355 val1 |= BNX2_EMAC_MDIO_MODE_AUTO_POLL;
356
357 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
358 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
359
360 udelay(40);
361 }
362
363 return ret;
364}
365
366static int
367bnx2_write_phy(struct bnx2 *bp, u32 reg, u32 val)
368{
369 u32 val1;
370 int i, ret;
371
583c28e5 372 if (bp->phy_flags & BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING) {
b6016b76
MC		 373 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
374 val1 &= ~BNX2_EMAC_MDIO_MODE_AUTO_POLL;
375
376 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
377 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
378
379 udelay(40);
380 }
381
382 val1 = (bp->phy_addr << 21) | (reg << 16) | val |
383 BNX2_EMAC_MDIO_COMM_COMMAND_WRITE |
384 BNX2_EMAC_MDIO_COMM_START_BUSY | BNX2_EMAC_MDIO_COMM_DISEXT;
385 REG_WR(bp, BNX2_EMAC_MDIO_COMM, val1);
6aa20a22 386
b6016b76
MC		 387 for (i = 0; i < 50; i++) {
388 udelay(10);
389
390 val1 = REG_RD(bp, BNX2_EMAC_MDIO_COMM);
391 if (!(val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)) {
392 udelay(5);
393 break;
394 }
395 }
396
397 if (val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)
398 ret = -EBUSY;
399 else
400 ret = 0;
401
583c28e5 402 if (bp->phy_flags & BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING) {
b6016b76
MC		 403 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
404 val1 |= BNX2_EMAC_MDIO_MODE_AUTO_POLL;
405
406 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
407 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
408
409 udelay(40);
410 }
411
412 return ret;
413}
414
415static void
416bnx2_disable_int(struct bnx2 *bp)
417{
b4b36042
MC		 418 int i;
419 struct bnx2_napi *bnapi;
420
421 for (i = 0; i < bp->irq_nvecs; i++) {
422 bnapi = &bp->bnx2_napi[i];
423 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num |
424 BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
425 }
b6016b76
MC		 426 REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD);
427}
428
429static void
430bnx2_enable_int(struct bnx2 *bp)
431{
b4b36042
MC		 432 int i;
433 struct bnx2_napi *bnapi;
35efa7c1 434
b4b36042
MC		 435 for (i = 0; i < bp->irq_nvecs; i++) {
436 bnapi = &bp->bnx2_napi[i];
1269a8a6 437
b4b36042
MC		 438 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num |
439 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
440 BNX2_PCICFG_INT_ACK_CMD_MASK_INT |
441 bnapi->last_status_idx);
b6016b76 442
b4b36042
MC		 443 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num |
444 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
445 bnapi->last_status_idx);
446 }
bf5295bb 447 REG_WR(bp, BNX2_HC_COMMAND, bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW);
b6016b76
MC		 448}
449
450static void
451bnx2_disable_int_sync(struct bnx2 *bp)
452{
b4b36042
MC		 453 int i;
454
b6016b76
MC		 455 atomic_inc(&bp->intr_sem);
456 bnx2_disable_int(bp);
b4b36042
MC		 457 for (i = 0; i < bp->irq_nvecs; i++)
458 synchronize_irq(bp->irq_tbl[i].vector);
b6016b76
MC		 459}
460
35efa7c1
MC		 461static void
462bnx2_napi_disable(struct bnx2 *bp)
463{
b4b36042
MC		 464 int i;
465
466 for (i = 0; i < bp->irq_nvecs; i++)
467 napi_disable(&bp->bnx2_napi[i].napi);
35efa7c1
MC		 468}
469
470static void
471bnx2_napi_enable(struct bnx2 *bp)
472{
b4b36042
MC		 473 int i;
474
475 for (i = 0; i < bp->irq_nvecs; i++)
476 napi_enable(&bp->bnx2_napi[i].napi);
35efa7c1
MC		 477}
478
b6016b76
MC		 479static void
480bnx2_netif_stop(struct bnx2 *bp)
481{
482 bnx2_disable_int_sync(bp);
483 if (netif_running(bp->dev)) {
35efa7c1 484 bnx2_napi_disable(bp);
b6016b76
MC		 485 netif_tx_disable(bp->dev);
486 bp->dev->trans_start = jiffies; /* prevent tx timeout */
487 }
488}
489
490static void
491bnx2_netif_start(struct bnx2 *bp)
492{
493 if (atomic_dec_and_test(&bp->intr_sem)) {
494 if (netif_running(bp->dev)) {
706bf240 495 netif_tx_wake_all_queues(bp->dev);
35efa7c1 496 bnx2_napi_enable(bp);
b6016b76
MC		 497 bnx2_enable_int(bp);
498 }
499 }
500}
501
35e9010b
MC		 502static void
503bnx2_free_tx_mem(struct bnx2 *bp)
504{
505 int i;
506
507 for (i = 0; i < bp->num_tx_rings; i++) {
508 struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
509 struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
510
511 if (txr->tx_desc_ring) {
512 pci_free_consistent(bp->pdev, TXBD_RING_SIZE,
513 txr->tx_desc_ring,
514 txr->tx_desc_mapping);
515 txr->tx_desc_ring = NULL;
516 }
517 kfree(txr->tx_buf_ring);
518 txr->tx_buf_ring = NULL;
519 }
520}
521
bb4f98ab
MC		 522static void
523bnx2_free_rx_mem(struct bnx2 *bp)
524{
525 int i;
526
527 for (i = 0; i < bp->num_rx_rings; i++) {
528 struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
529 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
530 int j;
531
532 for (j = 0; j < bp->rx_max_ring; j++) {
533 if (rxr->rx_desc_ring[j])
534 pci_free_consistent(bp->pdev, RXBD_RING_SIZE,
535 rxr->rx_desc_ring[j],
536 rxr->rx_desc_mapping[j]);
537 rxr->rx_desc_ring[j] = NULL;
538 }
539 if (rxr->rx_buf_ring)
540 vfree(rxr->rx_buf_ring);
541 rxr->rx_buf_ring = NULL;
542
543 for (j = 0; j < bp->rx_max_pg_ring; j++) {
544 if (rxr->rx_pg_desc_ring[j])
545 pci_free_consistent(bp->pdev, RXBD_RING_SIZE,
546 rxr->rx_pg_desc_ring[i],
547 rxr->rx_pg_desc_mapping[i]);
548 rxr->rx_pg_desc_ring[i] = NULL;
549 }
550 if (rxr->rx_pg_ring)
551 vfree(rxr->rx_pg_ring);
552 rxr->rx_pg_ring = NULL;
553 }
554}
555
35e9010b
MC		 556static int
557bnx2_alloc_tx_mem(struct bnx2 *bp)
558{
559 int i;
560
561 for (i = 0; i < bp->num_tx_rings; i++) {
562 struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
563 struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
564
565 txr->tx_buf_ring = kzalloc(SW_TXBD_RING_SIZE, GFP_KERNEL);
566 if (txr->tx_buf_ring == NULL)
567 return -ENOMEM;
568
569 txr->tx_desc_ring =
570 pci_alloc_consistent(bp->pdev, TXBD_RING_SIZE,
571 &txr->tx_desc_mapping);
572 if (txr->tx_desc_ring == NULL)
573 return -ENOMEM;
574 }
575 return 0;
576}
577
bb4f98ab
MC		 578static int
579bnx2_alloc_rx_mem(struct bnx2 *bp)
580{
581 int i;
582
583 for (i = 0; i < bp->num_rx_rings; i++) {
584 struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
585 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
586 int j;
587
588 rxr->rx_buf_ring =
589 vmalloc(SW_RXBD_RING_SIZE * bp->rx_max_ring);
590 if (rxr->rx_buf_ring == NULL)
591 return -ENOMEM;
592
593 memset(rxr->rx_buf_ring, 0,
594 SW_RXBD_RING_SIZE * bp->rx_max_ring);
595
596 for (j = 0; j < bp->rx_max_ring; j++) {
597 rxr->rx_desc_ring[j] =
598 pci_alloc_consistent(bp->pdev, RXBD_RING_SIZE,
599 &rxr->rx_desc_mapping[j]);
600 if (rxr->rx_desc_ring[j] == NULL)
601 return -ENOMEM;
602
603 }
604
605 if (bp->rx_pg_ring_size) {
606 rxr->rx_pg_ring = vmalloc(SW_RXPG_RING_SIZE *
607 bp->rx_max_pg_ring);
608 if (rxr->rx_pg_ring == NULL)
609 return -ENOMEM;
610
611 memset(rxr->rx_pg_ring, 0, SW_RXPG_RING_SIZE *
612 bp->rx_max_pg_ring);
613 }
614
615 for (j = 0; j < bp->rx_max_pg_ring; j++) {
616 rxr->rx_pg_desc_ring[j] =
617 pci_alloc_consistent(bp->pdev, RXBD_RING_SIZE,
618 &rxr->rx_pg_desc_mapping[j]);
619 if (rxr->rx_pg_desc_ring[j] == NULL)
620 return -ENOMEM;
621
622 }
623 }
624 return 0;
625}
626
b6016b76
MC		 627static void
628bnx2_free_mem(struct bnx2 *bp)
629{
13daffa2 630 int i;
43e80b89 631 struct bnx2_napi *bnapi = &bp->bnx2_napi[0];
13daffa2 632
35e9010b 633 bnx2_free_tx_mem(bp);
bb4f98ab 634 bnx2_free_rx_mem(bp);
35e9010b 635
59b47d8a
MC		 636 for (i = 0; i < bp->ctx_pages; i++) {
637 if (bp->ctx_blk[i]) {
638 pci_free_consistent(bp->pdev, BCM_PAGE_SIZE,
639 bp->ctx_blk[i],
640 bp->ctx_blk_mapping[i]);
641 bp->ctx_blk[i] = NULL;
642 }
643 }
43e80b89 644 if (bnapi->status_blk.msi) {
0f31f994 645 pci_free_consistent(bp->pdev, bp->status_stats_size,
43e80b89
MC		 646 bnapi->status_blk.msi,
647 bp->status_blk_mapping);
648 bnapi->status_blk.msi = NULL;
0f31f994 649 bp->stats_blk = NULL;
b6016b76 650 }
b6016b76
MC		 651}
652
653static int
654bnx2_alloc_mem(struct bnx2 *bp)
655{
35e9010b 656 int i, status_blk_size, err;
43e80b89
MC		 657 struct bnx2_napi *bnapi;
658 void *status_blk;
b6016b76 659
0f31f994
MC		 660 /* Combine status and statistics blocks into one allocation. */
661 status_blk_size = L1_CACHE_ALIGN(sizeof(struct status_block));
f86e82fb 662 if (bp->flags & BNX2_FLAG_MSIX_CAP)
b4b36042
MC		 663 status_blk_size = L1_CACHE_ALIGN(BNX2_MAX_MSIX_HW_VEC *
664 BNX2_SBLK_MSIX_ALIGN_SIZE);
0f31f994
MC		 665 bp->status_stats_size = status_blk_size +
666 sizeof(struct statistics_block);
667
43e80b89
MC		 668 status_blk = pci_alloc_consistent(bp->pdev, bp->status_stats_size,
669 &bp->status_blk_mapping);
670 if (status_blk == NULL)
b6016b76
MC		 671 goto alloc_mem_err;
672
43e80b89 673 memset(status_blk, 0, bp->status_stats_size);
b6016b76 674
43e80b89
MC		 675 bnapi = &bp->bnx2_napi[0];
676 bnapi->status_blk.msi = status_blk;
677 bnapi->hw_tx_cons_ptr =
678 &bnapi->status_blk.msi->status_tx_quick_consumer_index0;
679 bnapi->hw_rx_cons_ptr =
680 &bnapi->status_blk.msi->status_rx_quick_consumer_index0;
f86e82fb 681 if (bp->flags & BNX2_FLAG_MSIX_CAP) {
b4b36042 682 for (i = 1; i < BNX2_MAX_MSIX_VEC; i++) {
43e80b89
MC		 683 struct status_block_msix *sblk;
684
685 bnapi = &bp->bnx2_napi[i];
b4b36042 686
43e80b89
MC		 687 sblk = (void *) (status_blk +
688 BNX2_SBLK_MSIX_ALIGN_SIZE * i);
689 bnapi->status_blk.msix = sblk;
690 bnapi->hw_tx_cons_ptr =
691 &sblk->status_tx_quick_consumer_index;
692 bnapi->hw_rx_cons_ptr =
693 &sblk->status_rx_quick_consumer_index;
b4b36042
MC		 694 bnapi->int_num = i << 24;
695 }
696 }
35efa7c1 697
43e80b89 698 bp->stats_blk = status_blk + status_blk_size;
b6016b76 699
0f31f994 700 bp->stats_blk_mapping = bp->status_blk_mapping + status_blk_size;
b6016b76 701
59b47d8a
MC		 702 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
703 bp->ctx_pages = 0x2000 / BCM_PAGE_SIZE;
704 if (bp->ctx_pages == 0)
705 bp->ctx_pages = 1;
706 for (i = 0; i < bp->ctx_pages; i++) {
707 bp->ctx_blk[i] = pci_alloc_consistent(bp->pdev,
708 BCM_PAGE_SIZE,
709 &bp->ctx_blk_mapping[i]);
710 if (bp->ctx_blk[i] == NULL)
711 goto alloc_mem_err;
712 }
713 }
35e9010b 714
bb4f98ab
MC		 715 err = bnx2_alloc_rx_mem(bp);
716 if (err)
717 goto alloc_mem_err;
718
35e9010b
MC		 719 err = bnx2_alloc_tx_mem(bp);
720 if (err)
721 goto alloc_mem_err;
722
b6016b76
MC		 723 return 0;
724
725alloc_mem_err:
726 bnx2_free_mem(bp);
727 return -ENOMEM;
728}
729
e3648b3d
MC		 730static void
731bnx2_report_fw_link(struct bnx2 *bp)
732{
733 u32 fw_link_status = 0;
734
583c28e5 735 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
0d8a6571
MC		 736 return;
737
e3648b3d
MC		 738 if (bp->link_up) {
739 u32 bmsr;
740
741 switch (bp->line_speed) {
742 case SPEED_10:
743 if (bp->duplex == DUPLEX_HALF)
744 fw_link_status = BNX2_LINK_STATUS_10HALF;
745 else
746 fw_link_status = BNX2_LINK_STATUS_10FULL;
747 break;
748 case SPEED_100:
749 if (bp->duplex == DUPLEX_HALF)
750 fw_link_status = BNX2_LINK_STATUS_100HALF;
751 else
752 fw_link_status = BNX2_LINK_STATUS_100FULL;
753 break;
754 case SPEED_1000:
755 if (bp->duplex == DUPLEX_HALF)
756 fw_link_status = BNX2_LINK_STATUS_1000HALF;
757 else
758 fw_link_status = BNX2_LINK_STATUS_1000FULL;
759 break;
760 case SPEED_2500:
761 if (bp->duplex == DUPLEX_HALF)
762 fw_link_status = BNX2_LINK_STATUS_2500HALF;
763 else
764 fw_link_status = BNX2_LINK_STATUS_2500FULL;
765 break;
766 }
767
768 fw_link_status |= BNX2_LINK_STATUS_LINK_UP;
769
770 if (bp->autoneg) {
771 fw_link_status |= BNX2_LINK_STATUS_AN_ENABLED;
772
ca58c3af
MC		 773 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
774 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
e3648b3d
MC		 775
776 if (!(bmsr & BMSR_ANEGCOMPLETE) ||
583c28e5 777 bp->phy_flags & BNX2_PHY_FLAG_PARALLEL_DETECT)
e3648b3d
MC		 778 fw_link_status |= BNX2_LINK_STATUS_PARALLEL_DET;
779 else
780 fw_link_status |= BNX2_LINK_STATUS_AN_COMPLETE;
781 }
782 }
783 else
784 fw_link_status = BNX2_LINK_STATUS_LINK_DOWN;
785
2726d6e1 786 bnx2_shmem_wr(bp, BNX2_LINK_STATUS, fw_link_status);
e3648b3d
MC		 787}
788
9b1084b8
MC		 789static char *
790bnx2_xceiver_str(struct bnx2 *bp)
791{
792 return ((bp->phy_port == PORT_FIBRE) ? "SerDes" :
583c28e5 793 ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) ? "Remote Copper" :
9b1084b8
MC		 794 "Copper"));
795}
796
b6016b76
MC		 797static void
798bnx2_report_link(struct bnx2 *bp)
799{
800 if (bp->link_up) {
801 netif_carrier_on(bp->dev);
9b1084b8
MC		 802 printk(KERN_INFO PFX "%s NIC %s Link is Up, ", bp->dev->name,
803 bnx2_xceiver_str(bp));
b6016b76
MC		 804
805 printk("%d Mbps ", bp->line_speed);
806
807 if (bp->duplex == DUPLEX_FULL)
808 printk("full duplex");
809 else
810 printk("half duplex");
811
812 if (bp->flow_ctrl) {
813 if (bp->flow_ctrl & FLOW_CTRL_RX) {
814 printk(", receive ");
815 if (bp->flow_ctrl & FLOW_CTRL_TX)
816 printk("& transmit ");
817 }
818 else {
819 printk(", transmit ");
820 }
821 printk("flow control ON");
822 }
823 printk("\n");
824 }
825 else {
826 netif_carrier_off(bp->dev);
9b1084b8
MC		 827 printk(KERN_ERR PFX "%s NIC %s Link is Down\n", bp->dev->name,
828 bnx2_xceiver_str(bp));
b6016b76 829 }
e3648b3d
MC		 830
831 bnx2_report_fw_link(bp);
b6016b76
MC		 832}
833
834static void
835bnx2_resolve_flow_ctrl(struct bnx2 *bp)
836{
837 u32 local_adv, remote_adv;
838
839 bp->flow_ctrl = 0;
6aa20a22 840 if ((bp->autoneg & (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) !=
b6016b76
MC		 841 (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) {
842
843 if (bp->duplex == DUPLEX_FULL) {
844 bp->flow_ctrl = bp->req_flow_ctrl;
845 }
846 return;
847 }
848
849 if (bp->duplex != DUPLEX_FULL) {
850 return;
851 }
852
583c28e5 853 if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
5b0c76ad
MC		 854 (CHIP_NUM(bp) == CHIP_NUM_5708)) {
855 u32 val;
856
857 bnx2_read_phy(bp, BCM5708S_1000X_STAT1, &val);
858 if (val & BCM5708S_1000X_STAT1_TX_PAUSE)
859 bp->flow_ctrl |= FLOW_CTRL_TX;
860 if (val & BCM5708S_1000X_STAT1_RX_PAUSE)
861 bp->flow_ctrl |= FLOW_CTRL_RX;
862 return;
863 }
864
ca58c3af
MC		 865 bnx2_read_phy(bp, bp->mii_adv, &local_adv);
866 bnx2_read_phy(bp, bp->mii_lpa, &remote_adv);
b6016b76 867
583c28e5 868 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
b6016b76
MC		 869 u32 new_local_adv = 0;
870 u32 new_remote_adv = 0;
871
872 if (local_adv & ADVERTISE_1000XPAUSE)
873 new_local_adv |= ADVERTISE_PAUSE_CAP;
874 if (local_adv & ADVERTISE_1000XPSE_ASYM)
875 new_local_adv |= ADVERTISE_PAUSE_ASYM;
876 if (remote_adv & ADVERTISE_1000XPAUSE)
877 new_remote_adv |= ADVERTISE_PAUSE_CAP;
878 if (remote_adv & ADVERTISE_1000XPSE_ASYM)
879 new_remote_adv |= ADVERTISE_PAUSE_ASYM;
880
881 local_adv = new_local_adv;
882 remote_adv = new_remote_adv;
883 }
884
885 /* See Table 28B-3 of 802.3ab-1999 spec. */
886 if (local_adv & ADVERTISE_PAUSE_CAP) {
887 if(local_adv & ADVERTISE_PAUSE_ASYM) {
888 if (remote_adv & ADVERTISE_PAUSE_CAP) {
889 bp->flow_ctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
890 }
891 else if (remote_adv & ADVERTISE_PAUSE_ASYM) {
892 bp->flow_ctrl = FLOW_CTRL_RX;
893 }
894 }
895 else {
896 if (remote_adv & ADVERTISE_PAUSE_CAP) {
897 bp->flow_ctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
898 }
899 }
900 }
901 else if (local_adv & ADVERTISE_PAUSE_ASYM) {
902 if ((remote_adv & ADVERTISE_PAUSE_CAP) &&
903 (remote_adv & ADVERTISE_PAUSE_ASYM)) {
904
905 bp->flow_ctrl = FLOW_CTRL_TX;
906 }
907 }
908}
909
27a005b8
MC		 910static int
911bnx2_5709s_linkup(struct bnx2 *bp)
912{
913 u32 val, speed;
914
915 bp->link_up = 1;
916
917 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_GP_STATUS);
918 bnx2_read_phy(bp, MII_BNX2_GP_TOP_AN_STATUS1, &val);
919 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
920
921 if ((bp->autoneg & AUTONEG_SPEED) == 0) {
922 bp->line_speed = bp->req_line_speed;
923 bp->duplex = bp->req_duplex;
924 return 0;
925 }
926 speed = val & MII_BNX2_GP_TOP_AN_SPEED_MSK;
927 switch (speed) {
928 case MII_BNX2_GP_TOP_AN_SPEED_10:
929 bp->line_speed = SPEED_10;
930 break;
931 case MII_BNX2_GP_TOP_AN_SPEED_100:
932 bp->line_speed = SPEED_100;
933 break;
934 case MII_BNX2_GP_TOP_AN_SPEED_1G:
935 case MII_BNX2_GP_TOP_AN_SPEED_1GKV:
936 bp->line_speed = SPEED_1000;
937 break;
938 case MII_BNX2_GP_TOP_AN_SPEED_2_5G:
939 bp->line_speed = SPEED_2500;
940 break;
941 }
942 if (val & MII_BNX2_GP_TOP_AN_FD)
943 bp->duplex = DUPLEX_FULL;
944 else
945 bp->duplex = DUPLEX_HALF;
946 return 0;
947}
948
b6016b76 949static int
5b0c76ad
MC		 950bnx2_5708s_linkup(struct bnx2 *bp)
951{
952 u32 val;
953
954 bp->link_up = 1;
955 bnx2_read_phy(bp, BCM5708S_1000X_STAT1, &val);
956 switch (val & BCM5708S_1000X_STAT1_SPEED_MASK) {
957 case BCM5708S_1000X_STAT1_SPEED_10:
958 bp->line_speed = SPEED_10;
959 break;
960 case BCM5708S_1000X_STAT1_SPEED_100:
961 bp->line_speed = SPEED_100;
962 break;
963 case BCM5708S_1000X_STAT1_SPEED_1G:
964 bp->line_speed = SPEED_1000;
965 break;
966 case BCM5708S_1000X_STAT1_SPEED_2G5:
967 bp->line_speed = SPEED_2500;
968 break;
969 }
970 if (val & BCM5708S_1000X_STAT1_FD)
971 bp->duplex = DUPLEX_FULL;
972 else
973 bp->duplex = DUPLEX_HALF;
974
975 return 0;
976}
977
978static int
979bnx2_5706s_linkup(struct bnx2 *bp)
b6016b76
MC		 980{
981 u32 bmcr, local_adv, remote_adv, common;
982
983 bp->link_up = 1;
984 bp->line_speed = SPEED_1000;
985
ca58c3af 986 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
b6016b76
MC		 987 if (bmcr & BMCR_FULLDPLX) {
988 bp->duplex = DUPLEX_FULL;
989 }
990 else {
991 bp->duplex = DUPLEX_HALF;
992 }
993
994 if (!(bmcr & BMCR_ANENABLE)) {
995 return 0;
996 }
997
ca58c3af
MC		 998 bnx2_read_phy(bp, bp->mii_adv, &local_adv);
999 bnx2_read_phy(bp, bp->mii_lpa, &remote_adv);
b6016b76
MC		 1000
1001 common = local_adv & remote_adv;
1002 if (common & (ADVERTISE_1000XHALF | ADVERTISE_1000XFULL)) {
1003
1004 if (common & ADVERTISE_1000XFULL) {
1005 bp->duplex = DUPLEX_FULL;
1006 }
1007 else {
1008 bp->duplex = DUPLEX_HALF;
1009 }
1010 }
1011
1012 return 0;
1013}
1014
1015static int
1016bnx2_copper_linkup(struct bnx2 *bp)
1017{
1018 u32 bmcr;
1019
ca58c3af 1020 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
b6016b76
MC		 1021 if (bmcr & BMCR_ANENABLE) {
1022 u32 local_adv, remote_adv, common;
1023
1024 bnx2_read_phy(bp, MII_CTRL1000, &local_adv);
1025 bnx2_read_phy(bp, MII_STAT1000, &remote_adv);
1026
1027 common = local_adv & (remote_adv >> 2);
1028 if (common & ADVERTISE_1000FULL) {
1029 bp->line_speed = SPEED_1000;
1030 bp->duplex = DUPLEX_FULL;
1031 }
1032 else if (common & ADVERTISE_1000HALF) {
1033 bp->line_speed = SPEED_1000;
1034 bp->duplex = DUPLEX_HALF;
1035 }
1036 else {
ca58c3af
MC		 1037 bnx2_read_phy(bp, bp->mii_adv, &local_adv);
1038 bnx2_read_phy(bp, bp->mii_lpa, &remote_adv);
b6016b76
MC		 1039
1040 common = local_adv & remote_adv;
1041 if (common & ADVERTISE_100FULL) {
1042 bp->line_speed = SPEED_100;
1043 bp->duplex = DUPLEX_FULL;
1044 }
1045 else if (common & ADVERTISE_100HALF) {
1046 bp->line_speed = SPEED_100;
1047 bp->duplex = DUPLEX_HALF;
1048 }
1049 else if (common & ADVERTISE_10FULL) {
1050 bp->line_speed = SPEED_10;
1051 bp->duplex = DUPLEX_FULL;
1052 }
1053 else if (common & ADVERTISE_10HALF) {
1054 bp->line_speed = SPEED_10;
1055 bp->duplex = DUPLEX_HALF;
1056 }
1057 else {
1058 bp->line_speed = 0;
1059 bp->link_up = 0;
1060 }
1061 }
1062 }
1063 else {
1064 if (bmcr & BMCR_SPEED100) {
1065 bp->line_speed = SPEED_100;
1066 }
1067 else {
1068 bp->line_speed = SPEED_10;
1069 }
1070 if (bmcr & BMCR_FULLDPLX) {
1071 bp->duplex = DUPLEX_FULL;
1072 }
1073 else {
1074 bp->duplex = DUPLEX_HALF;
1075 }
1076 }
1077
1078 return 0;
1079}
1080
83e3fc89 1081static void
bb4f98ab 1082bnx2_init_rx_context(struct bnx2 *bp, u32 cid)
83e3fc89 1083{
bb4f98ab 1084 u32 val, rx_cid_addr = GET_CID_ADDR(cid);
83e3fc89
MC		 1085
1086 val = BNX2_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE;
1087 val |= BNX2_L2CTX_CTX_TYPE_SIZE_L2;
1088 val |= 0x02 << 8;
1089
1090 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
1091 u32 lo_water, hi_water;
1092
1093 if (bp->flow_ctrl & FLOW_CTRL_TX)
1094 lo_water = BNX2_L2CTX_LO_WATER_MARK_DEFAULT;
1095 else
1096 lo_water = BNX2_L2CTX_LO_WATER_MARK_DIS;
1097 if (lo_water >= bp->rx_ring_size)
1098 lo_water = 0;
1099
1100 hi_water = bp->rx_ring_size / 4;
1101
1102 if (hi_water <= lo_water)
1103 lo_water = 0;
1104
1105 hi_water /= BNX2_L2CTX_HI_WATER_MARK_SCALE;
1106 lo_water /= BNX2_L2CTX_LO_WATER_MARK_SCALE;
1107
1108 if (hi_water > 0xf)
1109 hi_water = 0xf;
1110 else if (hi_water == 0)
1111 lo_water = 0;
1112 val |= lo_water | (hi_water << BNX2_L2CTX_HI_WATER_MARK_SHIFT);
1113 }
1114 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_CTX_TYPE, val);
1115}
1116
bb4f98ab
MC		 1117static void
1118bnx2_init_all_rx_contexts(struct bnx2 *bp)
1119{
1120 int i;
1121 u32 cid;
1122
1123 for (i = 0, cid = RX_CID; i < bp->num_rx_rings; i++, cid++) {
1124 if (i == 1)
1125 cid = RX_RSS_CID;
1126 bnx2_init_rx_context(bp, cid);
1127 }
1128}
1129
344478db 1130static void
b6016b76
MC		 1131bnx2_set_mac_link(struct bnx2 *bp)
1132{
1133 u32 val;
1134
1135 REG_WR(bp, BNX2_EMAC_TX_LENGTHS, 0x2620);
1136 if (bp->link_up && (bp->line_speed == SPEED_1000) &&
1137 (bp->duplex == DUPLEX_HALF)) {
1138 REG_WR(bp, BNX2_EMAC_TX_LENGTHS, 0x26ff);
1139 }
1140
1141 /* Configure the EMAC mode register. */
1142 val = REG_RD(bp, BNX2_EMAC_MODE);
1143
1144 val &= ~(BNX2_EMAC_MODE_PORT | BNX2_EMAC_MODE_HALF_DUPLEX |
5b0c76ad 1145 BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK |
59b47d8a 1146 BNX2_EMAC_MODE_25G_MODE);
b6016b76
MC		 1147
1148 if (bp->link_up) {
5b0c76ad
MC		 1149 switch (bp->line_speed) {
1150 case SPEED_10:
59b47d8a
MC		 1151 if (CHIP_NUM(bp) != CHIP_NUM_5706) {
1152 val |= BNX2_EMAC_MODE_PORT_MII_10M;
5b0c76ad
MC		 1153 break;
1154 }
1155 /* fall through */
1156 case SPEED_100:
1157 val |= BNX2_EMAC_MODE_PORT_MII;
1158 break;
1159 case SPEED_2500:
59b47d8a 1160 val |= BNX2_EMAC_MODE_25G_MODE;
5b0c76ad
MC		 1161 /* fall through */
1162 case SPEED_1000:
1163 val |= BNX2_EMAC_MODE_PORT_GMII;
1164 break;
1165 }
b6016b76
MC		 1166 }
1167 else {
1168 val |= BNX2_EMAC_MODE_PORT_GMII;
1169 }
1170
1171 /* Set the MAC to operate in the appropriate duplex mode. */
1172 if (bp->duplex == DUPLEX_HALF)
1173 val |= BNX2_EMAC_MODE_HALF_DUPLEX;
1174 REG_WR(bp, BNX2_EMAC_MODE, val);
1175
1176 /* Enable/disable rx PAUSE. */
1177 bp->rx_mode &= ~BNX2_EMAC_RX_MODE_FLOW_EN;
1178
1179 if (bp->flow_ctrl & FLOW_CTRL_RX)
1180 bp->rx_mode |= BNX2_EMAC_RX_MODE_FLOW_EN;
1181 REG_WR(bp, BNX2_EMAC_RX_MODE, bp->rx_mode);
1182
1183 /* Enable/disable tx PAUSE. */
1184 val = REG_RD(bp, BNX2_EMAC_TX_MODE);
1185 val &= ~BNX2_EMAC_TX_MODE_FLOW_EN;
1186
1187 if (bp->flow_ctrl & FLOW_CTRL_TX)
1188 val |= BNX2_EMAC_TX_MODE_FLOW_EN;
1189 REG_WR(bp, BNX2_EMAC_TX_MODE, val);
1190
1191 /* Acknowledge the interrupt. */
1192 REG_WR(bp, BNX2_EMAC_STATUS, BNX2_EMAC_STATUS_LINK_CHANGE);
1193
83e3fc89 1194 if (CHIP_NUM(bp) == CHIP_NUM_5709)
bb4f98ab 1195 bnx2_init_all_rx_contexts(bp);
b6016b76
MC		 1196}
1197
27a005b8
MC		 1198static void
1199bnx2_enable_bmsr1(struct bnx2 *bp)
1200{
583c28e5 1201 if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
27a005b8
MC		 1202 (CHIP_NUM(bp) == CHIP_NUM_5709))
1203 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1204 MII_BNX2_BLK_ADDR_GP_STATUS);
1205}
1206
1207static void
1208bnx2_disable_bmsr1(struct bnx2 *bp)
1209{
583c28e5 1210 if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
27a005b8
MC		 1211 (CHIP_NUM(bp) == CHIP_NUM_5709))
1212 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1213 MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1214}
1215
605a9e20
MC		 1216static int
1217bnx2_test_and_enable_2g5(struct bnx2 *bp)
1218{
1219 u32 up1;
1220 int ret = 1;
1221
583c28e5 1222 if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))
605a9e20
MC		 1223 return 0;
1224
1225 if (bp->autoneg & AUTONEG_SPEED)
1226 bp->advertising |= ADVERTISED_2500baseX_Full;
1227
27a005b8
MC		 1228 if (CHIP_NUM(bp) == CHIP_NUM_5709)
1229 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_OVER1G);
1230
605a9e20
MC		 1231 bnx2_read_phy(bp, bp->mii_up1, &up1);
1232 if (!(up1 & BCM5708S_UP1_2G5)) {
1233 up1 |= BCM5708S_UP1_2G5;
1234 bnx2_write_phy(bp, bp->mii_up1, up1);
1235 ret = 0;
1236 }
1237
27a005b8
MC		 1238 if (CHIP_NUM(bp) == CHIP_NUM_5709)
1239 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1240 MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1241
605a9e20
MC		 1242 return ret;
1243}
1244
1245static int
1246bnx2_test_and_disable_2g5(struct bnx2 *bp)
1247{
1248 u32 up1;
1249 int ret = 0;
1250
583c28e5 1251 if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))
605a9e20
MC		 1252 return 0;
1253
27a005b8
MC		 1254 if (CHIP_NUM(bp) == CHIP_NUM_5709)
1255 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_OVER1G);
1256
605a9e20
MC		 1257 bnx2_read_phy(bp, bp->mii_up1, &up1);
1258 if (up1 & BCM5708S_UP1_2G5) {
1259 up1 &= ~BCM5708S_UP1_2G5;
1260 bnx2_write_phy(bp, bp->mii_up1, up1);
1261 ret = 1;
1262 }
1263
27a005b8
MC		 1264 if (CHIP_NUM(bp) == CHIP_NUM_5709)
1265 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1266 MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1267
605a9e20
MC		 1268 return ret;
1269}
1270
1271static void
1272bnx2_enable_forced_2g5(struct bnx2 *bp)
1273{
1274 u32 bmcr;
1275
583c28e5 1276 if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))
605a9e20
MC		 1277 return;
1278
27a005b8
MC		 1279 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
1280 u32 val;
1281
1282 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1283 MII_BNX2_BLK_ADDR_SERDES_DIG);
1284 bnx2_read_phy(bp, MII_BNX2_SERDES_DIG_MISC1, &val);
1285 val &= ~MII_BNX2_SD_MISC1_FORCE_MSK;
1286 val |= MII_BNX2_SD_MISC1_FORCE | MII_BNX2_SD_MISC1_FORCE_2_5G;
1287 bnx2_write_phy(bp, MII_BNX2_SERDES_DIG_MISC1, val);
1288
1289 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1290 MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1291 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1292
1293 } else if (CHIP_NUM(bp) == CHIP_NUM_5708) {
605a9e20
MC		 1294 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1295 bmcr |= BCM5708S_BMCR_FORCE_2500;
1296 }
1297
1298 if (bp->autoneg & AUTONEG_SPEED) {
1299 bmcr &= ~BMCR_ANENABLE;
1300 if (bp->req_duplex == DUPLEX_FULL)
1301 bmcr |= BMCR_FULLDPLX;
1302 }
1303 bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
1304}
1305
1306static void
1307bnx2_disable_forced_2g5(struct bnx2 *bp)
1308{
1309 u32 bmcr;
1310
583c28e5 1311 if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))
605a9e20
MC		 1312 return;
1313
27a005b8
MC		 1314 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
1315 u32 val;
1316
1317 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1318 MII_BNX2_BLK_ADDR_SERDES_DIG);
1319 bnx2_read_phy(bp, MII_BNX2_SERDES_DIG_MISC1, &val);
1320 val &= ~MII_BNX2_SD_MISC1_FORCE;
1321 bnx2_write_phy(bp, MII_BNX2_SERDES_DIG_MISC1, val);
1322
1323 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1324 MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1325 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1326
1327 } else if (CHIP_NUM(bp) == CHIP_NUM_5708) {
605a9e20
MC		 1328 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1329 bmcr &= ~BCM5708S_BMCR_FORCE_2500;
1330 }
1331
1332 if (bp->autoneg & AUTONEG_SPEED)
1333 bmcr |= BMCR_SPEED1000 | BMCR_ANENABLE | BMCR_ANRESTART;
1334 bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
1335}
1336
b2fadeae
MC		 1337static void
1338bnx2_5706s_force_link_dn(struct bnx2 *bp, int start)
1339{
1340 u32 val;
1341
1342 bnx2_write_phy(bp, MII_BNX2_DSP_ADDRESS, MII_EXPAND_SERDES_CTL);
1343 bnx2_read_phy(bp, MII_BNX2_DSP_RW_PORT, &val);
1344 if (start)
1345 bnx2_write_phy(bp, MII_BNX2_DSP_RW_PORT, val & 0xff0f);
1346 else
1347 bnx2_write_phy(bp, MII_BNX2_DSP_RW_PORT, val | 0xc0);
1348}
1349
b6016b76
MC		 1350static int
1351bnx2_set_link(struct bnx2 *bp)
1352{
1353 u32 bmsr;
1354 u8 link_up;
1355
80be4434 1356 if (bp->loopback == MAC_LOOPBACK || bp->loopback == PHY_LOOPBACK) {
b6016b76
MC		 1357 bp->link_up = 1;
1358 return 0;
1359 }
1360
583c28e5 1361 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
0d8a6571
MC		 1362 return 0;
1363
b6016b76
MC		 1364 link_up = bp->link_up;
1365
27a005b8
MC		 1366 bnx2_enable_bmsr1(bp);
1367 bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr);
1368 bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr);
1369 bnx2_disable_bmsr1(bp);
b6016b76 1370
583c28e5 1371 if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
b6016b76 1372 (CHIP_NUM(bp) == CHIP_NUM_5706)) {
a2724e25 1373 u32 val, an_dbg;
b6016b76 1374
583c28e5 1375 if (bp->phy_flags & BNX2_PHY_FLAG_FORCED_DOWN) {
b2fadeae 1376 bnx2_5706s_force_link_dn(bp, 0);
583c28e5 1377 bp->phy_flags &= ~BNX2_PHY_FLAG_FORCED_DOWN;
b2fadeae 1378 }
b6016b76 1379 val = REG_RD(bp, BNX2_EMAC_STATUS);
a2724e25
MC		 1380
1381 bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_AN_DBG);
1382 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &an_dbg);
1383 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &an_dbg);
1384
1385 if ((val & BNX2_EMAC_STATUS_LINK) &&
1386 !(an_dbg & MISC_SHDW_AN_DBG_NOSYNC))
b6016b76
MC		 1387 bmsr |= BMSR_LSTATUS;
1388 else
1389 bmsr &= ~BMSR_LSTATUS;
1390 }
1391
1392 if (bmsr & BMSR_LSTATUS) {
1393 bp->link_up = 1;
1394
583c28e5 1395 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
5b0c76ad
MC		 1396 if (CHIP_NUM(bp) == CHIP_NUM_5706)
1397 bnx2_5706s_linkup(bp);
1398 else if (CHIP_NUM(bp) == CHIP_NUM_5708)
1399 bnx2_5708s_linkup(bp);
27a005b8
MC		 1400 else if (CHIP_NUM(bp) == CHIP_NUM_5709)
1401 bnx2_5709s_linkup(bp);
b6016b76
MC		 1402 }
1403 else {
1404 bnx2_copper_linkup(bp);
1405 }
1406 bnx2_resolve_flow_ctrl(bp);
1407 }
1408 else {
583c28e5 1409 if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
605a9e20
MC		 1410 (bp->autoneg & AUTONEG_SPEED))
1411 bnx2_disable_forced_2g5(bp);
b6016b76 1412
583c28e5 1413 if (bp->phy_flags & BNX2_PHY_FLAG_PARALLEL_DETECT) {
b2fadeae
MC		 1414 u32 bmcr;
1415
1416 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1417 bmcr |= BMCR_ANENABLE;
1418 bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
1419
583c28e5 1420 bp->phy_flags &= ~BNX2_PHY_FLAG_PARALLEL_DETECT;
b2fadeae 1421 }
b6016b76
MC		 1422 bp->link_up = 0;
1423 }
1424
1425 if (bp->link_up != link_up) {
1426 bnx2_report_link(bp);
1427 }
1428
1429 bnx2_set_mac_link(bp);
1430
1431 return 0;
1432}
1433
1434static int
1435bnx2_reset_phy(struct bnx2 *bp)
1436{
1437 int i;
1438 u32 reg;
1439
ca58c3af 1440 bnx2_write_phy(bp, bp->mii_bmcr, BMCR_RESET);
b6016b76
MC		 1441
1442#define PHY_RESET_MAX_WAIT 100
1443 for (i = 0; i < PHY_RESET_MAX_WAIT; i++) {
1444 udelay(10);
1445
ca58c3af 1446 bnx2_read_phy(bp, bp->mii_bmcr, &reg);
b6016b76
MC		 1447 if (!(reg & BMCR_RESET)) {
1448 udelay(20);
1449 break;
1450 }
1451 }
1452 if (i == PHY_RESET_MAX_WAIT) {
1453 return -EBUSY;
1454 }
1455 return 0;
1456}
1457
1458static u32
1459bnx2_phy_get_pause_adv(struct bnx2 *bp)
1460{
1461 u32 adv = 0;
1462
1463 if ((bp->req_flow_ctrl & (FLOW_CTRL_RX | FLOW_CTRL_TX)) ==
1464 (FLOW_CTRL_RX | FLOW_CTRL_TX)) {
1465
583c28e5 1466 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
b6016b76
MC		 1467 adv = ADVERTISE_1000XPAUSE;
1468 }
1469 else {
1470 adv = ADVERTISE_PAUSE_CAP;
1471 }
1472 }
1473 else if (bp->req_flow_ctrl & FLOW_CTRL_TX) {
583c28e5 1474 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
b6016b76
MC		 1475 adv = ADVERTISE_1000XPSE_ASYM;
1476 }
1477 else {
1478 adv = ADVERTISE_PAUSE_ASYM;
1479 }
1480 }
1481 else if (bp->req_flow_ctrl & FLOW_CTRL_RX) {
583c28e5 1482 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
b6016b76
MC		 1483 adv = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
1484 }
1485 else {
1486 adv = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1487 }
1488 }
1489 return adv;
1490}
1491
a2f13890 1492static int bnx2_fw_sync(struct bnx2 *, u32, int, int);
0d8a6571 1493
b6016b76 1494static int
0d8a6571
MC		 1495bnx2_setup_remote_phy(struct bnx2 *bp, u8 port)
1496{
1497 u32 speed_arg = 0, pause_adv;
1498
1499 pause_adv = bnx2_phy_get_pause_adv(bp);
1500
1501 if (bp->autoneg & AUTONEG_SPEED) {
1502 speed_arg |= BNX2_NETLINK_SET_LINK_ENABLE_AUTONEG;
1503 if (bp->advertising & ADVERTISED_10baseT_Half)
1504 speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_10HALF;
1505 if (bp->advertising & ADVERTISED_10baseT_Full)
1506 speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_10FULL;
1507 if (bp->advertising & ADVERTISED_100baseT_Half)
1508 speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_100HALF;
1509 if (bp->advertising & ADVERTISED_100baseT_Full)
1510 speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_100FULL;
1511 if (bp->advertising & ADVERTISED_1000baseT_Full)
1512 speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_1GFULL;
1513 if (bp->advertising & ADVERTISED_2500baseX_Full)
1514 speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_2G5FULL;
1515 } else {
1516 if (bp->req_line_speed == SPEED_2500)
1517 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_2G5FULL;
1518 else if (bp->req_line_speed == SPEED_1000)
1519 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_1GFULL;
1520 else if (bp->req_line_speed == SPEED_100) {
1521 if (bp->req_duplex == DUPLEX_FULL)
1522 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_100FULL;
1523 else
1524 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_100HALF;
1525 } else if (bp->req_line_speed == SPEED_10) {
1526 if (bp->req_duplex == DUPLEX_FULL)
1527 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_10FULL;
1528 else
1529 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_10HALF;
1530 }
1531 }
1532
1533 if (pause_adv & (ADVERTISE_1000XPAUSE | ADVERTISE_PAUSE_CAP))
1534 speed_arg |= BNX2_NETLINK_SET_LINK_FC_SYM_PAUSE;
c26736ec 1535 if (pause_adv & (ADVERTISE_1000XPSE_ASYM | ADVERTISE_PAUSE_ASYM))
0d8a6571
MC		 1536 speed_arg |= BNX2_NETLINK_SET_LINK_FC_ASYM_PAUSE;
1537
1538 if (port == PORT_TP)
1539 speed_arg |= BNX2_NETLINK_SET_LINK_PHY_APP_REMOTE |
1540 BNX2_NETLINK_SET_LINK_ETH_AT_WIRESPEED;
1541
2726d6e1 1542 bnx2_shmem_wr(bp, BNX2_DRV_MB_ARG0, speed_arg);
0d8a6571
MC		 1543
1544 spin_unlock_bh(&bp->phy_lock);
a2f13890 1545 bnx2_fw_sync(bp, BNX2_DRV_MSG_CODE_CMD_SET_LINK, 1, 0);
0d8a6571
MC		 1546 spin_lock_bh(&bp->phy_lock);
1547
1548 return 0;
1549}
1550
1551static int
1552bnx2_setup_serdes_phy(struct bnx2 *bp, u8 port)
b6016b76 1553{
605a9e20 1554 u32 adv, bmcr;
b6016b76
MC		 1555 u32 new_adv = 0;
1556
583c28e5 1557 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
0d8a6571
MC		 1558 return (bnx2_setup_remote_phy(bp, port));
1559
b6016b76
MC		 1560 if (!(bp->autoneg & AUTONEG_SPEED)) {
1561 u32 new_bmcr;
5b0c76ad
MC		 1562 int force_link_down = 0;
1563
605a9e20
MC		 1564 if (bp->req_line_speed == SPEED_2500) {
1565 if (!bnx2_test_and_enable_2g5(bp))
1566 force_link_down = 1;
1567 } else if (bp->req_line_speed == SPEED_1000) {
1568 if (bnx2_test_and_disable_2g5(bp))
1569 force_link_down = 1;
1570 }
ca58c3af 1571 bnx2_read_phy(bp, bp->mii_adv, &adv);
80be4434
MC		 1572 adv &= ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF);
1573
ca58c3af 1574 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
605a9e20 1575 new_bmcr = bmcr & ~BMCR_ANENABLE;
80be4434 1576 new_bmcr |= BMCR_SPEED1000;
605a9e20 1577
27a005b8
MC		 1578 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
1579 if (bp->req_line_speed == SPEED_2500)
1580 bnx2_enable_forced_2g5(bp);
1581 else if (bp->req_line_speed == SPEED_1000) {
1582 bnx2_disable_forced_2g5(bp);
1583 new_bmcr &= ~0x2000;
1584 }
1585
1586 } else if (CHIP_NUM(bp) == CHIP_NUM_5708) {
605a9e20
MC		 1587 if (bp->req_line_speed == SPEED_2500)
1588 new_bmcr |= BCM5708S_BMCR_FORCE_2500;
1589 else
1590 new_bmcr = bmcr & ~BCM5708S_BMCR_FORCE_2500;
5b0c76ad
MC		 1591 }
1592
b6016b76 1593 if (bp->req_duplex == DUPLEX_FULL) {
5b0c76ad 1594 adv |= ADVERTISE_1000XFULL;
b6016b76
MC		 1595 new_bmcr |= BMCR_FULLDPLX;
1596 }
1597 else {
5b0c76ad 1598 adv |= ADVERTISE_1000XHALF;
b6016b76
MC		 1599 new_bmcr &= ~BMCR_FULLDPLX;
1600 }
5b0c76ad 1601 if ((new_bmcr != bmcr) || (force_link_down)) {
b6016b76
MC		 1602 /* Force a link down visible on the other side */
1603 if (bp->link_up) {
ca58c3af 1604 bnx2_write_phy(bp, bp->mii_adv, adv &
5b0c76ad
MC		 1605 ~(ADVERTISE_1000XFULL |
1606 ADVERTISE_1000XHALF));
ca58c3af 1607 bnx2_write_phy(bp, bp->mii_bmcr, bmcr |
b6016b76
MC		 1608 BMCR_ANRESTART | BMCR_ANENABLE);
1609
1610 bp->link_up = 0;
1611 netif_carrier_off(bp->dev);
ca58c3af 1612 bnx2_write_phy(bp, bp->mii_bmcr, new_bmcr);
80be4434 1613 bnx2_report_link(bp);
b6016b76 1614 }
ca58c3af
MC		 1615 bnx2_write_phy(bp, bp->mii_adv, adv);
1616 bnx2_write_phy(bp, bp->mii_bmcr, new_bmcr);
605a9e20
MC		 1617 } else {
1618 bnx2_resolve_flow_ctrl(bp);
1619 bnx2_set_mac_link(bp);
b6016b76
MC		 1620 }
1621 return 0;
1622 }
1623
605a9e20 1624 bnx2_test_and_enable_2g5(bp);
5b0c76ad 1625
b6016b76
MC		 1626 if (bp->advertising & ADVERTISED_1000baseT_Full)
1627 new_adv |= ADVERTISE_1000XFULL;
1628
1629 new_adv |= bnx2_phy_get_pause_adv(bp);
1630
ca58c3af
MC		 1631 bnx2_read_phy(bp, bp->mii_adv, &adv);
1632 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
b6016b76
MC		 1633
1634 bp->serdes_an_pending = 0;
1635 if ((adv != new_adv) || ((bmcr & BMCR_ANENABLE) == 0)) {
1636 /* Force a link down visible on the other side */
1637 if (bp->link_up) {
ca58c3af 1638 bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK);
80be4434
MC		 1639 spin_unlock_bh(&bp->phy_lock);
1640 msleep(20);
1641 spin_lock_bh(&bp->phy_lock);
b6016b76
MC		 1642 }
1643
ca58c3af
MC		 1644 bnx2_write_phy(bp, bp->mii_adv, new_adv);
1645 bnx2_write_phy(bp, bp->mii_bmcr, bmcr | BMCR_ANRESTART |
b6016b76 1646 BMCR_ANENABLE);
f8dd064e
MC		 1647 /* Speed up link-up time when the link partner
1648 * does not autonegotiate which is very common
1649 * in blade servers. Some blade servers use
1650 * IPMI for kerboard input and it's important
1651 * to minimize link disruptions. Autoneg. involves
1652 * exchanging base pages plus 3 next pages and
1653 * normally completes in about 120 msec.
1654 */
1655 bp->current_interval = SERDES_AN_TIMEOUT;
1656 bp->serdes_an_pending = 1;
1657 mod_timer(&bp->timer, jiffies + bp->current_interval);
605a9e20
MC		 1658 } else {
1659 bnx2_resolve_flow_ctrl(bp);
1660 bnx2_set_mac_link(bp);
b6016b76
MC		 1661 }
1662
1663 return 0;
1664}
1665
1666#define ETHTOOL_ALL_FIBRE_SPEED \
583c28e5 1667 (bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE) ? \
deaf391b
MC		 1668 (ADVERTISED_2500baseX_Full | ADVERTISED_1000baseT_Full) :\
1669 (ADVERTISED_1000baseT_Full)
b6016b76
MC		 1670
1671#define ETHTOOL_ALL_COPPER_SPEED \
1672 (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full | \
1673 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full | \
1674 ADVERTISED_1000baseT_Full)
1675
1676#define PHY_ALL_10_100_SPEED (ADVERTISE_10HALF | ADVERTISE_10FULL | \
1677 ADVERTISE_100HALF | ADVERTISE_100FULL | ADVERTISE_CSMA)
6aa20a22 1678
b6016b76
MC		 1679#define PHY_ALL_1000_SPEED (ADVERTISE_1000HALF | ADVERTISE_1000FULL)
1680
0d8a6571
MC		 1681static void
1682bnx2_set_default_remote_link(struct bnx2 *bp)
1683{
1684 u32 link;
1685
1686 if (bp->phy_port == PORT_TP)
2726d6e1 1687 link = bnx2_shmem_rd(bp, BNX2_RPHY_COPPER_LINK);
0d8a6571 1688 else
2726d6e1 1689 link = bnx2_shmem_rd(bp, BNX2_RPHY_SERDES_LINK);
0d8a6571
MC		 1690
1691 if (link & BNX2_NETLINK_SET_LINK_ENABLE_AUTONEG) {
1692 bp->req_line_speed = 0;
1693 bp->autoneg |= AUTONEG_SPEED;
1694 bp->advertising = ADVERTISED_Autoneg;
1695 if (link & BNX2_NETLINK_SET_LINK_SPEED_10HALF)
1696 bp->advertising |= ADVERTISED_10baseT_Half;
1697 if (link & BNX2_NETLINK_SET_LINK_SPEED_10FULL)
1698 bp->advertising |= ADVERTISED_10baseT_Full;
1699 if (link & BNX2_NETLINK_SET_LINK_SPEED_100HALF)
1700 bp->advertising |= ADVERTISED_100baseT_Half;
1701 if (link & BNX2_NETLINK_SET_LINK_SPEED_100FULL)
1702 bp->advertising |= ADVERTISED_100baseT_Full;
1703 if (link & BNX2_NETLINK_SET_LINK_SPEED_1GFULL)
1704 bp->advertising |= ADVERTISED_1000baseT_Full;
1705 if (link & BNX2_NETLINK_SET_LINK_SPEED_2G5FULL)
1706 bp->advertising |= ADVERTISED_2500baseX_Full;
1707 } else {
1708 bp->autoneg = 0;
1709 bp->advertising = 0;
1710 bp->req_duplex = DUPLEX_FULL;
1711 if (link & BNX2_NETLINK_SET_LINK_SPEED_10) {
1712 bp->req_line_speed = SPEED_10;
1713 if (link & BNX2_NETLINK_SET_LINK_SPEED_10HALF)
1714 bp->req_duplex = DUPLEX_HALF;
1715 }
1716 if (link & BNX2_NETLINK_SET_LINK_SPEED_100) {
1717 bp->req_line_speed = SPEED_100;
1718 if (link & BNX2_NETLINK_SET_LINK_SPEED_100HALF)
1719 bp->req_duplex = DUPLEX_HALF;
1720 }
1721 if (link & BNX2_NETLINK_SET_LINK_SPEED_1GFULL)
1722 bp->req_line_speed = SPEED_1000;
1723 if (link & BNX2_NETLINK_SET_LINK_SPEED_2G5FULL)
1724 bp->req_line_speed = SPEED_2500;
1725 }
1726}
1727
deaf391b
MC		 1728static void
1729bnx2_set_default_link(struct bnx2 *bp)
1730{
ab59859d
HH		 1731 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) {
1732 bnx2_set_default_remote_link(bp);
1733 return;
1734 }
0d8a6571 1735
deaf391b
MC		 1736 bp->autoneg = AUTONEG_SPEED | AUTONEG_FLOW_CTRL;
1737 bp->req_line_speed = 0;
583c28e5 1738 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
deaf391b
MC		 1739 u32 reg;
1740
1741 bp->advertising = ETHTOOL_ALL_FIBRE_SPEED | ADVERTISED_Autoneg;
1742
2726d6e1 1743 reg = bnx2_shmem_rd(bp, BNX2_PORT_HW_CFG_CONFIG);
deaf391b
MC		 1744 reg &= BNX2_PORT_HW_CFG_CFG_DFLT_LINK_MASK;
1745 if (reg == BNX2_PORT_HW_CFG_CFG_DFLT_LINK_1G) {
1746 bp->autoneg = 0;
1747 bp->req_line_speed = bp->line_speed = SPEED_1000;
1748 bp->req_duplex = DUPLEX_FULL;
1749 }
1750 } else
1751 bp->advertising = ETHTOOL_ALL_COPPER_SPEED | ADVERTISED_Autoneg;
1752}
1753
df149d70
MC		 1754static void
1755bnx2_send_heart_beat(struct bnx2 *bp)
1756{
1757 u32 msg;
1758 u32 addr;
1759
1760 spin_lock(&bp->indirect_lock);
1761 msg = (u32) (++bp->fw_drv_pulse_wr_seq & BNX2_DRV_PULSE_SEQ_MASK);
1762 addr = bp->shmem_base + BNX2_DRV_PULSE_MB;
1763 REG_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, addr);
1764 REG_WR(bp, BNX2_PCICFG_REG_WINDOW, msg);
1765 spin_unlock(&bp->indirect_lock);
1766}
1767
0d8a6571
MC		 1768static void
1769bnx2_remote_phy_event(struct bnx2 *bp)
1770{
1771 u32 msg;
1772 u8 link_up = bp->link_up;
1773 u8 old_port;
1774
2726d6e1 1775 msg = bnx2_shmem_rd(bp, BNX2_LINK_STATUS);
0d8a6571 1776
df149d70
MC		 1777 if (msg & BNX2_LINK_STATUS_HEART_BEAT_EXPIRED)
1778 bnx2_send_heart_beat(bp);
1779
1780 msg &= ~BNX2_LINK_STATUS_HEART_BEAT_EXPIRED;
1781
0d8a6571
MC		 1782 if ((msg & BNX2_LINK_STATUS_LINK_UP) == BNX2_LINK_STATUS_LINK_DOWN)
1783 bp->link_up = 0;
1784 else {
1785 u32 speed;
1786
1787 bp->link_up = 1;
1788 speed = msg & BNX2_LINK_STATUS_SPEED_MASK;
1789 bp->duplex = DUPLEX_FULL;
1790 switch (speed) {
1791 case BNX2_LINK_STATUS_10HALF:
1792 bp->duplex = DUPLEX_HALF;
1793 case BNX2_LINK_STATUS_10FULL:
1794 bp->line_speed = SPEED_10;
1795 break;
1796 case BNX2_LINK_STATUS_100HALF:
1797 bp->duplex = DUPLEX_HALF;
1798 case BNX2_LINK_STATUS_100BASE_T4:
1799 case BNX2_LINK_STATUS_100FULL:
1800 bp->line_speed = SPEED_100;
1801 break;
1802 case BNX2_LINK_STATUS_1000HALF:
1803 bp->duplex = DUPLEX_HALF;
1804 case BNX2_LINK_STATUS_1000FULL:
1805 bp->line_speed = SPEED_1000;
1806 break;
1807 case BNX2_LINK_STATUS_2500HALF:
1808 bp->duplex = DUPLEX_HALF;
1809 case BNX2_LINK_STATUS_2500FULL:
1810 bp->line_speed = SPEED_2500;
1811 break;
1812 default:
1813 bp->line_speed = 0;
1814 break;
1815 }
1816
0d8a6571
MC		 1817 bp->flow_ctrl = 0;
1818 if ((bp->autoneg & (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) !=
1819 (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) {
1820 if (bp->duplex == DUPLEX_FULL)
1821 bp->flow_ctrl = bp->req_flow_ctrl;
1822 } else {
1823 if (msg & BNX2_LINK_STATUS_TX_FC_ENABLED)
1824 bp->flow_ctrl |= FLOW_CTRL_TX;
1825 if (msg & BNX2_LINK_STATUS_RX_FC_ENABLED)
1826 bp->flow_ctrl |= FLOW_CTRL_RX;
1827 }
1828
1829 old_port = bp->phy_port;
1830 if (msg & BNX2_LINK_STATUS_SERDES_LINK)
1831 bp->phy_port = PORT_FIBRE;
1832 else
1833 bp->phy_port = PORT_TP;
1834
1835 if (old_port != bp->phy_port)
1836 bnx2_set_default_link(bp);
1837
0d8a6571
MC		 1838 }
1839 if (bp->link_up != link_up)
1840 bnx2_report_link(bp);
1841
1842 bnx2_set_mac_link(bp);
1843}
1844
1845static int
1846bnx2_set_remote_link(struct bnx2 *bp)
1847{
1848 u32 evt_code;
1849
2726d6e1 1850 evt_code = bnx2_shmem_rd(bp, BNX2_FW_EVT_CODE_MB);
0d8a6571
MC		 1851 switch (evt_code) {
1852 case BNX2_FW_EVT_CODE_LINK_EVENT:
1853 bnx2_remote_phy_event(bp);
1854 break;
1855 case BNX2_FW_EVT_CODE_SW_TIMER_EXPIRATION_EVENT:
1856 default:
df149d70 1857 bnx2_send_heart_beat(bp);
0d8a6571
MC		 1858 break;
1859 }
1860 return 0;
1861}
1862
b6016b76
MC		 1863static int
1864bnx2_setup_copper_phy(struct bnx2 *bp)
1865{
1866 u32 bmcr;
1867 u32 new_bmcr;
1868
ca58c3af 1869 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
b6016b76
MC		 1870
1871 if (bp->autoneg & AUTONEG_SPEED) {
1872 u32 adv_reg, adv1000_reg;
1873 u32 new_adv_reg = 0;
1874 u32 new_adv1000_reg = 0;
1875
ca58c3af 1876 bnx2_read_phy(bp, bp->mii_adv, &adv_reg);
b6016b76
MC		 1877 adv_reg &= (PHY_ALL_10_100_SPEED | ADVERTISE_PAUSE_CAP |
1878 ADVERTISE_PAUSE_ASYM);
1879
1880 bnx2_read_phy(bp, MII_CTRL1000, &adv1000_reg);
1881 adv1000_reg &= PHY_ALL_1000_SPEED;
1882
1883 if (bp->advertising & ADVERTISED_10baseT_Half)
1884 new_adv_reg |= ADVERTISE_10HALF;
1885 if (bp->advertising & ADVERTISED_10baseT_Full)
1886 new_adv_reg |= ADVERTISE_10FULL;
1887 if (bp->advertising & ADVERTISED_100baseT_Half)
1888 new_adv_reg |= ADVERTISE_100HALF;
1889 if (bp->advertising & ADVERTISED_100baseT_Full)
1890 new_adv_reg |= ADVERTISE_100FULL;
1891 if (bp->advertising & ADVERTISED_1000baseT_Full)
1892 new_adv1000_reg |= ADVERTISE_1000FULL;
6aa20a22 1893
b6016b76
MC		 1894 new_adv_reg |= ADVERTISE_CSMA;
1895
1896 new_adv_reg |= bnx2_phy_get_pause_adv(bp);
1897
1898 if ((adv1000_reg != new_adv1000_reg) ||
1899 (adv_reg != new_adv_reg) ||
1900 ((bmcr & BMCR_ANENABLE) == 0)) {
1901
ca58c3af 1902 bnx2_write_phy(bp, bp->mii_adv, new_adv_reg);
b6016b76 1903 bnx2_write_phy(bp, MII_CTRL1000, new_adv1000_reg);
ca58c3af 1904 bnx2_write_phy(bp, bp->mii_bmcr, BMCR_ANRESTART |
b6016b76
MC		 1905 BMCR_ANENABLE);
1906 }
1907 else if (bp->link_up) {
1908 /* Flow ctrl may have changed from auto to forced */
1909 /* or vice-versa. */
1910
1911 bnx2_resolve_flow_ctrl(bp);
1912 bnx2_set_mac_link(bp);
1913 }
1914 return 0;
1915 }
1916
1917 new_bmcr = 0;
1918 if (bp->req_line_speed == SPEED_100) {
1919 new_bmcr |= BMCR_SPEED100;
1920 }
1921 if (bp->req_duplex == DUPLEX_FULL) {
1922 new_bmcr |= BMCR_FULLDPLX;
1923 }
1924 if (new_bmcr != bmcr) {
1925 u32 bmsr;
b6016b76 1926
ca58c3af
MC		 1927 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
1928 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
6aa20a22 1929
b6016b76
MC		 1930 if (bmsr & BMSR_LSTATUS) {
1931 /* Force link down */
ca58c3af 1932 bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK);
a16dda0e
MC		 1933 spin_unlock_bh(&bp->phy_lock);
1934 msleep(50);
1935 spin_lock_bh(&bp->phy_lock);
1936
ca58c3af
MC		 1937 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
1938 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
b6016b76
MC		 1939 }
1940
ca58c3af 1941 bnx2_write_phy(bp, bp->mii_bmcr, new_bmcr);
b6016b76
MC		 1942
1943 /* Normally, the new speed is setup after the link has
1944 * gone down and up again. In some cases, link will not go
1945 * down so we need to set up the new speed here.
1946 */
1947 if (bmsr & BMSR_LSTATUS) {
1948 bp->line_speed = bp->req_line_speed;
1949 bp->duplex = bp->req_duplex;
1950 bnx2_resolve_flow_ctrl(bp);
1951 bnx2_set_mac_link(bp);
1952 }
27a005b8
MC		 1953 } else {
1954 bnx2_resolve_flow_ctrl(bp);
1955 bnx2_set_mac_link(bp);
b6016b76
MC		 1956 }
1957 return 0;
1958}
1959
1960static int
0d8a6571 1961bnx2_setup_phy(struct bnx2 *bp, u8 port)
b6016b76
MC		 1962{
1963 if (bp->loopback == MAC_LOOPBACK)
1964 return 0;
1965
583c28e5 1966 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
0d8a6571 1967 return (bnx2_setup_serdes_phy(bp, port));
b6016b76
MC		 1968 }
1969 else {
1970 return (bnx2_setup_copper_phy(bp));
1971 }
1972}
1973
27a005b8 1974static int
9a120bc5 1975bnx2_init_5709s_phy(struct bnx2 *bp, int reset_phy)
27a005b8
MC		 1976{
1977 u32 val;
1978
1979 bp->mii_bmcr = MII_BMCR + 0x10;
1980 bp->mii_bmsr = MII_BMSR + 0x10;
1981 bp->mii_bmsr1 = MII_BNX2_GP_TOP_AN_STATUS1;
1982 bp->mii_adv = MII_ADVERTISE + 0x10;
1983 bp->mii_lpa = MII_LPA + 0x10;
1984 bp->mii_up1 = MII_BNX2_OVER1G_UP1;
1985
1986 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_AER);
1987 bnx2_write_phy(bp, MII_BNX2_AER_AER, MII_BNX2_AER_AER_AN_MMD);
1988
1989 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
9a120bc5
MC		 1990 if (reset_phy)
1991 bnx2_reset_phy(bp);
27a005b8
MC		 1992
1993 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_SERDES_DIG);
1994
1995 bnx2_read_phy(bp, MII_BNX2_SERDES_DIG_1000XCTL1, &val);
1996 val &= ~MII_BNX2_SD_1000XCTL1_AUTODET;
1997 val |= MII_BNX2_SD_1000XCTL1_FIBER;
1998 bnx2_write_phy(bp, MII_BNX2_SERDES_DIG_1000XCTL1, val);
1999
2000 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_OVER1G);
2001 bnx2_read_phy(bp, MII_BNX2_OVER1G_UP1, &val);
583c28e5 2002 if (bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE)
27a005b8
MC		 2003 val |= BCM5708S_UP1_2G5;
2004 else
2005 val &= ~BCM5708S_UP1_2G5;
2006 bnx2_write_phy(bp, MII_BNX2_OVER1G_UP1, val);
2007
2008 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_BAM_NXTPG);
2009 bnx2_read_phy(bp, MII_BNX2_BAM_NXTPG_CTL, &val);
2010 val |= MII_BNX2_NXTPG_CTL_T2 | MII_BNX2_NXTPG_CTL_BAM;
2011 bnx2_write_phy(bp, MII_BNX2_BAM_NXTPG_CTL, val);
2012
2013 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_CL73_USERB0);
2014
2015 val = MII_BNX2_CL73_BAM_EN | MII_BNX2_CL73_BAM_STA_MGR_EN |
2016 MII_BNX2_CL73_BAM_NP_AFT_BP_EN;
2017 bnx2_write_phy(bp, MII_BNX2_CL73_BAM_CTL1, val);
2018
2019 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
2020
2021 return 0;
2022}
2023
b6016b76 2024static int
9a120bc5 2025bnx2_init_5708s_phy(struct bnx2 *bp, int reset_phy)
5b0c76ad
MC		 2026{
2027 u32 val;
2028
9a120bc5
MC		 2029 if (reset_phy)
2030 bnx2_reset_phy(bp);
27a005b8
MC		 2031
2032 bp->mii_up1 = BCM5708S_UP1;
2033
5b0c76ad
MC		 2034 bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG3);
2035 bnx2_write_phy(bp, BCM5708S_DIG_3_0, BCM5708S_DIG_3_0_USE_IEEE);
2036 bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG);
2037
2038 bnx2_read_phy(bp, BCM5708S_1000X_CTL1, &val);
2039 val |= BCM5708S_1000X_CTL1_FIBER_MODE | BCM5708S_1000X_CTL1_AUTODET_EN;
2040 bnx2_write_phy(bp, BCM5708S_1000X_CTL1, val);
2041
2042 bnx2_read_phy(bp, BCM5708S_1000X_CTL2, &val);
2043 val |= BCM5708S_1000X_CTL2_PLLEL_DET_EN;
2044 bnx2_write_phy(bp, BCM5708S_1000X_CTL2, val);
2045
583c28e5 2046 if (bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE) {
5b0c76ad
MC		 2047 bnx2_read_phy(bp, BCM5708S_UP1, &val);
2048 val |= BCM5708S_UP1_2G5;
2049 bnx2_write_phy(bp, BCM5708S_UP1, val);
2050 }
2051
2052 if ((CHIP_ID(bp) == CHIP_ID_5708_A0) ||
dda1e390
MC		 2053 (CHIP_ID(bp) == CHIP_ID_5708_B0) ||
2054 (CHIP_ID(bp) == CHIP_ID_5708_B1)) {
5b0c76ad
MC		 2055 /* increase tx signal amplitude */
2056 bnx2_write_phy(bp, BCM5708S_BLK_ADDR,
2057 BCM5708S_BLK_ADDR_TX_MISC);
2058 bnx2_read_phy(bp, BCM5708S_TX_ACTL1, &val);
2059 val &= ~BCM5708S_TX_ACTL1_DRIVER_VCM;
2060 bnx2_write_phy(bp, BCM5708S_TX_ACTL1, val);
2061 bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG);
2062 }
2063
2726d6e1 2064 val = bnx2_shmem_rd(bp, BNX2_PORT_HW_CFG_CONFIG) &
5b0c76ad
MC		 2065 BNX2_PORT_HW_CFG_CFG_TXCTL3_MASK;
2066
2067 if (val) {
2068 u32 is_backplane;
2069
2726d6e1 2070 is_backplane = bnx2_shmem_rd(bp, BNX2_SHARED_HW_CFG_CONFIG);
5b0c76ad
MC		 2071 if (is_backplane & BNX2_SHARED_HW_CFG_PHY_BACKPLANE) {
2072 bnx2_write_phy(bp, BCM5708S_BLK_ADDR,
2073 BCM5708S_BLK_ADDR_TX_MISC);
2074 bnx2_write_phy(bp, BCM5708S_TX_ACTL3, val);
2075 bnx2_write_phy(bp, BCM5708S_BLK_ADDR,
2076 BCM5708S_BLK_ADDR_DIG);
2077 }
2078 }
2079 return 0;
2080}
2081
2082static int
9a120bc5 2083bnx2_init_5706s_phy(struct bnx2 *bp, int reset_phy)
b6016b76 2084{
9a120bc5
MC		 2085 if (reset_phy)
2086 bnx2_reset_phy(bp);
27a005b8 2087
583c28e5 2088 bp->phy_flags &= ~BNX2_PHY_FLAG_PARALLEL_DETECT;
b6016b76 2089
59b47d8a
MC		 2090 if (CHIP_NUM(bp) == CHIP_NUM_5706)
2091 REG_WR(bp, BNX2_MISC_GP_HW_CTL0, 0x300);
b6016b76
MC		 2092
2093 if (bp->dev->mtu > 1500) {
2094 u32 val;
2095
2096 /* Set extended packet length bit */
2097 bnx2_write_phy(bp, 0x18, 0x7);
2098 bnx2_read_phy(bp, 0x18, &val);
2099 bnx2_write_phy(bp, 0x18, (val & 0xfff8) | 0x4000);
2100
2101 bnx2_write_phy(bp, 0x1c, 0x6c00);
2102 bnx2_read_phy(bp, 0x1c, &val);
2103 bnx2_write_phy(bp, 0x1c, (val & 0x3ff) | 0xec02);
2104 }
2105 else {
2106 u32 val;
2107
2108 bnx2_write_phy(bp, 0x18, 0x7);
2109 bnx2_read_phy(bp, 0x18, &val);
2110 bnx2_write_phy(bp, 0x18, val & ~0x4007);
2111
2112 bnx2_write_phy(bp, 0x1c, 0x6c00);
2113 bnx2_read_phy(bp, 0x1c, &val);
2114 bnx2_write_phy(bp, 0x1c, (val & 0x3fd) | 0xec00);
2115 }
2116
2117 return 0;
2118}
2119
2120static int
9a120bc5 2121bnx2_init_copper_phy(struct bnx2 *bp, int reset_phy)
b6016b76 2122{
5b0c76ad
MC		 2123 u32 val;
2124
9a120bc5
MC		 2125 if (reset_phy)
2126 bnx2_reset_phy(bp);
27a005b8 2127
583c28e5 2128 if (bp->phy_flags & BNX2_PHY_FLAG_CRC_FIX) {
b6016b76
MC		 2129 bnx2_write_phy(bp, 0x18, 0x0c00);
2130 bnx2_write_phy(bp, 0x17, 0x000a);
2131 bnx2_write_phy(bp, 0x15, 0x310b);
2132 bnx2_write_phy(bp, 0x17, 0x201f);
2133 bnx2_write_phy(bp, 0x15, 0x9506);
2134 bnx2_write_phy(bp, 0x17, 0x401f);
2135 bnx2_write_phy(bp, 0x15, 0x14e2);
2136 bnx2_write_phy(bp, 0x18, 0x0400);
2137 }
2138
583c28e5 2139 if (bp->phy_flags & BNX2_PHY_FLAG_DIS_EARLY_DAC) {
b659f44e
MC		 2140 bnx2_write_phy(bp, MII_BNX2_DSP_ADDRESS,
2141 MII_BNX2_DSP_EXPAND_REG | 0x8);
2142 bnx2_read_phy(bp, MII_BNX2_DSP_RW_PORT, &val);
2143 val &= ~(1 << 8);
2144 bnx2_write_phy(bp, MII_BNX2_DSP_RW_PORT, val);
2145 }
2146
b6016b76 2147 if (bp->dev->mtu > 1500) {
b6016b76
MC		 2148 /* Set extended packet length bit */
2149 bnx2_write_phy(bp, 0x18, 0x7);
2150 bnx2_read_phy(bp, 0x18, &val);
2151 bnx2_write_phy(bp, 0x18, val | 0x4000);
2152
2153 bnx2_read_phy(bp, 0x10, &val);
2154 bnx2_write_phy(bp, 0x10, val | 0x1);
2155 }
2156 else {
b6016b76
MC		 2157 bnx2_write_phy(bp, 0x18, 0x7);
2158 bnx2_read_phy(bp, 0x18, &val);
2159 bnx2_write_phy(bp, 0x18, val & ~0x4007);
2160
2161 bnx2_read_phy(bp, 0x10, &val);
2162 bnx2_write_phy(bp, 0x10, val & ~0x1);
2163 }
2164
5b0c76ad
MC		 2165 /* ethernet@wirespeed */
2166 bnx2_write_phy(bp, 0x18, 0x7007);
2167 bnx2_read_phy(bp, 0x18, &val);
2168 bnx2_write_phy(bp, 0x18, val | (1 << 15) | (1 << 4));
b6016b76
MC		 2169 return 0;
2170}
2171
2172
2173static int
9a120bc5 2174bnx2_init_phy(struct bnx2 *bp, int reset_phy)
b6016b76
MC		 2175{
2176 u32 val;
2177 int rc = 0;
2178
583c28e5
MC		 2179 bp->phy_flags &= ~BNX2_PHY_FLAG_INT_MODE_MASK;
2180 bp->phy_flags |= BNX2_PHY_FLAG_INT_MODE_LINK_READY;
b6016b76 2181
ca58c3af
MC		 2182 bp->mii_bmcr = MII_BMCR;
2183 bp->mii_bmsr = MII_BMSR;
27a005b8 2184 bp->mii_bmsr1 = MII_BMSR;
ca58c3af
MC		 2185 bp->mii_adv = MII_ADVERTISE;
2186 bp->mii_lpa = MII_LPA;
2187
b6016b76
MC		 2188 REG_WR(bp, BNX2_EMAC_ATTENTION_ENA, BNX2_EMAC_ATTENTION_ENA_LINK);
2189
583c28e5 2190 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
0d8a6571
MC		 2191 goto setup_phy;
2192
b6016b76
MC		 2193 bnx2_read_phy(bp, MII_PHYSID1, &val);
2194 bp->phy_id = val << 16;
2195 bnx2_read_phy(bp, MII_PHYSID2, &val);
2196 bp->phy_id |= val & 0xffff;
2197
583c28e5 2198 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
5b0c76ad 2199 if (CHIP_NUM(bp) == CHIP_NUM_5706)
9a120bc5 2200 rc = bnx2_init_5706s_phy(bp, reset_phy);
5b0c76ad 2201 else if (CHIP_NUM(bp) == CHIP_NUM_5708)
9a120bc5 2202 rc = bnx2_init_5708s_phy(bp, reset_phy);
27a005b8 2203 else if (CHIP_NUM(bp) == CHIP_NUM_5709)
9a120bc5 2204 rc = bnx2_init_5709s_phy(bp, reset_phy);
b6016b76
MC		 2205 }
2206 else {
9a120bc5 2207 rc = bnx2_init_copper_phy(bp, reset_phy);
b6016b76
MC		 2208 }
2209
0d8a6571
MC		 2210setup_phy:
2211 if (!rc)
2212 rc = bnx2_setup_phy(bp, bp->phy_port);
b6016b76
MC		 2213
2214 return rc;
2215}
2216
2217static int
2218bnx2_set_mac_loopback(struct bnx2 *bp)
2219{
2220 u32 mac_mode;
2221
2222 mac_mode = REG_RD(bp, BNX2_EMAC_MODE);
2223 mac_mode &= ~BNX2_EMAC_MODE_PORT;
2224 mac_mode |= BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK;
2225 REG_WR(bp, BNX2_EMAC_MODE, mac_mode);
2226 bp->link_up = 1;
2227 return 0;
2228}
2229
bc5a0690
MC		 2230static int bnx2_test_link(struct bnx2 *);
2231
2232static int
2233bnx2_set_phy_loopback(struct bnx2 *bp)
2234{
2235 u32 mac_mode;
2236 int rc, i;
2237
2238 spin_lock_bh(&bp->phy_lock);
ca58c3af 2239 rc = bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK | BMCR_FULLDPLX |
bc5a0690
MC		 2240 BMCR_SPEED1000);
2241 spin_unlock_bh(&bp->phy_lock);
2242 if (rc)
2243 return rc;
2244
2245 for (i = 0; i < 10; i++) {
2246 if (bnx2_test_link(bp) == 0)
2247 break;
80be4434 2248 msleep(100);
bc5a0690
MC		 2249 }
2250
2251 mac_mode = REG_RD(bp, BNX2_EMAC_MODE);
2252 mac_mode &= ~(BNX2_EMAC_MODE_PORT | BNX2_EMAC_MODE_HALF_DUPLEX |
2253 BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK |
59b47d8a 2254 BNX2_EMAC_MODE_25G_MODE);
bc5a0690
MC		 2255
2256 mac_mode |= BNX2_EMAC_MODE_PORT_GMII;
2257 REG_WR(bp, BNX2_EMAC_MODE, mac_mode);
2258 bp->link_up = 1;
2259 return 0;
2260}
2261
b6016b76 2262static int
a2f13890 2263bnx2_fw_sync(struct bnx2 *bp, u32 msg_data, int ack, int silent)
b6016b76
MC		 2264{
2265 int i;
2266 u32 val;
2267
b6016b76
MC		 2268 bp->fw_wr_seq++;
2269 msg_data |= bp->fw_wr_seq;
2270
2726d6e1 2271 bnx2_shmem_wr(bp, BNX2_DRV_MB, msg_data);
b6016b76 2272
a2f13890
MC		 2273 if (!ack)
2274 return 0;
2275
b6016b76 2276 /* wait for an acknowledgement. */
b090ae2b
MC		 2277 for (i = 0; i < (FW_ACK_TIME_OUT_MS / 10); i++) {
2278 msleep(10);
b6016b76 2279
2726d6e1 2280 val = bnx2_shmem_rd(bp, BNX2_FW_MB);
b6016b76
MC		 2281
2282 if ((val & BNX2_FW_MSG_ACK) == (msg_data & BNX2_DRV_MSG_SEQ))
2283 break;
2284 }
b090ae2b
MC		 2285 if ((msg_data & BNX2_DRV_MSG_DATA) == BNX2_DRV_MSG_DATA_WAIT0)
2286 return 0;
b6016b76
MC		 2287
2288 /* If we timed out, inform the firmware that this is the case. */
b090ae2b
MC		 2289 if ((val & BNX2_FW_MSG_ACK) != (msg_data & BNX2_DRV_MSG_SEQ)) {
2290 if (!silent)
2291 printk(KERN_ERR PFX "fw sync timeout, reset code = "
2292 "%x\n", msg_data);
b6016b76
MC		 2293
2294 msg_data &= ~BNX2_DRV_MSG_CODE;
2295 msg_data |= BNX2_DRV_MSG_CODE_FW_TIMEOUT;
2296
2726d6e1 2297 bnx2_shmem_wr(bp, BNX2_DRV_MB, msg_data);
b6016b76 2298
b6016b76
MC		 2299 return -EBUSY;
2300 }
2301
b090ae2b
MC		 2302 if ((val & BNX2_FW_MSG_STATUS_MASK) != BNX2_FW_MSG_STATUS_OK)
2303 return -EIO;
2304
b6016b76
MC		 2305 return 0;
2306}
2307
59b47d8a
MC		 2308static int
2309bnx2_init_5709_context(struct bnx2 *bp)
2310{
2311 int i, ret = 0;
2312 u32 val;
2313
2314 val = BNX2_CTX_COMMAND_ENABLED | BNX2_CTX_COMMAND_MEM_INIT | (1 << 12);
2315 val |= (BCM_PAGE_BITS - 8) << 16;
2316 REG_WR(bp, BNX2_CTX_COMMAND, val);
641bdcd5
MC		 2317 for (i = 0; i < 10; i++) {
2318 val = REG_RD(bp, BNX2_CTX_COMMAND);
2319 if (!(val & BNX2_CTX_COMMAND_MEM_INIT))
2320 break;
2321 udelay(2);
2322 }
2323 if (val & BNX2_CTX_COMMAND_MEM_INIT)
2324 return -EBUSY;
2325
59b47d8a
MC		 2326 for (i = 0; i < bp->ctx_pages; i++) {
2327 int j;
2328
352f7687
MC		 2329 if (bp->ctx_blk[i])
2330 memset(bp->ctx_blk[i], 0, BCM_PAGE_SIZE);
2331 else
2332 return -ENOMEM;
2333
59b47d8a
MC		 2334 REG_WR(bp, BNX2_CTX_HOST_PAGE_TBL_DATA0,
2335 (bp->ctx_blk_mapping[i] & 0xffffffff) |
2336 BNX2_CTX_HOST_PAGE_TBL_DATA0_VALID);
2337 REG_WR(bp, BNX2_CTX_HOST_PAGE_TBL_DATA1,
2338 (u64) bp->ctx_blk_mapping[i] >> 32);
2339 REG_WR(bp, BNX2_CTX_HOST_PAGE_TBL_CTRL, i |
2340 BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ);
2341 for (j = 0; j < 10; j++) {
2342
2343 val = REG_RD(bp, BNX2_CTX_HOST_PAGE_TBL_CTRL);
2344 if (!(val & BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ))
2345 break;
2346 udelay(5);
2347 }
2348 if (val & BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ) {
2349 ret = -EBUSY;
2350 break;
2351 }
2352 }
2353 return ret;
2354}
2355
b6016b76
MC		 2356static void
2357bnx2_init_context(struct bnx2 *bp)
2358{
2359 u32 vcid;
2360
2361 vcid = 96;
2362 while (vcid) {
2363 u32 vcid_addr, pcid_addr, offset;
7947b20e 2364 int i;
b6016b76
MC		 2365
2366 vcid--;
2367
2368 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
2369 u32 new_vcid;
2370
2371 vcid_addr = GET_PCID_ADDR(vcid);
2372 if (vcid & 0x8) {
2373 new_vcid = 0x60 + (vcid & 0xf0) + (vcid & 0x7);
2374 }
2375 else {
2376 new_vcid = vcid;
2377 }
2378 pcid_addr = GET_PCID_ADDR(new_vcid);
2379 }
2380 else {
2381 vcid_addr = GET_CID_ADDR(vcid);
2382 pcid_addr = vcid_addr;
2383 }
2384
7947b20e
MC		 2385 for (i = 0; i < (CTX_SIZE / PHY_CTX_SIZE); i++) {
2386 vcid_addr += (i << PHY_CTX_SHIFT);
2387 pcid_addr += (i << PHY_CTX_SHIFT);
b6016b76 2388
5d5d0015 2389 REG_WR(bp, BNX2_CTX_VIRT_ADDR, vcid_addr);
7947b20e 2390 REG_WR(bp, BNX2_CTX_PAGE_TBL, pcid_addr);
b6016b76 2391
7947b20e
MC		 2392 /* Zero out the context. */
2393 for (offset = 0; offset < PHY_CTX_SIZE; offset += 4)
62a8313c 2394 bnx2_ctx_wr(bp, vcid_addr, offset, 0);
7947b20e 2395 }
b6016b76
MC		 2396 }
2397}
2398
2399static int
2400bnx2_alloc_bad_rbuf(struct bnx2 *bp)
2401{
2402 u16 *good_mbuf;
2403 u32 good_mbuf_cnt;
2404 u32 val;
2405
2406 good_mbuf = kmalloc(512 * sizeof(u16), GFP_KERNEL);
2407 if (good_mbuf == NULL) {
2408 printk(KERN_ERR PFX "Failed to allocate memory in "
2409 "bnx2_alloc_bad_rbuf\n");
2410 return -ENOMEM;
2411 }
2412
2413 REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS,
2414 BNX2_MISC_ENABLE_SET_BITS_RX_MBUF_ENABLE);
2415
2416 good_mbuf_cnt = 0;
2417
2418 /* Allocate a bunch of mbufs and save the good ones in an array. */
2726d6e1 2419 val = bnx2_reg_rd_ind(bp, BNX2_RBUF_STATUS1);
b6016b76 2420 while (val & BNX2_RBUF_STATUS1_FREE_COUNT) {
2726d6e1
MC		 2421 bnx2_reg_wr_ind(bp, BNX2_RBUF_COMMAND,
2422 BNX2_RBUF_COMMAND_ALLOC_REQ);
b6016b76 2423
2726d6e1 2424 val = bnx2_reg_rd_ind(bp, BNX2_RBUF_FW_BUF_ALLOC);
b6016b76
MC		 2425
2426 val &= BNX2_RBUF_FW_BUF_ALLOC_VALUE;
2427
2428 /* The addresses with Bit 9 set are bad memory blocks. */
2429 if (!(val & (1 << 9))) {
2430 good_mbuf[good_mbuf_cnt] = (u16) val;
2431 good_mbuf_cnt++;
2432 }
2433
2726d6e1 2434 val = bnx2_reg_rd_ind(bp, BNX2_RBUF_STATUS1);
b6016b76
MC		 2435 }
2436
2437 /* Free the good ones back to the mbuf pool thus discarding
2438 * all the bad ones. */
2439 while (good_mbuf_cnt) {
2440 good_mbuf_cnt--;
2441
2442 val = good_mbuf[good_mbuf_cnt];
2443 val = (val << 9) | val | 1;
2444
2726d6e1 2445 bnx2_reg_wr_ind(bp, BNX2_RBUF_FW_BUF_FREE, val);
b6016b76
MC		 2446 }
2447 kfree(good_mbuf);
2448 return 0;
2449}
2450
2451static void
5fcaed01 2452bnx2_set_mac_addr(struct bnx2 *bp, u8 *mac_addr, u32 pos)
b6016b76
MC		 2453{
2454 u32 val;
b6016b76
MC		 2455
2456 val = (mac_addr[0] << 8) | mac_addr[1];
2457
5fcaed01 2458 REG_WR(bp, BNX2_EMAC_MAC_MATCH0 + (pos * 8), val);
b6016b76 2459
6aa20a22 2460 val = (mac_addr[2] << 24) | (mac_addr[3] << 16) |
b6016b76
MC		 2461 (mac_addr[4] << 8) | mac_addr[5];
2462
5fcaed01 2463 REG_WR(bp, BNX2_EMAC_MAC_MATCH1 + (pos * 8), val);
b6016b76
MC		 2464}
2465
47bf4246 2466static inline int
bb4f98ab 2467bnx2_alloc_rx_page(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr, u16 index)
47bf4246
MC		 2468{
2469 dma_addr_t mapping;
bb4f98ab 2470 struct sw_pg *rx_pg = &rxr->rx_pg_ring[index];
47bf4246 2471 struct rx_bd *rxbd =
bb4f98ab 2472 &rxr->rx_pg_desc_ring[RX_RING(index)][RX_IDX(index)];
47bf4246
MC		 2473 struct page *page = alloc_page(GFP_ATOMIC);
2474
2475 if (!page)
2476 return -ENOMEM;
2477 mapping = pci_map_page(bp->pdev, page, 0, PAGE_SIZE,
2478 PCI_DMA_FROMDEVICE);
3d16af86
BL		 2479 if (pci_dma_mapping_error(bp->pdev, mapping)) {
2480 __free_page(page);
2481 return -EIO;
2482 }
2483
47bf4246
MC		 2484 rx_pg->page = page;
2485 pci_unmap_addr_set(rx_pg, mapping, mapping);
2486 rxbd->rx_bd_haddr_hi = (u64) mapping >> 32;
2487 rxbd->rx_bd_haddr_lo = (u64) mapping & 0xffffffff;
2488 return 0;
2489}
2490
2491static void
bb4f98ab 2492bnx2_free_rx_page(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr, u16 index)
47bf4246 2493{
bb4f98ab 2494 struct sw_pg *rx_pg = &rxr->rx_pg_ring[index];
47bf4246
MC		 2495 struct page *page = rx_pg->page;
2496
2497 if (!page)
2498 return;
2499
2500 pci_unmap_page(bp->pdev, pci_unmap_addr(rx_pg, mapping), PAGE_SIZE,
2501 PCI_DMA_FROMDEVICE);
2502
2503 __free_page(page);
2504 rx_pg->page = NULL;
2505}
2506
b6016b76 2507static inline int
bb4f98ab 2508bnx2_alloc_rx_skb(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr, u16 index)
b6016b76
MC		 2509{
2510 struct sk_buff *skb;
bb4f98ab 2511 struct sw_bd *rx_buf = &rxr->rx_buf_ring[index];
b6016b76 2512 dma_addr_t mapping;
bb4f98ab 2513 struct rx_bd *rxbd = &rxr->rx_desc_ring[RX_RING(index)][RX_IDX(index)];
b6016b76
MC		 2514 unsigned long align;
2515
932f3772 2516 skb = netdev_alloc_skb(bp->dev, bp->rx_buf_size);
b6016b76
MC		 2517 if (skb == NULL) {
2518 return -ENOMEM;
2519 }
2520
59b47d8a
MC		 2521 if (unlikely((align = (unsigned long) skb->data & (BNX2_RX_ALIGN - 1))))
2522 skb_reserve(skb, BNX2_RX_ALIGN - align);
b6016b76 2523
b6016b76
MC		 2524 mapping = pci_map_single(bp->pdev, skb->data, bp->rx_buf_use_size,
2525 PCI_DMA_FROMDEVICE);
3d16af86
BL		 2526 if (pci_dma_mapping_error(bp->pdev, mapping)) {
2527 dev_kfree_skb(skb);
2528 return -EIO;
2529 }
b6016b76
MC		 2530
2531 rx_buf->skb = skb;
2532 pci_unmap_addr_set(rx_buf, mapping, mapping);
2533
2534 rxbd->rx_bd_haddr_hi = (u64) mapping >> 32;
2535 rxbd->rx_bd_haddr_lo = (u64) mapping & 0xffffffff;
2536
bb4f98ab 2537 rxr->rx_prod_bseq += bp->rx_buf_use_size;
b6016b76
MC		 2538
2539 return 0;
2540}
2541
da3e4fbe 2542static int
35efa7c1 2543bnx2_phy_event_is_set(struct bnx2 *bp, struct bnx2_napi *bnapi, u32 event)
b6016b76 2544{
43e80b89 2545 struct status_block *sblk = bnapi->status_blk.msi;
b6016b76 2546 u32 new_link_state, old_link_state;
da3e4fbe 2547 int is_set = 1;
b6016b76 2548
da3e4fbe
MC		 2549 new_link_state = sblk->status_attn_bits & event;
2550 old_link_state = sblk->status_attn_bits_ack & event;
b6016b76 2551 if (new_link_state != old_link_state) {
da3e4fbe
MC		 2552 if (new_link_state)
2553 REG_WR(bp, BNX2_PCICFG_STATUS_BIT_SET_CMD, event);
2554 else
2555 REG_WR(bp, BNX2_PCICFG_STATUS_BIT_CLEAR_CMD, event);
2556 } else
2557 is_set = 0;
2558
2559 return is_set;
2560}
2561
2562static void
35efa7c1 2563bnx2_phy_int(struct bnx2 *bp, struct bnx2_napi *bnapi)
da3e4fbe 2564{
74ecc62d
MC		 2565 spin_lock(&bp->phy_lock);
2566
2567 if (bnx2_phy_event_is_set(bp, bnapi, STATUS_ATTN_BITS_LINK_STATE))
b6016b76 2568 bnx2_set_link(bp);
35efa7c1 2569 if (bnx2_phy_event_is_set(bp, bnapi, STATUS_ATTN_BITS_TIMER_ABORT))
0d8a6571
MC		 2570 bnx2_set_remote_link(bp);
2571
74ecc62d
MC		 2572 spin_unlock(&bp->phy_lock);
2573
b6016b76
MC		 2574}
2575
ead7270b 2576static inline u16
35efa7c1 2577bnx2_get_hw_tx_cons(struct bnx2_napi *bnapi)
ead7270b
MC		 2578{
2579 u16 cons;
2580
43e80b89
MC		 2581 /* Tell compiler that status block fields can change. */
2582 barrier();
2583 cons = *bnapi->hw_tx_cons_ptr;
ead7270b
MC		 2584 if (unlikely((cons & MAX_TX_DESC_CNT) == MAX_TX_DESC_CNT))
2585 cons++;
2586 return cons;
2587}
2588
57851d84
MC		 2589static int
2590bnx2_tx_int(struct bnx2 *bp, struct bnx2_napi *bnapi, int budget)
b6016b76 2591{
35e9010b 2592 struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
b6016b76 2593 u16 hw_cons, sw_cons, sw_ring_cons;
706bf240
BL		 2594 int tx_pkt = 0, index;
2595 struct netdev_queue *txq;
2596
2597 index = (bnapi - bp->bnx2_napi);
2598 txq = netdev_get_tx_queue(bp->dev, index);
b6016b76 2599
35efa7c1 2600 hw_cons = bnx2_get_hw_tx_cons(bnapi);
35e9010b 2601 sw_cons = txr->tx_cons;
b6016b76
MC		 2602
2603 while (sw_cons != hw_cons) {
3d16af86 2604 struct sw_tx_bd *tx_buf;
b6016b76
MC		 2605 struct sk_buff *skb;
2606 int i, last;
2607
2608 sw_ring_cons = TX_RING_IDX(sw_cons);
2609
35e9010b 2610 tx_buf = &txr->tx_buf_ring[sw_ring_cons];
b6016b76 2611 skb = tx_buf->skb;
1d39ed56 2612
b6016b76 2613 /* partial BD completions possible with TSO packets */
89114afd 2614 if (skb_is_gso(skb)) {
b6016b76
MC		 2615 u16 last_idx, last_ring_idx;
2616
2617 last_idx = sw_cons +
2618 skb_shinfo(skb)->nr_frags + 1;
2619 last_ring_idx = sw_ring_cons +
2620 skb_shinfo(skb)->nr_frags + 1;
2621 if (unlikely(last_ring_idx >= MAX_TX_DESC_CNT)) {
2622 last_idx++;
2623 }
2624 if (((s16) ((s16) last_idx - (s16) hw_cons)) > 0) {
2625 break;
2626 }
2627 }
1d39ed56 2628
3d16af86 2629 skb_dma_unmap(&bp->pdev->dev, skb, DMA_TO_DEVICE);
b6016b76
MC		 2630
2631 tx_buf->skb = NULL;
2632 last = skb_shinfo(skb)->nr_frags;
2633
2634 for (i = 0; i < last; i++) {
2635 sw_cons = NEXT_TX_BD(sw_cons);
b6016b76
MC		 2636 }
2637
2638 sw_cons = NEXT_TX_BD(sw_cons);
2639
745720e5 2640 dev_kfree_skb(skb);
57851d84
MC		 2641 tx_pkt++;
2642 if (tx_pkt == budget)
2643 break;
b6016b76 2644
35efa7c1 2645 hw_cons = bnx2_get_hw_tx_cons(bnapi);
b6016b76
MC		 2646 }
2647
35e9010b
MC		 2648 txr->hw_tx_cons = hw_cons;
2649 txr->tx_cons = sw_cons;
706bf240 2650
2f8af120 2651 /* Need to make the tx_cons update visible to bnx2_start_xmit()
706bf240 2652 * before checking for netif_tx_queue_stopped(). Without the
2f8af120
MC		 2653 * memory barrier, there is a small possibility that bnx2_start_xmit()
2654 * will miss it and cause the queue to be stopped forever.
2655 */
2656 smp_mb();
b6016b76 2657
706bf240 2658 if (unlikely(netif_tx_queue_stopped(txq)) &&
35e9010b 2659 (bnx2_tx_avail(bp, txr) > bp->tx_wake_thresh)) {
706bf240
BL		 2660 __netif_tx_lock(txq, smp_processor_id());
2661 if ((netif_tx_queue_stopped(txq)) &&
35e9010b 2662 (bnx2_tx_avail(bp, txr) > bp->tx_wake_thresh))
706bf240
BL		 2663 netif_tx_wake_queue(txq);
2664 __netif_tx_unlock(txq);
b6016b76 2665 }
706bf240 2666
57851d84 2667 return tx_pkt;
b6016b76
MC		 2668}
2669
1db82f2a 2670static void
bb4f98ab 2671bnx2_reuse_rx_skb_pages(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr,
a1f60190 2672 struct sk_buff *skb, int count)
1db82f2a
MC		 2673{
2674 struct sw_pg *cons_rx_pg, *prod_rx_pg;
2675 struct rx_bd *cons_bd, *prod_bd;
1db82f2a 2676 int i;
3d16af86 2677 u16 hw_prod, prod;
bb4f98ab 2678 u16 cons = rxr->rx_pg_cons;
1db82f2a 2679
3d16af86
BL		 2680 cons_rx_pg = &rxr->rx_pg_ring[cons];
2681
2682 /* The caller was unable to allocate a new page to replace the
2683 * last one in the frags array, so we need to recycle that page
2684 * and then free the skb.
2685 */
2686 if (skb) {
2687 struct page *page;
2688 struct skb_shared_info *shinfo;
2689
2690 shinfo = skb_shinfo(skb);
2691 shinfo->nr_frags--;
2692 page = shinfo->frags[shinfo->nr_frags].page;
2693 shinfo->frags[shinfo->nr_frags].page = NULL;
2694
2695 cons_rx_pg->page = page;
2696 dev_kfree_skb(skb);
2697 }
2698
2699 hw_prod = rxr->rx_pg_prod;
2700
1db82f2a
MC		 2701 for (i = 0; i < count; i++) {
2702 prod = RX_PG_RING_IDX(hw_prod);
2703
bb4f98ab
MC		 2704 prod_rx_pg = &rxr->rx_pg_ring[prod];
2705 cons_rx_pg = &rxr->rx_pg_ring[cons];
2706 cons_bd = &rxr->rx_pg_desc_ring[RX_RING(cons)][RX_IDX(cons)];
2707 prod_bd = &rxr->rx_pg_desc_ring[RX_RING(prod)][RX_IDX(prod)];
1db82f2a 2708
1db82f2a
MC		 2709 if (prod != cons) {
2710 prod_rx_pg->page = cons_rx_pg->page;
2711 cons_rx_pg->page = NULL;
2712 pci_unmap_addr_set(prod_rx_pg, mapping,
2713 pci_unmap_addr(cons_rx_pg, mapping));
2714
2715 prod_bd->rx_bd_haddr_hi = cons_bd->rx_bd_haddr_hi;
2716 prod_bd->rx_bd_haddr_lo = cons_bd->rx_bd_haddr_lo;
2717
2718 }
2719 cons = RX_PG_RING_IDX(NEXT_RX_BD(cons));
2720 hw_prod = NEXT_RX_BD(hw_prod);
2721 }
bb4f98ab
MC		 2722 rxr->rx_pg_prod = hw_prod;
2723 rxr->rx_pg_cons = cons;
1db82f2a
MC		 2724}
2725
b6016b76 2726static inline void
bb4f98ab
MC		 2727bnx2_reuse_rx_skb(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr,
2728 struct sk_buff *skb, u16 cons, u16 prod)
b6016b76 2729{
236b6394
MC		 2730 struct sw_bd *cons_rx_buf, *prod_rx_buf;
2731 struct rx_bd *cons_bd, *prod_bd;
2732
bb4f98ab
MC		 2733 cons_rx_buf = &rxr->rx_buf_ring[cons];
2734 prod_rx_buf = &rxr->rx_buf_ring[prod];
b6016b76
MC		 2735
2736 pci_dma_sync_single_for_device(bp->pdev,
2737 pci_unmap_addr(cons_rx_buf, mapping),
601d3d18 2738 BNX2_RX_OFFSET + BNX2_RX_COPY_THRESH, PCI_DMA_FROMDEVICE);
b6016b76 2739
bb4f98ab 2740 rxr->rx_prod_bseq += bp->rx_buf_use_size;
b6016b76 2741
236b6394 2742 prod_rx_buf->skb = skb;
b6016b76 2743
236b6394
MC		 2744 if (cons == prod)
2745 return;
b6016b76 2746
236b6394
MC		 2747 pci_unmap_addr_set(prod_rx_buf, mapping,
2748 pci_unmap_addr(cons_rx_buf, mapping));
2749
bb4f98ab
MC		 2750 cons_bd = &rxr->rx_desc_ring[RX_RING(cons)][RX_IDX(cons)];
2751 prod_bd = &rxr->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)];
236b6394
MC		 2752 prod_bd->rx_bd_haddr_hi = cons_bd->rx_bd_haddr_hi;
2753 prod_bd->rx_bd_haddr_lo = cons_bd->rx_bd_haddr_lo;
b6016b76
MC		 2754}
2755
85833c62 2756static int
bb4f98ab 2757bnx2_rx_skb(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr, struct sk_buff *skb,
a1f60190
MC		 2758 unsigned int len, unsigned int hdr_len, dma_addr_t dma_addr,
2759 u32 ring_idx)
85833c62
MC		 2760{
2761 int err;
2762 u16 prod = ring_idx & 0xffff;
2763
bb4f98ab 2764 err = bnx2_alloc_rx_skb(bp, rxr, prod);
85833c62 2765 if (unlikely(err)) {
bb4f98ab 2766 bnx2_reuse_rx_skb(bp, rxr, skb, (u16) (ring_idx >> 16), prod);
1db82f2a
MC		 2767 if (hdr_len) {
2768 unsigned int raw_len = len + 4;
2769 int pages = PAGE_ALIGN(raw_len - hdr_len) >> PAGE_SHIFT;
2770
bb4f98ab 2771 bnx2_reuse_rx_skb_pages(bp, rxr, NULL, pages);
1db82f2a 2772 }
85833c62
MC		 2773 return err;
2774 }
2775
d89cb6af 2776 skb_reserve(skb, BNX2_RX_OFFSET);
85833c62
MC		 2777 pci_unmap_single(bp->pdev, dma_addr, bp->rx_buf_use_size,
2778 PCI_DMA_FROMDEVICE);
2779
1db82f2a
MC		 2780 if (hdr_len == 0) {
2781 skb_put(skb, len);
2782 return 0;
2783 } else {
2784 unsigned int i, frag_len, frag_size, pages;
2785 struct sw_pg *rx_pg;
bb4f98ab
MC		 2786 u16 pg_cons = rxr->rx_pg_cons;
2787 u16 pg_prod = rxr->rx_pg_prod;
1db82f2a
MC		 2788
2789 frag_size = len + 4 - hdr_len;
2790 pages = PAGE_ALIGN(frag_size) >> PAGE_SHIFT;
2791 skb_put(skb, hdr_len);
2792
2793 for (i = 0; i < pages; i++) {
3d16af86
BL		 2794 dma_addr_t mapping_old;
2795
1db82f2a
MC		 2796 frag_len = min(frag_size, (unsigned int) PAGE_SIZE);
2797 if (unlikely(frag_len <= 4)) {
2798 unsigned int tail = 4 - frag_len;
2799
bb4f98ab
MC		 2800 rxr->rx_pg_cons = pg_cons;
2801 rxr->rx_pg_prod = pg_prod;
2802 bnx2_reuse_rx_skb_pages(bp, rxr, NULL,
a1f60190 2803 pages - i);
1db82f2a
MC		 2804 skb->len -= tail;
2805 if (i == 0) {
2806 skb->tail -= tail;
2807 } else {
2808 skb_frag_t *frag =
2809 &skb_shinfo(skb)->frags[i - 1];
2810 frag->size -= tail;
2811 skb->data_len -= tail;
2812 skb->truesize -= tail;
2813 }
2814 return 0;
2815 }
bb4f98ab 2816 rx_pg = &rxr->rx_pg_ring[pg_cons];
1db82f2a 2817
3d16af86
BL		 2818 /* Don't unmap yet. If we're unable to allocate a new
2819 * page, we need to recycle the page and the DMA addr.
2820 */
2821 mapping_old = pci_unmap_addr(rx_pg, mapping);
1db82f2a
MC		 2822 if (i == pages - 1)
2823 frag_len -= 4;
2824
2825 skb_fill_page_desc(skb, i, rx_pg->page, 0, frag_len);
2826 rx_pg->page = NULL;
2827
bb4f98ab
MC		 2828 err = bnx2_alloc_rx_page(bp, rxr,
2829 RX_PG_RING_IDX(pg_prod));
1db82f2a 2830 if (unlikely(err)) {
bb4f98ab
MC		 2831 rxr->rx_pg_cons = pg_cons;
2832 rxr->rx_pg_prod = pg_prod;
2833 bnx2_reuse_rx_skb_pages(bp, rxr, skb,
a1f60190 2834 pages - i);
1db82f2a
MC		 2835 return err;
2836 }
2837
3d16af86
BL		 2838 pci_unmap_page(bp->pdev, mapping_old,
2839 PAGE_SIZE, PCI_DMA_FROMDEVICE);
2840
1db82f2a
MC		 2841 frag_size -= frag_len;
2842 skb->data_len += frag_len;
2843 skb->truesize += frag_len;
2844 skb->len += frag_len;
2845
2846 pg_prod = NEXT_RX_BD(pg_prod);
2847 pg_cons = RX_PG_RING_IDX(NEXT_RX_BD(pg_cons));
2848 }
bb4f98ab
MC		 2849 rxr->rx_pg_prod = pg_prod;
2850 rxr->rx_pg_cons = pg_cons;
1db82f2a 2851 }
85833c62
MC		 2852 return 0;
2853}
2854
c09c2627 2855static inline u16
35efa7c1 2856bnx2_get_hw_rx_cons(struct bnx2_napi *bnapi)
c09c2627 2857{
bb4f98ab
MC		 2858 u16 cons;
2859
43e80b89
MC		 2860 /* Tell compiler that status block fields can change. */
2861 barrier();
2862 cons = *bnapi->hw_rx_cons_ptr;
c09c2627
MC		 2863 if (unlikely((cons & MAX_RX_DESC_CNT) == MAX_RX_DESC_CNT))
2864 cons++;
2865 return cons;
2866}
2867
b6016b76 2868static int
35efa7c1 2869bnx2_rx_int(struct bnx2 *bp, struct bnx2_napi *bnapi, int budget)
b6016b76 2870{
bb4f98ab 2871 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
b6016b76
MC		 2872 u16 hw_cons, sw_cons, sw_ring_cons, sw_prod, sw_ring_prod;
2873 struct l2_fhdr *rx_hdr;
1db82f2a 2874 int rx_pkt = 0, pg_ring_used = 0;
b6016b76 2875
35efa7c1 2876 hw_cons = bnx2_get_hw_rx_cons(bnapi);
bb4f98ab
MC		 2877 sw_cons = rxr->rx_cons;
2878 sw_prod = rxr->rx_prod;
b6016b76
MC		 2879
2880 /* Memory barrier necessary as speculative reads of the rx
2881 * buffer can be ahead of the index in the status block
2882 */
2883 rmb();
2884 while (sw_cons != hw_cons) {
1db82f2a 2885 unsigned int len, hdr_len;
ade2bfe7 2886 u32 status;
b6016b76
MC		 2887 struct sw_bd *rx_buf;
2888 struct sk_buff *skb;
236b6394 2889 dma_addr_t dma_addr;
f22828e8
MC		 2890 u16 vtag = 0;
2891 int hw_vlan __maybe_unused = 0;
b6016b76
MC		 2892
2893 sw_ring_cons = RX_RING_IDX(sw_cons);
2894 sw_ring_prod = RX_RING_IDX(sw_prod);
2895
bb4f98ab 2896 rx_buf = &rxr->rx_buf_ring[sw_ring_cons];
b6016b76 2897 skb = rx_buf->skb;
236b6394
MC		 2898
2899 rx_buf->skb = NULL;
2900
2901 dma_addr = pci_unmap_addr(rx_buf, mapping);
2902
2903 pci_dma_sync_single_for_cpu(bp->pdev, dma_addr,
601d3d18
BL		 2904 BNX2_RX_OFFSET + BNX2_RX_COPY_THRESH,
2905 PCI_DMA_FROMDEVICE);
b6016b76
MC		 2906
2907 rx_hdr = (struct l2_fhdr *) skb->data;
1db82f2a 2908 len = rx_hdr->l2_fhdr_pkt_len;
b6016b76 2909
ade2bfe7 2910 if ((status = rx_hdr->l2_fhdr_status) &
b6016b76
MC		 2911 (L2_FHDR_ERRORS_BAD_CRC |
2912 L2_FHDR_ERRORS_PHY_DECODE |
2913 L2_FHDR_ERRORS_ALIGNMENT |
2914 L2_FHDR_ERRORS_TOO_SHORT |
2915 L2_FHDR_ERRORS_GIANT_FRAME)) {
2916
bb4f98ab 2917 bnx2_reuse_rx_skb(bp, rxr, skb, sw_ring_cons,
a1f60190 2918 sw_ring_prod);
85833c62 2919 goto next_rx;
b6016b76 2920 }
1db82f2a
MC		 2921 hdr_len = 0;
2922 if (status & L2_FHDR_STATUS_SPLIT) {
2923 hdr_len = rx_hdr->l2_fhdr_ip_xsum;
2924 pg_ring_used = 1;
2925 } else if (len > bp->rx_jumbo_thresh) {
2926 hdr_len = bp->rx_jumbo_thresh;
2927 pg_ring_used = 1;
2928 }
2929
2930 len -= 4;
b6016b76 2931
5d5d0015 2932 if (len <= bp->rx_copy_thresh) {
b6016b76
MC		 2933 struct sk_buff *new_skb;
2934
f22828e8 2935 new_skb = netdev_alloc_skb(bp->dev, len + 6);
85833c62 2936 if (new_skb == NULL) {
bb4f98ab 2937 bnx2_reuse_rx_skb(bp, rxr, skb, sw_ring_cons,
85833c62
MC		 2938 sw_ring_prod);
2939 goto next_rx;
2940 }
b6016b76
MC		 2941
2942 /* aligned copy */
d89cb6af 2943 skb_copy_from_linear_data_offset(skb,
f22828e8
MC		 2944 BNX2_RX_OFFSET - 6,
2945 new_skb->data, len + 6);
2946 skb_reserve(new_skb, 6);
b6016b76 2947 skb_put(new_skb, len);
b6016b76 2948
bb4f98ab 2949 bnx2_reuse_rx_skb(bp, rxr, skb,
b6016b76
MC		 2950 sw_ring_cons, sw_ring_prod);
2951
2952 skb = new_skb;
bb4f98ab 2953 } else if (unlikely(bnx2_rx_skb(bp, rxr, skb, len, hdr_len,
a1f60190 2954 dma_addr, (sw_ring_cons << 16) | sw_ring_prod)))
b6016b76 2955 goto next_rx;
b6016b76 2956
f22828e8
MC		 2957 if ((status & L2_FHDR_STATUS_L2_VLAN_TAG) &&
2958 !(bp->rx_mode & BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG)) {
2959 vtag = rx_hdr->l2_fhdr_vlan_tag;
2960#ifdef BCM_VLAN
2961 if (bp->vlgrp)
2962 hw_vlan = 1;
2963 else
2964#endif
2965 {
2966 struct vlan_ethhdr *ve = (struct vlan_ethhdr *)
2967 __skb_push(skb, 4);
2968
2969 memmove(ve, skb->data + 4, ETH_ALEN * 2);
2970 ve->h_vlan_proto = htons(ETH_P_8021Q);
2971 ve->h_vlan_TCI = htons(vtag);
2972 len += 4;
2973 }
2974 }
2975
b6016b76
MC		 2976 skb->protocol = eth_type_trans(skb, bp->dev);
2977
2978 if ((len > (bp->dev->mtu + ETH_HLEN)) &&
d1e100ba 2979 (ntohs(skb->protocol) != 0x8100)) {
b6016b76 2980
745720e5 2981 dev_kfree_skb(skb);
b6016b76
MC		 2982 goto next_rx;
2983
2984 }
2985
b6016b76
MC		 2986 skb->ip_summed = CHECKSUM_NONE;
2987 if (bp->rx_csum &&
2988 (status & (L2_FHDR_STATUS_TCP_SEGMENT |
2989 L2_FHDR_STATUS_UDP_DATAGRAM))) {
2990
ade2bfe7
MC		 2991 if (likely((status & (L2_FHDR_ERRORS_TCP_XSUM |
2992 L2_FHDR_ERRORS_UDP_XSUM)) == 0))
b6016b76
MC		 2993 skb->ip_summed = CHECKSUM_UNNECESSARY;
2994 }
2995
2996#ifdef BCM_VLAN
f22828e8
MC		 2997 if (hw_vlan)
2998 vlan_hwaccel_receive_skb(skb, bp->vlgrp, vtag);
b6016b76
MC		 2999 else
3000#endif
3001 netif_receive_skb(skb);
3002
3003 bp->dev->last_rx = jiffies;
3004 rx_pkt++;
3005
3006next_rx:
b6016b76
MC		 3007 sw_cons = NEXT_RX_BD(sw_cons);
3008 sw_prod = NEXT_RX_BD(sw_prod);
3009
3010 if ((rx_pkt == budget))
3011 break;
f4e418f7
MC		 3012
3013 /* Refresh hw_cons to see if there is new work */
3014 if (sw_cons == hw_cons) {
35efa7c1 3015 hw_cons = bnx2_get_hw_rx_cons(bnapi);
f4e418f7
MC		 3016 rmb();
3017 }
b6016b76 3018 }
bb4f98ab
MC		 3019 rxr->rx_cons = sw_cons;
3020 rxr->rx_prod = sw_prod;
b6016b76 3021
1db82f2a 3022 if (pg_ring_used)
bb4f98ab 3023 REG_WR16(bp, rxr->rx_pg_bidx_addr, rxr->rx_pg_prod);
1db82f2a 3024
bb4f98ab 3025 REG_WR16(bp, rxr->rx_bidx_addr, sw_prod);
b6016b76 3026
bb4f98ab 3027 REG_WR(bp, rxr->rx_bseq_addr, rxr->rx_prod_bseq);
b6016b76
MC		 3028
3029 mmiowb();
3030
3031 return rx_pkt;
3032
3033}
3034
3035/* MSI ISR - The only difference between this and the INTx ISR
3036 * is that the MSI interrupt is always serviced.
3037 */
3038static irqreturn_t
7d12e780 3039bnx2_msi(int irq, void *dev_instance)
b6016b76 3040{
f0ea2e63
MC		 3041 struct bnx2_napi *bnapi = dev_instance;
3042 struct bnx2 *bp = bnapi->bp;
3043 struct net_device *dev = bp->dev;
b6016b76 3044
43e80b89 3045 prefetch(bnapi->status_blk.msi);
b6016b76
MC		 3046 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
3047 BNX2_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM |
3048 BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
3049
3050 /* Return here if interrupt is disabled. */
73eef4cd
MC		 3051 if (unlikely(atomic_read(&bp->intr_sem) != 0))
3052 return IRQ_HANDLED;
b6016b76 3053
35efa7c1 3054 netif_rx_schedule(dev, &bnapi->napi);
b6016b76 3055
73eef4cd 3056 return IRQ_HANDLED;
b6016b76
MC		 3057}
3058
8e6a72c4
MC		 3059static irqreturn_t
3060bnx2_msi_1shot(int irq, void *dev_instance)
3061{
f0ea2e63
MC		 3062 struct bnx2_napi *bnapi = dev_instance;
3063 struct bnx2 *bp = bnapi->bp;
3064 struct net_device *dev = bp->dev;
8e6a72c4 3065
43e80b89 3066 prefetch(bnapi->status_blk.msi);
8e6a72c4
MC		 3067
3068 /* Return here if interrupt is disabled. */
3069 if (unlikely(atomic_read(&bp->intr_sem) != 0))
3070 return IRQ_HANDLED;
3071
35efa7c1 3072 netif_rx_schedule(dev, &bnapi->napi);
8e6a72c4
MC		 3073
3074 return IRQ_HANDLED;
3075}
3076
b6016b76 3077static irqreturn_t
7d12e780 3078bnx2_interrupt(int irq, void *dev_instance)
b6016b76 3079{
f0ea2e63
MC		 3080 struct bnx2_napi *bnapi = dev_instance;
3081 struct bnx2 *bp = bnapi->bp;
3082 struct net_device *dev = bp->dev;
43e80b89 3083 struct status_block *sblk = bnapi->status_blk.msi;
b6016b76
MC		 3084
3085 /* When using INTx, it is possible for the interrupt to arrive
3086 * at the CPU before the status block posted prior to the
3087 * interrupt. Reading a register will flush the status block.
3088 * When using MSI, the MSI message will always complete after
3089 * the status block write.
3090 */
35efa7c1 3091 if ((sblk->status_idx == bnapi->last_status_idx) &&
b6016b76
MC		 3092 (REG_RD(bp, BNX2_PCICFG_MISC_STATUS) &
3093 BNX2_PCICFG_MISC_STATUS_INTA_VALUE))
73eef4cd 3094 return IRQ_NONE;
b6016b76
MC		 3095
3096 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
3097 BNX2_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM |
3098 BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
3099
b8a7ce7b
MC		 3100 /* Read back to deassert IRQ immediately to avoid too many
3101 * spurious interrupts.
3102 */
3103 REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD);
3104
b6016b76 3105 /* Return here if interrupt is shared and is disabled. */
73eef4cd
MC		 3106 if (unlikely(atomic_read(&bp->intr_sem) != 0))
3107 return IRQ_HANDLED;
b6016b76 3108
35efa7c1
MC		 3109 if (netif_rx_schedule_prep(dev, &bnapi->napi)) {
3110 bnapi->last_status_idx = sblk->status_idx;
3111 __netif_rx_schedule(dev, &bnapi->napi);
b8a7ce7b 3112 }
b6016b76 3113
73eef4cd 3114 return IRQ_HANDLED;
b6016b76
MC		 3115}
3116
f4e418f7 3117static inline int
43e80b89 3118bnx2_has_fast_work(struct bnx2_napi *bnapi)
f4e418f7 3119{
35e9010b 3120 struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
bb4f98ab 3121 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
f4e418f7 3122
bb4f98ab 3123 if ((bnx2_get_hw_rx_cons(bnapi) != rxr->rx_cons) ||
35e9010b 3124 (bnx2_get_hw_tx_cons(bnapi) != txr->hw_tx_cons))
f4e418f7 3125 return 1;
43e80b89
MC		 3126 return 0;
3127}
3128
3129#define STATUS_ATTN_EVENTS (STATUS_ATTN_BITS_LINK_STATE | \
3130 STATUS_ATTN_BITS_TIMER_ABORT)
3131
3132static inline int
3133bnx2_has_work(struct bnx2_napi *bnapi)
3134{
3135 struct status_block *sblk = bnapi->status_blk.msi;
3136
3137 if (bnx2_has_fast_work(bnapi))
3138 return 1;
f4e418f7 3139
da3e4fbe
MC		 3140 if ((sblk->status_attn_bits & STATUS_ATTN_EVENTS) !=
3141 (sblk->status_attn_bits_ack & STATUS_ATTN_EVENTS))
f4e418f7
MC		 3142 return 1;
3143
3144 return 0;
3145}
3146
efba0180
MC		 3147static void
3148bnx2_chk_missed_msi(struct bnx2 *bp)
3149{
3150 struct bnx2_napi *bnapi = &bp->bnx2_napi[0];
3151 u32 msi_ctrl;
3152
3153 if (bnx2_has_work(bnapi)) {
3154 msi_ctrl = REG_RD(bp, BNX2_PCICFG_MSI_CONTROL);
3155 if (!(msi_ctrl & BNX2_PCICFG_MSI_CONTROL_ENABLE))
3156 return;
3157
3158 if (bnapi->last_status_idx == bp->idle_chk_status_idx) {
3159 REG_WR(bp, BNX2_PCICFG_MSI_CONTROL, msi_ctrl &
3160 ~BNX2_PCICFG_MSI_CONTROL_ENABLE);
3161 REG_WR(bp, BNX2_PCICFG_MSI_CONTROL, msi_ctrl);
3162 bnx2_msi(bp->irq_tbl[0].vector, bnapi);
3163 }
3164 }
3165
3166 bp->idle_chk_status_idx = bnapi->last_status_idx;
3167}
3168
43e80b89 3169static void bnx2_poll_link(struct bnx2 *bp, struct bnx2_napi *bnapi)
b6016b76 3170{
43e80b89 3171 struct status_block *sblk = bnapi->status_blk.msi;
da3e4fbe
MC		 3172 u32 status_attn_bits = sblk->status_attn_bits;
3173 u32 status_attn_bits_ack = sblk->status_attn_bits_ack;
b6016b76 3174
da3e4fbe
MC		 3175 if ((status_attn_bits & STATUS_ATTN_EVENTS) !=
3176 (status_attn_bits_ack & STATUS_ATTN_EVENTS)) {
b6016b76 3177
35efa7c1 3178 bnx2_phy_int(bp, bnapi);
bf5295bb
MC		 3179
3180 /* This is needed to take care of transient status
3181 * during link changes.
3182 */
3183 REG_WR(bp, BNX2_HC_COMMAND,
3184 bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
3185 REG_RD(bp, BNX2_HC_COMMAND);
b6016b76 3186 }
43e80b89
MC		 3187}
3188
3189static int bnx2_poll_work(struct bnx2 *bp, struct bnx2_napi *bnapi,
3190 int work_done, int budget)
3191{
3192 struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
3193 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
b6016b76 3194
35e9010b 3195 if (bnx2_get_hw_tx_cons(bnapi) != txr->hw_tx_cons)
57851d84 3196 bnx2_tx_int(bp, bnapi, 0);
b6016b76 3197
bb4f98ab 3198 if (bnx2_get_hw_rx_cons(bnapi) != rxr->rx_cons)
35efa7c1 3199 work_done += bnx2_rx_int(bp, bnapi, budget - work_done);
6aa20a22 3200
6f535763
DM		 3201 return work_done;
3202}
3203
f0ea2e63
MC		 3204static int bnx2_poll_msix(struct napi_struct *napi, int budget)
3205{
3206 struct bnx2_napi *bnapi = container_of(napi, struct bnx2_napi, napi);
3207 struct bnx2 *bp = bnapi->bp;
3208 int work_done = 0;
3209 struct status_block_msix *sblk = bnapi->status_blk.msix;
3210
3211 while (1) {
3212 work_done = bnx2_poll_work(bp, bnapi, work_done, budget);
3213 if (unlikely(work_done >= budget))
3214 break;
3215
3216 bnapi->last_status_idx = sblk->status_idx;
3217 /* status idx must be read before checking for more work. */
3218 rmb();
3219 if (likely(!bnx2_has_fast_work(bnapi))) {
3220
3221 netif_rx_complete(bp->dev, napi);
3222 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num |
3223 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
3224 bnapi->last_status_idx);
3225 break;
3226 }
3227 }
3228 return work_done;
3229}
3230
6f535763
DM		 3231static int bnx2_poll(struct napi_struct *napi, int budget)
3232{
35efa7c1
MC		 3233 struct bnx2_napi *bnapi = container_of(napi, struct bnx2_napi, napi);
3234 struct bnx2 *bp = bnapi->bp;
6f535763 3235 int work_done = 0;
43e80b89 3236 struct status_block *sblk = bnapi->status_blk.msi;
6f535763
DM		 3237
3238 while (1) {
43e80b89
MC		 3239 bnx2_poll_link(bp, bnapi);
3240
35efa7c1 3241 work_done = bnx2_poll_work(bp, bnapi, work_done, budget);
f4e418f7 3242
35efa7c1 3243 /* bnapi->last_status_idx is used below to tell the hw how
6dee6421
MC		 3244 * much work has been processed, so we must read it before
3245 * checking for more work.
3246 */
35efa7c1 3247 bnapi->last_status_idx = sblk->status_idx;
efba0180
MC		 3248
3249 if (unlikely(work_done >= budget))
3250 break;
3251
6dee6421 3252 rmb();
35efa7c1 3253 if (likely(!bnx2_has_work(bnapi))) {
6f535763 3254 netif_rx_complete(bp->dev, napi);
f86e82fb 3255 if (likely(bp->flags & BNX2_FLAG_USING_MSI_OR_MSIX)) {
6f535763
DM		 3256 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
3257 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
35efa7c1 3258 bnapi->last_status_idx);
6dee6421 3259 break;
6f535763 3260 }
1269a8a6
MC		 3261 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
3262 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
6f535763 3263 BNX2_PCICFG_INT_ACK_CMD_MASK_INT |
35efa7c1 3264 bnapi->last_status_idx);
1269a8a6 3265
6f535763
DM		 3266 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
3267 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
35efa7c1 3268 bnapi->last_status_idx);
6f535763
DM		 3269 break;
3270 }
b6016b76
MC		 3271 }
3272
bea3348e 3273 return work_done;
b6016b76
MC		 3274}
3275
932ff279 3276/* Called with rtnl_lock from vlan functions and also netif_tx_lock
b6016b76
MC		 3277 * from set_multicast.
3278 */
3279static void
3280bnx2_set_rx_mode(struct net_device *dev)
3281{
972ec0d4 3282 struct bnx2 *bp = netdev_priv(dev);
b6016b76 3283 u32 rx_mode, sort_mode;
5fcaed01 3284 struct dev_addr_list *uc_ptr;
b6016b76 3285 int i;
b6016b76 3286
9f52b564
MC		 3287 if (!netif_running(dev))
3288 return;
3289
c770a65c 3290 spin_lock_bh(&bp->phy_lock);
b6016b76
MC		 3291
3292 rx_mode = bp->rx_mode & ~(BNX2_EMAC_RX_MODE_PROMISCUOUS |
3293 BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG);
3294 sort_mode = 1 | BNX2_RPM_SORT_USER0_BC_EN;
3295#ifdef BCM_VLAN
7c6337a1 3296 if (!bp->vlgrp && (bp->flags & BNX2_FLAG_CAN_KEEP_VLAN))
b6016b76 3297 rx_mode |= BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG;
b6016b76 3298#else
7c6337a1 3299 if (bp->flags & BNX2_FLAG_CAN_KEEP_VLAN)
e29054f9 3300 rx_mode |= BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG;
b6016b76
MC		 3301#endif
3302 if (dev->flags & IFF_PROMISC) {
3303 /* Promiscuous mode. */
3304 rx_mode |= BNX2_EMAC_RX_MODE_PROMISCUOUS;
7510873d
MC		 3305 sort_mode |= BNX2_RPM_SORT_USER0_PROM_EN |
3306 BNX2_RPM_SORT_USER0_PROM_VLAN;
b6016b76
MC		 3307 }
3308 else if (dev->flags & IFF_ALLMULTI) {
3309 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
3310 REG_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),
3311 0xffffffff);
3312 }
3313 sort_mode |= BNX2_RPM_SORT_USER0_MC_EN;
3314 }
3315 else {
3316 /* Accept one or more multicast(s). */
3317 struct dev_mc_list *mclist;
3318 u32 mc_filter[NUM_MC_HASH_REGISTERS];
3319 u32 regidx;
3320 u32 bit;
3321 u32 crc;
3322
3323 memset(mc_filter, 0, 4 * NUM_MC_HASH_REGISTERS);
3324
3325 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
3326 i++, mclist = mclist->next) {
3327
3328 crc = ether_crc_le(ETH_ALEN, mclist->dmi_addr);
3329 bit = crc & 0xff;
3330 regidx = (bit & 0xe0) >> 5;
3331 bit &= 0x1f;
3332 mc_filter[regidx] |= (1 << bit);
3333 }
3334
3335 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
3336 REG_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),
3337 mc_filter[i]);
3338 }
3339
3340 sort_mode |= BNX2_RPM_SORT_USER0_MC_HSH_EN;
3341 }
3342
5fcaed01
BL		 3343 uc_ptr = NULL;
3344 if (dev->uc_count > BNX2_MAX_UNICAST_ADDRESSES) {
3345 rx_mode |= BNX2_EMAC_RX_MODE_PROMISCUOUS;
3346 sort_mode |= BNX2_RPM_SORT_USER0_PROM_EN |
3347 BNX2_RPM_SORT_USER0_PROM_VLAN;
3348 } else if (!(dev->flags & IFF_PROMISC)) {
3349 uc_ptr = dev->uc_list;
3350
3351 /* Add all entries into to the match filter list */
3352 for (i = 0; i < dev->uc_count; i++) {
3353 bnx2_set_mac_addr(bp, uc_ptr->da_addr,
3354 i + BNX2_START_UNICAST_ADDRESS_INDEX);
3355 sort_mode |= (1 <<
3356 (i + BNX2_START_UNICAST_ADDRESS_INDEX));
3357 uc_ptr = uc_ptr->next;
3358 }
3359
3360 }
3361
b6016b76
MC		 3362 if (rx_mode != bp->rx_mode) {
3363 bp->rx_mode = rx_mode;
3364 REG_WR(bp, BNX2_EMAC_RX_MODE, rx_mode);
3365 }
3366
3367 REG_WR(bp, BNX2_RPM_SORT_USER0, 0x0);
3368 REG_WR(bp, BNX2_RPM_SORT_USER0, sort_mode);
3369 REG_WR(bp, BNX2_RPM_SORT_USER0, sort_mode | BNX2_RPM_SORT_USER0_ENA);
3370
c770a65c 3371 spin_unlock_bh(&bp->phy_lock);
b6016b76
MC		 3372}
3373
3374static void
b491edd5 3375load_rv2p_fw(struct bnx2 *bp, __le32 *rv2p_code, u32 rv2p_code_len,
b6016b76
MC		 3376 u32 rv2p_proc)
3377{
3378 int i;
3379 u32 val;
3380
d25be1d3
MC		 3381 if (rv2p_proc == RV2P_PROC2 && CHIP_NUM(bp) == CHIP_NUM_5709) {
3382 val = le32_to_cpu(rv2p_code[XI_RV2P_PROC2_MAX_BD_PAGE_LOC]);
3383 val &= ~XI_RV2P_PROC2_BD_PAGE_SIZE_MSK;
3384 val |= XI_RV2P_PROC2_BD_PAGE_SIZE;
3385 rv2p_code[XI_RV2P_PROC2_MAX_BD_PAGE_LOC] = cpu_to_le32(val);
3386 }
b6016b76
MC		 3387
3388 for (i = 0; i < rv2p_code_len; i += 8) {
b491edd5 3389 REG_WR(bp, BNX2_RV2P_INSTR_HIGH, le32_to_cpu(*rv2p_code));
b6016b76 3390 rv2p_code++;
b491edd5 3391 REG_WR(bp, BNX2_RV2P_INSTR_LOW, le32_to_cpu(*rv2p_code));
b6016b76
MC		 3392 rv2p_code++;
3393
3394 if (rv2p_proc == RV2P_PROC1) {
3395 val = (i / 8) | BNX2_RV2P_PROC1_ADDR_CMD_RDWR;
3396 REG_WR(bp, BNX2_RV2P_PROC1_ADDR_CMD, val);
3397 }
3398 else {
3399 val = (i / 8) | BNX2_RV2P_PROC2_ADDR_CMD_RDWR;
3400 REG_WR(bp, BNX2_RV2P_PROC2_ADDR_CMD, val);
3401 }
3402 }
3403
3404 /* Reset the processor, un-stall is done later. */
3405 if (rv2p_proc == RV2P_PROC1) {
3406 REG_WR(bp, BNX2_RV2P_COMMAND, BNX2_RV2P_COMMAND_PROC1_RESET);
3407 }
3408 else {
3409 REG_WR(bp, BNX2_RV2P_COMMAND, BNX2_RV2P_COMMAND_PROC2_RESET);
3410 }
3411}
3412
af3ee519 3413static int
10343cca 3414load_cpu_fw(struct bnx2 *bp, const struct cpu_reg *cpu_reg, struct fw_info *fw)
b6016b76
MC		 3415{
3416 u32 offset;
3417 u32 val;
af3ee519 3418 int rc;
b6016b76
MC		 3419
3420 /* Halt the CPU. */
2726d6e1 3421 val = bnx2_reg_rd_ind(bp, cpu_reg->mode);
b6016b76 3422 val |= cpu_reg->mode_value_halt;
2726d6e1
MC		 3423 bnx2_reg_wr_ind(bp, cpu_reg->mode, val);
3424 bnx2_reg_wr_ind(bp, cpu_reg->state, cpu_reg->state_value_clear);
b6016b76
MC		 3425
3426 /* Load the Text area. */
3427 offset = cpu_reg->spad_base + (fw->text_addr - cpu_reg->mips_view_base);
af3ee519 3428 if (fw->gz_text) {
b6016b76
MC		 3429 int j;
3430
ea1f8d5c
MC		 3431 rc = zlib_inflate_blob(fw->text, FW_BUF_SIZE, fw->gz_text,
3432 fw->gz_text_len);
3433 if (rc < 0)
b3448b0b 3434 return rc;
ea1f8d5c 3435
b6016b76 3436 for (j = 0; j < (fw->text_len / 4); j++, offset += 4) {
2726d6e1 3437 bnx2_reg_wr_ind(bp, offset, le32_to_cpu(fw->text[j]));
b6016b76
MC		 3438 }
3439 }
3440
3441 /* Load the Data area. */
3442 offset = cpu_reg->spad_base + (fw->data_addr - cpu_reg->mips_view_base);
3443 if (fw->data) {
3444 int j;
3445
3446 for (j = 0; j < (fw->data_len / 4); j++, offset += 4) {
2726d6e1 3447 bnx2_reg_wr_ind(bp, offset, fw->data[j]);
b6016b76
MC		 3448 }
3449 }
3450
3451 /* Load the SBSS area. */
3452 offset = cpu_reg->spad_base + (fw->sbss_addr - cpu_reg->mips_view_base);
ea1f8d5c 3453 if (fw->sbss_len) {
b6016b76
MC		 3454 int j;
3455
3456 for (j = 0; j < (fw->sbss_len / 4); j++, offset += 4) {
2726d6e1 3457 bnx2_reg_wr_ind(bp, offset, 0);
b6016b76
MC		 3458 }
3459 }
3460
3461 /* Load the BSS area. */
3462 offset = cpu_reg->spad_base + (fw->bss_addr - cpu_reg->mips_view_base);
ea1f8d5c 3463 if (fw->bss_len) {
b6016b76
MC		 3464 int j;
3465
3466 for (j = 0; j < (fw->bss_len/4); j++, offset += 4) {
2726d6e1 3467 bnx2_reg_wr_ind(bp, offset, 0);
b6016b76
MC		 3468 }
3469 }
3470
3471 /* Load the Read-Only area. */
3472 offset = cpu_reg->spad_base +
3473 (fw->rodata_addr - cpu_reg->mips_view_base);
3474 if (fw->rodata) {
3475 int j;
3476
3477 for (j = 0; j < (fw->rodata_len / 4); j++, offset += 4) {
2726d6e1 3478 bnx2_reg_wr_ind(bp, offset, fw->rodata[j]);
b6016b76
MC		 3479 }
3480 }
3481
3482 /* Clear the pre-fetch instruction. */
2726d6e1
MC		 3483 bnx2_reg_wr_ind(bp, cpu_reg->inst, 0);
3484 bnx2_reg_wr_ind(bp, cpu_reg->pc, fw->start_addr);
b6016b76
MC		 3485
3486 /* Start the CPU. */
2726d6e1 3487 val = bnx2_reg_rd_ind(bp, cpu_reg->mode);
b6016b76 3488 val &= ~cpu_reg->mode_value_halt;
2726d6e1
MC		 3489 bnx2_reg_wr_ind(bp, cpu_reg->state, cpu_reg->state_value_clear);
3490 bnx2_reg_wr_ind(bp, cpu_reg->mode, val);
af3ee519
MC		 3491
3492 return 0;
b6016b76
MC		 3493}
3494
fba9fe91 3495static int
b6016b76
MC		 3496bnx2_init_cpus(struct bnx2 *bp)
3497{
af3ee519 3498 struct fw_info *fw;
110d0ef9
MC		 3499 int rc, rv2p_len;
3500 void *text, *rv2p;
b6016b76
MC		 3501
3502 /* Initialize the RV2P processor. */
b3448b0b
DV		 3503 text = vmalloc(FW_BUF_SIZE);
3504 if (!text)
3505 return -ENOMEM;
110d0ef9
MC		 3506 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
3507 rv2p = bnx2_xi_rv2p_proc1;
3508 rv2p_len = sizeof(bnx2_xi_rv2p_proc1);
3509 } else {
3510 rv2p = bnx2_rv2p_proc1;
3511 rv2p_len = sizeof(bnx2_rv2p_proc1);
3512 }
3513 rc = zlib_inflate_blob(text, FW_BUF_SIZE, rv2p, rv2p_len);
ea1f8d5c 3514 if (rc < 0)
fba9fe91 3515 goto init_cpu_err;
ea1f8d5c 3516
b3448b0b 3517 load_rv2p_fw(bp, text, rc /* == len */, RV2P_PROC1);
fba9fe91 3518
110d0ef9
MC		 3519 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
3520 rv2p = bnx2_xi_rv2p_proc2;
3521 rv2p_len = sizeof(bnx2_xi_rv2p_proc2);
3522 } else {
3523 rv2p = bnx2_rv2p_proc2;
3524 rv2p_len = sizeof(bnx2_rv2p_proc2);
3525 }
3526 rc = zlib_inflate_blob(text, FW_BUF_SIZE, rv2p, rv2p_len);
ea1f8d5c 3527 if (rc < 0)
fba9fe91 3528 goto init_cpu_err;
ea1f8d5c 3529
b3448b0b 3530 load_rv2p_fw(bp, text, rc /* == len */, RV2P_PROC2);
b6016b76
MC		 3531
3532 /* Initialize the RX Processor. */
d43584c8
MC		 3533 if (CHIP_NUM(bp) == CHIP_NUM_5709)
3534 fw = &bnx2_rxp_fw_09;
3535 else
3536 fw = &bnx2_rxp_fw_06;
fba9fe91 3537
ea1f8d5c 3538 fw->text = text;
10343cca 3539 rc = load_cpu_fw(bp, &cpu_reg_rxp, fw);
fba9fe91
MC		 3540 if (rc)
3541 goto init_cpu_err;
3542
b6016b76 3543 /* Initialize the TX Processor. */
d43584c8
MC		 3544 if (CHIP_NUM(bp) == CHIP_NUM_5709)
3545 fw = &bnx2_txp_fw_09;
3546 else
3547 fw = &bnx2_txp_fw_06;
fba9fe91 3548
ea1f8d5c 3549 fw->text = text;
10343cca 3550 rc = load_cpu_fw(bp, &cpu_reg_txp, fw);
fba9fe91
MC		 3551 if (rc)
3552 goto init_cpu_err;
3553
b6016b76 3554 /* Initialize the TX Patch-up Processor. */
d43584c8
MC		 3555 if (CHIP_NUM(bp) == CHIP_NUM_5709)
3556 fw = &bnx2_tpat_fw_09;
3557 else
3558 fw = &bnx2_tpat_fw_06;
fba9fe91 3559
ea1f8d5c 3560 fw->text = text;
10343cca 3561 rc = load_cpu_fw(bp, &cpu_reg_tpat, fw);
fba9fe91
MC		 3562 if (rc)
3563 goto init_cpu_err;
3564
b6016b76 3565 /* Initialize the Completion Processor. */
d43584c8
MC		 3566 if (CHIP_NUM(bp) == CHIP_NUM_5709)
3567 fw = &bnx2_com_fw_09;
3568 else
3569 fw = &bnx2_com_fw_06;
fba9fe91 3570
ea1f8d5c 3571 fw->text = text;
10343cca 3572 rc = load_cpu_fw(bp, &cpu_reg_com, fw);
fba9fe91
MC		 3573 if (rc)
3574 goto init_cpu_err;
3575
d43584c8 3576 /* Initialize the Command Processor. */
110d0ef9 3577 if (CHIP_NUM(bp) == CHIP_NUM_5709)
d43584c8 3578 fw = &bnx2_cp_fw_09;
110d0ef9
MC		 3579 else
3580 fw = &bnx2_cp_fw_06;
3581
3582 fw->text = text;
10343cca 3583 rc = load_cpu_fw(bp, &cpu_reg_cp, fw);
b6016b76 3584
fba9fe91 3585init_cpu_err:
ea1f8d5c 3586 vfree(text);
fba9fe91 3587 return rc;
b6016b76
MC		 3588}
3589
3590static int
829ca9a3 3591bnx2_set_power_state(struct bnx2 *bp, pci_power_t state)
b6016b76
MC		 3592{
3593 u16 pmcsr;
3594
3595 pci_read_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL, &pmcsr);
3596
3597 switch (state) {
829ca9a3 3598 case PCI_D0: {
b6016b76
MC		 3599 u32 val;
3600
3601 pci_write_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL,
3602 (pmcsr & ~PCI_PM_CTRL_STATE_MASK) |
3603 PCI_PM_CTRL_PME_STATUS);
3604
3605 if (pmcsr & PCI_PM_CTRL_STATE_MASK)
3606 /* delay required during transition out of D3hot */
3607 msleep(20);
3608
3609 val = REG_RD(bp, BNX2_EMAC_MODE);
3610 val |= BNX2_EMAC_MODE_MPKT_RCVD | BNX2_EMAC_MODE_ACPI_RCVD;
3611 val &= ~BNX2_EMAC_MODE_MPKT;
3612 REG_WR(bp, BNX2_EMAC_MODE, val);
3613
3614 val = REG_RD(bp, BNX2_RPM_CONFIG);
3615 val &= ~BNX2_RPM_CONFIG_ACPI_ENA;
3616 REG_WR(bp, BNX2_RPM_CONFIG, val);
3617 break;
3618 }
829ca9a3 3619 case PCI_D3hot: {
b6016b76
MC		 3620 int i;
3621 u32 val, wol_msg;
3622
3623 if (bp->wol) {
3624 u32 advertising;
3625 u8 autoneg;
3626
3627 autoneg = bp->autoneg;
3628 advertising = bp->advertising;
3629
239cd343
MC		 3630 if (bp->phy_port == PORT_TP) {
3631 bp->autoneg = AUTONEG_SPEED;
3632 bp->advertising = ADVERTISED_10baseT_Half |
3633 ADVERTISED_10baseT_Full |
3634 ADVERTISED_100baseT_Half |
3635 ADVERTISED_100baseT_Full |
3636 ADVERTISED_Autoneg;
3637 }
b6016b76 3638
239cd343
MC		 3639 spin_lock_bh(&bp->phy_lock);
3640 bnx2_setup_phy(bp, bp->phy_port);
3641 spin_unlock_bh(&bp->phy_lock);
b6016b76
MC		 3642
3643 bp->autoneg = autoneg;
3644 bp->advertising = advertising;
3645
5fcaed01 3646 bnx2_set_mac_addr(bp, bp->dev->dev_addr, 0);
b6016b76
MC		 3647
3648 val = REG_RD(bp, BNX2_EMAC_MODE);
3649
3650 /* Enable port mode. */
3651 val &= ~BNX2_EMAC_MODE_PORT;
239cd343 3652 val |= BNX2_EMAC_MODE_MPKT_RCVD |
b6016b76 3653 BNX2_EMAC_MODE_ACPI_RCVD |
b6016b76 3654 BNX2_EMAC_MODE_MPKT;
239cd343
MC		 3655 if (bp->phy_port == PORT_TP)
3656 val |= BNX2_EMAC_MODE_PORT_MII;
3657 else {
3658 val |= BNX2_EMAC_MODE_PORT_GMII;
3659 if (bp->line_speed == SPEED_2500)
3660 val |= BNX2_EMAC_MODE_25G_MODE;
3661 }
b6016b76
MC		 3662
3663 REG_WR(bp, BNX2_EMAC_MODE, val);
3664
3665 /* receive all multicast */
3666 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
3667 REG_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),
3668 0xffffffff);
3669 }
3670 REG_WR(bp, BNX2_EMAC_RX_MODE,
3671 BNX2_EMAC_RX_MODE_SORT_MODE);
3672
3673 val = 1 | BNX2_RPM_SORT_USER0_BC_EN |
3674 BNX2_RPM_SORT_USER0_MC_EN;
3675 REG_WR(bp, BNX2_RPM_SORT_USER0, 0x0);
3676 REG_WR(bp, BNX2_RPM_SORT_USER0, val);
3677 REG_WR(bp, BNX2_RPM_SORT_USER0, val |
3678 BNX2_RPM_SORT_USER0_ENA);
3679
3680 /* Need to enable EMAC and RPM for WOL. */
3681 REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS,
3682 BNX2_MISC_ENABLE_SET_BITS_RX_PARSER_MAC_ENABLE |
3683 BNX2_MISC_ENABLE_SET_BITS_TX_HEADER_Q_ENABLE |
3684 BNX2_MISC_ENABLE_SET_BITS_EMAC_ENABLE);
3685
3686 val = REG_RD(bp, BNX2_RPM_CONFIG);
3687 val &= ~BNX2_RPM_CONFIG_ACPI_ENA;
3688 REG_WR(bp, BNX2_RPM_CONFIG, val);
3689
3690 wol_msg = BNX2_DRV_MSG_CODE_SUSPEND_WOL;
3691 }
3692 else {
3693 wol_msg = BNX2_DRV_MSG_CODE_SUSPEND_NO_WOL;
3694 }
3695
f86e82fb 3696 if (!(bp->flags & BNX2_FLAG_NO_WOL))
a2f13890
MC		 3697 bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT3 | wol_msg,
3698 1, 0);
b6016b76
MC		 3699
3700 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
3701 if ((CHIP_ID(bp) == CHIP_ID_5706_A0) ||
3702 (CHIP_ID(bp) == CHIP_ID_5706_A1)) {
3703
3704 if (bp->wol)
3705 pmcsr |= 3;
3706 }
3707 else {
3708 pmcsr |= 3;
3709 }
3710 if (bp->wol) {
3711 pmcsr |= PCI_PM_CTRL_PME_ENABLE;
3712 }
3713 pci_write_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL,
3714 pmcsr);
3715
3716 /* No more memory access after this point until
3717 * device is brought back to D0.
3718 */
3719 udelay(50);
3720 break;
3721 }
3722 default:
3723 return -EINVAL;
3724 }
3725 return 0;
3726}
3727
3728static int
3729bnx2_acquire_nvram_lock(struct bnx2 *bp)
3730{
3731 u32 val;
3732 int j;
3733
3734 /* Request access to the flash interface. */
3735 REG_WR(bp, BNX2_NVM_SW_ARB, BNX2_NVM_SW_ARB_ARB_REQ_SET2);
3736 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
3737 val = REG_RD(bp, BNX2_NVM_SW_ARB);
3738 if (val & BNX2_NVM_SW_ARB_ARB_ARB2)
3739 break;
3740
3741 udelay(5);
3742 }
3743
3744 if (j >= NVRAM_TIMEOUT_COUNT)
3745 return -EBUSY;
3746
3747 return 0;
3748}
3749
3750static int
3751bnx2_release_nvram_lock(struct bnx2 *bp)
3752{
3753 int j;
3754 u32 val;
3755
3756 /* Relinquish nvram interface. */
3757 REG_WR(bp, BNX2_NVM_SW_ARB, BNX2_NVM_SW_ARB_ARB_REQ_CLR2);
3758
3759 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
3760 val = REG_RD(bp, BNX2_NVM_SW_ARB);
3761 if (!(val & BNX2_NVM_SW_ARB_ARB_ARB2))
3762 break;
3763
3764 udelay(5);
3765 }
3766
3767 if (j >= NVRAM_TIMEOUT_COUNT)
3768 return -EBUSY;
3769
3770 return 0;
3771}
3772
3773
3774static int
3775bnx2_enable_nvram_write(struct bnx2 *bp)
3776{
3777 u32 val;
3778
3779 val = REG_RD(bp, BNX2_MISC_CFG);
3780 REG_WR(bp, BNX2_MISC_CFG, val | BNX2_MISC_CFG_NVM_WR_EN_PCI);
3781
e30372c9 3782 if (bp->flash_info->flags & BNX2_NV_WREN) {
b6016b76
MC		 3783 int j;
3784
3785 REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
3786 REG_WR(bp, BNX2_NVM_COMMAND,
3787 BNX2_NVM_COMMAND_WREN | BNX2_NVM_COMMAND_DOIT);
3788
3789 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
3790 udelay(5);
3791
3792 val = REG_RD(bp, BNX2_NVM_COMMAND);
3793 if (val & BNX2_NVM_COMMAND_DONE)
3794 break;
3795 }
3796
3797 if (j >= NVRAM_TIMEOUT_COUNT)
3798 return -EBUSY;
3799 }
3800 return 0;
3801}
3802
3803static void
3804bnx2_disable_nvram_write(struct bnx2 *bp)
3805{
3806 u32 val;
3807
3808 val = REG_RD(bp, BNX2_MISC_CFG);
3809 REG_WR(bp, BNX2_MISC_CFG, val & ~BNX2_MISC_CFG_NVM_WR_EN);
3810}
3811
3812
3813static void
3814bnx2_enable_nvram_access(struct bnx2 *bp)
3815{
3816 u32 val;
3817
3818 val = REG_RD(bp, BNX2_NVM_ACCESS_ENABLE);
3819 /* Enable both bits, even on read. */
6aa20a22 3820 REG_WR(bp, BNX2_NVM_ACCESS_ENABLE,
b6016b76
MC		 3821 val | BNX2_NVM_ACCESS_ENABLE_EN | BNX2_NVM_ACCESS_ENABLE_WR_EN);
3822}
3823
3824static void
3825bnx2_disable_nvram_access(struct bnx2 *bp)
3826{
3827 u32 val;
3828
3829 val = REG_RD(bp, BNX2_NVM_ACCESS_ENABLE);
3830 /* Disable both bits, even after read. */
6aa20a22 3831 REG_WR(bp, BNX2_NVM_ACCESS_ENABLE,
b6016b76
MC		 3832 val & ~(BNX2_NVM_ACCESS_ENABLE_EN |
3833 BNX2_NVM_ACCESS_ENABLE_WR_EN));
3834}
3835
3836static int
3837bnx2_nvram_erase_page(struct bnx2 *bp, u32 offset)
3838{
3839 u32 cmd;
3840 int j;
3841
e30372c9 3842 if (bp->flash_info->flags & BNX2_NV_BUFFERED)
b6016b76
MC		 3843 /* Buffered flash, no erase needed */
3844 return 0;
3845
3846 /* Build an erase command */
3847 cmd = BNX2_NVM_COMMAND_ERASE | BNX2_NVM_COMMAND_WR |
3848 BNX2_NVM_COMMAND_DOIT;
3849
3850 /* Need to clear DONE bit separately. */
3851 REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
3852
3853 /* Address of the NVRAM to read from. */
3854 REG_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);
3855
3856 /* Issue an erase command. */
3857 REG_WR(bp, BNX2_NVM_COMMAND, cmd);
3858
3859 /* Wait for completion. */
3860 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
3861 u32 val;
3862
3863 udelay(5);
3864
3865 val = REG_RD(bp, BNX2_NVM_COMMAND);
3866 if (val & BNX2_NVM_COMMAND_DONE)
3867 break;
3868 }
3869
3870 if (j >= NVRAM_TIMEOUT_COUNT)
3871 return -EBUSY;
3872
3873 return 0;
3874}
3875
3876static int
3877bnx2_nvram_read_dword(struct bnx2 *bp, u32 offset, u8 *ret_val, u32 cmd_flags)
3878{
3879 u32 cmd;
3880 int j;
3881
3882 /* Build the command word. */
3883 cmd = BNX2_NVM_COMMAND_DOIT | cmd_flags;
3884
e30372c9
MC		 3885 /* Calculate an offset of a buffered flash, not needed for 5709. */
3886 if (bp->flash_info->flags & BNX2_NV_TRANSLATE) {
b6016b76
MC		 3887 offset = ((offset / bp->flash_info->page_size) <<
3888 bp->flash_info->page_bits) +
3889 (offset % bp->flash_info->page_size);
3890 }
3891
3892 /* Need to clear DONE bit separately. */
3893 REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
3894
3895 /* Address of the NVRAM to read from. */
3896 REG_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);
3897
3898 /* Issue a read command. */
3899 REG_WR(bp, BNX2_NVM_COMMAND, cmd);
3900
3901 /* Wait for completion. */
3902 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
3903 u32 val;
3904
3905 udelay(5);
3906
3907 val = REG_RD(bp, BNX2_NVM_COMMAND);
3908 if (val & BNX2_NVM_COMMAND_DONE) {
b491edd5
AV		 3909 __be32 v = cpu_to_be32(REG_RD(bp, BNX2_NVM_READ));
3910 memcpy(ret_val, &v, 4);
b6016b76
MC		 3911 break;
3912 }
3913 }
3914 if (j >= NVRAM_TIMEOUT_COUNT)
3915 return -EBUSY;
3916
3917 return 0;
3918}
3919
3920
3921static int
3922bnx2_nvram_write_dword(struct bnx2 *bp, u32 offset, u8 *val, u32 cmd_flags)
3923{
b491edd5
AV		 3924 u32 cmd;
3925 __be32 val32;
b6016b76
MC		 3926 int j;
3927
3928 /* Build the command word. */
3929 cmd = BNX2_NVM_COMMAND_DOIT | BNX2_NVM_COMMAND_WR | cmd_flags;
3930
e30372c9
MC		 3931 /* Calculate an offset of a buffered flash, not needed for 5709. */
3932 if (bp->flash_info->flags & BNX2_NV_TRANSLATE) {
b6016b76
MC		 3933 offset = ((offset / bp->flash_info->page_size) <<
3934 bp->flash_info->page_bits) +
3935 (offset % bp->flash_info->page_size);
3936 }
3937
3938 /* Need to clear DONE bit separately. */
3939 REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
3940
3941 memcpy(&val32, val, 4);
b6016b76
MC		 3942
3943 /* Write the data. */
b491edd5 3944 REG_WR(bp, BNX2_NVM_WRITE, be32_to_cpu(val32));
b6016b76
MC		 3945
3946 /* Address of the NVRAM to write to. */
3947 REG_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);
3948
3949 /* Issue the write command. */
3950 REG_WR(bp, BNX2_NVM_COMMAND, cmd);
3951
3952 /* Wait for completion. */
3953 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
3954 udelay(5);
3955
3956 if (REG_RD(bp, BNX2_NVM_COMMAND) & BNX2_NVM_COMMAND_DONE)
3957 break;
3958 }
3959 if (j >= NVRAM_TIMEOUT_COUNT)
3960 return -EBUSY;
3961
3962 return 0;
3963}
3964
3965static int
3966bnx2_init_nvram(struct bnx2 *bp)
3967{
3968 u32 val;
e30372c9 3969 int j, entry_count, rc = 0;
b6016b76
MC		 3970 struct flash_spec *flash;
3971
e30372c9
MC		 3972 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
3973 bp->flash_info = &flash_5709;
3974 goto get_flash_size;
3975 }
3976
b6016b76
MC		 3977 /* Determine the selected interface. */
3978 val = REG_RD(bp, BNX2_NVM_CFG1);
3979
ff8ac609 3980 entry_count = ARRAY_SIZE(flash_table);
b6016b76 3981
b6016b76
MC		 3982 if (val & 0x40000000) {
3983
3984 /* Flash interface has been reconfigured */
3985 for (j = 0, flash = &flash_table[0]; j < entry_count;
37137709
MC		 3986 j++, flash++) {
3987 if ((val & FLASH_BACKUP_STRAP_MASK) ==
3988 (flash->config1 & FLASH_BACKUP_STRAP_MASK)) {
b6016b76
MC		 3989 bp->flash_info = flash;
3990 break;
3991 }
3992 }
3993 }
3994 else {
37137709 3995 u32 mask;
b6016b76
MC		 3996 /* Not yet been reconfigured */
3997
37137709
MC		 3998 if (val & (1 << 23))
3999 mask = FLASH_BACKUP_STRAP_MASK;
4000 else
4001 mask = FLASH_STRAP_MASK;
4002
b6016b76
MC		 4003 for (j = 0, flash = &flash_table[0]; j < entry_count;
4004 j++, flash++) {
4005
37137709 4006 if ((val & mask) == (flash->strapping & mask)) {
b6016b76
MC		 4007 bp->flash_info = flash;
4008
4009 /* Request access to the flash interface. */
4010 if ((rc = bnx2_acquire_nvram_lock(bp)) != 0)
4011 return rc;
4012
4013 /* Enable access to flash interface */
4014 bnx2_enable_nvram_access(bp);
4015
4016 /* Reconfigure the flash interface */
4017 REG_WR(bp, BNX2_NVM_CFG1, flash->config1);
4018 REG_WR(bp, BNX2_NVM_CFG2, flash->config2);
4019 REG_WR(bp, BNX2_NVM_CFG3, flash->config3);
4020 REG_WR(bp, BNX2_NVM_WRITE1, flash->write1);
4021
4022 /* Disable access to flash interface */
4023 bnx2_disable_nvram_access(bp);
4024 bnx2_release_nvram_lock(bp);
4025
4026 break;
4027 }
4028 }
4029 } /* if (val & 0x40000000) */
4030
4031 if (j == entry_count) {
4032 bp->flash_info = NULL;
2f23c523 4033 printk(KERN_ALERT PFX "Unknown flash/EEPROM type.\n");
1122db71 4034 return -ENODEV;
b6016b76
MC		 4035 }
4036
e30372c9 4037get_flash_size:
2726d6e1 4038 val = bnx2_shmem_rd(bp, BNX2_SHARED_HW_CFG_CONFIG2);
1122db71
MC		 4039 val &= BNX2_SHARED_HW_CFG2_NVM_SIZE_MASK;
4040 if (val)
4041 bp->flash_size = val;
4042 else
4043 bp->flash_size = bp->flash_info->total_size;
4044
b6016b76
MC		 4045 return rc;
4046}
4047
4048static int
4049bnx2_nvram_read(struct bnx2 *bp, u32 offset, u8 *ret_buf,
4050 int buf_size)
4051{
4052 int rc = 0;
4053 u32 cmd_flags, offset32, len32, extra;
4054
4055 if (buf_size == 0)
4056 return 0;
4057
4058 /* Request access to the flash interface. */
4059 if ((rc = bnx2_acquire_nvram_lock(bp)) != 0)
4060 return rc;
4061
4062 /* Enable access to flash interface */
4063 bnx2_enable_nvram_access(bp);
4064
4065 len32 = buf_size;
4066 offset32 = offset;
4067 extra = 0;
4068
4069 cmd_flags = 0;
4070
4071 if (offset32 & 3) {
4072 u8 buf[4];
4073 u32 pre_len;
4074
4075 offset32 &= ~3;
4076 pre_len = 4 - (offset & 3);
4077
4078 if (pre_len >= len32) {
4079 pre_len = len32;
4080 cmd_flags = BNX2_NVM_COMMAND_FIRST |
4081 BNX2_NVM_COMMAND_LAST;
4082 }
4083 else {
4084 cmd_flags = BNX2_NVM_COMMAND_FIRST;
4085 }
4086
4087 rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags);
4088
4089 if (rc)
4090 return rc;
4091
4092 memcpy(ret_buf, buf + (offset & 3), pre_len);
4093
4094 offset32 += 4;
4095 ret_buf += pre_len;
4096 len32 -= pre_len;
4097 }
4098 if (len32 & 3) {
4099 extra = 4 - (len32 & 3);
4100 len32 = (len32 + 4) & ~3;
4101 }
4102
4103 if (len32 == 4) {
4104 u8 buf[4];
4105
4106 if (cmd_flags)
4107 cmd_flags = BNX2_NVM_COMMAND_LAST;
4108 else
4109 cmd_flags = BNX2_NVM_COMMAND_FIRST |
4110 BNX2_NVM_COMMAND_LAST;
4111
4112 rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags);
4113
4114 memcpy(ret_buf, buf, 4 - extra);
4115 }
4116 else if (len32 > 0) {
4117 u8 buf[4];
4118
4119 /* Read the first word. */
4120 if (cmd_flags)
4121 cmd_flags = 0;
4122 else
4123 cmd_flags = BNX2_NVM_COMMAND_FIRST;
4124
4125 rc = bnx2_nvram_read_dword(bp, offset32, ret_buf, cmd_flags);
4126
4127 /* Advance to the next dword. */
4128 offset32 += 4;
4129 ret_buf += 4;
4130 len32 -= 4;
4131
4132 while (len32 > 4 && rc == 0) {
4133 rc = bnx2_nvram_read_dword(bp, offset32, ret_buf, 0);
4134
4135 /* Advance to the next dword. */
4136 offset32 += 4;
4137 ret_buf += 4;
4138 len32 -= 4;
4139 }
4140
4141 if (rc)
4142 return rc;
4143
4144 cmd_flags = BNX2_NVM_COMMAND_LAST;
4145 rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags);
4146
4147 memcpy(ret_buf, buf, 4 - extra);
4148 }
4149
4150 /* Disable access to flash interface */
4151 bnx2_disable_nvram_access(bp);
4152
4153 bnx2_release_nvram_lock(bp);
4154
4155 return rc;
4156}
4157
4158static int
4159bnx2_nvram_write(struct bnx2 *bp, u32 offset, u8 *data_buf,
4160 int buf_size)
4161{
4162 u32 written, offset32, len32;
e6be763f 4163 u8 *buf, start[4], end[4], *align_buf = NULL, *flash_buffer = NULL;
b6016b76
MC		 4164 int rc = 0;
4165 int align_start, align_end;
4166
4167 buf = data_buf;
4168 offset32 = offset;
4169 len32 = buf_size;
4170 align_start = align_end = 0;
4171
4172 if ((align_start = (offset32 & 3))) {
4173 offset32 &= ~3;
c873879c
MC		 4174 len32 += align_start;
4175 if (len32 < 4)
4176 len32 = 4;
b6016b76
MC		 4177 if ((rc = bnx2_nvram_read(bp, offset32, start, 4)))
4178 return rc;
4179 }
4180
4181 if (len32 & 3) {
c873879c
MC		 4182 align_end = 4 - (len32 & 3);
4183 len32 += align_end;
4184 if ((rc = bnx2_nvram_read(bp, offset32 + len32 - 4, end, 4)))
4185 return rc;
b6016b76
MC		 4186 }
4187
4188 if (align_start || align_end) {
e6be763f
MC		 4189 align_buf = kmalloc(len32, GFP_KERNEL);
4190 if (align_buf == NULL)
b6016b76
MC		 4191 return -ENOMEM;
4192 if (align_start) {
e6be763f 4193 memcpy(align_buf, start, 4);
b6016b76
MC		 4194 }
4195 if (align_end) {
e6be763f 4196 memcpy(align_buf + len32 - 4, end, 4);
b6016b76 4197 }
e6be763f
MC		 4198 memcpy(align_buf + align_start, data_buf, buf_size);
4199 buf = align_buf;
b6016b76
MC		 4200 }
4201
e30372c9 4202 if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) {
ae181bc4
MC		 4203 flash_buffer = kmalloc(264, GFP_KERNEL);
4204 if (flash_buffer == NULL) {
4205 rc = -ENOMEM;
4206 goto nvram_write_end;
4207 }
4208 }
4209
b6016b76
MC		 4210 written = 0;
4211 while ((written < len32) && (rc == 0)) {
4212 u32 page_start, page_end, data_start, data_end;
4213 u32 addr, cmd_flags;
4214 int i;
b6016b76
MC		 4215
4216 /* Find the page_start addr */
4217 page_start = offset32 + written;
4218 page_start -= (page_start % bp->flash_info->page_size);
4219 /* Find the page_end addr */
4220 page_end = page_start + bp->flash_info->page_size;
4221 /* Find the data_start addr */
4222 data_start = (written == 0) ? offset32 : page_start;
4223 /* Find the data_end addr */
6aa20a22 4224 data_end = (page_end > offset32 + len32) ?
b6016b76
MC		 4225 (offset32 + len32) : page_end;
4226
4227 /* Request access to the flash interface. */
4228 if ((rc = bnx2_acquire_nvram_lock(bp)) != 0)
4229 goto nvram_write_end;
4230
4231 /* Enable access to flash interface */
4232 bnx2_enable_nvram_access(bp);
4233
4234 cmd_flags = BNX2_NVM_COMMAND_FIRST;
e30372c9 4235 if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) {
b6016b76
MC		 4236 int j;
4237
4238 /* Read the whole page into the buffer
4239 * (non-buffer flash only) */
4240 for (j = 0; j < bp->flash_info->page_size; j += 4) {
4241 if (j == (bp->flash_info->page_size - 4)) {
4242 cmd_flags |= BNX2_NVM_COMMAND_LAST;
4243 }
4244 rc = bnx2_nvram_read_dword(bp,
6aa20a22
JG		 4245 page_start + j,
4246 &flash_buffer[j],
b6016b76
MC		 4247 cmd_flags);
4248
4249 if (rc)
4250 goto nvram_write_end;
4251
4252 cmd_flags = 0;
4253 }
4254 }
4255
4256 /* Enable writes to flash interface (unlock write-protect) */
4257 if ((rc = bnx2_enable_nvram_write(bp)) != 0)
4258 goto nvram_write_end;
4259
b6016b76
MC		 4260 /* Loop to write back the buffer data from page_start to
4261 * data_start */
4262 i = 0;
e30372c9 4263 if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) {
c873879c
MC		 4264 /* Erase the page */
4265 if ((rc = bnx2_nvram_erase_page(bp, page_start)) != 0)
4266 goto nvram_write_end;
4267
4268 /* Re-enable the write again for the actual write */
4269 bnx2_enable_nvram_write(bp);
4270
b6016b76
MC		 4271 for (addr = page_start; addr < data_start;
4272 addr += 4, i += 4) {
6aa20a22 4273
b6016b76
MC		 4274 rc = bnx2_nvram_write_dword(bp, addr,
4275 &flash_buffer[i], cmd_flags);
4276
4277 if (rc != 0)
4278 goto nvram_write_end;
4279
4280 cmd_flags = 0;
4281 }
4282 }
4283
4284 /* Loop to write the new data from data_start to data_end */
bae25761 4285 for (addr = data_start; addr < data_end; addr += 4, i += 4) {
b6016b76 4286 if ((addr == page_end - 4) ||
e30372c9 4287 ((bp->flash_info->flags & BNX2_NV_BUFFERED) &&
b6016b76
MC		 4288 (addr == data_end - 4))) {
4289
4290 cmd_flags |= BNX2_NVM_COMMAND_LAST;
4291 }
4292 rc = bnx2_nvram_write_dword(bp, addr, buf,
4293 cmd_flags);
4294
4295 if (rc != 0)
4296 goto nvram_write_end;
4297
4298 cmd_flags = 0;
4299 buf += 4;
4300 }
4301
4302 /* Loop to write back the buffer data from data_end
4303 * to page_end */
e30372c9 4304 if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) {
b6016b76
MC		 4305 for (addr = data_end; addr < page_end;
4306 addr += 4, i += 4) {
6aa20a22 4307
b6016b76
MC		 4308 if (addr == page_end-4) {
4309 cmd_flags = BNX2_NVM_COMMAND_LAST;
4310 }
4311 rc = bnx2_nvram_write_dword(bp, addr,
4312 &flash_buffer[i], cmd_flags);
4313
4314 if (rc != 0)
4315 goto nvram_write_end;
4316
4317 cmd_flags = 0;
4318 }
4319 }
4320
4321 /* Disable writes to flash interface (lock write-protect) */
4322 bnx2_disable_nvram_write(bp);
4323
4324 /* Disable access to flash interface */
4325 bnx2_disable_nvram_access(bp);
4326 bnx2_release_nvram_lock(bp);
4327
4328 /* Increment written */
4329 written += data_end - data_start;
4330 }
4331
4332nvram_write_end:
e6be763f
MC		 4333 kfree(flash_buffer);
4334 kfree(align_buf);
b6016b76
MC		 4335 return rc;
4336}
4337
0d8a6571 4338static void
7c62e83b 4339bnx2_init_fw_cap(struct bnx2 *bp)
0d8a6571 4340{
7c62e83b 4341 u32 val, sig = 0;
0d8a6571 4342
583c28e5 4343 bp->phy_flags &= ~BNX2_PHY_FLAG_REMOTE_PHY_CAP;
7c62e83b
MC		 4344 bp->flags &= ~BNX2_FLAG_CAN_KEEP_VLAN;
4345
4346 if (!(bp->flags & BNX2_FLAG_ASF_ENABLE))
4347 bp->flags |= BNX2_FLAG_CAN_KEEP_VLAN;
0d8a6571 4348
2726d6e1 4349 val = bnx2_shmem_rd(bp, BNX2_FW_CAP_MB);
0d8a6571
MC		 4350 if ((val & BNX2_FW_CAP_SIGNATURE_MASK) != BNX2_FW_CAP_SIGNATURE)
4351 return;
4352
7c62e83b
MC		 4353 if ((val & BNX2_FW_CAP_CAN_KEEP_VLAN) == BNX2_FW_CAP_CAN_KEEP_VLAN) {
4354 bp->flags |= BNX2_FLAG_CAN_KEEP_VLAN;
4355 sig |= BNX2_DRV_ACK_CAP_SIGNATURE | BNX2_FW_CAP_CAN_KEEP_VLAN;
4356 }
4357
4358 if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
4359 (val & BNX2_FW_CAP_REMOTE_PHY_CAPABLE)) {
4360 u32 link;
4361
583c28e5 4362 bp->phy_flags |= BNX2_PHY_FLAG_REMOTE_PHY_CAP;
0d8a6571 4363
7c62e83b
MC		 4364 link = bnx2_shmem_rd(bp, BNX2_LINK_STATUS);
4365 if (link & BNX2_LINK_STATUS_SERDES_LINK)
0d8a6571
MC		 4366 bp->phy_port = PORT_FIBRE;
4367 else
4368 bp->phy_port = PORT_TP;
489310a4 4369
7c62e83b
MC		 4370 sig |= BNX2_DRV_ACK_CAP_SIGNATURE |
4371 BNX2_FW_CAP_REMOTE_PHY_CAPABLE;
0d8a6571 4372 }
7c62e83b
MC		 4373
4374 if (netif_running(bp->dev) && sig)
4375 bnx2_shmem_wr(bp, BNX2_DRV_ACK_CAP_MB, sig);
0d8a6571
MC		 4376}
4377
b4b36042
MC		 4378static void
4379bnx2_setup_msix_tbl(struct bnx2 *bp)
4380{
4381 REG_WR(bp, BNX2_PCI_GRC_WINDOW_ADDR, BNX2_PCI_GRC_WINDOW_ADDR_SEP_WIN);
4382
4383 REG_WR(bp, BNX2_PCI_GRC_WINDOW2_ADDR, BNX2_MSIX_TABLE_ADDR);
4384 REG_WR(bp, BNX2_PCI_GRC_WINDOW3_ADDR, BNX2_MSIX_PBA_ADDR);
4385}
4386
b6016b76
MC		 4387static int
4388bnx2_reset_chip(struct bnx2 *bp, u32 reset_code)
4389{
4390 u32 val;
4391 int i, rc = 0;
489310a4 4392 u8 old_port;
b6016b76
MC		 4393
4394 /* Wait for the current PCI transaction to complete before
4395 * issuing a reset. */
4396 REG_WR(bp, BNX2_MISC_ENABLE_CLR_BITS,
4397 BNX2_MISC_ENABLE_CLR_BITS_TX_DMA_ENABLE |
4398 BNX2_MISC_ENABLE_CLR_BITS_DMA_ENGINE_ENABLE |
4399 BNX2_MISC_ENABLE_CLR_BITS_RX_DMA_ENABLE |
4400 BNX2_MISC_ENABLE_CLR_BITS_HOST_COALESCE_ENABLE);
4401 val = REG_RD(bp, BNX2_MISC_ENABLE_CLR_BITS);
4402 udelay(5);
4403
b090ae2b 4404 /* Wait for the firmware to tell us it is ok to issue a reset. */
a2f13890 4405 bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT0 | reset_code, 1, 1);
b090ae2b 4406
b6016b76
MC		 4407 /* Deposit a driver reset signature so the firmware knows that
4408 * this is a soft reset. */
2726d6e1
MC		 4409 bnx2_shmem_wr(bp, BNX2_DRV_RESET_SIGNATURE,
4410 BNX2_DRV_RESET_SIGNATURE_MAGIC);
b6016b76 4411
b6016b76
MC		 4412 /* Do a dummy read to force the chip to complete all current transaction
4413 * before we issue a reset. */
4414 val = REG_RD(bp, BNX2_MISC_ID);
4415
234754d5
MC		 4416 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
4417 REG_WR(bp, BNX2_MISC_COMMAND, BNX2_MISC_COMMAND_SW_RESET);
4418 REG_RD(bp, BNX2_MISC_COMMAND);
4419 udelay(5);
b6016b76 4420
234754d5
MC		 4421 val = BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
4422 BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP;
b6016b76 4423
234754d5 4424 pci_write_config_dword(bp->pdev, BNX2_PCICFG_MISC_CONFIG, val);
b6016b76 4425
234754d5
MC		 4426 } else {
4427 val = BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |
4428 BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
4429 BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP;
4430
4431 /* Chip reset. */
4432 REG_WR(bp, BNX2_PCICFG_MISC_CONFIG, val);
4433
594a9dfa
MC		 4434 /* Reading back any register after chip reset will hang the
4435 * bus on 5706 A0 and A1. The msleep below provides plenty
4436 * of margin for write posting.
4437 */
234754d5 4438 if ((CHIP_ID(bp) == CHIP_ID_5706_A0) ||
8e545881
AV		 4439 (CHIP_ID(bp) == CHIP_ID_5706_A1))
4440 msleep(20);
b6016b76 4441
234754d5
MC		 4442 /* Reset takes approximate 30 usec */
4443 for (i = 0; i < 10; i++) {
4444 val = REG_RD(bp, BNX2_PCICFG_MISC_CONFIG);
4445 if ((val & (BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |
4446 BNX2_PCICFG_MISC_CONFIG_CORE_RST_BSY)) == 0)
4447 break;
4448 udelay(10);
4449 }
4450
4451 if (val & (BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |
4452 BNX2_PCICFG_MISC_CONFIG_CORE_RST_BSY)) {
4453 printk(KERN_ERR PFX "Chip reset did not complete\n");
4454 return -EBUSY;
4455 }
b6016b76
MC		 4456 }
4457
4458 /* Make sure byte swapping is properly configured. */
4459 val = REG_RD(bp, BNX2_PCI_SWAP_DIAG0);
4460 if (val != 0x01020304) {
4461 printk(KERN_ERR PFX "Chip not in correct endian mode\n");
4462 return -ENODEV;
4463 }
4464
b6016b76 4465 /* Wait for the firmware to finish its initialization. */
a2f13890 4466 rc = bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT1 | reset_code, 1, 0);
b090ae2b
MC		 4467 if (rc)
4468 return rc;
b6016b76 4469
0d8a6571 4470 spin_lock_bh(&bp->phy_lock);
489310a4 4471 old_port = bp->phy_port;
7c62e83b 4472 bnx2_init_fw_cap(bp);
583c28e5
MC		 4473 if ((bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) &&
4474 old_port != bp->phy_port)
0d8a6571
MC		 4475 bnx2_set_default_remote_link(bp);
4476 spin_unlock_bh(&bp->phy_lock);
4477
b6016b76
MC		 4478 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
4479 /* Adjust the voltage regular to two steps lower. The default
4480 * of this register is 0x0000000e. */
4481 REG_WR(bp, BNX2_MISC_VREG_CONTROL, 0x000000fa);
4482
4483 /* Remove bad rbuf memory from the free pool. */
4484 rc = bnx2_alloc_bad_rbuf(bp);
4485 }
4486
f86e82fb 4487 if (bp->flags & BNX2_FLAG_USING_MSIX)
b4b36042
MC		 4488 bnx2_setup_msix_tbl(bp);
4489
b6016b76
MC		 4490 return rc;
4491}
4492
4493static int
4494bnx2_init_chip(struct bnx2 *bp)
4495{
4496 u32 val;
b4b36042 4497 int rc, i;
b6016b76
MC		 4498
4499 /* Make sure the interrupt is not active. */
4500 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
4501
4502 val = BNX2_DMA_CONFIG_DATA_BYTE_SWAP |
4503 BNX2_DMA_CONFIG_DATA_WORD_SWAP |
4504#ifdef __BIG_ENDIAN
6aa20a22 4505 BNX2_DMA_CONFIG_CNTL_BYTE_SWAP |
b6016b76 4506#endif
6aa20a22 4507 BNX2_DMA_CONFIG_CNTL_WORD_SWAP |
b6016b76
MC		 4508 DMA_READ_CHANS << 12 |
4509 DMA_WRITE_CHANS << 16;
4510
4511 val |= (0x2 << 20) | (1 << 11);
4512
f86e82fb 4513 if ((bp->flags & BNX2_FLAG_PCIX) && (bp->bus_speed_mhz == 133))
b6016b76
MC		 4514 val |= (1 << 23);
4515
4516 if ((CHIP_NUM(bp) == CHIP_NUM_5706) &&
f86e82fb 4517 (CHIP_ID(bp) != CHIP_ID_5706_A0) && !(bp->flags & BNX2_FLAG_PCIX))
b6016b76
MC		 4518 val |= BNX2_DMA_CONFIG_CNTL_PING_PONG_DMA;
4519
4520 REG_WR(bp, BNX2_DMA_CONFIG, val);
4521
4522 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
4523 val = REG_RD(bp, BNX2_TDMA_CONFIG);
4524 val |= BNX2_TDMA_CONFIG_ONE_DMA;
4525 REG_WR(bp, BNX2_TDMA_CONFIG, val);
4526 }
4527
f86e82fb 4528 if (bp->flags & BNX2_FLAG_PCIX) {
b6016b76
MC		 4529 u16 val16;
4530
4531 pci_read_config_word(bp->pdev, bp->pcix_cap + PCI_X_CMD,
4532 &val16);
4533 pci_write_config_word(bp->pdev, bp->pcix_cap + PCI_X_CMD,
4534 val16 & ~PCI_X_CMD_ERO);
4535 }
4536
4537 REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS,
4538 BNX2_MISC_ENABLE_SET_BITS_HOST_COALESCE_ENABLE |
4539 BNX2_MISC_ENABLE_STATUS_BITS_RX_V2P_ENABLE |
4540 BNX2_MISC_ENABLE_STATUS_BITS_CONTEXT_ENABLE);
4541
4542 /* Initialize context mapping and zero out the quick contexts. The
4543 * context block must have already been enabled. */
641bdcd5
MC		 4544 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
4545 rc = bnx2_init_5709_context(bp);
4546 if (rc)
4547 return rc;
4548 } else
59b47d8a 4549 bnx2_init_context(bp);
b6016b76 4550
fba9fe91
MC		 4551 if ((rc = bnx2_init_cpus(bp)) != 0)
4552 return rc;
4553
b6016b76
MC		 4554 bnx2_init_nvram(bp);
4555
5fcaed01 4556 bnx2_set_mac_addr(bp, bp->dev->dev_addr, 0);
b6016b76
MC		 4557
4558 val = REG_RD(bp, BNX2_MQ_CONFIG);
4559 val &= ~BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE;
4560 val |= BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE_256;
68c9f75a
MC		 4561 if (CHIP_ID(bp) == CHIP_ID_5709_A0 || CHIP_ID(bp) == CHIP_ID_5709_A1)
4562 val |= BNX2_MQ_CONFIG_HALT_DIS;
4563
b6016b76
MC		 4564 REG_WR(bp, BNX2_MQ_CONFIG, val);
4565
4566 val = 0x10000 + (MAX_CID_CNT * MB_KERNEL_CTX_SIZE);
4567 REG_WR(bp, BNX2_MQ_KNL_BYP_WIND_START, val);
4568 REG_WR(bp, BNX2_MQ_KNL_WIND_END, val);
4569
4570 val = (BCM_PAGE_BITS - 8) << 24;
4571 REG_WR(bp, BNX2_RV2P_CONFIG, val);
4572
4573 /* Configure page size. */
4574 val = REG_RD(bp, BNX2_TBDR_CONFIG);
4575 val &= ~BNX2_TBDR_CONFIG_PAGE_SIZE;
4576 val |= (BCM_PAGE_BITS - 8) << 24 | 0x40;
4577 REG_WR(bp, BNX2_TBDR_CONFIG, val);
4578
4579 val = bp->mac_addr[0] +
4580 (bp->mac_addr[1] << 8) +
4581 (bp->mac_addr[2] << 16) +
4582 bp->mac_addr[3] +
4583 (bp->mac_addr[4] << 8) +
4584 (bp->mac_addr[5] << 16);
4585 REG_WR(bp, BNX2_EMAC_BACKOFF_SEED, val);
4586
4587 /* Program the MTU. Also include 4 bytes for CRC32. */
4588 val = bp->dev->mtu + ETH_HLEN + 4;
4589 if (val > (MAX_ETHERNET_PACKET_SIZE + 4))
4590 val |= BNX2_EMAC_RX_MTU_SIZE_JUMBO_ENA;
4591 REG_WR(bp, BNX2_EMAC_RX_MTU_SIZE, val);
4592
b4b36042
MC		 4593 for (i = 0; i < BNX2_MAX_MSIX_VEC; i++)
4594 bp->bnx2_napi[i].last_status_idx = 0;
4595
efba0180
MC		 4596 bp->idle_chk_status_idx = 0xffff;
4597
b6016b76
MC		 4598 bp->rx_mode = BNX2_EMAC_RX_MODE_SORT_MODE;
4599
4600 /* Set up how to generate a link change interrupt. */
4601 REG_WR(bp, BNX2_EMAC_ATTENTION_ENA, BNX2_EMAC_ATTENTION_ENA_LINK);
4602
4603 REG_WR(bp, BNX2_HC_STATUS_ADDR_L,
4604 (u64) bp->status_blk_mapping & 0xffffffff);
4605 REG_WR(bp, BNX2_HC_STATUS_ADDR_H, (u64) bp->status_blk_mapping >> 32);
4606
4607 REG_WR(bp, BNX2_HC_STATISTICS_ADDR_L,
4608 (u64) bp->stats_blk_mapping & 0xffffffff);
4609 REG_WR(bp, BNX2_HC_STATISTICS_ADDR_H,
4610 (u64) bp->stats_blk_mapping >> 32);
4611
6aa20a22 4612 REG_WR(bp, BNX2_HC_TX_QUICK_CONS_TRIP,
b6016b76
MC		 4613 (bp->tx_quick_cons_trip_int << 16) | bp->tx_quick_cons_trip);
4614
4615 REG_WR(bp, BNX2_HC_RX_QUICK_CONS_TRIP,
4616 (bp->rx_quick_cons_trip_int << 16) | bp->rx_quick_cons_trip);
4617
4618 REG_WR(bp, BNX2_HC_COMP_PROD_TRIP,
4619 (bp->comp_prod_trip_int << 16) | bp->comp_prod_trip);
4620
4621 REG_WR(bp, BNX2_HC_TX_TICKS, (bp->tx_ticks_int << 16) | bp->tx_ticks);
4622
4623 REG_WR(bp, BNX2_HC_RX_TICKS, (bp->rx_ticks_int << 16) | bp->rx_ticks);
4624
4625 REG_WR(bp, BNX2_HC_COM_TICKS,
4626 (bp->com_ticks_int << 16) | bp->com_ticks);
4627
4628 REG_WR(bp, BNX2_HC_CMD_TICKS,
4629 (bp->cmd_ticks_int << 16) | bp->cmd_ticks);
4630
02537b06
MC		 4631 if (CHIP_NUM(bp) == CHIP_NUM_5708)
4632 REG_WR(bp, BNX2_HC_STATS_TICKS, 0);
4633 else
7ea6920e 4634 REG_WR(bp, BNX2_HC_STATS_TICKS, bp->stats_ticks);
b6016b76
MC		 4635 REG_WR(bp, BNX2_HC_STAT_COLLECT_TICKS, 0xbb8); /* 3ms */
4636
4637 if (CHIP_ID(bp) == CHIP_ID_5706_A1)
8e6a72c4 4638 val = BNX2_HC_CONFIG_COLLECT_STATS;
b6016b76 4639 else {
8e6a72c4
MC		 4640 val = BNX2_HC_CONFIG_RX_TMR_MODE | BNX2_HC_CONFIG_TX_TMR_MODE |
4641 BNX2_HC_CONFIG_COLLECT_STATS;
b6016b76
MC		 4642 }
4643
5e9ad9e1 4644 if (bp->irq_nvecs > 1) {
c76c0475
MC		 4645 REG_WR(bp, BNX2_HC_MSIX_BIT_VECTOR,
4646 BNX2_HC_MSIX_BIT_VECTOR_VAL);
4647
5e9ad9e1
MC		 4648 val |= BNX2_HC_CONFIG_SB_ADDR_INC_128B;
4649 }
4650
4651 if (bp->flags & BNX2_FLAG_ONE_SHOT_MSI)
4652 val |= BNX2_HC_CONFIG_ONE_SHOT;
4653
4654 REG_WR(bp, BNX2_HC_CONFIG, val);
4655
4656 for (i = 1; i < bp->irq_nvecs; i++) {
4657 u32 base = ((i - 1) * BNX2_HC_SB_CONFIG_SIZE) +
4658 BNX2_HC_SB_CONFIG_1;
4659
6f743ca0 4660 REG_WR(bp, base,
c76c0475 4661 BNX2_HC_SB_CONFIG_1_TX_TMR_MODE |
5e9ad9e1 4662 BNX2_HC_SB_CONFIG_1_RX_TMR_MODE |
c76c0475
MC		 4663 BNX2_HC_SB_CONFIG_1_ONE_SHOT);
4664
6f743ca0 4665 REG_WR(bp, base + BNX2_HC_TX_QUICK_CONS_TRIP_OFF,
c76c0475
MC		 4666 (bp->tx_quick_cons_trip_int << 16) |
4667 bp->tx_quick_cons_trip);
4668
6f743ca0 4669 REG_WR(bp, base + BNX2_HC_TX_TICKS_OFF,
c76c0475
MC		 4670 (bp->tx_ticks_int << 16) | bp->tx_ticks);
4671
5e9ad9e1
MC		 4672 REG_WR(bp, base + BNX2_HC_RX_QUICK_CONS_TRIP_OFF,
4673 (bp->rx_quick_cons_trip_int << 16) |
4674 bp->rx_quick_cons_trip);
8e6a72c4 4675
5e9ad9e1
MC		 4676 REG_WR(bp, base + BNX2_HC_RX_TICKS_OFF,
4677 (bp->rx_ticks_int << 16) | bp->rx_ticks);
4678 }
8e6a72c4 4679
b6016b76
MC		 4680 /* Clear internal stats counters. */
4681 REG_WR(bp, BNX2_HC_COMMAND, BNX2_HC_COMMAND_CLR_STAT_NOW);
4682
da3e4fbe 4683 REG_WR(bp, BNX2_HC_ATTN_BITS_ENABLE, STATUS_ATTN_EVENTS);
b6016b76
MC		 4684
4685 /* Initialize the receive filter. */
4686 bnx2_set_rx_mode(bp->dev);
4687
0aa38df7
MC		 4688 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
4689 val = REG_RD(bp, BNX2_MISC_NEW_CORE_CTL);
4690 val |= BNX2_MISC_NEW_CORE_CTL_DMA_ENABLE;
4691 REG_WR(bp, BNX2_MISC_NEW_CORE_CTL, val);
4692 }
b090ae2b 4693 rc = bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT2 | BNX2_DRV_MSG_CODE_RESET,
a2f13890 4694 1, 0);
b6016b76 4695
df149d70 4696 REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS, BNX2_MISC_ENABLE_DEFAULT);
b6016b76
MC		 4697 REG_RD(bp, BNX2_MISC_ENABLE_SET_BITS);
4698
4699 udelay(20);
4700
bf5295bb
MC		 4701 bp->hc_cmd = REG_RD(bp, BNX2_HC_COMMAND);
4702
b090ae2b 4703 return rc;
b6016b76
MC		 4704}
4705
c76c0475
MC		 4706static void
4707bnx2_clear_ring_states(struct bnx2 *bp)
4708{
4709 struct bnx2_napi *bnapi;
35e9010b 4710 struct bnx2_tx_ring_info *txr;
bb4f98ab 4711 struct bnx2_rx_ring_info *rxr;
c76c0475
MC		 4712 int i;
4713
4714 for (i = 0; i < BNX2_MAX_MSIX_VEC; i++) {
4715 bnapi = &bp->bnx2_napi[i];
35e9010b 4716 txr = &bnapi->tx_ring;
bb4f98ab 4717 rxr = &bnapi->rx_ring;
c76c0475 4718
35e9010b
MC		 4719 txr->tx_cons = 0;
4720 txr->hw_tx_cons = 0;
bb4f98ab
MC		 4721 rxr->rx_prod_bseq = 0;
4722 rxr->rx_prod = 0;
4723 rxr->rx_cons = 0;
4724 rxr->rx_pg_prod = 0;
4725 rxr->rx_pg_cons = 0;
c76c0475
MC		 4726 }
4727}
4728
59b47d8a 4729static void
35e9010b 4730bnx2_init_tx_context(struct bnx2 *bp, u32 cid, struct bnx2_tx_ring_info *txr)
59b47d8a
MC		 4731{
4732 u32 val, offset0, offset1, offset2, offset3;
62a8313c 4733 u32 cid_addr = GET_CID_ADDR(cid);
59b47d8a
MC		 4734
4735 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
4736 offset0 = BNX2_L2CTX_TYPE_XI;
4737 offset1 = BNX2_L2CTX_CMD_TYPE_XI;
4738 offset2 = BNX2_L2CTX_TBDR_BHADDR_HI_XI;
4739 offset3 = BNX2_L2CTX_TBDR_BHADDR_LO_XI;
4740 } else {
4741 offset0 = BNX2_L2CTX_TYPE;
4742 offset1 = BNX2_L2CTX_CMD_TYPE;
4743 offset2 = BNX2_L2CTX_TBDR_BHADDR_HI;
4744 offset3 = BNX2_L2CTX_TBDR_BHADDR_LO;
4745 }
4746 val = BNX2_L2CTX_TYPE_TYPE_L2 | BNX2_L2CTX_TYPE_SIZE_L2;
62a8313c 4747 bnx2_ctx_wr(bp, cid_addr, offset0, val);
59b47d8a
MC		 4748
4749 val = BNX2_L2CTX_CMD_TYPE_TYPE_L2 | (8 << 16);
62a8313c 4750 bnx2_ctx_wr(bp, cid_addr, offset1, val);
59b47d8a 4751
35e9010b 4752 val = (u64) txr->tx_desc_mapping >> 32;
62a8313c 4753 bnx2_ctx_wr(bp, cid_addr, offset2, val);
59b47d8a 4754
35e9010b 4755 val = (u64) txr->tx_desc_mapping & 0xffffffff;
62a8313c 4756 bnx2_ctx_wr(bp, cid_addr, offset3, val);
59b47d8a 4757}
b6016b76
MC		 4758
4759static void
35e9010b 4760bnx2_init_tx_ring(struct bnx2 *bp, int ring_num)
b6016b76
MC		 4761{
4762 struct tx_bd *txbd;
c76c0475
MC		 4763 u32 cid = TX_CID;
4764 struct bnx2_napi *bnapi;
35e9010b 4765 struct bnx2_tx_ring_info *txr;
c76c0475 4766
35e9010b
MC		 4767 bnapi = &bp->bnx2_napi[ring_num];
4768 txr = &bnapi->tx_ring;
4769
4770 if (ring_num == 0)
4771 cid = TX_CID;
4772 else
4773 cid = TX_TSS_CID + ring_num - 1;
b6016b76 4774
2f8af120
MC		 4775 bp->tx_wake_thresh = bp->tx_ring_size / 2;
4776
35e9010b 4777 txbd = &txr->tx_desc_ring[MAX_TX_DESC_CNT];
6aa20a22 4778
35e9010b
MC		 4779 txbd->tx_bd_haddr_hi = (u64) txr->tx_desc_mapping >> 32;
4780 txbd->tx_bd_haddr_lo = (u64) txr->tx_desc_mapping & 0xffffffff;
b6016b76 4781
35e9010b
MC		 4782 txr->tx_prod = 0;
4783 txr->tx_prod_bseq = 0;
6aa20a22 4784
35e9010b
MC		 4785 txr->tx_bidx_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_TX_HOST_BIDX;
4786 txr->tx_bseq_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_TX_HOST_BSEQ;
b6016b76 4787
35e9010b 4788 bnx2_init_tx_context(bp, cid, txr);
b6016b76
MC		 4789}
4790
4791static void
5d5d0015
MC		 4792bnx2_init_rxbd_rings(struct rx_bd *rx_ring[], dma_addr_t dma[], u32 buf_size,
4793 int num_rings)
b6016b76 4794{
b6016b76 4795 int i;
5d5d0015 4796 struct rx_bd *rxbd;
6aa20a22 4797
5d5d0015 4798 for (i = 0; i < num_rings; i++) {
13daffa2 4799 int j;
b6016b76 4800
5d5d0015 4801 rxbd = &rx_ring[i][0];
13daffa2 4802 for (j = 0; j < MAX_RX_DESC_CNT; j++, rxbd++) {
5d5d0015 4803 rxbd->rx_bd_len = buf_size;
13daffa2
MC		 4804 rxbd->rx_bd_flags = RX_BD_FLAGS_START | RX_BD_FLAGS_END;
4805 }
5d5d0015 4806 if (i == (num_rings - 1))
13daffa2
MC		 4807 j = 0;
4808 else
4809 j = i + 1;
5d5d0015
MC		 4810 rxbd->rx_bd_haddr_hi = (u64) dma[j] >> 32;
4811 rxbd->rx_bd_haddr_lo = (u64) dma[j] & 0xffffffff;
13daffa2 4812 }
5d5d0015
MC		 4813}
4814
4815static void
bb4f98ab 4816bnx2_init_rx_ring(struct bnx2 *bp, int ring_num)
5d5d0015
MC		 4817{
4818 int i;
4819 u16 prod, ring_prod;
bb4f98ab
MC		 4820 u32 cid, rx_cid_addr, val;
4821 struct bnx2_napi *bnapi = &bp->bnx2_napi[ring_num];
4822 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
4823
4824 if (ring_num == 0)
4825 cid = RX_CID;
4826 else
4827 cid = RX_RSS_CID + ring_num - 1;
4828
4829 rx_cid_addr = GET_CID_ADDR(cid);
5d5d0015 4830
bb4f98ab 4831 bnx2_init_rxbd_rings(rxr->rx_desc_ring, rxr->rx_desc_mapping,
5d5d0015
MC		 4832 bp->rx_buf_use_size, bp->rx_max_ring);
4833
bb4f98ab 4834 bnx2_init_rx_context(bp, cid);
83e3fc89
MC		 4835
4836 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
4837 val = REG_RD(bp, BNX2_MQ_MAP_L2_5);
4838 REG_WR(bp, BNX2_MQ_MAP_L2_5, val | BNX2_MQ_MAP_L2_5_ARM);
4839 }
4840
62a8313c 4841 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_PG_BUF_SIZE, 0);
47bf4246 4842 if (bp->rx_pg_ring_size) {
bb4f98ab
MC		 4843 bnx2_init_rxbd_rings(rxr->rx_pg_desc_ring,
4844 rxr->rx_pg_desc_mapping,
47bf4246
MC		 4845 PAGE_SIZE, bp->rx_max_pg_ring);
4846 val = (bp->rx_buf_use_size << 16) | PAGE_SIZE;
62a8313c
MC		 4847 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_PG_BUF_SIZE, val);
4848 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_RBDC_KEY,
5e9ad9e1 4849 BNX2_L2CTX_RBDC_JUMBO_KEY - ring_num);
47bf4246 4850
bb4f98ab 4851 val = (u64) rxr->rx_pg_desc_mapping[0] >> 32;
62a8313c 4852 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_PG_BDHADDR_HI, val);
47bf4246 4853
bb4f98ab 4854 val = (u64) rxr->rx_pg_desc_mapping[0] & 0xffffffff;
62a8313c 4855 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_PG_BDHADDR_LO, val);
47bf4246
MC		 4856
4857 if (CHIP_NUM(bp) == CHIP_NUM_5709)
4858 REG_WR(bp, BNX2_MQ_MAP_L2_3, BNX2_MQ_MAP_L2_3_DEFAULT);
4859 }
b6016b76 4860
bb4f98ab 4861 val = (u64) rxr->rx_desc_mapping[0] >> 32;
62a8313c 4862 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_BDHADDR_HI, val);
b6016b76 4863
bb4f98ab 4864 val = (u64) rxr->rx_desc_mapping[0] & 0xffffffff;
62a8313c 4865 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_BDHADDR_LO, val);
b6016b76 4866
bb4f98ab 4867 ring_prod = prod = rxr->rx_pg_prod;
47bf4246 4868 for (i = 0; i < bp->rx_pg_ring_size; i++) {
bb4f98ab 4869 if (bnx2_alloc_rx_page(bp, rxr, ring_prod) < 0)
47bf4246
MC		 4870 break;
4871 prod = NEXT_RX_BD(prod);
4872 ring_prod = RX_PG_RING_IDX(prod);
4873 }
bb4f98ab 4874 rxr->rx_pg_prod = prod;
47bf4246 4875
bb4f98ab 4876 ring_prod = prod = rxr->rx_prod;
236b6394 4877 for (i = 0; i < bp->rx_ring_size; i++) {
bb4f98ab 4878 if (bnx2_alloc_rx_skb(bp, rxr, ring_prod) < 0)
b6016b76 4879 break;
b6016b76
MC		 4880 prod = NEXT_RX_BD(prod);
4881 ring_prod = RX_RING_IDX(prod);
4882 }
bb4f98ab 4883 rxr->rx_prod = prod;
b6016b76 4884
bb4f98ab
MC		 4885 rxr->rx_bidx_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_HOST_BDIDX;
4886 rxr->rx_bseq_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_HOST_BSEQ;
4887 rxr->rx_pg_bidx_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_HOST_PG_BDIDX;
b6016b76 4888
bb4f98ab
MC		 4889 REG_WR16(bp, rxr->rx_pg_bidx_addr, rxr->rx_pg_prod);
4890 REG_WR16(bp, rxr->rx_bidx_addr, prod);
4891
4892 REG_WR(bp, rxr->rx_bseq_addr, rxr->rx_prod_bseq);
b6016b76
MC		 4893}
4894
35e9010b
MC		 4895static void
4896bnx2_init_all_rings(struct bnx2 *bp)
4897{
4898 int i;
5e9ad9e1 4899 u32 val;
35e9010b
MC		 4900
4901 bnx2_clear_ring_states(bp);
4902
4903 REG_WR(bp, BNX2_TSCH_TSS_CFG, 0);
4904 for (i = 0; i < bp->num_tx_rings; i++)
4905 bnx2_init_tx_ring(bp, i);
4906
4907 if (bp->num_tx_rings > 1)
4908 REG_WR(bp, BNX2_TSCH_TSS_CFG, ((bp->num_tx_rings - 1) << 24) |
4909 (TX_TSS_CID << 7));
4910
5e9ad9e1
MC		 4911 REG_WR(bp, BNX2_RLUP_RSS_CONFIG, 0);
4912 bnx2_reg_wr_ind(bp, BNX2_RXP_SCRATCH_RSS_TBL_SZ, 0);
4913
bb4f98ab
MC		 4914 for (i = 0; i < bp->num_rx_rings; i++)
4915 bnx2_init_rx_ring(bp, i);
5e9ad9e1
MC		 4916
4917 if (bp->num_rx_rings > 1) {
4918 u32 tbl_32;
4919 u8 *tbl = (u8 *) &tbl_32;
4920
4921 bnx2_reg_wr_ind(bp, BNX2_RXP_SCRATCH_RSS_TBL_SZ,
4922 BNX2_RXP_SCRATCH_RSS_TBL_MAX_ENTRIES);
4923
4924 for (i = 0; i < BNX2_RXP_SCRATCH_RSS_TBL_MAX_ENTRIES; i++) {
4925 tbl[i % 4] = i % (bp->num_rx_rings - 1);
4926 if ((i % 4) == 3)
4927 bnx2_reg_wr_ind(bp,
4928 BNX2_RXP_SCRATCH_RSS_TBL + i,
4929 cpu_to_be32(tbl_32));
4930 }
4931
4932 val = BNX2_RLUP_RSS_CONFIG_IPV4_RSS_TYPE_ALL_XI |
4933 BNX2_RLUP_RSS_CONFIG_IPV6_RSS_TYPE_ALL_XI;
4934
4935 REG_WR(bp, BNX2_RLUP_RSS_CONFIG, val);
4936
4937 }
35e9010b
MC		 4938}
4939
5d5d0015 4940static u32 bnx2_find_max_ring(u32 ring_size, u32 max_size)
13daffa2 4941{
5d5d0015 4942 u32 max, num_rings = 1;
13daffa2 4943
5d5d0015
MC		 4944 while (ring_size > MAX_RX_DESC_CNT) {
4945 ring_size -= MAX_RX_DESC_CNT;
13daffa2
MC		 4946 num_rings++;
4947 }
4948 /* round to next power of 2 */
5d5d0015 4949 max = max_size;
13daffa2
MC		 4950 while ((max & num_rings) == 0)
4951 max >>= 1;
4952
4953 if (num_rings != max)
4954 max <<= 1;
4955
5d5d0015
MC		 4956 return max;
4957}
4958
4959static void
4960bnx2_set_rx_ring_size(struct bnx2 *bp, u32 size)
4961{
84eaa187 4962 u32 rx_size, rx_space, jumbo_size;
5d5d0015
MC		 4963
4964 /* 8 for CRC and VLAN */
d89cb6af 4965 rx_size = bp->dev->mtu + ETH_HLEN + BNX2_RX_OFFSET + 8;
5d5d0015 4966
84eaa187
MC		 4967 rx_space = SKB_DATA_ALIGN(rx_size + BNX2_RX_ALIGN) + NET_SKB_PAD +
4968 sizeof(struct skb_shared_info);
4969
601d3d18 4970 bp->rx_copy_thresh = BNX2_RX_COPY_THRESH;
47bf4246
MC		 4971 bp->rx_pg_ring_size = 0;
4972 bp->rx_max_pg_ring = 0;
4973 bp->rx_max_pg_ring_idx = 0;
f86e82fb 4974 if ((rx_space > PAGE_SIZE) && !(bp->flags & BNX2_FLAG_JUMBO_BROKEN)) {
84eaa187
MC		 4975 int pages = PAGE_ALIGN(bp->dev->mtu - 40) >> PAGE_SHIFT;
4976
4977 jumbo_size = size * pages;
4978 if (jumbo_size > MAX_TOTAL_RX_PG_DESC_CNT)
4979 jumbo_size = MAX_TOTAL_RX_PG_DESC_CNT;
4980
4981 bp->rx_pg_ring_size = jumbo_size;
4982 bp->rx_max_pg_ring = bnx2_find_max_ring(jumbo_size,
4983 MAX_RX_PG_RINGS);
4984 bp->rx_max_pg_ring_idx = (bp->rx_max_pg_ring * RX_DESC_CNT) - 1;
601d3d18 4985 rx_size = BNX2_RX_COPY_THRESH + BNX2_RX_OFFSET;
84eaa187
MC		 4986 bp->rx_copy_thresh = 0;
4987 }
5d5d0015
MC		 4988
4989 bp->rx_buf_use_size = rx_size;
4990 /* hw alignment */
4991 bp->rx_buf_size = bp->rx_buf_use_size + BNX2_RX_ALIGN;
d89cb6af 4992 bp->rx_jumbo_thresh = rx_size - BNX2_RX_OFFSET;
5d5d0015
MC		 4993 bp->rx_ring_size = size;
4994 bp->rx_max_ring = bnx2_find_max_ring(size, MAX_RX_RINGS);
13daffa2
MC		 4995 bp->rx_max_ring_idx = (bp->rx_max_ring * RX_DESC_CNT) - 1;
4996}
4997
b6016b76
MC		 4998static void
4999bnx2_free_tx_skbs(struct bnx2 *bp)
5000{
5001 int i;
5002
35e9010b
MC		 5003 for (i = 0; i < bp->num_tx_rings; i++) {
5004 struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
5005 struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
5006 int j;
b6016b76 5007
35e9010b 5008 if (txr->tx_buf_ring == NULL)
b6016b76 5009 continue;
b6016b76 5010
35e9010b 5011 for (j = 0; j < TX_DESC_CNT; ) {
3d16af86 5012 struct sw_tx_bd *tx_buf = &txr->tx_buf_ring[j];
35e9010b 5013 struct sk_buff *skb = tx_buf->skb;
35e9010b
MC		 5014
5015 if (skb == NULL) {
5016 j++;
5017 continue;
5018 }
5019
3d16af86 5020 skb_dma_unmap(&bp->pdev->dev, skb, DMA_TO_DEVICE);
b6016b76 5021
35e9010b 5022 tx_buf->skb = NULL;
b6016b76 5023
3d16af86 5024 j += skb_shinfo(skb)->nr_frags + 1;
35e9010b 5025 dev_kfree_skb(skb);
b6016b76 5026 }
b6016b76 5027 }
b6016b76
MC		 5028}
5029
5030static void
5031bnx2_free_rx_skbs(struct bnx2 *bp)
5032{
5033 int i;
5034
bb4f98ab
MC		 5035 for (i = 0; i < bp->num_rx_rings; i++) {
5036 struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
5037 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
5038 int j;
b6016b76 5039
bb4f98ab
MC		 5040 if (rxr->rx_buf_ring == NULL)
5041 return;
b6016b76 5042
bb4f98ab
MC		 5043 for (j = 0; j < bp->rx_max_ring_idx; j++) {
5044 struct sw_bd *rx_buf = &rxr->rx_buf_ring[j];
5045 struct sk_buff *skb = rx_buf->skb;
b6016b76 5046
bb4f98ab
MC		 5047 if (skb == NULL)
5048 continue;
b6016b76 5049
bb4f98ab
MC		 5050 pci_unmap_single(bp->pdev,
5051 pci_unmap_addr(rx_buf, mapping),
5052 bp->rx_buf_use_size,
5053 PCI_DMA_FROMDEVICE);
b6016b76 5054
bb4f98ab
MC		 5055 rx_buf->skb = NULL;
5056
5057 dev_kfree_skb(skb);
5058 }
5059 for (j = 0; j < bp->rx_max_pg_ring_idx; j++)
5060 bnx2_free_rx_page(bp, rxr, j);
b6016b76
MC		 5061 }
5062}
5063
5064static void
5065bnx2_free_skbs(struct bnx2 *bp)
5066{
5067 bnx2_free_tx_skbs(bp);
5068 bnx2_free_rx_skbs(bp);
5069}
5070
5071static int
5072bnx2_reset_nic(struct bnx2 *bp, u32 reset_code)
5073{
5074 int rc;
5075
5076 rc = bnx2_reset_chip(bp, reset_code);
5077 bnx2_free_skbs(bp);
5078 if (rc)
5079 return rc;
5080
fba9fe91
MC		 5081 if ((rc = bnx2_init_chip(bp)) != 0)
5082 return rc;
5083
35e9010b 5084 bnx2_init_all_rings(bp);
b6016b76
MC		 5085 return 0;
5086}
5087
5088static int
9a120bc5 5089bnx2_init_nic(struct bnx2 *bp, int reset_phy)
b6016b76
MC		 5090{
5091 int rc;
5092
5093 if ((rc = bnx2_reset_nic(bp, BNX2_DRV_MSG_CODE_RESET)) != 0)
5094 return rc;
5095
80be4434 5096 spin_lock_bh(&bp->phy_lock);
9a120bc5 5097 bnx2_init_phy(bp, reset_phy);
b6016b76 5098 bnx2_set_link(bp);
543a827d
MC		 5099 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
5100 bnx2_remote_phy_event(bp);
0d8a6571 5101 spin_unlock_bh(&bp->phy_lock);
b6016b76
MC		 5102 return 0;
5103}
5104
74bf4ba3
MC		 5105static int
5106bnx2_shutdown_chip(struct bnx2 *bp)
5107{
5108 u32 reset_code;
5109
5110 if (bp->flags & BNX2_FLAG_NO_WOL)
5111 reset_code = BNX2_DRV_MSG_CODE_UNLOAD_LNK_DN;
5112 else if (bp->wol)
5113 reset_code = BNX2_DRV_MSG_CODE_SUSPEND_WOL;
5114 else
5115 reset_code = BNX2_DRV_MSG_CODE_SUSPEND_NO_WOL;
5116
5117 return bnx2_reset_chip(bp, reset_code);
5118}
5119
b6016b76
MC		 5120static int
5121bnx2_test_registers(struct bnx2 *bp)
5122{
5123 int ret;
5bae30c9 5124 int i, is_5709;
f71e1309 5125 static const struct {
b6016b76
MC		 5126 u16 offset;
5127 u16 flags;
5bae30c9 5128#define BNX2_FL_NOT_5709 1
b6016b76
MC		 5129 u32 rw_mask;
5130 u32 ro_mask;
5131 } reg_tbl[] = {
5132 { 0x006c, 0, 0x00000000, 0x0000003f },
5133 { 0x0090, 0, 0xffffffff, 0x00000000 },
5134 { 0x0094, 0, 0x00000000, 0x00000000 },
5135
5bae30c9
MC		 5136 { 0x0404, BNX2_FL_NOT_5709, 0x00003f00, 0x00000000 },
5137 { 0x0418, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
5138 { 0x041c, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
5139 { 0x0420, BNX2_FL_NOT_5709, 0x00000000, 0x80ffffff },
5140 { 0x0424, BNX2_FL_NOT_5709, 0x00000000, 0x00000000 },
5141 { 0x0428, BNX2_FL_NOT_5709, 0x00000000, 0x00000001 },
5142 { 0x0450, BNX2_FL_NOT_5709, 0x00000000, 0x0000ffff },
5143 { 0x0454, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
5144 { 0x0458, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
5145
5146 { 0x0808, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
5147 { 0x0854, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
5148 { 0x0868, BNX2_FL_NOT_5709, 0x00000000, 0x77777777 },
5149 { 0x086c, BNX2_FL_NOT_5709, 0x00000000, 0x77777777 },
5150 { 0x0870, BNX2_FL_NOT_5709, 0x00000000, 0x77777777 },
5151 { 0x0874, BNX2_FL_NOT_5709, 0x00000000, 0x77777777 },
5152
5153 { 0x0c00, BNX2_FL_NOT_5709, 0x00000000, 0x00000001 },
5154 { 0x0c04, BNX2_FL_NOT_5709, 0x00000000, 0x03ff0001 },
5155 { 0x0c08, BNX2_FL_NOT_5709, 0x0f0ff073, 0x00000000 },
b6016b76
MC		 5156
5157 { 0x1000, 0, 0x00000000, 0x00000001 },
15b169cc 5158 { 0x1004, BNX2_FL_NOT_5709, 0x00000000, 0x000f0001 },
b6016b76
MC		 5159
5160 { 0x1408, 0, 0x01c00800, 0x00000000 },
5161 { 0x149c, 0, 0x8000ffff, 0x00000000 },
5162 { 0x14a8, 0, 0x00000000, 0x000001ff },
5b0c76ad 5163 { 0x14ac, 0, 0x0fffffff, 0x10000000 },
b6016b76
MC		 5164 { 0x14b0, 0, 0x00000002, 0x00000001 },
5165 { 0x14b8, 0, 0x00000000, 0x00000000 },
5166 { 0x14c0, 0, 0x00000000, 0x00000009 },
5167 { 0x14c4, 0, 0x00003fff, 0x00000000 },
5168 { 0x14cc, 0, 0x00000000, 0x00000001 },
5169 { 0x14d0, 0, 0xffffffff, 0x00000000 },
b6016b76
MC		 5170
5171 { 0x1800, 0, 0x00000000, 0x00000001 },
5172 { 0x1804, 0, 0x00000000, 0x00000003 },
b6016b76
MC		 5173
5174 { 0x2800, 0, 0x00000000, 0x00000001 },
5175 { 0x2804, 0, 0x00000000, 0x00003f01 },
5176 { 0x2808, 0, 0x0f3f3f03, 0x00000000 },
5177 { 0x2810, 0, 0xffff0000, 0x00000000 },
5178 { 0x2814, 0, 0xffff0000, 0x00000000 },
5179 { 0x2818, 0, 0xffff0000, 0x00000000 },
5180 { 0x281c, 0, 0xffff0000, 0x00000000 },
5181 { 0x2834, 0, 0xffffffff, 0x00000000 },
5182 { 0x2840, 0, 0x00000000, 0xffffffff },
5183 { 0x2844, 0, 0x00000000, 0xffffffff },
5184 { 0x2848, 0, 0xffffffff, 0x00000000 },
5185 { 0x284c, 0, 0xf800f800, 0x07ff07ff },
5186
5187 { 0x2c00, 0, 0x00000000, 0x00000011 },
5188 { 0x2c04, 0, 0x00000000, 0x00030007 },
5189
b6016b76
MC		 5190 { 0x3c00, 0, 0x00000000, 0x00000001 },
5191 { 0x3c04, 0, 0x00000000, 0x00070000 },
5192 { 0x3c08, 0, 0x00007f71, 0x07f00000 },
5193 { 0x3c0c, 0, 0x1f3ffffc, 0x00000000 },
5194 { 0x3c10, 0, 0xffffffff, 0x00000000 },
5195 { 0x3c14, 0, 0x00000000, 0xffffffff },
5196 { 0x3c18, 0, 0x00000000, 0xffffffff },
5197 { 0x3c1c, 0, 0xfffff000, 0x00000000 },
5198 { 0x3c20, 0, 0xffffff00, 0x00000000 },
b6016b76
MC		 5199
5200 { 0x5004, 0, 0x00000000, 0x0000007f },
5201 { 0x5008, 0, 0x0f0007ff, 0x00000000 },
b6016b76 5202
b6016b76
MC		 5203 { 0x5c00, 0, 0x00000000, 0x00000001 },
5204 { 0x5c04, 0, 0x00000000, 0x0003000f },
5205 { 0x5c08, 0, 0x00000003, 0x00000000 },
5206 { 0x5c0c, 0, 0x0000fff8, 0x00000000 },
5207 { 0x5c10, 0, 0x00000000, 0xffffffff },
5208 { 0x5c80, 0, 0x00000000, 0x0f7113f1 },
5209 { 0x5c84, 0, 0x00000000, 0x0000f333 },
5210 { 0x5c88, 0, 0x00000000, 0x00077373 },
5211 { 0x5c8c, 0, 0x00000000, 0x0007f737 },
5212
5213 { 0x6808, 0, 0x0000ff7f, 0x00000000 },
5214 { 0x680c, 0, 0xffffffff, 0x00000000 },
5215 { 0x6810, 0, 0xffffffff, 0x00000000 },
5216 { 0x6814, 0, 0xffffffff, 0x00000000 },
5217 { 0x6818, 0, 0xffffffff, 0x00000000 },
5218 { 0x681c, 0, 0xffffffff, 0x00000000 },
5219 { 0x6820, 0, 0x00ff00ff, 0x00000000 },
5220 { 0x6824, 0, 0x00ff00ff, 0x00000000 },
5221 { 0x6828, 0, 0x00ff00ff, 0x00000000 },
5222 { 0x682c, 0, 0x03ff03ff, 0x00000000 },
5223 { 0x6830, 0, 0x03ff03ff, 0x00000000 },
5224 { 0x6834, 0, 0x03ff03ff, 0x00000000 },
5225 { 0x6838, 0, 0x03ff03ff, 0x00000000 },
5226 { 0x683c, 0, 0x0000ffff, 0x00000000 },
5227 { 0x6840, 0, 0x00000ff0, 0x00000000 },
5228 { 0x6844, 0, 0x00ffff00, 0x00000000 },
5229 { 0x684c, 0, 0xffffffff, 0x00000000 },
5230 { 0x6850, 0, 0x7f7f7f7f, 0x00000000 },
5231 { 0x6854, 0, 0x7f7f7f7f, 0x00000000 },
5232 { 0x6858, 0, 0x7f7f7f7f, 0x00000000 },
5233 { 0x685c, 0, 0x7f7f7f7f, 0x00000000 },
5234 { 0x6908, 0, 0x00000000, 0x0001ff0f },
5235 { 0x690c, 0, 0x00000000, 0x0ffe00f0 },
5236
5237 { 0xffff, 0, 0x00000000, 0x00000000 },
5238 };
5239
5240 ret = 0;
5bae30c9
MC		 5241 is_5709 = 0;
5242 if (CHIP_NUM(bp) == CHIP_NUM_5709)
5243 is_5709 = 1;
5244
b6016b76
MC		 5245 for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
5246 u32 offset, rw_mask, ro_mask, save_val, val;
5bae30c9
MC		 5247 u16 flags = reg_tbl[i].flags;
5248
5249 if (is_5709 && (flags & BNX2_FL_NOT_5709))
5250 continue;
b6016b76
MC		 5251
5252 offset = (u32) reg_tbl[i].offset;
5253 rw_mask = reg_tbl[i].rw_mask;
5254 ro_mask = reg_tbl[i].ro_mask;
5255
14ab9b86 5256 save_val = readl(bp->regview + offset);
b6016b76 5257
14ab9b86 5258 writel(0, bp->regview + offset);
b6016b76 5259
14ab9b86 5260 val = readl(bp->regview + offset);
b6016b76
MC		 5261 if ((val & rw_mask) != 0) {
5262 goto reg_test_err;
5263 }
5264
5265 if ((val & ro_mask) != (save_val & ro_mask)) {
5266 goto reg_test_err;
5267 }
5268
14ab9b86 5269 writel(0xffffffff, bp->regview + offset);
b6016b76 5270
14ab9b86 5271 val = readl(bp->regview + offset);
b6016b76
MC		 5272 if ((val & rw_mask) != rw_mask) {
5273 goto reg_test_err;
5274 }
5275
5276 if ((val & ro_mask) != (save_val & ro_mask)) {
5277 goto reg_test_err;
5278 }
5279
14ab9b86 5280 writel(save_val, bp->regview + offset);
b6016b76
MC		 5281 continue;
5282
5283reg_test_err:
14ab9b86 5284 writel(save_val, bp->regview + offset);
b6016b76
MC		 5285 ret = -ENODEV;
5286 break;
5287 }
5288 return ret;
5289}
5290
5291static int
5292bnx2_do_mem_test(struct bnx2 *bp, u32 start, u32 size)
5293{
f71e1309 5294 static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0x55555555,
b6016b76
MC		 5295 0xaaaaaaaa , 0xaa55aa55, 0x55aa55aa };
5296 int i;
5297
5298 for (i = 0; i < sizeof(test_pattern) / 4; i++) {
5299 u32 offset;
5300
5301 for (offset = 0; offset < size; offset += 4) {
5302
2726d6e1 5303 bnx2_reg_wr_ind(bp, start + offset, test_pattern[i]);
b6016b76 5304
2726d6e1 5305 if (bnx2_reg_rd_ind(bp, start + offset) !=
b6016b76
MC		 5306 test_pattern[i]) {
5307 return -ENODEV;
5308 }
5309 }
5310 }
5311 return 0;
5312}
5313
5314static int
5315bnx2_test_memory(struct bnx2 *bp)
5316{
5317 int ret = 0;
5318 int i;
5bae30c9 5319 static struct mem_entry {
b6016b76
MC		 5320 u32 offset;
5321 u32 len;
5bae30c9 5322 } mem_tbl_5706[] = {
b6016b76 5323 { 0x60000, 0x4000 },
5b0c76ad 5324 { 0xa0000, 0x3000 },
b6016b76
MC		 5325 { 0xe0000, 0x4000 },
5326 { 0x120000, 0x4000 },
5327 { 0x1a0000, 0x4000 },
5328 { 0x160000, 0x4000 },
5329 { 0xffffffff, 0 },
5bae30c9
MC		 5330 },
5331 mem_tbl_5709[] = {
5332 { 0x60000, 0x4000 },
5333 { 0xa0000, 0x3000 },
5334 { 0xe0000, 0x4000 },
5335 { 0x120000, 0x4000 },
5336 { 0x1a0000, 0x4000 },
5337 { 0xffffffff, 0 },
b6016b76 5338 };
5bae30c9
MC		 5339 struct mem_entry *mem_tbl;
5340
5341 if (CHIP_NUM(bp) == CHIP_NUM_5709)
5342 mem_tbl = mem_tbl_5709;
5343 else
5344 mem_tbl = mem_tbl_5706;
b6016b76
MC		 5345
5346 for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
5347 if ((ret = bnx2_do_mem_test(bp, mem_tbl[i].offset,
5348 mem_tbl[i].len)) != 0) {
5349 return ret;
5350 }
5351 }
6aa20a22 5352
b6016b76
MC		 5353 return ret;
5354}
5355
bc5a0690
MC		 5356#define BNX2_MAC_LOOPBACK 0
5357#define BNX2_PHY_LOOPBACK 1
5358
b6016b76 5359static int
bc5a0690 5360bnx2_run_loopback(struct bnx2 *bp, int loopback_mode)
b6016b76
MC		 5361{
5362 unsigned int pkt_size, num_pkts, i;
5363 struct sk_buff *skb, *rx_skb;
5364 unsigned char *packet;
bc5a0690 5365 u16 rx_start_idx, rx_idx;
b6016b76
MC		 5366 dma_addr_t map;
5367 struct tx_bd *txbd;
5368 struct sw_bd *rx_buf;
5369 struct l2_fhdr *rx_hdr;
5370 int ret = -ENODEV;
c76c0475 5371 struct bnx2_napi *bnapi = &bp->bnx2_napi[0], *tx_napi;
35e9010b 5372 struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
bb4f98ab 5373 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
c76c0475
MC		 5374
5375 tx_napi = bnapi;
b6016b76 5376
35e9010b 5377 txr = &tx_napi->tx_ring;
bb4f98ab 5378 rxr = &bnapi->rx_ring;
bc5a0690
MC		 5379 if (loopback_mode == BNX2_MAC_LOOPBACK) {
5380 bp->loopback = MAC_LOOPBACK;
5381 bnx2_set_mac_loopback(bp);
5382 }
5383 else if (loopback_mode == BNX2_PHY_LOOPBACK) {
583c28e5 5384 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
489310a4
MC		 5385 return 0;
5386
80be4434 5387 bp->loopback = PHY_LOOPBACK;
bc5a0690
MC		 5388 bnx2_set_phy_loopback(bp);
5389 }
5390 else
5391 return -EINVAL;
b6016b76 5392
84eaa187 5393 pkt_size = min(bp->dev->mtu + ETH_HLEN, bp->rx_jumbo_thresh - 4);
932f3772 5394 skb = netdev_alloc_skb(bp->dev, pkt_size);
b6cbc3b6
JL		 5395 if (!skb)
5396 return -ENOMEM;
b6016b76 5397 packet = skb_put(skb, pkt_size);
6634292b 5398 memcpy(packet, bp->dev->dev_addr, 6);
b6016b76
MC		 5399 memset(packet + 6, 0x0, 8);
5400 for (i = 14; i < pkt_size; i++)
5401 packet[i] = (unsigned char) (i & 0xff);
5402
3d16af86
BL		 5403 if (skb_dma_map(&bp->pdev->dev, skb, DMA_TO_DEVICE)) {
5404 dev_kfree_skb(skb);
5405 return -EIO;
5406 }
5407 map = skb_shinfo(skb)->dma_maps[0];
b6016b76 5408
bf5295bb
MC		 5409 REG_WR(bp, BNX2_HC_COMMAND,
5410 bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
5411
b6016b76
MC		 5412 REG_RD(bp, BNX2_HC_COMMAND);
5413
5414 udelay(5);
35efa7c1 5415 rx_start_idx = bnx2_get_hw_rx_cons(bnapi);
b6016b76 5416
b6016b76
MC		 5417 num_pkts = 0;
5418
35e9010b 5419 txbd = &txr->tx_desc_ring[TX_RING_IDX(txr->tx_prod)];
b6016b76
MC		 5420
5421 txbd->tx_bd_haddr_hi = (u64) map >> 32;
5422 txbd->tx_bd_haddr_lo = (u64) map & 0xffffffff;
5423 txbd->tx_bd_mss_nbytes = pkt_size;
5424 txbd->tx_bd_vlan_tag_flags = TX_BD_FLAGS_START | TX_BD_FLAGS_END;
5425
5426 num_pkts++;
35e9010b
MC		 5427 txr->tx_prod = NEXT_TX_BD(txr->tx_prod);
5428 txr->tx_prod_bseq += pkt_size;
b6016b76 5429
35e9010b
MC		 5430 REG_WR16(bp, txr->tx_bidx_addr, txr->tx_prod);
5431 REG_WR(bp, txr->tx_bseq_addr, txr->tx_prod_bseq);
b6016b76
MC		 5432
5433 udelay(100);
5434
bf5295bb
MC		 5435 REG_WR(bp, BNX2_HC_COMMAND,
5436 bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
5437
b6016b76
MC		 5438 REG_RD(bp, BNX2_HC_COMMAND);
5439
5440 udelay(5);
5441
3d16af86 5442 skb_dma_unmap(&bp->pdev->dev, skb, DMA_TO_DEVICE);
745720e5 5443 dev_kfree_skb(skb);
b6016b76 5444
35e9010b 5445 if (bnx2_get_hw_tx_cons(tx_napi) != txr->tx_prod)
b6016b76 5446 goto loopback_test_done;
b6016b76 5447
35efa7c1 5448 rx_idx = bnx2_get_hw_rx_cons(bnapi);
b6016b76
MC		 5449 if (rx_idx != rx_start_idx + num_pkts) {
5450 goto loopback_test_done;
5451 }
5452
bb4f98ab 5453 rx_buf = &rxr->rx_buf_ring[rx_start_idx];
b6016b76
MC		 5454 rx_skb = rx_buf->skb;
5455
5456 rx_hdr = (struct l2_fhdr *) rx_skb->data;
d89cb6af 5457 skb_reserve(rx_skb, BNX2_RX_OFFSET);
b6016b76
MC		 5458
5459 pci_dma_sync_single_for_cpu(bp->pdev,
5460 pci_unmap_addr(rx_buf, mapping),
5461 bp->rx_buf_size, PCI_DMA_FROMDEVICE);
5462
ade2bfe7 5463 if (rx_hdr->l2_fhdr_status &
b6016b76
MC		 5464 (L2_FHDR_ERRORS_BAD_CRC |
5465 L2_FHDR_ERRORS_PHY_DECODE |
5466 L2_FHDR_ERRORS_ALIGNMENT |
5467 L2_FHDR_ERRORS_TOO_SHORT |
5468 L2_FHDR_ERRORS_GIANT_FRAME)) {
5469
5470 goto loopback_test_done;
5471 }
5472
5473 if ((rx_hdr->l2_fhdr_pkt_len - 4) != pkt_size) {
5474 goto loopback_test_done;
5475 }
5476
5477 for (i = 14; i < pkt_size; i++) {
5478 if (*(rx_skb->data + i) != (unsigned char) (i & 0xff)) {
5479 goto loopback_test_done;
5480 }
5481 }
5482
5483 ret = 0;
5484
5485loopback_test_done:
5486 bp->loopback = 0;
5487 return ret;
5488}
5489
bc5a0690
MC		 5490#define BNX2_MAC_LOOPBACK_FAILED 1
5491#define BNX2_PHY_LOOPBACK_FAILED 2
5492#define BNX2_LOOPBACK_FAILED (BNX2_MAC_LOOPBACK_FAILED | \
5493 BNX2_PHY_LOOPBACK_FAILED)
5494
5495static int
5496bnx2_test_loopback(struct bnx2 *bp)
5497{
5498 int rc = 0;
5499
5500 if (!netif_running(bp->dev))
5501 return BNX2_LOOPBACK_FAILED;
5502
5503 bnx2_reset_nic(bp, BNX2_DRV_MSG_CODE_RESET);
5504 spin_lock_bh(&bp->phy_lock);
9a120bc5 5505 bnx2_init_phy(bp, 1);
bc5a0690
MC		 5506 spin_unlock_bh(&bp->phy_lock);
5507 if (bnx2_run_loopback(bp, BNX2_MAC_LOOPBACK))
5508 rc |= BNX2_MAC_LOOPBACK_FAILED;
5509 if (bnx2_run_loopback(bp, BNX2_PHY_LOOPBACK))
5510 rc |= BNX2_PHY_LOOPBACK_FAILED;
5511 return rc;
5512}
5513
b6016b76
MC		 5514#define NVRAM_SIZE 0x200
5515#define CRC32_RESIDUAL 0xdebb20e3
5516
5517static int
5518bnx2_test_nvram(struct bnx2 *bp)
5519{
b491edd5 5520 __be32 buf[NVRAM_SIZE / 4];
b6016b76
MC		 5521 u8 *data = (u8 *) buf;
5522 int rc = 0;
5523 u32 magic, csum;
5524
5525 if ((rc = bnx2_nvram_read(bp, 0, data, 4)) != 0)
5526 goto test_nvram_done;
5527
5528 magic = be32_to_cpu(buf[0]);
5529 if (magic != 0x669955aa) {
5530 rc = -ENODEV;
5531 goto test_nvram_done;
5532 }
5533
5534 if ((rc = bnx2_nvram_read(bp, 0x100, data, NVRAM_SIZE)) != 0)
5535 goto test_nvram_done;
5536
5537 csum = ether_crc_le(0x100, data);
5538 if (csum != CRC32_RESIDUAL) {
5539 rc = -ENODEV;
5540 goto test_nvram_done;
5541 }
5542
5543 csum = ether_crc_le(0x100, data + 0x100);
5544 if (csum != CRC32_RESIDUAL) {
5545 rc = -ENODEV;
5546 }
5547
5548test_nvram_done:
5549 return rc;
5550}
5551
5552static int
5553bnx2_test_link(struct bnx2 *bp)
5554{
5555 u32 bmsr;
5556
9f52b564
MC		 5557 if (!netif_running(bp->dev))
5558 return -ENODEV;
5559
583c28e5 5560 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) {
489310a4
MC		 5561 if (bp->link_up)
5562 return 0;
5563 return -ENODEV;
5564 }
c770a65c 5565 spin_lock_bh(&bp->phy_lock);
27a005b8
MC		 5566 bnx2_enable_bmsr1(bp);
5567 bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr);
5568 bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr);
5569 bnx2_disable_bmsr1(bp);
c770a65c 5570 spin_unlock_bh(&bp->phy_lock);
6aa20a22 5571
b6016b76
MC		 5572 if (bmsr & BMSR_LSTATUS) {
5573 return 0;
5574 }
5575 return -ENODEV;
5576}
5577
5578static int
5579bnx2_test_intr(struct bnx2 *bp)
5580{
5581 int i;
b6016b76
MC		 5582 u16 status_idx;
5583
5584 if (!netif_running(bp->dev))
5585 return -ENODEV;
5586
5587 status_idx = REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD) & 0xffff;
5588
5589 /* This register is not touched during run-time. */
bf5295bb 5590 REG_WR(bp, BNX2_HC_COMMAND, bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW);
b6016b76
MC		 5591 REG_RD(bp, BNX2_HC_COMMAND);
5592
5593 for (i = 0; i < 10; i++) {
5594 if ((REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD) & 0xffff) !=
5595 status_idx) {
5596
5597 break;
5598 }
5599
5600 msleep_interruptible(10);
5601 }
5602 if (i < 10)
5603 return 0;
5604
5605 return -ENODEV;
5606}
5607
38ea3686 5608/* Determining link for parallel detection. */
b2fadeae
MC		 5609static int
5610bnx2_5706_serdes_has_link(struct bnx2 *bp)
5611{
5612 u32 mode_ctl, an_dbg, exp;
5613
38ea3686
MC		 5614 if (bp->phy_flags & BNX2_PHY_FLAG_NO_PARALLEL)
5615 return 0;
5616
b2fadeae
MC		 5617 bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_MODE_CTL);
5618 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &mode_ctl);
5619
5620 if (!(mode_ctl & MISC_SHDW_MODE_CTL_SIG_DET))
5621 return 0;
5622
5623 bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_AN_DBG);
5624 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &an_dbg);
5625 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &an_dbg);
5626
f3014c0c 5627 if (an_dbg & (MISC_SHDW_AN_DBG_NOSYNC | MISC_SHDW_AN_DBG_RUDI_INVALID))
b2fadeae
MC		 5628 return 0;
5629
5630 bnx2_write_phy(bp, MII_BNX2_DSP_ADDRESS, MII_EXPAND_REG1);
5631 bnx2_read_phy(bp, MII_BNX2_DSP_RW_PORT, &exp);
5632 bnx2_read_phy(bp, MII_BNX2_DSP_RW_PORT, &exp);
5633
5634 if (exp & MII_EXPAND_REG1_RUDI_C) /* receiving CONFIG */
5635 return 0;
5636
5637 return 1;
5638}
5639
b6016b76 5640static void
48b01e2d 5641bnx2_5706_serdes_timer(struct bnx2 *bp)
b6016b76 5642{
b2fadeae
MC		 5643 int check_link = 1;
5644
48b01e2d 5645 spin_lock(&bp->phy_lock);
b2fadeae 5646 if (bp->serdes_an_pending) {
48b01e2d 5647 bp->serdes_an_pending--;
b2fadeae
MC		 5648 check_link = 0;
5649 } else if ((bp->link_up == 0) && (bp->autoneg & AUTONEG_SPEED)) {
48b01e2d 5650 u32 bmcr;
b6016b76 5651
ac392abc 5652 bp->current_interval = BNX2_TIMER_INTERVAL;
cd339a0e 5653
ca58c3af 5654 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
b6016b76 5655
48b01e2d 5656 if (bmcr & BMCR_ANENABLE) {
b2fadeae 5657 if (bnx2_5706_serdes_has_link(bp)) {
48b01e2d
MC		 5658 bmcr &= ~BMCR_ANENABLE;
5659 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
ca58c3af 5660 bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
583c28e5 5661 bp->phy_flags |= BNX2_PHY_FLAG_PARALLEL_DETECT;
48b01e2d 5662 }
b6016b76 5663 }
48b01e2d
MC		 5664 }
5665 else if ((bp->link_up) && (bp->autoneg & AUTONEG_SPEED) &&
583c28e5 5666 (bp->phy_flags & BNX2_PHY_FLAG_PARALLEL_DETECT)) {
48b01e2d 5667 u32 phy2;
b6016b76 5668
48b01e2d
MC		 5669 bnx2_write_phy(bp, 0x17, 0x0f01);
5670 bnx2_read_phy(bp, 0x15, &phy2);
5671 if (phy2 & 0x20) {
5672 u32 bmcr;
cd339a0e 5673
ca58c3af 5674 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
48b01e2d 5675 bmcr |= BMCR_ANENABLE;
ca58c3af 5676 bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
b6016b76 5677
583c28e5 5678 bp->phy_flags &= ~BNX2_PHY_FLAG_PARALLEL_DETECT;
48b01e2d
MC		 5679 }
5680 } else
ac392abc 5681 bp->current_interval = BNX2_TIMER_INTERVAL;
b6016b76 5682
a2724e25 5683 if (check_link) {
b2fadeae
MC		 5684 u32 val;
5685
5686 bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_AN_DBG);
5687 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &val);
5688 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &val);
5689
a2724e25
MC		 5690 if (bp->link_up && (val & MISC_SHDW_AN_DBG_NOSYNC)) {
5691 if (!(bp->phy_flags & BNX2_PHY_FLAG_FORCED_DOWN)) {
5692 bnx2_5706s_force_link_dn(bp, 1);
5693 bp->phy_flags |= BNX2_PHY_FLAG_FORCED_DOWN;
5694 } else
5695 bnx2_set_link(bp);
5696 } else if (!bp->link_up && !(val & MISC_SHDW_AN_DBG_NOSYNC))
5697 bnx2_set_link(bp);
b2fadeae 5698 }
48b01e2d
MC		 5699 spin_unlock(&bp->phy_lock);
5700}
b6016b76 5701
f8dd064e
MC		 5702static void
5703bnx2_5708_serdes_timer(struct bnx2 *bp)
5704{
583c28e5 5705 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
0d8a6571
MC		 5706 return;
5707
583c28e5 5708 if ((bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE) == 0) {
f8dd064e
MC		 5709 bp->serdes_an_pending = 0;
5710 return;
5711 }
b6016b76 5712
f8dd064e
MC		 5713 spin_lock(&bp->phy_lock);
5714 if (bp->serdes_an_pending)
5715 bp->serdes_an_pending--;
5716 else if ((bp->link_up == 0) && (bp->autoneg & AUTONEG_SPEED)) {
5717 u32 bmcr;
b6016b76 5718
ca58c3af 5719 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
f8dd064e 5720 if (bmcr & BMCR_ANENABLE) {
605a9e20 5721 bnx2_enable_forced_2g5(bp);
f8dd064e
MC		 5722 bp->current_interval = SERDES_FORCED_TIMEOUT;
5723 } else {
605a9e20 5724 bnx2_disable_forced_2g5(bp);
f8dd064e 5725 bp->serdes_an_pending = 2;
ac392abc 5726 bp->current_interval = BNX2_TIMER_INTERVAL;
b6016b76 5727 }
b6016b76 5728
f8dd064e 5729 } else
ac392abc 5730 bp->current_interval = BNX2_TIMER_INTERVAL;
b6016b76 5731
f8dd064e
MC		 5732 spin_unlock(&bp->phy_lock);
5733}
5734
48b01e2d
MC		 5735static void
5736bnx2_timer(unsigned long data)
5737{
5738 struct bnx2 *bp = (struct bnx2 *) data;
b6016b76 5739
48b01e2d
MC		 5740 if (!netif_running(bp->dev))
5741 return;
b6016b76 5742
48b01e2d
MC		 5743 if (atomic_read(&bp->intr_sem) != 0)
5744 goto bnx2_restart_timer;
b6016b76 5745
efba0180
MC		 5746 if ((bp->flags & (BNX2_FLAG_USING_MSI | BNX2_FLAG_ONE_SHOT_MSI)) ==
5747 BNX2_FLAG_USING_MSI)
5748 bnx2_chk_missed_msi(bp);
5749
df149d70 5750 bnx2_send_heart_beat(bp);
b6016b76 5751
2726d6e1
MC		 5752 bp->stats_blk->stat_FwRxDrop =
5753 bnx2_reg_rd_ind(bp, BNX2_FW_RX_DROP_COUNT);
b6016b76 5754
02537b06
MC		 5755 /* workaround occasional corrupted counters */
5756 if (CHIP_NUM(bp) == CHIP_NUM_5708 && bp->stats_ticks)
5757 REG_WR(bp, BNX2_HC_COMMAND, bp->hc_cmd |
5758 BNX2_HC_COMMAND_STATS_NOW);
5759
583c28e5 5760 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
f8dd064e
MC		 5761 if (CHIP_NUM(bp) == CHIP_NUM_5706)
5762 bnx2_5706_serdes_timer(bp);
27a005b8 5763 else
f8dd064e 5764 bnx2_5708_serdes_timer(bp);
b6016b76
MC		 5765 }
5766
5767bnx2_restart_timer:
cd339a0e 5768 mod_timer(&bp->timer, jiffies + bp->current_interval);
b6016b76
MC		 5769}
5770
8e6a72c4
MC		 5771static int
5772bnx2_request_irq(struct bnx2 *bp)
5773{
6d866ffc 5774 unsigned long flags;
b4b36042
MC		 5775 struct bnx2_irq *irq;
5776 int rc = 0, i;
8e6a72c4 5777
f86e82fb 5778 if (bp->flags & BNX2_FLAG_USING_MSI_OR_MSIX)
6d866ffc
MC		 5779 flags = 0;
5780 else
5781 flags = IRQF_SHARED;
b4b36042
MC		 5782
5783 for (i = 0; i < bp->irq_nvecs; i++) {
5784 irq = &bp->irq_tbl[i];
c76c0475 5785 rc = request_irq(irq->vector, irq->handler, flags, irq->name,
f0ea2e63 5786 &bp->bnx2_napi[i]);
b4b36042
MC		 5787 if (rc)
5788 break;
5789 irq->requested = 1;
5790 }
8e6a72c4
MC		 5791 return rc;
5792}
5793
5794static void
5795bnx2_free_irq(struct bnx2 *bp)
5796{
b4b36042
MC		 5797 struct bnx2_irq *irq;
5798 int i;
8e6a72c4 5799
b4b36042
MC		 5800 for (i = 0; i < bp->irq_nvecs; i++) {
5801 irq = &bp->irq_tbl[i];
5802 if (irq->requested)
f0ea2e63 5803 free_irq(irq->vector, &bp->bnx2_napi[i]);
b4b36042 5804 irq->requested = 0;
6d866ffc 5805 }
f86e82fb 5806 if (bp->flags & BNX2_FLAG_USING_MSI)
b4b36042 5807 pci_disable_msi(bp->pdev);
f86e82fb 5808 else if (bp->flags & BNX2_FLAG_USING_MSIX)
b4b36042
MC		 5809 pci_disable_msix(bp->pdev);
5810
f86e82fb 5811 bp->flags &= ~(BNX2_FLAG_USING_MSI_OR_MSIX | BNX2_FLAG_ONE_SHOT_MSI);
b4b36042
MC		 5812}
5813
5814static void
5e9ad9e1 5815bnx2_enable_msix(struct bnx2 *bp, int msix_vecs)
b4b36042 5816{
57851d84
MC		 5817 int i, rc;
5818 struct msix_entry msix_ent[BNX2_MAX_MSIX_VEC];
5819
b4b36042
MC		 5820 bnx2_setup_msix_tbl(bp);
5821 REG_WR(bp, BNX2_PCI_MSIX_CONTROL, BNX2_MAX_MSIX_HW_VEC - 1);
5822 REG_WR(bp, BNX2_PCI_MSIX_TBL_OFF_BIR, BNX2_PCI_GRC_WINDOW2_BASE);
5823 REG_WR(bp, BNX2_PCI_MSIX_PBA_OFF_BIT, BNX2_PCI_GRC_WINDOW3_BASE);
57851d84
MC		 5824
5825 for (i = 0; i < BNX2_MAX_MSIX_VEC; i++) {
5826 msix_ent[i].entry = i;
5827 msix_ent[i].vector = 0;
35e9010b
MC		 5828
5829 strcpy(bp->irq_tbl[i].name, bp->dev->name);
f0ea2e63 5830 bp->irq_tbl[i].handler = bnx2_msi_1shot;
57851d84
MC		 5831 }
5832
5833 rc = pci_enable_msix(bp->pdev, msix_ent, BNX2_MAX_MSIX_VEC);
5834 if (rc != 0)
5835 return;
5836
5e9ad9e1 5837 bp->irq_nvecs = msix_vecs;
f86e82fb 5838 bp->flags |= BNX2_FLAG_USING_MSIX | BNX2_FLAG_ONE_SHOT_MSI;
57851d84
MC		 5839 for (i = 0; i < BNX2_MAX_MSIX_VEC; i++)
5840 bp->irq_tbl[i].vector = msix_ent[i].vector;
6d866ffc
MC		 5841}
5842
5843static void
5844bnx2_setup_int_mode(struct bnx2 *bp, int dis_msi)
5845{
5e9ad9e1 5846 int cpus = num_online_cpus();
706bf240 5847 int msix_vecs = min(cpus + 1, RX_MAX_RINGS);
5e9ad9e1 5848
6d866ffc
MC		 5849 bp->irq_tbl[0].handler = bnx2_interrupt;
5850 strcpy(bp->irq_tbl[0].name, bp->dev->name);
b4b36042
MC		 5851 bp->irq_nvecs = 1;
5852 bp->irq_tbl[0].vector = bp->pdev->irq;
5853
5e9ad9e1
MC		 5854 if ((bp->flags & BNX2_FLAG_MSIX_CAP) && !dis_msi && cpus > 1)
5855 bnx2_enable_msix(bp, msix_vecs);
6d866ffc 5856
f86e82fb
DM		 5857 if ((bp->flags & BNX2_FLAG_MSI_CAP) && !dis_msi &&
5858 !(bp->flags & BNX2_FLAG_USING_MSIX)) {
6d866ffc 5859 if (pci_enable_msi(bp->pdev) == 0) {
f86e82fb 5860 bp->flags |= BNX2_FLAG_USING_MSI;
6d866ffc 5861 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
f86e82fb 5862 bp->flags |= BNX2_FLAG_ONE_SHOT_MSI;
6d866ffc
MC		 5863 bp->irq_tbl[0].handler = bnx2_msi_1shot;
5864 } else
5865 bp->irq_tbl[0].handler = bnx2_msi;
b4b36042
MC		 5866
5867 bp->irq_tbl[0].vector = bp->pdev->irq;
6d866ffc
MC		 5868 }
5869 }
706bf240
BL		 5870
5871 bp->num_tx_rings = rounddown_pow_of_two(bp->irq_nvecs);
5872 bp->dev->real_num_tx_queues = bp->num_tx_rings;
5873
5e9ad9e1 5874 bp->num_rx_rings = bp->irq_nvecs;
8e6a72c4
MC		 5875}
5876
b6016b76
MC		 5877/* Called with rtnl_lock */
5878static int
5879bnx2_open(struct net_device *dev)
5880{
972ec0d4 5881 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 5882 int rc;
5883
1b2f922f
MC		 5884 netif_carrier_off(dev);
5885
829ca9a3 5886 bnx2_set_power_state(bp, PCI_D0);
b6016b76
MC		 5887 bnx2_disable_int(bp);
5888
35e9010b
MC		 5889 bnx2_setup_int_mode(bp, disable_msi);
5890 bnx2_napi_enable(bp);
b6016b76 5891 rc = bnx2_alloc_mem(bp);
2739a8bb
MC		 5892 if (rc)
5893 goto open_err;
b6016b76 5894
8e6a72c4 5895 rc = bnx2_request_irq(bp);
2739a8bb
MC		 5896 if (rc)
5897 goto open_err;
b6016b76 5898
9a120bc5 5899 rc = bnx2_init_nic(bp, 1);
2739a8bb
MC		 5900 if (rc)
5901 goto open_err;
6aa20a22 5902
cd339a0e 5903 mod_timer(&bp->timer, jiffies + bp->current_interval);
b6016b76
MC		 5904
5905 atomic_set(&bp->intr_sem, 0);
5906
5907 bnx2_enable_int(bp);
5908
f86e82fb 5909 if (bp->flags & BNX2_FLAG_USING_MSI) {
b6016b76
MC		 5910 /* Test MSI to make sure it is working
5911 * If MSI test fails, go back to INTx mode
5912 */
5913 if (bnx2_test_intr(bp) != 0) {
5914 printk(KERN_WARNING PFX "%s: No interrupt was generated"
5915 " using MSI, switching to INTx mode. Please"
5916 " report this failure to the PCI maintainer"
5917 " and include system chipset information.\n",
5918 bp->dev->name);
5919
5920 bnx2_disable_int(bp);
8e6a72c4 5921 bnx2_free_irq(bp);
b6016b76 5922
6d866ffc
MC		 5923 bnx2_setup_int_mode(bp, 1);
5924
9a120bc5 5925 rc = bnx2_init_nic(bp, 0);
b6016b76 5926
8e6a72c4
MC		 5927 if (!rc)
5928 rc = bnx2_request_irq(bp);
5929
b6016b76 5930 if (rc) {
b6016b76 5931 del_timer_sync(&bp->timer);
2739a8bb 5932 goto open_err;
b6016b76
MC		 5933 }
5934 bnx2_enable_int(bp);
5935 }
5936 }
f86e82fb 5937 if (bp->flags & BNX2_FLAG_USING_MSI)
b6016b76 5938 printk(KERN_INFO PFX "%s: using MSI\n", dev->name);
f86e82fb 5939 else if (bp->flags & BNX2_FLAG_USING_MSIX)
57851d84 5940 printk(KERN_INFO PFX "%s: using MSIX\n", dev->name);
b6016b76 5941
706bf240 5942 netif_tx_start_all_queues(dev);
b6016b76
MC		 5943
5944 return 0;
2739a8bb
MC		 5945
5946open_err:
5947 bnx2_napi_disable(bp);
5948 bnx2_free_skbs(bp);
5949 bnx2_free_irq(bp);
5950 bnx2_free_mem(bp);
5951 return rc;
b6016b76
MC		 5952}
5953
5954static void
c4028958 5955bnx2_reset_task(struct work_struct *work)
b6016b76 5956{
c4028958 5957 struct bnx2 *bp = container_of(work, struct bnx2, reset_task);
b6016b76 5958
afdc08b9
MC		 5959 if (!netif_running(bp->dev))
5960 return;
5961
b6016b76
MC		 5962 bnx2_netif_stop(bp);
5963
9a120bc5 5964 bnx2_init_nic(bp, 1);
b6016b76
MC		 5965
5966 atomic_set(&bp->intr_sem, 1);
5967 bnx2_netif_start(bp);
5968}
5969
5970static void
5971bnx2_tx_timeout(struct net_device *dev)
5972{
972ec0d4 5973 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 5974
5975 /* This allows the netif to be shutdown gracefully before resetting */
5976 schedule_work(&bp->reset_task);
5977}
5978
5979#ifdef BCM_VLAN
5980/* Called with rtnl_lock */
5981static void
5982bnx2_vlan_rx_register(struct net_device *dev, struct vlan_group *vlgrp)
5983{
972ec0d4 5984 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 5985
5986 bnx2_netif_stop(bp);
5987
5988 bp->vlgrp = vlgrp;
5989 bnx2_set_rx_mode(dev);
7c62e83b
MC		 5990 if (bp->flags & BNX2_FLAG_CAN_KEEP_VLAN)
5991 bnx2_fw_sync(bp, BNX2_DRV_MSG_CODE_KEEP_VLAN_UPDATE, 0, 1);
b6016b76
MC		 5992
5993 bnx2_netif_start(bp);
5994}
b6016b76
MC		 5995#endif
5996
932ff279 5997/* Called with netif_tx_lock.
2f8af120
MC		 5998 * bnx2_tx_int() runs without netif_tx_lock unless it needs to call
5999 * netif_wake_queue().
b6016b76
MC		 6000 */
6001static int
6002bnx2_start_xmit(struct sk_buff *skb, struct net_device *dev)
6003{
972ec0d4 6004 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 6005 dma_addr_t mapping;
6006 struct tx_bd *txbd;
3d16af86 6007 struct sw_tx_bd *tx_buf;
b6016b76
MC		 6008 u32 len, vlan_tag_flags, last_frag, mss;
6009 u16 prod, ring_prod;
6010 int i;
706bf240
BL		 6011 struct bnx2_napi *bnapi;
6012 struct bnx2_tx_ring_info *txr;
6013 struct netdev_queue *txq;
3d16af86 6014 struct skb_shared_info *sp;
706bf240
BL		 6015
6016 /* Determine which tx ring we will be placed on */
6017 i = skb_get_queue_mapping(skb);
6018 bnapi = &bp->bnx2_napi[i];
6019 txr = &bnapi->tx_ring;
6020 txq = netdev_get_tx_queue(dev, i);
b6016b76 6021
35e9010b 6022 if (unlikely(bnx2_tx_avail(bp, txr) <
a550c99b 6023 (skb_shinfo(skb)->nr_frags + 1))) {
706bf240 6024 netif_tx_stop_queue(txq);
b6016b76
MC		 6025 printk(KERN_ERR PFX "%s: BUG! Tx ring full when queue awake!\n",
6026 dev->name);
6027
6028 return NETDEV_TX_BUSY;
6029 }
6030 len = skb_headlen(skb);
35e9010b 6031 prod = txr->tx_prod;
b6016b76
MC		 6032 ring_prod = TX_RING_IDX(prod);
6033
6034 vlan_tag_flags = 0;
84fa7933 6035 if (skb->ip_summed == CHECKSUM_PARTIAL) {
b6016b76
MC		 6036 vlan_tag_flags |= TX_BD_FLAGS_TCP_UDP_CKSUM;
6037 }
6038
729b85cd 6039#ifdef BCM_VLAN
79ea13ce 6040 if (bp->vlgrp && vlan_tx_tag_present(skb)) {
b6016b76
MC		 6041 vlan_tag_flags |=
6042 (TX_BD_FLAGS_VLAN_TAG | (vlan_tx_tag_get(skb) << 16));
6043 }
729b85cd 6044#endif
fde82055 6045 if ((mss = skb_shinfo(skb)->gso_size)) {
a1efb4b6 6046 u32 tcp_opt_len;
eddc9ec5 6047 struct iphdr *iph;
b6016b76 6048
b6016b76
MC		 6049 vlan_tag_flags |= TX_BD_FLAGS_SW_LSO;
6050
4666f87a
MC		 6051 tcp_opt_len = tcp_optlen(skb);
6052
6053 if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6) {
6054 u32 tcp_off = skb_transport_offset(skb) -
6055 sizeof(struct ipv6hdr) - ETH_HLEN;
ab6a5bb6 6056
4666f87a
MC		 6057 vlan_tag_flags |= ((tcp_opt_len >> 2) << 8) |
6058 TX_BD_FLAGS_SW_FLAGS;
6059 if (likely(tcp_off == 0))
6060 vlan_tag_flags &= ~TX_BD_FLAGS_TCP6_OFF0_MSK;
6061 else {
6062 tcp_off >>= 3;
6063 vlan_tag_flags |= ((tcp_off & 0x3) <<
6064 TX_BD_FLAGS_TCP6_OFF0_SHL) |
6065 ((tcp_off & 0x10) <<
6066 TX_BD_FLAGS_TCP6_OFF4_SHL);
6067 mss |= (tcp_off & 0xc) << TX_BD_TCP6_OFF2_SHL;
6068 }
6069 } else {
4666f87a 6070 iph = ip_hdr(skb);
4666f87a
MC		 6071 if (tcp_opt_len || (iph->ihl > 5)) {
6072 vlan_tag_flags |= ((iph->ihl - 5) +
6073 (tcp_opt_len >> 2)) << 8;
6074 }
b6016b76 6075 }
4666f87a 6076 } else
b6016b76 6077 mss = 0;
b6016b76 6078
3d16af86
BL		 6079 if (skb_dma_map(&bp->pdev->dev, skb, DMA_TO_DEVICE)) {
6080 dev_kfree_skb(skb);
6081 return NETDEV_TX_OK;
6082 }
6083
6084 sp = skb_shinfo(skb);
6085 mapping = sp->dma_maps[0];
6aa20a22 6086
35e9010b 6087 tx_buf = &txr->tx_buf_ring[ring_prod];
b6016b76 6088 tx_buf->skb = skb;
b6016b76 6089
35e9010b 6090 txbd = &txr->tx_desc_ring[ring_prod];
b6016b76
MC		 6091
6092 txbd->tx_bd_haddr_hi = (u64) mapping >> 32;
6093 txbd->tx_bd_haddr_lo = (u64) mapping & 0xffffffff;
6094 txbd->tx_bd_mss_nbytes = len | (mss << 16);
6095 txbd->tx_bd_vlan_tag_flags = vlan_tag_flags | TX_BD_FLAGS_START;
6096
6097 last_frag = skb_shinfo(skb)->nr_frags;
6098
6099 for (i = 0; i < last_frag; i++) {
6100 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
6101
6102 prod = NEXT_TX_BD(prod);
6103 ring_prod = TX_RING_IDX(prod);
35e9010b 6104 txbd = &txr->tx_desc_ring[ring_prod];
b6016b76
MC		 6105
6106 len = frag->size;
3d16af86 6107 mapping = sp->dma_maps[i + 1];
b6016b76
MC		 6108
6109 txbd->tx_bd_haddr_hi = (u64) mapping >> 32;
6110 txbd->tx_bd_haddr_lo = (u64) mapping & 0xffffffff;
6111 txbd->tx_bd_mss_nbytes = len | (mss << 16);
6112 txbd->tx_bd_vlan_tag_flags = vlan_tag_flags;
6113
6114 }
6115 txbd->tx_bd_vlan_tag_flags |= TX_BD_FLAGS_END;
6116
6117 prod = NEXT_TX_BD(prod);
35e9010b 6118 txr->tx_prod_bseq += skb->len;
b6016b76 6119
35e9010b
MC		 6120 REG_WR16(bp, txr->tx_bidx_addr, prod);
6121 REG_WR(bp, txr->tx_bseq_addr, txr->tx_prod_bseq);
b6016b76
MC		 6122
6123 mmiowb();
6124
35e9010b 6125 txr->tx_prod = prod;
b6016b76
MC		 6126 dev->trans_start = jiffies;
6127
35e9010b 6128 if (unlikely(bnx2_tx_avail(bp, txr) <= MAX_SKB_FRAGS)) {
706bf240 6129 netif_tx_stop_queue(txq);
35e9010b 6130 if (bnx2_tx_avail(bp, txr) > bp->tx_wake_thresh)
706bf240 6131 netif_tx_wake_queue(txq);
b6016b76
MC		 6132 }
6133
6134 return NETDEV_TX_OK;
6135}
6136
6137/* Called with rtnl_lock */
6138static int
6139bnx2_close(struct net_device *dev)
6140{
972ec0d4 6141 struct bnx2 *bp = netdev_priv(dev);
b6016b76 6142
4bb073c0 6143 cancel_work_sync(&bp->reset_task);
afdc08b9 6144
bea3348e 6145 bnx2_disable_int_sync(bp);
35efa7c1 6146 bnx2_napi_disable(bp);
b6016b76 6147 del_timer_sync(&bp->timer);
74bf4ba3 6148 bnx2_shutdown_chip(bp);
8e6a72c4 6149 bnx2_free_irq(bp);
b6016b76
MC		 6150 bnx2_free_skbs(bp);
6151 bnx2_free_mem(bp);
6152 bp->link_up = 0;
6153 netif_carrier_off(bp->dev);
829ca9a3 6154 bnx2_set_power_state(bp, PCI_D3hot);
b6016b76
MC		 6155 return 0;
6156}
6157
6158#define GET_NET_STATS64(ctr) \
6159 (unsigned long) ((unsigned long) (ctr##_hi) << 32) + \
6160 (unsigned long) (ctr##_lo)
6161
6162#define GET_NET_STATS32(ctr) \
6163 (ctr##_lo)
6164
6165#if (BITS_PER_LONG == 64)
6166#define GET_NET_STATS GET_NET_STATS64
6167#else
6168#define GET_NET_STATS GET_NET_STATS32
6169#endif
6170
6171static struct net_device_stats *
6172bnx2_get_stats(struct net_device *dev)
6173{
972ec0d4 6174 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 6175 struct statistics_block *stats_blk = bp->stats_blk;
6176 struct net_device_stats *net_stats = &bp->net_stats;
6177
6178 if (bp->stats_blk == NULL) {
6179 return net_stats;
6180 }
6181 net_stats->rx_packets =
6182 GET_NET_STATS(stats_blk->stat_IfHCInUcastPkts) +
6183 GET_NET_STATS(stats_blk->stat_IfHCInMulticastPkts) +
6184 GET_NET_STATS(stats_blk->stat_IfHCInBroadcastPkts);
6185
6186 net_stats->tx_packets =
6187 GET_NET_STATS(stats_blk->stat_IfHCOutUcastPkts) +
6188 GET_NET_STATS(stats_blk->stat_IfHCOutMulticastPkts) +
6189 GET_NET_STATS(stats_blk->stat_IfHCOutBroadcastPkts);
6190
6191 net_stats->rx_bytes =
6192 GET_NET_STATS(stats_blk->stat_IfHCInOctets);
6193
6194 net_stats->tx_bytes =
6195 GET_NET_STATS(stats_blk->stat_IfHCOutOctets);
6196
6aa20a22 6197 net_stats->multicast =
b6016b76
MC		 6198 GET_NET_STATS(stats_blk->stat_IfHCOutMulticastPkts);
6199
6aa20a22 6200 net_stats->collisions =
b6016b76
MC		 6201 (unsigned long) stats_blk->stat_EtherStatsCollisions;
6202
6aa20a22 6203 net_stats->rx_length_errors =
b6016b76
MC		 6204 (unsigned long) (stats_blk->stat_EtherStatsUndersizePkts +
6205 stats_blk->stat_EtherStatsOverrsizePkts);
6206
6aa20a22 6207 net_stats->rx_over_errors =
b6016b76
MC		 6208 (unsigned long) stats_blk->stat_IfInMBUFDiscards;
6209
6aa20a22 6210 net_stats->rx_frame_errors =
b6016b76
MC		 6211 (unsigned long) stats_blk->stat_Dot3StatsAlignmentErrors;
6212
6aa20a22 6213 net_stats->rx_crc_errors =
b6016b76
MC		 6214 (unsigned long) stats_blk->stat_Dot3StatsFCSErrors;
6215
6216 net_stats->rx_errors = net_stats->rx_length_errors +
6217 net_stats->rx_over_errors + net_stats->rx_frame_errors +
6218 net_stats->rx_crc_errors;
6219
6220 net_stats->tx_aborted_errors =
6221 (unsigned long) (stats_blk->stat_Dot3StatsExcessiveCollisions +
6222 stats_blk->stat_Dot3StatsLateCollisions);
6223
5b0c76ad
MC		 6224 if ((CHIP_NUM(bp) == CHIP_NUM_5706) ||
6225 (CHIP_ID(bp) == CHIP_ID_5708_A0))
b6016b76
MC		 6226 net_stats->tx_carrier_errors = 0;
6227 else {
6228 net_stats->tx_carrier_errors =
6229 (unsigned long)
6230 stats_blk->stat_Dot3StatsCarrierSenseErrors;
6231 }
6232
6233 net_stats->tx_errors =
6aa20a22 6234 (unsigned long)
b6016b76
MC		 6235 stats_blk->stat_emac_tx_stat_dot3statsinternalmactransmiterrors
6236 +
6237 net_stats->tx_aborted_errors +
6238 net_stats->tx_carrier_errors;
6239
cea94db9
MC		 6240 net_stats->rx_missed_errors =
6241 (unsigned long) (stats_blk->stat_IfInMBUFDiscards +
6242 stats_blk->stat_FwRxDrop);
6243
b6016b76
MC		 6244 return net_stats;
6245}
6246
6247/* All ethtool functions called with rtnl_lock */
6248
6249static int
6250bnx2_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
6251{
972ec0d4 6252 struct bnx2 *bp = netdev_priv(dev);
7b6b8347 6253 int support_serdes = 0, support_copper = 0;
b6016b76
MC		 6254
6255 cmd->supported = SUPPORTED_Autoneg;
583c28e5 6256 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) {
7b6b8347
MC		 6257 support_serdes = 1;
6258 support_copper = 1;
6259 } else if (bp->phy_port == PORT_FIBRE)
6260 support_serdes = 1;
6261 else
6262 support_copper = 1;
6263
6264 if (support_serdes) {
b6016b76
MC		 6265 cmd->supported |= SUPPORTED_1000baseT_Full |
6266 SUPPORTED_FIBRE;
583c28e5 6267 if (bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE)
605a9e20 6268 cmd->supported |= SUPPORTED_2500baseX_Full;
b6016b76 6269
b6016b76 6270 }
7b6b8347 6271 if (support_copper) {
b6016b76
MC		 6272 cmd->supported |= SUPPORTED_10baseT_Half |
6273 SUPPORTED_10baseT_Full |
6274 SUPPORTED_100baseT_Half |
6275 SUPPORTED_100baseT_Full |
6276 SUPPORTED_1000baseT_Full |
6277 SUPPORTED_TP;
6278
b6016b76
MC		 6279 }
6280
7b6b8347
MC		 6281 spin_lock_bh(&bp->phy_lock);
6282 cmd->port = bp->phy_port;
b6016b76
MC		 6283 cmd->advertising = bp->advertising;
6284
6285 if (bp->autoneg & AUTONEG_SPEED) {
6286 cmd->autoneg = AUTONEG_ENABLE;
6287 }
6288 else {
6289 cmd->autoneg = AUTONEG_DISABLE;
6290 }
6291
6292 if (netif_carrier_ok(dev)) {
6293 cmd->speed = bp->line_speed;
6294 cmd->duplex = bp->duplex;
6295 }
6296 else {
6297 cmd->speed = -1;
6298 cmd->duplex = -1;
6299 }
7b6b8347 6300 spin_unlock_bh(&bp->phy_lock);
b6016b76
MC		 6301
6302 cmd->transceiver = XCVR_INTERNAL;
6303 cmd->phy_address = bp->phy_addr;
6304
6305 return 0;
6306}
6aa20a22 6307
b6016b76
MC		 6308static int
6309bnx2_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
6310{
972ec0d4 6311 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 6312 u8 autoneg = bp->autoneg;
6313 u8 req_duplex = bp->req_duplex;
6314 u16 req_line_speed = bp->req_line_speed;
6315 u32 advertising = bp->advertising;
7b6b8347
MC		 6316 int err = -EINVAL;
6317
6318 spin_lock_bh(&bp->phy_lock);
6319
6320 if (cmd->port != PORT_TP && cmd->port != PORT_FIBRE)
6321 goto err_out_unlock;
6322
583c28e5
MC		 6323 if (cmd->port != bp->phy_port &&
6324 !(bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP))
7b6b8347 6325 goto err_out_unlock;
b6016b76 6326
d6b14486
MC		 6327 /* If device is down, we can store the settings only if the user
6328 * is setting the currently active port.
6329 */
6330 if (!netif_running(dev) && cmd->port != bp->phy_port)
6331 goto err_out_unlock;
6332
b6016b76
MC		 6333 if (cmd->autoneg == AUTONEG_ENABLE) {
6334 autoneg |= AUTONEG_SPEED;
6335
6aa20a22 6336 cmd->advertising &= ETHTOOL_ALL_COPPER_SPEED;
b6016b76
MC		 6337
6338 /* allow advertising 1 speed */
6339 if ((cmd->advertising == ADVERTISED_10baseT_Half) ||
6340 (cmd->advertising == ADVERTISED_10baseT_Full) ||
6341 (cmd->advertising == ADVERTISED_100baseT_Half) ||
6342 (cmd->advertising == ADVERTISED_100baseT_Full)) {
6343
7b6b8347
MC		 6344 if (cmd->port == PORT_FIBRE)
6345 goto err_out_unlock;
b6016b76
MC		 6346
6347 advertising = cmd->advertising;
6348
27a005b8 6349 } else if (cmd->advertising == ADVERTISED_2500baseX_Full) {
583c28e5 6350 if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE) ||
7b6b8347
MC		 6351 (cmd->port == PORT_TP))
6352 goto err_out_unlock;
6353 } else if (cmd->advertising == ADVERTISED_1000baseT_Full)
b6016b76 6354 advertising = cmd->advertising;
7b6b8347
MC		 6355 else if (cmd->advertising == ADVERTISED_1000baseT_Half)
6356 goto err_out_unlock;
b6016b76 6357 else {
7b6b8347 6358 if (cmd->port == PORT_FIBRE)
b6016b76 6359 advertising = ETHTOOL_ALL_FIBRE_SPEED;
7b6b8347 6360 else
b6016b76 6361 advertising = ETHTOOL_ALL_COPPER_SPEED;
b6016b76
MC		 6362 }
6363 advertising |= ADVERTISED_Autoneg;
6364 }
6365 else {
7b6b8347 6366 if (cmd->port == PORT_FIBRE) {
80be4434
MC		 6367 if ((cmd->speed != SPEED_1000 &&
6368 cmd->speed != SPEED_2500) ||
6369 (cmd->duplex != DUPLEX_FULL))
7b6b8347 6370 goto err_out_unlock;
80be4434
MC		 6371
6372 if (cmd->speed == SPEED_2500 &&
583c28e5 6373 !(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))
7b6b8347 6374 goto err_out_unlock;
b6016b76 6375 }
7b6b8347
MC		 6376 else if (cmd->speed == SPEED_1000 || cmd->speed == SPEED_2500)
6377 goto err_out_unlock;
6378
b6016b76
MC		 6379 autoneg &= ~AUTONEG_SPEED;
6380 req_line_speed = cmd->speed;
6381 req_duplex = cmd->duplex;
6382 advertising = 0;
6383 }
6384
6385 bp->autoneg = autoneg;
6386 bp->advertising = advertising;
6387 bp->req_line_speed = req_line_speed;
6388 bp->req_duplex = req_duplex;
6389
d6b14486
MC		 6390 err = 0;
6391 /* If device is down, the new settings will be picked up when it is
6392 * brought up.
6393 */
6394 if (netif_running(dev))
6395 err = bnx2_setup_phy(bp, cmd->port);
b6016b76 6396
7b6b8347 6397err_out_unlock:
c770a65c 6398 spin_unlock_bh(&bp->phy_lock);
b6016b76 6399
7b6b8347 6400 return err;
b6016b76
MC		 6401}
6402
6403static void
6404bnx2_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
6405{
972ec0d4 6406 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 6407
6408 strcpy(info->driver, DRV_MODULE_NAME);
6409 strcpy(info->version, DRV_MODULE_VERSION);
6410 strcpy(info->bus_info, pci_name(bp->pdev));
58fc2ea4 6411 strcpy(info->fw_version, bp->fw_version);
b6016b76
MC		 6412}
6413
244ac4f4
MC		 6414#define BNX2_REGDUMP_LEN (32 * 1024)
6415
6416static int
6417bnx2_get_regs_len(struct net_device *dev)
6418{
6419 return BNX2_REGDUMP_LEN;
6420}
6421
6422static void
6423bnx2_get_regs(struct net_device *dev, struct ethtool_regs *regs, void *_p)
6424{
6425 u32 *p = _p, i, offset;
6426 u8 *orig_p = _p;
6427 struct bnx2 *bp = netdev_priv(dev);
6428 u32 reg_boundaries[] = { 0x0000, 0x0098, 0x0400, 0x045c,
6429 0x0800, 0x0880, 0x0c00, 0x0c10,
6430 0x0c30, 0x0d08, 0x1000, 0x101c,
6431 0x1040, 0x1048, 0x1080, 0x10a4,
6432 0x1400, 0x1490, 0x1498, 0x14f0,
6433 0x1500, 0x155c, 0x1580, 0x15dc,
6434 0x1600, 0x1658, 0x1680, 0x16d8,
6435 0x1800, 0x1820, 0x1840, 0x1854,
6436 0x1880, 0x1894, 0x1900, 0x1984,
6437 0x1c00, 0x1c0c, 0x1c40, 0x1c54,
6438 0x1c80, 0x1c94, 0x1d00, 0x1d84,
6439 0x2000, 0x2030, 0x23c0, 0x2400,
6440 0x2800, 0x2820, 0x2830, 0x2850,
6441 0x2b40, 0x2c10, 0x2fc0, 0x3058,
6442 0x3c00, 0x3c94, 0x4000, 0x4010,
6443 0x4080, 0x4090, 0x43c0, 0x4458,
6444 0x4c00, 0x4c18, 0x4c40, 0x4c54,
6445 0x4fc0, 0x5010, 0x53c0, 0x5444,
6446 0x5c00, 0x5c18, 0x5c80, 0x5c90,
6447 0x5fc0, 0x6000, 0x6400, 0x6428,
6448 0x6800, 0x6848, 0x684c, 0x6860,
6449 0x6888, 0x6910, 0x8000 };
6450
6451 regs->version = 0;
6452
6453 memset(p, 0, BNX2_REGDUMP_LEN);
6454
6455 if (!netif_running(bp->dev))
6456 return;
6457
6458 i = 0;
6459 offset = reg_boundaries[0];
6460 p += offset;
6461 while (offset < BNX2_REGDUMP_LEN) {
6462 *p++ = REG_RD(bp, offset);
6463 offset += 4;
6464 if (offset == reg_boundaries[i + 1]) {
6465 offset = reg_boundaries[i + 2];
6466 p = (u32 *) (orig_p + offset);
6467 i += 2;
6468 }
6469 }
6470}
6471
b6016b76
MC		 6472static void
6473bnx2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
6474{
972ec0d4 6475 struct bnx2 *bp = netdev_priv(dev);
b6016b76 6476
f86e82fb 6477 if (bp->flags & BNX2_FLAG_NO_WOL) {
b6016b76
MC		 6478 wol->supported = 0;
6479 wol->wolopts = 0;
6480 }
6481 else {
6482 wol->supported = WAKE_MAGIC;
6483 if (bp->wol)
6484 wol->wolopts = WAKE_MAGIC;
6485 else
6486 wol->wolopts = 0;
6487 }
6488 memset(&wol->sopass, 0, sizeof(wol->sopass));
6489}
6490
6491static int
6492bnx2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
6493{
972ec0d4 6494 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 6495
6496 if (wol->wolopts & ~WAKE_MAGIC)
6497 return -EINVAL;
6498
6499 if (wol->wolopts & WAKE_MAGIC) {
f86e82fb 6500 if (bp->flags & BNX2_FLAG_NO_WOL)
b6016b76
MC		 6501 return -EINVAL;
6502
6503 bp->wol = 1;
6504 }
6505 else {
6506 bp->wol = 0;
6507 }
6508 return 0;
6509}
6510
6511static int
6512bnx2_nway_reset(struct net_device *dev)
6513{
972ec0d4 6514 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 6515 u32 bmcr;
6516
9f52b564
MC		 6517 if (!netif_running(dev))
6518 return -EAGAIN;
6519
b6016b76
MC		 6520 if (!(bp->autoneg & AUTONEG_SPEED)) {
6521 return -EINVAL;
6522 }
6523
c770a65c 6524 spin_lock_bh(&bp->phy_lock);
b6016b76 6525
583c28e5 6526 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) {
7b6b8347
MC		 6527 int rc;
6528
6529 rc = bnx2_setup_remote_phy(bp, bp->phy_port);
6530 spin_unlock_bh(&bp->phy_lock);
6531 return rc;
6532 }
6533
b6016b76 6534 /* Force a link down visible on the other side */
583c28e5 6535 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
ca58c3af 6536 bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK);
c770a65c 6537 spin_unlock_bh(&bp->phy_lock);
b6016b76
MC		 6538
6539 msleep(20);
6540
c770a65c 6541 spin_lock_bh(&bp->phy_lock);
f8dd064e
MC		 6542
6543 bp->current_interval = SERDES_AN_TIMEOUT;
6544 bp->serdes_an_pending = 1;
6545 mod_timer(&bp->timer, jiffies + bp->current_interval);
b6016b76
MC		 6546 }
6547
ca58c3af 6548 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
b6016b76 6549 bmcr &= ~BMCR_LOOPBACK;
ca58c3af 6550 bnx2_write_phy(bp, bp->mii_bmcr, bmcr | BMCR_ANRESTART | BMCR_ANENABLE);
b6016b76 6551
c770a65c 6552 spin_unlock_bh(&bp->phy_lock);
b6016b76
MC		 6553
6554 return 0;
6555}
6556
6557static int
6558bnx2_get_eeprom_len(struct net_device *dev)
6559{
972ec0d4 6560 struct bnx2 *bp = netdev_priv(dev);
b6016b76 6561
1122db71 6562 if (bp->flash_info == NULL)
b6016b76
MC		 6563 return 0;
6564
1122db71 6565 return (int) bp->flash_size;
b6016b76
MC		 6566}
6567
6568static int
6569bnx2_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
6570 u8 *eebuf)
6571{
972ec0d4 6572 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 6573 int rc;
6574
9f52b564
MC		 6575 if (!netif_running(dev))
6576 return -EAGAIN;
6577
1064e944 6578 /* parameters already validated in ethtool_get_eeprom */
b6016b76
MC		 6579
6580 rc = bnx2_nvram_read(bp, eeprom->offset, eebuf, eeprom->len);
6581
6582 return rc;
6583}
6584
6585static int
6586bnx2_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
6587 u8 *eebuf)
6588{
972ec0d4 6589 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 6590 int rc;
6591
9f52b564
MC		 6592 if (!netif_running(dev))
6593 return -EAGAIN;
6594
1064e944 6595 /* parameters already validated in ethtool_set_eeprom */
b6016b76
MC		 6596
6597 rc = bnx2_nvram_write(bp, eeprom->offset, eebuf, eeprom->len);
6598
6599 return rc;
6600}
6601
6602static int
6603bnx2_get_coalesce(struct net_device *dev, struct ethtool_coalesce *coal)
6604{
972ec0d4 6605 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 6606
6607 memset(coal, 0, sizeof(struct ethtool_coalesce));
6608
6609 coal->rx_coalesce_usecs = bp->rx_ticks;
6610 coal->rx_max_coalesced_frames = bp->rx_quick_cons_trip;
6611 coal->rx_coalesce_usecs_irq = bp->rx_ticks_int;
6612 coal->rx_max_coalesced_frames_irq = bp->rx_quick_cons_trip_int;
6613
6614 coal->tx_coalesce_usecs = bp->tx_ticks;
6615 coal->tx_max_coalesced_frames = bp->tx_quick_cons_trip;
6616 coal->tx_coalesce_usecs_irq = bp->tx_ticks_int;
6617 coal->tx_max_coalesced_frames_irq = bp->tx_quick_cons_trip_int;
6618
6619 coal->stats_block_coalesce_usecs = bp->stats_ticks;
6620
6621 return 0;
6622}
6623
6624static int
6625bnx2_set_coalesce(struct net_device *dev, struct ethtool_coalesce *coal)
6626{
972ec0d4 6627 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 6628
6629 bp->rx_ticks = (u16) coal->rx_coalesce_usecs;
6630 if (bp->rx_ticks > 0x3ff) bp->rx_ticks = 0x3ff;
6631
6aa20a22 6632 bp->rx_quick_cons_trip = (u16) coal->rx_max_coalesced_frames;
b6016b76
MC		 6633 if (bp->rx_quick_cons_trip > 0xff) bp->rx_quick_cons_trip = 0xff;
6634
6635 bp->rx_ticks_int = (u16) coal->rx_coalesce_usecs_irq;
6636 if (bp->rx_ticks_int > 0x3ff) bp->rx_ticks_int = 0x3ff;
6637
6638 bp->rx_quick_cons_trip_int = (u16) coal->rx_max_coalesced_frames_irq;
6639 if (bp->rx_quick_cons_trip_int > 0xff)
6640 bp->rx_quick_cons_trip_int = 0xff;
6641
6642 bp->tx_ticks = (u16) coal->tx_coalesce_usecs;
6643 if (bp->tx_ticks > 0x3ff) bp->tx_ticks = 0x3ff;
6644
6645 bp->tx_quick_cons_trip = (u16) coal->tx_max_coalesced_frames;
6646 if (bp->tx_quick_cons_trip > 0xff) bp->tx_quick_cons_trip = 0xff;
6647
6648 bp->tx_ticks_int = (u16) coal->tx_coalesce_usecs_irq;
6649 if (bp->tx_ticks_int > 0x3ff) bp->tx_ticks_int = 0x3ff;
6650
6651 bp->tx_quick_cons_trip_int = (u16) coal->tx_max_coalesced_frames_irq;
6652 if (bp->tx_quick_cons_trip_int > 0xff) bp->tx_quick_cons_trip_int =
6653 0xff;
6654
6655 bp->stats_ticks = coal->stats_block_coalesce_usecs;
02537b06
MC		 6656 if (CHIP_NUM(bp) == CHIP_NUM_5708) {
6657 if (bp->stats_ticks != 0 && bp->stats_ticks != USEC_PER_SEC)
6658 bp->stats_ticks = USEC_PER_SEC;
6659 }
7ea6920e
MC		 6660 if (bp->stats_ticks > BNX2_HC_STATS_TICKS_HC_STAT_TICKS)
6661 bp->stats_ticks = BNX2_HC_STATS_TICKS_HC_STAT_TICKS;
6662 bp->stats_ticks &= BNX2_HC_STATS_TICKS_HC_STAT_TICKS;
b6016b76
MC		 6663
6664 if (netif_running(bp->dev)) {
6665 bnx2_netif_stop(bp);
9a120bc5 6666 bnx2_init_nic(bp, 0);
b6016b76
MC		 6667 bnx2_netif_start(bp);
6668 }
6669
6670 return 0;
6671}
6672
6673static void
6674bnx2_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
6675{
972ec0d4 6676 struct bnx2 *bp = netdev_priv(dev);
b6016b76 6677
13daffa2 6678 ering->rx_max_pending = MAX_TOTAL_RX_DESC_CNT;
b6016b76 6679 ering->rx_mini_max_pending = 0;
47bf4246 6680 ering->rx_jumbo_max_pending = MAX_TOTAL_RX_PG_DESC_CNT;
b6016b76
MC		 6681
6682 ering->rx_pending = bp->rx_ring_size;
6683 ering->rx_mini_pending = 0;
47bf4246 6684 ering->rx_jumbo_pending = bp->rx_pg_ring_size;
b6016b76
MC		 6685
6686 ering->tx_max_pending = MAX_TX_DESC_CNT;
6687 ering->tx_pending = bp->tx_ring_size;
6688}
6689
6690static int
5d5d0015 6691bnx2_change_ring_size(struct bnx2 *bp, u32 rx, u32 tx)
b6016b76 6692{
13daffa2
MC		 6693 if (netif_running(bp->dev)) {
6694 bnx2_netif_stop(bp);
6695 bnx2_reset_chip(bp, BNX2_DRV_MSG_CODE_RESET);
6696 bnx2_free_skbs(bp);
6697 bnx2_free_mem(bp);
6698 }
6699
5d5d0015
MC		 6700 bnx2_set_rx_ring_size(bp, rx);
6701 bp->tx_ring_size = tx;
b6016b76
MC		 6702
6703 if (netif_running(bp->dev)) {
13daffa2
MC		 6704 int rc;
6705
6706 rc = bnx2_alloc_mem(bp);
6707 if (rc)
6708 return rc;
9a120bc5 6709 bnx2_init_nic(bp, 0);
b6016b76
MC		 6710 bnx2_netif_start(bp);
6711 }
b6016b76
MC		 6712 return 0;
6713}
6714
5d5d0015
MC		 6715static int
6716bnx2_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
6717{
6718 struct bnx2 *bp = netdev_priv(dev);
6719 int rc;
6720
6721 if ((ering->rx_pending > MAX_TOTAL_RX_DESC_CNT) ||
6722 (ering->tx_pending > MAX_TX_DESC_CNT) ||
6723 (ering->tx_pending <= MAX_SKB_FRAGS)) {
6724
6725 return -EINVAL;
6726 }
6727 rc = bnx2_change_ring_size(bp, ering->rx_pending, ering->tx_pending);
6728 return rc;
6729}
6730
b6016b76
MC		 6731static void
6732bnx2_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
6733{
972ec0d4 6734 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 6735
6736 epause->autoneg = ((bp->autoneg & AUTONEG_FLOW_CTRL) != 0);
6737 epause->rx_pause = ((bp->flow_ctrl & FLOW_CTRL_RX) != 0);
6738 epause->tx_pause = ((bp->flow_ctrl & FLOW_CTRL_TX) != 0);
6739}
6740
6741static int
6742bnx2_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
6743{
972ec0d4 6744 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 6745
6746 bp->req_flow_ctrl = 0;
6747 if (epause->rx_pause)
6748 bp->req_flow_ctrl |= FLOW_CTRL_RX;
6749 if (epause->tx_pause)
6750 bp->req_flow_ctrl |= FLOW_CTRL_TX;
6751
6752 if (epause->autoneg) {
6753 bp->autoneg |= AUTONEG_FLOW_CTRL;
6754 }
6755 else {
6756 bp->autoneg &= ~AUTONEG_FLOW_CTRL;
6757 }
6758
9f52b564
MC		 6759 if (netif_running(dev)) {
6760 spin_lock_bh(&bp->phy_lock);
6761 bnx2_setup_phy(bp, bp->phy_port);
6762 spin_unlock_bh(&bp->phy_lock);
6763 }
b6016b76
MC		 6764
6765 return 0;
6766}
6767
6768static u32
6769bnx2_get_rx_csum(struct net_device *dev)
6770{
972ec0d4 6771 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 6772
6773 return bp->rx_csum;
6774}
6775
6776static int
6777bnx2_set_rx_csum(struct net_device *dev, u32 data)
6778{
972ec0d4 6779 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 6780
6781 bp->rx_csum = data;
6782 return 0;
6783}
6784
b11d6213
MC		 6785static int
6786bnx2_set_tso(struct net_device *dev, u32 data)
6787{
4666f87a
MC		 6788 struct bnx2 *bp = netdev_priv(dev);
6789
6790 if (data) {
b11d6213 6791 dev->features |= NETIF_F_TSO | NETIF_F_TSO_ECN;
4666f87a
MC		 6792 if (CHIP_NUM(bp) == CHIP_NUM_5709)
6793 dev->features |= NETIF_F_TSO6;
6794 } else
6795 dev->features &= ~(NETIF_F_TSO | NETIF_F_TSO6 |
6796 NETIF_F_TSO_ECN);
b11d6213
MC		 6797 return 0;
6798}
6799
cea94db9 6800#define BNX2_NUM_STATS 46
b6016b76 6801
14ab9b86 6802static struct {
b6016b76
MC		 6803 char string[ETH_GSTRING_LEN];
6804} bnx2_stats_str_arr[BNX2_NUM_STATS] = {
6805 { "rx_bytes" },
6806 { "rx_error_bytes" },
6807 { "tx_bytes" },
6808 { "tx_error_bytes" },
6809 { "rx_ucast_packets" },
6810 { "rx_mcast_packets" },
6811 { "rx_bcast_packets" },
6812 { "tx_ucast_packets" },
6813 { "tx_mcast_packets" },
6814 { "tx_bcast_packets" },
6815 { "tx_mac_errors" },
6816 { "tx_carrier_errors" },
6817 { "rx_crc_errors" },
6818 { "rx_align_errors" },
6819 { "tx_single_collisions" },
6820 { "tx_multi_collisions" },
6821 { "tx_deferred" },
6822 { "tx_excess_collisions" },
6823 { "tx_late_collisions" },
6824 { "tx_total_collisions" },
6825 { "rx_fragments" },
6826 { "rx_jabbers" },
6827 { "rx_undersize_packets" },
6828 { "rx_oversize_packets" },
6829 { "rx_64_byte_packets" },
6830 { "rx_65_to_127_byte_packets" },
6831 { "rx_128_to_255_byte_packets" },
6832 { "rx_256_to_511_byte_packets" },
6833 { "rx_512_to_1023_byte_packets" },
6834 { "rx_1024_to_1522_byte_packets" },
6835 { "rx_1523_to_9022_byte_packets" },
6836 { "tx_64_byte_packets" },
6837 { "tx_65_to_127_byte_packets" },
6838 { "tx_128_to_255_byte_packets" },
6839 { "tx_256_to_511_byte_packets" },
6840 { "tx_512_to_1023_byte_packets" },
6841 { "tx_1024_to_1522_byte_packets" },
6842 { "tx_1523_to_9022_byte_packets" },
6843 { "rx_xon_frames" },
6844 { "rx_xoff_frames" },
6845 { "tx_xon_frames" },
6846 { "tx_xoff_frames" },
6847 { "rx_mac_ctrl_frames" },
6848 { "rx_filtered_packets" },
6849 { "rx_discards" },
cea94db9 6850 { "rx_fw_discards" },
b6016b76
MC		 6851};
6852
6853#define STATS_OFFSET32(offset_name) (offsetof(struct statistics_block, offset_name) / 4)
6854
f71e1309 6855static const unsigned long bnx2_stats_offset_arr[BNX2_NUM_STATS] = {
b6016b76
MC		 6856 STATS_OFFSET32(stat_IfHCInOctets_hi),
6857 STATS_OFFSET32(stat_IfHCInBadOctets_hi),
6858 STATS_OFFSET32(stat_IfHCOutOctets_hi),
6859 STATS_OFFSET32(stat_IfHCOutBadOctets_hi),
6860 STATS_OFFSET32(stat_IfHCInUcastPkts_hi),
6861 STATS_OFFSET32(stat_IfHCInMulticastPkts_hi),
6862 STATS_OFFSET32(stat_IfHCInBroadcastPkts_hi),
6863 STATS_OFFSET32(stat_IfHCOutUcastPkts_hi),
6864 STATS_OFFSET32(stat_IfHCOutMulticastPkts_hi),
6865 STATS_OFFSET32(stat_IfHCOutBroadcastPkts_hi),
6866 STATS_OFFSET32(stat_emac_tx_stat_dot3statsinternalmactransmiterrors),
6aa20a22
JG		 6867 STATS_OFFSET32(stat_Dot3StatsCarrierSenseErrors),
6868 STATS_OFFSET32(stat_Dot3StatsFCSErrors),
6869 STATS_OFFSET32(stat_Dot3StatsAlignmentErrors),
6870 STATS_OFFSET32(stat_Dot3StatsSingleCollisionFrames),
6871 STATS_OFFSET32(stat_Dot3StatsMultipleCollisionFrames),
6872 STATS_OFFSET32(stat_Dot3StatsDeferredTransmissions),
6873 STATS_OFFSET32(stat_Dot3StatsExcessiveCollisions),
6874 STATS_OFFSET32(stat_Dot3StatsLateCollisions),
6875 STATS_OFFSET32(stat_EtherStatsCollisions),
6876 STATS_OFFSET32(stat_EtherStatsFragments),
6877 STATS_OFFSET32(stat_EtherStatsJabbers),
6878 STATS_OFFSET32(stat_EtherStatsUndersizePkts),
6879 STATS_OFFSET32(stat_EtherStatsOverrsizePkts),
6880 STATS_OFFSET32(stat_EtherStatsPktsRx64Octets),
6881 STATS_OFFSET32(stat_EtherStatsPktsRx65Octetsto127Octets),
6882 STATS_OFFSET32(stat_EtherStatsPktsRx128Octetsto255Octets),
6883 STATS_OFFSET32(stat_EtherStatsPktsRx256Octetsto511Octets),
6884 STATS_OFFSET32(stat_EtherStatsPktsRx512Octetsto1023Octets),
6885 STATS_OFFSET32(stat_EtherStatsPktsRx1024Octetsto1522Octets),
6886 STATS_OFFSET32(stat_EtherStatsPktsRx1523Octetsto9022Octets),
6887 STATS_OFFSET32(stat_EtherStatsPktsTx64Octets),
6888 STATS_OFFSET32(stat_EtherStatsPktsTx65Octetsto127Octets),
6889 STATS_OFFSET32(stat_EtherStatsPktsTx128Octetsto255Octets),
6890 STATS_OFFSET32(stat_EtherStatsPktsTx256Octetsto511Octets),
6891 STATS_OFFSET32(stat_EtherStatsPktsTx512Octetsto1023Octets),
6892 STATS_OFFSET32(stat_EtherStatsPktsTx1024Octetsto1522Octets),
6893 STATS_OFFSET32(stat_EtherStatsPktsTx1523Octetsto9022Octets),
6894 STATS_OFFSET32(stat_XonPauseFramesReceived),
6895 STATS_OFFSET32(stat_XoffPauseFramesReceived),
6896 STATS_OFFSET32(stat_OutXonSent),
6897 STATS_OFFSET32(stat_OutXoffSent),
6898 STATS_OFFSET32(stat_MacControlFramesReceived),
6899 STATS_OFFSET32(stat_IfInFramesL2FilterDiscards),
6900 STATS_OFFSET32(stat_IfInMBUFDiscards),
cea94db9 6901 STATS_OFFSET32(stat_FwRxDrop),
b6016b76
MC		 6902};
6903
6904/* stat_IfHCInBadOctets and stat_Dot3StatsCarrierSenseErrors are
6905 * skipped because of errata.
6aa20a22 6906 */
14ab9b86 6907static u8 bnx2_5706_stats_len_arr[BNX2_NUM_STATS] = {
b6016b76
MC		 6908 8,0,8,8,8,8,8,8,8,8,
6909 4,0,4,4,4,4,4,4,4,4,
6910 4,4,4,4,4,4,4,4,4,4,
6911 4,4,4,4,4,4,4,4,4,4,
cea94db9 6912 4,4,4,4,4,4,
b6016b76
MC		 6913};
6914
5b0c76ad
MC		 6915static u8 bnx2_5708_stats_len_arr[BNX2_NUM_STATS] = {
6916 8,0,8,8,8,8,8,8,8,8,
6917 4,4,4,4,4,4,4,4,4,4,
6918 4,4,4,4,4,4,4,4,4,4,
6919 4,4,4,4,4,4,4,4,4,4,
cea94db9 6920 4,4,4,4,4,4,
5b0c76ad
MC		 6921};
6922
b6016b76
MC		 6923#define BNX2_NUM_TESTS 6
6924
14ab9b86 6925static struct {
b6016b76
MC		 6926 char string[ETH_GSTRING_LEN];
6927} bnx2_tests_str_arr[BNX2_NUM_TESTS] = {
6928 { "register_test (offline)" },
6929 { "memory_test (offline)" },
6930 { "loopback_test (offline)" },
6931 { "nvram_test (online)" },
6932 { "interrupt_test (online)" },
6933 { "link_test (online)" },
6934};
6935
6936static int
b9f2c044 6937bnx2_get_sset_count(struct net_device *dev, int sset)
b6016b76 6938{
b9f2c044
JG		 6939 switch (sset) {
6940 case ETH_SS_TEST:
6941 return BNX2_NUM_TESTS;
6942 case ETH_SS_STATS:
6943 return BNX2_NUM_STATS;
6944 default:
6945 return -EOPNOTSUPP;
6946 }
b6016b76
MC		 6947}
6948
6949static void
6950bnx2_self_test(struct net_device *dev, struct ethtool_test *etest, u64 *buf)
6951{
972ec0d4 6952 struct bnx2 *bp = netdev_priv(dev);
b6016b76 6953
9f52b564
MC		 6954 bnx2_set_power_state(bp, PCI_D0);
6955
b6016b76
MC		 6956 memset(buf, 0, sizeof(u64) * BNX2_NUM_TESTS);
6957 if (etest->flags & ETH_TEST_FL_OFFLINE) {
80be4434
MC		 6958 int i;
6959
b6016b76
MC		 6960 bnx2_netif_stop(bp);
6961 bnx2_reset_chip(bp, BNX2_DRV_MSG_CODE_DIAG);
6962 bnx2_free_skbs(bp);
6963
6964 if (bnx2_test_registers(bp) != 0) {
6965 buf[0] = 1;
6966 etest->flags |= ETH_TEST_FL_FAILED;
6967 }
6968 if (bnx2_test_memory(bp) != 0) {
6969 buf[1] = 1;
6970 etest->flags |= ETH_TEST_FL_FAILED;
6971 }
bc5a0690 6972 if ((buf[2] = bnx2_test_loopback(bp)) != 0)
b6016b76 6973 etest->flags |= ETH_TEST_FL_FAILED;
b6016b76 6974
9f52b564
MC		 6975 if (!netif_running(bp->dev))
6976 bnx2_shutdown_chip(bp);
b6016b76 6977 else {
9a120bc5 6978 bnx2_init_nic(bp, 1);
b6016b76
MC		 6979 bnx2_netif_start(bp);
6980 }
6981
6982 /* wait for link up */
80be4434
MC		 6983 for (i = 0; i < 7; i++) {
6984 if (bp->link_up)
6985 break;
6986 msleep_interruptible(1000);
6987 }
b6016b76
MC		 6988 }
6989
6990 if (bnx2_test_nvram(bp) != 0) {
6991 buf[3] = 1;
6992 etest->flags |= ETH_TEST_FL_FAILED;
6993 }
6994 if (bnx2_test_intr(bp) != 0) {
6995 buf[4] = 1;
6996 etest->flags |= ETH_TEST_FL_FAILED;
6997 }
6998
6999 if (bnx2_test_link(bp) != 0) {
7000 buf[5] = 1;
7001 etest->flags |= ETH_TEST_FL_FAILED;
7002
7003 }
9f52b564
MC		 7004 if (!netif_running(bp->dev))
7005 bnx2_set_power_state(bp, PCI_D3hot);
b6016b76
MC		 7006}
7007
7008static void
7009bnx2_get_strings(struct net_device *dev, u32 stringset, u8 *buf)
7010{
7011 switch (stringset) {
7012 case ETH_SS_STATS:
7013 memcpy(buf, bnx2_stats_str_arr,
7014 sizeof(bnx2_stats_str_arr));
7015 break;
7016 case ETH_SS_TEST:
7017 memcpy(buf, bnx2_tests_str_arr,
7018 sizeof(bnx2_tests_str_arr));
7019 break;
7020 }
7021}
7022
b6016b76
MC		 7023static void
7024bnx2_get_ethtool_stats(struct net_device *dev,
7025 struct ethtool_stats *stats, u64 *buf)
7026{
972ec0d4 7027 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 7028 int i;
7029 u32 *hw_stats = (u32 *) bp->stats_blk;
14ab9b86 7030 u8 *stats_len_arr = NULL;
b6016b76
MC		 7031
7032 if (hw_stats == NULL) {
7033 memset(buf, 0, sizeof(u64) * BNX2_NUM_STATS);
7034 return;
7035 }
7036
5b0c76ad
MC		 7037 if ((CHIP_ID(bp) == CHIP_ID_5706_A0) ||
7038 (CHIP_ID(bp) == CHIP_ID_5706_A1) ||
7039 (CHIP_ID(bp) == CHIP_ID_5706_A2) ||
7040 (CHIP_ID(bp) == CHIP_ID_5708_A0))
b6016b76 7041 stats_len_arr = bnx2_5706_stats_len_arr;
5b0c76ad
MC		 7042 else
7043 stats_len_arr = bnx2_5708_stats_len_arr;
b6016b76
MC		 7044
7045 for (i = 0; i < BNX2_NUM_STATS; i++) {
7046 if (stats_len_arr[i] == 0) {
7047 /* skip this counter */
7048 buf[i] = 0;
7049 continue;
7050 }
7051 if (stats_len_arr[i] == 4) {
7052 /* 4-byte counter */
7053 buf[i] = (u64)
7054 *(hw_stats + bnx2_stats_offset_arr[i]);
7055 continue;
7056 }
7057 /* 8-byte counter */
7058 buf[i] = (((u64) *(hw_stats +
7059 bnx2_stats_offset_arr[i])) << 32) +
7060 *(hw_stats + bnx2_stats_offset_arr[i] + 1);
7061 }
7062}
7063
7064static int
7065bnx2_phys_id(struct net_device *dev, u32 data)
7066{
972ec0d4 7067 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 7068 int i;
7069 u32 save;
7070
9f52b564
MC		 7071 bnx2_set_power_state(bp, PCI_D0);
7072
b6016b76
MC		 7073 if (data == 0)
7074 data = 2;
7075
7076 save = REG_RD(bp, BNX2_MISC_CFG);
7077 REG_WR(bp, BNX2_MISC_CFG, BNX2_MISC_CFG_LEDMODE_MAC);
7078
7079 for (i = 0; i < (data * 2); i++) {
7080 if ((i % 2) == 0) {
7081 REG_WR(bp, BNX2_EMAC_LED, BNX2_EMAC_LED_OVERRIDE);
7082 }
7083 else {
7084 REG_WR(bp, BNX2_EMAC_LED, BNX2_EMAC_LED_OVERRIDE |
7085 BNX2_EMAC_LED_1000MB_OVERRIDE |
7086 BNX2_EMAC_LED_100MB_OVERRIDE |
7087 BNX2_EMAC_LED_10MB_OVERRIDE |
7088 BNX2_EMAC_LED_TRAFFIC_OVERRIDE |
7089 BNX2_EMAC_LED_TRAFFIC);
7090 }
7091 msleep_interruptible(500);
7092 if (signal_pending(current))
7093 break;
7094 }
7095 REG_WR(bp, BNX2_EMAC_LED, 0);
7096 REG_WR(bp, BNX2_MISC_CFG, save);
9f52b564
MC		 7097
7098 if (!netif_running(dev))
7099 bnx2_set_power_state(bp, PCI_D3hot);
7100
b6016b76
MC		 7101 return 0;
7102}
7103
4666f87a
MC		 7104static int
7105bnx2_set_tx_csum(struct net_device *dev, u32 data)
7106{
7107 struct bnx2 *bp = netdev_priv(dev);
7108
7109 if (CHIP_NUM(bp) == CHIP_NUM_5709)
6460d948 7110 return (ethtool_op_set_tx_ipv6_csum(dev, data));
4666f87a
MC		 7111 else
7112 return (ethtool_op_set_tx_csum(dev, data));
7113}
7114
7282d491 7115static const struct ethtool_ops bnx2_ethtool_ops = {
b6016b76
MC		 7116 .get_settings = bnx2_get_settings,
7117 .set_settings = bnx2_set_settings,
7118 .get_drvinfo = bnx2_get_drvinfo,
244ac4f4
MC		 7119 .get_regs_len = bnx2_get_regs_len,
7120 .get_regs = bnx2_get_regs,
b6016b76
MC		 7121 .get_wol = bnx2_get_wol,
7122 .set_wol = bnx2_set_wol,
7123 .nway_reset = bnx2_nway_reset,
7124 .get_link = ethtool_op_get_link,
7125 .get_eeprom_len = bnx2_get_eeprom_len,
7126 .get_eeprom = bnx2_get_eeprom,
7127 .set_eeprom = bnx2_set_eeprom,
7128 .get_coalesce = bnx2_get_coalesce,
7129 .set_coalesce = bnx2_set_coalesce,
7130 .get_ringparam = bnx2_get_ringparam,
7131 .set_ringparam = bnx2_set_ringparam,
7132 .get_pauseparam = bnx2_get_pauseparam,
7133 .set_pauseparam = bnx2_set_pauseparam,
7134 .get_rx_csum = bnx2_get_rx_csum,
7135 .set_rx_csum = bnx2_set_rx_csum,
4666f87a 7136 .set_tx_csum = bnx2_set_tx_csum,
b6016b76 7137 .set_sg = ethtool_op_set_sg,
b11d6213 7138 .set_tso = bnx2_set_tso,
b6016b76
MC		 7139 .self_test = bnx2_self_test,
7140 .get_strings = bnx2_get_strings,
7141 .phys_id = bnx2_phys_id,
b6016b76 7142 .get_ethtool_stats = bnx2_get_ethtool_stats,
b9f2c044 7143 .get_sset_count = bnx2_get_sset_count,
b6016b76
MC		 7144};
7145
7146/* Called with rtnl_lock */
7147static int
7148bnx2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
7149{
14ab9b86 7150 struct mii_ioctl_data *data = if_mii(ifr);
972ec0d4 7151 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 7152 int err;
7153
7154 switch(cmd) {
7155 case SIOCGMIIPHY:
7156 data->phy_id = bp->phy_addr;
7157
7158 /* fallthru */
7159 case SIOCGMIIREG: {
7160 u32 mii_regval;
7161
583c28e5 7162 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
7b6b8347
MC		 7163 return -EOPNOTSUPP;
7164
dad3e452
MC		 7165 if (!netif_running(dev))
7166 return -EAGAIN;
7167
c770a65c 7168 spin_lock_bh(&bp->phy_lock);
b6016b76 7169 err = bnx2_read_phy(bp, data->reg_num & 0x1f, &mii_regval);
c770a65c 7170 spin_unlock_bh(&bp->phy_lock);
b6016b76
MC		 7171
7172 data->val_out = mii_regval;
7173
7174 return err;
7175 }
7176
7177 case SIOCSMIIREG:
7178 if (!capable(CAP_NET_ADMIN))
7179 return -EPERM;
7180
583c28e5 7181 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
7b6b8347
MC		 7182 return -EOPNOTSUPP;
7183
dad3e452
MC		 7184 if (!netif_running(dev))
7185 return -EAGAIN;
7186
c770a65c 7187 spin_lock_bh(&bp->phy_lock);
b6016b76 7188 err = bnx2_write_phy(bp, data->reg_num & 0x1f, data->val_in);
c770a65c 7189 spin_unlock_bh(&bp->phy_lock);
b6016b76
MC		 7190
7191 return err;
7192
7193 default:
7194 /* do nothing */
7195 break;
7196 }
7197 return -EOPNOTSUPP;
7198}
7199
7200/* Called with rtnl_lock */
7201static int
7202bnx2_change_mac_addr(struct net_device *dev, void *p)
7203{
7204 struct sockaddr *addr = p;
972ec0d4 7205 struct bnx2 *bp = netdev_priv(dev);
b6016b76 7206
73eef4cd
MC		 7207 if (!is_valid_ether_addr(addr->sa_data))
7208 return -EINVAL;
7209
b6016b76
MC		 7210 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
7211 if (netif_running(dev))
5fcaed01 7212 bnx2_set_mac_addr(bp, bp->dev->dev_addr, 0);
b6016b76
MC		 7213
7214 return 0;
7215}
7216
7217/* Called with rtnl_lock */
7218static int
7219bnx2_change_mtu(struct net_device *dev, int new_mtu)
7220{
972ec0d4 7221 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 7222
7223 if (((new_mtu + ETH_HLEN) > MAX_ETHERNET_JUMBO_PACKET_SIZE) ||
7224 ((new_mtu + ETH_HLEN) < MIN_ETHERNET_PACKET_SIZE))
7225 return -EINVAL;
7226
7227 dev->mtu = new_mtu;
5d5d0015 7228 return (bnx2_change_ring_size(bp, bp->rx_ring_size, bp->tx_ring_size));
b6016b76
MC		 7229}
7230
7231#if defined(HAVE_POLL_CONTROLLER) || defined(CONFIG_NET_POLL_CONTROLLER)
7232static void
7233poll_bnx2(struct net_device *dev)
7234{
972ec0d4 7235 struct bnx2 *bp = netdev_priv(dev);
b2af2c1d 7236 int i;
b6016b76 7237
b2af2c1d
NH		 7238 for (i = 0; i < bp->irq_nvecs; i++) {
7239 disable_irq(bp->irq_tbl[i].vector);
7240 bnx2_interrupt(bp->irq_tbl[i].vector, &bp->bnx2_napi[i]);
7241 enable_irq(bp->irq_tbl[i].vector);
7242 }
b6016b76
MC		 7243}
7244#endif
7245
253c8b75
MC		 7246static void __devinit
7247bnx2_get_5709_media(struct bnx2 *bp)
7248{
7249 u32 val = REG_RD(bp, BNX2_MISC_DUAL_MEDIA_CTRL);
7250 u32 bond_id = val & BNX2_MISC_DUAL_MEDIA_CTRL_BOND_ID;
7251 u32 strap;
7252
7253 if (bond_id == BNX2_MISC_DUAL_MEDIA_CTRL_BOND_ID_C)
7254 return;
7255 else if (bond_id == BNX2_MISC_DUAL_MEDIA_CTRL_BOND_ID_S) {
583c28e5 7256 bp->phy_flags |= BNX2_PHY_FLAG_SERDES;
253c8b75
MC		 7257 return;
7258 }
7259
7260 if (val & BNX2_MISC_DUAL_MEDIA_CTRL_STRAP_OVERRIDE)
7261 strap = (val & BNX2_MISC_DUAL_MEDIA_CTRL_PHY_CTRL) >> 21;
7262 else
7263 strap = (val & BNX2_MISC_DUAL_MEDIA_CTRL_PHY_CTRL_STRAP) >> 8;
7264
7265 if (PCI_FUNC(bp->pdev->devfn) == 0) {
7266 switch (strap) {
7267 case 0x4:
7268 case 0x5:
7269 case 0x6:
583c28e5 7270 bp->phy_flags |= BNX2_PHY_FLAG_SERDES;
253c8b75
MC		 7271 return;
7272 }
7273 } else {
7274 switch (strap) {
7275 case 0x1:
7276 case 0x2:
7277 case 0x4:
583c28e5 7278 bp->phy_flags |= BNX2_PHY_FLAG_SERDES;
253c8b75
MC		 7279 return;
7280 }
7281 }
7282}
7283
883e5151
MC		 7284static void __devinit
7285bnx2_get_pci_speed(struct bnx2 *bp)
7286{
7287 u32 reg;
7288
7289 reg = REG_RD(bp, BNX2_PCICFG_MISC_STATUS);
7290 if (reg & BNX2_PCICFG_MISC_STATUS_PCIX_DET) {
7291 u32 clkreg;
7292
f86e82fb 7293 bp->flags |= BNX2_FLAG_PCIX;
883e5151
MC		 7294
7295 clkreg = REG_RD(bp, BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS);
7296
7297 clkreg &= BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET;
7298 switch (clkreg) {
7299 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ:
7300 bp->bus_speed_mhz = 133;
7301 break;
7302
7303 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ:
7304 bp->bus_speed_mhz = 100;
7305 break;
7306
7307 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ:
7308 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ:
7309 bp->bus_speed_mhz = 66;
7310 break;
7311
7312 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ:
7313 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ:
7314 bp->bus_speed_mhz = 50;
7315 break;
7316
7317 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_LOW:
7318 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ:
7319 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ:
7320 bp->bus_speed_mhz = 33;
7321 break;
7322 }
7323 }
7324 else {
7325 if (reg & BNX2_PCICFG_MISC_STATUS_M66EN)
7326 bp->bus_speed_mhz = 66;
7327 else
7328 bp->bus_speed_mhz = 33;
7329 }
7330
7331 if (reg & BNX2_PCICFG_MISC_STATUS_32BIT_DET)
f86e82fb 7332 bp->flags |= BNX2_FLAG_PCI_32BIT;
883e5151
MC		 7333
7334}
7335
b6016b76
MC		 7336static int __devinit
7337bnx2_init_board(struct pci_dev *pdev, struct net_device *dev)
7338{
7339 struct bnx2 *bp;
7340 unsigned long mem_len;
58fc2ea4 7341 int rc, i, j;
b6016b76 7342 u32 reg;
40453c83 7343 u64 dma_mask, persist_dma_mask;
b6016b76 7344
b6016b76 7345 SET_NETDEV_DEV(dev, &pdev->dev);
972ec0d4 7346 bp = netdev_priv(dev);
b6016b76
MC		 7347
7348 bp->flags = 0;
7349 bp->phy_flags = 0;
7350
7351 /* enable device (incl. PCI PM wakeup), and bus-mastering */
7352 rc = pci_enable_device(pdev);
7353 if (rc) {
898eb71c 7354 dev_err(&pdev->dev, "Cannot enable PCI device, aborting.\n");
b6016b76
MC		 7355 goto err_out;
7356 }
7357
7358 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
9b91cf9d 7359 dev_err(&pdev->dev,
2e8a538d 7360 "Cannot find PCI device base address, aborting.\n");
b6016b76
MC		 7361 rc = -ENODEV;
7362 goto err_out_disable;
7363 }
7364
7365 rc = pci_request_regions(pdev, DRV_MODULE_NAME);
7366 if (rc) {
9b91cf9d 7367 dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting.\n");
b6016b76
MC		 7368 goto err_out_disable;
7369 }
7370
7371 pci_set_master(pdev);
6ff2da49 7372 pci_save_state(pdev);
b6016b76
MC		 7373
7374 bp->pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
7375 if (bp->pm_cap == 0) {
9b91cf9d 7376 dev_err(&pdev->dev,
2e8a538d 7377 "Cannot find power management capability, aborting.\n");
b6016b76
MC		 7378 rc = -EIO;
7379 goto err_out_release;
7380 }
7381
b6016b76
MC		 7382 bp->dev = dev;
7383 bp->pdev = pdev;
7384
7385 spin_lock_init(&bp->phy_lock);
1b8227c4 7386 spin_lock_init(&bp->indirect_lock);
c4028958 7387 INIT_WORK(&bp->reset_task, bnx2_reset_task);
b6016b76
MC		 7388
7389 dev->base_addr = dev->mem_start = pci_resource_start(pdev, 0);
706bf240 7390 mem_len = MB_GET_CID_ADDR(TX_TSS_CID + TX_MAX_TSS_RINGS);
b6016b76
MC		 7391 dev->mem_end = dev->mem_start + mem_len;
7392 dev->irq = pdev->irq;
7393
7394 bp->regview = ioremap_nocache(dev->base_addr, mem_len);
7395
7396 if (!bp->regview) {
9b91cf9d 7397 dev_err(&pdev->dev, "Cannot map register space, aborting.\n");
b6016b76
MC		 7398 rc = -ENOMEM;
7399 goto err_out_release;
7400 }
7401
7402 /* Configure byte swap and enable write to the reg_window registers.
7403 * Rely on CPU to do target byte swapping on big endian systems
7404 * The chip's target access swapping will not swap all accesses
7405 */
7406 pci_write_config_dword(bp->pdev, BNX2_PCICFG_MISC_CONFIG,
7407 BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
7408 BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP);
7409
829ca9a3 7410 bnx2_set_power_state(bp, PCI_D0);
b6016b76
MC		 7411
7412 bp->chip_id = REG_RD(bp, BNX2_MISC_ID);
7413
883e5151
MC		 7414 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
7415 if (pci_find_capability(pdev, PCI_CAP_ID_EXP) == 0) {
7416 dev_err(&pdev->dev,
7417 "Cannot find PCIE capability, aborting.\n");
7418 rc = -EIO;
7419 goto err_out_unmap;
7420 }
f86e82fb 7421 bp->flags |= BNX2_FLAG_PCIE;
2dd201d7 7422 if (CHIP_REV(bp) == CHIP_REV_Ax)
f86e82fb 7423 bp->flags |= BNX2_FLAG_JUMBO_BROKEN;
883e5151 7424 } else {
59b47d8a
MC		 7425 bp->pcix_cap = pci_find_capability(pdev, PCI_CAP_ID_PCIX);
7426 if (bp->pcix_cap == 0) {
7427 dev_err(&pdev->dev,
7428 "Cannot find PCIX capability, aborting.\n");
7429 rc = -EIO;
7430 goto err_out_unmap;
7431 }
7432 }
7433
b4b36042
MC		 7434 if (CHIP_NUM(bp) == CHIP_NUM_5709 && CHIP_REV(bp) != CHIP_REV_Ax) {
7435 if (pci_find_capability(pdev, PCI_CAP_ID_MSIX))
f86e82fb 7436 bp->flags |= BNX2_FLAG_MSIX_CAP;
b4b36042
MC		 7437 }
7438
8e6a72c4
MC		 7439 if (CHIP_ID(bp) != CHIP_ID_5706_A0 && CHIP_ID(bp) != CHIP_ID_5706_A1) {
7440 if (pci_find_capability(pdev, PCI_CAP_ID_MSI))
f86e82fb 7441 bp->flags |= BNX2_FLAG_MSI_CAP;
8e6a72c4
MC		 7442 }
7443
40453c83
MC		 7444 /* 5708 cannot support DMA addresses > 40-bit. */
7445 if (CHIP_NUM(bp) == CHIP_NUM_5708)
7446 persist_dma_mask = dma_mask = DMA_40BIT_MASK;
7447 else
7448 persist_dma_mask = dma_mask = DMA_64BIT_MASK;
7449
7450 /* Configure DMA attributes. */
7451 if (pci_set_dma_mask(pdev, dma_mask) == 0) {
7452 dev->features |= NETIF_F_HIGHDMA;
7453 rc = pci_set_consistent_dma_mask(pdev, persist_dma_mask);
7454 if (rc) {
7455 dev_err(&pdev->dev,
7456 "pci_set_consistent_dma_mask failed, aborting.\n");
7457 goto err_out_unmap;
7458 }
7459 } else if ((rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK)) != 0) {
7460 dev_err(&pdev->dev, "System does not support DMA, aborting.\n");
7461 goto err_out_unmap;
7462 }
7463
f86e82fb 7464 if (!(bp->flags & BNX2_FLAG_PCIE))
883e5151 7465 bnx2_get_pci_speed(bp);
b6016b76
MC		 7466
7467 /* 5706A0 may falsely detect SERR and PERR. */
7468 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
7469 reg = REG_RD(bp, PCI_COMMAND);
7470 reg &= ~(PCI_COMMAND_SERR | PCI_COMMAND_PARITY);
7471 REG_WR(bp, PCI_COMMAND, reg);
7472 }
7473 else if ((CHIP_ID(bp) == CHIP_ID_5706_A1) &&
f86e82fb 7474 !(bp->flags & BNX2_FLAG_PCIX)) {
b6016b76 7475
9b91cf9d 7476 dev_err(&pdev->dev,
2e8a538d 7477 "5706 A1 can only be used in a PCIX bus, aborting.\n");
b6016b76
MC		 7478 goto err_out_unmap;
7479 }
7480
7481 bnx2_init_nvram(bp);
7482
2726d6e1 7483 reg = bnx2_reg_rd_ind(bp, BNX2_SHM_HDR_SIGNATURE);
e3648b3d
MC		 7484
7485 if ((reg & BNX2_SHM_HDR_SIGNATURE_SIG_MASK) ==
24cb230b
MC		 7486 BNX2_SHM_HDR_SIGNATURE_SIG) {
7487 u32 off = PCI_FUNC(pdev->devfn) << 2;
7488
2726d6e1 7489 bp->shmem_base = bnx2_reg_rd_ind(bp, BNX2_SHM_HDR_ADDR_0 + off);
24cb230b 7490 } else
e3648b3d
MC		 7491 bp->shmem_base = HOST_VIEW_SHMEM_BASE;
7492
b6016b76
MC		 7493 /* Get the permanent MAC address. First we need to make sure the
7494 * firmware is actually running.
7495 */
2726d6e1 7496 reg = bnx2_shmem_rd(bp, BNX2_DEV_INFO_SIGNATURE);
b6016b76
MC		 7497
7498 if ((reg & BNX2_DEV_INFO_SIGNATURE_MAGIC_MASK) !=
7499 BNX2_DEV_INFO_SIGNATURE_MAGIC) {
9b91cf9d 7500 dev_err(&pdev->dev, "Firmware not running, aborting.\n");
b6016b76
MC		 7501 rc = -ENODEV;
7502 goto err_out_unmap;
7503 }
7504
2726d6e1 7505 reg = bnx2_shmem_rd(bp, BNX2_DEV_INFO_BC_REV);
58fc2ea4
MC		 7506 for (i = 0, j = 0; i < 3; i++) {
7507 u8 num, k, skip0;
7508
7509 num = (u8) (reg >> (24 - (i * 8)));
7510 for (k = 100, skip0 = 1; k >= 1; num %= k, k /= 10) {
7511 if (num >= k || !skip0 || k == 1) {
7512 bp->fw_version[j++] = (num / k) + '0';
7513 skip0 = 0;
7514 }
7515 }
7516 if (i != 2)
7517 bp->fw_version[j++] = '.';
7518 }
2726d6e1 7519 reg = bnx2_shmem_rd(bp, BNX2_PORT_FEATURE);
846f5c62
MC		 7520 if (reg & BNX2_PORT_FEATURE_WOL_ENABLED)
7521 bp->wol = 1;
7522
7523 if (reg & BNX2_PORT_FEATURE_ASF_ENABLED) {
f86e82fb 7524 bp->flags |= BNX2_FLAG_ASF_ENABLE;
c2d3db8c
MC		 7525
7526 for (i = 0; i < 30; i++) {
2726d6e1 7527 reg = bnx2_shmem_rd(bp, BNX2_BC_STATE_CONDITION);
c2d3db8c
MC		 7528 if (reg & BNX2_CONDITION_MFW_RUN_MASK)
7529 break;
7530 msleep(10);
7531 }
7532 }
2726d6e1 7533 reg = bnx2_shmem_rd(bp, BNX2_BC_STATE_CONDITION);
58fc2ea4
MC		 7534 reg &= BNX2_CONDITION_MFW_RUN_MASK;
7535 if (reg != BNX2_CONDITION_MFW_RUN_UNKNOWN &&
7536 reg != BNX2_CONDITION_MFW_RUN_NONE) {
2726d6e1 7537 u32 addr = bnx2_shmem_rd(bp, BNX2_MFW_VER_PTR);
58fc2ea4
MC		 7538
7539 bp->fw_version[j++] = ' ';
7540 for (i = 0; i < 3; i++) {
2726d6e1 7541 reg = bnx2_reg_rd_ind(bp, addr + i * 4);
58fc2ea4
MC		 7542 reg = swab32(reg);
7543 memcpy(&bp->fw_version[j], &reg, 4);
7544 j += 4;
7545 }
7546 }
b6016b76 7547
2726d6e1 7548 reg = bnx2_shmem_rd(bp, BNX2_PORT_HW_CFG_MAC_UPPER);
b6016b76
MC		 7549 bp->mac_addr[0] = (u8) (reg >> 8);
7550 bp->mac_addr[1] = (u8) reg;
7551
2726d6e1 7552 reg = bnx2_shmem_rd(bp, BNX2_PORT_HW_CFG_MAC_LOWER);
b6016b76
MC		 7553 bp->mac_addr[2] = (u8) (reg >> 24);
7554 bp->mac_addr[3] = (u8) (reg >> 16);
7555 bp->mac_addr[4] = (u8) (reg >> 8);
7556 bp->mac_addr[5] = (u8) reg;
7557
7558 bp->tx_ring_size = MAX_TX_DESC_CNT;
932f3772 7559 bnx2_set_rx_ring_size(bp, 255);
b6016b76
MC		 7560
7561 bp->rx_csum = 1;
7562
b6016b76
MC		 7563 bp->tx_quick_cons_trip_int = 20;
7564 bp->tx_quick_cons_trip = 20;
7565 bp->tx_ticks_int = 80;
7566 bp->tx_ticks = 80;
6aa20a22 7567
b6016b76
MC		 7568 bp->rx_quick_cons_trip_int = 6;
7569 bp->rx_quick_cons_trip = 6;
7570 bp->rx_ticks_int = 18;
7571 bp->rx_ticks = 18;
7572
7ea6920e 7573 bp->stats_ticks = USEC_PER_SEC & BNX2_HC_STATS_TICKS_HC_STAT_TICKS;
b6016b76 7574
ac392abc 7575 bp->current_interval = BNX2_TIMER_INTERVAL;
b6016b76 7576
5b0c76ad
MC		 7577 bp->phy_addr = 1;
7578
b6016b76 7579 /* Disable WOL support if we are running on a SERDES chip. */
253c8b75
MC		 7580 if (CHIP_NUM(bp) == CHIP_NUM_5709)
7581 bnx2_get_5709_media(bp);
7582 else if (CHIP_BOND_ID(bp) & CHIP_BOND_ID_SERDES_BIT)
583c28e5 7583 bp->phy_flags |= BNX2_PHY_FLAG_SERDES;
bac0dff6 7584
0d8a6571 7585 bp->phy_port = PORT_TP;
583c28e5 7586 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
0d8a6571 7587 bp->phy_port = PORT_FIBRE;
2726d6e1 7588 reg = bnx2_shmem_rd(bp, BNX2_SHARED_HW_CFG_CONFIG);
846f5c62 7589 if (!(reg & BNX2_SHARED_HW_CFG_GIG_LINK_ON_VAUX)) {
f86e82fb 7590 bp->flags |= BNX2_FLAG_NO_WOL;
846f5c62
MC		 7591 bp->wol = 0;
7592 }
38ea3686
MC		 7593 if (CHIP_NUM(bp) == CHIP_NUM_5706) {
7594 /* Don't do parallel detect on this board because of
7595 * some board problems. The link will not go down
7596 * if we do parallel detect.
7597 */
7598 if (pdev->subsystem_vendor == PCI_VENDOR_ID_HP &&
7599 pdev->subsystem_device == 0x310c)
7600 bp->phy_flags |= BNX2_PHY_FLAG_NO_PARALLEL;
7601 } else {
5b0c76ad 7602 bp->phy_addr = 2;
5b0c76ad 7603 if (reg & BNX2_SHARED_HW_CFG_PHY_2_5G)
583c28e5 7604 bp->phy_flags |= BNX2_PHY_FLAG_2_5G_CAPABLE;
5b0c76ad 7605 }
261dd5ca
MC		 7606 } else if (CHIP_NUM(bp) == CHIP_NUM_5706 ||
7607 CHIP_NUM(bp) == CHIP_NUM_5708)
583c28e5 7608 bp->phy_flags |= BNX2_PHY_FLAG_CRC_FIX;
fb0c18bd
MC		 7609 else if (CHIP_NUM(bp) == CHIP_NUM_5709 &&
7610 (CHIP_REV(bp) == CHIP_REV_Ax ||
7611 CHIP_REV(bp) == CHIP_REV_Bx))
583c28e5 7612 bp->phy_flags |= BNX2_PHY_FLAG_DIS_EARLY_DAC;
b6016b76 7613
7c62e83b
MC		 7614 bnx2_init_fw_cap(bp);
7615
16088272
MC		 7616 if ((CHIP_ID(bp) == CHIP_ID_5708_A0) ||
7617 (CHIP_ID(bp) == CHIP_ID_5708_B0) ||
846f5c62 7618 (CHIP_ID(bp) == CHIP_ID_5708_B1)) {
f86e82fb 7619 bp->flags |= BNX2_FLAG_NO_WOL;
846f5c62
MC		 7620 bp->wol = 0;
7621 }
dda1e390 7622
b6016b76
MC		 7623 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
7624 bp->tx_quick_cons_trip_int =
7625 bp->tx_quick_cons_trip;
7626 bp->tx_ticks_int = bp->tx_ticks;
7627 bp->rx_quick_cons_trip_int =
7628 bp->rx_quick_cons_trip;
7629 bp->rx_ticks_int = bp->rx_ticks;
7630 bp->comp_prod_trip_int = bp->comp_prod_trip;
7631 bp->com_ticks_int = bp->com_ticks;
7632 bp->cmd_ticks_int = bp->cmd_ticks;
7633 }
7634
f9317a40
MC		 7635 /* Disable MSI on 5706 if AMD 8132 bridge is found.
7636 *
7637 * MSI is defined to be 32-bit write. The 5706 does 64-bit MSI writes
7638 * with byte enables disabled on the unused 32-bit word. This is legal
7639 * but causes problems on the AMD 8132 which will eventually stop
7640 * responding after a while.
7641 *
7642 * AMD believes this incompatibility is unique to the 5706, and
88187dfa 7643 * prefers to locally disable MSI rather than globally disabling it.
f9317a40
MC		 7644 */
7645 if (CHIP_NUM(bp) == CHIP_NUM_5706 && disable_msi == 0) {
7646 struct pci_dev *amd_8132 = NULL;
7647
7648 while ((amd_8132 = pci_get_device(PCI_VENDOR_ID_AMD,
7649 PCI_DEVICE_ID_AMD_8132_BRIDGE,
7650 amd_8132))) {
f9317a40 7651
44c10138
AK		 7652 if (amd_8132->revision >= 0x10 &&
7653 amd_8132->revision <= 0x13) {
f9317a40
MC		 7654 disable_msi = 1;
7655 pci_dev_put(amd_8132);
7656 break;
7657 }
7658 }
7659 }
7660
deaf391b 7661 bnx2_set_default_link(bp);
b6016b76
MC		 7662 bp->req_flow_ctrl = FLOW_CTRL_RX | FLOW_CTRL_TX;
7663
cd339a0e 7664 init_timer(&bp->timer);
ac392abc 7665 bp->timer.expires = RUN_AT(BNX2_TIMER_INTERVAL);
cd339a0e
MC		 7666 bp->timer.data = (unsigned long) bp;
7667 bp->timer.function = bnx2_timer;
7668
b6016b76
MC		 7669 return 0;
7670
7671err_out_unmap:
7672 if (bp->regview) {
7673 iounmap(bp->regview);
73eef4cd 7674 bp->regview = NULL;
b6016b76
MC		 7675 }
7676
7677err_out_release:
7678 pci_release_regions(pdev);
7679
7680err_out_disable:
7681 pci_disable_device(pdev);
7682 pci_set_drvdata(pdev, NULL);
7683
7684err_out:
7685 return rc;
7686}
7687
883e5151
MC		 7688static char * __devinit
7689bnx2_bus_string(struct bnx2 *bp, char *str)
7690{
7691 char *s = str;
7692
f86e82fb 7693 if (bp->flags & BNX2_FLAG_PCIE) {
883e5151
MC		 7694 s += sprintf(s, "PCI Express");
7695 } else {
7696 s += sprintf(s, "PCI");
f86e82fb 7697 if (bp->flags & BNX2_FLAG_PCIX)
883e5151 7698 s += sprintf(s, "-X");
f86e82fb 7699 if (bp->flags & BNX2_FLAG_PCI_32BIT)
883e5151
MC		 7700 s += sprintf(s, " 32-bit");
7701 else
7702 s += sprintf(s, " 64-bit");
7703 s += sprintf(s, " %dMHz", bp->bus_speed_mhz);
7704 }
7705 return str;
7706}
7707
2ba582b7 7708static void __devinit
35efa7c1
MC		 7709bnx2_init_napi(struct bnx2 *bp)
7710{
b4b36042 7711 int i;
35efa7c1 7712
b4b36042 7713 for (i = 0; i < BNX2_MAX_MSIX_VEC; i++) {
35e9010b
MC		 7714 struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
7715 int (*poll)(struct napi_struct *, int);
7716
7717 if (i == 0)
7718 poll = bnx2_poll;
7719 else
f0ea2e63 7720 poll = bnx2_poll_msix;
35e9010b
MC		 7721
7722 netif_napi_add(bp->dev, &bp->bnx2_napi[i].napi, poll, 64);
b4b36042
MC		 7723 bnapi->bp = bp;
7724 }
35efa7c1
MC		 7725}
7726
b6016b76
MC		 7727static int __devinit
7728bnx2_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
7729{
7730 static int version_printed = 0;
7731 struct net_device *dev = NULL;
7732 struct bnx2 *bp;
0795af57 7733 int rc;
883e5151 7734 char str[40];
0795af57 7735 DECLARE_MAC_BUF(mac);
b6016b76
MC		 7736
7737 if (version_printed++ == 0)
7738 printk(KERN_INFO "%s", version);
7739
7740 /* dev zeroed in init_etherdev */
706bf240 7741 dev = alloc_etherdev_mq(sizeof(*bp), TX_MAX_RINGS);
b6016b76
MC		 7742
7743 if (!dev)
7744 return -ENOMEM;
7745
7746 rc = bnx2_init_board(pdev, dev);
7747 if (rc < 0) {
7748 free_netdev(dev);
7749 return rc;
7750 }
7751
7752 dev->open = bnx2_open;
7753 dev->hard_start_xmit = bnx2_start_xmit;
7754 dev->stop = bnx2_close;
7755 dev->get_stats = bnx2_get_stats;
5fcaed01 7756 dev->set_rx_mode = bnx2_set_rx_mode;
b6016b76
MC		 7757 dev->do_ioctl = bnx2_ioctl;
7758 dev->set_mac_address = bnx2_change_mac_addr;
7759 dev->change_mtu = bnx2_change_mtu;
7760 dev->tx_timeout = bnx2_tx_timeout;
7761 dev->watchdog_timeo = TX_TIMEOUT;
7762#ifdef BCM_VLAN
7763 dev->vlan_rx_register = bnx2_vlan_rx_register;
b6016b76 7764#endif
b6016b76 7765 dev->ethtool_ops = &bnx2_ethtool_ops;
b6016b76 7766
972ec0d4 7767 bp = netdev_priv(dev);
35efa7c1 7768 bnx2_init_napi(bp);
b6016b76
MC		 7769
7770#if defined(HAVE_POLL_CONTROLLER) || defined(CONFIG_NET_POLL_CONTROLLER)
7771 dev->poll_controller = poll_bnx2;
7772#endif
7773
1b2f922f
MC		 7774 pci_set_drvdata(pdev, dev);
7775
7776 memcpy(dev->dev_addr, bp->mac_addr, 6);
7777 memcpy(dev->perm_addr, bp->mac_addr, 6);
1b2f922f 7778
d212f87b 7779 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
4666f87a 7780 if (CHIP_NUM(bp) == CHIP_NUM_5709)
d212f87b
SH		 7781 dev->features |= NETIF_F_IPV6_CSUM;
7782
1b2f922f
MC		 7783#ifdef BCM_VLAN
7784 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
7785#endif
7786 dev->features |= NETIF_F_TSO | NETIF_F_TSO_ECN;
4666f87a
MC		 7787 if (CHIP_NUM(bp) == CHIP_NUM_5709)
7788 dev->features |= NETIF_F_TSO6;
1b2f922f 7789
b6016b76 7790 if ((rc = register_netdev(dev))) {
9b91cf9d 7791 dev_err(&pdev->dev, "Cannot register net device\n");
b6016b76
MC		 7792 if (bp->regview)
7793 iounmap(bp->regview);
7794 pci_release_regions(pdev);
7795 pci_disable_device(pdev);
7796 pci_set_drvdata(pdev, NULL);
7797 free_netdev(dev);
7798 return rc;
7799 }
7800
883e5151 7801 printk(KERN_INFO "%s: %s (%c%d) %s found at mem %lx, "
0795af57 7802 "IRQ %d, node addr %s\n",
b6016b76 7803 dev->name,
fbbf68b7 7804 board_info[ent->driver_data].name,
b6016b76
MC		 7805 ((CHIP_ID(bp) & 0xf000) >> 12) + 'A',
7806 ((CHIP_ID(bp) & 0x0ff0) >> 4),
883e5151 7807 bnx2_bus_string(bp, str),
b6016b76 7808 dev->base_addr,
0795af57 7809 bp->pdev->irq, print_mac(mac, dev->dev_addr));
b6016b76 7810
b6016b76
MC		 7811 return 0;
7812}
7813
7814static void __devexit
7815bnx2_remove_one(struct pci_dev *pdev)
7816{
7817 struct net_device *dev = pci_get_drvdata(pdev);
972ec0d4 7818 struct bnx2 *bp = netdev_priv(dev);
b6016b76 7819
afdc08b9
MC		 7820 flush_scheduled_work();
7821
b6016b76
MC		 7822 unregister_netdev(dev);
7823
7824 if (bp->regview)
7825 iounmap(bp->regview);
7826
7827 free_netdev(dev);
7828 pci_release_regions(pdev);
7829 pci_disable_device(pdev);
7830 pci_set_drvdata(pdev, NULL);
7831}
7832
7833static int
829ca9a3 7834bnx2_suspend(struct pci_dev *pdev, pm_message_t state)
b6016b76
MC		 7835{
7836 struct net_device *dev = pci_get_drvdata(pdev);
972ec0d4 7837 struct bnx2 *bp = netdev_priv(dev);
b6016b76 7838
6caebb02
MC		 7839 /* PCI register 4 needs to be saved whether netif_running() or not.
7840 * MSI address and data need to be saved if using MSI and
7841 * netif_running().
7842 */
7843 pci_save_state(pdev);
b6016b76
MC		 7844 if (!netif_running(dev))
7845 return 0;
7846
1d60290f 7847 flush_scheduled_work();
b6016b76
MC		 7848 bnx2_netif_stop(bp);
7849 netif_device_detach(dev);
7850 del_timer_sync(&bp->timer);
74bf4ba3 7851 bnx2_shutdown_chip(bp);
b6016b76 7852 bnx2_free_skbs(bp);
829ca9a3 7853 bnx2_set_power_state(bp, pci_choose_state(pdev, state));
b6016b76
MC		 7854 return 0;
7855}
7856
7857static int
7858bnx2_resume(struct pci_dev *pdev)
7859{
7860 struct net_device *dev = pci_get_drvdata(pdev);
972ec0d4 7861 struct bnx2 *bp = netdev_priv(dev);
b6016b76 7862
6caebb02 7863 pci_restore_state(pdev);
b6016b76
MC		 7864 if (!netif_running(dev))
7865 return 0;
7866
829ca9a3 7867 bnx2_set_power_state(bp, PCI_D0);
b6016b76 7868 netif_device_attach(dev);
9a120bc5 7869 bnx2_init_nic(bp, 1);
b6016b76
MC		 7870 bnx2_netif_start(bp);
7871 return 0;
7872}
7873
6ff2da49
WX		 7874/**
7875 * bnx2_io_error_detected - called when PCI error is detected
7876 * @pdev: Pointer to PCI device
7877 * @state: The current pci connection state
7878 *
7879 * This function is called after a PCI bus error affecting
7880 * this device has been detected.
7881 */
7882static pci_ers_result_t bnx2_io_error_detected(struct pci_dev *pdev,
7883 pci_channel_state_t state)
7884{
7885 struct net_device *dev = pci_get_drvdata(pdev);
7886 struct bnx2 *bp = netdev_priv(dev);
7887
7888 rtnl_lock();
7889 netif_device_detach(dev);
7890
7891 if (netif_running(dev)) {
7892 bnx2_netif_stop(bp);
7893 del_timer_sync(&bp->timer);
7894 bnx2_reset_nic(bp, BNX2_DRV_MSG_CODE_RESET);
7895 }
7896
7897 pci_disable_device(pdev);
7898 rtnl_unlock();
7899
7900 /* Request a slot slot reset. */
7901 return PCI_ERS_RESULT_NEED_RESET;
7902}
7903
7904/**
7905 * bnx2_io_slot_reset - called after the pci bus has been reset.
7906 * @pdev: Pointer to PCI device
7907 *
7908 * Restart the card from scratch, as if from a cold-boot.
7909 */
7910static pci_ers_result_t bnx2_io_slot_reset(struct pci_dev *pdev)
7911{
7912 struct net_device *dev = pci_get_drvdata(pdev);
7913 struct bnx2 *bp = netdev_priv(dev);
7914
7915 rtnl_lock();
7916 if (pci_enable_device(pdev)) {
7917 dev_err(&pdev->dev,
7918 "Cannot re-enable PCI device after reset.\n");
7919 rtnl_unlock();
7920 return PCI_ERS_RESULT_DISCONNECT;
7921 }
7922 pci_set_master(pdev);
7923 pci_restore_state(pdev);
7924
7925 if (netif_running(dev)) {
7926 bnx2_set_power_state(bp, PCI_D0);
7927 bnx2_init_nic(bp, 1);
7928 }
7929
7930 rtnl_unlock();
7931 return PCI_ERS_RESULT_RECOVERED;
7932}
7933
7934/**
7935 * bnx2_io_resume - called when traffic can start flowing again.
7936 * @pdev: Pointer to PCI device
7937 *
7938 * This callback is called when the error recovery driver tells us that
7939 * its OK to resume normal operation.
7940 */
7941static void bnx2_io_resume(struct pci_dev *pdev)
7942{
7943 struct net_device *dev = pci_get_drvdata(pdev);
7944 struct bnx2 *bp = netdev_priv(dev);
7945
7946 rtnl_lock();
7947 if (netif_running(dev))
7948 bnx2_netif_start(bp);
7949
7950 netif_device_attach(dev);
7951 rtnl_unlock();
7952}
7953
7954static struct pci_error_handlers bnx2_err_handler = {
7955 .error_detected = bnx2_io_error_detected,
7956 .slot_reset = bnx2_io_slot_reset,
7957 .resume = bnx2_io_resume,
7958};
7959
b6016b76 7960static struct pci_driver bnx2_pci_driver = {
14ab9b86
PH		 7961 .name = DRV_MODULE_NAME,
7962 .id_table = bnx2_pci_tbl,
7963 .probe = bnx2_init_one,
7964 .remove = __devexit_p(bnx2_remove_one),
7965 .suspend = bnx2_suspend,
7966 .resume = bnx2_resume,
6ff2da49 7967 .err_handler = &bnx2_err_handler,
b6016b76
MC		 7968};
7969
7970static int __init bnx2_init(void)
7971{
29917620 7972 return pci_register_driver(&bnx2_pci_driver);
b6016b76
MC		 7973}
7974
7975static void __exit bnx2_cleanup(void)
7976{
7977 pci_unregister_driver(&bnx2_pci_driver);
7978}
7979
7980module_init(bnx2_init);
7981module_exit(bnx2_cleanup);
7982
7983
7984
Linux kernel - Deliverables
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