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[BNX2]: Use netdev_priv()
[deliverable/linux.git] / drivers / net / bnx2.c
CommitLineData
b6016b76
MC		 1/* bnx2.c: Broadcom NX2 network driver.
2 *
3 * Copyright (c) 2004, 2005 Broadcom Corporation
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
8 *
9 * Written by: Michael Chan (mchan@broadcom.com)
10 */
11
12#include "bnx2.h"
13#include "bnx2_fw.h"
14
15#define DRV_MODULE_NAME "bnx2"
16#define PFX DRV_MODULE_NAME ": "
05d0f1cf
MC		 17#define DRV_MODULE_VERSION "1.4.30"
18#define DRV_MODULE_RELDATE "October 11, 2005"
b6016b76
MC		 19
20#define RUN_AT(x) (jiffies + (x))
21
22/* Time in jiffies before concluding the transmitter is hung. */
23#define TX_TIMEOUT (5*HZ)
24
25static char version[] __devinitdata =
26 "Broadcom NetXtreme II Gigabit Ethernet Driver " DRV_MODULE_NAME " v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
27
28MODULE_AUTHOR("Michael Chan <mchan@broadcom.com>");
05d0f1cf 29MODULE_DESCRIPTION("Broadcom NetXtreme II BCM5706/5708 Driver");
b6016b76
MC		 30MODULE_LICENSE("GPL");
31MODULE_VERSION(DRV_MODULE_VERSION);
32
33static int disable_msi = 0;
34
35module_param(disable_msi, int, 0);
36MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)");
37
38typedef enum {
39 BCM5706 = 0,
40 NC370T,
41 NC370I,
42 BCM5706S,
43 NC370F,
5b0c76ad
MC		 44 BCM5708,
45 BCM5708S,
b6016b76
MC		 46} board_t;
47
48/* indexed by board_t, above */
49static struct {
50 char *name;
51} board_info[] __devinitdata = {
52 { "Broadcom NetXtreme II BCM5706 1000Base-T" },
53 { "HP NC370T Multifunction Gigabit Server Adapter" },
54 { "HP NC370i Multifunction Gigabit Server Adapter" },
55 { "Broadcom NetXtreme II BCM5706 1000Base-SX" },
56 { "HP NC370F Multifunction Gigabit Server Adapter" },
5b0c76ad
MC		 57 { "Broadcom NetXtreme II BCM5708 1000Base-T" },
58 { "Broadcom NetXtreme II BCM5708 1000Base-SX" },
b6016b76
MC		 59 };
60
61static struct pci_device_id bnx2_pci_tbl[] = {
62 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706,
63 PCI_VENDOR_ID_HP, 0x3101, 0, 0, NC370T },
64 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706,
65 PCI_VENDOR_ID_HP, 0x3106, 0, 0, NC370I },
66 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706,
67 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5706 },
5b0c76ad
MC		 68 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5708,
69 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5708 },
b6016b76
MC		 70 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706S,
71 PCI_VENDOR_ID_HP, 0x3102, 0, 0, NC370F },
72 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706S,
73 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5706S },
5b0c76ad
MC		 74 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5708S,
75 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5708S },
b6016b76
MC		 76 { 0, }
77};
78
79static struct flash_spec flash_table[] =
80{
81 /* Slow EEPROM */
37137709 82 {0x00000000, 0x40830380, 0x009f0081, 0xa184a053, 0xaf000400,
b6016b76
MC		 83 1, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE,
84 SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE,
85 "EEPROM - slow"},
37137709
MC		 86 /* Expansion entry 0001 */
87 {0x08000002, 0x4b808201, 0x00050081, 0x03840253, 0xaf020406,
b6016b76 88 0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
37137709
MC		 89 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
90 "Entry 0001"},
b6016b76
MC		 91 /* Saifun SA25F010 (non-buffered flash) */
92 /* strap, cfg1, & write1 need updates */
37137709 93 {0x04000001, 0x47808201, 0x00050081, 0x03840253, 0xaf020406,
b6016b76
MC		 94 0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
95 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*2,
96 "Non-buffered flash (128kB)"},
97 /* Saifun SA25F020 (non-buffered flash) */
98 /* strap, cfg1, & write1 need updates */
37137709 99 {0x0c000003, 0x4f808201, 0x00050081, 0x03840253, 0xaf020406,
b6016b76
MC		 100 0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
101 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*4,
102 "Non-buffered flash (256kB)"},
37137709
MC		 103 /* Expansion entry 0100 */
104 {0x11000000, 0x53808201, 0x00050081, 0x03840253, 0xaf020406,
105 0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
106 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
107 "Entry 0100"},
108 /* Entry 0101: ST M45PE10 (non-buffered flash, TetonII B0) */
109 {0x19000002, 0x5b808201, 0x000500db, 0x03840253, 0xaf020406,
110 0, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE,
111 ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*2,
112 "Entry 0101: ST M45PE10 (128kB non-bufferred)"},
113 /* Entry 0110: ST M45PE20 (non-buffered flash)*/
114 {0x15000001, 0x57808201, 0x000500db, 0x03840253, 0xaf020406,
115 0, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE,
116 ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*4,
117 "Entry 0110: ST M45PE20 (256kB non-bufferred)"},
118 /* Saifun SA25F005 (non-buffered flash) */
119 /* strap, cfg1, & write1 need updates */
120 {0x1d000003, 0x5f808201, 0x00050081, 0x03840253, 0xaf020406,
121 0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
122 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE,
123 "Non-buffered flash (64kB)"},
124 /* Fast EEPROM */
125 {0x22000000, 0x62808380, 0x009f0081, 0xa184a053, 0xaf000400,
126 1, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE,
127 SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE,
128 "EEPROM - fast"},
129 /* Expansion entry 1001 */
130 {0x2a000002, 0x6b808201, 0x00050081, 0x03840253, 0xaf020406,
131 0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
132 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
133 "Entry 1001"},
134 /* Expansion entry 1010 */
135 {0x26000001, 0x67808201, 0x00050081, 0x03840253, 0xaf020406,
136 0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
137 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
138 "Entry 1010"},
139 /* ATMEL AT45DB011B (buffered flash) */
140 {0x2e000003, 0x6e808273, 0x00570081, 0x68848353, 0xaf000400,
141 1, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
142 BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE,
143 "Buffered flash (128kB)"},
144 /* Expansion entry 1100 */
145 {0x33000000, 0x73808201, 0x00050081, 0x03840253, 0xaf020406,
146 0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
147 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
148 "Entry 1100"},
149 /* Expansion entry 1101 */
150 {0x3b000002, 0x7b808201, 0x00050081, 0x03840253, 0xaf020406,
151 0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
152 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
153 "Entry 1101"},
154 /* Ateml Expansion entry 1110 */
155 {0x37000001, 0x76808273, 0x00570081, 0x68848353, 0xaf000400,
156 1, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
157 BUFFERED_FLASH_BYTE_ADDR_MASK, 0,
158 "Entry 1110 (Atmel)"},
159 /* ATMEL AT45DB021B (buffered flash) */
160 {0x3f000003, 0x7e808273, 0x00570081, 0x68848353, 0xaf000400,
161 1, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
162 BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE*2,
163 "Buffered flash (256kB)"},
b6016b76
MC		 164};
165
166MODULE_DEVICE_TABLE(pci, bnx2_pci_tbl);
167
e89bbf10
MC		 168static inline u32 bnx2_tx_avail(struct bnx2 *bp)
169{
170 u32 diff = TX_RING_IDX(bp->tx_prod) - TX_RING_IDX(bp->tx_cons);
171
172 if (diff > MAX_TX_DESC_CNT)
173 diff = (diff & MAX_TX_DESC_CNT) - 1;
174 return (bp->tx_ring_size - diff);
175}
176
b6016b76
MC		 177static u32
178bnx2_reg_rd_ind(struct bnx2 *bp, u32 offset)
179{
180 REG_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, offset);
181 return (REG_RD(bp, BNX2_PCICFG_REG_WINDOW));
182}
183
184static void
185bnx2_reg_wr_ind(struct bnx2 *bp, u32 offset, u32 val)
186{
187 REG_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, offset);
188 REG_WR(bp, BNX2_PCICFG_REG_WINDOW, val);
189}
190
191static void
192bnx2_ctx_wr(struct bnx2 *bp, u32 cid_addr, u32 offset, u32 val)
193{
194 offset += cid_addr;
195 REG_WR(bp, BNX2_CTX_DATA_ADR, offset);
196 REG_WR(bp, BNX2_CTX_DATA, val);
197}
198
199static int
200bnx2_read_phy(struct bnx2 *bp, u32 reg, u32 *val)
201{
202 u32 val1;
203 int i, ret;
204
205 if (bp->phy_flags & PHY_INT_MODE_AUTO_POLLING_FLAG) {
206 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
207 val1 &= ~BNX2_EMAC_MDIO_MODE_AUTO_POLL;
208
209 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
210 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
211
212 udelay(40);
213 }
214
215 val1 = (bp->phy_addr << 21) | (reg << 16) |
216 BNX2_EMAC_MDIO_COMM_COMMAND_READ | BNX2_EMAC_MDIO_COMM_DISEXT |
217 BNX2_EMAC_MDIO_COMM_START_BUSY;
218 REG_WR(bp, BNX2_EMAC_MDIO_COMM, val1);
219
220 for (i = 0; i < 50; i++) {
221 udelay(10);
222
223 val1 = REG_RD(bp, BNX2_EMAC_MDIO_COMM);
224 if (!(val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)) {
225 udelay(5);
226
227 val1 = REG_RD(bp, BNX2_EMAC_MDIO_COMM);
228 val1 &= BNX2_EMAC_MDIO_COMM_DATA;
229
230 break;
231 }
232 }
233
234 if (val1 & BNX2_EMAC_MDIO_COMM_START_BUSY) {
235 *val = 0x0;
236 ret = -EBUSY;
237 }
238 else {
239 *val = val1;
240 ret = 0;
241 }
242
243 if (bp->phy_flags & PHY_INT_MODE_AUTO_POLLING_FLAG) {
244 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
245 val1 |= BNX2_EMAC_MDIO_MODE_AUTO_POLL;
246
247 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
248 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
249
250 udelay(40);
251 }
252
253 return ret;
254}
255
256static int
257bnx2_write_phy(struct bnx2 *bp, u32 reg, u32 val)
258{
259 u32 val1;
260 int i, ret;
261
262 if (bp->phy_flags & PHY_INT_MODE_AUTO_POLLING_FLAG) {
263 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
264 val1 &= ~BNX2_EMAC_MDIO_MODE_AUTO_POLL;
265
266 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
267 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
268
269 udelay(40);
270 }
271
272 val1 = (bp->phy_addr << 21) | (reg << 16) | val |
273 BNX2_EMAC_MDIO_COMM_COMMAND_WRITE |
274 BNX2_EMAC_MDIO_COMM_START_BUSY | BNX2_EMAC_MDIO_COMM_DISEXT;
275 REG_WR(bp, BNX2_EMAC_MDIO_COMM, val1);
276
277 for (i = 0; i < 50; i++) {
278 udelay(10);
279
280 val1 = REG_RD(bp, BNX2_EMAC_MDIO_COMM);
281 if (!(val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)) {
282 udelay(5);
283 break;
284 }
285 }
286
287 if (val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)
288 ret = -EBUSY;
289 else
290 ret = 0;
291
292 if (bp->phy_flags & PHY_INT_MODE_AUTO_POLLING_FLAG) {
293 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
294 val1 |= BNX2_EMAC_MDIO_MODE_AUTO_POLL;
295
296 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
297 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
298
299 udelay(40);
300 }
301
302 return ret;
303}
304
305static void
306bnx2_disable_int(struct bnx2 *bp)
307{
308 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
309 BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
310 REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD);
311}
312
313static void
314bnx2_enable_int(struct bnx2 *bp)
315{
316 u32 val;
317
1269a8a6
MC		 318 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
319 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
320 BNX2_PCICFG_INT_ACK_CMD_MASK_INT | bp->last_status_idx);
321
b6016b76
MC		 322 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
323 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID | bp->last_status_idx);
324
325 val = REG_RD(bp, BNX2_HC_COMMAND);
326 REG_WR(bp, BNX2_HC_COMMAND, val | BNX2_HC_COMMAND_COAL_NOW);
327}
328
329static void
330bnx2_disable_int_sync(struct bnx2 *bp)
331{
332 atomic_inc(&bp->intr_sem);
333 bnx2_disable_int(bp);
334 synchronize_irq(bp->pdev->irq);
335}
336
337static void
338bnx2_netif_stop(struct bnx2 *bp)
339{
340 bnx2_disable_int_sync(bp);
341 if (netif_running(bp->dev)) {
342 netif_poll_disable(bp->dev);
343 netif_tx_disable(bp->dev);
344 bp->dev->trans_start = jiffies; /* prevent tx timeout */
345 }
346}
347
348static void
349bnx2_netif_start(struct bnx2 *bp)
350{
351 if (atomic_dec_and_test(&bp->intr_sem)) {
352 if (netif_running(bp->dev)) {
353 netif_wake_queue(bp->dev);
354 netif_poll_enable(bp->dev);
355 bnx2_enable_int(bp);
356 }
357 }
358}
359
360static void
361bnx2_free_mem(struct bnx2 *bp)
362{
363 if (bp->stats_blk) {
364 pci_free_consistent(bp->pdev, sizeof(struct statistics_block),
365 bp->stats_blk, bp->stats_blk_mapping);
366 bp->stats_blk = NULL;
367 }
368 if (bp->status_blk) {
369 pci_free_consistent(bp->pdev, sizeof(struct status_block),
370 bp->status_blk, bp->status_blk_mapping);
371 bp->status_blk = NULL;
372 }
373 if (bp->tx_desc_ring) {
374 pci_free_consistent(bp->pdev,
375 sizeof(struct tx_bd) * TX_DESC_CNT,
376 bp->tx_desc_ring, bp->tx_desc_mapping);
377 bp->tx_desc_ring = NULL;
378 }
b4558ea9
JJ		 379 kfree(bp->tx_buf_ring);
380 bp->tx_buf_ring = NULL;
b6016b76
MC		 381 if (bp->rx_desc_ring) {
382 pci_free_consistent(bp->pdev,
383 sizeof(struct rx_bd) * RX_DESC_CNT,
384 bp->rx_desc_ring, bp->rx_desc_mapping);
385 bp->rx_desc_ring = NULL;
386 }
b4558ea9
JJ		 387 kfree(bp->rx_buf_ring);
388 bp->rx_buf_ring = NULL;
b6016b76
MC		 389}
390
391static int
392bnx2_alloc_mem(struct bnx2 *bp)
393{
394 bp->tx_buf_ring = kmalloc(sizeof(struct sw_bd) * TX_DESC_CNT,
395 GFP_KERNEL);
396 if (bp->tx_buf_ring == NULL)
397 return -ENOMEM;
398
399 memset(bp->tx_buf_ring, 0, sizeof(struct sw_bd) * TX_DESC_CNT);
400 bp->tx_desc_ring = pci_alloc_consistent(bp->pdev,
401 sizeof(struct tx_bd) *
402 TX_DESC_CNT,
403 &bp->tx_desc_mapping);
404 if (bp->tx_desc_ring == NULL)
405 goto alloc_mem_err;
406
407 bp->rx_buf_ring = kmalloc(sizeof(struct sw_bd) * RX_DESC_CNT,
408 GFP_KERNEL);
409 if (bp->rx_buf_ring == NULL)
410 goto alloc_mem_err;
411
412 memset(bp->rx_buf_ring, 0, sizeof(struct sw_bd) * RX_DESC_CNT);
413 bp->rx_desc_ring = pci_alloc_consistent(bp->pdev,
414 sizeof(struct rx_bd) *
415 RX_DESC_CNT,
416 &bp->rx_desc_mapping);
417 if (bp->rx_desc_ring == NULL)
418 goto alloc_mem_err;
419
420 bp->status_blk = pci_alloc_consistent(bp->pdev,
421 sizeof(struct status_block),
422 &bp->status_blk_mapping);
423 if (bp->status_blk == NULL)
424 goto alloc_mem_err;
425
426 memset(bp->status_blk, 0, sizeof(struct status_block));
427
428 bp->stats_blk = pci_alloc_consistent(bp->pdev,
429 sizeof(struct statistics_block),
430 &bp->stats_blk_mapping);
431 if (bp->stats_blk == NULL)
432 goto alloc_mem_err;
433
434 memset(bp->stats_blk, 0, sizeof(struct statistics_block));
435
436 return 0;
437
438alloc_mem_err:
439 bnx2_free_mem(bp);
440 return -ENOMEM;
441}
442
e3648b3d
MC		 443static void
444bnx2_report_fw_link(struct bnx2 *bp)
445{
446 u32 fw_link_status = 0;
447
448 if (bp->link_up) {
449 u32 bmsr;
450
451 switch (bp->line_speed) {
452 case SPEED_10:
453 if (bp->duplex == DUPLEX_HALF)
454 fw_link_status = BNX2_LINK_STATUS_10HALF;
455 else
456 fw_link_status = BNX2_LINK_STATUS_10FULL;
457 break;
458 case SPEED_100:
459 if (bp->duplex == DUPLEX_HALF)
460 fw_link_status = BNX2_LINK_STATUS_100HALF;
461 else
462 fw_link_status = BNX2_LINK_STATUS_100FULL;
463 break;
464 case SPEED_1000:
465 if (bp->duplex == DUPLEX_HALF)
466 fw_link_status = BNX2_LINK_STATUS_1000HALF;
467 else
468 fw_link_status = BNX2_LINK_STATUS_1000FULL;
469 break;
470 case SPEED_2500:
471 if (bp->duplex == DUPLEX_HALF)
472 fw_link_status = BNX2_LINK_STATUS_2500HALF;
473 else
474 fw_link_status = BNX2_LINK_STATUS_2500FULL;
475 break;
476 }
477
478 fw_link_status |= BNX2_LINK_STATUS_LINK_UP;
479
480 if (bp->autoneg) {
481 fw_link_status |= BNX2_LINK_STATUS_AN_ENABLED;
482
483 bnx2_read_phy(bp, MII_BMSR, &bmsr);
484 bnx2_read_phy(bp, MII_BMSR, &bmsr);
485
486 if (!(bmsr & BMSR_ANEGCOMPLETE) ||
487 bp->phy_flags & PHY_PARALLEL_DETECT_FLAG)
488 fw_link_status |= BNX2_LINK_STATUS_PARALLEL_DET;
489 else
490 fw_link_status |= BNX2_LINK_STATUS_AN_COMPLETE;
491 }
492 }
493 else
494 fw_link_status = BNX2_LINK_STATUS_LINK_DOWN;
495
496 REG_WR_IND(bp, bp->shmem_base + BNX2_LINK_STATUS, fw_link_status);
497}
498
b6016b76
MC		 499static void
500bnx2_report_link(struct bnx2 *bp)
501{
502 if (bp->link_up) {
503 netif_carrier_on(bp->dev);
504 printk(KERN_INFO PFX "%s NIC Link is Up, ", bp->dev->name);
505
506 printk("%d Mbps ", bp->line_speed);
507
508 if (bp->duplex == DUPLEX_FULL)
509 printk("full duplex");
510 else
511 printk("half duplex");
512
513 if (bp->flow_ctrl) {
514 if (bp->flow_ctrl & FLOW_CTRL_RX) {
515 printk(", receive ");
516 if (bp->flow_ctrl & FLOW_CTRL_TX)
517 printk("& transmit ");
518 }
519 else {
520 printk(", transmit ");
521 }
522 printk("flow control ON");
523 }
524 printk("\n");
525 }
526 else {
527 netif_carrier_off(bp->dev);
528 printk(KERN_ERR PFX "%s NIC Link is Down\n", bp->dev->name);
529 }
e3648b3d
MC		 530
531 bnx2_report_fw_link(bp);
b6016b76
MC		 532}
533
534static void
535bnx2_resolve_flow_ctrl(struct bnx2 *bp)
536{
537 u32 local_adv, remote_adv;
538
539 bp->flow_ctrl = 0;
540 if ((bp->autoneg & (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) !=
541 (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) {
542
543 if (bp->duplex == DUPLEX_FULL) {
544 bp->flow_ctrl = bp->req_flow_ctrl;
545 }
546 return;
547 }
548
549 if (bp->duplex != DUPLEX_FULL) {
550 return;
551 }
552
5b0c76ad
MC		 553 if ((bp->phy_flags & PHY_SERDES_FLAG) &&
554 (CHIP_NUM(bp) == CHIP_NUM_5708)) {
555 u32 val;
556
557 bnx2_read_phy(bp, BCM5708S_1000X_STAT1, &val);
558 if (val & BCM5708S_1000X_STAT1_TX_PAUSE)
559 bp->flow_ctrl |= FLOW_CTRL_TX;
560 if (val & BCM5708S_1000X_STAT1_RX_PAUSE)
561 bp->flow_ctrl |= FLOW_CTRL_RX;
562 return;
563 }
564
b6016b76
MC		 565 bnx2_read_phy(bp, MII_ADVERTISE, &local_adv);
566 bnx2_read_phy(bp, MII_LPA, &remote_adv);
567
568 if (bp->phy_flags & PHY_SERDES_FLAG) {
569 u32 new_local_adv = 0;
570 u32 new_remote_adv = 0;
571
572 if (local_adv & ADVERTISE_1000XPAUSE)
573 new_local_adv |= ADVERTISE_PAUSE_CAP;
574 if (local_adv & ADVERTISE_1000XPSE_ASYM)
575 new_local_adv |= ADVERTISE_PAUSE_ASYM;
576 if (remote_adv & ADVERTISE_1000XPAUSE)
577 new_remote_adv |= ADVERTISE_PAUSE_CAP;
578 if (remote_adv & ADVERTISE_1000XPSE_ASYM)
579 new_remote_adv |= ADVERTISE_PAUSE_ASYM;
580
581 local_adv = new_local_adv;
582 remote_adv = new_remote_adv;
583 }
584
585 /* See Table 28B-3 of 802.3ab-1999 spec. */
586 if (local_adv & ADVERTISE_PAUSE_CAP) {
587 if(local_adv & ADVERTISE_PAUSE_ASYM) {
588 if (remote_adv & ADVERTISE_PAUSE_CAP) {
589 bp->flow_ctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
590 }
591 else if (remote_adv & ADVERTISE_PAUSE_ASYM) {
592 bp->flow_ctrl = FLOW_CTRL_RX;
593 }
594 }
595 else {
596 if (remote_adv & ADVERTISE_PAUSE_CAP) {
597 bp->flow_ctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
598 }
599 }
600 }
601 else if (local_adv & ADVERTISE_PAUSE_ASYM) {
602 if ((remote_adv & ADVERTISE_PAUSE_CAP) &&
603 (remote_adv & ADVERTISE_PAUSE_ASYM)) {
604
605 bp->flow_ctrl = FLOW_CTRL_TX;
606 }
607 }
608}
609
610static int
5b0c76ad
MC		 611bnx2_5708s_linkup(struct bnx2 *bp)
612{
613 u32 val;
614
615 bp->link_up = 1;
616 bnx2_read_phy(bp, BCM5708S_1000X_STAT1, &val);
617 switch (val & BCM5708S_1000X_STAT1_SPEED_MASK) {
618 case BCM5708S_1000X_STAT1_SPEED_10:
619 bp->line_speed = SPEED_10;
620 break;
621 case BCM5708S_1000X_STAT1_SPEED_100:
622 bp->line_speed = SPEED_100;
623 break;
624 case BCM5708S_1000X_STAT1_SPEED_1G:
625 bp->line_speed = SPEED_1000;
626 break;
627 case BCM5708S_1000X_STAT1_SPEED_2G5:
628 bp->line_speed = SPEED_2500;
629 break;
630 }
631 if (val & BCM5708S_1000X_STAT1_FD)
632 bp->duplex = DUPLEX_FULL;
633 else
634 bp->duplex = DUPLEX_HALF;
635
636 return 0;
637}
638
639static int
640bnx2_5706s_linkup(struct bnx2 *bp)
b6016b76
MC		 641{
642 u32 bmcr, local_adv, remote_adv, common;
643
644 bp->link_up = 1;
645 bp->line_speed = SPEED_1000;
646
647 bnx2_read_phy(bp, MII_BMCR, &bmcr);
648 if (bmcr & BMCR_FULLDPLX) {
649 bp->duplex = DUPLEX_FULL;
650 }
651 else {
652 bp->duplex = DUPLEX_HALF;
653 }
654
655 if (!(bmcr & BMCR_ANENABLE)) {
656 return 0;
657 }
658
659 bnx2_read_phy(bp, MII_ADVERTISE, &local_adv);
660 bnx2_read_phy(bp, MII_LPA, &remote_adv);
661
662 common = local_adv & remote_adv;
663 if (common & (ADVERTISE_1000XHALF | ADVERTISE_1000XFULL)) {
664
665 if (common & ADVERTISE_1000XFULL) {
666 bp->duplex = DUPLEX_FULL;
667 }
668 else {
669 bp->duplex = DUPLEX_HALF;
670 }
671 }
672
673 return 0;
674}
675
676static int
677bnx2_copper_linkup(struct bnx2 *bp)
678{
679 u32 bmcr;
680
681 bnx2_read_phy(bp, MII_BMCR, &bmcr);
682 if (bmcr & BMCR_ANENABLE) {
683 u32 local_adv, remote_adv, common;
684
685 bnx2_read_phy(bp, MII_CTRL1000, &local_adv);
686 bnx2_read_phy(bp, MII_STAT1000, &remote_adv);
687
688 common = local_adv & (remote_adv >> 2);
689 if (common & ADVERTISE_1000FULL) {
690 bp->line_speed = SPEED_1000;
691 bp->duplex = DUPLEX_FULL;
692 }
693 else if (common & ADVERTISE_1000HALF) {
694 bp->line_speed = SPEED_1000;
695 bp->duplex = DUPLEX_HALF;
696 }
697 else {
698 bnx2_read_phy(bp, MII_ADVERTISE, &local_adv);
699 bnx2_read_phy(bp, MII_LPA, &remote_adv);
700
701 common = local_adv & remote_adv;
702 if (common & ADVERTISE_100FULL) {
703 bp->line_speed = SPEED_100;
704 bp->duplex = DUPLEX_FULL;
705 }
706 else if (common & ADVERTISE_100HALF) {
707 bp->line_speed = SPEED_100;
708 bp->duplex = DUPLEX_HALF;
709 }
710 else if (common & ADVERTISE_10FULL) {
711 bp->line_speed = SPEED_10;
712 bp->duplex = DUPLEX_FULL;
713 }
714 else if (common & ADVERTISE_10HALF) {
715 bp->line_speed = SPEED_10;
716 bp->duplex = DUPLEX_HALF;
717 }
718 else {
719 bp->line_speed = 0;
720 bp->link_up = 0;
721 }
722 }
723 }
724 else {
725 if (bmcr & BMCR_SPEED100) {
726 bp->line_speed = SPEED_100;
727 }
728 else {
729 bp->line_speed = SPEED_10;
730 }
731 if (bmcr & BMCR_FULLDPLX) {
732 bp->duplex = DUPLEX_FULL;
733 }
734 else {
735 bp->duplex = DUPLEX_HALF;
736 }
737 }
738
739 return 0;
740}
741
742static int
743bnx2_set_mac_link(struct bnx2 *bp)
744{
745 u32 val;
746
747 REG_WR(bp, BNX2_EMAC_TX_LENGTHS, 0x2620);
748 if (bp->link_up && (bp->line_speed == SPEED_1000) &&
749 (bp->duplex == DUPLEX_HALF)) {
750 REG_WR(bp, BNX2_EMAC_TX_LENGTHS, 0x26ff);
751 }
752
753 /* Configure the EMAC mode register. */
754 val = REG_RD(bp, BNX2_EMAC_MODE);
755
756 val &= ~(BNX2_EMAC_MODE_PORT | BNX2_EMAC_MODE_HALF_DUPLEX |
5b0c76ad
MC		 757 BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK |
758 BNX2_EMAC_MODE_25G);
b6016b76
MC		 759
760 if (bp->link_up) {
5b0c76ad
MC		 761 switch (bp->line_speed) {
762 case SPEED_10:
763 if (CHIP_NUM(bp) == CHIP_NUM_5708) {
764 val |= BNX2_EMAC_MODE_PORT_MII_10;
765 break;
766 }
767 /* fall through */
768 case SPEED_100:
769 val |= BNX2_EMAC_MODE_PORT_MII;
770 break;
771 case SPEED_2500:
772 val |= BNX2_EMAC_MODE_25G;
773 /* fall through */
774 case SPEED_1000:
775 val |= BNX2_EMAC_MODE_PORT_GMII;
776 break;
777 }
b6016b76
MC		 778 }
779 else {
780 val |= BNX2_EMAC_MODE_PORT_GMII;
781 }
782
783 /* Set the MAC to operate in the appropriate duplex mode. */
784 if (bp->duplex == DUPLEX_HALF)
785 val |= BNX2_EMAC_MODE_HALF_DUPLEX;
786 REG_WR(bp, BNX2_EMAC_MODE, val);
787
788 /* Enable/disable rx PAUSE. */
789 bp->rx_mode &= ~BNX2_EMAC_RX_MODE_FLOW_EN;
790
791 if (bp->flow_ctrl & FLOW_CTRL_RX)
792 bp->rx_mode |= BNX2_EMAC_RX_MODE_FLOW_EN;
793 REG_WR(bp, BNX2_EMAC_RX_MODE, bp->rx_mode);
794
795 /* Enable/disable tx PAUSE. */
796 val = REG_RD(bp, BNX2_EMAC_TX_MODE);
797 val &= ~BNX2_EMAC_TX_MODE_FLOW_EN;
798
799 if (bp->flow_ctrl & FLOW_CTRL_TX)
800 val |= BNX2_EMAC_TX_MODE_FLOW_EN;
801 REG_WR(bp, BNX2_EMAC_TX_MODE, val);
802
803 /* Acknowledge the interrupt. */
804 REG_WR(bp, BNX2_EMAC_STATUS, BNX2_EMAC_STATUS_LINK_CHANGE);
805
806 return 0;
807}
808
809static int
810bnx2_set_link(struct bnx2 *bp)
811{
812 u32 bmsr;
813 u8 link_up;
814
815 if (bp->loopback == MAC_LOOPBACK) {
816 bp->link_up = 1;
817 return 0;
818 }
819
820 link_up = bp->link_up;
821
822 bnx2_read_phy(bp, MII_BMSR, &bmsr);
823 bnx2_read_phy(bp, MII_BMSR, &bmsr);
824
825 if ((bp->phy_flags & PHY_SERDES_FLAG) &&
826 (CHIP_NUM(bp) == CHIP_NUM_5706)) {
827 u32 val;
828
829 val = REG_RD(bp, BNX2_EMAC_STATUS);
830 if (val & BNX2_EMAC_STATUS_LINK)
831 bmsr |= BMSR_LSTATUS;
832 else
833 bmsr &= ~BMSR_LSTATUS;
834 }
835
836 if (bmsr & BMSR_LSTATUS) {
837 bp->link_up = 1;
838
839 if (bp->phy_flags & PHY_SERDES_FLAG) {
5b0c76ad
MC		 840 if (CHIP_NUM(bp) == CHIP_NUM_5706)
841 bnx2_5706s_linkup(bp);
842 else if (CHIP_NUM(bp) == CHIP_NUM_5708)
843 bnx2_5708s_linkup(bp);
b6016b76
MC		 844 }
845 else {
846 bnx2_copper_linkup(bp);
847 }
848 bnx2_resolve_flow_ctrl(bp);
849 }
850 else {
851 if ((bp->phy_flags & PHY_SERDES_FLAG) &&
852 (bp->autoneg & AUTONEG_SPEED)) {
853
854 u32 bmcr;
855
856 bnx2_read_phy(bp, MII_BMCR, &bmcr);
857 if (!(bmcr & BMCR_ANENABLE)) {
858 bnx2_write_phy(bp, MII_BMCR, bmcr |
859 BMCR_ANENABLE);
860 }
861 }
862 bp->phy_flags &= ~PHY_PARALLEL_DETECT_FLAG;
863 bp->link_up = 0;
864 }
865
866 if (bp->link_up != link_up) {
867 bnx2_report_link(bp);
868 }
869
870 bnx2_set_mac_link(bp);
871
872 return 0;
873}
874
875static int
876bnx2_reset_phy(struct bnx2 *bp)
877{
878 int i;
879 u32 reg;
880
881 bnx2_write_phy(bp, MII_BMCR, BMCR_RESET);
882
883#define PHY_RESET_MAX_WAIT 100
884 for (i = 0; i < PHY_RESET_MAX_WAIT; i++) {
885 udelay(10);
886
887 bnx2_read_phy(bp, MII_BMCR, &reg);
888 if (!(reg & BMCR_RESET)) {
889 udelay(20);
890 break;
891 }
892 }
893 if (i == PHY_RESET_MAX_WAIT) {
894 return -EBUSY;
895 }
896 return 0;
897}
898
899static u32
900bnx2_phy_get_pause_adv(struct bnx2 *bp)
901{
902 u32 adv = 0;
903
904 if ((bp->req_flow_ctrl & (FLOW_CTRL_RX | FLOW_CTRL_TX)) ==
905 (FLOW_CTRL_RX | FLOW_CTRL_TX)) {
906
907 if (bp->phy_flags & PHY_SERDES_FLAG) {
908 adv = ADVERTISE_1000XPAUSE;
909 }
910 else {
911 adv = ADVERTISE_PAUSE_CAP;
912 }
913 }
914 else if (bp->req_flow_ctrl & FLOW_CTRL_TX) {
915 if (bp->phy_flags & PHY_SERDES_FLAG) {
916 adv = ADVERTISE_1000XPSE_ASYM;
917 }
918 else {
919 adv = ADVERTISE_PAUSE_ASYM;
920 }
921 }
922 else if (bp->req_flow_ctrl & FLOW_CTRL_RX) {
923 if (bp->phy_flags & PHY_SERDES_FLAG) {
924 adv = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
925 }
926 else {
927 adv = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
928 }
929 }
930 return adv;
931}
932
933static int
934bnx2_setup_serdes_phy(struct bnx2 *bp)
935{
5b0c76ad 936 u32 adv, bmcr, up1;
b6016b76
MC		 937 u32 new_adv = 0;
938
939 if (!(bp->autoneg & AUTONEG_SPEED)) {
940 u32 new_bmcr;
5b0c76ad
MC		 941 int force_link_down = 0;
942
943 if (CHIP_NUM(bp) == CHIP_NUM_5708) {
944 bnx2_read_phy(bp, BCM5708S_UP1, &up1);
945 if (up1 & BCM5708S_UP1_2G5) {
946 up1 &= ~BCM5708S_UP1_2G5;
947 bnx2_write_phy(bp, BCM5708S_UP1, up1);
948 force_link_down = 1;
949 }
950 }
951
952 bnx2_read_phy(bp, MII_ADVERTISE, &adv);
953 adv &= ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF);
b6016b76
MC		 954
955 bnx2_read_phy(bp, MII_BMCR, &bmcr);
956 new_bmcr = bmcr & ~BMCR_ANENABLE;
957 new_bmcr |= BMCR_SPEED1000;
958 if (bp->req_duplex == DUPLEX_FULL) {
5b0c76ad 959 adv |= ADVERTISE_1000XFULL;
b6016b76
MC		 960 new_bmcr |= BMCR_FULLDPLX;
961 }
962 else {
5b0c76ad 963 adv |= ADVERTISE_1000XHALF;
b6016b76
MC		 964 new_bmcr &= ~BMCR_FULLDPLX;
965 }
5b0c76ad 966 if ((new_bmcr != bmcr) || (force_link_down)) {
b6016b76
MC		 967 /* Force a link down visible on the other side */
968 if (bp->link_up) {
5b0c76ad
MC		 969 bnx2_write_phy(bp, MII_ADVERTISE, adv &
970 ~(ADVERTISE_1000XFULL |
971 ADVERTISE_1000XHALF));
b6016b76
MC		 972 bnx2_write_phy(bp, MII_BMCR, bmcr |
973 BMCR_ANRESTART | BMCR_ANENABLE);
974
975 bp->link_up = 0;
976 netif_carrier_off(bp->dev);
5b0c76ad 977 bnx2_write_phy(bp, MII_BMCR, new_bmcr);
b6016b76 978 }
5b0c76ad 979 bnx2_write_phy(bp, MII_ADVERTISE, adv);
b6016b76
MC		 980 bnx2_write_phy(bp, MII_BMCR, new_bmcr);
981 }
982 return 0;
983 }
984
5b0c76ad
MC		 985 if (bp->phy_flags & PHY_2_5G_CAPABLE_FLAG) {
986 bnx2_read_phy(bp, BCM5708S_UP1, &up1);
987 up1 |= BCM5708S_UP1_2G5;
988 bnx2_write_phy(bp, BCM5708S_UP1, up1);
989 }
990
b6016b76
MC		 991 if (bp->advertising & ADVERTISED_1000baseT_Full)
992 new_adv |= ADVERTISE_1000XFULL;
993
994 new_adv |= bnx2_phy_get_pause_adv(bp);
995
996 bnx2_read_phy(bp, MII_ADVERTISE, &adv);
997 bnx2_read_phy(bp, MII_BMCR, &bmcr);
998
999 bp->serdes_an_pending = 0;
1000 if ((adv != new_adv) || ((bmcr & BMCR_ANENABLE) == 0)) {
1001 /* Force a link down visible on the other side */
1002 if (bp->link_up) {
1003 int i;
1004
1005 bnx2_write_phy(bp, MII_BMCR, BMCR_LOOPBACK);
1006 for (i = 0; i < 110; i++) {
1007 udelay(100);
1008 }
1009 }
1010
1011 bnx2_write_phy(bp, MII_ADVERTISE, new_adv);
1012 bnx2_write_phy(bp, MII_BMCR, bmcr | BMCR_ANRESTART |
1013 BMCR_ANENABLE);
cd339a0e
MC		 1014 if (CHIP_NUM(bp) == CHIP_NUM_5706) {
1015 /* Speed up link-up time when the link partner
1016 * does not autonegotiate which is very common
1017 * in blade servers. Some blade servers use
1018 * IPMI for kerboard input and it's important
1019 * to minimize link disruptions. Autoneg. involves
1020 * exchanging base pages plus 3 next pages and
1021 * normally completes in about 120 msec.
1022 */
1023 bp->current_interval = SERDES_AN_TIMEOUT;
1024 bp->serdes_an_pending = 1;
1025 mod_timer(&bp->timer, jiffies + bp->current_interval);
1026 }
b6016b76
MC		 1027 }
1028
1029 return 0;
1030}
1031
1032#define ETHTOOL_ALL_FIBRE_SPEED \
1033 (ADVERTISED_1000baseT_Full)
1034
1035#define ETHTOOL_ALL_COPPER_SPEED \
1036 (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full | \
1037 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full | \
1038 ADVERTISED_1000baseT_Full)
1039
1040#define PHY_ALL_10_100_SPEED (ADVERTISE_10HALF | ADVERTISE_10FULL | \
1041 ADVERTISE_100HALF | ADVERTISE_100FULL | ADVERTISE_CSMA)
1042
1043#define PHY_ALL_1000_SPEED (ADVERTISE_1000HALF | ADVERTISE_1000FULL)
1044
1045static int
1046bnx2_setup_copper_phy(struct bnx2 *bp)
1047{
1048 u32 bmcr;
1049 u32 new_bmcr;
1050
1051 bnx2_read_phy(bp, MII_BMCR, &bmcr);
1052
1053 if (bp->autoneg & AUTONEG_SPEED) {
1054 u32 adv_reg, adv1000_reg;
1055 u32 new_adv_reg = 0;
1056 u32 new_adv1000_reg = 0;
1057
1058 bnx2_read_phy(bp, MII_ADVERTISE, &adv_reg);
1059 adv_reg &= (PHY_ALL_10_100_SPEED | ADVERTISE_PAUSE_CAP |
1060 ADVERTISE_PAUSE_ASYM);
1061
1062 bnx2_read_phy(bp, MII_CTRL1000, &adv1000_reg);
1063 adv1000_reg &= PHY_ALL_1000_SPEED;
1064
1065 if (bp->advertising & ADVERTISED_10baseT_Half)
1066 new_adv_reg |= ADVERTISE_10HALF;
1067 if (bp->advertising & ADVERTISED_10baseT_Full)
1068 new_adv_reg |= ADVERTISE_10FULL;
1069 if (bp->advertising & ADVERTISED_100baseT_Half)
1070 new_adv_reg |= ADVERTISE_100HALF;
1071 if (bp->advertising & ADVERTISED_100baseT_Full)
1072 new_adv_reg |= ADVERTISE_100FULL;
1073 if (bp->advertising & ADVERTISED_1000baseT_Full)
1074 new_adv1000_reg |= ADVERTISE_1000FULL;
1075
1076 new_adv_reg |= ADVERTISE_CSMA;
1077
1078 new_adv_reg |= bnx2_phy_get_pause_adv(bp);
1079
1080 if ((adv1000_reg != new_adv1000_reg) ||
1081 (adv_reg != new_adv_reg) ||
1082 ((bmcr & BMCR_ANENABLE) == 0)) {
1083
1084 bnx2_write_phy(bp, MII_ADVERTISE, new_adv_reg);
1085 bnx2_write_phy(bp, MII_CTRL1000, new_adv1000_reg);
1086 bnx2_write_phy(bp, MII_BMCR, BMCR_ANRESTART |
1087 BMCR_ANENABLE);
1088 }
1089 else if (bp->link_up) {
1090 /* Flow ctrl may have changed from auto to forced */
1091 /* or vice-versa. */
1092
1093 bnx2_resolve_flow_ctrl(bp);
1094 bnx2_set_mac_link(bp);
1095 }
1096 return 0;
1097 }
1098
1099 new_bmcr = 0;
1100 if (bp->req_line_speed == SPEED_100) {
1101 new_bmcr |= BMCR_SPEED100;
1102 }
1103 if (bp->req_duplex == DUPLEX_FULL) {
1104 new_bmcr |= BMCR_FULLDPLX;
1105 }
1106 if (new_bmcr != bmcr) {
1107 u32 bmsr;
1108 int i = 0;
1109
1110 bnx2_read_phy(bp, MII_BMSR, &bmsr);
1111 bnx2_read_phy(bp, MII_BMSR, &bmsr);
1112
1113 if (bmsr & BMSR_LSTATUS) {
1114 /* Force link down */
1115 bnx2_write_phy(bp, MII_BMCR, BMCR_LOOPBACK);
1116 do {
1117 udelay(100);
1118 bnx2_read_phy(bp, MII_BMSR, &bmsr);
1119 bnx2_read_phy(bp, MII_BMSR, &bmsr);
1120 i++;
1121 } while ((bmsr & BMSR_LSTATUS) && (i < 620));
1122 }
1123
1124 bnx2_write_phy(bp, MII_BMCR, new_bmcr);
1125
1126 /* Normally, the new speed is setup after the link has
1127 * gone down and up again. In some cases, link will not go
1128 * down so we need to set up the new speed here.
1129 */
1130 if (bmsr & BMSR_LSTATUS) {
1131 bp->line_speed = bp->req_line_speed;
1132 bp->duplex = bp->req_duplex;
1133 bnx2_resolve_flow_ctrl(bp);
1134 bnx2_set_mac_link(bp);
1135 }
1136 }
1137 return 0;
1138}
1139
1140static int
1141bnx2_setup_phy(struct bnx2 *bp)
1142{
1143 if (bp->loopback == MAC_LOOPBACK)
1144 return 0;
1145
1146 if (bp->phy_flags & PHY_SERDES_FLAG) {
1147 return (bnx2_setup_serdes_phy(bp));
1148 }
1149 else {
1150 return (bnx2_setup_copper_phy(bp));
1151 }
1152}
1153
1154static int
5b0c76ad
MC		 1155bnx2_init_5708s_phy(struct bnx2 *bp)
1156{
1157 u32 val;
1158
1159 bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG3);
1160 bnx2_write_phy(bp, BCM5708S_DIG_3_0, BCM5708S_DIG_3_0_USE_IEEE);
1161 bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG);
1162
1163 bnx2_read_phy(bp, BCM5708S_1000X_CTL1, &val);
1164 val |= BCM5708S_1000X_CTL1_FIBER_MODE | BCM5708S_1000X_CTL1_AUTODET_EN;
1165 bnx2_write_phy(bp, BCM5708S_1000X_CTL1, val);
1166
1167 bnx2_read_phy(bp, BCM5708S_1000X_CTL2, &val);
1168 val |= BCM5708S_1000X_CTL2_PLLEL_DET_EN;
1169 bnx2_write_phy(bp, BCM5708S_1000X_CTL2, val);
1170
1171 if (bp->phy_flags & PHY_2_5G_CAPABLE_FLAG) {
1172 bnx2_read_phy(bp, BCM5708S_UP1, &val);
1173 val |= BCM5708S_UP1_2G5;
1174 bnx2_write_phy(bp, BCM5708S_UP1, val);
1175 }
1176
1177 if ((CHIP_ID(bp) == CHIP_ID_5708_A0) ||
dda1e390
MC		 1178 (CHIP_ID(bp) == CHIP_ID_5708_B0) ||
1179 (CHIP_ID(bp) == CHIP_ID_5708_B1)) {
5b0c76ad
MC		 1180 /* increase tx signal amplitude */
1181 bnx2_write_phy(bp, BCM5708S_BLK_ADDR,
1182 BCM5708S_BLK_ADDR_TX_MISC);
1183 bnx2_read_phy(bp, BCM5708S_TX_ACTL1, &val);
1184 val &= ~BCM5708S_TX_ACTL1_DRIVER_VCM;
1185 bnx2_write_phy(bp, BCM5708S_TX_ACTL1, val);
1186 bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG);
1187 }
1188
e3648b3d 1189 val = REG_RD_IND(bp, bp->shmem_base + BNX2_PORT_HW_CFG_CONFIG) &
5b0c76ad
MC		 1190 BNX2_PORT_HW_CFG_CFG_TXCTL3_MASK;
1191
1192 if (val) {
1193 u32 is_backplane;
1194
e3648b3d 1195 is_backplane = REG_RD_IND(bp, bp->shmem_base +
5b0c76ad
MC		 1196 BNX2_SHARED_HW_CFG_CONFIG);
1197 if (is_backplane & BNX2_SHARED_HW_CFG_PHY_BACKPLANE) {
1198 bnx2_write_phy(bp, BCM5708S_BLK_ADDR,
1199 BCM5708S_BLK_ADDR_TX_MISC);
1200 bnx2_write_phy(bp, BCM5708S_TX_ACTL3, val);
1201 bnx2_write_phy(bp, BCM5708S_BLK_ADDR,
1202 BCM5708S_BLK_ADDR_DIG);
1203 }
1204 }
1205 return 0;
1206}
1207
1208static int
1209bnx2_init_5706s_phy(struct bnx2 *bp)
b6016b76
MC		 1210{
1211 bp->phy_flags &= ~PHY_PARALLEL_DETECT_FLAG;
1212
1213 if (CHIP_NUM(bp) == CHIP_NUM_5706) {
1214 REG_WR(bp, BNX2_MISC_UNUSED0, 0x300);
1215 }
1216
1217 if (bp->dev->mtu > 1500) {
1218 u32 val;
1219
1220 /* Set extended packet length bit */
1221 bnx2_write_phy(bp, 0x18, 0x7);
1222 bnx2_read_phy(bp, 0x18, &val);
1223 bnx2_write_phy(bp, 0x18, (val & 0xfff8) | 0x4000);
1224
1225 bnx2_write_phy(bp, 0x1c, 0x6c00);
1226 bnx2_read_phy(bp, 0x1c, &val);
1227 bnx2_write_phy(bp, 0x1c, (val & 0x3ff) | 0xec02);
1228 }
1229 else {
1230 u32 val;
1231
1232 bnx2_write_phy(bp, 0x18, 0x7);
1233 bnx2_read_phy(bp, 0x18, &val);
1234 bnx2_write_phy(bp, 0x18, val & ~0x4007);
1235
1236 bnx2_write_phy(bp, 0x1c, 0x6c00);
1237 bnx2_read_phy(bp, 0x1c, &val);
1238 bnx2_write_phy(bp, 0x1c, (val & 0x3fd) | 0xec00);
1239 }
1240
1241 return 0;
1242}
1243
1244static int
1245bnx2_init_copper_phy(struct bnx2 *bp)
1246{
5b0c76ad
MC		 1247 u32 val;
1248
b6016b76
MC		 1249 bp->phy_flags |= PHY_CRC_FIX_FLAG;
1250
1251 if (bp->phy_flags & PHY_CRC_FIX_FLAG) {
1252 bnx2_write_phy(bp, 0x18, 0x0c00);
1253 bnx2_write_phy(bp, 0x17, 0x000a);
1254 bnx2_write_phy(bp, 0x15, 0x310b);
1255 bnx2_write_phy(bp, 0x17, 0x201f);
1256 bnx2_write_phy(bp, 0x15, 0x9506);
1257 bnx2_write_phy(bp, 0x17, 0x401f);
1258 bnx2_write_phy(bp, 0x15, 0x14e2);
1259 bnx2_write_phy(bp, 0x18, 0x0400);
1260 }
1261
1262 if (bp->dev->mtu > 1500) {
b6016b76
MC		 1263 /* Set extended packet length bit */
1264 bnx2_write_phy(bp, 0x18, 0x7);
1265 bnx2_read_phy(bp, 0x18, &val);
1266 bnx2_write_phy(bp, 0x18, val | 0x4000);
1267
1268 bnx2_read_phy(bp, 0x10, &val);
1269 bnx2_write_phy(bp, 0x10, val | 0x1);
1270 }
1271 else {
b6016b76
MC		 1272 bnx2_write_phy(bp, 0x18, 0x7);
1273 bnx2_read_phy(bp, 0x18, &val);
1274 bnx2_write_phy(bp, 0x18, val & ~0x4007);
1275
1276 bnx2_read_phy(bp, 0x10, &val);
1277 bnx2_write_phy(bp, 0x10, val & ~0x1);
1278 }
1279
5b0c76ad
MC		 1280 /* ethernet@wirespeed */
1281 bnx2_write_phy(bp, 0x18, 0x7007);
1282 bnx2_read_phy(bp, 0x18, &val);
1283 bnx2_write_phy(bp, 0x18, val | (1 << 15) | (1 << 4));
b6016b76
MC		 1284 return 0;
1285}
1286
1287
1288static int
1289bnx2_init_phy(struct bnx2 *bp)
1290{
1291 u32 val;
1292 int rc = 0;
1293
1294 bp->phy_flags &= ~PHY_INT_MODE_MASK_FLAG;
1295 bp->phy_flags |= PHY_INT_MODE_LINK_READY_FLAG;
1296
1297 REG_WR(bp, BNX2_EMAC_ATTENTION_ENA, BNX2_EMAC_ATTENTION_ENA_LINK);
1298
1299 bnx2_reset_phy(bp);
1300
1301 bnx2_read_phy(bp, MII_PHYSID1, &val);
1302 bp->phy_id = val << 16;
1303 bnx2_read_phy(bp, MII_PHYSID2, &val);
1304 bp->phy_id |= val & 0xffff;
1305
1306 if (bp->phy_flags & PHY_SERDES_FLAG) {
5b0c76ad
MC		 1307 if (CHIP_NUM(bp) == CHIP_NUM_5706)
1308 rc = bnx2_init_5706s_phy(bp);
1309 else if (CHIP_NUM(bp) == CHIP_NUM_5708)
1310 rc = bnx2_init_5708s_phy(bp);
b6016b76
MC		 1311 }
1312 else {
1313 rc = bnx2_init_copper_phy(bp);
1314 }
1315
1316 bnx2_setup_phy(bp);
1317
1318 return rc;
1319}
1320
1321static int
1322bnx2_set_mac_loopback(struct bnx2 *bp)
1323{
1324 u32 mac_mode;
1325
1326 mac_mode = REG_RD(bp, BNX2_EMAC_MODE);
1327 mac_mode &= ~BNX2_EMAC_MODE_PORT;
1328 mac_mode |= BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK;
1329 REG_WR(bp, BNX2_EMAC_MODE, mac_mode);
1330 bp->link_up = 1;
1331 return 0;
1332}
1333
1334static int
b090ae2b 1335bnx2_fw_sync(struct bnx2 *bp, u32 msg_data, int silent)
b6016b76
MC		 1336{
1337 int i;
1338 u32 val;
1339
b6016b76
MC		 1340 bp->fw_wr_seq++;
1341 msg_data |= bp->fw_wr_seq;
1342
e3648b3d 1343 REG_WR_IND(bp, bp->shmem_base + BNX2_DRV_MB, msg_data);
b6016b76
MC		 1344
1345 /* wait for an acknowledgement. */
b090ae2b
MC		 1346 for (i = 0; i < (FW_ACK_TIME_OUT_MS / 10); i++) {
1347 msleep(10);
b6016b76 1348
e3648b3d 1349 val = REG_RD_IND(bp, bp->shmem_base + BNX2_FW_MB);
b6016b76
MC		 1350
1351 if ((val & BNX2_FW_MSG_ACK) == (msg_data & BNX2_DRV_MSG_SEQ))
1352 break;
1353 }
b090ae2b
MC		 1354 if ((msg_data & BNX2_DRV_MSG_DATA) == BNX2_DRV_MSG_DATA_WAIT0)
1355 return 0;
b6016b76
MC		 1356
1357 /* If we timed out, inform the firmware that this is the case. */
b090ae2b
MC		 1358 if ((val & BNX2_FW_MSG_ACK) != (msg_data & BNX2_DRV_MSG_SEQ)) {
1359 if (!silent)
1360 printk(KERN_ERR PFX "fw sync timeout, reset code = "
1361 "%x\n", msg_data);
b6016b76
MC		 1362
1363 msg_data &= ~BNX2_DRV_MSG_CODE;
1364 msg_data |= BNX2_DRV_MSG_CODE_FW_TIMEOUT;
1365
e3648b3d 1366 REG_WR_IND(bp, bp->shmem_base + BNX2_DRV_MB, msg_data);
b6016b76 1367
b6016b76
MC		 1368 return -EBUSY;
1369 }
1370
b090ae2b
MC		 1371 if ((val & BNX2_FW_MSG_STATUS_MASK) != BNX2_FW_MSG_STATUS_OK)
1372 return -EIO;
1373
b6016b76
MC		 1374 return 0;
1375}
1376
1377static void
1378bnx2_init_context(struct bnx2 *bp)
1379{
1380 u32 vcid;
1381
1382 vcid = 96;
1383 while (vcid) {
1384 u32 vcid_addr, pcid_addr, offset;
1385
1386 vcid--;
1387
1388 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
1389 u32 new_vcid;
1390
1391 vcid_addr = GET_PCID_ADDR(vcid);
1392 if (vcid & 0x8) {
1393 new_vcid = 0x60 + (vcid & 0xf0) + (vcid & 0x7);
1394 }
1395 else {
1396 new_vcid = vcid;
1397 }
1398 pcid_addr = GET_PCID_ADDR(new_vcid);
1399 }
1400 else {
1401 vcid_addr = GET_CID_ADDR(vcid);
1402 pcid_addr = vcid_addr;
1403 }
1404
1405 REG_WR(bp, BNX2_CTX_VIRT_ADDR, 0x00);
1406 REG_WR(bp, BNX2_CTX_PAGE_TBL, pcid_addr);
1407
1408 /* Zero out the context. */
1409 for (offset = 0; offset < PHY_CTX_SIZE; offset += 4) {
1410 CTX_WR(bp, 0x00, offset, 0);
1411 }
1412
1413 REG_WR(bp, BNX2_CTX_VIRT_ADDR, vcid_addr);
1414 REG_WR(bp, BNX2_CTX_PAGE_TBL, pcid_addr);
1415 }
1416}
1417
1418static int
1419bnx2_alloc_bad_rbuf(struct bnx2 *bp)
1420{
1421 u16 *good_mbuf;
1422 u32 good_mbuf_cnt;
1423 u32 val;
1424
1425 good_mbuf = kmalloc(512 * sizeof(u16), GFP_KERNEL);
1426 if (good_mbuf == NULL) {
1427 printk(KERN_ERR PFX "Failed to allocate memory in "
1428 "bnx2_alloc_bad_rbuf\n");
1429 return -ENOMEM;
1430 }
1431
1432 REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS,
1433 BNX2_MISC_ENABLE_SET_BITS_RX_MBUF_ENABLE);
1434
1435 good_mbuf_cnt = 0;
1436
1437 /* Allocate a bunch of mbufs and save the good ones in an array. */
1438 val = REG_RD_IND(bp, BNX2_RBUF_STATUS1);
1439 while (val & BNX2_RBUF_STATUS1_FREE_COUNT) {
1440 REG_WR_IND(bp, BNX2_RBUF_COMMAND, BNX2_RBUF_COMMAND_ALLOC_REQ);
1441
1442 val = REG_RD_IND(bp, BNX2_RBUF_FW_BUF_ALLOC);
1443
1444 val &= BNX2_RBUF_FW_BUF_ALLOC_VALUE;
1445
1446 /* The addresses with Bit 9 set are bad memory blocks. */
1447 if (!(val & (1 << 9))) {
1448 good_mbuf[good_mbuf_cnt] = (u16) val;
1449 good_mbuf_cnt++;
1450 }
1451
1452 val = REG_RD_IND(bp, BNX2_RBUF_STATUS1);
1453 }
1454
1455 /* Free the good ones back to the mbuf pool thus discarding
1456 * all the bad ones. */
1457 while (good_mbuf_cnt) {
1458 good_mbuf_cnt--;
1459
1460 val = good_mbuf[good_mbuf_cnt];
1461 val = (val << 9) | val | 1;
1462
1463 REG_WR_IND(bp, BNX2_RBUF_FW_BUF_FREE, val);
1464 }
1465 kfree(good_mbuf);
1466 return 0;
1467}
1468
1469static void
1470bnx2_set_mac_addr(struct bnx2 *bp)
1471{
1472 u32 val;
1473 u8 *mac_addr = bp->dev->dev_addr;
1474
1475 val = (mac_addr[0] << 8) | mac_addr[1];
1476
1477 REG_WR(bp, BNX2_EMAC_MAC_MATCH0, val);
1478
1479 val = (mac_addr[2] << 24) | (mac_addr[3] << 16) |
1480 (mac_addr[4] << 8) | mac_addr[5];
1481
1482 REG_WR(bp, BNX2_EMAC_MAC_MATCH1, val);
1483}
1484
1485static inline int
1486bnx2_alloc_rx_skb(struct bnx2 *bp, u16 index)
1487{
1488 struct sk_buff *skb;
1489 struct sw_bd *rx_buf = &bp->rx_buf_ring[index];
1490 dma_addr_t mapping;
1491 struct rx_bd *rxbd = &bp->rx_desc_ring[index];
1492 unsigned long align;
1493
1494 skb = dev_alloc_skb(bp->rx_buf_size);
1495 if (skb == NULL) {
1496 return -ENOMEM;
1497 }
1498
1499 if (unlikely((align = (unsigned long) skb->data & 0x7))) {
1500 skb_reserve(skb, 8 - align);
1501 }
1502
1503 skb->dev = bp->dev;
1504 mapping = pci_map_single(bp->pdev, skb->data, bp->rx_buf_use_size,
1505 PCI_DMA_FROMDEVICE);
1506
1507 rx_buf->skb = skb;
1508 pci_unmap_addr_set(rx_buf, mapping, mapping);
1509
1510 rxbd->rx_bd_haddr_hi = (u64) mapping >> 32;
1511 rxbd->rx_bd_haddr_lo = (u64) mapping & 0xffffffff;
1512
1513 bp->rx_prod_bseq += bp->rx_buf_use_size;
1514
1515 return 0;
1516}
1517
1518static void
1519bnx2_phy_int(struct bnx2 *bp)
1520{
1521 u32 new_link_state, old_link_state;
1522
1523 new_link_state = bp->status_blk->status_attn_bits &
1524 STATUS_ATTN_BITS_LINK_STATE;
1525 old_link_state = bp->status_blk->status_attn_bits_ack &
1526 STATUS_ATTN_BITS_LINK_STATE;
1527 if (new_link_state != old_link_state) {
1528 if (new_link_state) {
1529 REG_WR(bp, BNX2_PCICFG_STATUS_BIT_SET_CMD,
1530 STATUS_ATTN_BITS_LINK_STATE);
1531 }
1532 else {
1533 REG_WR(bp, BNX2_PCICFG_STATUS_BIT_CLEAR_CMD,
1534 STATUS_ATTN_BITS_LINK_STATE);
1535 }
1536 bnx2_set_link(bp);
1537 }
1538}
1539
1540static void
1541bnx2_tx_int(struct bnx2 *bp)
1542{
f4e418f7 1543 struct status_block *sblk = bp->status_blk;
b6016b76
MC		 1544 u16 hw_cons, sw_cons, sw_ring_cons;
1545 int tx_free_bd = 0;
1546
f4e418f7 1547 hw_cons = bp->hw_tx_cons = sblk->status_tx_quick_consumer_index0;
b6016b76
MC		 1548 if ((hw_cons & MAX_TX_DESC_CNT) == MAX_TX_DESC_CNT) {
1549 hw_cons++;
1550 }
1551 sw_cons = bp->tx_cons;
1552
1553 while (sw_cons != hw_cons) {
1554 struct sw_bd *tx_buf;
1555 struct sk_buff *skb;
1556 int i, last;
1557
1558 sw_ring_cons = TX_RING_IDX(sw_cons);
1559
1560 tx_buf = &bp->tx_buf_ring[sw_ring_cons];
1561 skb = tx_buf->skb;
1562#ifdef BCM_TSO
1563 /* partial BD completions possible with TSO packets */
1564 if (skb_shinfo(skb)->tso_size) {
1565 u16 last_idx, last_ring_idx;
1566
1567 last_idx = sw_cons +
1568 skb_shinfo(skb)->nr_frags + 1;
1569 last_ring_idx = sw_ring_cons +
1570 skb_shinfo(skb)->nr_frags + 1;
1571 if (unlikely(last_ring_idx >= MAX_TX_DESC_CNT)) {
1572 last_idx++;
1573 }
1574 if (((s16) ((s16) last_idx - (s16) hw_cons)) > 0) {
1575 break;
1576 }
1577 }
1578#endif
1579 pci_unmap_single(bp->pdev, pci_unmap_addr(tx_buf, mapping),
1580 skb_headlen(skb), PCI_DMA_TODEVICE);
1581
1582 tx_buf->skb = NULL;
1583 last = skb_shinfo(skb)->nr_frags;
1584
1585 for (i = 0; i < last; i++) {
1586 sw_cons = NEXT_TX_BD(sw_cons);
1587
1588 pci_unmap_page(bp->pdev,
1589 pci_unmap_addr(
1590 &bp->tx_buf_ring[TX_RING_IDX(sw_cons)],
1591 mapping),
1592 skb_shinfo(skb)->frags[i].size,
1593 PCI_DMA_TODEVICE);
1594 }
1595
1596 sw_cons = NEXT_TX_BD(sw_cons);
1597
1598 tx_free_bd += last + 1;
1599
1600 dev_kfree_skb_irq(skb);
1601
f4e418f7
MC		 1602 hw_cons = bp->hw_tx_cons =
1603 sblk->status_tx_quick_consumer_index0;
1604
b6016b76
MC		 1605 if ((hw_cons & MAX_TX_DESC_CNT) == MAX_TX_DESC_CNT) {
1606 hw_cons++;
1607 }
1608 }
1609
e89bbf10 1610 bp->tx_cons = sw_cons;
b6016b76
MC		 1611
1612 if (unlikely(netif_queue_stopped(bp->dev))) {
c770a65c 1613 spin_lock(&bp->tx_lock);
b6016b76 1614 if ((netif_queue_stopped(bp->dev)) &&
e89bbf10 1615 (bnx2_tx_avail(bp) > MAX_SKB_FRAGS)) {
b6016b76
MC		 1616
1617 netif_wake_queue(bp->dev);
1618 }
c770a65c 1619 spin_unlock(&bp->tx_lock);
b6016b76 1620 }
b6016b76
MC		 1621}
1622
1623static inline void
1624bnx2_reuse_rx_skb(struct bnx2 *bp, struct sk_buff *skb,
1625 u16 cons, u16 prod)
1626{
1627 struct sw_bd *cons_rx_buf = &bp->rx_buf_ring[cons];
1628 struct sw_bd *prod_rx_buf = &bp->rx_buf_ring[prod];
1629 struct rx_bd *cons_bd = &bp->rx_desc_ring[cons];
1630 struct rx_bd *prod_bd = &bp->rx_desc_ring[prod];
1631
1632 pci_dma_sync_single_for_device(bp->pdev,
1633 pci_unmap_addr(cons_rx_buf, mapping),
1634 bp->rx_offset + RX_COPY_THRESH, PCI_DMA_FROMDEVICE);
1635
1636 prod_rx_buf->skb = cons_rx_buf->skb;
1637 pci_unmap_addr_set(prod_rx_buf, mapping,
1638 pci_unmap_addr(cons_rx_buf, mapping));
1639
1640 memcpy(prod_bd, cons_bd, 8);
1641
1642 bp->rx_prod_bseq += bp->rx_buf_use_size;
1643
1644}
1645
1646static int
1647bnx2_rx_int(struct bnx2 *bp, int budget)
1648{
f4e418f7 1649 struct status_block *sblk = bp->status_blk;
b6016b76
MC		 1650 u16 hw_cons, sw_cons, sw_ring_cons, sw_prod, sw_ring_prod;
1651 struct l2_fhdr *rx_hdr;
1652 int rx_pkt = 0;
1653
f4e418f7 1654 hw_cons = bp->hw_rx_cons = sblk->status_rx_quick_consumer_index0;
b6016b76
MC		 1655 if ((hw_cons & MAX_RX_DESC_CNT) == MAX_RX_DESC_CNT) {
1656 hw_cons++;
1657 }
1658 sw_cons = bp->rx_cons;
1659 sw_prod = bp->rx_prod;
1660
1661 /* Memory barrier necessary as speculative reads of the rx
1662 * buffer can be ahead of the index in the status block
1663 */
1664 rmb();
1665 while (sw_cons != hw_cons) {
1666 unsigned int len;
ade2bfe7 1667 u32 status;
b6016b76
MC		 1668 struct sw_bd *rx_buf;
1669 struct sk_buff *skb;
1670
1671 sw_ring_cons = RX_RING_IDX(sw_cons);
1672 sw_ring_prod = RX_RING_IDX(sw_prod);
1673
1674 rx_buf = &bp->rx_buf_ring[sw_ring_cons];
1675 skb = rx_buf->skb;
1676 pci_dma_sync_single_for_cpu(bp->pdev,
1677 pci_unmap_addr(rx_buf, mapping),
1678 bp->rx_offset + RX_COPY_THRESH, PCI_DMA_FROMDEVICE);
1679
1680 rx_hdr = (struct l2_fhdr *) skb->data;
1681 len = rx_hdr->l2_fhdr_pkt_len - 4;
1682
ade2bfe7 1683 if ((status = rx_hdr->l2_fhdr_status) &
b6016b76
MC		 1684 (L2_FHDR_ERRORS_BAD_CRC |
1685 L2_FHDR_ERRORS_PHY_DECODE |
1686 L2_FHDR_ERRORS_ALIGNMENT |
1687 L2_FHDR_ERRORS_TOO_SHORT |
1688 L2_FHDR_ERRORS_GIANT_FRAME)) {
1689
1690 goto reuse_rx;
1691 }
1692
1693 /* Since we don't have a jumbo ring, copy small packets
1694 * if mtu > 1500
1695 */
1696 if ((bp->dev->mtu > 1500) && (len <= RX_COPY_THRESH)) {
1697 struct sk_buff *new_skb;
1698
1699 new_skb = dev_alloc_skb(len + 2);
1700 if (new_skb == NULL)
1701 goto reuse_rx;
1702
1703 /* aligned copy */
1704 memcpy(new_skb->data,
1705 skb->data + bp->rx_offset - 2,
1706 len + 2);
1707
1708 skb_reserve(new_skb, 2);
1709 skb_put(new_skb, len);
1710 new_skb->dev = bp->dev;
1711
1712 bnx2_reuse_rx_skb(bp, skb,
1713 sw_ring_cons, sw_ring_prod);
1714
1715 skb = new_skb;
1716 }
1717 else if (bnx2_alloc_rx_skb(bp, sw_ring_prod) == 0) {
1718 pci_unmap_single(bp->pdev,
1719 pci_unmap_addr(rx_buf, mapping),
1720 bp->rx_buf_use_size, PCI_DMA_FROMDEVICE);
1721
1722 skb_reserve(skb, bp->rx_offset);
1723 skb_put(skb, len);
1724 }
1725 else {
1726reuse_rx:
1727 bnx2_reuse_rx_skb(bp, skb,
1728 sw_ring_cons, sw_ring_prod);
1729 goto next_rx;
1730 }
1731
1732 skb->protocol = eth_type_trans(skb, bp->dev);
1733
1734 if ((len > (bp->dev->mtu + ETH_HLEN)) &&
1735 (htons(skb->protocol) != 0x8100)) {
1736
1737 dev_kfree_skb_irq(skb);
1738 goto next_rx;
1739
1740 }
1741
b6016b76
MC		 1742 skb->ip_summed = CHECKSUM_NONE;
1743 if (bp->rx_csum &&
1744 (status & (L2_FHDR_STATUS_TCP_SEGMENT |
1745 L2_FHDR_STATUS_UDP_DATAGRAM))) {
1746
ade2bfe7
MC		 1747 if (likely((status & (L2_FHDR_ERRORS_TCP_XSUM |
1748 L2_FHDR_ERRORS_UDP_XSUM)) == 0))
b6016b76
MC		 1749 skb->ip_summed = CHECKSUM_UNNECESSARY;
1750 }
1751
1752#ifdef BCM_VLAN
1753 if ((status & L2_FHDR_STATUS_L2_VLAN_TAG) && (bp->vlgrp != 0)) {
1754 vlan_hwaccel_receive_skb(skb, bp->vlgrp,
1755 rx_hdr->l2_fhdr_vlan_tag);
1756 }
1757 else
1758#endif
1759 netif_receive_skb(skb);
1760
1761 bp->dev->last_rx = jiffies;
1762 rx_pkt++;
1763
1764next_rx:
1765 rx_buf->skb = NULL;
1766
1767 sw_cons = NEXT_RX_BD(sw_cons);
1768 sw_prod = NEXT_RX_BD(sw_prod);
1769
1770 if ((rx_pkt == budget))
1771 break;
f4e418f7
MC		 1772
1773 /* Refresh hw_cons to see if there is new work */
1774 if (sw_cons == hw_cons) {
1775 hw_cons = bp->hw_rx_cons =
1776 sblk->status_rx_quick_consumer_index0;
1777 if ((hw_cons & MAX_RX_DESC_CNT) == MAX_RX_DESC_CNT)
1778 hw_cons++;
1779 rmb();
1780 }
b6016b76
MC		 1781 }
1782 bp->rx_cons = sw_cons;
1783 bp->rx_prod = sw_prod;
1784
1785 REG_WR16(bp, MB_RX_CID_ADDR + BNX2_L2CTX_HOST_BDIDX, sw_prod);
1786
1787 REG_WR(bp, MB_RX_CID_ADDR + BNX2_L2CTX_HOST_BSEQ, bp->rx_prod_bseq);
1788
1789 mmiowb();
1790
1791 return rx_pkt;
1792
1793}
1794
1795/* MSI ISR - The only difference between this and the INTx ISR
1796 * is that the MSI interrupt is always serviced.
1797 */
1798static irqreturn_t
1799bnx2_msi(int irq, void *dev_instance, struct pt_regs *regs)
1800{
1801 struct net_device *dev = dev_instance;
972ec0d4 1802 struct bnx2 *bp = netdev_priv(dev);
b6016b76 1803
c921e4c4 1804 prefetch(bp->status_blk);
b6016b76
MC		 1805 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
1806 BNX2_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM |
1807 BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
1808
1809 /* Return here if interrupt is disabled. */
73eef4cd
MC		 1810 if (unlikely(atomic_read(&bp->intr_sem) != 0))
1811 return IRQ_HANDLED;
b6016b76 1812
73eef4cd 1813 netif_rx_schedule(dev);
b6016b76 1814
73eef4cd 1815 return IRQ_HANDLED;
b6016b76
MC		 1816}
1817
1818static irqreturn_t
1819bnx2_interrupt(int irq, void *dev_instance, struct pt_regs *regs)
1820{
1821 struct net_device *dev = dev_instance;
972ec0d4 1822 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 1823
1824 /* When using INTx, it is possible for the interrupt to arrive
1825 * at the CPU before the status block posted prior to the
1826 * interrupt. Reading a register will flush the status block.
1827 * When using MSI, the MSI message will always complete after
1828 * the status block write.
1829 */
c921e4c4 1830 if ((bp->status_blk->status_idx == bp->last_status_idx) &&
b6016b76
MC		 1831 (REG_RD(bp, BNX2_PCICFG_MISC_STATUS) &
1832 BNX2_PCICFG_MISC_STATUS_INTA_VALUE))
73eef4cd 1833 return IRQ_NONE;
b6016b76
MC		 1834
1835 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
1836 BNX2_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM |
1837 BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
1838
1839 /* Return here if interrupt is shared and is disabled. */
73eef4cd
MC		 1840 if (unlikely(atomic_read(&bp->intr_sem) != 0))
1841 return IRQ_HANDLED;
b6016b76 1842
73eef4cd 1843 netif_rx_schedule(dev);
b6016b76 1844
73eef4cd 1845 return IRQ_HANDLED;
b6016b76
MC		 1846}
1847
f4e418f7
MC		 1848static inline int
1849bnx2_has_work(struct bnx2 *bp)
1850{
1851 struct status_block *sblk = bp->status_blk;
1852
1853 if ((sblk->status_rx_quick_consumer_index0 != bp->hw_rx_cons) ||
1854 (sblk->status_tx_quick_consumer_index0 != bp->hw_tx_cons))
1855 return 1;
1856
1857 if (((sblk->status_attn_bits & STATUS_ATTN_BITS_LINK_STATE) != 0) !=
1858 bp->link_up)
1859 return 1;
1860
1861 return 0;
1862}
1863
b6016b76
MC		 1864static int
1865bnx2_poll(struct net_device *dev, int *budget)
1866{
972ec0d4 1867 struct bnx2 *bp = netdev_priv(dev);
b6016b76 1868
b6016b76
MC		 1869 if ((bp->status_blk->status_attn_bits &
1870 STATUS_ATTN_BITS_LINK_STATE) !=
1871 (bp->status_blk->status_attn_bits_ack &
1872 STATUS_ATTN_BITS_LINK_STATE)) {
1873
c770a65c 1874 spin_lock(&bp->phy_lock);
b6016b76 1875 bnx2_phy_int(bp);
c770a65c 1876 spin_unlock(&bp->phy_lock);
b6016b76
MC		 1877 }
1878
f4e418f7 1879 if (bp->status_blk->status_tx_quick_consumer_index0 != bp->hw_tx_cons)
b6016b76 1880 bnx2_tx_int(bp);
b6016b76 1881
f4e418f7 1882 if (bp->status_blk->status_rx_quick_consumer_index0 != bp->hw_rx_cons) {
b6016b76
MC		 1883 int orig_budget = *budget;
1884 int work_done;
1885
1886 if (orig_budget > dev->quota)
1887 orig_budget = dev->quota;
1888
1889 work_done = bnx2_rx_int(bp, orig_budget);
1890 *budget -= work_done;
1891 dev->quota -= work_done;
b6016b76
MC		 1892 }
1893
f4e418f7
MC		 1894 bp->last_status_idx = bp->status_blk->status_idx;
1895 rmb();
1896
1897 if (!bnx2_has_work(bp)) {
b6016b76 1898 netif_rx_complete(dev);
1269a8a6
MC		 1899 if (likely(bp->flags & USING_MSI_FLAG)) {
1900 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
1901 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
1902 bp->last_status_idx);
1903 return 0;
1904 }
1905 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
1906 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
1907 BNX2_PCICFG_INT_ACK_CMD_MASK_INT |
1908 bp->last_status_idx);
1909
b6016b76 1910 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
1269a8a6
MC		 1911 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
1912 bp->last_status_idx);
b6016b76
MC		 1913 return 0;
1914 }
1915
1916 return 1;
1917}
1918
1919/* Called with rtnl_lock from vlan functions and also dev->xmit_lock
1920 * from set_multicast.
1921 */
1922static void
1923bnx2_set_rx_mode(struct net_device *dev)
1924{
972ec0d4 1925 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 1926 u32 rx_mode, sort_mode;
1927 int i;
b6016b76 1928
c770a65c 1929 spin_lock_bh(&bp->phy_lock);
b6016b76
MC		 1930
1931 rx_mode = bp->rx_mode & ~(BNX2_EMAC_RX_MODE_PROMISCUOUS |
1932 BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG);
1933 sort_mode = 1 | BNX2_RPM_SORT_USER0_BC_EN;
1934#ifdef BCM_VLAN
e29054f9 1935 if (!bp->vlgrp && !(bp->flags & ASF_ENABLE_FLAG))
b6016b76 1936 rx_mode |= BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG;
b6016b76 1937#else
e29054f9
MC		 1938 if (!(bp->flags & ASF_ENABLE_FLAG))
1939 rx_mode |= BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG;
b6016b76
MC		 1940#endif
1941 if (dev->flags & IFF_PROMISC) {
1942 /* Promiscuous mode. */
1943 rx_mode |= BNX2_EMAC_RX_MODE_PROMISCUOUS;
1944 sort_mode |= BNX2_RPM_SORT_USER0_PROM_EN;
1945 }
1946 else if (dev->flags & IFF_ALLMULTI) {
1947 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
1948 REG_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),
1949 0xffffffff);
1950 }
1951 sort_mode |= BNX2_RPM_SORT_USER0_MC_EN;
1952 }
1953 else {
1954 /* Accept one or more multicast(s). */
1955 struct dev_mc_list *mclist;
1956 u32 mc_filter[NUM_MC_HASH_REGISTERS];
1957 u32 regidx;
1958 u32 bit;
1959 u32 crc;
1960
1961 memset(mc_filter, 0, 4 * NUM_MC_HASH_REGISTERS);
1962
1963 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
1964 i++, mclist = mclist->next) {
1965
1966 crc = ether_crc_le(ETH_ALEN, mclist->dmi_addr);
1967 bit = crc & 0xff;
1968 regidx = (bit & 0xe0) >> 5;
1969 bit &= 0x1f;
1970 mc_filter[regidx] |= (1 << bit);
1971 }
1972
1973 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
1974 REG_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),
1975 mc_filter[i]);
1976 }
1977
1978 sort_mode |= BNX2_RPM_SORT_USER0_MC_HSH_EN;
1979 }
1980
1981 if (rx_mode != bp->rx_mode) {
1982 bp->rx_mode = rx_mode;
1983 REG_WR(bp, BNX2_EMAC_RX_MODE, rx_mode);
1984 }
1985
1986 REG_WR(bp, BNX2_RPM_SORT_USER0, 0x0);
1987 REG_WR(bp, BNX2_RPM_SORT_USER0, sort_mode);
1988 REG_WR(bp, BNX2_RPM_SORT_USER0, sort_mode | BNX2_RPM_SORT_USER0_ENA);
1989
c770a65c 1990 spin_unlock_bh(&bp->phy_lock);
b6016b76
MC		 1991}
1992
1993static void
1994load_rv2p_fw(struct bnx2 *bp, u32 *rv2p_code, u32 rv2p_code_len,
1995 u32 rv2p_proc)
1996{
1997 int i;
1998 u32 val;
1999
2000
2001 for (i = 0; i < rv2p_code_len; i += 8) {
2002 REG_WR(bp, BNX2_RV2P_INSTR_HIGH, *rv2p_code);
2003 rv2p_code++;
2004 REG_WR(bp, BNX2_RV2P_INSTR_LOW, *rv2p_code);
2005 rv2p_code++;
2006
2007 if (rv2p_proc == RV2P_PROC1) {
2008 val = (i / 8) | BNX2_RV2P_PROC1_ADDR_CMD_RDWR;
2009 REG_WR(bp, BNX2_RV2P_PROC1_ADDR_CMD, val);
2010 }
2011 else {
2012 val = (i / 8) | BNX2_RV2P_PROC2_ADDR_CMD_RDWR;
2013 REG_WR(bp, BNX2_RV2P_PROC2_ADDR_CMD, val);
2014 }
2015 }
2016
2017 /* Reset the processor, un-stall is done later. */
2018 if (rv2p_proc == RV2P_PROC1) {
2019 REG_WR(bp, BNX2_RV2P_COMMAND, BNX2_RV2P_COMMAND_PROC1_RESET);
2020 }
2021 else {
2022 REG_WR(bp, BNX2_RV2P_COMMAND, BNX2_RV2P_COMMAND_PROC2_RESET);
2023 }
2024}
2025
2026static void
2027load_cpu_fw(struct bnx2 *bp, struct cpu_reg *cpu_reg, struct fw_info *fw)
2028{
2029 u32 offset;
2030 u32 val;
2031
2032 /* Halt the CPU. */
2033 val = REG_RD_IND(bp, cpu_reg->mode);
2034 val |= cpu_reg->mode_value_halt;
2035 REG_WR_IND(bp, cpu_reg->mode, val);
2036 REG_WR_IND(bp, cpu_reg->state, cpu_reg->state_value_clear);
2037
2038 /* Load the Text area. */
2039 offset = cpu_reg->spad_base + (fw->text_addr - cpu_reg->mips_view_base);
2040 if (fw->text) {
2041 int j;
2042
2043 for (j = 0; j < (fw->text_len / 4); j++, offset += 4) {
2044 REG_WR_IND(bp, offset, fw->text[j]);
2045 }
2046 }
2047
2048 /* Load the Data area. */
2049 offset = cpu_reg->spad_base + (fw->data_addr - cpu_reg->mips_view_base);
2050 if (fw->data) {
2051 int j;
2052
2053 for (j = 0; j < (fw->data_len / 4); j++, offset += 4) {
2054 REG_WR_IND(bp, offset, fw->data[j]);
2055 }
2056 }
2057
2058 /* Load the SBSS area. */
2059 offset = cpu_reg->spad_base + (fw->sbss_addr - cpu_reg->mips_view_base);
2060 if (fw->sbss) {
2061 int j;
2062
2063 for (j = 0; j < (fw->sbss_len / 4); j++, offset += 4) {
2064 REG_WR_IND(bp, offset, fw->sbss[j]);
2065 }
2066 }
2067
2068 /* Load the BSS area. */
2069 offset = cpu_reg->spad_base + (fw->bss_addr - cpu_reg->mips_view_base);
2070 if (fw->bss) {
2071 int j;
2072
2073 for (j = 0; j < (fw->bss_len/4); j++, offset += 4) {
2074 REG_WR_IND(bp, offset, fw->bss[j]);
2075 }
2076 }
2077
2078 /* Load the Read-Only area. */
2079 offset = cpu_reg->spad_base +
2080 (fw->rodata_addr - cpu_reg->mips_view_base);
2081 if (fw->rodata) {
2082 int j;
2083
2084 for (j = 0; j < (fw->rodata_len / 4); j++, offset += 4) {
2085 REG_WR_IND(bp, offset, fw->rodata[j]);
2086 }
2087 }
2088
2089 /* Clear the pre-fetch instruction. */
2090 REG_WR_IND(bp, cpu_reg->inst, 0);
2091 REG_WR_IND(bp, cpu_reg->pc, fw->start_addr);
2092
2093 /* Start the CPU. */
2094 val = REG_RD_IND(bp, cpu_reg->mode);
2095 val &= ~cpu_reg->mode_value_halt;
2096 REG_WR_IND(bp, cpu_reg->state, cpu_reg->state_value_clear);
2097 REG_WR_IND(bp, cpu_reg->mode, val);
2098}
2099
2100static void
2101bnx2_init_cpus(struct bnx2 *bp)
2102{
2103 struct cpu_reg cpu_reg;
2104 struct fw_info fw;
2105
2106 /* Initialize the RV2P processor. */
2107 load_rv2p_fw(bp, bnx2_rv2p_proc1, sizeof(bnx2_rv2p_proc1), RV2P_PROC1);
2108 load_rv2p_fw(bp, bnx2_rv2p_proc2, sizeof(bnx2_rv2p_proc2), RV2P_PROC2);
2109
2110 /* Initialize the RX Processor. */
2111 cpu_reg.mode = BNX2_RXP_CPU_MODE;
2112 cpu_reg.mode_value_halt = BNX2_RXP_CPU_MODE_SOFT_HALT;
2113 cpu_reg.mode_value_sstep = BNX2_RXP_CPU_MODE_STEP_ENA;
2114 cpu_reg.state = BNX2_RXP_CPU_STATE;
2115 cpu_reg.state_value_clear = 0xffffff;
2116 cpu_reg.gpr0 = BNX2_RXP_CPU_REG_FILE;
2117 cpu_reg.evmask = BNX2_RXP_CPU_EVENT_MASK;
2118 cpu_reg.pc = BNX2_RXP_CPU_PROGRAM_COUNTER;
2119 cpu_reg.inst = BNX2_RXP_CPU_INSTRUCTION;
2120 cpu_reg.bp = BNX2_RXP_CPU_HW_BREAKPOINT;
2121 cpu_reg.spad_base = BNX2_RXP_SCRATCH;
2122 cpu_reg.mips_view_base = 0x8000000;
2123
2124 fw.ver_major = bnx2_RXP_b06FwReleaseMajor;
2125 fw.ver_minor = bnx2_RXP_b06FwReleaseMinor;
2126 fw.ver_fix = bnx2_RXP_b06FwReleaseFix;
2127 fw.start_addr = bnx2_RXP_b06FwStartAddr;
2128
2129 fw.text_addr = bnx2_RXP_b06FwTextAddr;
2130 fw.text_len = bnx2_RXP_b06FwTextLen;
2131 fw.text_index = 0;
2132 fw.text = bnx2_RXP_b06FwText;
2133
2134 fw.data_addr = bnx2_RXP_b06FwDataAddr;
2135 fw.data_len = bnx2_RXP_b06FwDataLen;
2136 fw.data_index = 0;
2137 fw.data = bnx2_RXP_b06FwData;
2138
2139 fw.sbss_addr = bnx2_RXP_b06FwSbssAddr;
2140 fw.sbss_len = bnx2_RXP_b06FwSbssLen;
2141 fw.sbss_index = 0;
2142 fw.sbss = bnx2_RXP_b06FwSbss;
2143
2144 fw.bss_addr = bnx2_RXP_b06FwBssAddr;
2145 fw.bss_len = bnx2_RXP_b06FwBssLen;
2146 fw.bss_index = 0;
2147 fw.bss = bnx2_RXP_b06FwBss;
2148
2149 fw.rodata_addr = bnx2_RXP_b06FwRodataAddr;
2150 fw.rodata_len = bnx2_RXP_b06FwRodataLen;
2151 fw.rodata_index = 0;
2152 fw.rodata = bnx2_RXP_b06FwRodata;
2153
2154 load_cpu_fw(bp, &cpu_reg, &fw);
2155
2156 /* Initialize the TX Processor. */
2157 cpu_reg.mode = BNX2_TXP_CPU_MODE;
2158 cpu_reg.mode_value_halt = BNX2_TXP_CPU_MODE_SOFT_HALT;
2159 cpu_reg.mode_value_sstep = BNX2_TXP_CPU_MODE_STEP_ENA;
2160 cpu_reg.state = BNX2_TXP_CPU_STATE;
2161 cpu_reg.state_value_clear = 0xffffff;
2162 cpu_reg.gpr0 = BNX2_TXP_CPU_REG_FILE;
2163 cpu_reg.evmask = BNX2_TXP_CPU_EVENT_MASK;
2164 cpu_reg.pc = BNX2_TXP_CPU_PROGRAM_COUNTER;
2165 cpu_reg.inst = BNX2_TXP_CPU_INSTRUCTION;
2166 cpu_reg.bp = BNX2_TXP_CPU_HW_BREAKPOINT;
2167 cpu_reg.spad_base = BNX2_TXP_SCRATCH;
2168 cpu_reg.mips_view_base = 0x8000000;
2169
2170 fw.ver_major = bnx2_TXP_b06FwReleaseMajor;
2171 fw.ver_minor = bnx2_TXP_b06FwReleaseMinor;
2172 fw.ver_fix = bnx2_TXP_b06FwReleaseFix;
2173 fw.start_addr = bnx2_TXP_b06FwStartAddr;
2174
2175 fw.text_addr = bnx2_TXP_b06FwTextAddr;
2176 fw.text_len = bnx2_TXP_b06FwTextLen;
2177 fw.text_index = 0;
2178 fw.text = bnx2_TXP_b06FwText;
2179
2180 fw.data_addr = bnx2_TXP_b06FwDataAddr;
2181 fw.data_len = bnx2_TXP_b06FwDataLen;
2182 fw.data_index = 0;
2183 fw.data = bnx2_TXP_b06FwData;
2184
2185 fw.sbss_addr = bnx2_TXP_b06FwSbssAddr;
2186 fw.sbss_len = bnx2_TXP_b06FwSbssLen;
2187 fw.sbss_index = 0;
2188 fw.sbss = bnx2_TXP_b06FwSbss;
2189
2190 fw.bss_addr = bnx2_TXP_b06FwBssAddr;
2191 fw.bss_len = bnx2_TXP_b06FwBssLen;
2192 fw.bss_index = 0;
2193 fw.bss = bnx2_TXP_b06FwBss;
2194
2195 fw.rodata_addr = bnx2_TXP_b06FwRodataAddr;
2196 fw.rodata_len = bnx2_TXP_b06FwRodataLen;
2197 fw.rodata_index = 0;
2198 fw.rodata = bnx2_TXP_b06FwRodata;
2199
2200 load_cpu_fw(bp, &cpu_reg, &fw);
2201
2202 /* Initialize the TX Patch-up Processor. */
2203 cpu_reg.mode = BNX2_TPAT_CPU_MODE;
2204 cpu_reg.mode_value_halt = BNX2_TPAT_CPU_MODE_SOFT_HALT;
2205 cpu_reg.mode_value_sstep = BNX2_TPAT_CPU_MODE_STEP_ENA;
2206 cpu_reg.state = BNX2_TPAT_CPU_STATE;
2207 cpu_reg.state_value_clear = 0xffffff;
2208 cpu_reg.gpr0 = BNX2_TPAT_CPU_REG_FILE;
2209 cpu_reg.evmask = BNX2_TPAT_CPU_EVENT_MASK;
2210 cpu_reg.pc = BNX2_TPAT_CPU_PROGRAM_COUNTER;
2211 cpu_reg.inst = BNX2_TPAT_CPU_INSTRUCTION;
2212 cpu_reg.bp = BNX2_TPAT_CPU_HW_BREAKPOINT;
2213 cpu_reg.spad_base = BNX2_TPAT_SCRATCH;
2214 cpu_reg.mips_view_base = 0x8000000;
2215
2216 fw.ver_major = bnx2_TPAT_b06FwReleaseMajor;
2217 fw.ver_minor = bnx2_TPAT_b06FwReleaseMinor;
2218 fw.ver_fix = bnx2_TPAT_b06FwReleaseFix;
2219 fw.start_addr = bnx2_TPAT_b06FwStartAddr;
2220
2221 fw.text_addr = bnx2_TPAT_b06FwTextAddr;
2222 fw.text_len = bnx2_TPAT_b06FwTextLen;
2223 fw.text_index = 0;
2224 fw.text = bnx2_TPAT_b06FwText;
2225
2226 fw.data_addr = bnx2_TPAT_b06FwDataAddr;
2227 fw.data_len = bnx2_TPAT_b06FwDataLen;
2228 fw.data_index = 0;
2229 fw.data = bnx2_TPAT_b06FwData;
2230
2231 fw.sbss_addr = bnx2_TPAT_b06FwSbssAddr;
2232 fw.sbss_len = bnx2_TPAT_b06FwSbssLen;
2233 fw.sbss_index = 0;
2234 fw.sbss = bnx2_TPAT_b06FwSbss;
2235
2236 fw.bss_addr = bnx2_TPAT_b06FwBssAddr;
2237 fw.bss_len = bnx2_TPAT_b06FwBssLen;
2238 fw.bss_index = 0;
2239 fw.bss = bnx2_TPAT_b06FwBss;
2240
2241 fw.rodata_addr = bnx2_TPAT_b06FwRodataAddr;
2242 fw.rodata_len = bnx2_TPAT_b06FwRodataLen;
2243 fw.rodata_index = 0;
2244 fw.rodata = bnx2_TPAT_b06FwRodata;
2245
2246 load_cpu_fw(bp, &cpu_reg, &fw);
2247
2248 /* Initialize the Completion Processor. */
2249 cpu_reg.mode = BNX2_COM_CPU_MODE;
2250 cpu_reg.mode_value_halt = BNX2_COM_CPU_MODE_SOFT_HALT;
2251 cpu_reg.mode_value_sstep = BNX2_COM_CPU_MODE_STEP_ENA;
2252 cpu_reg.state = BNX2_COM_CPU_STATE;
2253 cpu_reg.state_value_clear = 0xffffff;
2254 cpu_reg.gpr0 = BNX2_COM_CPU_REG_FILE;
2255 cpu_reg.evmask = BNX2_COM_CPU_EVENT_MASK;
2256 cpu_reg.pc = BNX2_COM_CPU_PROGRAM_COUNTER;
2257 cpu_reg.inst = BNX2_COM_CPU_INSTRUCTION;
2258 cpu_reg.bp = BNX2_COM_CPU_HW_BREAKPOINT;
2259 cpu_reg.spad_base = BNX2_COM_SCRATCH;
2260 cpu_reg.mips_view_base = 0x8000000;
2261
2262 fw.ver_major = bnx2_COM_b06FwReleaseMajor;
2263 fw.ver_minor = bnx2_COM_b06FwReleaseMinor;
2264 fw.ver_fix = bnx2_COM_b06FwReleaseFix;
2265 fw.start_addr = bnx2_COM_b06FwStartAddr;
2266
2267 fw.text_addr = bnx2_COM_b06FwTextAddr;
2268 fw.text_len = bnx2_COM_b06FwTextLen;
2269 fw.text_index = 0;
2270 fw.text = bnx2_COM_b06FwText;
2271
2272 fw.data_addr = bnx2_COM_b06FwDataAddr;
2273 fw.data_len = bnx2_COM_b06FwDataLen;
2274 fw.data_index = 0;
2275 fw.data = bnx2_COM_b06FwData;
2276
2277 fw.sbss_addr = bnx2_COM_b06FwSbssAddr;
2278 fw.sbss_len = bnx2_COM_b06FwSbssLen;
2279 fw.sbss_index = 0;
2280 fw.sbss = bnx2_COM_b06FwSbss;
2281
2282 fw.bss_addr = bnx2_COM_b06FwBssAddr;
2283 fw.bss_len = bnx2_COM_b06FwBssLen;
2284 fw.bss_index = 0;
2285 fw.bss = bnx2_COM_b06FwBss;
2286
2287 fw.rodata_addr = bnx2_COM_b06FwRodataAddr;
2288 fw.rodata_len = bnx2_COM_b06FwRodataLen;
2289 fw.rodata_index = 0;
2290 fw.rodata = bnx2_COM_b06FwRodata;
2291
2292 load_cpu_fw(bp, &cpu_reg, &fw);
2293
2294}
2295
2296static int
829ca9a3 2297bnx2_set_power_state(struct bnx2 *bp, pci_power_t state)
b6016b76
MC		 2298{
2299 u16 pmcsr;
2300
2301 pci_read_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL, &pmcsr);
2302
2303 switch (state) {
829ca9a3 2304 case PCI_D0: {
b6016b76
MC		 2305 u32 val;
2306
2307 pci_write_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL,
2308 (pmcsr & ~PCI_PM_CTRL_STATE_MASK) |
2309 PCI_PM_CTRL_PME_STATUS);
2310
2311 if (pmcsr & PCI_PM_CTRL_STATE_MASK)
2312 /* delay required during transition out of D3hot */
2313 msleep(20);
2314
2315 val = REG_RD(bp, BNX2_EMAC_MODE);
2316 val |= BNX2_EMAC_MODE_MPKT_RCVD | BNX2_EMAC_MODE_ACPI_RCVD;
2317 val &= ~BNX2_EMAC_MODE_MPKT;
2318 REG_WR(bp, BNX2_EMAC_MODE, val);
2319
2320 val = REG_RD(bp, BNX2_RPM_CONFIG);
2321 val &= ~BNX2_RPM_CONFIG_ACPI_ENA;
2322 REG_WR(bp, BNX2_RPM_CONFIG, val);
2323 break;
2324 }
829ca9a3 2325 case PCI_D3hot: {
b6016b76
MC		 2326 int i;
2327 u32 val, wol_msg;
2328
2329 if (bp->wol) {
2330 u32 advertising;
2331 u8 autoneg;
2332
2333 autoneg = bp->autoneg;
2334 advertising = bp->advertising;
2335
2336 bp->autoneg = AUTONEG_SPEED;
2337 bp->advertising = ADVERTISED_10baseT_Half |
2338 ADVERTISED_10baseT_Full |
2339 ADVERTISED_100baseT_Half |
2340 ADVERTISED_100baseT_Full |
2341 ADVERTISED_Autoneg;
2342
2343 bnx2_setup_copper_phy(bp);
2344
2345 bp->autoneg = autoneg;
2346 bp->advertising = advertising;
2347
2348 bnx2_set_mac_addr(bp);
2349
2350 val = REG_RD(bp, BNX2_EMAC_MODE);
2351
2352 /* Enable port mode. */
2353 val &= ~BNX2_EMAC_MODE_PORT;
2354 val |= BNX2_EMAC_MODE_PORT_MII |
2355 BNX2_EMAC_MODE_MPKT_RCVD |
2356 BNX2_EMAC_MODE_ACPI_RCVD |
b6016b76
MC		 2357 BNX2_EMAC_MODE_MPKT;
2358
2359 REG_WR(bp, BNX2_EMAC_MODE, val);
2360
2361 /* receive all multicast */
2362 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
2363 REG_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),
2364 0xffffffff);
2365 }
2366 REG_WR(bp, BNX2_EMAC_RX_MODE,
2367 BNX2_EMAC_RX_MODE_SORT_MODE);
2368
2369 val = 1 | BNX2_RPM_SORT_USER0_BC_EN |
2370 BNX2_RPM_SORT_USER0_MC_EN;
2371 REG_WR(bp, BNX2_RPM_SORT_USER0, 0x0);
2372 REG_WR(bp, BNX2_RPM_SORT_USER0, val);
2373 REG_WR(bp, BNX2_RPM_SORT_USER0, val |
2374 BNX2_RPM_SORT_USER0_ENA);
2375
2376 /* Need to enable EMAC and RPM for WOL. */
2377 REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS,
2378 BNX2_MISC_ENABLE_SET_BITS_RX_PARSER_MAC_ENABLE |
2379 BNX2_MISC_ENABLE_SET_BITS_TX_HEADER_Q_ENABLE |
2380 BNX2_MISC_ENABLE_SET_BITS_EMAC_ENABLE);
2381
2382 val = REG_RD(bp, BNX2_RPM_CONFIG);
2383 val &= ~BNX2_RPM_CONFIG_ACPI_ENA;
2384 REG_WR(bp, BNX2_RPM_CONFIG, val);
2385
2386 wol_msg = BNX2_DRV_MSG_CODE_SUSPEND_WOL;
2387 }
2388 else {
2389 wol_msg = BNX2_DRV_MSG_CODE_SUSPEND_NO_WOL;
2390 }
2391
dda1e390
MC		 2392 if (!(bp->flags & NO_WOL_FLAG))
2393 bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT3 | wol_msg, 0);
b6016b76
MC		 2394
2395 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
2396 if ((CHIP_ID(bp) == CHIP_ID_5706_A0) ||
2397 (CHIP_ID(bp) == CHIP_ID_5706_A1)) {
2398
2399 if (bp->wol)
2400 pmcsr |= 3;
2401 }
2402 else {
2403 pmcsr |= 3;
2404 }
2405 if (bp->wol) {
2406 pmcsr |= PCI_PM_CTRL_PME_ENABLE;
2407 }
2408 pci_write_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL,
2409 pmcsr);
2410
2411 /* No more memory access after this point until
2412 * device is brought back to D0.
2413 */
2414 udelay(50);
2415 break;
2416 }
2417 default:
2418 return -EINVAL;
2419 }
2420 return 0;
2421}
2422
2423static int
2424bnx2_acquire_nvram_lock(struct bnx2 *bp)
2425{
2426 u32 val;
2427 int j;
2428
2429 /* Request access to the flash interface. */
2430 REG_WR(bp, BNX2_NVM_SW_ARB, BNX2_NVM_SW_ARB_ARB_REQ_SET2);
2431 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
2432 val = REG_RD(bp, BNX2_NVM_SW_ARB);
2433 if (val & BNX2_NVM_SW_ARB_ARB_ARB2)
2434 break;
2435
2436 udelay(5);
2437 }
2438
2439 if (j >= NVRAM_TIMEOUT_COUNT)
2440 return -EBUSY;
2441
2442 return 0;
2443}
2444
2445static int
2446bnx2_release_nvram_lock(struct bnx2 *bp)
2447{
2448 int j;
2449 u32 val;
2450
2451 /* Relinquish nvram interface. */
2452 REG_WR(bp, BNX2_NVM_SW_ARB, BNX2_NVM_SW_ARB_ARB_REQ_CLR2);
2453
2454 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
2455 val = REG_RD(bp, BNX2_NVM_SW_ARB);
2456 if (!(val & BNX2_NVM_SW_ARB_ARB_ARB2))
2457 break;
2458
2459 udelay(5);
2460 }
2461
2462 if (j >= NVRAM_TIMEOUT_COUNT)
2463 return -EBUSY;
2464
2465 return 0;
2466}
2467
2468
2469static int
2470bnx2_enable_nvram_write(struct bnx2 *bp)
2471{
2472 u32 val;
2473
2474 val = REG_RD(bp, BNX2_MISC_CFG);
2475 REG_WR(bp, BNX2_MISC_CFG, val | BNX2_MISC_CFG_NVM_WR_EN_PCI);
2476
2477 if (!bp->flash_info->buffered) {
2478 int j;
2479
2480 REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
2481 REG_WR(bp, BNX2_NVM_COMMAND,
2482 BNX2_NVM_COMMAND_WREN | BNX2_NVM_COMMAND_DOIT);
2483
2484 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
2485 udelay(5);
2486
2487 val = REG_RD(bp, BNX2_NVM_COMMAND);
2488 if (val & BNX2_NVM_COMMAND_DONE)
2489 break;
2490 }
2491
2492 if (j >= NVRAM_TIMEOUT_COUNT)
2493 return -EBUSY;
2494 }
2495 return 0;
2496}
2497
2498static void
2499bnx2_disable_nvram_write(struct bnx2 *bp)
2500{
2501 u32 val;
2502
2503 val = REG_RD(bp, BNX2_MISC_CFG);
2504 REG_WR(bp, BNX2_MISC_CFG, val & ~BNX2_MISC_CFG_NVM_WR_EN);
2505}
2506
2507
2508static void
2509bnx2_enable_nvram_access(struct bnx2 *bp)
2510{
2511 u32 val;
2512
2513 val = REG_RD(bp, BNX2_NVM_ACCESS_ENABLE);
2514 /* Enable both bits, even on read. */
2515 REG_WR(bp, BNX2_NVM_ACCESS_ENABLE,
2516 val | BNX2_NVM_ACCESS_ENABLE_EN | BNX2_NVM_ACCESS_ENABLE_WR_EN);
2517}
2518
2519static void
2520bnx2_disable_nvram_access(struct bnx2 *bp)
2521{
2522 u32 val;
2523
2524 val = REG_RD(bp, BNX2_NVM_ACCESS_ENABLE);
2525 /* Disable both bits, even after read. */
2526 REG_WR(bp, BNX2_NVM_ACCESS_ENABLE,
2527 val & ~(BNX2_NVM_ACCESS_ENABLE_EN |
2528 BNX2_NVM_ACCESS_ENABLE_WR_EN));
2529}
2530
2531static int
2532bnx2_nvram_erase_page(struct bnx2 *bp, u32 offset)
2533{
2534 u32 cmd;
2535 int j;
2536
2537 if (bp->flash_info->buffered)
2538 /* Buffered flash, no erase needed */
2539 return 0;
2540
2541 /* Build an erase command */
2542 cmd = BNX2_NVM_COMMAND_ERASE | BNX2_NVM_COMMAND_WR |
2543 BNX2_NVM_COMMAND_DOIT;
2544
2545 /* Need to clear DONE bit separately. */
2546 REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
2547
2548 /* Address of the NVRAM to read from. */
2549 REG_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);
2550
2551 /* Issue an erase command. */
2552 REG_WR(bp, BNX2_NVM_COMMAND, cmd);
2553
2554 /* Wait for completion. */
2555 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
2556 u32 val;
2557
2558 udelay(5);
2559
2560 val = REG_RD(bp, BNX2_NVM_COMMAND);
2561 if (val & BNX2_NVM_COMMAND_DONE)
2562 break;
2563 }
2564
2565 if (j >= NVRAM_TIMEOUT_COUNT)
2566 return -EBUSY;
2567
2568 return 0;
2569}
2570
2571static int
2572bnx2_nvram_read_dword(struct bnx2 *bp, u32 offset, u8 *ret_val, u32 cmd_flags)
2573{
2574 u32 cmd;
2575 int j;
2576
2577 /* Build the command word. */
2578 cmd = BNX2_NVM_COMMAND_DOIT | cmd_flags;
2579
2580 /* Calculate an offset of a buffered flash. */
2581 if (bp->flash_info->buffered) {
2582 offset = ((offset / bp->flash_info->page_size) <<
2583 bp->flash_info->page_bits) +
2584 (offset % bp->flash_info->page_size);
2585 }
2586
2587 /* Need to clear DONE bit separately. */
2588 REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
2589
2590 /* Address of the NVRAM to read from. */
2591 REG_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);
2592
2593 /* Issue a read command. */
2594 REG_WR(bp, BNX2_NVM_COMMAND, cmd);
2595
2596 /* Wait for completion. */
2597 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
2598 u32 val;
2599
2600 udelay(5);
2601
2602 val = REG_RD(bp, BNX2_NVM_COMMAND);
2603 if (val & BNX2_NVM_COMMAND_DONE) {
2604 val = REG_RD(bp, BNX2_NVM_READ);
2605
2606 val = be32_to_cpu(val);
2607 memcpy(ret_val, &val, 4);
2608 break;
2609 }
2610 }
2611 if (j >= NVRAM_TIMEOUT_COUNT)
2612 return -EBUSY;
2613
2614 return 0;
2615}
2616
2617
2618static int
2619bnx2_nvram_write_dword(struct bnx2 *bp, u32 offset, u8 *val, u32 cmd_flags)
2620{
2621 u32 cmd, val32;
2622 int j;
2623
2624 /* Build the command word. */
2625 cmd = BNX2_NVM_COMMAND_DOIT | BNX2_NVM_COMMAND_WR | cmd_flags;
2626
2627 /* Calculate an offset of a buffered flash. */
2628 if (bp->flash_info->buffered) {
2629 offset = ((offset / bp->flash_info->page_size) <<
2630 bp->flash_info->page_bits) +
2631 (offset % bp->flash_info->page_size);
2632 }
2633
2634 /* Need to clear DONE bit separately. */
2635 REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
2636
2637 memcpy(&val32, val, 4);
2638 val32 = cpu_to_be32(val32);
2639
2640 /* Write the data. */
2641 REG_WR(bp, BNX2_NVM_WRITE, val32);
2642
2643 /* Address of the NVRAM to write to. */
2644 REG_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);
2645
2646 /* Issue the write command. */
2647 REG_WR(bp, BNX2_NVM_COMMAND, cmd);
2648
2649 /* Wait for completion. */
2650 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
2651 udelay(5);
2652
2653 if (REG_RD(bp, BNX2_NVM_COMMAND) & BNX2_NVM_COMMAND_DONE)
2654 break;
2655 }
2656 if (j >= NVRAM_TIMEOUT_COUNT)
2657 return -EBUSY;
2658
2659 return 0;
2660}
2661
2662static int
2663bnx2_init_nvram(struct bnx2 *bp)
2664{
2665 u32 val;
2666 int j, entry_count, rc;
2667 struct flash_spec *flash;
2668
2669 /* Determine the selected interface. */
2670 val = REG_RD(bp, BNX2_NVM_CFG1);
2671
2672 entry_count = sizeof(flash_table) / sizeof(struct flash_spec);
2673
2674 rc = 0;
2675 if (val & 0x40000000) {
2676
2677 /* Flash interface has been reconfigured */
2678 for (j = 0, flash = &flash_table[0]; j < entry_count;
37137709
MC		 2679 j++, flash++) {
2680 if ((val & FLASH_BACKUP_STRAP_MASK) ==
2681 (flash->config1 & FLASH_BACKUP_STRAP_MASK)) {
b6016b76
MC		 2682 bp->flash_info = flash;
2683 break;
2684 }
2685 }
2686 }
2687 else {
37137709 2688 u32 mask;
b6016b76
MC		 2689 /* Not yet been reconfigured */
2690
37137709
MC		 2691 if (val & (1 << 23))
2692 mask = FLASH_BACKUP_STRAP_MASK;
2693 else
2694 mask = FLASH_STRAP_MASK;
2695
b6016b76
MC		 2696 for (j = 0, flash = &flash_table[0]; j < entry_count;
2697 j++, flash++) {
2698
37137709 2699 if ((val & mask) == (flash->strapping & mask)) {
b6016b76
MC		 2700 bp->flash_info = flash;
2701
2702 /* Request access to the flash interface. */
2703 if ((rc = bnx2_acquire_nvram_lock(bp)) != 0)
2704 return rc;
2705
2706 /* Enable access to flash interface */
2707 bnx2_enable_nvram_access(bp);
2708
2709 /* Reconfigure the flash interface */
2710 REG_WR(bp, BNX2_NVM_CFG1, flash->config1);
2711 REG_WR(bp, BNX2_NVM_CFG2, flash->config2);
2712 REG_WR(bp, BNX2_NVM_CFG3, flash->config3);
2713 REG_WR(bp, BNX2_NVM_WRITE1, flash->write1);
2714
2715 /* Disable access to flash interface */
2716 bnx2_disable_nvram_access(bp);
2717 bnx2_release_nvram_lock(bp);
2718
2719 break;
2720 }
2721 }
2722 } /* if (val & 0x40000000) */
2723
2724 if (j == entry_count) {
2725 bp->flash_info = NULL;
2f23c523 2726 printk(KERN_ALERT PFX "Unknown flash/EEPROM type.\n");
1122db71 2727 return -ENODEV;
b6016b76
MC		 2728 }
2729
1122db71
MC		 2730 val = REG_RD_IND(bp, bp->shmem_base + BNX2_SHARED_HW_CFG_CONFIG2);
2731 val &= BNX2_SHARED_HW_CFG2_NVM_SIZE_MASK;
2732 if (val)
2733 bp->flash_size = val;
2734 else
2735 bp->flash_size = bp->flash_info->total_size;
2736
b6016b76
MC		 2737 return rc;
2738}
2739
2740static int
2741bnx2_nvram_read(struct bnx2 *bp, u32 offset, u8 *ret_buf,
2742 int buf_size)
2743{
2744 int rc = 0;
2745 u32 cmd_flags, offset32, len32, extra;
2746
2747 if (buf_size == 0)
2748 return 0;
2749
2750 /* Request access to the flash interface. */
2751 if ((rc = bnx2_acquire_nvram_lock(bp)) != 0)
2752 return rc;
2753
2754 /* Enable access to flash interface */
2755 bnx2_enable_nvram_access(bp);
2756
2757 len32 = buf_size;
2758 offset32 = offset;
2759 extra = 0;
2760
2761 cmd_flags = 0;
2762
2763 if (offset32 & 3) {
2764 u8 buf[4];
2765 u32 pre_len;
2766
2767 offset32 &= ~3;
2768 pre_len = 4 - (offset & 3);
2769
2770 if (pre_len >= len32) {
2771 pre_len = len32;
2772 cmd_flags = BNX2_NVM_COMMAND_FIRST |
2773 BNX2_NVM_COMMAND_LAST;
2774 }
2775 else {
2776 cmd_flags = BNX2_NVM_COMMAND_FIRST;
2777 }
2778
2779 rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags);
2780
2781 if (rc)
2782 return rc;
2783
2784 memcpy(ret_buf, buf + (offset & 3), pre_len);
2785
2786 offset32 += 4;
2787 ret_buf += pre_len;
2788 len32 -= pre_len;
2789 }
2790 if (len32 & 3) {
2791 extra = 4 - (len32 & 3);
2792 len32 = (len32 + 4) & ~3;
2793 }
2794
2795 if (len32 == 4) {
2796 u8 buf[4];
2797
2798 if (cmd_flags)
2799 cmd_flags = BNX2_NVM_COMMAND_LAST;
2800 else
2801 cmd_flags = BNX2_NVM_COMMAND_FIRST |
2802 BNX2_NVM_COMMAND_LAST;
2803
2804 rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags);
2805
2806 memcpy(ret_buf, buf, 4 - extra);
2807 }
2808 else if (len32 > 0) {
2809 u8 buf[4];
2810
2811 /* Read the first word. */
2812 if (cmd_flags)
2813 cmd_flags = 0;
2814 else
2815 cmd_flags = BNX2_NVM_COMMAND_FIRST;
2816
2817 rc = bnx2_nvram_read_dword(bp, offset32, ret_buf, cmd_flags);
2818
2819 /* Advance to the next dword. */
2820 offset32 += 4;
2821 ret_buf += 4;
2822 len32 -= 4;
2823
2824 while (len32 > 4 && rc == 0) {
2825 rc = bnx2_nvram_read_dword(bp, offset32, ret_buf, 0);
2826
2827 /* Advance to the next dword. */
2828 offset32 += 4;
2829 ret_buf += 4;
2830 len32 -= 4;
2831 }
2832
2833 if (rc)
2834 return rc;
2835
2836 cmd_flags = BNX2_NVM_COMMAND_LAST;
2837 rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags);
2838
2839 memcpy(ret_buf, buf, 4 - extra);
2840 }
2841
2842 /* Disable access to flash interface */
2843 bnx2_disable_nvram_access(bp);
2844
2845 bnx2_release_nvram_lock(bp);
2846
2847 return rc;
2848}
2849
2850static int
2851bnx2_nvram_write(struct bnx2 *bp, u32 offset, u8 *data_buf,
2852 int buf_size)
2853{
2854 u32 written, offset32, len32;
2855 u8 *buf, start[4], end[4];
2856 int rc = 0;
2857 int align_start, align_end;
2858
2859 buf = data_buf;
2860 offset32 = offset;
2861 len32 = buf_size;
2862 align_start = align_end = 0;
2863
2864 if ((align_start = (offset32 & 3))) {
2865 offset32 &= ~3;
2866 len32 += align_start;
2867 if ((rc = bnx2_nvram_read(bp, offset32, start, 4)))
2868 return rc;
2869 }
2870
2871 if (len32 & 3) {
2872 if ((len32 > 4) || !align_start) {
2873 align_end = 4 - (len32 & 3);
2874 len32 += align_end;
2875 if ((rc = bnx2_nvram_read(bp, offset32 + len32 - 4,
2876 end, 4))) {
2877 return rc;
2878 }
2879 }
2880 }
2881
2882 if (align_start || align_end) {
2883 buf = kmalloc(len32, GFP_KERNEL);
2884 if (buf == 0)
2885 return -ENOMEM;
2886 if (align_start) {
2887 memcpy(buf, start, 4);
2888 }
2889 if (align_end) {
2890 memcpy(buf + len32 - 4, end, 4);
2891 }
2892 memcpy(buf + align_start, data_buf, buf_size);
2893 }
2894
2895 written = 0;
2896 while ((written < len32) && (rc == 0)) {
2897 u32 page_start, page_end, data_start, data_end;
2898 u32 addr, cmd_flags;
2899 int i;
2900 u8 flash_buffer[264];
2901
2902 /* Find the page_start addr */
2903 page_start = offset32 + written;
2904 page_start -= (page_start % bp->flash_info->page_size);
2905 /* Find the page_end addr */
2906 page_end = page_start + bp->flash_info->page_size;
2907 /* Find the data_start addr */
2908 data_start = (written == 0) ? offset32 : page_start;
2909 /* Find the data_end addr */
2910 data_end = (page_end > offset32 + len32) ?
2911 (offset32 + len32) : page_end;
2912
2913 /* Request access to the flash interface. */
2914 if ((rc = bnx2_acquire_nvram_lock(bp)) != 0)
2915 goto nvram_write_end;
2916
2917 /* Enable access to flash interface */
2918 bnx2_enable_nvram_access(bp);
2919
2920 cmd_flags = BNX2_NVM_COMMAND_FIRST;
2921 if (bp->flash_info->buffered == 0) {
2922 int j;
2923
2924 /* Read the whole page into the buffer
2925 * (non-buffer flash only) */
2926 for (j = 0; j < bp->flash_info->page_size; j += 4) {
2927 if (j == (bp->flash_info->page_size - 4)) {
2928 cmd_flags |= BNX2_NVM_COMMAND_LAST;
2929 }
2930 rc = bnx2_nvram_read_dword(bp,
2931 page_start + j,
2932 &flash_buffer[j],
2933 cmd_flags);
2934
2935 if (rc)
2936 goto nvram_write_end;
2937
2938 cmd_flags = 0;
2939 }
2940 }
2941
2942 /* Enable writes to flash interface (unlock write-protect) */
2943 if ((rc = bnx2_enable_nvram_write(bp)) != 0)
2944 goto nvram_write_end;
2945
2946 /* Erase the page */
2947 if ((rc = bnx2_nvram_erase_page(bp, page_start)) != 0)
2948 goto nvram_write_end;
2949
2950 /* Re-enable the write again for the actual write */
2951 bnx2_enable_nvram_write(bp);
2952
2953 /* Loop to write back the buffer data from page_start to
2954 * data_start */
2955 i = 0;
2956 if (bp->flash_info->buffered == 0) {
2957 for (addr = page_start; addr < data_start;
2958 addr += 4, i += 4) {
2959
2960 rc = bnx2_nvram_write_dword(bp, addr,
2961 &flash_buffer[i], cmd_flags);
2962
2963 if (rc != 0)
2964 goto nvram_write_end;
2965
2966 cmd_flags = 0;
2967 }
2968 }
2969
2970 /* Loop to write the new data from data_start to data_end */
2971 for (addr = data_start; addr < data_end; addr += 4, i++) {
2972 if ((addr == page_end - 4) ||
2973 ((bp->flash_info->buffered) &&
2974 (addr == data_end - 4))) {
2975
2976 cmd_flags |= BNX2_NVM_COMMAND_LAST;
2977 }
2978 rc = bnx2_nvram_write_dword(bp, addr, buf,
2979 cmd_flags);
2980
2981 if (rc != 0)
2982 goto nvram_write_end;
2983
2984 cmd_flags = 0;
2985 buf += 4;
2986 }
2987
2988 /* Loop to write back the buffer data from data_end
2989 * to page_end */
2990 if (bp->flash_info->buffered == 0) {
2991 for (addr = data_end; addr < page_end;
2992 addr += 4, i += 4) {
2993
2994 if (addr == page_end-4) {
2995 cmd_flags = BNX2_NVM_COMMAND_LAST;
2996 }
2997 rc = bnx2_nvram_write_dword(bp, addr,
2998 &flash_buffer[i], cmd_flags);
2999
3000 if (rc != 0)
3001 goto nvram_write_end;
3002
3003 cmd_flags = 0;
3004 }
3005 }
3006
3007 /* Disable writes to flash interface (lock write-protect) */
3008 bnx2_disable_nvram_write(bp);
3009
3010 /* Disable access to flash interface */
3011 bnx2_disable_nvram_access(bp);
3012 bnx2_release_nvram_lock(bp);
3013
3014 /* Increment written */
3015 written += data_end - data_start;
3016 }
3017
3018nvram_write_end:
3019 if (align_start || align_end)
3020 kfree(buf);
3021 return rc;
3022}
3023
3024static int
3025bnx2_reset_chip(struct bnx2 *bp, u32 reset_code)
3026{
3027 u32 val;
3028 int i, rc = 0;
3029
3030 /* Wait for the current PCI transaction to complete before
3031 * issuing a reset. */
3032 REG_WR(bp, BNX2_MISC_ENABLE_CLR_BITS,
3033 BNX2_MISC_ENABLE_CLR_BITS_TX_DMA_ENABLE |
3034 BNX2_MISC_ENABLE_CLR_BITS_DMA_ENGINE_ENABLE |
3035 BNX2_MISC_ENABLE_CLR_BITS_RX_DMA_ENABLE |
3036 BNX2_MISC_ENABLE_CLR_BITS_HOST_COALESCE_ENABLE);
3037 val = REG_RD(bp, BNX2_MISC_ENABLE_CLR_BITS);
3038 udelay(5);
3039
b090ae2b
MC		 3040 /* Wait for the firmware to tell us it is ok to issue a reset. */
3041 bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT0 | reset_code, 1);
3042
b6016b76
MC		 3043 /* Deposit a driver reset signature so the firmware knows that
3044 * this is a soft reset. */
e3648b3d 3045 REG_WR_IND(bp, bp->shmem_base + BNX2_DRV_RESET_SIGNATURE,
b6016b76
MC		 3046 BNX2_DRV_RESET_SIGNATURE_MAGIC);
3047
b6016b76
MC		 3048 /* Do a dummy read to force the chip to complete all current transaction
3049 * before we issue a reset. */
3050 val = REG_RD(bp, BNX2_MISC_ID);
3051
3052 val = BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |
3053 BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
3054 BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP;
3055
3056 /* Chip reset. */
3057 REG_WR(bp, BNX2_PCICFG_MISC_CONFIG, val);
3058
3059 if ((CHIP_ID(bp) == CHIP_ID_5706_A0) ||
3060 (CHIP_ID(bp) == CHIP_ID_5706_A1))
3061 msleep(15);
3062
3063 /* Reset takes approximate 30 usec */
3064 for (i = 0; i < 10; i++) {
3065 val = REG_RD(bp, BNX2_PCICFG_MISC_CONFIG);
3066 if ((val & (BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |
3067 BNX2_PCICFG_MISC_CONFIG_CORE_RST_BSY)) == 0) {
3068 break;
3069 }
3070 udelay(10);
3071 }
3072
3073 if (val & (BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |
3074 BNX2_PCICFG_MISC_CONFIG_CORE_RST_BSY)) {
3075 printk(KERN_ERR PFX "Chip reset did not complete\n");
3076 return -EBUSY;
3077 }
3078
3079 /* Make sure byte swapping is properly configured. */
3080 val = REG_RD(bp, BNX2_PCI_SWAP_DIAG0);
3081 if (val != 0x01020304) {
3082 printk(KERN_ERR PFX "Chip not in correct endian mode\n");
3083 return -ENODEV;
3084 }
3085
b6016b76 3086 /* Wait for the firmware to finish its initialization. */
b090ae2b
MC		 3087 rc = bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT1 | reset_code, 0);
3088 if (rc)
3089 return rc;
b6016b76
MC		 3090
3091 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
3092 /* Adjust the voltage regular to two steps lower. The default
3093 * of this register is 0x0000000e. */
3094 REG_WR(bp, BNX2_MISC_VREG_CONTROL, 0x000000fa);
3095
3096 /* Remove bad rbuf memory from the free pool. */
3097 rc = bnx2_alloc_bad_rbuf(bp);
3098 }
3099
3100 return rc;
3101}
3102
3103static int
3104bnx2_init_chip(struct bnx2 *bp)
3105{
3106 u32 val;
b090ae2b 3107 int rc;
b6016b76
MC		 3108
3109 /* Make sure the interrupt is not active. */
3110 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
3111
3112 val = BNX2_DMA_CONFIG_DATA_BYTE_SWAP |
3113 BNX2_DMA_CONFIG_DATA_WORD_SWAP |
3114#ifdef __BIG_ENDIAN
3115 BNX2_DMA_CONFIG_CNTL_BYTE_SWAP |
3116#endif
3117 BNX2_DMA_CONFIG_CNTL_WORD_SWAP |
3118 DMA_READ_CHANS << 12 |
3119 DMA_WRITE_CHANS << 16;
3120
3121 val |= (0x2 << 20) | (1 << 11);
3122
dda1e390 3123 if ((bp->flags & PCIX_FLAG) && (bp->bus_speed_mhz == 133))
b6016b76
MC		 3124 val |= (1 << 23);
3125
3126 if ((CHIP_NUM(bp) == CHIP_NUM_5706) &&
3127 (CHIP_ID(bp) != CHIP_ID_5706_A0) && !(bp->flags & PCIX_FLAG))
3128 val |= BNX2_DMA_CONFIG_CNTL_PING_PONG_DMA;
3129
3130 REG_WR(bp, BNX2_DMA_CONFIG, val);
3131
3132 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
3133 val = REG_RD(bp, BNX2_TDMA_CONFIG);
3134 val |= BNX2_TDMA_CONFIG_ONE_DMA;
3135 REG_WR(bp, BNX2_TDMA_CONFIG, val);
3136 }
3137
3138 if (bp->flags & PCIX_FLAG) {
3139 u16 val16;
3140
3141 pci_read_config_word(bp->pdev, bp->pcix_cap + PCI_X_CMD,
3142 &val16);
3143 pci_write_config_word(bp->pdev, bp->pcix_cap + PCI_X_CMD,
3144 val16 & ~PCI_X_CMD_ERO);
3145 }
3146
3147 REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS,
3148 BNX2_MISC_ENABLE_SET_BITS_HOST_COALESCE_ENABLE |
3149 BNX2_MISC_ENABLE_STATUS_BITS_RX_V2P_ENABLE |
3150 BNX2_MISC_ENABLE_STATUS_BITS_CONTEXT_ENABLE);
3151
3152 /* Initialize context mapping and zero out the quick contexts. The
3153 * context block must have already been enabled. */
3154 bnx2_init_context(bp);
3155
3156 bnx2_init_cpus(bp);
3157 bnx2_init_nvram(bp);
3158
3159 bnx2_set_mac_addr(bp);
3160
3161 val = REG_RD(bp, BNX2_MQ_CONFIG);
3162 val &= ~BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE;
3163 val |= BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE_256;
3164 REG_WR(bp, BNX2_MQ_CONFIG, val);
3165
3166 val = 0x10000 + (MAX_CID_CNT * MB_KERNEL_CTX_SIZE);
3167 REG_WR(bp, BNX2_MQ_KNL_BYP_WIND_START, val);
3168 REG_WR(bp, BNX2_MQ_KNL_WIND_END, val);
3169
3170 val = (BCM_PAGE_BITS - 8) << 24;
3171 REG_WR(bp, BNX2_RV2P_CONFIG, val);
3172
3173 /* Configure page size. */
3174 val = REG_RD(bp, BNX2_TBDR_CONFIG);
3175 val &= ~BNX2_TBDR_CONFIG_PAGE_SIZE;
3176 val |= (BCM_PAGE_BITS - 8) << 24 | 0x40;
3177 REG_WR(bp, BNX2_TBDR_CONFIG, val);
3178
3179 val = bp->mac_addr[0] +
3180 (bp->mac_addr[1] << 8) +
3181 (bp->mac_addr[2] << 16) +
3182 bp->mac_addr[3] +
3183 (bp->mac_addr[4] << 8) +
3184 (bp->mac_addr[5] << 16);
3185 REG_WR(bp, BNX2_EMAC_BACKOFF_SEED, val);
3186
3187 /* Program the MTU. Also include 4 bytes for CRC32. */
3188 val = bp->dev->mtu + ETH_HLEN + 4;
3189 if (val > (MAX_ETHERNET_PACKET_SIZE + 4))
3190 val |= BNX2_EMAC_RX_MTU_SIZE_JUMBO_ENA;
3191 REG_WR(bp, BNX2_EMAC_RX_MTU_SIZE, val);
3192
3193 bp->last_status_idx = 0;
3194 bp->rx_mode = BNX2_EMAC_RX_MODE_SORT_MODE;
3195
3196 /* Set up how to generate a link change interrupt. */
3197 REG_WR(bp, BNX2_EMAC_ATTENTION_ENA, BNX2_EMAC_ATTENTION_ENA_LINK);
3198
3199 REG_WR(bp, BNX2_HC_STATUS_ADDR_L,
3200 (u64) bp->status_blk_mapping & 0xffffffff);
3201 REG_WR(bp, BNX2_HC_STATUS_ADDR_H, (u64) bp->status_blk_mapping >> 32);
3202
3203 REG_WR(bp, BNX2_HC_STATISTICS_ADDR_L,
3204 (u64) bp->stats_blk_mapping & 0xffffffff);
3205 REG_WR(bp, BNX2_HC_STATISTICS_ADDR_H,
3206 (u64) bp->stats_blk_mapping >> 32);
3207
3208 REG_WR(bp, BNX2_HC_TX_QUICK_CONS_TRIP,
3209 (bp->tx_quick_cons_trip_int << 16) | bp->tx_quick_cons_trip);
3210
3211 REG_WR(bp, BNX2_HC_RX_QUICK_CONS_TRIP,
3212 (bp->rx_quick_cons_trip_int << 16) | bp->rx_quick_cons_trip);
3213
3214 REG_WR(bp, BNX2_HC_COMP_PROD_TRIP,
3215 (bp->comp_prod_trip_int << 16) | bp->comp_prod_trip);
3216
3217 REG_WR(bp, BNX2_HC_TX_TICKS, (bp->tx_ticks_int << 16) | bp->tx_ticks);
3218
3219 REG_WR(bp, BNX2_HC_RX_TICKS, (bp->rx_ticks_int << 16) | bp->rx_ticks);
3220
3221 REG_WR(bp, BNX2_HC_COM_TICKS,
3222 (bp->com_ticks_int << 16) | bp->com_ticks);
3223
3224 REG_WR(bp, BNX2_HC_CMD_TICKS,
3225 (bp->cmd_ticks_int << 16) | bp->cmd_ticks);
3226
3227 REG_WR(bp, BNX2_HC_STATS_TICKS, bp->stats_ticks & 0xffff00);
3228 REG_WR(bp, BNX2_HC_STAT_COLLECT_TICKS, 0xbb8); /* 3ms */
3229
3230 if (CHIP_ID(bp) == CHIP_ID_5706_A1)
3231 REG_WR(bp, BNX2_HC_CONFIG, BNX2_HC_CONFIG_COLLECT_STATS);
3232 else {
3233 REG_WR(bp, BNX2_HC_CONFIG, BNX2_HC_CONFIG_RX_TMR_MODE |
3234 BNX2_HC_CONFIG_TX_TMR_MODE |
3235 BNX2_HC_CONFIG_COLLECT_STATS);
3236 }
3237
3238 /* Clear internal stats counters. */
3239 REG_WR(bp, BNX2_HC_COMMAND, BNX2_HC_COMMAND_CLR_STAT_NOW);
3240
3241 REG_WR(bp, BNX2_HC_ATTN_BITS_ENABLE, STATUS_ATTN_BITS_LINK_STATE);
3242
e29054f9
MC		 3243 if (REG_RD_IND(bp, bp->shmem_base + BNX2_PORT_FEATURE) &
3244 BNX2_PORT_FEATURE_ASF_ENABLED)
3245 bp->flags |= ASF_ENABLE_FLAG;
3246
b6016b76
MC		 3247 /* Initialize the receive filter. */
3248 bnx2_set_rx_mode(bp->dev);
3249
b090ae2b
MC		 3250 rc = bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT2 | BNX2_DRV_MSG_CODE_RESET,
3251 0);
b6016b76
MC		 3252
3253 REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS, 0x5ffffff);
3254 REG_RD(bp, BNX2_MISC_ENABLE_SET_BITS);
3255
3256 udelay(20);
3257
b090ae2b 3258 return rc;
b6016b76
MC		 3259}
3260
3261
3262static void
3263bnx2_init_tx_ring(struct bnx2 *bp)
3264{
3265 struct tx_bd *txbd;
3266 u32 val;
3267
3268 txbd = &bp->tx_desc_ring[MAX_TX_DESC_CNT];
3269
3270 txbd->tx_bd_haddr_hi = (u64) bp->tx_desc_mapping >> 32;
3271 txbd->tx_bd_haddr_lo = (u64) bp->tx_desc_mapping & 0xffffffff;
3272
3273 bp->tx_prod = 0;
3274 bp->tx_cons = 0;
f4e418f7 3275 bp->hw_tx_cons = 0;
b6016b76 3276 bp->tx_prod_bseq = 0;
b6016b76
MC		 3277
3278 val = BNX2_L2CTX_TYPE_TYPE_L2;
3279 val |= BNX2_L2CTX_TYPE_SIZE_L2;
3280 CTX_WR(bp, GET_CID_ADDR(TX_CID), BNX2_L2CTX_TYPE, val);
3281
3282 val = BNX2_L2CTX_CMD_TYPE_TYPE_L2;
3283 val |= 8 << 16;
3284 CTX_WR(bp, GET_CID_ADDR(TX_CID), BNX2_L2CTX_CMD_TYPE, val);
3285
3286 val = (u64) bp->tx_desc_mapping >> 32;
3287 CTX_WR(bp, GET_CID_ADDR(TX_CID), BNX2_L2CTX_TBDR_BHADDR_HI, val);
3288
3289 val = (u64) bp->tx_desc_mapping & 0xffffffff;
3290 CTX_WR(bp, GET_CID_ADDR(TX_CID), BNX2_L2CTX_TBDR_BHADDR_LO, val);
3291}
3292
3293static void
3294bnx2_init_rx_ring(struct bnx2 *bp)
3295{
3296 struct rx_bd *rxbd;
3297 int i;
3298 u16 prod, ring_prod;
3299 u32 val;
3300
3301 /* 8 for CRC and VLAN */
3302 bp->rx_buf_use_size = bp->dev->mtu + ETH_HLEN + bp->rx_offset + 8;
3303 /* 8 for alignment */
3304 bp->rx_buf_size = bp->rx_buf_use_size + 8;
3305
3306 ring_prod = prod = bp->rx_prod = 0;
3307 bp->rx_cons = 0;
f4e418f7 3308 bp->hw_rx_cons = 0;
b6016b76
MC		 3309 bp->rx_prod_bseq = 0;
3310
3311 rxbd = &bp->rx_desc_ring[0];
3312 for (i = 0; i < MAX_RX_DESC_CNT; i++, rxbd++) {
3313 rxbd->rx_bd_len = bp->rx_buf_use_size;
3314 rxbd->rx_bd_flags = RX_BD_FLAGS_START | RX_BD_FLAGS_END;
3315 }
3316
3317 rxbd->rx_bd_haddr_hi = (u64) bp->rx_desc_mapping >> 32;
3318 rxbd->rx_bd_haddr_lo = (u64) bp->rx_desc_mapping & 0xffffffff;
3319
3320 val = BNX2_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE;
3321 val |= BNX2_L2CTX_CTX_TYPE_SIZE_L2;
3322 val |= 0x02 << 8;
3323 CTX_WR(bp, GET_CID_ADDR(RX_CID), BNX2_L2CTX_CTX_TYPE, val);
3324
3325 val = (u64) bp->rx_desc_mapping >> 32;
3326 CTX_WR(bp, GET_CID_ADDR(RX_CID), BNX2_L2CTX_NX_BDHADDR_HI, val);
3327
3328 val = (u64) bp->rx_desc_mapping & 0xffffffff;
3329 CTX_WR(bp, GET_CID_ADDR(RX_CID), BNX2_L2CTX_NX_BDHADDR_LO, val);
3330
3331 for ( ;ring_prod < bp->rx_ring_size; ) {
3332 if (bnx2_alloc_rx_skb(bp, ring_prod) < 0) {
3333 break;
3334 }
3335 prod = NEXT_RX_BD(prod);
3336 ring_prod = RX_RING_IDX(prod);
3337 }
3338 bp->rx_prod = prod;
3339
3340 REG_WR16(bp, MB_RX_CID_ADDR + BNX2_L2CTX_HOST_BDIDX, prod);
3341
3342 REG_WR(bp, MB_RX_CID_ADDR + BNX2_L2CTX_HOST_BSEQ, bp->rx_prod_bseq);
3343}
3344
3345static void
3346bnx2_free_tx_skbs(struct bnx2 *bp)
3347{
3348 int i;
3349
3350 if (bp->tx_buf_ring == NULL)
3351 return;
3352
3353 for (i = 0; i < TX_DESC_CNT; ) {
3354 struct sw_bd *tx_buf = &bp->tx_buf_ring[i];
3355 struct sk_buff *skb = tx_buf->skb;
3356 int j, last;
3357
3358 if (skb == NULL) {
3359 i++;
3360 continue;
3361 }
3362
3363 pci_unmap_single(bp->pdev, pci_unmap_addr(tx_buf, mapping),
3364 skb_headlen(skb), PCI_DMA_TODEVICE);
3365
3366 tx_buf->skb = NULL;
3367
3368 last = skb_shinfo(skb)->nr_frags;
3369 for (j = 0; j < last; j++) {
3370 tx_buf = &bp->tx_buf_ring[i + j + 1];
3371 pci_unmap_page(bp->pdev,
3372 pci_unmap_addr(tx_buf, mapping),
3373 skb_shinfo(skb)->frags[j].size,
3374 PCI_DMA_TODEVICE);
3375 }
3376 dev_kfree_skb_any(skb);
3377 i += j + 1;
3378 }
3379
3380}
3381
3382static void
3383bnx2_free_rx_skbs(struct bnx2 *bp)
3384{
3385 int i;
3386
3387 if (bp->rx_buf_ring == NULL)
3388 return;
3389
3390 for (i = 0; i < RX_DESC_CNT; i++) {
3391 struct sw_bd *rx_buf = &bp->rx_buf_ring[i];
3392 struct sk_buff *skb = rx_buf->skb;
3393
05d0f1cf 3394 if (skb == NULL)
b6016b76
MC		 3395 continue;
3396
3397 pci_unmap_single(bp->pdev, pci_unmap_addr(rx_buf, mapping),
3398 bp->rx_buf_use_size, PCI_DMA_FROMDEVICE);
3399
3400 rx_buf->skb = NULL;
3401
3402 dev_kfree_skb_any(skb);
3403 }
3404}
3405
3406static void
3407bnx2_free_skbs(struct bnx2 *bp)
3408{
3409 bnx2_free_tx_skbs(bp);
3410 bnx2_free_rx_skbs(bp);
3411}
3412
3413static int
3414bnx2_reset_nic(struct bnx2 *bp, u32 reset_code)
3415{
3416 int rc;
3417
3418 rc = bnx2_reset_chip(bp, reset_code);
3419 bnx2_free_skbs(bp);
3420 if (rc)
3421 return rc;
3422
3423 bnx2_init_chip(bp);
3424 bnx2_init_tx_ring(bp);
3425 bnx2_init_rx_ring(bp);
3426 return 0;
3427}
3428
3429static int
3430bnx2_init_nic(struct bnx2 *bp)
3431{
3432 int rc;
3433
3434 if ((rc = bnx2_reset_nic(bp, BNX2_DRV_MSG_CODE_RESET)) != 0)
3435 return rc;
3436
3437 bnx2_init_phy(bp);
3438 bnx2_set_link(bp);
3439 return 0;
3440}
3441
3442static int
3443bnx2_test_registers(struct bnx2 *bp)
3444{
3445 int ret;
3446 int i;
3447 static struct {
3448 u16 offset;
3449 u16 flags;
3450 u32 rw_mask;
3451 u32 ro_mask;
3452 } reg_tbl[] = {
3453 { 0x006c, 0, 0x00000000, 0x0000003f },
3454 { 0x0090, 0, 0xffffffff, 0x00000000 },
3455 { 0x0094, 0, 0x00000000, 0x00000000 },
3456
3457 { 0x0404, 0, 0x00003f00, 0x00000000 },
3458 { 0x0418, 0, 0x00000000, 0xffffffff },
3459 { 0x041c, 0, 0x00000000, 0xffffffff },
3460 { 0x0420, 0, 0x00000000, 0x80ffffff },
3461 { 0x0424, 0, 0x00000000, 0x00000000 },
3462 { 0x0428, 0, 0x00000000, 0x00000001 },
3463 { 0x0450, 0, 0x00000000, 0x0000ffff },
3464 { 0x0454, 0, 0x00000000, 0xffffffff },
3465 { 0x0458, 0, 0x00000000, 0xffffffff },
3466
3467 { 0x0808, 0, 0x00000000, 0xffffffff },
3468 { 0x0854, 0, 0x00000000, 0xffffffff },
3469 { 0x0868, 0, 0x00000000, 0x77777777 },
3470 { 0x086c, 0, 0x00000000, 0x77777777 },
3471 { 0x0870, 0, 0x00000000, 0x77777777 },
3472 { 0x0874, 0, 0x00000000, 0x77777777 },
3473
3474 { 0x0c00, 0, 0x00000000, 0x00000001 },
3475 { 0x0c04, 0, 0x00000000, 0x03ff0001 },
3476 { 0x0c08, 0, 0x0f0ff073, 0x00000000 },
3477 { 0x0c0c, 0, 0x00ffffff, 0x00000000 },
3478 { 0x0c30, 0, 0x00000000, 0xffffffff },
3479 { 0x0c34, 0, 0x00000000, 0xffffffff },
3480 { 0x0c38, 0, 0x00000000, 0xffffffff },
3481 { 0x0c3c, 0, 0x00000000, 0xffffffff },
3482 { 0x0c40, 0, 0x00000000, 0xffffffff },
3483 { 0x0c44, 0, 0x00000000, 0xffffffff },
3484 { 0x0c48, 0, 0x00000000, 0x0007ffff },
3485 { 0x0c4c, 0, 0x00000000, 0xffffffff },
3486 { 0x0c50, 0, 0x00000000, 0xffffffff },
3487 { 0x0c54, 0, 0x00000000, 0xffffffff },
3488 { 0x0c58, 0, 0x00000000, 0xffffffff },
3489 { 0x0c5c, 0, 0x00000000, 0xffffffff },
3490 { 0x0c60, 0, 0x00000000, 0xffffffff },
3491 { 0x0c64, 0, 0x00000000, 0xffffffff },
3492 { 0x0c68, 0, 0x00000000, 0xffffffff },
3493 { 0x0c6c, 0, 0x00000000, 0xffffffff },
3494 { 0x0c70, 0, 0x00000000, 0xffffffff },
3495 { 0x0c74, 0, 0x00000000, 0xffffffff },
3496 { 0x0c78, 0, 0x00000000, 0xffffffff },
3497 { 0x0c7c, 0, 0x00000000, 0xffffffff },
3498 { 0x0c80, 0, 0x00000000, 0xffffffff },
3499 { 0x0c84, 0, 0x00000000, 0xffffffff },
3500 { 0x0c88, 0, 0x00000000, 0xffffffff },
3501 { 0x0c8c, 0, 0x00000000, 0xffffffff },
3502 { 0x0c90, 0, 0x00000000, 0xffffffff },
3503 { 0x0c94, 0, 0x00000000, 0xffffffff },
3504 { 0x0c98, 0, 0x00000000, 0xffffffff },
3505 { 0x0c9c, 0, 0x00000000, 0xffffffff },
3506 { 0x0ca0, 0, 0x00000000, 0xffffffff },
3507 { 0x0ca4, 0, 0x00000000, 0xffffffff },
3508 { 0x0ca8, 0, 0x00000000, 0x0007ffff },
3509 { 0x0cac, 0, 0x00000000, 0xffffffff },
3510 { 0x0cb0, 0, 0x00000000, 0xffffffff },
3511 { 0x0cb4, 0, 0x00000000, 0xffffffff },
3512 { 0x0cb8, 0, 0x00000000, 0xffffffff },
3513 { 0x0cbc, 0, 0x00000000, 0xffffffff },
3514 { 0x0cc0, 0, 0x00000000, 0xffffffff },
3515 { 0x0cc4, 0, 0x00000000, 0xffffffff },
3516 { 0x0cc8, 0, 0x00000000, 0xffffffff },
3517 { 0x0ccc, 0, 0x00000000, 0xffffffff },
3518 { 0x0cd0, 0, 0x00000000, 0xffffffff },
3519 { 0x0cd4, 0, 0x00000000, 0xffffffff },
3520 { 0x0cd8, 0, 0x00000000, 0xffffffff },
3521 { 0x0cdc, 0, 0x00000000, 0xffffffff },
3522 { 0x0ce0, 0, 0x00000000, 0xffffffff },
3523 { 0x0ce4, 0, 0x00000000, 0xffffffff },
3524 { 0x0ce8, 0, 0x00000000, 0xffffffff },
3525 { 0x0cec, 0, 0x00000000, 0xffffffff },
3526 { 0x0cf0, 0, 0x00000000, 0xffffffff },
3527 { 0x0cf4, 0, 0x00000000, 0xffffffff },
3528 { 0x0cf8, 0, 0x00000000, 0xffffffff },
3529 { 0x0cfc, 0, 0x00000000, 0xffffffff },
3530 { 0x0d00, 0, 0x00000000, 0xffffffff },
3531 { 0x0d04, 0, 0x00000000, 0xffffffff },
3532
3533 { 0x1000, 0, 0x00000000, 0x00000001 },
3534 { 0x1004, 0, 0x00000000, 0x000f0001 },
3535 { 0x1044, 0, 0x00000000, 0xffc003ff },
3536 { 0x1080, 0, 0x00000000, 0x0001ffff },
3537 { 0x1084, 0, 0x00000000, 0xffffffff },
3538 { 0x1088, 0, 0x00000000, 0xffffffff },
3539 { 0x108c, 0, 0x00000000, 0xffffffff },
3540 { 0x1090, 0, 0x00000000, 0xffffffff },
3541 { 0x1094, 0, 0x00000000, 0xffffffff },
3542 { 0x1098, 0, 0x00000000, 0xffffffff },
3543 { 0x109c, 0, 0x00000000, 0xffffffff },
3544 { 0x10a0, 0, 0x00000000, 0xffffffff },
3545
3546 { 0x1408, 0, 0x01c00800, 0x00000000 },
3547 { 0x149c, 0, 0x8000ffff, 0x00000000 },
3548 { 0x14a8, 0, 0x00000000, 0x000001ff },
5b0c76ad 3549 { 0x14ac, 0, 0x0fffffff, 0x10000000 },
b6016b76
MC		 3550 { 0x14b0, 0, 0x00000002, 0x00000001 },
3551 { 0x14b8, 0, 0x00000000, 0x00000000 },
3552 { 0x14c0, 0, 0x00000000, 0x00000009 },
3553 { 0x14c4, 0, 0x00003fff, 0x00000000 },
3554 { 0x14cc, 0, 0x00000000, 0x00000001 },
3555 { 0x14d0, 0, 0xffffffff, 0x00000000 },
3556 { 0x1500, 0, 0x00000000, 0xffffffff },
3557 { 0x1504, 0, 0x00000000, 0xffffffff },
3558 { 0x1508, 0, 0x00000000, 0xffffffff },
3559 { 0x150c, 0, 0x00000000, 0xffffffff },
3560 { 0x1510, 0, 0x00000000, 0xffffffff },
3561 { 0x1514, 0, 0x00000000, 0xffffffff },
3562 { 0x1518, 0, 0x00000000, 0xffffffff },
3563 { 0x151c, 0, 0x00000000, 0xffffffff },
3564 { 0x1520, 0, 0x00000000, 0xffffffff },
3565 { 0x1524, 0, 0x00000000, 0xffffffff },
3566 { 0x1528, 0, 0x00000000, 0xffffffff },
3567 { 0x152c, 0, 0x00000000, 0xffffffff },
3568 { 0x1530, 0, 0x00000000, 0xffffffff },
3569 { 0x1534, 0, 0x00000000, 0xffffffff },
3570 { 0x1538, 0, 0x00000000, 0xffffffff },
3571 { 0x153c, 0, 0x00000000, 0xffffffff },
3572 { 0x1540, 0, 0x00000000, 0xffffffff },
3573 { 0x1544, 0, 0x00000000, 0xffffffff },
3574 { 0x1548, 0, 0x00000000, 0xffffffff },
3575 { 0x154c, 0, 0x00000000, 0xffffffff },
3576 { 0x1550, 0, 0x00000000, 0xffffffff },
3577 { 0x1554, 0, 0x00000000, 0xffffffff },
3578 { 0x1558, 0, 0x00000000, 0xffffffff },
3579 { 0x1600, 0, 0x00000000, 0xffffffff },
3580 { 0x1604, 0, 0x00000000, 0xffffffff },
3581 { 0x1608, 0, 0x00000000, 0xffffffff },
3582 { 0x160c, 0, 0x00000000, 0xffffffff },
3583 { 0x1610, 0, 0x00000000, 0xffffffff },
3584 { 0x1614, 0, 0x00000000, 0xffffffff },
3585 { 0x1618, 0, 0x00000000, 0xffffffff },
3586 { 0x161c, 0, 0x00000000, 0xffffffff },
3587 { 0x1620, 0, 0x00000000, 0xffffffff },
3588 { 0x1624, 0, 0x00000000, 0xffffffff },
3589 { 0x1628, 0, 0x00000000, 0xffffffff },
3590 { 0x162c, 0, 0x00000000, 0xffffffff },
3591 { 0x1630, 0, 0x00000000, 0xffffffff },
3592 { 0x1634, 0, 0x00000000, 0xffffffff },
3593 { 0x1638, 0, 0x00000000, 0xffffffff },
3594 { 0x163c, 0, 0x00000000, 0xffffffff },
3595 { 0x1640, 0, 0x00000000, 0xffffffff },
3596 { 0x1644, 0, 0x00000000, 0xffffffff },
3597 { 0x1648, 0, 0x00000000, 0xffffffff },
3598 { 0x164c, 0, 0x00000000, 0xffffffff },
3599 { 0x1650, 0, 0x00000000, 0xffffffff },
3600 { 0x1654, 0, 0x00000000, 0xffffffff },
3601
3602 { 0x1800, 0, 0x00000000, 0x00000001 },
3603 { 0x1804, 0, 0x00000000, 0x00000003 },
3604 { 0x1840, 0, 0x00000000, 0xffffffff },
3605 { 0x1844, 0, 0x00000000, 0xffffffff },
3606 { 0x1848, 0, 0x00000000, 0xffffffff },
3607 { 0x184c, 0, 0x00000000, 0xffffffff },
3608 { 0x1850, 0, 0x00000000, 0xffffffff },
3609 { 0x1900, 0, 0x7ffbffff, 0x00000000 },
3610 { 0x1904, 0, 0xffffffff, 0x00000000 },
3611 { 0x190c, 0, 0xffffffff, 0x00000000 },
3612 { 0x1914, 0, 0xffffffff, 0x00000000 },
3613 { 0x191c, 0, 0xffffffff, 0x00000000 },
3614 { 0x1924, 0, 0xffffffff, 0x00000000 },
3615 { 0x192c, 0, 0xffffffff, 0x00000000 },
3616 { 0x1934, 0, 0xffffffff, 0x00000000 },
3617 { 0x193c, 0, 0xffffffff, 0x00000000 },
3618 { 0x1944, 0, 0xffffffff, 0x00000000 },
3619 { 0x194c, 0, 0xffffffff, 0x00000000 },
3620 { 0x1954, 0, 0xffffffff, 0x00000000 },
3621 { 0x195c, 0, 0xffffffff, 0x00000000 },
3622 { 0x1964, 0, 0xffffffff, 0x00000000 },
3623 { 0x196c, 0, 0xffffffff, 0x00000000 },
3624 { 0x1974, 0, 0xffffffff, 0x00000000 },
3625 { 0x197c, 0, 0xffffffff, 0x00000000 },
3626 { 0x1980, 0, 0x0700ffff, 0x00000000 },
3627
3628 { 0x1c00, 0, 0x00000000, 0x00000001 },
3629 { 0x1c04, 0, 0x00000000, 0x00000003 },
3630 { 0x1c08, 0, 0x0000000f, 0x00000000 },
3631 { 0x1c40, 0, 0x00000000, 0xffffffff },
3632 { 0x1c44, 0, 0x00000000, 0xffffffff },
3633 { 0x1c48, 0, 0x00000000, 0xffffffff },
3634 { 0x1c4c, 0, 0x00000000, 0xffffffff },
3635 { 0x1c50, 0, 0x00000000, 0xffffffff },
3636 { 0x1d00, 0, 0x7ffbffff, 0x00000000 },
3637 { 0x1d04, 0, 0xffffffff, 0x00000000 },
3638 { 0x1d0c, 0, 0xffffffff, 0x00000000 },
3639 { 0x1d14, 0, 0xffffffff, 0x00000000 },
3640 { 0x1d1c, 0, 0xffffffff, 0x00000000 },
3641 { 0x1d24, 0, 0xffffffff, 0x00000000 },
3642 { 0x1d2c, 0, 0xffffffff, 0x00000000 },
3643 { 0x1d34, 0, 0xffffffff, 0x00000000 },
3644 { 0x1d3c, 0, 0xffffffff, 0x00000000 },
3645 { 0x1d44, 0, 0xffffffff, 0x00000000 },
3646 { 0x1d4c, 0, 0xffffffff, 0x00000000 },
3647 { 0x1d54, 0, 0xffffffff, 0x00000000 },
3648 { 0x1d5c, 0, 0xffffffff, 0x00000000 },
3649 { 0x1d64, 0, 0xffffffff, 0x00000000 },
3650 { 0x1d6c, 0, 0xffffffff, 0x00000000 },
3651 { 0x1d74, 0, 0xffffffff, 0x00000000 },
3652 { 0x1d7c, 0, 0xffffffff, 0x00000000 },
3653 { 0x1d80, 0, 0x0700ffff, 0x00000000 },
3654
3655 { 0x2004, 0, 0x00000000, 0x0337000f },
3656 { 0x2008, 0, 0xffffffff, 0x00000000 },
3657 { 0x200c, 0, 0xffffffff, 0x00000000 },
3658 { 0x2010, 0, 0xffffffff, 0x00000000 },
3659 { 0x2014, 0, 0x801fff80, 0x00000000 },
3660 { 0x2018, 0, 0x000003ff, 0x00000000 },
3661
3662 { 0x2800, 0, 0x00000000, 0x00000001 },
3663 { 0x2804, 0, 0x00000000, 0x00003f01 },
3664 { 0x2808, 0, 0x0f3f3f03, 0x00000000 },
3665 { 0x2810, 0, 0xffff0000, 0x00000000 },
3666 { 0x2814, 0, 0xffff0000, 0x00000000 },
3667 { 0x2818, 0, 0xffff0000, 0x00000000 },
3668 { 0x281c, 0, 0xffff0000, 0x00000000 },
3669 { 0x2834, 0, 0xffffffff, 0x00000000 },
3670 { 0x2840, 0, 0x00000000, 0xffffffff },
3671 { 0x2844, 0, 0x00000000, 0xffffffff },
3672 { 0x2848, 0, 0xffffffff, 0x00000000 },
3673 { 0x284c, 0, 0xf800f800, 0x07ff07ff },
3674
3675 { 0x2c00, 0, 0x00000000, 0x00000011 },
3676 { 0x2c04, 0, 0x00000000, 0x00030007 },
3677
3678 { 0x3000, 0, 0x00000000, 0x00000001 },
3679 { 0x3004, 0, 0x00000000, 0x007007ff },
3680 { 0x3008, 0, 0x00000003, 0x00000000 },
3681 { 0x300c, 0, 0xffffffff, 0x00000000 },
3682 { 0x3010, 0, 0xffffffff, 0x00000000 },
3683 { 0x3014, 0, 0xffffffff, 0x00000000 },
3684 { 0x3034, 0, 0xffffffff, 0x00000000 },
3685 { 0x3038, 0, 0xffffffff, 0x00000000 },
3686 { 0x3050, 0, 0x00000001, 0x00000000 },
3687
3688 { 0x3c00, 0, 0x00000000, 0x00000001 },
3689 { 0x3c04, 0, 0x00000000, 0x00070000 },
3690 { 0x3c08, 0, 0x00007f71, 0x07f00000 },
3691 { 0x3c0c, 0, 0x1f3ffffc, 0x00000000 },
3692 { 0x3c10, 0, 0xffffffff, 0x00000000 },
3693 { 0x3c14, 0, 0x00000000, 0xffffffff },
3694 { 0x3c18, 0, 0x00000000, 0xffffffff },
3695 { 0x3c1c, 0, 0xfffff000, 0x00000000 },
3696 { 0x3c20, 0, 0xffffff00, 0x00000000 },
3697 { 0x3c24, 0, 0xffffffff, 0x00000000 },
3698 { 0x3c28, 0, 0xffffffff, 0x00000000 },
3699 { 0x3c2c, 0, 0xffffffff, 0x00000000 },
3700 { 0x3c30, 0, 0xffffffff, 0x00000000 },
3701 { 0x3c34, 0, 0xffffffff, 0x00000000 },
3702 { 0x3c38, 0, 0xffffffff, 0x00000000 },
3703 { 0x3c3c, 0, 0xffffffff, 0x00000000 },
3704 { 0x3c40, 0, 0xffffffff, 0x00000000 },
3705 { 0x3c44, 0, 0xffffffff, 0x00000000 },
3706 { 0x3c48, 0, 0xffffffff, 0x00000000 },
3707 { 0x3c4c, 0, 0xffffffff, 0x00000000 },
3708 { 0x3c50, 0, 0xffffffff, 0x00000000 },
3709 { 0x3c54, 0, 0xffffffff, 0x00000000 },
3710 { 0x3c58, 0, 0xffffffff, 0x00000000 },
3711 { 0x3c5c, 0, 0xffffffff, 0x00000000 },
3712 { 0x3c60, 0, 0xffffffff, 0x00000000 },
3713 { 0x3c64, 0, 0xffffffff, 0x00000000 },
3714 { 0x3c68, 0, 0xffffffff, 0x00000000 },
3715 { 0x3c6c, 0, 0xffffffff, 0x00000000 },
3716 { 0x3c70, 0, 0xffffffff, 0x00000000 },
3717 { 0x3c74, 0, 0x0000003f, 0x00000000 },
3718 { 0x3c78, 0, 0x00000000, 0x00000000 },
3719 { 0x3c7c, 0, 0x00000000, 0x00000000 },
3720 { 0x3c80, 0, 0x3fffffff, 0x00000000 },
3721 { 0x3c84, 0, 0x0000003f, 0x00000000 },
3722 { 0x3c88, 0, 0x00000000, 0xffffffff },
3723 { 0x3c8c, 0, 0x00000000, 0xffffffff },
3724
3725 { 0x4000, 0, 0x00000000, 0x00000001 },
3726 { 0x4004, 0, 0x00000000, 0x00030000 },
3727 { 0x4008, 0, 0x00000ff0, 0x00000000 },
3728 { 0x400c, 0, 0xffffffff, 0x00000000 },
3729 { 0x4088, 0, 0x00000000, 0x00070303 },
3730
3731 { 0x4400, 0, 0x00000000, 0x00000001 },
3732 { 0x4404, 0, 0x00000000, 0x00003f01 },
3733 { 0x4408, 0, 0x7fff00ff, 0x00000000 },
3734 { 0x440c, 0, 0xffffffff, 0x00000000 },
3735 { 0x4410, 0, 0xffff, 0x0000 },
3736 { 0x4414, 0, 0xffff, 0x0000 },
3737 { 0x4418, 0, 0xffff, 0x0000 },
3738 { 0x441c, 0, 0xffff, 0x0000 },
3739 { 0x4428, 0, 0xffffffff, 0x00000000 },
3740 { 0x442c, 0, 0xffffffff, 0x00000000 },
3741 { 0x4430, 0, 0xffffffff, 0x00000000 },
3742 { 0x4434, 0, 0xffffffff, 0x00000000 },
3743 { 0x4438, 0, 0xffffffff, 0x00000000 },
3744 { 0x443c, 0, 0xffffffff, 0x00000000 },
3745 { 0x4440, 0, 0xffffffff, 0x00000000 },
3746 { 0x4444, 0, 0xffffffff, 0x00000000 },
3747
3748 { 0x4c00, 0, 0x00000000, 0x00000001 },
3749 { 0x4c04, 0, 0x00000000, 0x0000003f },
3750 { 0x4c08, 0, 0xffffffff, 0x00000000 },
3751 { 0x4c0c, 0, 0x0007fc00, 0x00000000 },
3752 { 0x4c10, 0, 0x80003fe0, 0x00000000 },
3753 { 0x4c14, 0, 0xffffffff, 0x00000000 },
3754 { 0x4c44, 0, 0x00000000, 0x9fff9fff },
3755 { 0x4c48, 0, 0x00000000, 0xb3009fff },
3756 { 0x4c4c, 0, 0x00000000, 0x77f33b30 },
3757 { 0x4c50, 0, 0x00000000, 0xffffffff },
3758
3759 { 0x5004, 0, 0x00000000, 0x0000007f },
3760 { 0x5008, 0, 0x0f0007ff, 0x00000000 },
3761 { 0x500c, 0, 0xf800f800, 0x07ff07ff },
3762
3763 { 0x5400, 0, 0x00000008, 0x00000001 },
3764 { 0x5404, 0, 0x00000000, 0x0000003f },
3765 { 0x5408, 0, 0x0000001f, 0x00000000 },
3766 { 0x540c, 0, 0xffffffff, 0x00000000 },
3767 { 0x5410, 0, 0xffffffff, 0x00000000 },
3768 { 0x5414, 0, 0x0000ffff, 0x00000000 },
3769 { 0x5418, 0, 0x0000ffff, 0x00000000 },
3770 { 0x541c, 0, 0x0000ffff, 0x00000000 },
3771 { 0x5420, 0, 0x0000ffff, 0x00000000 },
3772 { 0x5428, 0, 0x000000ff, 0x00000000 },
3773 { 0x542c, 0, 0xff00ffff, 0x00000000 },
3774 { 0x5430, 0, 0x001fff80, 0x00000000 },
3775 { 0x5438, 0, 0xffffffff, 0x00000000 },
3776 { 0x543c, 0, 0xffffffff, 0x00000000 },
3777 { 0x5440, 0, 0xf800f800, 0x07ff07ff },
3778
3779 { 0x5c00, 0, 0x00000000, 0x00000001 },
3780 { 0x5c04, 0, 0x00000000, 0x0003000f },
3781 { 0x5c08, 0, 0x00000003, 0x00000000 },
3782 { 0x5c0c, 0, 0x0000fff8, 0x00000000 },
3783 { 0x5c10, 0, 0x00000000, 0xffffffff },
3784 { 0x5c80, 0, 0x00000000, 0x0f7113f1 },
3785 { 0x5c84, 0, 0x00000000, 0x0000f333 },
3786 { 0x5c88, 0, 0x00000000, 0x00077373 },
3787 { 0x5c8c, 0, 0x00000000, 0x0007f737 },
3788
3789 { 0x6808, 0, 0x0000ff7f, 0x00000000 },
3790 { 0x680c, 0, 0xffffffff, 0x00000000 },
3791 { 0x6810, 0, 0xffffffff, 0x00000000 },
3792 { 0x6814, 0, 0xffffffff, 0x00000000 },
3793 { 0x6818, 0, 0xffffffff, 0x00000000 },
3794 { 0x681c, 0, 0xffffffff, 0x00000000 },
3795 { 0x6820, 0, 0x00ff00ff, 0x00000000 },
3796 { 0x6824, 0, 0x00ff00ff, 0x00000000 },
3797 { 0x6828, 0, 0x00ff00ff, 0x00000000 },
3798 { 0x682c, 0, 0x03ff03ff, 0x00000000 },
3799 { 0x6830, 0, 0x03ff03ff, 0x00000000 },
3800 { 0x6834, 0, 0x03ff03ff, 0x00000000 },
3801 { 0x6838, 0, 0x03ff03ff, 0x00000000 },
3802 { 0x683c, 0, 0x0000ffff, 0x00000000 },
3803 { 0x6840, 0, 0x00000ff0, 0x00000000 },
3804 { 0x6844, 0, 0x00ffff00, 0x00000000 },
3805 { 0x684c, 0, 0xffffffff, 0x00000000 },
3806 { 0x6850, 0, 0x7f7f7f7f, 0x00000000 },
3807 { 0x6854, 0, 0x7f7f7f7f, 0x00000000 },
3808 { 0x6858, 0, 0x7f7f7f7f, 0x00000000 },
3809 { 0x685c, 0, 0x7f7f7f7f, 0x00000000 },
3810 { 0x6908, 0, 0x00000000, 0x0001ff0f },
3811 { 0x690c, 0, 0x00000000, 0x0ffe00f0 },
3812
3813 { 0xffff, 0, 0x00000000, 0x00000000 },
3814 };
3815
3816 ret = 0;
3817 for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
3818 u32 offset, rw_mask, ro_mask, save_val, val;
3819
3820 offset = (u32) reg_tbl[i].offset;
3821 rw_mask = reg_tbl[i].rw_mask;
3822 ro_mask = reg_tbl[i].ro_mask;
3823
14ab9b86 3824 save_val = readl(bp->regview + offset);
b6016b76 3825
14ab9b86 3826 writel(0, bp->regview + offset);
b6016b76 3827
14ab9b86 3828 val = readl(bp->regview + offset);
b6016b76
MC		 3829 if ((val & rw_mask) != 0) {
3830 goto reg_test_err;
3831 }
3832
3833 if ((val & ro_mask) != (save_val & ro_mask)) {
3834 goto reg_test_err;
3835 }
3836
14ab9b86 3837 writel(0xffffffff, bp->regview + offset);
b6016b76 3838
14ab9b86 3839 val = readl(bp->regview + offset);
b6016b76
MC		 3840 if ((val & rw_mask) != rw_mask) {
3841 goto reg_test_err;
3842 }
3843
3844 if ((val & ro_mask) != (save_val & ro_mask)) {
3845 goto reg_test_err;
3846 }
3847
14ab9b86 3848 writel(save_val, bp->regview + offset);
b6016b76
MC		 3849 continue;
3850
3851reg_test_err:
14ab9b86 3852 writel(save_val, bp->regview + offset);
b6016b76
MC		 3853 ret = -ENODEV;
3854 break;
3855 }
3856 return ret;
3857}
3858
3859static int
3860bnx2_do_mem_test(struct bnx2 *bp, u32 start, u32 size)
3861{
3862 static u32 test_pattern[] = { 0x00000000, 0xffffffff, 0x55555555,
3863 0xaaaaaaaa , 0xaa55aa55, 0x55aa55aa };
3864 int i;
3865
3866 for (i = 0; i < sizeof(test_pattern) / 4; i++) {
3867 u32 offset;
3868
3869 for (offset = 0; offset < size; offset += 4) {
3870
3871 REG_WR_IND(bp, start + offset, test_pattern[i]);
3872
3873 if (REG_RD_IND(bp, start + offset) !=
3874 test_pattern[i]) {
3875 return -ENODEV;
3876 }
3877 }
3878 }
3879 return 0;
3880}
3881
3882static int
3883bnx2_test_memory(struct bnx2 *bp)
3884{
3885 int ret = 0;
3886 int i;
3887 static struct {
3888 u32 offset;
3889 u32 len;
3890 } mem_tbl[] = {
3891 { 0x60000, 0x4000 },
5b0c76ad 3892 { 0xa0000, 0x3000 },
b6016b76
MC		 3893 { 0xe0000, 0x4000 },
3894 { 0x120000, 0x4000 },
3895 { 0x1a0000, 0x4000 },
3896 { 0x160000, 0x4000 },
3897 { 0xffffffff, 0 },
3898 };
3899
3900 for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
3901 if ((ret = bnx2_do_mem_test(bp, mem_tbl[i].offset,
3902 mem_tbl[i].len)) != 0) {
3903 return ret;
3904 }
3905 }
3906
3907 return ret;
3908}
3909
3910static int
3911bnx2_test_loopback(struct bnx2 *bp)
3912{
3913 unsigned int pkt_size, num_pkts, i;
3914 struct sk_buff *skb, *rx_skb;
3915 unsigned char *packet;
3916 u16 rx_start_idx, rx_idx, send_idx;
3917 u32 send_bseq, val;
3918 dma_addr_t map;
3919 struct tx_bd *txbd;
3920 struct sw_bd *rx_buf;
3921 struct l2_fhdr *rx_hdr;
3922 int ret = -ENODEV;
3923
3924 if (!netif_running(bp->dev))
3925 return -ENODEV;
3926
3927 bp->loopback = MAC_LOOPBACK;
3928 bnx2_reset_nic(bp, BNX2_DRV_MSG_CODE_DIAG);
3929 bnx2_set_mac_loopback(bp);
3930
3931 pkt_size = 1514;
3932 skb = dev_alloc_skb(pkt_size);
b6cbc3b6
JL		 3933 if (!skb)
3934 return -ENOMEM;
b6016b76
MC		 3935 packet = skb_put(skb, pkt_size);
3936 memcpy(packet, bp->mac_addr, 6);
3937 memset(packet + 6, 0x0, 8);
3938 for (i = 14; i < pkt_size; i++)
3939 packet[i] = (unsigned char) (i & 0xff);
3940
3941 map = pci_map_single(bp->pdev, skb->data, pkt_size,
3942 PCI_DMA_TODEVICE);
3943
3944 val = REG_RD(bp, BNX2_HC_COMMAND);
3945 REG_WR(bp, BNX2_HC_COMMAND, val | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
3946 REG_RD(bp, BNX2_HC_COMMAND);
3947
3948 udelay(5);
3949 rx_start_idx = bp->status_blk->status_rx_quick_consumer_index0;
3950
3951 send_idx = 0;
3952 send_bseq = 0;
3953 num_pkts = 0;
3954
3955 txbd = &bp->tx_desc_ring[send_idx];
3956
3957 txbd->tx_bd_haddr_hi = (u64) map >> 32;
3958 txbd->tx_bd_haddr_lo = (u64) map & 0xffffffff;
3959 txbd->tx_bd_mss_nbytes = pkt_size;
3960 txbd->tx_bd_vlan_tag_flags = TX_BD_FLAGS_START | TX_BD_FLAGS_END;
3961
3962 num_pkts++;
3963 send_idx = NEXT_TX_BD(send_idx);
3964
3965 send_bseq += pkt_size;
3966
3967 REG_WR16(bp, MB_TX_CID_ADDR + BNX2_L2CTX_TX_HOST_BIDX, send_idx);
3968 REG_WR(bp, MB_TX_CID_ADDR + BNX2_L2CTX_TX_HOST_BSEQ, send_bseq);
3969
3970
3971 udelay(100);
3972
3973 val = REG_RD(bp, BNX2_HC_COMMAND);
3974 REG_WR(bp, BNX2_HC_COMMAND, val | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
3975 REG_RD(bp, BNX2_HC_COMMAND);
3976
3977 udelay(5);
3978
3979 pci_unmap_single(bp->pdev, map, pkt_size, PCI_DMA_TODEVICE);
3980 dev_kfree_skb_irq(skb);
3981
3982 if (bp->status_blk->status_tx_quick_consumer_index0 != send_idx) {
3983 goto loopback_test_done;
3984 }
3985
3986 rx_idx = bp->status_blk->status_rx_quick_consumer_index0;
3987 if (rx_idx != rx_start_idx + num_pkts) {
3988 goto loopback_test_done;
3989 }
3990
3991 rx_buf = &bp->rx_buf_ring[rx_start_idx];
3992 rx_skb = rx_buf->skb;
3993
3994 rx_hdr = (struct l2_fhdr *) rx_skb->data;
3995 skb_reserve(rx_skb, bp->rx_offset);
3996
3997 pci_dma_sync_single_for_cpu(bp->pdev,
3998 pci_unmap_addr(rx_buf, mapping),
3999 bp->rx_buf_size, PCI_DMA_FROMDEVICE);
4000
ade2bfe7 4001 if (rx_hdr->l2_fhdr_status &
b6016b76
MC		 4002 (L2_FHDR_ERRORS_BAD_CRC |
4003 L2_FHDR_ERRORS_PHY_DECODE |
4004 L2_FHDR_ERRORS_ALIGNMENT |
4005 L2_FHDR_ERRORS_TOO_SHORT |
4006 L2_FHDR_ERRORS_GIANT_FRAME)) {
4007
4008 goto loopback_test_done;
4009 }
4010
4011 if ((rx_hdr->l2_fhdr_pkt_len - 4) != pkt_size) {
4012 goto loopback_test_done;
4013 }
4014
4015 for (i = 14; i < pkt_size; i++) {
4016 if (*(rx_skb->data + i) != (unsigned char) (i & 0xff)) {
4017 goto loopback_test_done;
4018 }
4019 }
4020
4021 ret = 0;
4022
4023loopback_test_done:
4024 bp->loopback = 0;
4025 return ret;
4026}
4027
4028#define NVRAM_SIZE 0x200
4029#define CRC32_RESIDUAL 0xdebb20e3
4030
4031static int
4032bnx2_test_nvram(struct bnx2 *bp)
4033{
4034 u32 buf[NVRAM_SIZE / 4];
4035 u8 *data = (u8 *) buf;
4036 int rc = 0;
4037 u32 magic, csum;
4038
4039 if ((rc = bnx2_nvram_read(bp, 0, data, 4)) != 0)
4040 goto test_nvram_done;
4041
4042 magic = be32_to_cpu(buf[0]);
4043 if (magic != 0x669955aa) {
4044 rc = -ENODEV;
4045 goto test_nvram_done;
4046 }
4047
4048 if ((rc = bnx2_nvram_read(bp, 0x100, data, NVRAM_SIZE)) != 0)
4049 goto test_nvram_done;
4050
4051 csum = ether_crc_le(0x100, data);
4052 if (csum != CRC32_RESIDUAL) {
4053 rc = -ENODEV;
4054 goto test_nvram_done;
4055 }
4056
4057 csum = ether_crc_le(0x100, data + 0x100);
4058 if (csum != CRC32_RESIDUAL) {
4059 rc = -ENODEV;
4060 }
4061
4062test_nvram_done:
4063 return rc;
4064}
4065
4066static int
4067bnx2_test_link(struct bnx2 *bp)
4068{
4069 u32 bmsr;
4070
c770a65c 4071 spin_lock_bh(&bp->phy_lock);
b6016b76
MC		 4072 bnx2_read_phy(bp, MII_BMSR, &bmsr);
4073 bnx2_read_phy(bp, MII_BMSR, &bmsr);
c770a65c 4074 spin_unlock_bh(&bp->phy_lock);
b6016b76
MC		 4075
4076 if (bmsr & BMSR_LSTATUS) {
4077 return 0;
4078 }
4079 return -ENODEV;
4080}
4081
4082static int
4083bnx2_test_intr(struct bnx2 *bp)
4084{
4085 int i;
4086 u32 val;
4087 u16 status_idx;
4088
4089 if (!netif_running(bp->dev))
4090 return -ENODEV;
4091
4092 status_idx = REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD) & 0xffff;
4093
4094 /* This register is not touched during run-time. */
4095 val = REG_RD(bp, BNX2_HC_COMMAND);
4096 REG_WR(bp, BNX2_HC_COMMAND, val | BNX2_HC_COMMAND_COAL_NOW);
4097 REG_RD(bp, BNX2_HC_COMMAND);
4098
4099 for (i = 0; i < 10; i++) {
4100 if ((REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD) & 0xffff) !=
4101 status_idx) {
4102
4103 break;
4104 }
4105
4106 msleep_interruptible(10);
4107 }
4108 if (i < 10)
4109 return 0;
4110
4111 return -ENODEV;
4112}
4113
4114static void
4115bnx2_timer(unsigned long data)
4116{
4117 struct bnx2 *bp = (struct bnx2 *) data;
4118 u32 msg;
4119
cd339a0e
MC		 4120 if (!netif_running(bp->dev))
4121 return;
4122
b6016b76
MC		 4123 if (atomic_read(&bp->intr_sem) != 0)
4124 goto bnx2_restart_timer;
4125
4126 msg = (u32) ++bp->fw_drv_pulse_wr_seq;
e3648b3d 4127 REG_WR_IND(bp, bp->shmem_base + BNX2_DRV_PULSE_MB, msg);
b6016b76
MC		 4128
4129 if ((bp->phy_flags & PHY_SERDES_FLAG) &&
4130 (CHIP_NUM(bp) == CHIP_NUM_5706)) {
b6016b76 4131
c770a65c 4132 spin_lock(&bp->phy_lock);
b6016b76
MC		 4133 if (bp->serdes_an_pending) {
4134 bp->serdes_an_pending--;
4135 }
4136 else if ((bp->link_up == 0) && (bp->autoneg & AUTONEG_SPEED)) {
4137 u32 bmcr;
4138
cd339a0e
MC		 4139 bp->current_interval = bp->timer_interval;
4140
b6016b76
MC		 4141 bnx2_read_phy(bp, MII_BMCR, &bmcr);
4142
4143 if (bmcr & BMCR_ANENABLE) {
4144 u32 phy1, phy2;
4145
4146 bnx2_write_phy(bp, 0x1c, 0x7c00);
4147 bnx2_read_phy(bp, 0x1c, &phy1);
4148
4149 bnx2_write_phy(bp, 0x17, 0x0f01);
4150 bnx2_read_phy(bp, 0x15, &phy2);
4151 bnx2_write_phy(bp, 0x17, 0x0f01);
4152 bnx2_read_phy(bp, 0x15, &phy2);
4153
4154 if ((phy1 & 0x10) && /* SIGNAL DETECT */
4155 !(phy2 & 0x20)) { /* no CONFIG */
4156
4157 bmcr &= ~BMCR_ANENABLE;
4158 bmcr |= BMCR_SPEED1000 |
4159 BMCR_FULLDPLX;
4160 bnx2_write_phy(bp, MII_BMCR, bmcr);
4161 bp->phy_flags |=
4162 PHY_PARALLEL_DETECT_FLAG;
4163 }
4164 }
4165 }
4166 else if ((bp->link_up) && (bp->autoneg & AUTONEG_SPEED) &&
4167 (bp->phy_flags & PHY_PARALLEL_DETECT_FLAG)) {
4168 u32 phy2;
4169
4170 bnx2_write_phy(bp, 0x17, 0x0f01);
4171 bnx2_read_phy(bp, 0x15, &phy2);
4172 if (phy2 & 0x20) {
4173 u32 bmcr;
4174
4175 bnx2_read_phy(bp, MII_BMCR, &bmcr);
4176 bmcr |= BMCR_ANENABLE;
4177 bnx2_write_phy(bp, MII_BMCR, bmcr);
4178
4179 bp->phy_flags &= ~PHY_PARALLEL_DETECT_FLAG;
4180
4181 }
4182 }
cd339a0e
MC		 4183 else
4184 bp->current_interval = bp->timer_interval;
b6016b76 4185
c770a65c 4186 spin_unlock(&bp->phy_lock);
b6016b76
MC		 4187 }
4188
4189bnx2_restart_timer:
cd339a0e 4190 mod_timer(&bp->timer, jiffies + bp->current_interval);
b6016b76
MC		 4191}
4192
4193/* Called with rtnl_lock */
4194static int
4195bnx2_open(struct net_device *dev)
4196{
972ec0d4 4197 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 4198 int rc;
4199
829ca9a3 4200 bnx2_set_power_state(bp, PCI_D0);
b6016b76
MC		 4201 bnx2_disable_int(bp);
4202
4203 rc = bnx2_alloc_mem(bp);
4204 if (rc)
4205 return rc;
4206
4207 if ((CHIP_ID(bp) != CHIP_ID_5706_A0) &&
4208 (CHIP_ID(bp) != CHIP_ID_5706_A1) &&
4209 !disable_msi) {
4210
4211 if (pci_enable_msi(bp->pdev) == 0) {
4212 bp->flags |= USING_MSI_FLAG;
4213 rc = request_irq(bp->pdev->irq, bnx2_msi, 0, dev->name,
4214 dev);
4215 }
4216 else {
4217 rc = request_irq(bp->pdev->irq, bnx2_interrupt,
4218 SA_SHIRQ, dev->name, dev);
4219 }
4220 }
4221 else {
4222 rc = request_irq(bp->pdev->irq, bnx2_interrupt, SA_SHIRQ,
4223 dev->name, dev);
4224 }
4225 if (rc) {
4226 bnx2_free_mem(bp);
4227 return rc;
4228 }
4229
4230 rc = bnx2_init_nic(bp);
4231
4232 if (rc) {
4233 free_irq(bp->pdev->irq, dev);
4234 if (bp->flags & USING_MSI_FLAG) {
4235 pci_disable_msi(bp->pdev);
4236 bp->flags &= ~USING_MSI_FLAG;
4237 }
4238 bnx2_free_skbs(bp);
4239 bnx2_free_mem(bp);
4240 return rc;
4241 }
4242
cd339a0e 4243 mod_timer(&bp->timer, jiffies + bp->current_interval);
b6016b76
MC		 4244
4245 atomic_set(&bp->intr_sem, 0);
4246
4247 bnx2_enable_int(bp);
4248
4249 if (bp->flags & USING_MSI_FLAG) {
4250 /* Test MSI to make sure it is working
4251 * If MSI test fails, go back to INTx mode
4252 */
4253 if (bnx2_test_intr(bp) != 0) {
4254 printk(KERN_WARNING PFX "%s: No interrupt was generated"
4255 " using MSI, switching to INTx mode. Please"
4256 " report this failure to the PCI maintainer"
4257 " and include system chipset information.\n",
4258 bp->dev->name);
4259
4260 bnx2_disable_int(bp);
4261 free_irq(bp->pdev->irq, dev);
4262 pci_disable_msi(bp->pdev);
4263 bp->flags &= ~USING_MSI_FLAG;
4264
4265 rc = bnx2_init_nic(bp);
4266
4267 if (!rc) {
4268 rc = request_irq(bp->pdev->irq, bnx2_interrupt,
4269 SA_SHIRQ, dev->name, dev);
4270 }
4271 if (rc) {
4272 bnx2_free_skbs(bp);
4273 bnx2_free_mem(bp);
4274 del_timer_sync(&bp->timer);
4275 return rc;
4276 }
4277 bnx2_enable_int(bp);
4278 }
4279 }
4280 if (bp->flags & USING_MSI_FLAG) {
4281 printk(KERN_INFO PFX "%s: using MSI\n", dev->name);
4282 }
4283
4284 netif_start_queue(dev);
4285
4286 return 0;
4287}
4288
4289static void
4290bnx2_reset_task(void *data)
4291{
4292 struct bnx2 *bp = data;
4293
afdc08b9
MC		 4294 if (!netif_running(bp->dev))
4295 return;
4296
4297 bp->in_reset_task = 1;
b6016b76
MC		 4298 bnx2_netif_stop(bp);
4299
4300 bnx2_init_nic(bp);
4301
4302 atomic_set(&bp->intr_sem, 1);
4303 bnx2_netif_start(bp);
afdc08b9 4304 bp->in_reset_task = 0;
b6016b76
MC		 4305}
4306
4307static void
4308bnx2_tx_timeout(struct net_device *dev)
4309{
972ec0d4 4310 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 4311
4312 /* This allows the netif to be shutdown gracefully before resetting */
4313 schedule_work(&bp->reset_task);
4314}
4315
4316#ifdef BCM_VLAN
4317/* Called with rtnl_lock */
4318static void
4319bnx2_vlan_rx_register(struct net_device *dev, struct vlan_group *vlgrp)
4320{
972ec0d4 4321 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 4322
4323 bnx2_netif_stop(bp);
4324
4325 bp->vlgrp = vlgrp;
4326 bnx2_set_rx_mode(dev);
4327
4328 bnx2_netif_start(bp);
4329}
4330
4331/* Called with rtnl_lock */
4332static void
4333bnx2_vlan_rx_kill_vid(struct net_device *dev, uint16_t vid)
4334{
972ec0d4 4335 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 4336
4337 bnx2_netif_stop(bp);
4338
4339 if (bp->vlgrp)
4340 bp->vlgrp->vlan_devices[vid] = NULL;
4341 bnx2_set_rx_mode(dev);
4342
4343 bnx2_netif_start(bp);
4344}
4345#endif
4346
4347/* Called with dev->xmit_lock.
4348 * hard_start_xmit is pseudo-lockless - a lock is only required when
4349 * the tx queue is full. This way, we get the benefit of lockless
4350 * operations most of the time without the complexities to handle
4351 * netif_stop_queue/wake_queue race conditions.
4352 */
4353static int
4354bnx2_start_xmit(struct sk_buff *skb, struct net_device *dev)
4355{
972ec0d4 4356 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 4357 dma_addr_t mapping;
4358 struct tx_bd *txbd;
4359 struct sw_bd *tx_buf;
4360 u32 len, vlan_tag_flags, last_frag, mss;
4361 u16 prod, ring_prod;
4362 int i;
4363
e89bbf10 4364 if (unlikely(bnx2_tx_avail(bp) < (skb_shinfo(skb)->nr_frags + 1))) {
b6016b76
MC		 4365 netif_stop_queue(dev);
4366 printk(KERN_ERR PFX "%s: BUG! Tx ring full when queue awake!\n",
4367 dev->name);
4368
4369 return NETDEV_TX_BUSY;
4370 }
4371 len = skb_headlen(skb);
4372 prod = bp->tx_prod;
4373 ring_prod = TX_RING_IDX(prod);
4374
4375 vlan_tag_flags = 0;
4376 if (skb->ip_summed == CHECKSUM_HW) {
4377 vlan_tag_flags |= TX_BD_FLAGS_TCP_UDP_CKSUM;
4378 }
4379
4380 if (bp->vlgrp != 0 && vlan_tx_tag_present(skb)) {
4381 vlan_tag_flags |=
4382 (TX_BD_FLAGS_VLAN_TAG | (vlan_tx_tag_get(skb) << 16));
4383 }
4384#ifdef BCM_TSO
4385 if ((mss = skb_shinfo(skb)->tso_size) &&
4386 (skb->len > (bp->dev->mtu + ETH_HLEN))) {
4387 u32 tcp_opt_len, ip_tcp_len;
4388
4389 if (skb_header_cloned(skb) &&
4390 pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
4391 dev_kfree_skb(skb);
4392 return NETDEV_TX_OK;
4393 }
4394
4395 tcp_opt_len = ((skb->h.th->doff - 5) * 4);
4396 vlan_tag_flags |= TX_BD_FLAGS_SW_LSO;
4397
4398 tcp_opt_len = 0;
4399 if (skb->h.th->doff > 5) {
4400 tcp_opt_len = (skb->h.th->doff - 5) << 2;
4401 }
4402 ip_tcp_len = (skb->nh.iph->ihl << 2) + sizeof(struct tcphdr);
4403
4404 skb->nh.iph->check = 0;
4405 skb->nh.iph->tot_len = ntohs(mss + ip_tcp_len + tcp_opt_len);
4406 skb->h.th->check =
4407 ~csum_tcpudp_magic(skb->nh.iph->saddr,
4408 skb->nh.iph->daddr,
4409 0, IPPROTO_TCP, 0);
4410
4411 if (tcp_opt_len || (skb->nh.iph->ihl > 5)) {
4412 vlan_tag_flags |= ((skb->nh.iph->ihl - 5) +
4413 (tcp_opt_len >> 2)) << 8;
4414 }
4415 }
4416 else
4417#endif
4418 {
4419 mss = 0;
4420 }
4421
4422 mapping = pci_map_single(bp->pdev, skb->data, len, PCI_DMA_TODEVICE);
4423
4424 tx_buf = &bp->tx_buf_ring[ring_prod];
4425 tx_buf->skb = skb;
4426 pci_unmap_addr_set(tx_buf, mapping, mapping);
4427
4428 txbd = &bp->tx_desc_ring[ring_prod];
4429
4430 txbd->tx_bd_haddr_hi = (u64) mapping >> 32;
4431 txbd->tx_bd_haddr_lo = (u64) mapping & 0xffffffff;
4432 txbd->tx_bd_mss_nbytes = len | (mss << 16);
4433 txbd->tx_bd_vlan_tag_flags = vlan_tag_flags | TX_BD_FLAGS_START;
4434
4435 last_frag = skb_shinfo(skb)->nr_frags;
4436
4437 for (i = 0; i < last_frag; i++) {
4438 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
4439
4440 prod = NEXT_TX_BD(prod);
4441 ring_prod = TX_RING_IDX(prod);
4442 txbd = &bp->tx_desc_ring[ring_prod];
4443
4444 len = frag->size;
4445 mapping = pci_map_page(bp->pdev, frag->page, frag->page_offset,
4446 len, PCI_DMA_TODEVICE);
4447 pci_unmap_addr_set(&bp->tx_buf_ring[ring_prod],
4448 mapping, mapping);
4449
4450 txbd->tx_bd_haddr_hi = (u64) mapping >> 32;
4451 txbd->tx_bd_haddr_lo = (u64) mapping & 0xffffffff;
4452 txbd->tx_bd_mss_nbytes = len | (mss << 16);
4453 txbd->tx_bd_vlan_tag_flags = vlan_tag_flags;
4454
4455 }
4456 txbd->tx_bd_vlan_tag_flags |= TX_BD_FLAGS_END;
4457
4458 prod = NEXT_TX_BD(prod);
4459 bp->tx_prod_bseq += skb->len;
4460
b6016b76
MC		 4461 REG_WR16(bp, MB_TX_CID_ADDR + BNX2_L2CTX_TX_HOST_BIDX, prod);
4462 REG_WR(bp, MB_TX_CID_ADDR + BNX2_L2CTX_TX_HOST_BSEQ, bp->tx_prod_bseq);
4463
4464 mmiowb();
4465
4466 bp->tx_prod = prod;
4467 dev->trans_start = jiffies;
4468
e89bbf10 4469 if (unlikely(bnx2_tx_avail(bp) <= MAX_SKB_FRAGS)) {
c770a65c 4470 spin_lock(&bp->tx_lock);
e89bbf10
MC		 4471 netif_stop_queue(dev);
4472
4473 if (bnx2_tx_avail(bp) > MAX_SKB_FRAGS)
4474 netif_wake_queue(dev);
c770a65c 4475 spin_unlock(&bp->tx_lock);
b6016b76
MC		 4476 }
4477
4478 return NETDEV_TX_OK;
4479}
4480
4481/* Called with rtnl_lock */
4482static int
4483bnx2_close(struct net_device *dev)
4484{
972ec0d4 4485 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 4486 u32 reset_code;
4487
afdc08b9
MC		 4488 /* Calling flush_scheduled_work() may deadlock because
4489 * linkwatch_event() may be on the workqueue and it will try to get
4490 * the rtnl_lock which we are holding.
4491 */
4492 while (bp->in_reset_task)
4493 msleep(1);
4494
b6016b76
MC		 4495 bnx2_netif_stop(bp);
4496 del_timer_sync(&bp->timer);
dda1e390
MC		 4497 if (bp->flags & NO_WOL_FLAG)
4498 reset_code = BNX2_DRV_MSG_CODE_UNLOAD;
4499 else if (bp->wol)
b6016b76
MC		 4500 reset_code = BNX2_DRV_MSG_CODE_SUSPEND_WOL;
4501 else
4502 reset_code = BNX2_DRV_MSG_CODE_SUSPEND_NO_WOL;
4503 bnx2_reset_chip(bp, reset_code);
4504 free_irq(bp->pdev->irq, dev);
4505 if (bp->flags & USING_MSI_FLAG) {
4506 pci_disable_msi(bp->pdev);
4507 bp->flags &= ~USING_MSI_FLAG;
4508 }
4509 bnx2_free_skbs(bp);
4510 bnx2_free_mem(bp);
4511 bp->link_up = 0;
4512 netif_carrier_off(bp->dev);
829ca9a3 4513 bnx2_set_power_state(bp, PCI_D3hot);
b6016b76
MC		 4514 return 0;
4515}
4516
4517#define GET_NET_STATS64(ctr) \
4518 (unsigned long) ((unsigned long) (ctr##_hi) << 32) + \
4519 (unsigned long) (ctr##_lo)
4520
4521#define GET_NET_STATS32(ctr) \
4522 (ctr##_lo)
4523
4524#if (BITS_PER_LONG == 64)
4525#define GET_NET_STATS GET_NET_STATS64
4526#else
4527#define GET_NET_STATS GET_NET_STATS32
4528#endif
4529
4530static struct net_device_stats *
4531bnx2_get_stats(struct net_device *dev)
4532{
972ec0d4 4533 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 4534 struct statistics_block *stats_blk = bp->stats_blk;
4535 struct net_device_stats *net_stats = &bp->net_stats;
4536
4537 if (bp->stats_blk == NULL) {
4538 return net_stats;
4539 }
4540 net_stats->rx_packets =
4541 GET_NET_STATS(stats_blk->stat_IfHCInUcastPkts) +
4542 GET_NET_STATS(stats_blk->stat_IfHCInMulticastPkts) +
4543 GET_NET_STATS(stats_blk->stat_IfHCInBroadcastPkts);
4544
4545 net_stats->tx_packets =
4546 GET_NET_STATS(stats_blk->stat_IfHCOutUcastPkts) +
4547 GET_NET_STATS(stats_blk->stat_IfHCOutMulticastPkts) +
4548 GET_NET_STATS(stats_blk->stat_IfHCOutBroadcastPkts);
4549
4550 net_stats->rx_bytes =
4551 GET_NET_STATS(stats_blk->stat_IfHCInOctets);
4552
4553 net_stats->tx_bytes =
4554 GET_NET_STATS(stats_blk->stat_IfHCOutOctets);
4555
4556 net_stats->multicast =
4557 GET_NET_STATS(stats_blk->stat_IfHCOutMulticastPkts);
4558
4559 net_stats->collisions =
4560 (unsigned long) stats_blk->stat_EtherStatsCollisions;
4561
4562 net_stats->rx_length_errors =
4563 (unsigned long) (stats_blk->stat_EtherStatsUndersizePkts +
4564 stats_blk->stat_EtherStatsOverrsizePkts);
4565
4566 net_stats->rx_over_errors =
4567 (unsigned long) stats_blk->stat_IfInMBUFDiscards;
4568
4569 net_stats->rx_frame_errors =
4570 (unsigned long) stats_blk->stat_Dot3StatsAlignmentErrors;
4571
4572 net_stats->rx_crc_errors =
4573 (unsigned long) stats_blk->stat_Dot3StatsFCSErrors;
4574
4575 net_stats->rx_errors = net_stats->rx_length_errors +
4576 net_stats->rx_over_errors + net_stats->rx_frame_errors +
4577 net_stats->rx_crc_errors;
4578
4579 net_stats->tx_aborted_errors =
4580 (unsigned long) (stats_blk->stat_Dot3StatsExcessiveCollisions +
4581 stats_blk->stat_Dot3StatsLateCollisions);
4582
5b0c76ad
MC		 4583 if ((CHIP_NUM(bp) == CHIP_NUM_5706) ||
4584 (CHIP_ID(bp) == CHIP_ID_5708_A0))
b6016b76
MC		 4585 net_stats->tx_carrier_errors = 0;
4586 else {
4587 net_stats->tx_carrier_errors =
4588 (unsigned long)
4589 stats_blk->stat_Dot3StatsCarrierSenseErrors;
4590 }
4591
4592 net_stats->tx_errors =
4593 (unsigned long)
4594 stats_blk->stat_emac_tx_stat_dot3statsinternalmactransmiterrors
4595 +
4596 net_stats->tx_aborted_errors +
4597 net_stats->tx_carrier_errors;
4598
4599 return net_stats;
4600}
4601
4602/* All ethtool functions called with rtnl_lock */
4603
4604static int
4605bnx2_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
4606{
972ec0d4 4607 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 4608
4609 cmd->supported = SUPPORTED_Autoneg;
4610 if (bp->phy_flags & PHY_SERDES_FLAG) {
4611 cmd->supported |= SUPPORTED_1000baseT_Full |
4612 SUPPORTED_FIBRE;
4613
4614 cmd->port = PORT_FIBRE;
4615 }
4616 else {
4617 cmd->supported |= SUPPORTED_10baseT_Half |
4618 SUPPORTED_10baseT_Full |
4619 SUPPORTED_100baseT_Half |
4620 SUPPORTED_100baseT_Full |
4621 SUPPORTED_1000baseT_Full |
4622 SUPPORTED_TP;
4623
4624 cmd->port = PORT_TP;
4625 }
4626
4627 cmd->advertising = bp->advertising;
4628
4629 if (bp->autoneg & AUTONEG_SPEED) {
4630 cmd->autoneg = AUTONEG_ENABLE;
4631 }
4632 else {
4633 cmd->autoneg = AUTONEG_DISABLE;
4634 }
4635
4636 if (netif_carrier_ok(dev)) {
4637 cmd->speed = bp->line_speed;
4638 cmd->duplex = bp->duplex;
4639 }
4640 else {
4641 cmd->speed = -1;
4642 cmd->duplex = -1;
4643 }
4644
4645 cmd->transceiver = XCVR_INTERNAL;
4646 cmd->phy_address = bp->phy_addr;
4647
4648 return 0;
4649}
4650
4651static int
4652bnx2_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
4653{
972ec0d4 4654 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 4655 u8 autoneg = bp->autoneg;
4656 u8 req_duplex = bp->req_duplex;
4657 u16 req_line_speed = bp->req_line_speed;
4658 u32 advertising = bp->advertising;
4659
4660 if (cmd->autoneg == AUTONEG_ENABLE) {
4661 autoneg |= AUTONEG_SPEED;
4662
4663 cmd->advertising &= ETHTOOL_ALL_COPPER_SPEED;
4664
4665 /* allow advertising 1 speed */
4666 if ((cmd->advertising == ADVERTISED_10baseT_Half) ||
4667 (cmd->advertising == ADVERTISED_10baseT_Full) ||
4668 (cmd->advertising == ADVERTISED_100baseT_Half) ||
4669 (cmd->advertising == ADVERTISED_100baseT_Full)) {
4670
4671 if (bp->phy_flags & PHY_SERDES_FLAG)
4672 return -EINVAL;
4673
4674 advertising = cmd->advertising;
4675
4676 }
4677 else if (cmd->advertising == ADVERTISED_1000baseT_Full) {
4678 advertising = cmd->advertising;
4679 }
4680 else if (cmd->advertising == ADVERTISED_1000baseT_Half) {
4681 return -EINVAL;
4682 }
4683 else {
4684 if (bp->phy_flags & PHY_SERDES_FLAG) {
4685 advertising = ETHTOOL_ALL_FIBRE_SPEED;
4686 }
4687 else {
4688 advertising = ETHTOOL_ALL_COPPER_SPEED;
4689 }
4690 }
4691 advertising |= ADVERTISED_Autoneg;
4692 }
4693 else {
4694 if (bp->phy_flags & PHY_SERDES_FLAG) {
4695 if ((cmd->speed != SPEED_1000) ||
4696 (cmd->duplex != DUPLEX_FULL)) {
4697 return -EINVAL;
4698 }
4699 }
4700 else if (cmd->speed == SPEED_1000) {
4701 return -EINVAL;
4702 }
4703 autoneg &= ~AUTONEG_SPEED;
4704 req_line_speed = cmd->speed;
4705 req_duplex = cmd->duplex;
4706 advertising = 0;
4707 }
4708
4709 bp->autoneg = autoneg;
4710 bp->advertising = advertising;
4711 bp->req_line_speed = req_line_speed;
4712 bp->req_duplex = req_duplex;
4713
c770a65c 4714 spin_lock_bh(&bp->phy_lock);
b6016b76
MC		 4715
4716 bnx2_setup_phy(bp);
4717
c770a65c 4718 spin_unlock_bh(&bp->phy_lock);
b6016b76
MC		 4719
4720 return 0;
4721}
4722
4723static void
4724bnx2_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
4725{
972ec0d4 4726 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 4727
4728 strcpy(info->driver, DRV_MODULE_NAME);
4729 strcpy(info->version, DRV_MODULE_VERSION);
4730 strcpy(info->bus_info, pci_name(bp->pdev));
4731 info->fw_version[0] = ((bp->fw_ver & 0xff000000) >> 24) + '0';
4732 info->fw_version[2] = ((bp->fw_ver & 0xff0000) >> 16) + '0';
4733 info->fw_version[4] = ((bp->fw_ver & 0xff00) >> 8) + '0';
4734 info->fw_version[6] = (bp->fw_ver & 0xff) + '0';
4735 info->fw_version[1] = info->fw_version[3] = info->fw_version[5] = '.';
4736 info->fw_version[7] = 0;
4737}
4738
4739static void
4740bnx2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
4741{
972ec0d4 4742 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 4743
4744 if (bp->flags & NO_WOL_FLAG) {
4745 wol->supported = 0;
4746 wol->wolopts = 0;
4747 }
4748 else {
4749 wol->supported = WAKE_MAGIC;
4750 if (bp->wol)
4751 wol->wolopts = WAKE_MAGIC;
4752 else
4753 wol->wolopts = 0;
4754 }
4755 memset(&wol->sopass, 0, sizeof(wol->sopass));
4756}
4757
4758static int
4759bnx2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
4760{
972ec0d4 4761 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 4762
4763 if (wol->wolopts & ~WAKE_MAGIC)
4764 return -EINVAL;
4765
4766 if (wol->wolopts & WAKE_MAGIC) {
4767 if (bp->flags & NO_WOL_FLAG)
4768 return -EINVAL;
4769
4770 bp->wol = 1;
4771 }
4772 else {
4773 bp->wol = 0;
4774 }
4775 return 0;
4776}
4777
4778static int
4779bnx2_nway_reset(struct net_device *dev)
4780{
972ec0d4 4781 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 4782 u32 bmcr;
4783
4784 if (!(bp->autoneg & AUTONEG_SPEED)) {
4785 return -EINVAL;
4786 }
4787
c770a65c 4788 spin_lock_bh(&bp->phy_lock);
b6016b76
MC		 4789
4790 /* Force a link down visible on the other side */
4791 if (bp->phy_flags & PHY_SERDES_FLAG) {
4792 bnx2_write_phy(bp, MII_BMCR, BMCR_LOOPBACK);
c770a65c 4793 spin_unlock_bh(&bp->phy_lock);
b6016b76
MC		 4794
4795 msleep(20);
4796
c770a65c 4797 spin_lock_bh(&bp->phy_lock);
b6016b76 4798 if (CHIP_NUM(bp) == CHIP_NUM_5706) {
cd339a0e
MC		 4799 bp->current_interval = SERDES_AN_TIMEOUT;
4800 bp->serdes_an_pending = 1;
4801 mod_timer(&bp->timer, jiffies + bp->current_interval);
b6016b76
MC		 4802 }
4803 }
4804
4805 bnx2_read_phy(bp, MII_BMCR, &bmcr);
4806 bmcr &= ~BMCR_LOOPBACK;
4807 bnx2_write_phy(bp, MII_BMCR, bmcr | BMCR_ANRESTART | BMCR_ANENABLE);
4808
c770a65c 4809 spin_unlock_bh(&bp->phy_lock);
b6016b76
MC		 4810
4811 return 0;
4812}
4813
4814static int
4815bnx2_get_eeprom_len(struct net_device *dev)
4816{
972ec0d4 4817 struct bnx2 *bp = netdev_priv(dev);
b6016b76 4818
1122db71 4819 if (bp->flash_info == NULL)
b6016b76
MC		 4820 return 0;
4821
1122db71 4822 return (int) bp->flash_size;
b6016b76
MC		 4823}
4824
4825static int
4826bnx2_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
4827 u8 *eebuf)
4828{
972ec0d4 4829 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 4830 int rc;
4831
1064e944 4832 /* parameters already validated in ethtool_get_eeprom */
b6016b76
MC		 4833
4834 rc = bnx2_nvram_read(bp, eeprom->offset, eebuf, eeprom->len);
4835
4836 return rc;
4837}
4838
4839static int
4840bnx2_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
4841 u8 *eebuf)
4842{
972ec0d4 4843 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 4844 int rc;
4845
1064e944 4846 /* parameters already validated in ethtool_set_eeprom */
b6016b76
MC		 4847
4848 rc = bnx2_nvram_write(bp, eeprom->offset, eebuf, eeprom->len);
4849
4850 return rc;
4851}
4852
4853static int
4854bnx2_get_coalesce(struct net_device *dev, struct ethtool_coalesce *coal)
4855{
972ec0d4 4856 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 4857
4858 memset(coal, 0, sizeof(struct ethtool_coalesce));
4859
4860 coal->rx_coalesce_usecs = bp->rx_ticks;
4861 coal->rx_max_coalesced_frames = bp->rx_quick_cons_trip;
4862 coal->rx_coalesce_usecs_irq = bp->rx_ticks_int;
4863 coal->rx_max_coalesced_frames_irq = bp->rx_quick_cons_trip_int;
4864
4865 coal->tx_coalesce_usecs = bp->tx_ticks;
4866 coal->tx_max_coalesced_frames = bp->tx_quick_cons_trip;
4867 coal->tx_coalesce_usecs_irq = bp->tx_ticks_int;
4868 coal->tx_max_coalesced_frames_irq = bp->tx_quick_cons_trip_int;
4869
4870 coal->stats_block_coalesce_usecs = bp->stats_ticks;
4871
4872 return 0;
4873}
4874
4875static int
4876bnx2_set_coalesce(struct net_device *dev, struct ethtool_coalesce *coal)
4877{
972ec0d4 4878 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 4879
4880 bp->rx_ticks = (u16) coal->rx_coalesce_usecs;
4881 if (bp->rx_ticks > 0x3ff) bp->rx_ticks = 0x3ff;
4882
4883 bp->rx_quick_cons_trip = (u16) coal->rx_max_coalesced_frames;
4884 if (bp->rx_quick_cons_trip > 0xff) bp->rx_quick_cons_trip = 0xff;
4885
4886 bp->rx_ticks_int = (u16) coal->rx_coalesce_usecs_irq;
4887 if (bp->rx_ticks_int > 0x3ff) bp->rx_ticks_int = 0x3ff;
4888
4889 bp->rx_quick_cons_trip_int = (u16) coal->rx_max_coalesced_frames_irq;
4890 if (bp->rx_quick_cons_trip_int > 0xff)
4891 bp->rx_quick_cons_trip_int = 0xff;
4892
4893 bp->tx_ticks = (u16) coal->tx_coalesce_usecs;
4894 if (bp->tx_ticks > 0x3ff) bp->tx_ticks = 0x3ff;
4895
4896 bp->tx_quick_cons_trip = (u16) coal->tx_max_coalesced_frames;
4897 if (bp->tx_quick_cons_trip > 0xff) bp->tx_quick_cons_trip = 0xff;
4898
4899 bp->tx_ticks_int = (u16) coal->tx_coalesce_usecs_irq;
4900 if (bp->tx_ticks_int > 0x3ff) bp->tx_ticks_int = 0x3ff;
4901
4902 bp->tx_quick_cons_trip_int = (u16) coal->tx_max_coalesced_frames_irq;
4903 if (bp->tx_quick_cons_trip_int > 0xff) bp->tx_quick_cons_trip_int =
4904 0xff;
4905
4906 bp->stats_ticks = coal->stats_block_coalesce_usecs;
4907 if (bp->stats_ticks > 0xffff00) bp->stats_ticks = 0xffff00;
4908 bp->stats_ticks &= 0xffff00;
4909
4910 if (netif_running(bp->dev)) {
4911 bnx2_netif_stop(bp);
4912 bnx2_init_nic(bp);
4913 bnx2_netif_start(bp);
4914 }
4915
4916 return 0;
4917}
4918
4919static void
4920bnx2_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
4921{
972ec0d4 4922 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 4923
4924 ering->rx_max_pending = MAX_RX_DESC_CNT;
4925 ering->rx_mini_max_pending = 0;
4926 ering->rx_jumbo_max_pending = 0;
4927
4928 ering->rx_pending = bp->rx_ring_size;
4929 ering->rx_mini_pending = 0;
4930 ering->rx_jumbo_pending = 0;
4931
4932 ering->tx_max_pending = MAX_TX_DESC_CNT;
4933 ering->tx_pending = bp->tx_ring_size;
4934}
4935
4936static int
4937bnx2_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
4938{
972ec0d4 4939 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 4940
4941 if ((ering->rx_pending > MAX_RX_DESC_CNT) ||
4942 (ering->tx_pending > MAX_TX_DESC_CNT) ||
4943 (ering->tx_pending <= MAX_SKB_FRAGS)) {
4944
4945 return -EINVAL;
4946 }
4947 bp->rx_ring_size = ering->rx_pending;
4948 bp->tx_ring_size = ering->tx_pending;
4949
4950 if (netif_running(bp->dev)) {
4951 bnx2_netif_stop(bp);
4952 bnx2_init_nic(bp);
4953 bnx2_netif_start(bp);
4954 }
4955
4956 return 0;
4957}
4958
4959static void
4960bnx2_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
4961{
972ec0d4 4962 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 4963
4964 epause->autoneg = ((bp->autoneg & AUTONEG_FLOW_CTRL) != 0);
4965 epause->rx_pause = ((bp->flow_ctrl & FLOW_CTRL_RX) != 0);
4966 epause->tx_pause = ((bp->flow_ctrl & FLOW_CTRL_TX) != 0);
4967}
4968
4969static int
4970bnx2_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
4971{
972ec0d4 4972 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 4973
4974 bp->req_flow_ctrl = 0;
4975 if (epause->rx_pause)
4976 bp->req_flow_ctrl |= FLOW_CTRL_RX;
4977 if (epause->tx_pause)
4978 bp->req_flow_ctrl |= FLOW_CTRL_TX;
4979
4980 if (epause->autoneg) {
4981 bp->autoneg |= AUTONEG_FLOW_CTRL;
4982 }
4983 else {
4984 bp->autoneg &= ~AUTONEG_FLOW_CTRL;
4985 }
4986
c770a65c 4987 spin_lock_bh(&bp->phy_lock);
b6016b76
MC		 4988
4989 bnx2_setup_phy(bp);
4990
c770a65c 4991 spin_unlock_bh(&bp->phy_lock);
b6016b76
MC		 4992
4993 return 0;
4994}
4995
4996static u32
4997bnx2_get_rx_csum(struct net_device *dev)
4998{
972ec0d4 4999 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 5000
5001 return bp->rx_csum;
5002}
5003
5004static int
5005bnx2_set_rx_csum(struct net_device *dev, u32 data)
5006{
972ec0d4 5007 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 5008
5009 bp->rx_csum = data;
5010 return 0;
5011}
5012
5013#define BNX2_NUM_STATS 45
5014
14ab9b86 5015static struct {
b6016b76
MC		 5016 char string[ETH_GSTRING_LEN];
5017} bnx2_stats_str_arr[BNX2_NUM_STATS] = {
5018 { "rx_bytes" },
5019 { "rx_error_bytes" },
5020 { "tx_bytes" },
5021 { "tx_error_bytes" },
5022 { "rx_ucast_packets" },
5023 { "rx_mcast_packets" },
5024 { "rx_bcast_packets" },
5025 { "tx_ucast_packets" },
5026 { "tx_mcast_packets" },
5027 { "tx_bcast_packets" },
5028 { "tx_mac_errors" },
5029 { "tx_carrier_errors" },
5030 { "rx_crc_errors" },
5031 { "rx_align_errors" },
5032 { "tx_single_collisions" },
5033 { "tx_multi_collisions" },
5034 { "tx_deferred" },
5035 { "tx_excess_collisions" },
5036 { "tx_late_collisions" },
5037 { "tx_total_collisions" },
5038 { "rx_fragments" },
5039 { "rx_jabbers" },
5040 { "rx_undersize_packets" },
5041 { "rx_oversize_packets" },
5042 { "rx_64_byte_packets" },
5043 { "rx_65_to_127_byte_packets" },
5044 { "rx_128_to_255_byte_packets" },
5045 { "rx_256_to_511_byte_packets" },
5046 { "rx_512_to_1023_byte_packets" },
5047 { "rx_1024_to_1522_byte_packets" },
5048 { "rx_1523_to_9022_byte_packets" },
5049 { "tx_64_byte_packets" },
5050 { "tx_65_to_127_byte_packets" },
5051 { "tx_128_to_255_byte_packets" },
5052 { "tx_256_to_511_byte_packets" },
5053 { "tx_512_to_1023_byte_packets" },
5054 { "tx_1024_to_1522_byte_packets" },
5055 { "tx_1523_to_9022_byte_packets" },
5056 { "rx_xon_frames" },
5057 { "rx_xoff_frames" },
5058 { "tx_xon_frames" },
5059 { "tx_xoff_frames" },
5060 { "rx_mac_ctrl_frames" },
5061 { "rx_filtered_packets" },
5062 { "rx_discards" },
5063};
5064
5065#define STATS_OFFSET32(offset_name) (offsetof(struct statistics_block, offset_name) / 4)
5066
14ab9b86 5067static unsigned long bnx2_stats_offset_arr[BNX2_NUM_STATS] = {
b6016b76
MC		 5068 STATS_OFFSET32(stat_IfHCInOctets_hi),
5069 STATS_OFFSET32(stat_IfHCInBadOctets_hi),
5070 STATS_OFFSET32(stat_IfHCOutOctets_hi),
5071 STATS_OFFSET32(stat_IfHCOutBadOctets_hi),
5072 STATS_OFFSET32(stat_IfHCInUcastPkts_hi),
5073 STATS_OFFSET32(stat_IfHCInMulticastPkts_hi),
5074 STATS_OFFSET32(stat_IfHCInBroadcastPkts_hi),
5075 STATS_OFFSET32(stat_IfHCOutUcastPkts_hi),
5076 STATS_OFFSET32(stat_IfHCOutMulticastPkts_hi),
5077 STATS_OFFSET32(stat_IfHCOutBroadcastPkts_hi),
5078 STATS_OFFSET32(stat_emac_tx_stat_dot3statsinternalmactransmiterrors),
5079 STATS_OFFSET32(stat_Dot3StatsCarrierSenseErrors),
5080 STATS_OFFSET32(stat_Dot3StatsFCSErrors),
5081 STATS_OFFSET32(stat_Dot3StatsAlignmentErrors),
5082 STATS_OFFSET32(stat_Dot3StatsSingleCollisionFrames),
5083 STATS_OFFSET32(stat_Dot3StatsMultipleCollisionFrames),
5084 STATS_OFFSET32(stat_Dot3StatsDeferredTransmissions),
5085 STATS_OFFSET32(stat_Dot3StatsExcessiveCollisions),
5086 STATS_OFFSET32(stat_Dot3StatsLateCollisions),
5087 STATS_OFFSET32(stat_EtherStatsCollisions),
5088 STATS_OFFSET32(stat_EtherStatsFragments),
5089 STATS_OFFSET32(stat_EtherStatsJabbers),
5090 STATS_OFFSET32(stat_EtherStatsUndersizePkts),
5091 STATS_OFFSET32(stat_EtherStatsOverrsizePkts),
5092 STATS_OFFSET32(stat_EtherStatsPktsRx64Octets),
5093 STATS_OFFSET32(stat_EtherStatsPktsRx65Octetsto127Octets),
5094 STATS_OFFSET32(stat_EtherStatsPktsRx128Octetsto255Octets),
5095 STATS_OFFSET32(stat_EtherStatsPktsRx256Octetsto511Octets),
5096 STATS_OFFSET32(stat_EtherStatsPktsRx512Octetsto1023Octets),
5097 STATS_OFFSET32(stat_EtherStatsPktsRx1024Octetsto1522Octets),
5098 STATS_OFFSET32(stat_EtherStatsPktsRx1523Octetsto9022Octets),
5099 STATS_OFFSET32(stat_EtherStatsPktsTx64Octets),
5100 STATS_OFFSET32(stat_EtherStatsPktsTx65Octetsto127Octets),
5101 STATS_OFFSET32(stat_EtherStatsPktsTx128Octetsto255Octets),
5102 STATS_OFFSET32(stat_EtherStatsPktsTx256Octetsto511Octets),
5103 STATS_OFFSET32(stat_EtherStatsPktsTx512Octetsto1023Octets),
5104 STATS_OFFSET32(stat_EtherStatsPktsTx1024Octetsto1522Octets),
5105 STATS_OFFSET32(stat_EtherStatsPktsTx1523Octetsto9022Octets),
5106 STATS_OFFSET32(stat_XonPauseFramesReceived),
5107 STATS_OFFSET32(stat_XoffPauseFramesReceived),
5108 STATS_OFFSET32(stat_OutXonSent),
5109 STATS_OFFSET32(stat_OutXoffSent),
5110 STATS_OFFSET32(stat_MacControlFramesReceived),
5111 STATS_OFFSET32(stat_IfInFramesL2FilterDiscards),
5112 STATS_OFFSET32(stat_IfInMBUFDiscards),
5113};
5114
5115/* stat_IfHCInBadOctets and stat_Dot3StatsCarrierSenseErrors are
5116 * skipped because of errata.
5117 */
14ab9b86 5118static u8 bnx2_5706_stats_len_arr[BNX2_NUM_STATS] = {
b6016b76
MC		 5119 8,0,8,8,8,8,8,8,8,8,
5120 4,0,4,4,4,4,4,4,4,4,
5121 4,4,4,4,4,4,4,4,4,4,
5122 4,4,4,4,4,4,4,4,4,4,
5123 4,4,4,4,4,
5124};
5125
5b0c76ad
MC		 5126static u8 bnx2_5708_stats_len_arr[BNX2_NUM_STATS] = {
5127 8,0,8,8,8,8,8,8,8,8,
5128 4,4,4,4,4,4,4,4,4,4,
5129 4,4,4,4,4,4,4,4,4,4,
5130 4,4,4,4,4,4,4,4,4,4,
5131 4,4,4,4,4,
5132};
5133
b6016b76
MC		 5134#define BNX2_NUM_TESTS 6
5135
14ab9b86 5136static struct {
b6016b76
MC		 5137 char string[ETH_GSTRING_LEN];
5138} bnx2_tests_str_arr[BNX2_NUM_TESTS] = {
5139 { "register_test (offline)" },
5140 { "memory_test (offline)" },
5141 { "loopback_test (offline)" },
5142 { "nvram_test (online)" },
5143 { "interrupt_test (online)" },
5144 { "link_test (online)" },
5145};
5146
5147static int
5148bnx2_self_test_count(struct net_device *dev)
5149{
5150 return BNX2_NUM_TESTS;
5151}
5152
5153static void
5154bnx2_self_test(struct net_device *dev, struct ethtool_test *etest, u64 *buf)
5155{
972ec0d4 5156 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 5157
5158 memset(buf, 0, sizeof(u64) * BNX2_NUM_TESTS);
5159 if (etest->flags & ETH_TEST_FL_OFFLINE) {
5160 bnx2_netif_stop(bp);
5161 bnx2_reset_chip(bp, BNX2_DRV_MSG_CODE_DIAG);
5162 bnx2_free_skbs(bp);
5163
5164 if (bnx2_test_registers(bp) != 0) {
5165 buf[0] = 1;
5166 etest->flags |= ETH_TEST_FL_FAILED;
5167 }
5168 if (bnx2_test_memory(bp) != 0) {
5169 buf[1] = 1;
5170 etest->flags |= ETH_TEST_FL_FAILED;
5171 }
5172 if (bnx2_test_loopback(bp) != 0) {
5173 buf[2] = 1;
5174 etest->flags |= ETH_TEST_FL_FAILED;
5175 }
5176
5177 if (!netif_running(bp->dev)) {
5178 bnx2_reset_chip(bp, BNX2_DRV_MSG_CODE_RESET);
5179 }
5180 else {
5181 bnx2_init_nic(bp);
5182 bnx2_netif_start(bp);
5183 }
5184
5185 /* wait for link up */
5186 msleep_interruptible(3000);
5187 if ((!bp->link_up) && !(bp->phy_flags & PHY_SERDES_FLAG))
5188 msleep_interruptible(4000);
5189 }
5190
5191 if (bnx2_test_nvram(bp) != 0) {
5192 buf[3] = 1;
5193 etest->flags |= ETH_TEST_FL_FAILED;
5194 }
5195 if (bnx2_test_intr(bp) != 0) {
5196 buf[4] = 1;
5197 etest->flags |= ETH_TEST_FL_FAILED;
5198 }
5199
5200 if (bnx2_test_link(bp) != 0) {
5201 buf[5] = 1;
5202 etest->flags |= ETH_TEST_FL_FAILED;
5203
5204 }
5205}
5206
5207static void
5208bnx2_get_strings(struct net_device *dev, u32 stringset, u8 *buf)
5209{
5210 switch (stringset) {
5211 case ETH_SS_STATS:
5212 memcpy(buf, bnx2_stats_str_arr,
5213 sizeof(bnx2_stats_str_arr));
5214 break;
5215 case ETH_SS_TEST:
5216 memcpy(buf, bnx2_tests_str_arr,
5217 sizeof(bnx2_tests_str_arr));
5218 break;
5219 }
5220}
5221
5222static int
5223bnx2_get_stats_count(struct net_device *dev)
5224{
5225 return BNX2_NUM_STATS;
5226}
5227
5228static void
5229bnx2_get_ethtool_stats(struct net_device *dev,
5230 struct ethtool_stats *stats, u64 *buf)
5231{
972ec0d4 5232 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 5233 int i;
5234 u32 *hw_stats = (u32 *) bp->stats_blk;
14ab9b86 5235 u8 *stats_len_arr = NULL;
b6016b76
MC		 5236
5237 if (hw_stats == NULL) {
5238 memset(buf, 0, sizeof(u64) * BNX2_NUM_STATS);
5239 return;
5240 }
5241
5b0c76ad
MC		 5242 if ((CHIP_ID(bp) == CHIP_ID_5706_A0) ||
5243 (CHIP_ID(bp) == CHIP_ID_5706_A1) ||
5244 (CHIP_ID(bp) == CHIP_ID_5706_A2) ||
5245 (CHIP_ID(bp) == CHIP_ID_5708_A0))
b6016b76 5246 stats_len_arr = bnx2_5706_stats_len_arr;
5b0c76ad
MC		 5247 else
5248 stats_len_arr = bnx2_5708_stats_len_arr;
b6016b76
MC		 5249
5250 for (i = 0; i < BNX2_NUM_STATS; i++) {
5251 if (stats_len_arr[i] == 0) {
5252 /* skip this counter */
5253 buf[i] = 0;
5254 continue;
5255 }
5256 if (stats_len_arr[i] == 4) {
5257 /* 4-byte counter */
5258 buf[i] = (u64)
5259 *(hw_stats + bnx2_stats_offset_arr[i]);
5260 continue;
5261 }
5262 /* 8-byte counter */
5263 buf[i] = (((u64) *(hw_stats +
5264 bnx2_stats_offset_arr[i])) << 32) +
5265 *(hw_stats + bnx2_stats_offset_arr[i] + 1);
5266 }
5267}
5268
5269static int
5270bnx2_phys_id(struct net_device *dev, u32 data)
5271{
972ec0d4 5272 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 5273 int i;
5274 u32 save;
5275
5276 if (data == 0)
5277 data = 2;
5278
5279 save = REG_RD(bp, BNX2_MISC_CFG);
5280 REG_WR(bp, BNX2_MISC_CFG, BNX2_MISC_CFG_LEDMODE_MAC);
5281
5282 for (i = 0; i < (data * 2); i++) {
5283 if ((i % 2) == 0) {
5284 REG_WR(bp, BNX2_EMAC_LED, BNX2_EMAC_LED_OVERRIDE);
5285 }
5286 else {
5287 REG_WR(bp, BNX2_EMAC_LED, BNX2_EMAC_LED_OVERRIDE |
5288 BNX2_EMAC_LED_1000MB_OVERRIDE |
5289 BNX2_EMAC_LED_100MB_OVERRIDE |
5290 BNX2_EMAC_LED_10MB_OVERRIDE |
5291 BNX2_EMAC_LED_TRAFFIC_OVERRIDE |
5292 BNX2_EMAC_LED_TRAFFIC);
5293 }
5294 msleep_interruptible(500);
5295 if (signal_pending(current))
5296 break;
5297 }
5298 REG_WR(bp, BNX2_EMAC_LED, 0);
5299 REG_WR(bp, BNX2_MISC_CFG, save);
5300 return 0;
5301}
5302
5303static struct ethtool_ops bnx2_ethtool_ops = {
5304 .get_settings = bnx2_get_settings,
5305 .set_settings = bnx2_set_settings,
5306 .get_drvinfo = bnx2_get_drvinfo,
5307 .get_wol = bnx2_get_wol,
5308 .set_wol = bnx2_set_wol,
5309 .nway_reset = bnx2_nway_reset,
5310 .get_link = ethtool_op_get_link,
5311 .get_eeprom_len = bnx2_get_eeprom_len,
5312 .get_eeprom = bnx2_get_eeprom,
5313 .set_eeprom = bnx2_set_eeprom,
5314 .get_coalesce = bnx2_get_coalesce,
5315 .set_coalesce = bnx2_set_coalesce,
5316 .get_ringparam = bnx2_get_ringparam,
5317 .set_ringparam = bnx2_set_ringparam,
5318 .get_pauseparam = bnx2_get_pauseparam,
5319 .set_pauseparam = bnx2_set_pauseparam,
5320 .get_rx_csum = bnx2_get_rx_csum,
5321 .set_rx_csum = bnx2_set_rx_csum,
5322 .get_tx_csum = ethtool_op_get_tx_csum,
5323 .set_tx_csum = ethtool_op_set_tx_csum,
5324 .get_sg = ethtool_op_get_sg,
5325 .set_sg = ethtool_op_set_sg,
5326#ifdef BCM_TSO
5327 .get_tso = ethtool_op_get_tso,
5328 .set_tso = ethtool_op_set_tso,
5329#endif
5330 .self_test_count = bnx2_self_test_count,
5331 .self_test = bnx2_self_test,
5332 .get_strings = bnx2_get_strings,
5333 .phys_id = bnx2_phys_id,
5334 .get_stats_count = bnx2_get_stats_count,
5335 .get_ethtool_stats = bnx2_get_ethtool_stats,
24b8e05d 5336 .get_perm_addr = ethtool_op_get_perm_addr,
b6016b76
MC		 5337};
5338
5339/* Called with rtnl_lock */
5340static int
5341bnx2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
5342{
14ab9b86 5343 struct mii_ioctl_data *data = if_mii(ifr);
972ec0d4 5344 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 5345 int err;
5346
5347 switch(cmd) {
5348 case SIOCGMIIPHY:
5349 data->phy_id = bp->phy_addr;
5350
5351 /* fallthru */
5352 case SIOCGMIIREG: {
5353 u32 mii_regval;
5354
c770a65c 5355 spin_lock_bh(&bp->phy_lock);
b6016b76 5356 err = bnx2_read_phy(bp, data->reg_num & 0x1f, &mii_regval);
c770a65c 5357 spin_unlock_bh(&bp->phy_lock);
b6016b76
MC		 5358
5359 data->val_out = mii_regval;
5360
5361 return err;
5362 }
5363
5364 case SIOCSMIIREG:
5365 if (!capable(CAP_NET_ADMIN))
5366 return -EPERM;
5367
c770a65c 5368 spin_lock_bh(&bp->phy_lock);
b6016b76 5369 err = bnx2_write_phy(bp, data->reg_num & 0x1f, data->val_in);
c770a65c 5370 spin_unlock_bh(&bp->phy_lock);
b6016b76
MC		 5371
5372 return err;
5373
5374 default:
5375 /* do nothing */
5376 break;
5377 }
5378 return -EOPNOTSUPP;
5379}
5380
5381/* Called with rtnl_lock */
5382static int
5383bnx2_change_mac_addr(struct net_device *dev, void *p)
5384{
5385 struct sockaddr *addr = p;
972ec0d4 5386 struct bnx2 *bp = netdev_priv(dev);
b6016b76 5387
73eef4cd
MC		 5388 if (!is_valid_ether_addr(addr->sa_data))
5389 return -EINVAL;
5390
b6016b76
MC		 5391 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
5392 if (netif_running(dev))
5393 bnx2_set_mac_addr(bp);
5394
5395 return 0;
5396}
5397
5398/* Called with rtnl_lock */
5399static int
5400bnx2_change_mtu(struct net_device *dev, int new_mtu)
5401{
972ec0d4 5402 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 5403
5404 if (((new_mtu + ETH_HLEN) > MAX_ETHERNET_JUMBO_PACKET_SIZE) ||
5405 ((new_mtu + ETH_HLEN) < MIN_ETHERNET_PACKET_SIZE))
5406 return -EINVAL;
5407
5408 dev->mtu = new_mtu;
5409 if (netif_running(dev)) {
5410 bnx2_netif_stop(bp);
5411
5412 bnx2_init_nic(bp);
5413
5414 bnx2_netif_start(bp);
5415 }
5416 return 0;
5417}
5418
5419#if defined(HAVE_POLL_CONTROLLER) || defined(CONFIG_NET_POLL_CONTROLLER)
5420static void
5421poll_bnx2(struct net_device *dev)
5422{
972ec0d4 5423 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 5424
5425 disable_irq(bp->pdev->irq);
5426 bnx2_interrupt(bp->pdev->irq, dev, NULL);
5427 enable_irq(bp->pdev->irq);
5428}
5429#endif
5430
5431static int __devinit
5432bnx2_init_board(struct pci_dev *pdev, struct net_device *dev)
5433{
5434 struct bnx2 *bp;
5435 unsigned long mem_len;
5436 int rc;
5437 u32 reg;
5438
5439 SET_MODULE_OWNER(dev);
5440 SET_NETDEV_DEV(dev, &pdev->dev);
972ec0d4 5441 bp = netdev_priv(dev);
b6016b76
MC		 5442
5443 bp->flags = 0;
5444 bp->phy_flags = 0;
5445
5446 /* enable device (incl. PCI PM wakeup), and bus-mastering */
5447 rc = pci_enable_device(pdev);
5448 if (rc) {
5449 printk(KERN_ERR PFX "Cannot enable PCI device, aborting.");
5450 goto err_out;
5451 }
5452
5453 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
5454 printk(KERN_ERR PFX "Cannot find PCI device base address, "
5455 "aborting.\n");
5456 rc = -ENODEV;
5457 goto err_out_disable;
5458 }
5459
5460 rc = pci_request_regions(pdev, DRV_MODULE_NAME);
5461 if (rc) {
5462 printk(KERN_ERR PFX "Cannot obtain PCI resources, aborting.\n");
5463 goto err_out_disable;
5464 }
5465
5466 pci_set_master(pdev);
5467
5468 bp->pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
5469 if (bp->pm_cap == 0) {
5470 printk(KERN_ERR PFX "Cannot find power management capability, "
5471 "aborting.\n");
5472 rc = -EIO;
5473 goto err_out_release;
5474 }
5475
5476 bp->pcix_cap = pci_find_capability(pdev, PCI_CAP_ID_PCIX);
5477 if (bp->pcix_cap == 0) {
5478 printk(KERN_ERR PFX "Cannot find PCIX capability, aborting.\n");
5479 rc = -EIO;
5480 goto err_out_release;
5481 }
5482
5483 if (pci_set_dma_mask(pdev, DMA_64BIT_MASK) == 0) {
5484 bp->flags |= USING_DAC_FLAG;
5485 if (pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK) != 0) {
5486 printk(KERN_ERR PFX "pci_set_consistent_dma_mask "
5487 "failed, aborting.\n");
5488 rc = -EIO;
5489 goto err_out_release;
5490 }
5491 }
5492 else if (pci_set_dma_mask(pdev, DMA_32BIT_MASK) != 0) {
5493 printk(KERN_ERR PFX "System does not support DMA, aborting.\n");
5494 rc = -EIO;
5495 goto err_out_release;
5496 }
5497
5498 bp->dev = dev;
5499 bp->pdev = pdev;
5500
5501 spin_lock_init(&bp->phy_lock);
5502 spin_lock_init(&bp->tx_lock);
5503 INIT_WORK(&bp->reset_task, bnx2_reset_task, bp);
5504
5505 dev->base_addr = dev->mem_start = pci_resource_start(pdev, 0);
5506 mem_len = MB_GET_CID_ADDR(17);
5507 dev->mem_end = dev->mem_start + mem_len;
5508 dev->irq = pdev->irq;
5509
5510 bp->regview = ioremap_nocache(dev->base_addr, mem_len);
5511
5512 if (!bp->regview) {
5513 printk(KERN_ERR PFX "Cannot map register space, aborting.\n");
5514 rc = -ENOMEM;
5515 goto err_out_release;
5516 }
5517
5518 /* Configure byte swap and enable write to the reg_window registers.
5519 * Rely on CPU to do target byte swapping on big endian systems
5520 * The chip's target access swapping will not swap all accesses
5521 */
5522 pci_write_config_dword(bp->pdev, BNX2_PCICFG_MISC_CONFIG,
5523 BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
5524 BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP);
5525
829ca9a3 5526 bnx2_set_power_state(bp, PCI_D0);
b6016b76
MC		 5527
5528 bp->chip_id = REG_RD(bp, BNX2_MISC_ID);
5529
b6016b76
MC		 5530 /* Get bus information. */
5531 reg = REG_RD(bp, BNX2_PCICFG_MISC_STATUS);
5532 if (reg & BNX2_PCICFG_MISC_STATUS_PCIX_DET) {
5533 u32 clkreg;
5534
5535 bp->flags |= PCIX_FLAG;
5536
5537 clkreg = REG_RD(bp, BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS);
5538
5539 clkreg &= BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET;
5540 switch (clkreg) {
5541 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ:
5542 bp->bus_speed_mhz = 133;
5543 break;
5544
5545 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ:
5546 bp->bus_speed_mhz = 100;
5547 break;
5548
5549 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ:
5550 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ:
5551 bp->bus_speed_mhz = 66;
5552 break;
5553
5554 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ:
5555 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ:
5556 bp->bus_speed_mhz = 50;
5557 break;
5558
5559 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_LOW:
5560 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ:
5561 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ:
5562 bp->bus_speed_mhz = 33;
5563 break;
5564 }
5565 }
5566 else {
5567 if (reg & BNX2_PCICFG_MISC_STATUS_M66EN)
5568 bp->bus_speed_mhz = 66;
5569 else
5570 bp->bus_speed_mhz = 33;
5571 }
5572
5573 if (reg & BNX2_PCICFG_MISC_STATUS_32BIT_DET)
5574 bp->flags |= PCI_32BIT_FLAG;
5575
5576 /* 5706A0 may falsely detect SERR and PERR. */
5577 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
5578 reg = REG_RD(bp, PCI_COMMAND);
5579 reg &= ~(PCI_COMMAND_SERR | PCI_COMMAND_PARITY);
5580 REG_WR(bp, PCI_COMMAND, reg);
5581 }
5582 else if ((CHIP_ID(bp) == CHIP_ID_5706_A1) &&
5583 !(bp->flags & PCIX_FLAG)) {
5584
5585 printk(KERN_ERR PFX "5706 A1 can only be used in a PCIX bus, "
5586 "aborting.\n");
5587 goto err_out_unmap;
5588 }
5589
5590 bnx2_init_nvram(bp);
5591
e3648b3d
MC		 5592 reg = REG_RD_IND(bp, BNX2_SHM_HDR_SIGNATURE);
5593
5594 if ((reg & BNX2_SHM_HDR_SIGNATURE_SIG_MASK) ==
5595 BNX2_SHM_HDR_SIGNATURE_SIG)
5596 bp->shmem_base = REG_RD_IND(bp, BNX2_SHM_HDR_ADDR_0);
5597 else
5598 bp->shmem_base = HOST_VIEW_SHMEM_BASE;
5599
b6016b76
MC		 5600 /* Get the permanent MAC address. First we need to make sure the
5601 * firmware is actually running.
5602 */
e3648b3d 5603 reg = REG_RD_IND(bp, bp->shmem_base + BNX2_DEV_INFO_SIGNATURE);
b6016b76
MC		 5604
5605 if ((reg & BNX2_DEV_INFO_SIGNATURE_MAGIC_MASK) !=
5606 BNX2_DEV_INFO_SIGNATURE_MAGIC) {
5607 printk(KERN_ERR PFX "Firmware not running, aborting.\n");
5608 rc = -ENODEV;
5609 goto err_out_unmap;
5610 }
5611
e3648b3d 5612 bp->fw_ver = REG_RD_IND(bp, bp->shmem_base + BNX2_DEV_INFO_BC_REV);
b6016b76 5613
e3648b3d 5614 reg = REG_RD_IND(bp, bp->shmem_base + BNX2_PORT_HW_CFG_MAC_UPPER);
b6016b76
MC		 5615 bp->mac_addr[0] = (u8) (reg >> 8);
5616 bp->mac_addr[1] = (u8) reg;
5617
e3648b3d 5618 reg = REG_RD_IND(bp, bp->shmem_base + BNX2_PORT_HW_CFG_MAC_LOWER);
b6016b76
MC		 5619 bp->mac_addr[2] = (u8) (reg >> 24);
5620 bp->mac_addr[3] = (u8) (reg >> 16);
5621 bp->mac_addr[4] = (u8) (reg >> 8);
5622 bp->mac_addr[5] = (u8) reg;
5623
5624 bp->tx_ring_size = MAX_TX_DESC_CNT;
5625 bp->rx_ring_size = 100;
5626
5627 bp->rx_csum = 1;
5628
5629 bp->rx_offset = sizeof(struct l2_fhdr) + 2;
5630
5631 bp->tx_quick_cons_trip_int = 20;
5632 bp->tx_quick_cons_trip = 20;
5633 bp->tx_ticks_int = 80;
5634 bp->tx_ticks = 80;
5635
5636 bp->rx_quick_cons_trip_int = 6;
5637 bp->rx_quick_cons_trip = 6;
5638 bp->rx_ticks_int = 18;
5639 bp->rx_ticks = 18;
5640
5641 bp->stats_ticks = 1000000 & 0xffff00;
5642
5643 bp->timer_interval = HZ;
cd339a0e 5644 bp->current_interval = HZ;
b6016b76 5645
5b0c76ad
MC		 5646 bp->phy_addr = 1;
5647
b6016b76
MC		 5648 /* Disable WOL support if we are running on a SERDES chip. */
5649 if (CHIP_BOND_ID(bp) & CHIP_BOND_ID_SERDES_BIT) {
5650 bp->phy_flags |= PHY_SERDES_FLAG;
5651 bp->flags |= NO_WOL_FLAG;
5b0c76ad
MC		 5652 if (CHIP_NUM(bp) == CHIP_NUM_5708) {
5653 bp->phy_addr = 2;
e3648b3d 5654 reg = REG_RD_IND(bp, bp->shmem_base +
5b0c76ad
MC		 5655 BNX2_SHARED_HW_CFG_CONFIG);
5656 if (reg & BNX2_SHARED_HW_CFG_PHY_2_5G)
5657 bp->phy_flags |= PHY_2_5G_CAPABLE_FLAG;
5658 }
b6016b76
MC		 5659 }
5660
dda1e390
MC		 5661 if (CHIP_NUM(bp) == CHIP_NUM_5708)
5662 bp->flags |= NO_WOL_FLAG;
5663
b6016b76
MC		 5664 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
5665 bp->tx_quick_cons_trip_int =
5666 bp->tx_quick_cons_trip;
5667 bp->tx_ticks_int = bp->tx_ticks;
5668 bp->rx_quick_cons_trip_int =
5669 bp->rx_quick_cons_trip;
5670 bp->rx_ticks_int = bp->rx_ticks;
5671 bp->comp_prod_trip_int = bp->comp_prod_trip;
5672 bp->com_ticks_int = bp->com_ticks;
5673 bp->cmd_ticks_int = bp->cmd_ticks;
5674 }
5675
5676 bp->autoneg = AUTONEG_SPEED | AUTONEG_FLOW_CTRL;
5677 bp->req_line_speed = 0;
5678 if (bp->phy_flags & PHY_SERDES_FLAG) {
5679 bp->advertising = ETHTOOL_ALL_FIBRE_SPEED | ADVERTISED_Autoneg;
cd339a0e 5680
e3648b3d 5681 reg = REG_RD_IND(bp, bp->shmem_base + BNX2_PORT_HW_CFG_CONFIG);
cd339a0e
MC		 5682 reg &= BNX2_PORT_HW_CFG_CFG_DFLT_LINK_MASK;
5683 if (reg == BNX2_PORT_HW_CFG_CFG_DFLT_LINK_1G) {
5684 bp->autoneg = 0;
5685 bp->req_line_speed = bp->line_speed = SPEED_1000;
5686 bp->req_duplex = DUPLEX_FULL;
5687 }
b6016b76
MC		 5688 }
5689 else {
5690 bp->advertising = ETHTOOL_ALL_COPPER_SPEED | ADVERTISED_Autoneg;
5691 }
5692
5693 bp->req_flow_ctrl = FLOW_CTRL_RX | FLOW_CTRL_TX;
5694
cd339a0e
MC		 5695 init_timer(&bp->timer);
5696 bp->timer.expires = RUN_AT(bp->timer_interval);
5697 bp->timer.data = (unsigned long) bp;
5698 bp->timer.function = bnx2_timer;
5699
b6016b76
MC		 5700 return 0;
5701
5702err_out_unmap:
5703 if (bp->regview) {
5704 iounmap(bp->regview);
73eef4cd 5705 bp->regview = NULL;
b6016b76
MC		 5706 }
5707
5708err_out_release:
5709 pci_release_regions(pdev);
5710
5711err_out_disable:
5712 pci_disable_device(pdev);
5713 pci_set_drvdata(pdev, NULL);
5714
5715err_out:
5716 return rc;
5717}
5718
5719static int __devinit
5720bnx2_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
5721{
5722 static int version_printed = 0;
5723 struct net_device *dev = NULL;
5724 struct bnx2 *bp;
5725 int rc, i;
5726
5727 if (version_printed++ == 0)
5728 printk(KERN_INFO "%s", version);
5729
5730 /* dev zeroed in init_etherdev */
5731 dev = alloc_etherdev(sizeof(*bp));
5732
5733 if (!dev)
5734 return -ENOMEM;
5735
5736 rc = bnx2_init_board(pdev, dev);
5737 if (rc < 0) {
5738 free_netdev(dev);
5739 return rc;
5740 }
5741
5742 dev->open = bnx2_open;
5743 dev->hard_start_xmit = bnx2_start_xmit;
5744 dev->stop = bnx2_close;
5745 dev->get_stats = bnx2_get_stats;
5746 dev->set_multicast_list = bnx2_set_rx_mode;
5747 dev->do_ioctl = bnx2_ioctl;
5748 dev->set_mac_address = bnx2_change_mac_addr;
5749 dev->change_mtu = bnx2_change_mtu;
5750 dev->tx_timeout = bnx2_tx_timeout;
5751 dev->watchdog_timeo = TX_TIMEOUT;
5752#ifdef BCM_VLAN
5753 dev->vlan_rx_register = bnx2_vlan_rx_register;
5754 dev->vlan_rx_kill_vid = bnx2_vlan_rx_kill_vid;
5755#endif
5756 dev->poll = bnx2_poll;
5757 dev->ethtool_ops = &bnx2_ethtool_ops;
5758 dev->weight = 64;
5759
972ec0d4 5760 bp = netdev_priv(dev);
b6016b76
MC		 5761
5762#if defined(HAVE_POLL_CONTROLLER) || defined(CONFIG_NET_POLL_CONTROLLER)
5763 dev->poll_controller = poll_bnx2;
5764#endif
5765
5766 if ((rc = register_netdev(dev))) {
5767 printk(KERN_ERR PFX "Cannot register net device\n");
5768 if (bp->regview)
5769 iounmap(bp->regview);
5770 pci_release_regions(pdev);
5771 pci_disable_device(pdev);
5772 pci_set_drvdata(pdev, NULL);
5773 free_netdev(dev);
5774 return rc;
5775 }
5776
5777 pci_set_drvdata(pdev, dev);
5778
5779 memcpy(dev->dev_addr, bp->mac_addr, 6);
24b8e05d 5780 memcpy(dev->perm_addr, bp->mac_addr, 6);
b6016b76
MC		 5781 bp->name = board_info[ent->driver_data].name,
5782 printk(KERN_INFO "%s: %s (%c%d) PCI%s %s %dMHz found at mem %lx, "
5783 "IRQ %d, ",
5784 dev->name,
5785 bp->name,
5786 ((CHIP_ID(bp) & 0xf000) >> 12) + 'A',
5787 ((CHIP_ID(bp) & 0x0ff0) >> 4),
5788 ((bp->flags & PCIX_FLAG) ? "-X" : ""),
5789 ((bp->flags & PCI_32BIT_FLAG) ? "32-bit" : "64-bit"),
5790 bp->bus_speed_mhz,
5791 dev->base_addr,
5792 bp->pdev->irq);
5793
5794 printk("node addr ");
5795 for (i = 0; i < 6; i++)
5796 printk("%2.2x", dev->dev_addr[i]);
5797 printk("\n");
5798
5799 dev->features |= NETIF_F_SG;
5800 if (bp->flags & USING_DAC_FLAG)
5801 dev->features |= NETIF_F_HIGHDMA;
5802 dev->features |= NETIF_F_IP_CSUM;
5803#ifdef BCM_VLAN
5804 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
5805#endif
5806#ifdef BCM_TSO
5807 dev->features |= NETIF_F_TSO;
5808#endif
5809
5810 netif_carrier_off(bp->dev);
5811
5812 return 0;
5813}
5814
5815static void __devexit
5816bnx2_remove_one(struct pci_dev *pdev)
5817{
5818 struct net_device *dev = pci_get_drvdata(pdev);
972ec0d4 5819 struct bnx2 *bp = netdev_priv(dev);
b6016b76 5820
afdc08b9
MC		 5821 flush_scheduled_work();
5822
b6016b76
MC		 5823 unregister_netdev(dev);
5824
5825 if (bp->regview)
5826 iounmap(bp->regview);
5827
5828 free_netdev(dev);
5829 pci_release_regions(pdev);
5830 pci_disable_device(pdev);
5831 pci_set_drvdata(pdev, NULL);
5832}
5833
5834static int
829ca9a3 5835bnx2_suspend(struct pci_dev *pdev, pm_message_t state)
b6016b76
MC		 5836{
5837 struct net_device *dev = pci_get_drvdata(pdev);
972ec0d4 5838 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 5839 u32 reset_code;
5840
5841 if (!netif_running(dev))
5842 return 0;
5843
5844 bnx2_netif_stop(bp);
5845 netif_device_detach(dev);
5846 del_timer_sync(&bp->timer);
dda1e390
MC		 5847 if (bp->flags & NO_WOL_FLAG)
5848 reset_code = BNX2_DRV_MSG_CODE_UNLOAD;
5849 else if (bp->wol)
b6016b76
MC		 5850 reset_code = BNX2_DRV_MSG_CODE_SUSPEND_WOL;
5851 else
5852 reset_code = BNX2_DRV_MSG_CODE_SUSPEND_NO_WOL;
5853 bnx2_reset_chip(bp, reset_code);
5854 bnx2_free_skbs(bp);
829ca9a3 5855 bnx2_set_power_state(bp, pci_choose_state(pdev, state));
b6016b76
MC		 5856 return 0;
5857}
5858
5859static int
5860bnx2_resume(struct pci_dev *pdev)
5861{
5862 struct net_device *dev = pci_get_drvdata(pdev);
972ec0d4 5863 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 5864
5865 if (!netif_running(dev))
5866 return 0;
5867
829ca9a3 5868 bnx2_set_power_state(bp, PCI_D0);
b6016b76
MC		 5869 netif_device_attach(dev);
5870 bnx2_init_nic(bp);
5871 bnx2_netif_start(bp);
5872 return 0;
5873}
5874
5875static struct pci_driver bnx2_pci_driver = {
14ab9b86
PH		 5876 .name = DRV_MODULE_NAME,
5877 .id_table = bnx2_pci_tbl,
5878 .probe = bnx2_init_one,
5879 .remove = __devexit_p(bnx2_remove_one),
5880 .suspend = bnx2_suspend,
5881 .resume = bnx2_resume,
b6016b76
MC		 5882};
5883
5884static int __init bnx2_init(void)
5885{
5886 return pci_module_init(&bnx2_pci_driver);
5887}
5888
5889static void __exit bnx2_cleanup(void)
5890{
5891 pci_unregister_driver(&bnx2_pci_driver);
5892}
5893
5894module_init(bnx2_init);
5895module_exit(bnx2_cleanup);
5896
5897
5898
Linux kernel - Deliverables
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