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bnx2: Update RV2P firmware for 5709.
[deliverable/linux.git] / drivers / net / bnx2.c
CommitLineData
b6016b76
MC		 1/* bnx2.c: Broadcom NX2 network driver.
2 *
feebb331 3 * Copyright (c) 2004-2008 Broadcom Corporation
b6016b76
MC		 4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
8 *
9 * Written by: Michael Chan (mchan@broadcom.com)
10 */
11
f2a4f052
MC		 12
13#include <linux/module.h>
14#include <linux/moduleparam.h>
15
16#include <linux/kernel.h>
17#include <linux/timer.h>
18#include <linux/errno.h>
19#include <linux/ioport.h>
20#include <linux/slab.h>
21#include <linux/vmalloc.h>
22#include <linux/interrupt.h>
23#include <linux/pci.h>
24#include <linux/init.h>
25#include <linux/netdevice.h>
26#include <linux/etherdevice.h>
27#include <linux/skbuff.h>
28#include <linux/dma-mapping.h>
1977f032 29#include <linux/bitops.h>
f2a4f052
MC		 30#include <asm/io.h>
31#include <asm/irq.h>
32#include <linux/delay.h>
33#include <asm/byteorder.h>
c86a31f4 34#include <asm/page.h>
f2a4f052
MC		 35#include <linux/time.h>
36#include <linux/ethtool.h>
37#include <linux/mii.h>
38#ifdef NETIF_F_HW_VLAN_TX
39#include <linux/if_vlan.h>
40#define BCM_VLAN 1
41#endif
f2a4f052 42#include <net/ip.h>
de081fa5 43#include <net/tcp.h>
f2a4f052 44#include <net/checksum.h>
f2a4f052
MC		 45#include <linux/workqueue.h>
46#include <linux/crc32.h>
47#include <linux/prefetch.h>
29b12174 48#include <linux/cache.h>
fba9fe91 49#include <linux/zlib.h>
f2a4f052 50
b6016b76
MC		 51#include "bnx2.h"
52#include "bnx2_fw.h"
d43584c8 53#include "bnx2_fw2.h"
b6016b76 54
110d0ef9 55#define FW_BUF_SIZE 0x10000
b3448b0b 56
b6016b76
MC		 57#define DRV_MODULE_NAME "bnx2"
58#define PFX DRV_MODULE_NAME ": "
c73b1d1f
MC		 59#define DRV_MODULE_VERSION "1.7.4"
60#define DRV_MODULE_RELDATE "February 18, 2008"
b6016b76
MC		 61
62#define RUN_AT(x) (jiffies + (x))
63
64/* Time in jiffies before concluding the transmitter is hung. */
65#define TX_TIMEOUT (5*HZ)
66
fefa8645 67static char version[] __devinitdata =
b6016b76
MC		 68 "Broadcom NetXtreme II Gigabit Ethernet Driver " DRV_MODULE_NAME " v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
69
70MODULE_AUTHOR("Michael Chan <mchan@broadcom.com>");
05d0f1cf 71MODULE_DESCRIPTION("Broadcom NetXtreme II BCM5706/5708 Driver");
b6016b76
MC		 72MODULE_LICENSE("GPL");
73MODULE_VERSION(DRV_MODULE_VERSION);
74
75static int disable_msi = 0;
76
77module_param(disable_msi, int, 0);
78MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)");
79
80typedef enum {
81 BCM5706 = 0,
82 NC370T,
83 NC370I,
84 BCM5706S,
85 NC370F,
5b0c76ad
MC		 86 BCM5708,
87 BCM5708S,
bac0dff6 88 BCM5709,
27a005b8 89 BCM5709S,
b6016b76
MC		 90} board_t;
91
92/* indexed by board_t, above */
fefa8645 93static struct {
b6016b76
MC		 94 char *name;
95} board_info[] __devinitdata = {
96 { "Broadcom NetXtreme II BCM5706 1000Base-T" },
97 { "HP NC370T Multifunction Gigabit Server Adapter" },
98 { "HP NC370i Multifunction Gigabit Server Adapter" },
99 { "Broadcom NetXtreme II BCM5706 1000Base-SX" },
100 { "HP NC370F Multifunction Gigabit Server Adapter" },
5b0c76ad
MC		 101 { "Broadcom NetXtreme II BCM5708 1000Base-T" },
102 { "Broadcom NetXtreme II BCM5708 1000Base-SX" },
bac0dff6 103 { "Broadcom NetXtreme II BCM5709 1000Base-T" },
27a005b8 104 { "Broadcom NetXtreme II BCM5709 1000Base-SX" },
b6016b76
MC		 105 };
106
107static struct pci_device_id bnx2_pci_tbl[] = {
108 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706,
109 PCI_VENDOR_ID_HP, 0x3101, 0, 0, NC370T },
110 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706,
111 PCI_VENDOR_ID_HP, 0x3106, 0, 0, NC370I },
112 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706,
113 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5706 },
5b0c76ad
MC		 114 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5708,
115 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5708 },
b6016b76
MC		 116 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706S,
117 PCI_VENDOR_ID_HP, 0x3102, 0, 0, NC370F },
118 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706S,
119 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5706S },
5b0c76ad
MC		 120 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5708S,
121 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5708S },
bac0dff6
MC		 122 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5709,
123 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5709 },
27a005b8
MC		 124 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5709S,
125 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5709S },
b6016b76
MC		 126 { 0, }
127};
128
129static struct flash_spec flash_table[] =
130{
e30372c9
MC		 131#define BUFFERED_FLAGS (BNX2_NV_BUFFERED | BNX2_NV_TRANSLATE)
132#define NONBUFFERED_FLAGS (BNX2_NV_WREN)
b6016b76 133 /* Slow EEPROM */
37137709 134 {0x00000000, 0x40830380, 0x009f0081, 0xa184a053, 0xaf000400,
e30372c9 135 BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE,
b6016b76
MC		 136 SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE,
137 "EEPROM - slow"},
37137709
MC		 138 /* Expansion entry 0001 */
139 {0x08000002, 0x4b808201, 0x00050081, 0x03840253, 0xaf020406,
e30372c9 140 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
37137709
MC		 141 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
142 "Entry 0001"},
b6016b76
MC		 143 /* Saifun SA25F010 (non-buffered flash) */
144 /* strap, cfg1, & write1 need updates */
37137709 145 {0x04000001, 0x47808201, 0x00050081, 0x03840253, 0xaf020406,
e30372c9 146 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
b6016b76
MC		 147 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*2,
148 "Non-buffered flash (128kB)"},
149 /* Saifun SA25F020 (non-buffered flash) */
150 /* strap, cfg1, & write1 need updates */
37137709 151 {0x0c000003, 0x4f808201, 0x00050081, 0x03840253, 0xaf020406,
e30372c9 152 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
b6016b76
MC		 153 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*4,
154 "Non-buffered flash (256kB)"},
37137709
MC		 155 /* Expansion entry 0100 */
156 {0x11000000, 0x53808201, 0x00050081, 0x03840253, 0xaf020406,
e30372c9 157 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
37137709
MC		 158 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
159 "Entry 0100"},
160 /* Entry 0101: ST M45PE10 (non-buffered flash, TetonII B0) */
6aa20a22 161 {0x19000002, 0x5b808201, 0x000500db, 0x03840253, 0xaf020406,
e30372c9 162 NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE,
37137709
MC		 163 ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*2,
164 "Entry 0101: ST M45PE10 (128kB non-bufferred)"},
165 /* Entry 0110: ST M45PE20 (non-buffered flash)*/
166 {0x15000001, 0x57808201, 0x000500db, 0x03840253, 0xaf020406,
e30372c9 167 NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE,
37137709
MC		 168 ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*4,
169 "Entry 0110: ST M45PE20 (256kB non-bufferred)"},
170 /* Saifun SA25F005 (non-buffered flash) */
171 /* strap, cfg1, & write1 need updates */
172 {0x1d000003, 0x5f808201, 0x00050081, 0x03840253, 0xaf020406,
e30372c9 173 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
37137709
MC		 174 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE,
175 "Non-buffered flash (64kB)"},
176 /* Fast EEPROM */
177 {0x22000000, 0x62808380, 0x009f0081, 0xa184a053, 0xaf000400,
e30372c9 178 BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE,
37137709
MC		 179 SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE,
180 "EEPROM - fast"},
181 /* Expansion entry 1001 */
182 {0x2a000002, 0x6b808201, 0x00050081, 0x03840253, 0xaf020406,
e30372c9 183 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
37137709
MC		 184 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
185 "Entry 1001"},
186 /* Expansion entry 1010 */
187 {0x26000001, 0x67808201, 0x00050081, 0x03840253, 0xaf020406,
e30372c9 188 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
37137709
MC		 189 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
190 "Entry 1010"},
191 /* ATMEL AT45DB011B (buffered flash) */
192 {0x2e000003, 0x6e808273, 0x00570081, 0x68848353, 0xaf000400,
e30372c9 193 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
37137709
MC		 194 BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE,
195 "Buffered flash (128kB)"},
196 /* Expansion entry 1100 */
197 {0x33000000, 0x73808201, 0x00050081, 0x03840253, 0xaf020406,
e30372c9 198 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
37137709
MC		 199 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
200 "Entry 1100"},
201 /* Expansion entry 1101 */
202 {0x3b000002, 0x7b808201, 0x00050081, 0x03840253, 0xaf020406,
e30372c9 203 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
37137709
MC		 204 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
205 "Entry 1101"},
206 /* Ateml Expansion entry 1110 */
207 {0x37000001, 0x76808273, 0x00570081, 0x68848353, 0xaf000400,
e30372c9 208 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
37137709
MC		 209 BUFFERED_FLASH_BYTE_ADDR_MASK, 0,
210 "Entry 1110 (Atmel)"},
211 /* ATMEL AT45DB021B (buffered flash) */
212 {0x3f000003, 0x7e808273, 0x00570081, 0x68848353, 0xaf000400,
e30372c9 213 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
37137709
MC		 214 BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE*2,
215 "Buffered flash (256kB)"},
b6016b76
MC		 216};
217
e30372c9
MC		 218static struct flash_spec flash_5709 = {
219 .flags = BNX2_NV_BUFFERED,
220 .page_bits = BCM5709_FLASH_PAGE_BITS,
221 .page_size = BCM5709_FLASH_PAGE_SIZE,
222 .addr_mask = BCM5709_FLASH_BYTE_ADDR_MASK,
223 .total_size = BUFFERED_FLASH_TOTAL_SIZE*2,
224 .name = "5709 Buffered flash (256kB)",
225};
226
b6016b76
MC		 227MODULE_DEVICE_TABLE(pci, bnx2_pci_tbl);
228
a550c99b 229static inline u32 bnx2_tx_avail(struct bnx2 *bp, struct bnx2_napi *bnapi)
e89bbf10 230{
2f8af120 231 u32 diff;
e89bbf10 232
2f8af120 233 smp_mb();
faac9c4b
MC		 234
235 /* The ring uses 256 indices for 255 entries, one of them
236 * needs to be skipped.
237 */
a550c99b 238 diff = bp->tx_prod - bnapi->tx_cons;
faac9c4b
MC		 239 if (unlikely(diff >= TX_DESC_CNT)) {
240 diff &= 0xffff;
241 if (diff == TX_DESC_CNT)
242 diff = MAX_TX_DESC_CNT;
243 }
e89bbf10
MC		 244 return (bp->tx_ring_size - diff);
245}
246
b6016b76
MC		 247static u32
248bnx2_reg_rd_ind(struct bnx2 *bp, u32 offset)
249{
1b8227c4
MC		 250 u32 val;
251
252 spin_lock_bh(&bp->indirect_lock);
b6016b76 253 REG_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, offset);
1b8227c4
MC		 254 val = REG_RD(bp, BNX2_PCICFG_REG_WINDOW);
255 spin_unlock_bh(&bp->indirect_lock);
256 return val;
b6016b76
MC		 257}
258
259static void
260bnx2_reg_wr_ind(struct bnx2 *bp, u32 offset, u32 val)
261{
1b8227c4 262 spin_lock_bh(&bp->indirect_lock);
b6016b76
MC		 263 REG_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, offset);
264 REG_WR(bp, BNX2_PCICFG_REG_WINDOW, val);
1b8227c4 265 spin_unlock_bh(&bp->indirect_lock);
b6016b76
MC		 266}
267
2726d6e1
MC		 268static void
269bnx2_shmem_wr(struct bnx2 *bp, u32 offset, u32 val)
270{
271 bnx2_reg_wr_ind(bp, bp->shmem_base + offset, val);
272}
273
274static u32
275bnx2_shmem_rd(struct bnx2 *bp, u32 offset)
276{
277 return (bnx2_reg_rd_ind(bp, bp->shmem_base + offset));
278}
279
b6016b76
MC		 280static void
281bnx2_ctx_wr(struct bnx2 *bp, u32 cid_addr, u32 offset, u32 val)
282{
283 offset += cid_addr;
1b8227c4 284 spin_lock_bh(&bp->indirect_lock);
59b47d8a
MC		 285 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
286 int i;
287
288 REG_WR(bp, BNX2_CTX_CTX_DATA, val);
289 REG_WR(bp, BNX2_CTX_CTX_CTRL,
290 offset | BNX2_CTX_CTX_CTRL_WRITE_REQ);
291 for (i = 0; i < 5; i++) {
292 u32 val;
293 val = REG_RD(bp, BNX2_CTX_CTX_CTRL);
294 if ((val & BNX2_CTX_CTX_CTRL_WRITE_REQ) == 0)
295 break;
296 udelay(5);
297 }
298 } else {
299 REG_WR(bp, BNX2_CTX_DATA_ADR, offset);
300 REG_WR(bp, BNX2_CTX_DATA, val);
301 }
1b8227c4 302 spin_unlock_bh(&bp->indirect_lock);
b6016b76
MC		 303}
304
305static int
306bnx2_read_phy(struct bnx2 *bp, u32 reg, u32 *val)
307{
308 u32 val1;
309 int i, ret;
310
583c28e5 311 if (bp->phy_flags & BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING) {
b6016b76
MC		 312 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
313 val1 &= ~BNX2_EMAC_MDIO_MODE_AUTO_POLL;
314
315 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
316 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
317
318 udelay(40);
319 }
320
321 val1 = (bp->phy_addr << 21) | (reg << 16) |
322 BNX2_EMAC_MDIO_COMM_COMMAND_READ | BNX2_EMAC_MDIO_COMM_DISEXT |
323 BNX2_EMAC_MDIO_COMM_START_BUSY;
324 REG_WR(bp, BNX2_EMAC_MDIO_COMM, val1);
325
326 for (i = 0; i < 50; i++) {
327 udelay(10);
328
329 val1 = REG_RD(bp, BNX2_EMAC_MDIO_COMM);
330 if (!(val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)) {
331 udelay(5);
332
333 val1 = REG_RD(bp, BNX2_EMAC_MDIO_COMM);
334 val1 &= BNX2_EMAC_MDIO_COMM_DATA;
335
336 break;
337 }
338 }
339
340 if (val1 & BNX2_EMAC_MDIO_COMM_START_BUSY) {
341 *val = 0x0;
342 ret = -EBUSY;
343 }
344 else {
345 *val = val1;
346 ret = 0;
347 }
348
583c28e5 349 if (bp->phy_flags & BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING) {
b6016b76
MC		 350 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
351 val1 |= BNX2_EMAC_MDIO_MODE_AUTO_POLL;
352
353 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
354 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
355
356 udelay(40);
357 }
358
359 return ret;
360}
361
362static int
363bnx2_write_phy(struct bnx2 *bp, u32 reg, u32 val)
364{
365 u32 val1;
366 int i, ret;
367
583c28e5 368 if (bp->phy_flags & BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING) {
b6016b76
MC		 369 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
370 val1 &= ~BNX2_EMAC_MDIO_MODE_AUTO_POLL;
371
372 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
373 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
374
375 udelay(40);
376 }
377
378 val1 = (bp->phy_addr << 21) | (reg << 16) | val |
379 BNX2_EMAC_MDIO_COMM_COMMAND_WRITE |
380 BNX2_EMAC_MDIO_COMM_START_BUSY | BNX2_EMAC_MDIO_COMM_DISEXT;
381 REG_WR(bp, BNX2_EMAC_MDIO_COMM, val1);
6aa20a22 382
b6016b76
MC		 383 for (i = 0; i < 50; i++) {
384 udelay(10);
385
386 val1 = REG_RD(bp, BNX2_EMAC_MDIO_COMM);
387 if (!(val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)) {
388 udelay(5);
389 break;
390 }
391 }
392
393 if (val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)
394 ret = -EBUSY;
395 else
396 ret = 0;
397
583c28e5 398 if (bp->phy_flags & BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING) {
b6016b76
MC		 399 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
400 val1 |= BNX2_EMAC_MDIO_MODE_AUTO_POLL;
401
402 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
403 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
404
405 udelay(40);
406 }
407
408 return ret;
409}
410
411static void
412bnx2_disable_int(struct bnx2 *bp)
413{
b4b36042
MC		 414 int i;
415 struct bnx2_napi *bnapi;
416
417 for (i = 0; i < bp->irq_nvecs; i++) {
418 bnapi = &bp->bnx2_napi[i];
419 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num |
420 BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
421 }
b6016b76
MC		 422 REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD);
423}
424
425static void
426bnx2_enable_int(struct bnx2 *bp)
427{
b4b36042
MC		 428 int i;
429 struct bnx2_napi *bnapi;
35efa7c1 430
b4b36042
MC		 431 for (i = 0; i < bp->irq_nvecs; i++) {
432 bnapi = &bp->bnx2_napi[i];
1269a8a6 433
b4b36042
MC		 434 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num |
435 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
436 BNX2_PCICFG_INT_ACK_CMD_MASK_INT |
437 bnapi->last_status_idx);
b6016b76 438
b4b36042
MC		 439 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num |
440 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
441 bnapi->last_status_idx);
442 }
bf5295bb 443 REG_WR(bp, BNX2_HC_COMMAND, bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW);
b6016b76
MC		 444}
445
446static void
447bnx2_disable_int_sync(struct bnx2 *bp)
448{
b4b36042
MC		 449 int i;
450
b6016b76
MC		 451 atomic_inc(&bp->intr_sem);
452 bnx2_disable_int(bp);
b4b36042
MC		 453 for (i = 0; i < bp->irq_nvecs; i++)
454 synchronize_irq(bp->irq_tbl[i].vector);
b6016b76
MC		 455}
456
35efa7c1
MC		 457static void
458bnx2_napi_disable(struct bnx2 *bp)
459{
b4b36042
MC		 460 int i;
461
462 for (i = 0; i < bp->irq_nvecs; i++)
463 napi_disable(&bp->bnx2_napi[i].napi);
35efa7c1
MC		 464}
465
466static void
467bnx2_napi_enable(struct bnx2 *bp)
468{
b4b36042
MC		 469 int i;
470
471 for (i = 0; i < bp->irq_nvecs; i++)
472 napi_enable(&bp->bnx2_napi[i].napi);
35efa7c1
MC		 473}
474
b6016b76
MC		 475static void
476bnx2_netif_stop(struct bnx2 *bp)
477{
478 bnx2_disable_int_sync(bp);
479 if (netif_running(bp->dev)) {
35efa7c1 480 bnx2_napi_disable(bp);
b6016b76
MC		 481 netif_tx_disable(bp->dev);
482 bp->dev->trans_start = jiffies; /* prevent tx timeout */
483 }
484}
485
486static void
487bnx2_netif_start(struct bnx2 *bp)
488{
489 if (atomic_dec_and_test(&bp->intr_sem)) {
490 if (netif_running(bp->dev)) {
491 netif_wake_queue(bp->dev);
35efa7c1 492 bnx2_napi_enable(bp);
b6016b76
MC		 493 bnx2_enable_int(bp);
494 }
495 }
496}
497
498static void
499bnx2_free_mem(struct bnx2 *bp)
500{
13daffa2
MC		 501 int i;
502
59b47d8a
MC		 503 for (i = 0; i < bp->ctx_pages; i++) {
504 if (bp->ctx_blk[i]) {
505 pci_free_consistent(bp->pdev, BCM_PAGE_SIZE,
506 bp->ctx_blk[i],
507 bp->ctx_blk_mapping[i]);
508 bp->ctx_blk[i] = NULL;
509 }
510 }
b6016b76 511 if (bp->status_blk) {
0f31f994 512 pci_free_consistent(bp->pdev, bp->status_stats_size,
b6016b76
MC		 513 bp->status_blk, bp->status_blk_mapping);
514 bp->status_blk = NULL;
0f31f994 515 bp->stats_blk = NULL;
b6016b76
MC		 516 }
517 if (bp->tx_desc_ring) {
e343d55c 518 pci_free_consistent(bp->pdev, TXBD_RING_SIZE,
b6016b76
MC		 519 bp->tx_desc_ring, bp->tx_desc_mapping);
520 bp->tx_desc_ring = NULL;
521 }
b4558ea9
JJ		 522 kfree(bp->tx_buf_ring);
523 bp->tx_buf_ring = NULL;
13daffa2
MC		 524 for (i = 0; i < bp->rx_max_ring; i++) {
525 if (bp->rx_desc_ring[i])
e343d55c 526 pci_free_consistent(bp->pdev, RXBD_RING_SIZE,
13daffa2
MC		 527 bp->rx_desc_ring[i],
528 bp->rx_desc_mapping[i]);
529 bp->rx_desc_ring[i] = NULL;
530 }
531 vfree(bp->rx_buf_ring);
b4558ea9 532 bp->rx_buf_ring = NULL;
47bf4246
MC		 533 for (i = 0; i < bp->rx_max_pg_ring; i++) {
534 if (bp->rx_pg_desc_ring[i])
535 pci_free_consistent(bp->pdev, RXBD_RING_SIZE,
536 bp->rx_pg_desc_ring[i],
537 bp->rx_pg_desc_mapping[i]);
538 bp->rx_pg_desc_ring[i] = NULL;
539 }
540 if (bp->rx_pg_ring)
541 vfree(bp->rx_pg_ring);
542 bp->rx_pg_ring = NULL;
b6016b76
MC		 543}
544
545static int
546bnx2_alloc_mem(struct bnx2 *bp)
547{
0f31f994 548 int i, status_blk_size;
13daffa2 549
e343d55c 550 bp->tx_buf_ring = kzalloc(SW_TXBD_RING_SIZE, GFP_KERNEL);
b6016b76
MC		 551 if (bp->tx_buf_ring == NULL)
552 return -ENOMEM;
553
e343d55c 554 bp->tx_desc_ring = pci_alloc_consistent(bp->pdev, TXBD_RING_SIZE,
b6016b76
MC		 555 &bp->tx_desc_mapping);
556 if (bp->tx_desc_ring == NULL)
557 goto alloc_mem_err;
558
e343d55c 559 bp->rx_buf_ring = vmalloc(SW_RXBD_RING_SIZE * bp->rx_max_ring);
b6016b76
MC		 560 if (bp->rx_buf_ring == NULL)
561 goto alloc_mem_err;
562
e343d55c 563 memset(bp->rx_buf_ring, 0, SW_RXBD_RING_SIZE * bp->rx_max_ring);
13daffa2
MC		 564
565 for (i = 0; i < bp->rx_max_ring; i++) {
566 bp->rx_desc_ring[i] =
e343d55c 567 pci_alloc_consistent(bp->pdev, RXBD_RING_SIZE,
13daffa2
MC		 568 &bp->rx_desc_mapping[i]);
569 if (bp->rx_desc_ring[i] == NULL)
570 goto alloc_mem_err;
571
572 }
b6016b76 573
47bf4246
MC		 574 if (bp->rx_pg_ring_size) {
575 bp->rx_pg_ring = vmalloc(SW_RXPG_RING_SIZE *
576 bp->rx_max_pg_ring);
577 if (bp->rx_pg_ring == NULL)
578 goto alloc_mem_err;
579
580 memset(bp->rx_pg_ring, 0, SW_RXPG_RING_SIZE *
581 bp->rx_max_pg_ring);
582 }
583
584 for (i = 0; i < bp->rx_max_pg_ring; i++) {
585 bp->rx_pg_desc_ring[i] =
586 pci_alloc_consistent(bp->pdev, RXBD_RING_SIZE,
587 &bp->rx_pg_desc_mapping[i]);
588 if (bp->rx_pg_desc_ring[i] == NULL)
589 goto alloc_mem_err;
590
591 }
592
0f31f994
MC		 593 /* Combine status and statistics blocks into one allocation. */
594 status_blk_size = L1_CACHE_ALIGN(sizeof(struct status_block));
f86e82fb 595 if (bp->flags & BNX2_FLAG_MSIX_CAP)
b4b36042
MC		 596 status_blk_size = L1_CACHE_ALIGN(BNX2_MAX_MSIX_HW_VEC *
597 BNX2_SBLK_MSIX_ALIGN_SIZE);
0f31f994
MC		 598 bp->status_stats_size = status_blk_size +
599 sizeof(struct statistics_block);
600
601 bp->status_blk = pci_alloc_consistent(bp->pdev, bp->status_stats_size,
b6016b76
MC		 602 &bp->status_blk_mapping);
603 if (bp->status_blk == NULL)
604 goto alloc_mem_err;
605
0f31f994 606 memset(bp->status_blk, 0, bp->status_stats_size);
b6016b76 607
b4b36042 608 bp->bnx2_napi[0].status_blk = bp->status_blk;
f86e82fb 609 if (bp->flags & BNX2_FLAG_MSIX_CAP) {
b4b36042
MC		 610 for (i = 1; i < BNX2_MAX_MSIX_VEC; i++) {
611 struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
612
57851d84 613 bnapi->status_blk_msix = (void *)
b4b36042
MC		 614 ((unsigned long) bp->status_blk +
615 BNX2_SBLK_MSIX_ALIGN_SIZE * i);
616 bnapi->int_num = i << 24;
617 }
618 }
35efa7c1 619
0f31f994
MC		 620 bp->stats_blk = (void *) ((unsigned long) bp->status_blk +
621 status_blk_size);
b6016b76 622
0f31f994 623 bp->stats_blk_mapping = bp->status_blk_mapping + status_blk_size;
b6016b76 624
59b47d8a
MC		 625 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
626 bp->ctx_pages = 0x2000 / BCM_PAGE_SIZE;
627 if (bp->ctx_pages == 0)
628 bp->ctx_pages = 1;
629 for (i = 0; i < bp->ctx_pages; i++) {
630 bp->ctx_blk[i] = pci_alloc_consistent(bp->pdev,
631 BCM_PAGE_SIZE,
632 &bp->ctx_blk_mapping[i]);
633 if (bp->ctx_blk[i] == NULL)
634 goto alloc_mem_err;
635 }
636 }
b6016b76
MC		 637 return 0;
638
639alloc_mem_err:
640 bnx2_free_mem(bp);
641 return -ENOMEM;
642}
643
e3648b3d
MC		 644static void
645bnx2_report_fw_link(struct bnx2 *bp)
646{
647 u32 fw_link_status = 0;
648
583c28e5 649 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
0d8a6571
MC		 650 return;
651
e3648b3d
MC		 652 if (bp->link_up) {
653 u32 bmsr;
654
655 switch (bp->line_speed) {
656 case SPEED_10:
657 if (bp->duplex == DUPLEX_HALF)
658 fw_link_status = BNX2_LINK_STATUS_10HALF;
659 else
660 fw_link_status = BNX2_LINK_STATUS_10FULL;
661 break;
662 case SPEED_100:
663 if (bp->duplex == DUPLEX_HALF)
664 fw_link_status = BNX2_LINK_STATUS_100HALF;
665 else
666 fw_link_status = BNX2_LINK_STATUS_100FULL;
667 break;
668 case SPEED_1000:
669 if (bp->duplex == DUPLEX_HALF)
670 fw_link_status = BNX2_LINK_STATUS_1000HALF;
671 else
672 fw_link_status = BNX2_LINK_STATUS_1000FULL;
673 break;
674 case SPEED_2500:
675 if (bp->duplex == DUPLEX_HALF)
676 fw_link_status = BNX2_LINK_STATUS_2500HALF;
677 else
678 fw_link_status = BNX2_LINK_STATUS_2500FULL;
679 break;
680 }
681
682 fw_link_status |= BNX2_LINK_STATUS_LINK_UP;
683
684 if (bp->autoneg) {
685 fw_link_status |= BNX2_LINK_STATUS_AN_ENABLED;
686
ca58c3af
MC		 687 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
688 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
e3648b3d
MC		 689
690 if (!(bmsr & BMSR_ANEGCOMPLETE) ||
583c28e5 691 bp->phy_flags & BNX2_PHY_FLAG_PARALLEL_DETECT)
e3648b3d
MC		 692 fw_link_status |= BNX2_LINK_STATUS_PARALLEL_DET;
693 else
694 fw_link_status |= BNX2_LINK_STATUS_AN_COMPLETE;
695 }
696 }
697 else
698 fw_link_status = BNX2_LINK_STATUS_LINK_DOWN;
699
2726d6e1 700 bnx2_shmem_wr(bp, BNX2_LINK_STATUS, fw_link_status);
e3648b3d
MC		 701}
702
9b1084b8
MC		 703static char *
704bnx2_xceiver_str(struct bnx2 *bp)
705{
706 return ((bp->phy_port == PORT_FIBRE) ? "SerDes" :
583c28e5 707 ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) ? "Remote Copper" :
9b1084b8
MC		 708 "Copper"));
709}
710
b6016b76
MC		 711static void
712bnx2_report_link(struct bnx2 *bp)
713{
714 if (bp->link_up) {
715 netif_carrier_on(bp->dev);
9b1084b8
MC		 716 printk(KERN_INFO PFX "%s NIC %s Link is Up, ", bp->dev->name,
717 bnx2_xceiver_str(bp));
b6016b76
MC		 718
719 printk("%d Mbps ", bp->line_speed);
720
721 if (bp->duplex == DUPLEX_FULL)
722 printk("full duplex");
723 else
724 printk("half duplex");
725
726 if (bp->flow_ctrl) {
727 if (bp->flow_ctrl & FLOW_CTRL_RX) {
728 printk(", receive ");
729 if (bp->flow_ctrl & FLOW_CTRL_TX)
730 printk("& transmit ");
731 }
732 else {
733 printk(", transmit ");
734 }
735 printk("flow control ON");
736 }
737 printk("\n");
738 }
739 else {
740 netif_carrier_off(bp->dev);
9b1084b8
MC		 741 printk(KERN_ERR PFX "%s NIC %s Link is Down\n", bp->dev->name,
742 bnx2_xceiver_str(bp));
b6016b76 743 }
e3648b3d
MC		 744
745 bnx2_report_fw_link(bp);
b6016b76
MC		 746}
747
748static void
749bnx2_resolve_flow_ctrl(struct bnx2 *bp)
750{
751 u32 local_adv, remote_adv;
752
753 bp->flow_ctrl = 0;
6aa20a22 754 if ((bp->autoneg & (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) !=
b6016b76
MC		 755 (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) {
756
757 if (bp->duplex == DUPLEX_FULL) {
758 bp->flow_ctrl = bp->req_flow_ctrl;
759 }
760 return;
761 }
762
763 if (bp->duplex != DUPLEX_FULL) {
764 return;
765 }
766
583c28e5 767 if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
5b0c76ad
MC		 768 (CHIP_NUM(bp) == CHIP_NUM_5708)) {
769 u32 val;
770
771 bnx2_read_phy(bp, BCM5708S_1000X_STAT1, &val);
772 if (val & BCM5708S_1000X_STAT1_TX_PAUSE)
773 bp->flow_ctrl |= FLOW_CTRL_TX;
774 if (val & BCM5708S_1000X_STAT1_RX_PAUSE)
775 bp->flow_ctrl |= FLOW_CTRL_RX;
776 return;
777 }
778
ca58c3af
MC		 779 bnx2_read_phy(bp, bp->mii_adv, &local_adv);
780 bnx2_read_phy(bp, bp->mii_lpa, &remote_adv);
b6016b76 781
583c28e5 782 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
b6016b76
MC		 783 u32 new_local_adv = 0;
784 u32 new_remote_adv = 0;
785
786 if (local_adv & ADVERTISE_1000XPAUSE)
787 new_local_adv |= ADVERTISE_PAUSE_CAP;
788 if (local_adv & ADVERTISE_1000XPSE_ASYM)
789 new_local_adv |= ADVERTISE_PAUSE_ASYM;
790 if (remote_adv & ADVERTISE_1000XPAUSE)
791 new_remote_adv |= ADVERTISE_PAUSE_CAP;
792 if (remote_adv & ADVERTISE_1000XPSE_ASYM)
793 new_remote_adv |= ADVERTISE_PAUSE_ASYM;
794
795 local_adv = new_local_adv;
796 remote_adv = new_remote_adv;
797 }
798
799 /* See Table 28B-3 of 802.3ab-1999 spec. */
800 if (local_adv & ADVERTISE_PAUSE_CAP) {
801 if(local_adv & ADVERTISE_PAUSE_ASYM) {
802 if (remote_adv & ADVERTISE_PAUSE_CAP) {
803 bp->flow_ctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
804 }
805 else if (remote_adv & ADVERTISE_PAUSE_ASYM) {
806 bp->flow_ctrl = FLOW_CTRL_RX;
807 }
808 }
809 else {
810 if (remote_adv & ADVERTISE_PAUSE_CAP) {
811 bp->flow_ctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
812 }
813 }
814 }
815 else if (local_adv & ADVERTISE_PAUSE_ASYM) {
816 if ((remote_adv & ADVERTISE_PAUSE_CAP) &&
817 (remote_adv & ADVERTISE_PAUSE_ASYM)) {
818
819 bp->flow_ctrl = FLOW_CTRL_TX;
820 }
821 }
822}
823
27a005b8
MC		 824static int
825bnx2_5709s_linkup(struct bnx2 *bp)
826{
827 u32 val, speed;
828
829 bp->link_up = 1;
830
831 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_GP_STATUS);
832 bnx2_read_phy(bp, MII_BNX2_GP_TOP_AN_STATUS1, &val);
833 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
834
835 if ((bp->autoneg & AUTONEG_SPEED) == 0) {
836 bp->line_speed = bp->req_line_speed;
837 bp->duplex = bp->req_duplex;
838 return 0;
839 }
840 speed = val & MII_BNX2_GP_TOP_AN_SPEED_MSK;
841 switch (speed) {
842 case MII_BNX2_GP_TOP_AN_SPEED_10:
843 bp->line_speed = SPEED_10;
844 break;
845 case MII_BNX2_GP_TOP_AN_SPEED_100:
846 bp->line_speed = SPEED_100;
847 break;
848 case MII_BNX2_GP_TOP_AN_SPEED_1G:
849 case MII_BNX2_GP_TOP_AN_SPEED_1GKV:
850 bp->line_speed = SPEED_1000;
851 break;
852 case MII_BNX2_GP_TOP_AN_SPEED_2_5G:
853 bp->line_speed = SPEED_2500;
854 break;
855 }
856 if (val & MII_BNX2_GP_TOP_AN_FD)
857 bp->duplex = DUPLEX_FULL;
858 else
859 bp->duplex = DUPLEX_HALF;
860 return 0;
861}
862
b6016b76 863static int
5b0c76ad
MC		 864bnx2_5708s_linkup(struct bnx2 *bp)
865{
866 u32 val;
867
868 bp->link_up = 1;
869 bnx2_read_phy(bp, BCM5708S_1000X_STAT1, &val);
870 switch (val & BCM5708S_1000X_STAT1_SPEED_MASK) {
871 case BCM5708S_1000X_STAT1_SPEED_10:
872 bp->line_speed = SPEED_10;
873 break;
874 case BCM5708S_1000X_STAT1_SPEED_100:
875 bp->line_speed = SPEED_100;
876 break;
877 case BCM5708S_1000X_STAT1_SPEED_1G:
878 bp->line_speed = SPEED_1000;
879 break;
880 case BCM5708S_1000X_STAT1_SPEED_2G5:
881 bp->line_speed = SPEED_2500;
882 break;
883 }
884 if (val & BCM5708S_1000X_STAT1_FD)
885 bp->duplex = DUPLEX_FULL;
886 else
887 bp->duplex = DUPLEX_HALF;
888
889 return 0;
890}
891
892static int
893bnx2_5706s_linkup(struct bnx2 *bp)
b6016b76
MC		 894{
895 u32 bmcr, local_adv, remote_adv, common;
896
897 bp->link_up = 1;
898 bp->line_speed = SPEED_1000;
899
ca58c3af 900 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
b6016b76
MC		 901 if (bmcr & BMCR_FULLDPLX) {
902 bp->duplex = DUPLEX_FULL;
903 }
904 else {
905 bp->duplex = DUPLEX_HALF;
906 }
907
908 if (!(bmcr & BMCR_ANENABLE)) {
909 return 0;
910 }
911
ca58c3af
MC		 912 bnx2_read_phy(bp, bp->mii_adv, &local_adv);
913 bnx2_read_phy(bp, bp->mii_lpa, &remote_adv);
b6016b76
MC		 914
915 common = local_adv & remote_adv;
916 if (common & (ADVERTISE_1000XHALF | ADVERTISE_1000XFULL)) {
917
918 if (common & ADVERTISE_1000XFULL) {
919 bp->duplex = DUPLEX_FULL;
920 }
921 else {
922 bp->duplex = DUPLEX_HALF;
923 }
924 }
925
926 return 0;
927}
928
929static int
930bnx2_copper_linkup(struct bnx2 *bp)
931{
932 u32 bmcr;
933
ca58c3af 934 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
b6016b76
MC		 935 if (bmcr & BMCR_ANENABLE) {
936 u32 local_adv, remote_adv, common;
937
938 bnx2_read_phy(bp, MII_CTRL1000, &local_adv);
939 bnx2_read_phy(bp, MII_STAT1000, &remote_adv);
940
941 common = local_adv & (remote_adv >> 2);
942 if (common & ADVERTISE_1000FULL) {
943 bp->line_speed = SPEED_1000;
944 bp->duplex = DUPLEX_FULL;
945 }
946 else if (common & ADVERTISE_1000HALF) {
947 bp->line_speed = SPEED_1000;
948 bp->duplex = DUPLEX_HALF;
949 }
950 else {
ca58c3af
MC		 951 bnx2_read_phy(bp, bp->mii_adv, &local_adv);
952 bnx2_read_phy(bp, bp->mii_lpa, &remote_adv);
b6016b76
MC		 953
954 common = local_adv & remote_adv;
955 if (common & ADVERTISE_100FULL) {
956 bp->line_speed = SPEED_100;
957 bp->duplex = DUPLEX_FULL;
958 }
959 else if (common & ADVERTISE_100HALF) {
960 bp->line_speed = SPEED_100;
961 bp->duplex = DUPLEX_HALF;
962 }
963 else if (common & ADVERTISE_10FULL) {
964 bp->line_speed = SPEED_10;
965 bp->duplex = DUPLEX_FULL;
966 }
967 else if (common & ADVERTISE_10HALF) {
968 bp->line_speed = SPEED_10;
969 bp->duplex = DUPLEX_HALF;
970 }
971 else {
972 bp->line_speed = 0;
973 bp->link_up = 0;
974 }
975 }
976 }
977 else {
978 if (bmcr & BMCR_SPEED100) {
979 bp->line_speed = SPEED_100;
980 }
981 else {
982 bp->line_speed = SPEED_10;
983 }
984 if (bmcr & BMCR_FULLDPLX) {
985 bp->duplex = DUPLEX_FULL;
986 }
987 else {
988 bp->duplex = DUPLEX_HALF;
989 }
990 }
991
992 return 0;
993}
994
83e3fc89
MC		 995static void
996bnx2_init_rx_context0(struct bnx2 *bp)
997{
998 u32 val, rx_cid_addr = GET_CID_ADDR(RX_CID);
999
1000 val = BNX2_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE;
1001 val |= BNX2_L2CTX_CTX_TYPE_SIZE_L2;
1002 val |= 0x02 << 8;
1003
1004 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
1005 u32 lo_water, hi_water;
1006
1007 if (bp->flow_ctrl & FLOW_CTRL_TX)
1008 lo_water = BNX2_L2CTX_LO_WATER_MARK_DEFAULT;
1009 else
1010 lo_water = BNX2_L2CTX_LO_WATER_MARK_DIS;
1011 if (lo_water >= bp->rx_ring_size)
1012 lo_water = 0;
1013
1014 hi_water = bp->rx_ring_size / 4;
1015
1016 if (hi_water <= lo_water)
1017 lo_water = 0;
1018
1019 hi_water /= BNX2_L2CTX_HI_WATER_MARK_SCALE;
1020 lo_water /= BNX2_L2CTX_LO_WATER_MARK_SCALE;
1021
1022 if (hi_water > 0xf)
1023 hi_water = 0xf;
1024 else if (hi_water == 0)
1025 lo_water = 0;
1026 val |= lo_water | (hi_water << BNX2_L2CTX_HI_WATER_MARK_SHIFT);
1027 }
1028 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_CTX_TYPE, val);
1029}
1030
b6016b76
MC		 1031static int
1032bnx2_set_mac_link(struct bnx2 *bp)
1033{
1034 u32 val;
1035
1036 REG_WR(bp, BNX2_EMAC_TX_LENGTHS, 0x2620);
1037 if (bp->link_up && (bp->line_speed == SPEED_1000) &&
1038 (bp->duplex == DUPLEX_HALF)) {
1039 REG_WR(bp, BNX2_EMAC_TX_LENGTHS, 0x26ff);
1040 }
1041
1042 /* Configure the EMAC mode register. */
1043 val = REG_RD(bp, BNX2_EMAC_MODE);
1044
1045 val &= ~(BNX2_EMAC_MODE_PORT | BNX2_EMAC_MODE_HALF_DUPLEX |
5b0c76ad 1046 BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK |
59b47d8a 1047 BNX2_EMAC_MODE_25G_MODE);
b6016b76
MC		 1048
1049 if (bp->link_up) {
5b0c76ad
MC		 1050 switch (bp->line_speed) {
1051 case SPEED_10:
59b47d8a
MC		 1052 if (CHIP_NUM(bp) != CHIP_NUM_5706) {
1053 val |= BNX2_EMAC_MODE_PORT_MII_10M;
5b0c76ad
MC		 1054 break;
1055 }
1056 /* fall through */
1057 case SPEED_100:
1058 val |= BNX2_EMAC_MODE_PORT_MII;
1059 break;
1060 case SPEED_2500:
59b47d8a 1061 val |= BNX2_EMAC_MODE_25G_MODE;
5b0c76ad
MC		 1062 /* fall through */
1063 case SPEED_1000:
1064 val |= BNX2_EMAC_MODE_PORT_GMII;
1065 break;
1066 }
b6016b76
MC		 1067 }
1068 else {
1069 val |= BNX2_EMAC_MODE_PORT_GMII;
1070 }
1071
1072 /* Set the MAC to operate in the appropriate duplex mode. */
1073 if (bp->duplex == DUPLEX_HALF)
1074 val |= BNX2_EMAC_MODE_HALF_DUPLEX;
1075 REG_WR(bp, BNX2_EMAC_MODE, val);
1076
1077 /* Enable/disable rx PAUSE. */
1078 bp->rx_mode &= ~BNX2_EMAC_RX_MODE_FLOW_EN;
1079
1080 if (bp->flow_ctrl & FLOW_CTRL_RX)
1081 bp->rx_mode |= BNX2_EMAC_RX_MODE_FLOW_EN;
1082 REG_WR(bp, BNX2_EMAC_RX_MODE, bp->rx_mode);
1083
1084 /* Enable/disable tx PAUSE. */
1085 val = REG_RD(bp, BNX2_EMAC_TX_MODE);
1086 val &= ~BNX2_EMAC_TX_MODE_FLOW_EN;
1087
1088 if (bp->flow_ctrl & FLOW_CTRL_TX)
1089 val |= BNX2_EMAC_TX_MODE_FLOW_EN;
1090 REG_WR(bp, BNX2_EMAC_TX_MODE, val);
1091
1092 /* Acknowledge the interrupt. */
1093 REG_WR(bp, BNX2_EMAC_STATUS, BNX2_EMAC_STATUS_LINK_CHANGE);
1094
83e3fc89
MC		 1095 if (CHIP_NUM(bp) == CHIP_NUM_5709)
1096 bnx2_init_rx_context0(bp);
1097
b6016b76
MC		 1098 return 0;
1099}
1100
27a005b8
MC		 1101static void
1102bnx2_enable_bmsr1(struct bnx2 *bp)
1103{
583c28e5 1104 if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
27a005b8
MC		 1105 (CHIP_NUM(bp) == CHIP_NUM_5709))
1106 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1107 MII_BNX2_BLK_ADDR_GP_STATUS);
1108}
1109
1110static void
1111bnx2_disable_bmsr1(struct bnx2 *bp)
1112{
583c28e5 1113 if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
27a005b8
MC		 1114 (CHIP_NUM(bp) == CHIP_NUM_5709))
1115 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1116 MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1117}
1118
605a9e20
MC		 1119static int
1120bnx2_test_and_enable_2g5(struct bnx2 *bp)
1121{
1122 u32 up1;
1123 int ret = 1;
1124
583c28e5 1125 if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))
605a9e20
MC		 1126 return 0;
1127
1128 if (bp->autoneg & AUTONEG_SPEED)
1129 bp->advertising |= ADVERTISED_2500baseX_Full;
1130
27a005b8
MC		 1131 if (CHIP_NUM(bp) == CHIP_NUM_5709)
1132 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_OVER1G);
1133
605a9e20
MC		 1134 bnx2_read_phy(bp, bp->mii_up1, &up1);
1135 if (!(up1 & BCM5708S_UP1_2G5)) {
1136 up1 |= BCM5708S_UP1_2G5;
1137 bnx2_write_phy(bp, bp->mii_up1, up1);
1138 ret = 0;
1139 }
1140
27a005b8
MC		 1141 if (CHIP_NUM(bp) == CHIP_NUM_5709)
1142 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1143 MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1144
605a9e20
MC		 1145 return ret;
1146}
1147
1148static int
1149bnx2_test_and_disable_2g5(struct bnx2 *bp)
1150{
1151 u32 up1;
1152 int ret = 0;
1153
583c28e5 1154 if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))
605a9e20
MC		 1155 return 0;
1156
27a005b8
MC		 1157 if (CHIP_NUM(bp) == CHIP_NUM_5709)
1158 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_OVER1G);
1159
605a9e20
MC		 1160 bnx2_read_phy(bp, bp->mii_up1, &up1);
1161 if (up1 & BCM5708S_UP1_2G5) {
1162 up1 &= ~BCM5708S_UP1_2G5;
1163 bnx2_write_phy(bp, bp->mii_up1, up1);
1164 ret = 1;
1165 }
1166
27a005b8
MC		 1167 if (CHIP_NUM(bp) == CHIP_NUM_5709)
1168 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1169 MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1170
605a9e20
MC		 1171 return ret;
1172}
1173
1174static void
1175bnx2_enable_forced_2g5(struct bnx2 *bp)
1176{
1177 u32 bmcr;
1178
583c28e5 1179 if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))
605a9e20
MC		 1180 return;
1181
27a005b8
MC		 1182 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
1183 u32 val;
1184
1185 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1186 MII_BNX2_BLK_ADDR_SERDES_DIG);
1187 bnx2_read_phy(bp, MII_BNX2_SERDES_DIG_MISC1, &val);
1188 val &= ~MII_BNX2_SD_MISC1_FORCE_MSK;
1189 val |= MII_BNX2_SD_MISC1_FORCE | MII_BNX2_SD_MISC1_FORCE_2_5G;
1190 bnx2_write_phy(bp, MII_BNX2_SERDES_DIG_MISC1, val);
1191
1192 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1193 MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1194 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1195
1196 } else if (CHIP_NUM(bp) == CHIP_NUM_5708) {
605a9e20
MC		 1197 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1198 bmcr |= BCM5708S_BMCR_FORCE_2500;
1199 }
1200
1201 if (bp->autoneg & AUTONEG_SPEED) {
1202 bmcr &= ~BMCR_ANENABLE;
1203 if (bp->req_duplex == DUPLEX_FULL)
1204 bmcr |= BMCR_FULLDPLX;
1205 }
1206 bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
1207}
1208
1209static void
1210bnx2_disable_forced_2g5(struct bnx2 *bp)
1211{
1212 u32 bmcr;
1213
583c28e5 1214 if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))
605a9e20
MC		 1215 return;
1216
27a005b8
MC		 1217 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
1218 u32 val;
1219
1220 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1221 MII_BNX2_BLK_ADDR_SERDES_DIG);
1222 bnx2_read_phy(bp, MII_BNX2_SERDES_DIG_MISC1, &val);
1223 val &= ~MII_BNX2_SD_MISC1_FORCE;
1224 bnx2_write_phy(bp, MII_BNX2_SERDES_DIG_MISC1, val);
1225
1226 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1227 MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1228 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1229
1230 } else if (CHIP_NUM(bp) == CHIP_NUM_5708) {
605a9e20
MC		 1231 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1232 bmcr &= ~BCM5708S_BMCR_FORCE_2500;
1233 }
1234
1235 if (bp->autoneg & AUTONEG_SPEED)
1236 bmcr |= BMCR_SPEED1000 | BMCR_ANENABLE | BMCR_ANRESTART;
1237 bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
1238}
1239
b2fadeae
MC		 1240static void
1241bnx2_5706s_force_link_dn(struct bnx2 *bp, int start)
1242{
1243 u32 val;
1244
1245 bnx2_write_phy(bp, MII_BNX2_DSP_ADDRESS, MII_EXPAND_SERDES_CTL);
1246 bnx2_read_phy(bp, MII_BNX2_DSP_RW_PORT, &val);
1247 if (start)
1248 bnx2_write_phy(bp, MII_BNX2_DSP_RW_PORT, val & 0xff0f);
1249 else
1250 bnx2_write_phy(bp, MII_BNX2_DSP_RW_PORT, val | 0xc0);
1251}
1252
b6016b76
MC		 1253static int
1254bnx2_set_link(struct bnx2 *bp)
1255{
1256 u32 bmsr;
1257 u8 link_up;
1258
80be4434 1259 if (bp->loopback == MAC_LOOPBACK || bp->loopback == PHY_LOOPBACK) {
b6016b76
MC		 1260 bp->link_up = 1;
1261 return 0;
1262 }
1263
583c28e5 1264 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
0d8a6571
MC		 1265 return 0;
1266
b6016b76
MC		 1267 link_up = bp->link_up;
1268
27a005b8
MC		 1269 bnx2_enable_bmsr1(bp);
1270 bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr);
1271 bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr);
1272 bnx2_disable_bmsr1(bp);
b6016b76 1273
583c28e5 1274 if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
b6016b76 1275 (CHIP_NUM(bp) == CHIP_NUM_5706)) {
a2724e25 1276 u32 val, an_dbg;
b6016b76 1277
583c28e5 1278 if (bp->phy_flags & BNX2_PHY_FLAG_FORCED_DOWN) {
b2fadeae 1279 bnx2_5706s_force_link_dn(bp, 0);
583c28e5 1280 bp->phy_flags &= ~BNX2_PHY_FLAG_FORCED_DOWN;
b2fadeae 1281 }
b6016b76 1282 val = REG_RD(bp, BNX2_EMAC_STATUS);
a2724e25
MC		 1283
1284 bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_AN_DBG);
1285 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &an_dbg);
1286 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &an_dbg);
1287
1288 if ((val & BNX2_EMAC_STATUS_LINK) &&
1289 !(an_dbg & MISC_SHDW_AN_DBG_NOSYNC))
b6016b76
MC		 1290 bmsr |= BMSR_LSTATUS;
1291 else
1292 bmsr &= ~BMSR_LSTATUS;
1293 }
1294
1295 if (bmsr & BMSR_LSTATUS) {
1296 bp->link_up = 1;
1297
583c28e5 1298 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
5b0c76ad
MC		 1299 if (CHIP_NUM(bp) == CHIP_NUM_5706)
1300 bnx2_5706s_linkup(bp);
1301 else if (CHIP_NUM(bp) == CHIP_NUM_5708)
1302 bnx2_5708s_linkup(bp);
27a005b8
MC		 1303 else if (CHIP_NUM(bp) == CHIP_NUM_5709)
1304 bnx2_5709s_linkup(bp);
b6016b76
MC		 1305 }
1306 else {
1307 bnx2_copper_linkup(bp);
1308 }
1309 bnx2_resolve_flow_ctrl(bp);
1310 }
1311 else {
583c28e5 1312 if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
605a9e20
MC		 1313 (bp->autoneg & AUTONEG_SPEED))
1314 bnx2_disable_forced_2g5(bp);
b6016b76 1315
583c28e5 1316 if (bp->phy_flags & BNX2_PHY_FLAG_PARALLEL_DETECT) {
b2fadeae
MC		 1317 u32 bmcr;
1318
1319 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1320 bmcr |= BMCR_ANENABLE;
1321 bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
1322
583c28e5 1323 bp->phy_flags &= ~BNX2_PHY_FLAG_PARALLEL_DETECT;
b2fadeae 1324 }
b6016b76
MC		 1325 bp->link_up = 0;
1326 }
1327
1328 if (bp->link_up != link_up) {
1329 bnx2_report_link(bp);
1330 }
1331
1332 bnx2_set_mac_link(bp);
1333
1334 return 0;
1335}
1336
1337static int
1338bnx2_reset_phy(struct bnx2 *bp)
1339{
1340 int i;
1341 u32 reg;
1342
ca58c3af 1343 bnx2_write_phy(bp, bp->mii_bmcr, BMCR_RESET);
b6016b76
MC		 1344
1345#define PHY_RESET_MAX_WAIT 100
1346 for (i = 0; i < PHY_RESET_MAX_WAIT; i++) {
1347 udelay(10);
1348
ca58c3af 1349 bnx2_read_phy(bp, bp->mii_bmcr, &reg);
b6016b76
MC		 1350 if (!(reg & BMCR_RESET)) {
1351 udelay(20);
1352 break;
1353 }
1354 }
1355 if (i == PHY_RESET_MAX_WAIT) {
1356 return -EBUSY;
1357 }
1358 return 0;
1359}
1360
1361static u32
1362bnx2_phy_get_pause_adv(struct bnx2 *bp)
1363{
1364 u32 adv = 0;
1365
1366 if ((bp->req_flow_ctrl & (FLOW_CTRL_RX | FLOW_CTRL_TX)) ==
1367 (FLOW_CTRL_RX | FLOW_CTRL_TX)) {
1368
583c28e5 1369 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
b6016b76
MC		 1370 adv = ADVERTISE_1000XPAUSE;
1371 }
1372 else {
1373 adv = ADVERTISE_PAUSE_CAP;
1374 }
1375 }
1376 else if (bp->req_flow_ctrl & FLOW_CTRL_TX) {
583c28e5 1377 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
b6016b76
MC		 1378 adv = ADVERTISE_1000XPSE_ASYM;
1379 }
1380 else {
1381 adv = ADVERTISE_PAUSE_ASYM;
1382 }
1383 }
1384 else if (bp->req_flow_ctrl & FLOW_CTRL_RX) {
583c28e5 1385 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
b6016b76
MC		 1386 adv = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
1387 }
1388 else {
1389 adv = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1390 }
1391 }
1392 return adv;
1393}
1394
0d8a6571
MC		 1395static int bnx2_fw_sync(struct bnx2 *, u32, int);
1396
b6016b76 1397static int
0d8a6571
MC		 1398bnx2_setup_remote_phy(struct bnx2 *bp, u8 port)
1399{
1400 u32 speed_arg = 0, pause_adv;
1401
1402 pause_adv = bnx2_phy_get_pause_adv(bp);
1403
1404 if (bp->autoneg & AUTONEG_SPEED) {
1405 speed_arg |= BNX2_NETLINK_SET_LINK_ENABLE_AUTONEG;
1406 if (bp->advertising & ADVERTISED_10baseT_Half)
1407 speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_10HALF;
1408 if (bp->advertising & ADVERTISED_10baseT_Full)
1409 speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_10FULL;
1410 if (bp->advertising & ADVERTISED_100baseT_Half)
1411 speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_100HALF;
1412 if (bp->advertising & ADVERTISED_100baseT_Full)
1413 speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_100FULL;
1414 if (bp->advertising & ADVERTISED_1000baseT_Full)
1415 speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_1GFULL;
1416 if (bp->advertising & ADVERTISED_2500baseX_Full)
1417 speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_2G5FULL;
1418 } else {
1419 if (bp->req_line_speed == SPEED_2500)
1420 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_2G5FULL;
1421 else if (bp->req_line_speed == SPEED_1000)
1422 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_1GFULL;
1423 else if (bp->req_line_speed == SPEED_100) {
1424 if (bp->req_duplex == DUPLEX_FULL)
1425 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_100FULL;
1426 else
1427 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_100HALF;
1428 } else if (bp->req_line_speed == SPEED_10) {
1429 if (bp->req_duplex == DUPLEX_FULL)
1430 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_10FULL;
1431 else
1432 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_10HALF;
1433 }
1434 }
1435
1436 if (pause_adv & (ADVERTISE_1000XPAUSE | ADVERTISE_PAUSE_CAP))
1437 speed_arg |= BNX2_NETLINK_SET_LINK_FC_SYM_PAUSE;
c26736ec 1438 if (pause_adv & (ADVERTISE_1000XPSE_ASYM | ADVERTISE_PAUSE_ASYM))
0d8a6571
MC		 1439 speed_arg |= BNX2_NETLINK_SET_LINK_FC_ASYM_PAUSE;
1440
1441 if (port == PORT_TP)
1442 speed_arg |= BNX2_NETLINK_SET_LINK_PHY_APP_REMOTE |
1443 BNX2_NETLINK_SET_LINK_ETH_AT_WIRESPEED;
1444
2726d6e1 1445 bnx2_shmem_wr(bp, BNX2_DRV_MB_ARG0, speed_arg);
0d8a6571
MC		 1446
1447 spin_unlock_bh(&bp->phy_lock);
1448 bnx2_fw_sync(bp, BNX2_DRV_MSG_CODE_CMD_SET_LINK, 0);
1449 spin_lock_bh(&bp->phy_lock);
1450
1451 return 0;
1452}
1453
1454static int
1455bnx2_setup_serdes_phy(struct bnx2 *bp, u8 port)
b6016b76 1456{
605a9e20 1457 u32 adv, bmcr;
b6016b76
MC		 1458 u32 new_adv = 0;
1459
583c28e5 1460 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
0d8a6571
MC		 1461 return (bnx2_setup_remote_phy(bp, port));
1462
b6016b76
MC		 1463 if (!(bp->autoneg & AUTONEG_SPEED)) {
1464 u32 new_bmcr;
5b0c76ad
MC		 1465 int force_link_down = 0;
1466
605a9e20
MC		 1467 if (bp->req_line_speed == SPEED_2500) {
1468 if (!bnx2_test_and_enable_2g5(bp))
1469 force_link_down = 1;
1470 } else if (bp->req_line_speed == SPEED_1000) {
1471 if (bnx2_test_and_disable_2g5(bp))
1472 force_link_down = 1;
1473 }
ca58c3af 1474 bnx2_read_phy(bp, bp->mii_adv, &adv);
80be4434
MC		 1475 adv &= ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF);
1476
ca58c3af 1477 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
605a9e20 1478 new_bmcr = bmcr & ~BMCR_ANENABLE;
80be4434 1479 new_bmcr |= BMCR_SPEED1000;
605a9e20 1480
27a005b8
MC		 1481 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
1482 if (bp->req_line_speed == SPEED_2500)
1483 bnx2_enable_forced_2g5(bp);
1484 else if (bp->req_line_speed == SPEED_1000) {
1485 bnx2_disable_forced_2g5(bp);
1486 new_bmcr &= ~0x2000;
1487 }
1488
1489 } else if (CHIP_NUM(bp) == CHIP_NUM_5708) {
605a9e20
MC		 1490 if (bp->req_line_speed == SPEED_2500)
1491 new_bmcr |= BCM5708S_BMCR_FORCE_2500;
1492 else
1493 new_bmcr = bmcr & ~BCM5708S_BMCR_FORCE_2500;
5b0c76ad
MC		 1494 }
1495
b6016b76 1496 if (bp->req_duplex == DUPLEX_FULL) {
5b0c76ad 1497 adv |= ADVERTISE_1000XFULL;
b6016b76
MC		 1498 new_bmcr |= BMCR_FULLDPLX;
1499 }
1500 else {
5b0c76ad 1501 adv |= ADVERTISE_1000XHALF;
b6016b76
MC		 1502 new_bmcr &= ~BMCR_FULLDPLX;
1503 }
5b0c76ad 1504 if ((new_bmcr != bmcr) || (force_link_down)) {
b6016b76
MC		 1505 /* Force a link down visible on the other side */
1506 if (bp->link_up) {
ca58c3af 1507 bnx2_write_phy(bp, bp->mii_adv, adv &
5b0c76ad
MC		 1508 ~(ADVERTISE_1000XFULL |
1509 ADVERTISE_1000XHALF));
ca58c3af 1510 bnx2_write_phy(bp, bp->mii_bmcr, bmcr |
b6016b76
MC		 1511 BMCR_ANRESTART | BMCR_ANENABLE);
1512
1513 bp->link_up = 0;
1514 netif_carrier_off(bp->dev);
ca58c3af 1515 bnx2_write_phy(bp, bp->mii_bmcr, new_bmcr);
80be4434 1516 bnx2_report_link(bp);
b6016b76 1517 }
ca58c3af
MC		 1518 bnx2_write_phy(bp, bp->mii_adv, adv);
1519 bnx2_write_phy(bp, bp->mii_bmcr, new_bmcr);
605a9e20
MC		 1520 } else {
1521 bnx2_resolve_flow_ctrl(bp);
1522 bnx2_set_mac_link(bp);
b6016b76
MC		 1523 }
1524 return 0;
1525 }
1526
605a9e20 1527 bnx2_test_and_enable_2g5(bp);
5b0c76ad 1528
b6016b76
MC		 1529 if (bp->advertising & ADVERTISED_1000baseT_Full)
1530 new_adv |= ADVERTISE_1000XFULL;
1531
1532 new_adv |= bnx2_phy_get_pause_adv(bp);
1533
ca58c3af
MC		 1534 bnx2_read_phy(bp, bp->mii_adv, &adv);
1535 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
b6016b76
MC		 1536
1537 bp->serdes_an_pending = 0;
1538 if ((adv != new_adv) || ((bmcr & BMCR_ANENABLE) == 0)) {
1539 /* Force a link down visible on the other side */
1540 if (bp->link_up) {
ca58c3af 1541 bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK);
80be4434
MC		 1542 spin_unlock_bh(&bp->phy_lock);
1543 msleep(20);
1544 spin_lock_bh(&bp->phy_lock);
b6016b76
MC		 1545 }
1546
ca58c3af
MC		 1547 bnx2_write_phy(bp, bp->mii_adv, new_adv);
1548 bnx2_write_phy(bp, bp->mii_bmcr, bmcr | BMCR_ANRESTART |
b6016b76 1549 BMCR_ANENABLE);
f8dd064e
MC		 1550 /* Speed up link-up time when the link partner
1551 * does not autonegotiate which is very common
1552 * in blade servers. Some blade servers use
1553 * IPMI for kerboard input and it's important
1554 * to minimize link disruptions. Autoneg. involves
1555 * exchanging base pages plus 3 next pages and
1556 * normally completes in about 120 msec.
1557 */
1558 bp->current_interval = SERDES_AN_TIMEOUT;
1559 bp->serdes_an_pending = 1;
1560 mod_timer(&bp->timer, jiffies + bp->current_interval);
605a9e20
MC		 1561 } else {
1562 bnx2_resolve_flow_ctrl(bp);
1563 bnx2_set_mac_link(bp);
b6016b76
MC		 1564 }
1565
1566 return 0;
1567}
1568
1569#define ETHTOOL_ALL_FIBRE_SPEED \
583c28e5 1570 (bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE) ? \
deaf391b
MC		 1571 (ADVERTISED_2500baseX_Full | ADVERTISED_1000baseT_Full) :\
1572 (ADVERTISED_1000baseT_Full)
b6016b76
MC		 1573
1574#define ETHTOOL_ALL_COPPER_SPEED \
1575 (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full | \
1576 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full | \
1577 ADVERTISED_1000baseT_Full)
1578
1579#define PHY_ALL_10_100_SPEED (ADVERTISE_10HALF | ADVERTISE_10FULL | \
1580 ADVERTISE_100HALF | ADVERTISE_100FULL | ADVERTISE_CSMA)
6aa20a22 1581
b6016b76
MC		 1582#define PHY_ALL_1000_SPEED (ADVERTISE_1000HALF | ADVERTISE_1000FULL)
1583
0d8a6571
MC		 1584static void
1585bnx2_set_default_remote_link(struct bnx2 *bp)
1586{
1587 u32 link;
1588
1589 if (bp->phy_port == PORT_TP)
2726d6e1 1590 link = bnx2_shmem_rd(bp, BNX2_RPHY_COPPER_LINK);
0d8a6571 1591 else
2726d6e1 1592 link = bnx2_shmem_rd(bp, BNX2_RPHY_SERDES_LINK);
0d8a6571
MC		 1593
1594 if (link & BNX2_NETLINK_SET_LINK_ENABLE_AUTONEG) {
1595 bp->req_line_speed = 0;
1596 bp->autoneg |= AUTONEG_SPEED;
1597 bp->advertising = ADVERTISED_Autoneg;
1598 if (link & BNX2_NETLINK_SET_LINK_SPEED_10HALF)
1599 bp->advertising |= ADVERTISED_10baseT_Half;
1600 if (link & BNX2_NETLINK_SET_LINK_SPEED_10FULL)
1601 bp->advertising |= ADVERTISED_10baseT_Full;
1602 if (link & BNX2_NETLINK_SET_LINK_SPEED_100HALF)
1603 bp->advertising |= ADVERTISED_100baseT_Half;
1604 if (link & BNX2_NETLINK_SET_LINK_SPEED_100FULL)
1605 bp->advertising |= ADVERTISED_100baseT_Full;
1606 if (link & BNX2_NETLINK_SET_LINK_SPEED_1GFULL)
1607 bp->advertising |= ADVERTISED_1000baseT_Full;
1608 if (link & BNX2_NETLINK_SET_LINK_SPEED_2G5FULL)
1609 bp->advertising |= ADVERTISED_2500baseX_Full;
1610 } else {
1611 bp->autoneg = 0;
1612 bp->advertising = 0;
1613 bp->req_duplex = DUPLEX_FULL;
1614 if (link & BNX2_NETLINK_SET_LINK_SPEED_10) {
1615 bp->req_line_speed = SPEED_10;
1616 if (link & BNX2_NETLINK_SET_LINK_SPEED_10HALF)
1617 bp->req_duplex = DUPLEX_HALF;
1618 }
1619 if (link & BNX2_NETLINK_SET_LINK_SPEED_100) {
1620 bp->req_line_speed = SPEED_100;
1621 if (link & BNX2_NETLINK_SET_LINK_SPEED_100HALF)
1622 bp->req_duplex = DUPLEX_HALF;
1623 }
1624 if (link & BNX2_NETLINK_SET_LINK_SPEED_1GFULL)
1625 bp->req_line_speed = SPEED_1000;
1626 if (link & BNX2_NETLINK_SET_LINK_SPEED_2G5FULL)
1627 bp->req_line_speed = SPEED_2500;
1628 }
1629}
1630
deaf391b
MC		 1631static void
1632bnx2_set_default_link(struct bnx2 *bp)
1633{
ab59859d
HH		 1634 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) {
1635 bnx2_set_default_remote_link(bp);
1636 return;
1637 }
0d8a6571 1638
deaf391b
MC		 1639 bp->autoneg = AUTONEG_SPEED | AUTONEG_FLOW_CTRL;
1640 bp->req_line_speed = 0;
583c28e5 1641 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
deaf391b
MC		 1642 u32 reg;
1643
1644 bp->advertising = ETHTOOL_ALL_FIBRE_SPEED | ADVERTISED_Autoneg;
1645
2726d6e1 1646 reg = bnx2_shmem_rd(bp, BNX2_PORT_HW_CFG_CONFIG);
deaf391b
MC		 1647 reg &= BNX2_PORT_HW_CFG_CFG_DFLT_LINK_MASK;
1648 if (reg == BNX2_PORT_HW_CFG_CFG_DFLT_LINK_1G) {
1649 bp->autoneg = 0;
1650 bp->req_line_speed = bp->line_speed = SPEED_1000;
1651 bp->req_duplex = DUPLEX_FULL;
1652 }
1653 } else
1654 bp->advertising = ETHTOOL_ALL_COPPER_SPEED | ADVERTISED_Autoneg;
1655}
1656
df149d70
MC		 1657static void
1658bnx2_send_heart_beat(struct bnx2 *bp)
1659{
1660 u32 msg;
1661 u32 addr;
1662
1663 spin_lock(&bp->indirect_lock);
1664 msg = (u32) (++bp->fw_drv_pulse_wr_seq & BNX2_DRV_PULSE_SEQ_MASK);
1665 addr = bp->shmem_base + BNX2_DRV_PULSE_MB;
1666 REG_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, addr);
1667 REG_WR(bp, BNX2_PCICFG_REG_WINDOW, msg);
1668 spin_unlock(&bp->indirect_lock);
1669}
1670
0d8a6571
MC		 1671static void
1672bnx2_remote_phy_event(struct bnx2 *bp)
1673{
1674 u32 msg;
1675 u8 link_up = bp->link_up;
1676 u8 old_port;
1677
2726d6e1 1678 msg = bnx2_shmem_rd(bp, BNX2_LINK_STATUS);
0d8a6571 1679
df149d70
MC		 1680 if (msg & BNX2_LINK_STATUS_HEART_BEAT_EXPIRED)
1681 bnx2_send_heart_beat(bp);
1682
1683 msg &= ~BNX2_LINK_STATUS_HEART_BEAT_EXPIRED;
1684
0d8a6571
MC		 1685 if ((msg & BNX2_LINK_STATUS_LINK_UP) == BNX2_LINK_STATUS_LINK_DOWN)
1686 bp->link_up = 0;
1687 else {
1688 u32 speed;
1689
1690 bp->link_up = 1;
1691 speed = msg & BNX2_LINK_STATUS_SPEED_MASK;
1692 bp->duplex = DUPLEX_FULL;
1693 switch (speed) {
1694 case BNX2_LINK_STATUS_10HALF:
1695 bp->duplex = DUPLEX_HALF;
1696 case BNX2_LINK_STATUS_10FULL:
1697 bp->line_speed = SPEED_10;
1698 break;
1699 case BNX2_LINK_STATUS_100HALF:
1700 bp->duplex = DUPLEX_HALF;
1701 case BNX2_LINK_STATUS_100BASE_T4:
1702 case BNX2_LINK_STATUS_100FULL:
1703 bp->line_speed = SPEED_100;
1704 break;
1705 case BNX2_LINK_STATUS_1000HALF:
1706 bp->duplex = DUPLEX_HALF;
1707 case BNX2_LINK_STATUS_1000FULL:
1708 bp->line_speed = SPEED_1000;
1709 break;
1710 case BNX2_LINK_STATUS_2500HALF:
1711 bp->duplex = DUPLEX_HALF;
1712 case BNX2_LINK_STATUS_2500FULL:
1713 bp->line_speed = SPEED_2500;
1714 break;
1715 default:
1716 bp->line_speed = 0;
1717 break;
1718 }
1719
0d8a6571
MC		 1720 bp->flow_ctrl = 0;
1721 if ((bp->autoneg & (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) !=
1722 (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) {
1723 if (bp->duplex == DUPLEX_FULL)
1724 bp->flow_ctrl = bp->req_flow_ctrl;
1725 } else {
1726 if (msg & BNX2_LINK_STATUS_TX_FC_ENABLED)
1727 bp->flow_ctrl |= FLOW_CTRL_TX;
1728 if (msg & BNX2_LINK_STATUS_RX_FC_ENABLED)
1729 bp->flow_ctrl |= FLOW_CTRL_RX;
1730 }
1731
1732 old_port = bp->phy_port;
1733 if (msg & BNX2_LINK_STATUS_SERDES_LINK)
1734 bp->phy_port = PORT_FIBRE;
1735 else
1736 bp->phy_port = PORT_TP;
1737
1738 if (old_port != bp->phy_port)
1739 bnx2_set_default_link(bp);
1740
0d8a6571
MC		 1741 }
1742 if (bp->link_up != link_up)
1743 bnx2_report_link(bp);
1744
1745 bnx2_set_mac_link(bp);
1746}
1747
1748static int
1749bnx2_set_remote_link(struct bnx2 *bp)
1750{
1751 u32 evt_code;
1752
2726d6e1 1753 evt_code = bnx2_shmem_rd(bp, BNX2_FW_EVT_CODE_MB);
0d8a6571
MC		 1754 switch (evt_code) {
1755 case BNX2_FW_EVT_CODE_LINK_EVENT:
1756 bnx2_remote_phy_event(bp);
1757 break;
1758 case BNX2_FW_EVT_CODE_SW_TIMER_EXPIRATION_EVENT:
1759 default:
df149d70 1760 bnx2_send_heart_beat(bp);
0d8a6571
MC		 1761 break;
1762 }
1763 return 0;
1764}
1765
b6016b76
MC		 1766static int
1767bnx2_setup_copper_phy(struct bnx2 *bp)
1768{
1769 u32 bmcr;
1770 u32 new_bmcr;
1771
ca58c3af 1772 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
b6016b76
MC		 1773
1774 if (bp->autoneg & AUTONEG_SPEED) {
1775 u32 adv_reg, adv1000_reg;
1776 u32 new_adv_reg = 0;
1777 u32 new_adv1000_reg = 0;
1778
ca58c3af 1779 bnx2_read_phy(bp, bp->mii_adv, &adv_reg);
b6016b76
MC		 1780 adv_reg &= (PHY_ALL_10_100_SPEED | ADVERTISE_PAUSE_CAP |
1781 ADVERTISE_PAUSE_ASYM);
1782
1783 bnx2_read_phy(bp, MII_CTRL1000, &adv1000_reg);
1784 adv1000_reg &= PHY_ALL_1000_SPEED;
1785
1786 if (bp->advertising & ADVERTISED_10baseT_Half)
1787 new_adv_reg |= ADVERTISE_10HALF;
1788 if (bp->advertising & ADVERTISED_10baseT_Full)
1789 new_adv_reg |= ADVERTISE_10FULL;
1790 if (bp->advertising & ADVERTISED_100baseT_Half)
1791 new_adv_reg |= ADVERTISE_100HALF;
1792 if (bp->advertising & ADVERTISED_100baseT_Full)
1793 new_adv_reg |= ADVERTISE_100FULL;
1794 if (bp->advertising & ADVERTISED_1000baseT_Full)
1795 new_adv1000_reg |= ADVERTISE_1000FULL;
6aa20a22 1796
b6016b76
MC		 1797 new_adv_reg |= ADVERTISE_CSMA;
1798
1799 new_adv_reg |= bnx2_phy_get_pause_adv(bp);
1800
1801 if ((adv1000_reg != new_adv1000_reg) ||
1802 (adv_reg != new_adv_reg) ||
1803 ((bmcr & BMCR_ANENABLE) == 0)) {
1804
ca58c3af 1805 bnx2_write_phy(bp, bp->mii_adv, new_adv_reg);
b6016b76 1806 bnx2_write_phy(bp, MII_CTRL1000, new_adv1000_reg);
ca58c3af 1807 bnx2_write_phy(bp, bp->mii_bmcr, BMCR_ANRESTART |
b6016b76
MC		 1808 BMCR_ANENABLE);
1809 }
1810 else if (bp->link_up) {
1811 /* Flow ctrl may have changed from auto to forced */
1812 /* or vice-versa. */
1813
1814 bnx2_resolve_flow_ctrl(bp);
1815 bnx2_set_mac_link(bp);
1816 }
1817 return 0;
1818 }
1819
1820 new_bmcr = 0;
1821 if (bp->req_line_speed == SPEED_100) {
1822 new_bmcr |= BMCR_SPEED100;
1823 }
1824 if (bp->req_duplex == DUPLEX_FULL) {
1825 new_bmcr |= BMCR_FULLDPLX;
1826 }
1827 if (new_bmcr != bmcr) {
1828 u32 bmsr;
b6016b76 1829
ca58c3af
MC		 1830 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
1831 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
6aa20a22 1832
b6016b76
MC		 1833 if (bmsr & BMSR_LSTATUS) {
1834 /* Force link down */
ca58c3af 1835 bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK);
a16dda0e
MC		 1836 spin_unlock_bh(&bp->phy_lock);
1837 msleep(50);
1838 spin_lock_bh(&bp->phy_lock);
1839
ca58c3af
MC		 1840 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
1841 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
b6016b76
MC		 1842 }
1843
ca58c3af 1844 bnx2_write_phy(bp, bp->mii_bmcr, new_bmcr);
b6016b76
MC		 1845
1846 /* Normally, the new speed is setup after the link has
1847 * gone down and up again. In some cases, link will not go
1848 * down so we need to set up the new speed here.
1849 */
1850 if (bmsr & BMSR_LSTATUS) {
1851 bp->line_speed = bp->req_line_speed;
1852 bp->duplex = bp->req_duplex;
1853 bnx2_resolve_flow_ctrl(bp);
1854 bnx2_set_mac_link(bp);
1855 }
27a005b8
MC		 1856 } else {
1857 bnx2_resolve_flow_ctrl(bp);
1858 bnx2_set_mac_link(bp);
b6016b76
MC		 1859 }
1860 return 0;
1861}
1862
1863static int
0d8a6571 1864bnx2_setup_phy(struct bnx2 *bp, u8 port)
b6016b76
MC		 1865{
1866 if (bp->loopback == MAC_LOOPBACK)
1867 return 0;
1868
583c28e5 1869 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
0d8a6571 1870 return (bnx2_setup_serdes_phy(bp, port));
b6016b76
MC		 1871 }
1872 else {
1873 return (bnx2_setup_copper_phy(bp));
1874 }
1875}
1876
27a005b8
MC		 1877static int
1878bnx2_init_5709s_phy(struct bnx2 *bp)
1879{
1880 u32 val;
1881
1882 bp->mii_bmcr = MII_BMCR + 0x10;
1883 bp->mii_bmsr = MII_BMSR + 0x10;
1884 bp->mii_bmsr1 = MII_BNX2_GP_TOP_AN_STATUS1;
1885 bp->mii_adv = MII_ADVERTISE + 0x10;
1886 bp->mii_lpa = MII_LPA + 0x10;
1887 bp->mii_up1 = MII_BNX2_OVER1G_UP1;
1888
1889 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_AER);
1890 bnx2_write_phy(bp, MII_BNX2_AER_AER, MII_BNX2_AER_AER_AN_MMD);
1891
1892 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1893 bnx2_reset_phy(bp);
1894
1895 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_SERDES_DIG);
1896
1897 bnx2_read_phy(bp, MII_BNX2_SERDES_DIG_1000XCTL1, &val);
1898 val &= ~MII_BNX2_SD_1000XCTL1_AUTODET;
1899 val |= MII_BNX2_SD_1000XCTL1_FIBER;
1900 bnx2_write_phy(bp, MII_BNX2_SERDES_DIG_1000XCTL1, val);
1901
1902 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_OVER1G);
1903 bnx2_read_phy(bp, MII_BNX2_OVER1G_UP1, &val);
583c28e5 1904 if (bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE)
27a005b8
MC		 1905 val |= BCM5708S_UP1_2G5;
1906 else
1907 val &= ~BCM5708S_UP1_2G5;
1908 bnx2_write_phy(bp, MII_BNX2_OVER1G_UP1, val);
1909
1910 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_BAM_NXTPG);
1911 bnx2_read_phy(bp, MII_BNX2_BAM_NXTPG_CTL, &val);
1912 val |= MII_BNX2_NXTPG_CTL_T2 | MII_BNX2_NXTPG_CTL_BAM;
1913 bnx2_write_phy(bp, MII_BNX2_BAM_NXTPG_CTL, val);
1914
1915 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_CL73_USERB0);
1916
1917 val = MII_BNX2_CL73_BAM_EN | MII_BNX2_CL73_BAM_STA_MGR_EN |
1918 MII_BNX2_CL73_BAM_NP_AFT_BP_EN;
1919 bnx2_write_phy(bp, MII_BNX2_CL73_BAM_CTL1, val);
1920
1921 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1922
1923 return 0;
1924}
1925
b6016b76 1926static int
5b0c76ad
MC		 1927bnx2_init_5708s_phy(struct bnx2 *bp)
1928{
1929 u32 val;
1930
27a005b8
MC		 1931 bnx2_reset_phy(bp);
1932
1933 bp->mii_up1 = BCM5708S_UP1;
1934
5b0c76ad
MC		 1935 bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG3);
1936 bnx2_write_phy(bp, BCM5708S_DIG_3_0, BCM5708S_DIG_3_0_USE_IEEE);
1937 bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG);
1938
1939 bnx2_read_phy(bp, BCM5708S_1000X_CTL1, &val);
1940 val |= BCM5708S_1000X_CTL1_FIBER_MODE | BCM5708S_1000X_CTL1_AUTODET_EN;
1941 bnx2_write_phy(bp, BCM5708S_1000X_CTL1, val);
1942
1943 bnx2_read_phy(bp, BCM5708S_1000X_CTL2, &val);
1944 val |= BCM5708S_1000X_CTL2_PLLEL_DET_EN;
1945 bnx2_write_phy(bp, BCM5708S_1000X_CTL2, val);
1946
583c28e5 1947 if (bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE) {
5b0c76ad
MC		 1948 bnx2_read_phy(bp, BCM5708S_UP1, &val);
1949 val |= BCM5708S_UP1_2G5;
1950 bnx2_write_phy(bp, BCM5708S_UP1, val);
1951 }
1952
1953 if ((CHIP_ID(bp) == CHIP_ID_5708_A0) ||
dda1e390
MC		 1954 (CHIP_ID(bp) == CHIP_ID_5708_B0) ||
1955 (CHIP_ID(bp) == CHIP_ID_5708_B1)) {
5b0c76ad
MC		 1956 /* increase tx signal amplitude */
1957 bnx2_write_phy(bp, BCM5708S_BLK_ADDR,
1958 BCM5708S_BLK_ADDR_TX_MISC);
1959 bnx2_read_phy(bp, BCM5708S_TX_ACTL1, &val);
1960 val &= ~BCM5708S_TX_ACTL1_DRIVER_VCM;
1961 bnx2_write_phy(bp, BCM5708S_TX_ACTL1, val);
1962 bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG);
1963 }
1964
2726d6e1 1965 val = bnx2_shmem_rd(bp, BNX2_PORT_HW_CFG_CONFIG) &
5b0c76ad
MC		 1966 BNX2_PORT_HW_CFG_CFG_TXCTL3_MASK;
1967
1968 if (val) {
1969 u32 is_backplane;
1970
2726d6e1 1971 is_backplane = bnx2_shmem_rd(bp, BNX2_SHARED_HW_CFG_CONFIG);
5b0c76ad
MC		 1972 if (is_backplane & BNX2_SHARED_HW_CFG_PHY_BACKPLANE) {
1973 bnx2_write_phy(bp, BCM5708S_BLK_ADDR,
1974 BCM5708S_BLK_ADDR_TX_MISC);
1975 bnx2_write_phy(bp, BCM5708S_TX_ACTL3, val);
1976 bnx2_write_phy(bp, BCM5708S_BLK_ADDR,
1977 BCM5708S_BLK_ADDR_DIG);
1978 }
1979 }
1980 return 0;
1981}
1982
1983static int
1984bnx2_init_5706s_phy(struct bnx2 *bp)
b6016b76 1985{
27a005b8
MC		 1986 bnx2_reset_phy(bp);
1987
583c28e5 1988 bp->phy_flags &= ~BNX2_PHY_FLAG_PARALLEL_DETECT;
b6016b76 1989
59b47d8a
MC		 1990 if (CHIP_NUM(bp) == CHIP_NUM_5706)
1991 REG_WR(bp, BNX2_MISC_GP_HW_CTL0, 0x300);
b6016b76
MC		 1992
1993 if (bp->dev->mtu > 1500) {
1994 u32 val;
1995
1996 /* Set extended packet length bit */
1997 bnx2_write_phy(bp, 0x18, 0x7);
1998 bnx2_read_phy(bp, 0x18, &val);
1999 bnx2_write_phy(bp, 0x18, (val & 0xfff8) | 0x4000);
2000
2001 bnx2_write_phy(bp, 0x1c, 0x6c00);
2002 bnx2_read_phy(bp, 0x1c, &val);
2003 bnx2_write_phy(bp, 0x1c, (val & 0x3ff) | 0xec02);
2004 }
2005 else {
2006 u32 val;
2007
2008 bnx2_write_phy(bp, 0x18, 0x7);
2009 bnx2_read_phy(bp, 0x18, &val);
2010 bnx2_write_phy(bp, 0x18, val & ~0x4007);
2011
2012 bnx2_write_phy(bp, 0x1c, 0x6c00);
2013 bnx2_read_phy(bp, 0x1c, &val);
2014 bnx2_write_phy(bp, 0x1c, (val & 0x3fd) | 0xec00);
2015 }
2016
2017 return 0;
2018}
2019
2020static int
2021bnx2_init_copper_phy(struct bnx2 *bp)
2022{
5b0c76ad
MC		 2023 u32 val;
2024
27a005b8
MC		 2025 bnx2_reset_phy(bp);
2026
583c28e5 2027 if (bp->phy_flags & BNX2_PHY_FLAG_CRC_FIX) {
b6016b76
MC		 2028 bnx2_write_phy(bp, 0x18, 0x0c00);
2029 bnx2_write_phy(bp, 0x17, 0x000a);
2030 bnx2_write_phy(bp, 0x15, 0x310b);
2031 bnx2_write_phy(bp, 0x17, 0x201f);
2032 bnx2_write_phy(bp, 0x15, 0x9506);
2033 bnx2_write_phy(bp, 0x17, 0x401f);
2034 bnx2_write_phy(bp, 0x15, 0x14e2);
2035 bnx2_write_phy(bp, 0x18, 0x0400);
2036 }
2037
583c28e5 2038 if (bp->phy_flags & BNX2_PHY_FLAG_DIS_EARLY_DAC) {
b659f44e
MC		 2039 bnx2_write_phy(bp, MII_BNX2_DSP_ADDRESS,
2040 MII_BNX2_DSP_EXPAND_REG | 0x8);
2041 bnx2_read_phy(bp, MII_BNX2_DSP_RW_PORT, &val);
2042 val &= ~(1 << 8);
2043 bnx2_write_phy(bp, MII_BNX2_DSP_RW_PORT, val);
2044 }
2045
b6016b76 2046 if (bp->dev->mtu > 1500) {
b6016b76
MC		 2047 /* Set extended packet length bit */
2048 bnx2_write_phy(bp, 0x18, 0x7);
2049 bnx2_read_phy(bp, 0x18, &val);
2050 bnx2_write_phy(bp, 0x18, val | 0x4000);
2051
2052 bnx2_read_phy(bp, 0x10, &val);
2053 bnx2_write_phy(bp, 0x10, val | 0x1);
2054 }
2055 else {
b6016b76
MC		 2056 bnx2_write_phy(bp, 0x18, 0x7);
2057 bnx2_read_phy(bp, 0x18, &val);
2058 bnx2_write_phy(bp, 0x18, val & ~0x4007);
2059
2060 bnx2_read_phy(bp, 0x10, &val);
2061 bnx2_write_phy(bp, 0x10, val & ~0x1);
2062 }
2063
5b0c76ad
MC		 2064 /* ethernet@wirespeed */
2065 bnx2_write_phy(bp, 0x18, 0x7007);
2066 bnx2_read_phy(bp, 0x18, &val);
2067 bnx2_write_phy(bp, 0x18, val | (1 << 15) | (1 << 4));
b6016b76
MC		 2068 return 0;
2069}
2070
2071
2072static int
2073bnx2_init_phy(struct bnx2 *bp)
2074{
2075 u32 val;
2076 int rc = 0;
2077
583c28e5
MC		 2078 bp->phy_flags &= ~BNX2_PHY_FLAG_INT_MODE_MASK;
2079 bp->phy_flags |= BNX2_PHY_FLAG_INT_MODE_LINK_READY;
b6016b76 2080
ca58c3af
MC		 2081 bp->mii_bmcr = MII_BMCR;
2082 bp->mii_bmsr = MII_BMSR;
27a005b8 2083 bp->mii_bmsr1 = MII_BMSR;
ca58c3af
MC		 2084 bp->mii_adv = MII_ADVERTISE;
2085 bp->mii_lpa = MII_LPA;
2086
b6016b76
MC		 2087 REG_WR(bp, BNX2_EMAC_ATTENTION_ENA, BNX2_EMAC_ATTENTION_ENA_LINK);
2088
583c28e5 2089 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
0d8a6571
MC		 2090 goto setup_phy;
2091
b6016b76
MC		 2092 bnx2_read_phy(bp, MII_PHYSID1, &val);
2093 bp->phy_id = val << 16;
2094 bnx2_read_phy(bp, MII_PHYSID2, &val);
2095 bp->phy_id |= val & 0xffff;
2096
583c28e5 2097 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
5b0c76ad
MC		 2098 if (CHIP_NUM(bp) == CHIP_NUM_5706)
2099 rc = bnx2_init_5706s_phy(bp);
2100 else if (CHIP_NUM(bp) == CHIP_NUM_5708)
2101 rc = bnx2_init_5708s_phy(bp);
27a005b8
MC		 2102 else if (CHIP_NUM(bp) == CHIP_NUM_5709)
2103 rc = bnx2_init_5709s_phy(bp);
b6016b76
MC		 2104 }
2105 else {
2106 rc = bnx2_init_copper_phy(bp);
2107 }
2108
0d8a6571
MC		 2109setup_phy:
2110 if (!rc)
2111 rc = bnx2_setup_phy(bp, bp->phy_port);
b6016b76
MC		 2112
2113 return rc;
2114}
2115
2116static int
2117bnx2_set_mac_loopback(struct bnx2 *bp)
2118{
2119 u32 mac_mode;
2120
2121 mac_mode = REG_RD(bp, BNX2_EMAC_MODE);
2122 mac_mode &= ~BNX2_EMAC_MODE_PORT;
2123 mac_mode |= BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK;
2124 REG_WR(bp, BNX2_EMAC_MODE, mac_mode);
2125 bp->link_up = 1;
2126 return 0;
2127}
2128
bc5a0690
MC		 2129static int bnx2_test_link(struct bnx2 *);
2130
2131static int
2132bnx2_set_phy_loopback(struct bnx2 *bp)
2133{
2134 u32 mac_mode;
2135 int rc, i;
2136
2137 spin_lock_bh(&bp->phy_lock);
ca58c3af 2138 rc = bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK | BMCR_FULLDPLX |
bc5a0690
MC		 2139 BMCR_SPEED1000);
2140 spin_unlock_bh(&bp->phy_lock);
2141 if (rc)
2142 return rc;
2143
2144 for (i = 0; i < 10; i++) {
2145 if (bnx2_test_link(bp) == 0)
2146 break;
80be4434 2147 msleep(100);
bc5a0690
MC		 2148 }
2149
2150 mac_mode = REG_RD(bp, BNX2_EMAC_MODE);
2151 mac_mode &= ~(BNX2_EMAC_MODE_PORT | BNX2_EMAC_MODE_HALF_DUPLEX |
2152 BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK |
59b47d8a 2153 BNX2_EMAC_MODE_25G_MODE);
bc5a0690
MC		 2154
2155 mac_mode |= BNX2_EMAC_MODE_PORT_GMII;
2156 REG_WR(bp, BNX2_EMAC_MODE, mac_mode);
2157 bp->link_up = 1;
2158 return 0;
2159}
2160
b6016b76 2161static int
b090ae2b 2162bnx2_fw_sync(struct bnx2 *bp, u32 msg_data, int silent)
b6016b76
MC		 2163{
2164 int i;
2165 u32 val;
2166
b6016b76
MC		 2167 bp->fw_wr_seq++;
2168 msg_data |= bp->fw_wr_seq;
2169
2726d6e1 2170 bnx2_shmem_wr(bp, BNX2_DRV_MB, msg_data);
b6016b76
MC		 2171
2172 /* wait for an acknowledgement. */
b090ae2b
MC		 2173 for (i = 0; i < (FW_ACK_TIME_OUT_MS / 10); i++) {
2174 msleep(10);
b6016b76 2175
2726d6e1 2176 val = bnx2_shmem_rd(bp, BNX2_FW_MB);
b6016b76
MC		 2177
2178 if ((val & BNX2_FW_MSG_ACK) == (msg_data & BNX2_DRV_MSG_SEQ))
2179 break;
2180 }
b090ae2b
MC		 2181 if ((msg_data & BNX2_DRV_MSG_DATA) == BNX2_DRV_MSG_DATA_WAIT0)
2182 return 0;
b6016b76
MC		 2183
2184 /* If we timed out, inform the firmware that this is the case. */
b090ae2b
MC		 2185 if ((val & BNX2_FW_MSG_ACK) != (msg_data & BNX2_DRV_MSG_SEQ)) {
2186 if (!silent)
2187 printk(KERN_ERR PFX "fw sync timeout, reset code = "
2188 "%x\n", msg_data);
b6016b76
MC		 2189
2190 msg_data &= ~BNX2_DRV_MSG_CODE;
2191 msg_data |= BNX2_DRV_MSG_CODE_FW_TIMEOUT;
2192
2726d6e1 2193 bnx2_shmem_wr(bp, BNX2_DRV_MB, msg_data);
b6016b76 2194
b6016b76
MC		 2195 return -EBUSY;
2196 }
2197
b090ae2b
MC		 2198 if ((val & BNX2_FW_MSG_STATUS_MASK) != BNX2_FW_MSG_STATUS_OK)
2199 return -EIO;
2200
b6016b76
MC		 2201 return 0;
2202}
2203
59b47d8a
MC		 2204static int
2205bnx2_init_5709_context(struct bnx2 *bp)
2206{
2207 int i, ret = 0;
2208 u32 val;
2209
2210 val = BNX2_CTX_COMMAND_ENABLED | BNX2_CTX_COMMAND_MEM_INIT | (1 << 12);
2211 val |= (BCM_PAGE_BITS - 8) << 16;
2212 REG_WR(bp, BNX2_CTX_COMMAND, val);
641bdcd5
MC		 2213 for (i = 0; i < 10; i++) {
2214 val = REG_RD(bp, BNX2_CTX_COMMAND);
2215 if (!(val & BNX2_CTX_COMMAND_MEM_INIT))
2216 break;
2217 udelay(2);
2218 }
2219 if (val & BNX2_CTX_COMMAND_MEM_INIT)
2220 return -EBUSY;
2221
59b47d8a
MC		 2222 for (i = 0; i < bp->ctx_pages; i++) {
2223 int j;
2224
352f7687
MC		 2225 if (bp->ctx_blk[i])
2226 memset(bp->ctx_blk[i], 0, BCM_PAGE_SIZE);
2227 else
2228 return -ENOMEM;
2229
59b47d8a
MC		 2230 REG_WR(bp, BNX2_CTX_HOST_PAGE_TBL_DATA0,
2231 (bp->ctx_blk_mapping[i] & 0xffffffff) |
2232 BNX2_CTX_HOST_PAGE_TBL_DATA0_VALID);
2233 REG_WR(bp, BNX2_CTX_HOST_PAGE_TBL_DATA1,
2234 (u64) bp->ctx_blk_mapping[i] >> 32);
2235 REG_WR(bp, BNX2_CTX_HOST_PAGE_TBL_CTRL, i |
2236 BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ);
2237 for (j = 0; j < 10; j++) {
2238
2239 val = REG_RD(bp, BNX2_CTX_HOST_PAGE_TBL_CTRL);
2240 if (!(val & BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ))
2241 break;
2242 udelay(5);
2243 }
2244 if (val & BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ) {
2245 ret = -EBUSY;
2246 break;
2247 }
2248 }
2249 return ret;
2250}
2251
b6016b76
MC		 2252static void
2253bnx2_init_context(struct bnx2 *bp)
2254{
2255 u32 vcid;
2256
2257 vcid = 96;
2258 while (vcid) {
2259 u32 vcid_addr, pcid_addr, offset;
7947b20e 2260 int i;
b6016b76
MC		 2261
2262 vcid--;
2263
2264 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
2265 u32 new_vcid;
2266
2267 vcid_addr = GET_PCID_ADDR(vcid);
2268 if (vcid & 0x8) {
2269 new_vcid = 0x60 + (vcid & 0xf0) + (vcid & 0x7);
2270 }
2271 else {
2272 new_vcid = vcid;
2273 }
2274 pcid_addr = GET_PCID_ADDR(new_vcid);
2275 }
2276 else {
2277 vcid_addr = GET_CID_ADDR(vcid);
2278 pcid_addr = vcid_addr;
2279 }
2280
7947b20e
MC		 2281 for (i = 0; i < (CTX_SIZE / PHY_CTX_SIZE); i++) {
2282 vcid_addr += (i << PHY_CTX_SHIFT);
2283 pcid_addr += (i << PHY_CTX_SHIFT);
b6016b76 2284
5d5d0015 2285 REG_WR(bp, BNX2_CTX_VIRT_ADDR, vcid_addr);
7947b20e 2286 REG_WR(bp, BNX2_CTX_PAGE_TBL, pcid_addr);
b6016b76 2287
7947b20e
MC		 2288 /* Zero out the context. */
2289 for (offset = 0; offset < PHY_CTX_SIZE; offset += 4)
62a8313c 2290 bnx2_ctx_wr(bp, vcid_addr, offset, 0);
7947b20e 2291 }
b6016b76
MC		 2292 }
2293}
2294
2295static int
2296bnx2_alloc_bad_rbuf(struct bnx2 *bp)
2297{
2298 u16 *good_mbuf;
2299 u32 good_mbuf_cnt;
2300 u32 val;
2301
2302 good_mbuf = kmalloc(512 * sizeof(u16), GFP_KERNEL);
2303 if (good_mbuf == NULL) {
2304 printk(KERN_ERR PFX "Failed to allocate memory in "
2305 "bnx2_alloc_bad_rbuf\n");
2306 return -ENOMEM;
2307 }
2308
2309 REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS,
2310 BNX2_MISC_ENABLE_SET_BITS_RX_MBUF_ENABLE);
2311
2312 good_mbuf_cnt = 0;
2313
2314 /* Allocate a bunch of mbufs and save the good ones in an array. */
2726d6e1 2315 val = bnx2_reg_rd_ind(bp, BNX2_RBUF_STATUS1);
b6016b76 2316 while (val & BNX2_RBUF_STATUS1_FREE_COUNT) {
2726d6e1
MC		 2317 bnx2_reg_wr_ind(bp, BNX2_RBUF_COMMAND,
2318 BNX2_RBUF_COMMAND_ALLOC_REQ);
b6016b76 2319
2726d6e1 2320 val = bnx2_reg_rd_ind(bp, BNX2_RBUF_FW_BUF_ALLOC);
b6016b76
MC		 2321
2322 val &= BNX2_RBUF_FW_BUF_ALLOC_VALUE;
2323
2324 /* The addresses with Bit 9 set are bad memory blocks. */
2325 if (!(val & (1 << 9))) {
2326 good_mbuf[good_mbuf_cnt] = (u16) val;
2327 good_mbuf_cnt++;
2328 }
2329
2726d6e1 2330 val = bnx2_reg_rd_ind(bp, BNX2_RBUF_STATUS1);
b6016b76
MC		 2331 }
2332
2333 /* Free the good ones back to the mbuf pool thus discarding
2334 * all the bad ones. */
2335 while (good_mbuf_cnt) {
2336 good_mbuf_cnt--;
2337
2338 val = good_mbuf[good_mbuf_cnt];
2339 val = (val << 9) | val | 1;
2340
2726d6e1 2341 bnx2_reg_wr_ind(bp, BNX2_RBUF_FW_BUF_FREE, val);
b6016b76
MC		 2342 }
2343 kfree(good_mbuf);
2344 return 0;
2345}
2346
2347static void
6aa20a22 2348bnx2_set_mac_addr(struct bnx2 *bp)
b6016b76
MC		 2349{
2350 u32 val;
2351 u8 *mac_addr = bp->dev->dev_addr;
2352
2353 val = (mac_addr[0] << 8) | mac_addr[1];
2354
2355 REG_WR(bp, BNX2_EMAC_MAC_MATCH0, val);
2356
6aa20a22 2357 val = (mac_addr[2] << 24) | (mac_addr[3] << 16) |
b6016b76
MC		 2358 (mac_addr[4] << 8) | mac_addr[5];
2359
2360 REG_WR(bp, BNX2_EMAC_MAC_MATCH1, val);
2361}
2362
47bf4246
MC		 2363static inline int
2364bnx2_alloc_rx_page(struct bnx2 *bp, u16 index)
2365{
2366 dma_addr_t mapping;
2367 struct sw_pg *rx_pg = &bp->rx_pg_ring[index];
2368 struct rx_bd *rxbd =
2369 &bp->rx_pg_desc_ring[RX_RING(index)][RX_IDX(index)];
2370 struct page *page = alloc_page(GFP_ATOMIC);
2371
2372 if (!page)
2373 return -ENOMEM;
2374 mapping = pci_map_page(bp->pdev, page, 0, PAGE_SIZE,
2375 PCI_DMA_FROMDEVICE);
2376 rx_pg->page = page;
2377 pci_unmap_addr_set(rx_pg, mapping, mapping);
2378 rxbd->rx_bd_haddr_hi = (u64) mapping >> 32;
2379 rxbd->rx_bd_haddr_lo = (u64) mapping & 0xffffffff;
2380 return 0;
2381}
2382
2383static void
2384bnx2_free_rx_page(struct bnx2 *bp, u16 index)
2385{
2386 struct sw_pg *rx_pg = &bp->rx_pg_ring[index];
2387 struct page *page = rx_pg->page;
2388
2389 if (!page)
2390 return;
2391
2392 pci_unmap_page(bp->pdev, pci_unmap_addr(rx_pg, mapping), PAGE_SIZE,
2393 PCI_DMA_FROMDEVICE);
2394
2395 __free_page(page);
2396 rx_pg->page = NULL;
2397}
2398
b6016b76 2399static inline int
a1f60190 2400bnx2_alloc_rx_skb(struct bnx2 *bp, struct bnx2_napi *bnapi, u16 index)
b6016b76
MC		 2401{
2402 struct sk_buff *skb;
2403 struct sw_bd *rx_buf = &bp->rx_buf_ring[index];
2404 dma_addr_t mapping;
13daffa2 2405 struct rx_bd *rxbd = &bp->rx_desc_ring[RX_RING(index)][RX_IDX(index)];
b6016b76
MC		 2406 unsigned long align;
2407
932f3772 2408 skb = netdev_alloc_skb(bp->dev, bp->rx_buf_size);
b6016b76
MC		 2409 if (skb == NULL) {
2410 return -ENOMEM;
2411 }
2412
59b47d8a
MC		 2413 if (unlikely((align = (unsigned long) skb->data & (BNX2_RX_ALIGN - 1))))
2414 skb_reserve(skb, BNX2_RX_ALIGN - align);
b6016b76 2415
b6016b76
MC		 2416 mapping = pci_map_single(bp->pdev, skb->data, bp->rx_buf_use_size,
2417 PCI_DMA_FROMDEVICE);
2418
2419 rx_buf->skb = skb;
2420 pci_unmap_addr_set(rx_buf, mapping, mapping);
2421
2422 rxbd->rx_bd_haddr_hi = (u64) mapping >> 32;
2423 rxbd->rx_bd_haddr_lo = (u64) mapping & 0xffffffff;
2424
a1f60190 2425 bnapi->rx_prod_bseq += bp->rx_buf_use_size;
b6016b76
MC		 2426
2427 return 0;
2428}
2429
da3e4fbe 2430static int
35efa7c1 2431bnx2_phy_event_is_set(struct bnx2 *bp, struct bnx2_napi *bnapi, u32 event)
b6016b76 2432{
35efa7c1 2433 struct status_block *sblk = bnapi->status_blk;
b6016b76 2434 u32 new_link_state, old_link_state;
da3e4fbe 2435 int is_set = 1;
b6016b76 2436
da3e4fbe
MC		 2437 new_link_state = sblk->status_attn_bits & event;
2438 old_link_state = sblk->status_attn_bits_ack & event;
b6016b76 2439 if (new_link_state != old_link_state) {
da3e4fbe
MC		 2440 if (new_link_state)
2441 REG_WR(bp, BNX2_PCICFG_STATUS_BIT_SET_CMD, event);
2442 else
2443 REG_WR(bp, BNX2_PCICFG_STATUS_BIT_CLEAR_CMD, event);
2444 } else
2445 is_set = 0;
2446
2447 return is_set;
2448}
2449
2450static void
35efa7c1 2451bnx2_phy_int(struct bnx2 *bp, struct bnx2_napi *bnapi)
da3e4fbe 2452{
74ecc62d
MC		 2453 spin_lock(&bp->phy_lock);
2454
2455 if (bnx2_phy_event_is_set(bp, bnapi, STATUS_ATTN_BITS_LINK_STATE))
b6016b76 2456 bnx2_set_link(bp);
35efa7c1 2457 if (bnx2_phy_event_is_set(bp, bnapi, STATUS_ATTN_BITS_TIMER_ABORT))
0d8a6571
MC		 2458 bnx2_set_remote_link(bp);
2459
74ecc62d
MC		 2460 spin_unlock(&bp->phy_lock);
2461
b6016b76
MC		 2462}
2463
ead7270b 2464static inline u16
35efa7c1 2465bnx2_get_hw_tx_cons(struct bnx2_napi *bnapi)
ead7270b
MC		 2466{
2467 u16 cons;
2468
c76c0475
MC		 2469 if (bnapi->int_num == 0)
2470 cons = bnapi->status_blk->status_tx_quick_consumer_index0;
2471 else
2472 cons = bnapi->status_blk_msix->status_tx_quick_consumer_index;
ead7270b
MC		 2473
2474 if (unlikely((cons & MAX_TX_DESC_CNT) == MAX_TX_DESC_CNT))
2475 cons++;
2476 return cons;
2477}
2478
57851d84
MC		 2479static int
2480bnx2_tx_int(struct bnx2 *bp, struct bnx2_napi *bnapi, int budget)
b6016b76
MC		 2481{
2482 u16 hw_cons, sw_cons, sw_ring_cons;
57851d84 2483 int tx_pkt = 0;
b6016b76 2484
35efa7c1 2485 hw_cons = bnx2_get_hw_tx_cons(bnapi);
a550c99b 2486 sw_cons = bnapi->tx_cons;
b6016b76
MC		 2487
2488 while (sw_cons != hw_cons) {
2489 struct sw_bd *tx_buf;
2490 struct sk_buff *skb;
2491 int i, last;
2492
2493 sw_ring_cons = TX_RING_IDX(sw_cons);
2494
2495 tx_buf = &bp->tx_buf_ring[sw_ring_cons];
2496 skb = tx_buf->skb;
1d39ed56 2497
b6016b76 2498 /* partial BD completions possible with TSO packets */
89114afd 2499 if (skb_is_gso(skb)) {
b6016b76
MC		 2500 u16 last_idx, last_ring_idx;
2501
2502 last_idx = sw_cons +
2503 skb_shinfo(skb)->nr_frags + 1;
2504 last_ring_idx = sw_ring_cons +
2505 skb_shinfo(skb)->nr_frags + 1;
2506 if (unlikely(last_ring_idx >= MAX_TX_DESC_CNT)) {
2507 last_idx++;
2508 }
2509 if (((s16) ((s16) last_idx - (s16) hw_cons)) > 0) {
2510 break;
2511 }
2512 }
1d39ed56 2513
b6016b76
MC		 2514 pci_unmap_single(bp->pdev, pci_unmap_addr(tx_buf, mapping),
2515 skb_headlen(skb), PCI_DMA_TODEVICE);
2516
2517 tx_buf->skb = NULL;
2518 last = skb_shinfo(skb)->nr_frags;
2519
2520 for (i = 0; i < last; i++) {
2521 sw_cons = NEXT_TX_BD(sw_cons);
2522
2523 pci_unmap_page(bp->pdev,
2524 pci_unmap_addr(
2525 &bp->tx_buf_ring[TX_RING_IDX(sw_cons)],
2526 mapping),
2527 skb_shinfo(skb)->frags[i].size,
2528 PCI_DMA_TODEVICE);
2529 }
2530
2531 sw_cons = NEXT_TX_BD(sw_cons);
2532
745720e5 2533 dev_kfree_skb(skb);
57851d84
MC		 2534 tx_pkt++;
2535 if (tx_pkt == budget)
2536 break;
b6016b76 2537
35efa7c1 2538 hw_cons = bnx2_get_hw_tx_cons(bnapi);
b6016b76
MC		 2539 }
2540
a550c99b
MC		 2541 bnapi->hw_tx_cons = hw_cons;
2542 bnapi->tx_cons = sw_cons;
2f8af120
MC		 2543 /* Need to make the tx_cons update visible to bnx2_start_xmit()
2544 * before checking for netif_queue_stopped(). Without the
2545 * memory barrier, there is a small possibility that bnx2_start_xmit()
2546 * will miss it and cause the queue to be stopped forever.
2547 */
2548 smp_mb();
b6016b76 2549
2f8af120 2550 if (unlikely(netif_queue_stopped(bp->dev)) &&
a550c99b 2551 (bnx2_tx_avail(bp, bnapi) > bp->tx_wake_thresh)) {
2f8af120 2552 netif_tx_lock(bp->dev);
b6016b76 2553 if ((netif_queue_stopped(bp->dev)) &&
a550c99b 2554 (bnx2_tx_avail(bp, bnapi) > bp->tx_wake_thresh))
b6016b76 2555 netif_wake_queue(bp->dev);
2f8af120 2556 netif_tx_unlock(bp->dev);
b6016b76 2557 }
57851d84 2558 return tx_pkt;
b6016b76
MC		 2559}
2560
1db82f2a 2561static void
a1f60190
MC		 2562bnx2_reuse_rx_skb_pages(struct bnx2 *bp, struct bnx2_napi *bnapi,
2563 struct sk_buff *skb, int count)
1db82f2a
MC		 2564{
2565 struct sw_pg *cons_rx_pg, *prod_rx_pg;
2566 struct rx_bd *cons_bd, *prod_bd;
2567 dma_addr_t mapping;
2568 int i;
a1f60190
MC		 2569 u16 hw_prod = bnapi->rx_pg_prod, prod;
2570 u16 cons = bnapi->rx_pg_cons;
1db82f2a
MC		 2571
2572 for (i = 0; i < count; i++) {
2573 prod = RX_PG_RING_IDX(hw_prod);
2574
2575 prod_rx_pg = &bp->rx_pg_ring[prod];
2576 cons_rx_pg = &bp->rx_pg_ring[cons];
2577 cons_bd = &bp->rx_pg_desc_ring[RX_RING(cons)][RX_IDX(cons)];
2578 prod_bd = &bp->rx_pg_desc_ring[RX_RING(prod)][RX_IDX(prod)];
2579
2580 if (i == 0 && skb) {
2581 struct page *page;
2582 struct skb_shared_info *shinfo;
2583
2584 shinfo = skb_shinfo(skb);
2585 shinfo->nr_frags--;
2586 page = shinfo->frags[shinfo->nr_frags].page;
2587 shinfo->frags[shinfo->nr_frags].page = NULL;
2588 mapping = pci_map_page(bp->pdev, page, 0, PAGE_SIZE,
2589 PCI_DMA_FROMDEVICE);
2590 cons_rx_pg->page = page;
2591 pci_unmap_addr_set(cons_rx_pg, mapping, mapping);
2592 dev_kfree_skb(skb);
2593 }
2594 if (prod != cons) {
2595 prod_rx_pg->page = cons_rx_pg->page;
2596 cons_rx_pg->page = NULL;
2597 pci_unmap_addr_set(prod_rx_pg, mapping,
2598 pci_unmap_addr(cons_rx_pg, mapping));
2599
2600 prod_bd->rx_bd_haddr_hi = cons_bd->rx_bd_haddr_hi;
2601 prod_bd->rx_bd_haddr_lo = cons_bd->rx_bd_haddr_lo;
2602
2603 }
2604 cons = RX_PG_RING_IDX(NEXT_RX_BD(cons));
2605 hw_prod = NEXT_RX_BD(hw_prod);
2606 }
a1f60190
MC		 2607 bnapi->rx_pg_prod = hw_prod;
2608 bnapi->rx_pg_cons = cons;
1db82f2a
MC		 2609}
2610
b6016b76 2611static inline void
a1f60190 2612bnx2_reuse_rx_skb(struct bnx2 *bp, struct bnx2_napi *bnapi, struct sk_buff *skb,
b6016b76
MC		 2613 u16 cons, u16 prod)
2614{
236b6394
MC		 2615 struct sw_bd *cons_rx_buf, *prod_rx_buf;
2616 struct rx_bd *cons_bd, *prod_bd;
2617
2618 cons_rx_buf = &bp->rx_buf_ring[cons];
2619 prod_rx_buf = &bp->rx_buf_ring[prod];
b6016b76
MC		 2620
2621 pci_dma_sync_single_for_device(bp->pdev,
2622 pci_unmap_addr(cons_rx_buf, mapping),
2623 bp->rx_offset + RX_COPY_THRESH, PCI_DMA_FROMDEVICE);
2624
a1f60190 2625 bnapi->rx_prod_bseq += bp->rx_buf_use_size;
b6016b76 2626
236b6394 2627 prod_rx_buf->skb = skb;
b6016b76 2628
236b6394
MC		 2629 if (cons == prod)
2630 return;
b6016b76 2631
236b6394
MC		 2632 pci_unmap_addr_set(prod_rx_buf, mapping,
2633 pci_unmap_addr(cons_rx_buf, mapping));
2634
3fdfcc2c
MC		 2635 cons_bd = &bp->rx_desc_ring[RX_RING(cons)][RX_IDX(cons)];
2636 prod_bd = &bp->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)];
236b6394
MC		 2637 prod_bd->rx_bd_haddr_hi = cons_bd->rx_bd_haddr_hi;
2638 prod_bd->rx_bd_haddr_lo = cons_bd->rx_bd_haddr_lo;
b6016b76
MC		 2639}
2640
85833c62 2641static int
a1f60190
MC		 2642bnx2_rx_skb(struct bnx2 *bp, struct bnx2_napi *bnapi, struct sk_buff *skb,
2643 unsigned int len, unsigned int hdr_len, dma_addr_t dma_addr,
2644 u32 ring_idx)
85833c62
MC		 2645{
2646 int err;
2647 u16 prod = ring_idx & 0xffff;
2648
a1f60190 2649 err = bnx2_alloc_rx_skb(bp, bnapi, prod);
85833c62 2650 if (unlikely(err)) {
a1f60190 2651 bnx2_reuse_rx_skb(bp, bnapi, skb, (u16) (ring_idx >> 16), prod);
1db82f2a
MC		 2652 if (hdr_len) {
2653 unsigned int raw_len = len + 4;
2654 int pages = PAGE_ALIGN(raw_len - hdr_len) >> PAGE_SHIFT;
2655
a1f60190 2656 bnx2_reuse_rx_skb_pages(bp, bnapi, NULL, pages);
1db82f2a 2657 }
85833c62
MC		 2658 return err;
2659 }
2660
2661 skb_reserve(skb, bp->rx_offset);
2662 pci_unmap_single(bp->pdev, dma_addr, bp->rx_buf_use_size,
2663 PCI_DMA_FROMDEVICE);
2664
1db82f2a
MC		 2665 if (hdr_len == 0) {
2666 skb_put(skb, len);
2667 return 0;
2668 } else {
2669 unsigned int i, frag_len, frag_size, pages;
2670 struct sw_pg *rx_pg;
a1f60190
MC		 2671 u16 pg_cons = bnapi->rx_pg_cons;
2672 u16 pg_prod = bnapi->rx_pg_prod;
1db82f2a
MC		 2673
2674 frag_size = len + 4 - hdr_len;
2675 pages = PAGE_ALIGN(frag_size) >> PAGE_SHIFT;
2676 skb_put(skb, hdr_len);
2677
2678 for (i = 0; i < pages; i++) {
2679 frag_len = min(frag_size, (unsigned int) PAGE_SIZE);
2680 if (unlikely(frag_len <= 4)) {
2681 unsigned int tail = 4 - frag_len;
2682
a1f60190
MC		 2683 bnapi->rx_pg_cons = pg_cons;
2684 bnapi->rx_pg_prod = pg_prod;
2685 bnx2_reuse_rx_skb_pages(bp, bnapi, NULL,
2686 pages - i);
1db82f2a
MC		 2687 skb->len -= tail;
2688 if (i == 0) {
2689 skb->tail -= tail;
2690 } else {
2691 skb_frag_t *frag =
2692 &skb_shinfo(skb)->frags[i - 1];
2693 frag->size -= tail;
2694 skb->data_len -= tail;
2695 skb->truesize -= tail;
2696 }
2697 return 0;
2698 }
2699 rx_pg = &bp->rx_pg_ring[pg_cons];
2700
2701 pci_unmap_page(bp->pdev, pci_unmap_addr(rx_pg, mapping),
2702 PAGE_SIZE, PCI_DMA_FROMDEVICE);
2703
2704 if (i == pages - 1)
2705 frag_len -= 4;
2706
2707 skb_fill_page_desc(skb, i, rx_pg->page, 0, frag_len);
2708 rx_pg->page = NULL;
2709
2710 err = bnx2_alloc_rx_page(bp, RX_PG_RING_IDX(pg_prod));
2711 if (unlikely(err)) {
a1f60190
MC		 2712 bnapi->rx_pg_cons = pg_cons;
2713 bnapi->rx_pg_prod = pg_prod;
2714 bnx2_reuse_rx_skb_pages(bp, bnapi, skb,
2715 pages - i);
1db82f2a
MC		 2716 return err;
2717 }
2718
2719 frag_size -= frag_len;
2720 skb->data_len += frag_len;
2721 skb->truesize += frag_len;
2722 skb->len += frag_len;
2723
2724 pg_prod = NEXT_RX_BD(pg_prod);
2725 pg_cons = RX_PG_RING_IDX(NEXT_RX_BD(pg_cons));
2726 }
a1f60190
MC		 2727 bnapi->rx_pg_prod = pg_prod;
2728 bnapi->rx_pg_cons = pg_cons;
1db82f2a 2729 }
85833c62
MC		 2730 return 0;
2731}
2732
c09c2627 2733static inline u16
35efa7c1 2734bnx2_get_hw_rx_cons(struct bnx2_napi *bnapi)
c09c2627 2735{
35efa7c1 2736 u16 cons = bnapi->status_blk->status_rx_quick_consumer_index0;
c09c2627
MC		 2737
2738 if (unlikely((cons & MAX_RX_DESC_CNT) == MAX_RX_DESC_CNT))
2739 cons++;
2740 return cons;
2741}
2742
b6016b76 2743static int
35efa7c1 2744bnx2_rx_int(struct bnx2 *bp, struct bnx2_napi *bnapi, int budget)
b6016b76
MC		 2745{
2746 u16 hw_cons, sw_cons, sw_ring_cons, sw_prod, sw_ring_prod;
2747 struct l2_fhdr *rx_hdr;
1db82f2a 2748 int rx_pkt = 0, pg_ring_used = 0;
b6016b76 2749
35efa7c1 2750 hw_cons = bnx2_get_hw_rx_cons(bnapi);
a1f60190
MC		 2751 sw_cons = bnapi->rx_cons;
2752 sw_prod = bnapi->rx_prod;
b6016b76
MC		 2753
2754 /* Memory barrier necessary as speculative reads of the rx
2755 * buffer can be ahead of the index in the status block
2756 */
2757 rmb();
2758 while (sw_cons != hw_cons) {
1db82f2a 2759 unsigned int len, hdr_len;
ade2bfe7 2760 u32 status;
b6016b76
MC		 2761 struct sw_bd *rx_buf;
2762 struct sk_buff *skb;
236b6394 2763 dma_addr_t dma_addr;
b6016b76
MC		 2764
2765 sw_ring_cons = RX_RING_IDX(sw_cons);
2766 sw_ring_prod = RX_RING_IDX(sw_prod);
2767
2768 rx_buf = &bp->rx_buf_ring[sw_ring_cons];
2769 skb = rx_buf->skb;
236b6394
MC		 2770
2771 rx_buf->skb = NULL;
2772
2773 dma_addr = pci_unmap_addr(rx_buf, mapping);
2774
2775 pci_dma_sync_single_for_cpu(bp->pdev, dma_addr,
b6016b76
MC		 2776 bp->rx_offset + RX_COPY_THRESH, PCI_DMA_FROMDEVICE);
2777
2778 rx_hdr = (struct l2_fhdr *) skb->data;
1db82f2a 2779 len = rx_hdr->l2_fhdr_pkt_len;
b6016b76 2780
ade2bfe7 2781 if ((status = rx_hdr->l2_fhdr_status) &
b6016b76
MC		 2782 (L2_FHDR_ERRORS_BAD_CRC |
2783 L2_FHDR_ERRORS_PHY_DECODE |
2784 L2_FHDR_ERRORS_ALIGNMENT |
2785 L2_FHDR_ERRORS_TOO_SHORT |
2786 L2_FHDR_ERRORS_GIANT_FRAME)) {
2787
a1f60190
MC		 2788 bnx2_reuse_rx_skb(bp, bnapi, skb, sw_ring_cons,
2789 sw_ring_prod);
85833c62 2790 goto next_rx;
b6016b76 2791 }
1db82f2a
MC		 2792 hdr_len = 0;
2793 if (status & L2_FHDR_STATUS_SPLIT) {
2794 hdr_len = rx_hdr->l2_fhdr_ip_xsum;
2795 pg_ring_used = 1;
2796 } else if (len > bp->rx_jumbo_thresh) {
2797 hdr_len = bp->rx_jumbo_thresh;
2798 pg_ring_used = 1;
2799 }
2800
2801 len -= 4;
b6016b76 2802
5d5d0015 2803 if (len <= bp->rx_copy_thresh) {
b6016b76
MC		 2804 struct sk_buff *new_skb;
2805
932f3772 2806 new_skb = netdev_alloc_skb(bp->dev, len + 2);
85833c62 2807 if (new_skb == NULL) {
a1f60190 2808 bnx2_reuse_rx_skb(bp, bnapi, skb, sw_ring_cons,
85833c62
MC		 2809 sw_ring_prod);
2810 goto next_rx;
2811 }
b6016b76
MC		 2812
2813 /* aligned copy */
d626f62b
ACM		 2814 skb_copy_from_linear_data_offset(skb, bp->rx_offset - 2,
2815 new_skb->data, len + 2);
b6016b76
MC		 2816 skb_reserve(new_skb, 2);
2817 skb_put(new_skb, len);
b6016b76 2818
a1f60190 2819 bnx2_reuse_rx_skb(bp, bnapi, skb,
b6016b76
MC		 2820 sw_ring_cons, sw_ring_prod);
2821
2822 skb = new_skb;
a1f60190
MC		 2823 } else if (unlikely(bnx2_rx_skb(bp, bnapi, skb, len, hdr_len,
2824 dma_addr, (sw_ring_cons << 16) | sw_ring_prod)))
b6016b76 2825 goto next_rx;
b6016b76
MC		 2826
2827 skb->protocol = eth_type_trans(skb, bp->dev);
2828
2829 if ((len > (bp->dev->mtu + ETH_HLEN)) &&
d1e100ba 2830 (ntohs(skb->protocol) != 0x8100)) {
b6016b76 2831
745720e5 2832 dev_kfree_skb(skb);
b6016b76
MC		 2833 goto next_rx;
2834
2835 }
2836
b6016b76
MC		 2837 skb->ip_summed = CHECKSUM_NONE;
2838 if (bp->rx_csum &&
2839 (status & (L2_FHDR_STATUS_TCP_SEGMENT |
2840 L2_FHDR_STATUS_UDP_DATAGRAM))) {
2841
ade2bfe7
MC		 2842 if (likely((status & (L2_FHDR_ERRORS_TCP_XSUM |
2843 L2_FHDR_ERRORS_UDP_XSUM)) == 0))
b6016b76
MC		 2844 skb->ip_summed = CHECKSUM_UNNECESSARY;
2845 }
2846
2847#ifdef BCM_VLAN
79ea13ce 2848 if ((status & L2_FHDR_STATUS_L2_VLAN_TAG) && bp->vlgrp) {
b6016b76
MC		 2849 vlan_hwaccel_receive_skb(skb, bp->vlgrp,
2850 rx_hdr->l2_fhdr_vlan_tag);
2851 }
2852 else
2853#endif
2854 netif_receive_skb(skb);
2855
2856 bp->dev->last_rx = jiffies;
2857 rx_pkt++;
2858
2859next_rx:
b6016b76
MC		 2860 sw_cons = NEXT_RX_BD(sw_cons);
2861 sw_prod = NEXT_RX_BD(sw_prod);
2862
2863 if ((rx_pkt == budget))
2864 break;
f4e418f7
MC		 2865
2866 /* Refresh hw_cons to see if there is new work */
2867 if (sw_cons == hw_cons) {
35efa7c1 2868 hw_cons = bnx2_get_hw_rx_cons(bnapi);
f4e418f7
MC		 2869 rmb();
2870 }
b6016b76 2871 }
a1f60190
MC		 2872 bnapi->rx_cons = sw_cons;
2873 bnapi->rx_prod = sw_prod;
b6016b76 2874
1db82f2a
MC		 2875 if (pg_ring_used)
2876 REG_WR16(bp, MB_RX_CID_ADDR + BNX2_L2CTX_HOST_PG_BDIDX,
a1f60190 2877 bnapi->rx_pg_prod);
1db82f2a 2878
b6016b76
MC		 2879 REG_WR16(bp, MB_RX_CID_ADDR + BNX2_L2CTX_HOST_BDIDX, sw_prod);
2880
a1f60190 2881 REG_WR(bp, MB_RX_CID_ADDR + BNX2_L2CTX_HOST_BSEQ, bnapi->rx_prod_bseq);
b6016b76
MC		 2882
2883 mmiowb();
2884
2885 return rx_pkt;
2886
2887}
2888
2889/* MSI ISR - The only difference between this and the INTx ISR
2890 * is that the MSI interrupt is always serviced.
2891 */
2892static irqreturn_t
7d12e780 2893bnx2_msi(int irq, void *dev_instance)
b6016b76
MC		 2894{
2895 struct net_device *dev = dev_instance;
972ec0d4 2896 struct bnx2 *bp = netdev_priv(dev);
b4b36042 2897 struct bnx2_napi *bnapi = &bp->bnx2_napi[0];
b6016b76 2898
35efa7c1 2899 prefetch(bnapi->status_blk);
b6016b76
MC		 2900 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
2901 BNX2_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM |
2902 BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
2903
2904 /* Return here if interrupt is disabled. */
73eef4cd
MC		 2905 if (unlikely(atomic_read(&bp->intr_sem) != 0))
2906 return IRQ_HANDLED;
b6016b76 2907
35efa7c1 2908 netif_rx_schedule(dev, &bnapi->napi);
b6016b76 2909
73eef4cd 2910 return IRQ_HANDLED;
b6016b76
MC		 2911}
2912
8e6a72c4
MC		 2913static irqreturn_t
2914bnx2_msi_1shot(int irq, void *dev_instance)
2915{
2916 struct net_device *dev = dev_instance;
2917 struct bnx2 *bp = netdev_priv(dev);
b4b36042 2918 struct bnx2_napi *bnapi = &bp->bnx2_napi[0];
8e6a72c4 2919
35efa7c1 2920 prefetch(bnapi->status_blk);
8e6a72c4
MC		 2921
2922 /* Return here if interrupt is disabled. */
2923 if (unlikely(atomic_read(&bp->intr_sem) != 0))
2924 return IRQ_HANDLED;
2925
35efa7c1 2926 netif_rx_schedule(dev, &bnapi->napi);
8e6a72c4
MC		 2927
2928 return IRQ_HANDLED;
2929}
2930
b6016b76 2931static irqreturn_t
7d12e780 2932bnx2_interrupt(int irq, void *dev_instance)
b6016b76
MC		 2933{
2934 struct net_device *dev = dev_instance;
972ec0d4 2935 struct bnx2 *bp = netdev_priv(dev);
b4b36042 2936 struct bnx2_napi *bnapi = &bp->bnx2_napi[0];
35efa7c1 2937 struct status_block *sblk = bnapi->status_blk;
b6016b76
MC		 2938
2939 /* When using INTx, it is possible for the interrupt to arrive
2940 * at the CPU before the status block posted prior to the
2941 * interrupt. Reading a register will flush the status block.
2942 * When using MSI, the MSI message will always complete after
2943 * the status block write.
2944 */
35efa7c1 2945 if ((sblk->status_idx == bnapi->last_status_idx) &&
b6016b76
MC		 2946 (REG_RD(bp, BNX2_PCICFG_MISC_STATUS) &
2947 BNX2_PCICFG_MISC_STATUS_INTA_VALUE))
73eef4cd 2948 return IRQ_NONE;
b6016b76
MC		 2949
2950 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
2951 BNX2_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM |
2952 BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
2953
b8a7ce7b
MC		 2954 /* Read back to deassert IRQ immediately to avoid too many
2955 * spurious interrupts.
2956 */
2957 REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD);
2958
b6016b76 2959 /* Return here if interrupt is shared and is disabled. */
73eef4cd
MC		 2960 if (unlikely(atomic_read(&bp->intr_sem) != 0))
2961 return IRQ_HANDLED;
b6016b76 2962
35efa7c1
MC		 2963 if (netif_rx_schedule_prep(dev, &bnapi->napi)) {
2964 bnapi->last_status_idx = sblk->status_idx;
2965 __netif_rx_schedule(dev, &bnapi->napi);
b8a7ce7b 2966 }
b6016b76 2967
73eef4cd 2968 return IRQ_HANDLED;
b6016b76
MC		 2969}
2970
57851d84
MC		 2971static irqreturn_t
2972bnx2_tx_msix(int irq, void *dev_instance)
2973{
2974 struct net_device *dev = dev_instance;
2975 struct bnx2 *bp = netdev_priv(dev);
2976 struct bnx2_napi *bnapi = &bp->bnx2_napi[BNX2_TX_VEC];
2977
2978 prefetch(bnapi->status_blk_msix);
2979
2980 /* Return here if interrupt is disabled. */
2981 if (unlikely(atomic_read(&bp->intr_sem) != 0))
2982 return IRQ_HANDLED;
2983
2984 netif_rx_schedule(dev, &bnapi->napi);
2985 return IRQ_HANDLED;
2986}
2987
0d8a6571
MC		 2988#define STATUS_ATTN_EVENTS (STATUS_ATTN_BITS_LINK_STATE | \
2989 STATUS_ATTN_BITS_TIMER_ABORT)
da3e4fbe 2990
f4e418f7 2991static inline int
35efa7c1 2992bnx2_has_work(struct bnx2_napi *bnapi)
f4e418f7 2993{
1097f5e9 2994 struct status_block *sblk = bnapi->status_blk;
f4e418f7 2995
a1f60190 2996 if ((bnx2_get_hw_rx_cons(bnapi) != bnapi->rx_cons) ||
a550c99b 2997 (bnx2_get_hw_tx_cons(bnapi) != bnapi->hw_tx_cons))
f4e418f7
MC		 2998 return 1;
2999
da3e4fbe
MC		 3000 if ((sblk->status_attn_bits & STATUS_ATTN_EVENTS) !=
3001 (sblk->status_attn_bits_ack & STATUS_ATTN_EVENTS))
f4e418f7
MC		 3002 return 1;
3003
3004 return 0;
3005}
3006
57851d84
MC		 3007static int bnx2_tx_poll(struct napi_struct *napi, int budget)
3008{
3009 struct bnx2_napi *bnapi = container_of(napi, struct bnx2_napi, napi);
3010 struct bnx2 *bp = bnapi->bp;
3011 int work_done = 0;
3012 struct status_block_msix *sblk = bnapi->status_blk_msix;
3013
3014 do {
3015 work_done += bnx2_tx_int(bp, bnapi, budget - work_done);
3016 if (unlikely(work_done >= budget))
3017 return work_done;
3018
3019 bnapi->last_status_idx = sblk->status_idx;
3020 rmb();
3021 } while (bnx2_get_hw_tx_cons(bnapi) != bnapi->hw_tx_cons);
3022
3023 netif_rx_complete(bp->dev, napi);
3024 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num |
3025 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
3026 bnapi->last_status_idx);
3027 return work_done;
3028}
3029
35efa7c1
MC		 3030static int bnx2_poll_work(struct bnx2 *bp, struct bnx2_napi *bnapi,
3031 int work_done, int budget)
b6016b76 3032{
35efa7c1 3033 struct status_block *sblk = bnapi->status_blk;
da3e4fbe
MC		 3034 u32 status_attn_bits = sblk->status_attn_bits;
3035 u32 status_attn_bits_ack = sblk->status_attn_bits_ack;
b6016b76 3036
da3e4fbe
MC		 3037 if ((status_attn_bits & STATUS_ATTN_EVENTS) !=
3038 (status_attn_bits_ack & STATUS_ATTN_EVENTS)) {
b6016b76 3039
35efa7c1 3040 bnx2_phy_int(bp, bnapi);
bf5295bb
MC		 3041
3042 /* This is needed to take care of transient status
3043 * during link changes.
3044 */
3045 REG_WR(bp, BNX2_HC_COMMAND,
3046 bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
3047 REG_RD(bp, BNX2_HC_COMMAND);
b6016b76
MC		 3048 }
3049
a550c99b 3050 if (bnx2_get_hw_tx_cons(bnapi) != bnapi->hw_tx_cons)
57851d84 3051 bnx2_tx_int(bp, bnapi, 0);
b6016b76 3052
a1f60190 3053 if (bnx2_get_hw_rx_cons(bnapi) != bnapi->rx_cons)
35efa7c1 3054 work_done += bnx2_rx_int(bp, bnapi, budget - work_done);
6aa20a22 3055
6f535763
DM		 3056 return work_done;
3057}
3058
3059static int bnx2_poll(struct napi_struct *napi, int budget)
3060{
35efa7c1
MC		 3061 struct bnx2_napi *bnapi = container_of(napi, struct bnx2_napi, napi);
3062 struct bnx2 *bp = bnapi->bp;
6f535763 3063 int work_done = 0;
35efa7c1 3064 struct status_block *sblk = bnapi->status_blk;
6f535763
DM		 3065
3066 while (1) {
35efa7c1 3067 work_done = bnx2_poll_work(bp, bnapi, work_done, budget);
f4e418f7 3068
6f535763
DM		 3069 if (unlikely(work_done >= budget))
3070 break;
3071
35efa7c1 3072 /* bnapi->last_status_idx is used below to tell the hw how
6dee6421
MC		 3073 * much work has been processed, so we must read it before
3074 * checking for more work.
3075 */
35efa7c1 3076 bnapi->last_status_idx = sblk->status_idx;
6dee6421 3077 rmb();
35efa7c1 3078 if (likely(!bnx2_has_work(bnapi))) {
6f535763 3079 netif_rx_complete(bp->dev, napi);
f86e82fb 3080 if (likely(bp->flags & BNX2_FLAG_USING_MSI_OR_MSIX)) {
6f535763
DM		 3081 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
3082 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
35efa7c1 3083 bnapi->last_status_idx);
6dee6421 3084 break;
6f535763 3085 }
1269a8a6
MC		 3086 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
3087 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
6f535763 3088 BNX2_PCICFG_INT_ACK_CMD_MASK_INT |
35efa7c1 3089 bnapi->last_status_idx);
1269a8a6 3090
6f535763
DM		 3091 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
3092 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
35efa7c1 3093 bnapi->last_status_idx);
6f535763
DM		 3094 break;
3095 }
b6016b76
MC		 3096 }
3097
bea3348e 3098 return work_done;
b6016b76
MC		 3099}
3100
932ff279 3101/* Called with rtnl_lock from vlan functions and also netif_tx_lock
b6016b76
MC		 3102 * from set_multicast.
3103 */
3104static void
3105bnx2_set_rx_mode(struct net_device *dev)
3106{
972ec0d4 3107 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 3108 u32 rx_mode, sort_mode;
3109 int i;
b6016b76 3110
c770a65c 3111 spin_lock_bh(&bp->phy_lock);
b6016b76
MC		 3112
3113 rx_mode = bp->rx_mode & ~(BNX2_EMAC_RX_MODE_PROMISCUOUS |
3114 BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG);
3115 sort_mode = 1 | BNX2_RPM_SORT_USER0_BC_EN;
3116#ifdef BCM_VLAN
f86e82fb 3117 if (!bp->vlgrp && !(bp->flags & BNX2_FLAG_ASF_ENABLE))
b6016b76 3118 rx_mode |= BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG;
b6016b76 3119#else
f86e82fb 3120 if (!(bp->flags & BNX2_FLAG_ASF_ENABLE))
e29054f9 3121 rx_mode |= BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG;
b6016b76
MC		 3122#endif
3123 if (dev->flags & IFF_PROMISC) {
3124 /* Promiscuous mode. */
3125 rx_mode |= BNX2_EMAC_RX_MODE_PROMISCUOUS;
7510873d
MC		 3126 sort_mode |= BNX2_RPM_SORT_USER0_PROM_EN |
3127 BNX2_RPM_SORT_USER0_PROM_VLAN;
b6016b76
MC		 3128 }
3129 else if (dev->flags & IFF_ALLMULTI) {
3130 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
3131 REG_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),
3132 0xffffffff);
3133 }
3134 sort_mode |= BNX2_RPM_SORT_USER0_MC_EN;
3135 }
3136 else {
3137 /* Accept one or more multicast(s). */
3138 struct dev_mc_list *mclist;
3139 u32 mc_filter[NUM_MC_HASH_REGISTERS];
3140 u32 regidx;
3141 u32 bit;
3142 u32 crc;
3143
3144 memset(mc_filter, 0, 4 * NUM_MC_HASH_REGISTERS);
3145
3146 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
3147 i++, mclist = mclist->next) {
3148
3149 crc = ether_crc_le(ETH_ALEN, mclist->dmi_addr);
3150 bit = crc & 0xff;
3151 regidx = (bit & 0xe0) >> 5;
3152 bit &= 0x1f;
3153 mc_filter[regidx] |= (1 << bit);
3154 }
3155
3156 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
3157 REG_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),
3158 mc_filter[i]);
3159 }
3160
3161 sort_mode |= BNX2_RPM_SORT_USER0_MC_HSH_EN;
3162 }
3163
3164 if (rx_mode != bp->rx_mode) {
3165 bp->rx_mode = rx_mode;
3166 REG_WR(bp, BNX2_EMAC_RX_MODE, rx_mode);
3167 }
3168
3169 REG_WR(bp, BNX2_RPM_SORT_USER0, 0x0);
3170 REG_WR(bp, BNX2_RPM_SORT_USER0, sort_mode);
3171 REG_WR(bp, BNX2_RPM_SORT_USER0, sort_mode | BNX2_RPM_SORT_USER0_ENA);
3172
c770a65c 3173 spin_unlock_bh(&bp->phy_lock);
b6016b76
MC		 3174}
3175
3176static void
b491edd5 3177load_rv2p_fw(struct bnx2 *bp, __le32 *rv2p_code, u32 rv2p_code_len,
b6016b76
MC		 3178 u32 rv2p_proc)
3179{
3180 int i;
3181 u32 val;
3182
d25be1d3
MC		 3183 if (rv2p_proc == RV2P_PROC2 && CHIP_NUM(bp) == CHIP_NUM_5709) {
3184 val = le32_to_cpu(rv2p_code[XI_RV2P_PROC2_MAX_BD_PAGE_LOC]);
3185 val &= ~XI_RV2P_PROC2_BD_PAGE_SIZE_MSK;
3186 val |= XI_RV2P_PROC2_BD_PAGE_SIZE;
3187 rv2p_code[XI_RV2P_PROC2_MAX_BD_PAGE_LOC] = cpu_to_le32(val);
3188 }
b6016b76
MC		 3189
3190 for (i = 0; i < rv2p_code_len; i += 8) {
b491edd5 3191 REG_WR(bp, BNX2_RV2P_INSTR_HIGH, le32_to_cpu(*rv2p_code));
b6016b76 3192 rv2p_code++;
b491edd5 3193 REG_WR(bp, BNX2_RV2P_INSTR_LOW, le32_to_cpu(*rv2p_code));
b6016b76
MC		 3194 rv2p_code++;
3195
3196 if (rv2p_proc == RV2P_PROC1) {
3197 val = (i / 8) | BNX2_RV2P_PROC1_ADDR_CMD_RDWR;
3198 REG_WR(bp, BNX2_RV2P_PROC1_ADDR_CMD, val);
3199 }
3200 else {
3201 val = (i / 8) | BNX2_RV2P_PROC2_ADDR_CMD_RDWR;
3202 REG_WR(bp, BNX2_RV2P_PROC2_ADDR_CMD, val);
3203 }
3204 }
3205
3206 /* Reset the processor, un-stall is done later. */
3207 if (rv2p_proc == RV2P_PROC1) {
3208 REG_WR(bp, BNX2_RV2P_COMMAND, BNX2_RV2P_COMMAND_PROC1_RESET);
3209 }
3210 else {
3211 REG_WR(bp, BNX2_RV2P_COMMAND, BNX2_RV2P_COMMAND_PROC2_RESET);
3212 }
3213}
3214
af3ee519 3215static int
b6016b76
MC		 3216load_cpu_fw(struct bnx2 *bp, struct cpu_reg *cpu_reg, struct fw_info *fw)
3217{
3218 u32 offset;
3219 u32 val;
af3ee519 3220 int rc;
b6016b76
MC		 3221
3222 /* Halt the CPU. */
2726d6e1 3223 val = bnx2_reg_rd_ind(bp, cpu_reg->mode);
b6016b76 3224 val |= cpu_reg->mode_value_halt;
2726d6e1
MC		 3225 bnx2_reg_wr_ind(bp, cpu_reg->mode, val);
3226 bnx2_reg_wr_ind(bp, cpu_reg->state, cpu_reg->state_value_clear);
b6016b76
MC		 3227
3228 /* Load the Text area. */
3229 offset = cpu_reg->spad_base + (fw->text_addr - cpu_reg->mips_view_base);
af3ee519 3230 if (fw->gz_text) {
b6016b76
MC		 3231 int j;
3232
ea1f8d5c
MC		 3233 rc = zlib_inflate_blob(fw->text, FW_BUF_SIZE, fw->gz_text,
3234 fw->gz_text_len);
3235 if (rc < 0)
b3448b0b 3236 return rc;
ea1f8d5c 3237
b6016b76 3238 for (j = 0; j < (fw->text_len / 4); j++, offset += 4) {
2726d6e1 3239 bnx2_reg_wr_ind(bp, offset, le32_to_cpu(fw->text[j]));
b6016b76
MC		 3240 }
3241 }
3242
3243 /* Load the Data area. */
3244 offset = cpu_reg->spad_base + (fw->data_addr - cpu_reg->mips_view_base);
3245 if (fw->data) {
3246 int j;
3247
3248 for (j = 0; j < (fw->data_len / 4); j++, offset += 4) {
2726d6e1 3249 bnx2_reg_wr_ind(bp, offset, fw->data[j]);
b6016b76
MC		 3250 }
3251 }
3252
3253 /* Load the SBSS area. */
3254 offset = cpu_reg->spad_base + (fw->sbss_addr - cpu_reg->mips_view_base);
ea1f8d5c 3255 if (fw->sbss_len) {
b6016b76
MC		 3256 int j;
3257
3258 for (j = 0; j < (fw->sbss_len / 4); j++, offset += 4) {
2726d6e1 3259 bnx2_reg_wr_ind(bp, offset, 0);
b6016b76
MC		 3260 }
3261 }
3262
3263 /* Load the BSS area. */
3264 offset = cpu_reg->spad_base + (fw->bss_addr - cpu_reg->mips_view_base);
ea1f8d5c 3265 if (fw->bss_len) {
b6016b76
MC		 3266 int j;
3267
3268 for (j = 0; j < (fw->bss_len/4); j++, offset += 4) {
2726d6e1 3269 bnx2_reg_wr_ind(bp, offset, 0);
b6016b76
MC		 3270 }
3271 }
3272
3273 /* Load the Read-Only area. */
3274 offset = cpu_reg->spad_base +
3275 (fw->rodata_addr - cpu_reg->mips_view_base);
3276 if (fw->rodata) {
3277 int j;
3278
3279 for (j = 0; j < (fw->rodata_len / 4); j++, offset += 4) {
2726d6e1 3280 bnx2_reg_wr_ind(bp, offset, fw->rodata[j]);
b6016b76
MC		 3281 }
3282 }
3283
3284 /* Clear the pre-fetch instruction. */
2726d6e1
MC		 3285 bnx2_reg_wr_ind(bp, cpu_reg->inst, 0);
3286 bnx2_reg_wr_ind(bp, cpu_reg->pc, fw->start_addr);
b6016b76
MC		 3287
3288 /* Start the CPU. */
2726d6e1 3289 val = bnx2_reg_rd_ind(bp, cpu_reg->mode);
b6016b76 3290 val &= ~cpu_reg->mode_value_halt;
2726d6e1
MC		 3291 bnx2_reg_wr_ind(bp, cpu_reg->state, cpu_reg->state_value_clear);
3292 bnx2_reg_wr_ind(bp, cpu_reg->mode, val);
af3ee519
MC		 3293
3294 return 0;
b6016b76
MC		 3295}
3296
fba9fe91 3297static int
b6016b76
MC		 3298bnx2_init_cpus(struct bnx2 *bp)
3299{
3300 struct cpu_reg cpu_reg;
af3ee519 3301 struct fw_info *fw;
110d0ef9
MC		 3302 int rc, rv2p_len;
3303 void *text, *rv2p;
b6016b76
MC		 3304
3305 /* Initialize the RV2P processor. */
b3448b0b
DV		 3306 text = vmalloc(FW_BUF_SIZE);
3307 if (!text)
3308 return -ENOMEM;
110d0ef9
MC		 3309 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
3310 rv2p = bnx2_xi_rv2p_proc1;
3311 rv2p_len = sizeof(bnx2_xi_rv2p_proc1);
3312 } else {
3313 rv2p = bnx2_rv2p_proc1;
3314 rv2p_len = sizeof(bnx2_rv2p_proc1);
3315 }
3316 rc = zlib_inflate_blob(text, FW_BUF_SIZE, rv2p, rv2p_len);
ea1f8d5c 3317 if (rc < 0)
fba9fe91 3318 goto init_cpu_err;
ea1f8d5c 3319
b3448b0b 3320 load_rv2p_fw(bp, text, rc /* == len */, RV2P_PROC1);
fba9fe91 3321
110d0ef9
MC		 3322 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
3323 rv2p = bnx2_xi_rv2p_proc2;
3324 rv2p_len = sizeof(bnx2_xi_rv2p_proc2);
3325 } else {
3326 rv2p = bnx2_rv2p_proc2;
3327 rv2p_len = sizeof(bnx2_rv2p_proc2);
3328 }
3329 rc = zlib_inflate_blob(text, FW_BUF_SIZE, rv2p, rv2p_len);
ea1f8d5c 3330 if (rc < 0)
fba9fe91 3331 goto init_cpu_err;
ea1f8d5c 3332
b3448b0b 3333 load_rv2p_fw(bp, text, rc /* == len */, RV2P_PROC2);
b6016b76
MC		 3334
3335 /* Initialize the RX Processor. */
3336 cpu_reg.mode = BNX2_RXP_CPU_MODE;
3337 cpu_reg.mode_value_halt = BNX2_RXP_CPU_MODE_SOFT_HALT;
3338 cpu_reg.mode_value_sstep = BNX2_RXP_CPU_MODE_STEP_ENA;
3339 cpu_reg.state = BNX2_RXP_CPU_STATE;
3340 cpu_reg.state_value_clear = 0xffffff;
3341 cpu_reg.gpr0 = BNX2_RXP_CPU_REG_FILE;
3342 cpu_reg.evmask = BNX2_RXP_CPU_EVENT_MASK;
3343 cpu_reg.pc = BNX2_RXP_CPU_PROGRAM_COUNTER;
3344 cpu_reg.inst = BNX2_RXP_CPU_INSTRUCTION;
3345 cpu_reg.bp = BNX2_RXP_CPU_HW_BREAKPOINT;
3346 cpu_reg.spad_base = BNX2_RXP_SCRATCH;
3347 cpu_reg.mips_view_base = 0x8000000;
6aa20a22 3348
d43584c8
MC		 3349 if (CHIP_NUM(bp) == CHIP_NUM_5709)
3350 fw = &bnx2_rxp_fw_09;
3351 else
3352 fw = &bnx2_rxp_fw_06;
fba9fe91 3353
ea1f8d5c 3354 fw->text = text;
af3ee519 3355 rc = load_cpu_fw(bp, &cpu_reg, fw);
fba9fe91
MC		 3356 if (rc)
3357 goto init_cpu_err;
3358
b6016b76
MC		 3359 /* Initialize the TX Processor. */
3360 cpu_reg.mode = BNX2_TXP_CPU_MODE;
3361 cpu_reg.mode_value_halt = BNX2_TXP_CPU_MODE_SOFT_HALT;
3362 cpu_reg.mode_value_sstep = BNX2_TXP_CPU_MODE_STEP_ENA;
3363 cpu_reg.state = BNX2_TXP_CPU_STATE;
3364 cpu_reg.state_value_clear = 0xffffff;
3365 cpu_reg.gpr0 = BNX2_TXP_CPU_REG_FILE;
3366 cpu_reg.evmask = BNX2_TXP_CPU_EVENT_MASK;
3367 cpu_reg.pc = BNX2_TXP_CPU_PROGRAM_COUNTER;
3368 cpu_reg.inst = BNX2_TXP_CPU_INSTRUCTION;
3369 cpu_reg.bp = BNX2_TXP_CPU_HW_BREAKPOINT;
3370 cpu_reg.spad_base = BNX2_TXP_SCRATCH;
3371 cpu_reg.mips_view_base = 0x8000000;
6aa20a22 3372
d43584c8
MC		 3373 if (CHIP_NUM(bp) == CHIP_NUM_5709)
3374 fw = &bnx2_txp_fw_09;
3375 else
3376 fw = &bnx2_txp_fw_06;
fba9fe91 3377
ea1f8d5c 3378 fw->text = text;
af3ee519 3379 rc = load_cpu_fw(bp, &cpu_reg, fw);
fba9fe91
MC		 3380 if (rc)
3381 goto init_cpu_err;
3382
b6016b76
MC		 3383 /* Initialize the TX Patch-up Processor. */
3384 cpu_reg.mode = BNX2_TPAT_CPU_MODE;
3385 cpu_reg.mode_value_halt = BNX2_TPAT_CPU_MODE_SOFT_HALT;
3386 cpu_reg.mode_value_sstep = BNX2_TPAT_CPU_MODE_STEP_ENA;
3387 cpu_reg.state = BNX2_TPAT_CPU_STATE;
3388 cpu_reg.state_value_clear = 0xffffff;
3389 cpu_reg.gpr0 = BNX2_TPAT_CPU_REG_FILE;
3390 cpu_reg.evmask = BNX2_TPAT_CPU_EVENT_MASK;
3391 cpu_reg.pc = BNX2_TPAT_CPU_PROGRAM_COUNTER;
3392 cpu_reg.inst = BNX2_TPAT_CPU_INSTRUCTION;
3393 cpu_reg.bp = BNX2_TPAT_CPU_HW_BREAKPOINT;
3394 cpu_reg.spad_base = BNX2_TPAT_SCRATCH;
3395 cpu_reg.mips_view_base = 0x8000000;
6aa20a22 3396
d43584c8
MC		 3397 if (CHIP_NUM(bp) == CHIP_NUM_5709)
3398 fw = &bnx2_tpat_fw_09;
3399 else
3400 fw = &bnx2_tpat_fw_06;
fba9fe91 3401
ea1f8d5c 3402 fw->text = text;
af3ee519 3403 rc = load_cpu_fw(bp, &cpu_reg, fw);
fba9fe91
MC		 3404 if (rc)
3405 goto init_cpu_err;
3406
b6016b76
MC		 3407 /* Initialize the Completion Processor. */
3408 cpu_reg.mode = BNX2_COM_CPU_MODE;
3409 cpu_reg.mode_value_halt = BNX2_COM_CPU_MODE_SOFT_HALT;
3410 cpu_reg.mode_value_sstep = BNX2_COM_CPU_MODE_STEP_ENA;
3411 cpu_reg.state = BNX2_COM_CPU_STATE;
3412 cpu_reg.state_value_clear = 0xffffff;
3413 cpu_reg.gpr0 = BNX2_COM_CPU_REG_FILE;
3414 cpu_reg.evmask = BNX2_COM_CPU_EVENT_MASK;
3415 cpu_reg.pc = BNX2_COM_CPU_PROGRAM_COUNTER;
3416 cpu_reg.inst = BNX2_COM_CPU_INSTRUCTION;
3417 cpu_reg.bp = BNX2_COM_CPU_HW_BREAKPOINT;
3418 cpu_reg.spad_base = BNX2_COM_SCRATCH;
3419 cpu_reg.mips_view_base = 0x8000000;
6aa20a22 3420
d43584c8
MC		 3421 if (CHIP_NUM(bp) == CHIP_NUM_5709)
3422 fw = &bnx2_com_fw_09;
3423 else
3424 fw = &bnx2_com_fw_06;
fba9fe91 3425
ea1f8d5c 3426 fw->text = text;
af3ee519 3427 rc = load_cpu_fw(bp, &cpu_reg, fw);
fba9fe91
MC		 3428 if (rc)
3429 goto init_cpu_err;
3430
d43584c8
MC		 3431 /* Initialize the Command Processor. */
3432 cpu_reg.mode = BNX2_CP_CPU_MODE;
3433 cpu_reg.mode_value_halt = BNX2_CP_CPU_MODE_SOFT_HALT;
3434 cpu_reg.mode_value_sstep = BNX2_CP_CPU_MODE_STEP_ENA;
3435 cpu_reg.state = BNX2_CP_CPU_STATE;
3436 cpu_reg.state_value_clear = 0xffffff;
3437 cpu_reg.gpr0 = BNX2_CP_CPU_REG_FILE;
3438 cpu_reg.evmask = BNX2_CP_CPU_EVENT_MASK;
3439 cpu_reg.pc = BNX2_CP_CPU_PROGRAM_COUNTER;
3440 cpu_reg.inst = BNX2_CP_CPU_INSTRUCTION;
3441 cpu_reg.bp = BNX2_CP_CPU_HW_BREAKPOINT;
3442 cpu_reg.spad_base = BNX2_CP_SCRATCH;
3443 cpu_reg.mips_view_base = 0x8000000;
b6016b76 3444
110d0ef9 3445 if (CHIP_NUM(bp) == CHIP_NUM_5709)
d43584c8 3446 fw = &bnx2_cp_fw_09;
110d0ef9
MC		 3447 else
3448 fw = &bnx2_cp_fw_06;
3449
3450 fw->text = text;
3451 rc = load_cpu_fw(bp, &cpu_reg, fw);
b6016b76 3452
fba9fe91 3453init_cpu_err:
ea1f8d5c 3454 vfree(text);
fba9fe91 3455 return rc;
b6016b76
MC		 3456}
3457
3458static int
829ca9a3 3459bnx2_set_power_state(struct bnx2 *bp, pci_power_t state)
b6016b76
MC		 3460{
3461 u16 pmcsr;
3462
3463 pci_read_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL, &pmcsr);
3464
3465 switch (state) {
829ca9a3 3466 case PCI_D0: {
b6016b76
MC		 3467 u32 val;
3468
3469 pci_write_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL,
3470 (pmcsr & ~PCI_PM_CTRL_STATE_MASK) |
3471 PCI_PM_CTRL_PME_STATUS);
3472
3473 if (pmcsr & PCI_PM_CTRL_STATE_MASK)
3474 /* delay required during transition out of D3hot */
3475 msleep(20);
3476
3477 val = REG_RD(bp, BNX2_EMAC_MODE);
3478 val |= BNX2_EMAC_MODE_MPKT_RCVD | BNX2_EMAC_MODE_ACPI_RCVD;
3479 val &= ~BNX2_EMAC_MODE_MPKT;
3480 REG_WR(bp, BNX2_EMAC_MODE, val);
3481
3482 val = REG_RD(bp, BNX2_RPM_CONFIG);
3483 val &= ~BNX2_RPM_CONFIG_ACPI_ENA;
3484 REG_WR(bp, BNX2_RPM_CONFIG, val);
3485 break;
3486 }
829ca9a3 3487 case PCI_D3hot: {
b6016b76
MC		 3488 int i;
3489 u32 val, wol_msg;
3490
3491 if (bp->wol) {
3492 u32 advertising;
3493 u8 autoneg;
3494
3495 autoneg = bp->autoneg;
3496 advertising = bp->advertising;
3497
239cd343
MC		 3498 if (bp->phy_port == PORT_TP) {
3499 bp->autoneg = AUTONEG_SPEED;
3500 bp->advertising = ADVERTISED_10baseT_Half |
3501 ADVERTISED_10baseT_Full |
3502 ADVERTISED_100baseT_Half |
3503 ADVERTISED_100baseT_Full |
3504 ADVERTISED_Autoneg;
3505 }
b6016b76 3506
239cd343
MC		 3507 spin_lock_bh(&bp->phy_lock);
3508 bnx2_setup_phy(bp, bp->phy_port);
3509 spin_unlock_bh(&bp->phy_lock);
b6016b76
MC		 3510
3511 bp->autoneg = autoneg;
3512 bp->advertising = advertising;
3513
3514 bnx2_set_mac_addr(bp);
3515
3516 val = REG_RD(bp, BNX2_EMAC_MODE);
3517
3518 /* Enable port mode. */
3519 val &= ~BNX2_EMAC_MODE_PORT;
239cd343 3520 val |= BNX2_EMAC_MODE_MPKT_RCVD |
b6016b76 3521 BNX2_EMAC_MODE_ACPI_RCVD |
b6016b76 3522 BNX2_EMAC_MODE_MPKT;
239cd343
MC		 3523 if (bp->phy_port == PORT_TP)
3524 val |= BNX2_EMAC_MODE_PORT_MII;
3525 else {
3526 val |= BNX2_EMAC_MODE_PORT_GMII;
3527 if (bp->line_speed == SPEED_2500)
3528 val |= BNX2_EMAC_MODE_25G_MODE;
3529 }
b6016b76
MC		 3530
3531 REG_WR(bp, BNX2_EMAC_MODE, val);
3532
3533 /* receive all multicast */
3534 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
3535 REG_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),
3536 0xffffffff);
3537 }
3538 REG_WR(bp, BNX2_EMAC_RX_MODE,
3539 BNX2_EMAC_RX_MODE_SORT_MODE);
3540
3541 val = 1 | BNX2_RPM_SORT_USER0_BC_EN |
3542 BNX2_RPM_SORT_USER0_MC_EN;
3543 REG_WR(bp, BNX2_RPM_SORT_USER0, 0x0);
3544 REG_WR(bp, BNX2_RPM_SORT_USER0, val);
3545 REG_WR(bp, BNX2_RPM_SORT_USER0, val |
3546 BNX2_RPM_SORT_USER0_ENA);
3547
3548 /* Need to enable EMAC and RPM for WOL. */
3549 REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS,
3550 BNX2_MISC_ENABLE_SET_BITS_RX_PARSER_MAC_ENABLE |
3551 BNX2_MISC_ENABLE_SET_BITS_TX_HEADER_Q_ENABLE |
3552 BNX2_MISC_ENABLE_SET_BITS_EMAC_ENABLE);
3553
3554 val = REG_RD(bp, BNX2_RPM_CONFIG);
3555 val &= ~BNX2_RPM_CONFIG_ACPI_ENA;
3556 REG_WR(bp, BNX2_RPM_CONFIG, val);
3557
3558 wol_msg = BNX2_DRV_MSG_CODE_SUSPEND_WOL;
3559 }
3560 else {
3561 wol_msg = BNX2_DRV_MSG_CODE_SUSPEND_NO_WOL;
3562 }
3563
f86e82fb 3564 if (!(bp->flags & BNX2_FLAG_NO_WOL))
dda1e390 3565 bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT3 | wol_msg, 0);
b6016b76
MC		 3566
3567 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
3568 if ((CHIP_ID(bp) == CHIP_ID_5706_A0) ||
3569 (CHIP_ID(bp) == CHIP_ID_5706_A1)) {
3570
3571 if (bp->wol)
3572 pmcsr |= 3;
3573 }
3574 else {
3575 pmcsr |= 3;
3576 }
3577 if (bp->wol) {
3578 pmcsr |= PCI_PM_CTRL_PME_ENABLE;
3579 }
3580 pci_write_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL,
3581 pmcsr);
3582
3583 /* No more memory access after this point until
3584 * device is brought back to D0.
3585 */
3586 udelay(50);
3587 break;
3588 }
3589 default:
3590 return -EINVAL;
3591 }
3592 return 0;
3593}
3594
3595static int
3596bnx2_acquire_nvram_lock(struct bnx2 *bp)
3597{
3598 u32 val;
3599 int j;
3600
3601 /* Request access to the flash interface. */
3602 REG_WR(bp, BNX2_NVM_SW_ARB, BNX2_NVM_SW_ARB_ARB_REQ_SET2);
3603 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
3604 val = REG_RD(bp, BNX2_NVM_SW_ARB);
3605 if (val & BNX2_NVM_SW_ARB_ARB_ARB2)
3606 break;
3607
3608 udelay(5);
3609 }
3610
3611 if (j >= NVRAM_TIMEOUT_COUNT)
3612 return -EBUSY;
3613
3614 return 0;
3615}
3616
3617static int
3618bnx2_release_nvram_lock(struct bnx2 *bp)
3619{
3620 int j;
3621 u32 val;
3622
3623 /* Relinquish nvram interface. */
3624 REG_WR(bp, BNX2_NVM_SW_ARB, BNX2_NVM_SW_ARB_ARB_REQ_CLR2);
3625
3626 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
3627 val = REG_RD(bp, BNX2_NVM_SW_ARB);
3628 if (!(val & BNX2_NVM_SW_ARB_ARB_ARB2))
3629 break;
3630
3631 udelay(5);
3632 }
3633
3634 if (j >= NVRAM_TIMEOUT_COUNT)
3635 return -EBUSY;
3636
3637 return 0;
3638}
3639
3640
3641static int
3642bnx2_enable_nvram_write(struct bnx2 *bp)
3643{
3644 u32 val;
3645
3646 val = REG_RD(bp, BNX2_MISC_CFG);
3647 REG_WR(bp, BNX2_MISC_CFG, val | BNX2_MISC_CFG_NVM_WR_EN_PCI);
3648
e30372c9 3649 if (bp->flash_info->flags & BNX2_NV_WREN) {
b6016b76
MC		 3650 int j;
3651
3652 REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
3653 REG_WR(bp, BNX2_NVM_COMMAND,
3654 BNX2_NVM_COMMAND_WREN | BNX2_NVM_COMMAND_DOIT);
3655
3656 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
3657 udelay(5);
3658
3659 val = REG_RD(bp, BNX2_NVM_COMMAND);
3660 if (val & BNX2_NVM_COMMAND_DONE)
3661 break;
3662 }
3663
3664 if (j >= NVRAM_TIMEOUT_COUNT)
3665 return -EBUSY;
3666 }
3667 return 0;
3668}
3669
3670static void
3671bnx2_disable_nvram_write(struct bnx2 *bp)
3672{
3673 u32 val;
3674
3675 val = REG_RD(bp, BNX2_MISC_CFG);
3676 REG_WR(bp, BNX2_MISC_CFG, val & ~BNX2_MISC_CFG_NVM_WR_EN);
3677}
3678
3679
3680static void
3681bnx2_enable_nvram_access(struct bnx2 *bp)
3682{
3683 u32 val;
3684
3685 val = REG_RD(bp, BNX2_NVM_ACCESS_ENABLE);
3686 /* Enable both bits, even on read. */
6aa20a22 3687 REG_WR(bp, BNX2_NVM_ACCESS_ENABLE,
b6016b76
MC		 3688 val | BNX2_NVM_ACCESS_ENABLE_EN | BNX2_NVM_ACCESS_ENABLE_WR_EN);
3689}
3690
3691static void
3692bnx2_disable_nvram_access(struct bnx2 *bp)
3693{
3694 u32 val;
3695
3696 val = REG_RD(bp, BNX2_NVM_ACCESS_ENABLE);
3697 /* Disable both bits, even after read. */
6aa20a22 3698 REG_WR(bp, BNX2_NVM_ACCESS_ENABLE,
b6016b76
MC		 3699 val & ~(BNX2_NVM_ACCESS_ENABLE_EN |
3700 BNX2_NVM_ACCESS_ENABLE_WR_EN));
3701}
3702
3703static int
3704bnx2_nvram_erase_page(struct bnx2 *bp, u32 offset)
3705{
3706 u32 cmd;
3707 int j;
3708
e30372c9 3709 if (bp->flash_info->flags & BNX2_NV_BUFFERED)
b6016b76
MC		 3710 /* Buffered flash, no erase needed */
3711 return 0;
3712
3713 /* Build an erase command */
3714 cmd = BNX2_NVM_COMMAND_ERASE | BNX2_NVM_COMMAND_WR |
3715 BNX2_NVM_COMMAND_DOIT;
3716
3717 /* Need to clear DONE bit separately. */
3718 REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
3719
3720 /* Address of the NVRAM to read from. */
3721 REG_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);
3722
3723 /* Issue an erase command. */
3724 REG_WR(bp, BNX2_NVM_COMMAND, cmd);
3725
3726 /* Wait for completion. */
3727 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
3728 u32 val;
3729
3730 udelay(5);
3731
3732 val = REG_RD(bp, BNX2_NVM_COMMAND);
3733 if (val & BNX2_NVM_COMMAND_DONE)
3734 break;
3735 }
3736
3737 if (j >= NVRAM_TIMEOUT_COUNT)
3738 return -EBUSY;
3739
3740 return 0;
3741}
3742
3743static int
3744bnx2_nvram_read_dword(struct bnx2 *bp, u32 offset, u8 *ret_val, u32 cmd_flags)
3745{
3746 u32 cmd;
3747 int j;
3748
3749 /* Build the command word. */
3750 cmd = BNX2_NVM_COMMAND_DOIT | cmd_flags;
3751
e30372c9
MC		 3752 /* Calculate an offset of a buffered flash, not needed for 5709. */
3753 if (bp->flash_info->flags & BNX2_NV_TRANSLATE) {
b6016b76
MC		 3754 offset = ((offset / bp->flash_info->page_size) <<
3755 bp->flash_info->page_bits) +
3756 (offset % bp->flash_info->page_size);
3757 }
3758
3759 /* Need to clear DONE bit separately. */
3760 REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
3761
3762 /* Address of the NVRAM to read from. */
3763 REG_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);
3764
3765 /* Issue a read command. */
3766 REG_WR(bp, BNX2_NVM_COMMAND, cmd);
3767
3768 /* Wait for completion. */
3769 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
3770 u32 val;
3771
3772 udelay(5);
3773
3774 val = REG_RD(bp, BNX2_NVM_COMMAND);
3775 if (val & BNX2_NVM_COMMAND_DONE) {
b491edd5
AV		 3776 __be32 v = cpu_to_be32(REG_RD(bp, BNX2_NVM_READ));
3777 memcpy(ret_val, &v, 4);
b6016b76
MC		 3778 break;
3779 }
3780 }
3781 if (j >= NVRAM_TIMEOUT_COUNT)
3782 return -EBUSY;
3783
3784 return 0;
3785}
3786
3787
3788static int
3789bnx2_nvram_write_dword(struct bnx2 *bp, u32 offset, u8 *val, u32 cmd_flags)
3790{
b491edd5
AV		 3791 u32 cmd;
3792 __be32 val32;
b6016b76
MC		 3793 int j;
3794
3795 /* Build the command word. */
3796 cmd = BNX2_NVM_COMMAND_DOIT | BNX2_NVM_COMMAND_WR | cmd_flags;
3797
e30372c9
MC		 3798 /* Calculate an offset of a buffered flash, not needed for 5709. */
3799 if (bp->flash_info->flags & BNX2_NV_TRANSLATE) {
b6016b76
MC		 3800 offset = ((offset / bp->flash_info->page_size) <<
3801 bp->flash_info->page_bits) +
3802 (offset % bp->flash_info->page_size);
3803 }
3804
3805 /* Need to clear DONE bit separately. */
3806 REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
3807
3808 memcpy(&val32, val, 4);
b6016b76
MC		 3809
3810 /* Write the data. */
b491edd5 3811 REG_WR(bp, BNX2_NVM_WRITE, be32_to_cpu(val32));
b6016b76
MC		 3812
3813 /* Address of the NVRAM to write to. */
3814 REG_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);
3815
3816 /* Issue the write command. */
3817 REG_WR(bp, BNX2_NVM_COMMAND, cmd);
3818
3819 /* Wait for completion. */
3820 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
3821 udelay(5);
3822
3823 if (REG_RD(bp, BNX2_NVM_COMMAND) & BNX2_NVM_COMMAND_DONE)
3824 break;
3825 }
3826 if (j >= NVRAM_TIMEOUT_COUNT)
3827 return -EBUSY;
3828
3829 return 0;
3830}
3831
3832static int
3833bnx2_init_nvram(struct bnx2 *bp)
3834{
3835 u32 val;
e30372c9 3836 int j, entry_count, rc = 0;
b6016b76
MC		 3837 struct flash_spec *flash;
3838
e30372c9
MC		 3839 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
3840 bp->flash_info = &flash_5709;
3841 goto get_flash_size;
3842 }
3843
b6016b76
MC		 3844 /* Determine the selected interface. */
3845 val = REG_RD(bp, BNX2_NVM_CFG1);
3846
ff8ac609 3847 entry_count = ARRAY_SIZE(flash_table);
b6016b76 3848
b6016b76
MC		 3849 if (val & 0x40000000) {
3850
3851 /* Flash interface has been reconfigured */
3852 for (j = 0, flash = &flash_table[0]; j < entry_count;
37137709
MC		 3853 j++, flash++) {
3854 if ((val & FLASH_BACKUP_STRAP_MASK) ==
3855 (flash->config1 & FLASH_BACKUP_STRAP_MASK)) {
b6016b76
MC		 3856 bp->flash_info = flash;
3857 break;
3858 }
3859 }
3860 }
3861 else {
37137709 3862 u32 mask;
b6016b76
MC		 3863 /* Not yet been reconfigured */
3864
37137709
MC		 3865 if (val & (1 << 23))
3866 mask = FLASH_BACKUP_STRAP_MASK;
3867 else
3868 mask = FLASH_STRAP_MASK;
3869
b6016b76
MC		 3870 for (j = 0, flash = &flash_table[0]; j < entry_count;
3871 j++, flash++) {
3872
37137709 3873 if ((val & mask) == (flash->strapping & mask)) {
b6016b76
MC		 3874 bp->flash_info = flash;
3875
3876 /* Request access to the flash interface. */
3877 if ((rc = bnx2_acquire_nvram_lock(bp)) != 0)
3878 return rc;
3879
3880 /* Enable access to flash interface */
3881 bnx2_enable_nvram_access(bp);
3882
3883 /* Reconfigure the flash interface */
3884 REG_WR(bp, BNX2_NVM_CFG1, flash->config1);
3885 REG_WR(bp, BNX2_NVM_CFG2, flash->config2);
3886 REG_WR(bp, BNX2_NVM_CFG3, flash->config3);
3887 REG_WR(bp, BNX2_NVM_WRITE1, flash->write1);
3888
3889 /* Disable access to flash interface */
3890 bnx2_disable_nvram_access(bp);
3891 bnx2_release_nvram_lock(bp);
3892
3893 break;
3894 }
3895 }
3896 } /* if (val & 0x40000000) */
3897
3898 if (j == entry_count) {
3899 bp->flash_info = NULL;
2f23c523 3900 printk(KERN_ALERT PFX "Unknown flash/EEPROM type.\n");
1122db71 3901 return -ENODEV;
b6016b76
MC		 3902 }
3903
e30372c9 3904get_flash_size:
2726d6e1 3905 val = bnx2_shmem_rd(bp, BNX2_SHARED_HW_CFG_CONFIG2);
1122db71
MC		 3906 val &= BNX2_SHARED_HW_CFG2_NVM_SIZE_MASK;
3907 if (val)
3908 bp->flash_size = val;
3909 else
3910 bp->flash_size = bp->flash_info->total_size;
3911
b6016b76
MC		 3912 return rc;
3913}
3914
3915static int
3916bnx2_nvram_read(struct bnx2 *bp, u32 offset, u8 *ret_buf,
3917 int buf_size)
3918{
3919 int rc = 0;
3920 u32 cmd_flags, offset32, len32, extra;
3921
3922 if (buf_size == 0)
3923 return 0;
3924
3925 /* Request access to the flash interface. */
3926 if ((rc = bnx2_acquire_nvram_lock(bp)) != 0)
3927 return rc;
3928
3929 /* Enable access to flash interface */
3930 bnx2_enable_nvram_access(bp);
3931
3932 len32 = buf_size;
3933 offset32 = offset;
3934 extra = 0;
3935
3936 cmd_flags = 0;
3937
3938 if (offset32 & 3) {
3939 u8 buf[4];
3940 u32 pre_len;
3941
3942 offset32 &= ~3;
3943 pre_len = 4 - (offset & 3);
3944
3945 if (pre_len >= len32) {
3946 pre_len = len32;
3947 cmd_flags = BNX2_NVM_COMMAND_FIRST |
3948 BNX2_NVM_COMMAND_LAST;
3949 }
3950 else {
3951 cmd_flags = BNX2_NVM_COMMAND_FIRST;
3952 }
3953
3954 rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags);
3955
3956 if (rc)
3957 return rc;
3958
3959 memcpy(ret_buf, buf + (offset & 3), pre_len);
3960
3961 offset32 += 4;
3962 ret_buf += pre_len;
3963 len32 -= pre_len;
3964 }
3965 if (len32 & 3) {
3966 extra = 4 - (len32 & 3);
3967 len32 = (len32 + 4) & ~3;
3968 }
3969
3970 if (len32 == 4) {
3971 u8 buf[4];
3972
3973 if (cmd_flags)
3974 cmd_flags = BNX2_NVM_COMMAND_LAST;
3975 else
3976 cmd_flags = BNX2_NVM_COMMAND_FIRST |
3977 BNX2_NVM_COMMAND_LAST;
3978
3979 rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags);
3980
3981 memcpy(ret_buf, buf, 4 - extra);
3982 }
3983 else if (len32 > 0) {
3984 u8 buf[4];
3985
3986 /* Read the first word. */
3987 if (cmd_flags)
3988 cmd_flags = 0;
3989 else
3990 cmd_flags = BNX2_NVM_COMMAND_FIRST;
3991
3992 rc = bnx2_nvram_read_dword(bp, offset32, ret_buf, cmd_flags);
3993
3994 /* Advance to the next dword. */
3995 offset32 += 4;
3996 ret_buf += 4;
3997 len32 -= 4;
3998
3999 while (len32 > 4 && rc == 0) {
4000 rc = bnx2_nvram_read_dword(bp, offset32, ret_buf, 0);
4001
4002 /* Advance to the next dword. */
4003 offset32 += 4;
4004 ret_buf += 4;
4005 len32 -= 4;
4006 }
4007
4008 if (rc)
4009 return rc;
4010
4011 cmd_flags = BNX2_NVM_COMMAND_LAST;
4012 rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags);
4013
4014 memcpy(ret_buf, buf, 4 - extra);
4015 }
4016
4017 /* Disable access to flash interface */
4018 bnx2_disable_nvram_access(bp);
4019
4020 bnx2_release_nvram_lock(bp);
4021
4022 return rc;
4023}
4024
4025static int
4026bnx2_nvram_write(struct bnx2 *bp, u32 offset, u8 *data_buf,
4027 int buf_size)
4028{
4029 u32 written, offset32, len32;
e6be763f 4030 u8 *buf, start[4], end[4], *align_buf = NULL, *flash_buffer = NULL;
b6016b76
MC		 4031 int rc = 0;
4032 int align_start, align_end;
4033
4034 buf = data_buf;
4035 offset32 = offset;
4036 len32 = buf_size;
4037 align_start = align_end = 0;
4038
4039 if ((align_start = (offset32 & 3))) {
4040 offset32 &= ~3;
c873879c
MC		 4041 len32 += align_start;
4042 if (len32 < 4)
4043 len32 = 4;
b6016b76
MC		 4044 if ((rc = bnx2_nvram_read(bp, offset32, start, 4)))
4045 return rc;
4046 }
4047
4048 if (len32 & 3) {
c873879c
MC		 4049 align_end = 4 - (len32 & 3);
4050 len32 += align_end;
4051 if ((rc = bnx2_nvram_read(bp, offset32 + len32 - 4, end, 4)))
4052 return rc;
b6016b76
MC		 4053 }
4054
4055 if (align_start || align_end) {
e6be763f
MC		 4056 align_buf = kmalloc(len32, GFP_KERNEL);
4057 if (align_buf == NULL)
b6016b76
MC		 4058 return -ENOMEM;
4059 if (align_start) {
e6be763f 4060 memcpy(align_buf, start, 4);
b6016b76
MC		 4061 }
4062 if (align_end) {
e6be763f 4063 memcpy(align_buf + len32 - 4, end, 4);
b6016b76 4064 }
e6be763f
MC		 4065 memcpy(align_buf + align_start, data_buf, buf_size);
4066 buf = align_buf;
b6016b76
MC		 4067 }
4068
e30372c9 4069 if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) {
ae181bc4
MC		 4070 flash_buffer = kmalloc(264, GFP_KERNEL);
4071 if (flash_buffer == NULL) {
4072 rc = -ENOMEM;
4073 goto nvram_write_end;
4074 }
4075 }
4076
b6016b76
MC		 4077 written = 0;
4078 while ((written < len32) && (rc == 0)) {
4079 u32 page_start, page_end, data_start, data_end;
4080 u32 addr, cmd_flags;
4081 int i;
b6016b76
MC		 4082
4083 /* Find the page_start addr */
4084 page_start = offset32 + written;
4085 page_start -= (page_start % bp->flash_info->page_size);
4086 /* Find the page_end addr */
4087 page_end = page_start + bp->flash_info->page_size;
4088 /* Find the data_start addr */
4089 data_start = (written == 0) ? offset32 : page_start;
4090 /* Find the data_end addr */
6aa20a22 4091 data_end = (page_end > offset32 + len32) ?
b6016b76
MC		 4092 (offset32 + len32) : page_end;
4093
4094 /* Request access to the flash interface. */
4095 if ((rc = bnx2_acquire_nvram_lock(bp)) != 0)
4096 goto nvram_write_end;
4097
4098 /* Enable access to flash interface */
4099 bnx2_enable_nvram_access(bp);
4100
4101 cmd_flags = BNX2_NVM_COMMAND_FIRST;
e30372c9 4102 if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) {
b6016b76
MC		 4103 int j;
4104
4105 /* Read the whole page into the buffer
4106 * (non-buffer flash only) */
4107 for (j = 0; j < bp->flash_info->page_size; j += 4) {
4108 if (j == (bp->flash_info->page_size - 4)) {
4109 cmd_flags |= BNX2_NVM_COMMAND_LAST;
4110 }
4111 rc = bnx2_nvram_read_dword(bp,
6aa20a22
JG		 4112 page_start + j,
4113 &flash_buffer[j],
b6016b76
MC		 4114 cmd_flags);
4115
4116 if (rc)
4117 goto nvram_write_end;
4118
4119 cmd_flags = 0;
4120 }
4121 }
4122
4123 /* Enable writes to flash interface (unlock write-protect) */
4124 if ((rc = bnx2_enable_nvram_write(bp)) != 0)
4125 goto nvram_write_end;
4126
b6016b76
MC		 4127 /* Loop to write back the buffer data from page_start to
4128 * data_start */
4129 i = 0;
e30372c9 4130 if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) {
c873879c
MC		 4131 /* Erase the page */
4132 if ((rc = bnx2_nvram_erase_page(bp, page_start)) != 0)
4133 goto nvram_write_end;
4134
4135 /* Re-enable the write again for the actual write */
4136 bnx2_enable_nvram_write(bp);
4137
b6016b76
MC		 4138 for (addr = page_start; addr < data_start;
4139 addr += 4, i += 4) {
6aa20a22 4140
b6016b76
MC		 4141 rc = bnx2_nvram_write_dword(bp, addr,
4142 &flash_buffer[i], cmd_flags);
4143
4144 if (rc != 0)
4145 goto nvram_write_end;
4146
4147 cmd_flags = 0;
4148 }
4149 }
4150
4151 /* Loop to write the new data from data_start to data_end */
bae25761 4152 for (addr = data_start; addr < data_end; addr += 4, i += 4) {
b6016b76 4153 if ((addr == page_end - 4) ||
e30372c9 4154 ((bp->flash_info->flags & BNX2_NV_BUFFERED) &&
b6016b76
MC		 4155 (addr == data_end - 4))) {
4156
4157 cmd_flags |= BNX2_NVM_COMMAND_LAST;
4158 }
4159 rc = bnx2_nvram_write_dword(bp, addr, buf,
4160 cmd_flags);
4161
4162 if (rc != 0)
4163 goto nvram_write_end;
4164
4165 cmd_flags = 0;
4166 buf += 4;
4167 }
4168
4169 /* Loop to write back the buffer data from data_end
4170 * to page_end */
e30372c9 4171 if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) {
b6016b76
MC		 4172 for (addr = data_end; addr < page_end;
4173 addr += 4, i += 4) {
6aa20a22 4174
b6016b76
MC		 4175 if (addr == page_end-4) {
4176 cmd_flags = BNX2_NVM_COMMAND_LAST;
4177 }
4178 rc = bnx2_nvram_write_dword(bp, addr,
4179 &flash_buffer[i], cmd_flags);
4180
4181 if (rc != 0)
4182 goto nvram_write_end;
4183
4184 cmd_flags = 0;
4185 }
4186 }
4187
4188 /* Disable writes to flash interface (lock write-protect) */
4189 bnx2_disable_nvram_write(bp);
4190
4191 /* Disable access to flash interface */
4192 bnx2_disable_nvram_access(bp);
4193 bnx2_release_nvram_lock(bp);
4194
4195 /* Increment written */
4196 written += data_end - data_start;
4197 }
4198
4199nvram_write_end:
e6be763f
MC		 4200 kfree(flash_buffer);
4201 kfree(align_buf);
b6016b76
MC		 4202 return rc;
4203}
4204
0d8a6571
MC		 4205static void
4206bnx2_init_remote_phy(struct bnx2 *bp)
4207{
4208 u32 val;
4209
583c28e5
MC		 4210 bp->phy_flags &= ~BNX2_PHY_FLAG_REMOTE_PHY_CAP;
4211 if (!(bp->phy_flags & BNX2_PHY_FLAG_SERDES))
0d8a6571
MC		 4212 return;
4213
2726d6e1 4214 val = bnx2_shmem_rd(bp, BNX2_FW_CAP_MB);
0d8a6571
MC		 4215 if ((val & BNX2_FW_CAP_SIGNATURE_MASK) != BNX2_FW_CAP_SIGNATURE)
4216 return;
4217
4218 if (val & BNX2_FW_CAP_REMOTE_PHY_CAPABLE) {
583c28e5 4219 bp->phy_flags |= BNX2_PHY_FLAG_REMOTE_PHY_CAP;
0d8a6571 4220
2726d6e1 4221 val = bnx2_shmem_rd(bp, BNX2_LINK_STATUS);
0d8a6571
MC		 4222 if (val & BNX2_LINK_STATUS_SERDES_LINK)
4223 bp->phy_port = PORT_FIBRE;
4224 else
4225 bp->phy_port = PORT_TP;
489310a4
MC		 4226
4227 if (netif_running(bp->dev)) {
4228 u32 sig;
4229
489310a4
MC		 4230 sig = BNX2_DRV_ACK_CAP_SIGNATURE |
4231 BNX2_FW_CAP_REMOTE_PHY_CAPABLE;
2726d6e1 4232 bnx2_shmem_wr(bp, BNX2_DRV_ACK_CAP_MB, sig);
489310a4 4233 }
0d8a6571
MC		 4234 }
4235}
4236
b4b36042
MC		 4237static void
4238bnx2_setup_msix_tbl(struct bnx2 *bp)
4239{
4240 REG_WR(bp, BNX2_PCI_GRC_WINDOW_ADDR, BNX2_PCI_GRC_WINDOW_ADDR_SEP_WIN);
4241
4242 REG_WR(bp, BNX2_PCI_GRC_WINDOW2_ADDR, BNX2_MSIX_TABLE_ADDR);
4243 REG_WR(bp, BNX2_PCI_GRC_WINDOW3_ADDR, BNX2_MSIX_PBA_ADDR);
4244}
4245
b6016b76
MC		 4246static int
4247bnx2_reset_chip(struct bnx2 *bp, u32 reset_code)
4248{
4249 u32 val;
4250 int i, rc = 0;
489310a4 4251 u8 old_port;
b6016b76
MC		 4252
4253 /* Wait for the current PCI transaction to complete before
4254 * issuing a reset. */
4255 REG_WR(bp, BNX2_MISC_ENABLE_CLR_BITS,
4256 BNX2_MISC_ENABLE_CLR_BITS_TX_DMA_ENABLE |
4257 BNX2_MISC_ENABLE_CLR_BITS_DMA_ENGINE_ENABLE |
4258 BNX2_MISC_ENABLE_CLR_BITS_RX_DMA_ENABLE |
4259 BNX2_MISC_ENABLE_CLR_BITS_HOST_COALESCE_ENABLE);
4260 val = REG_RD(bp, BNX2_MISC_ENABLE_CLR_BITS);
4261 udelay(5);
4262
b090ae2b
MC		 4263 /* Wait for the firmware to tell us it is ok to issue a reset. */
4264 bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT0 | reset_code, 1);
4265
b6016b76
MC		 4266 /* Deposit a driver reset signature so the firmware knows that
4267 * this is a soft reset. */
2726d6e1
MC		 4268 bnx2_shmem_wr(bp, BNX2_DRV_RESET_SIGNATURE,
4269 BNX2_DRV_RESET_SIGNATURE_MAGIC);
b6016b76 4270
b6016b76
MC		 4271 /* Do a dummy read to force the chip to complete all current transaction
4272 * before we issue a reset. */
4273 val = REG_RD(bp, BNX2_MISC_ID);
4274
234754d5
MC		 4275 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
4276 REG_WR(bp, BNX2_MISC_COMMAND, BNX2_MISC_COMMAND_SW_RESET);
4277 REG_RD(bp, BNX2_MISC_COMMAND);
4278 udelay(5);
b6016b76 4279
234754d5
MC		 4280 val = BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
4281 BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP;
b6016b76 4282
234754d5 4283 pci_write_config_dword(bp->pdev, BNX2_PCICFG_MISC_CONFIG, val);
b6016b76 4284
234754d5
MC		 4285 } else {
4286 val = BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |
4287 BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
4288 BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP;
4289
4290 /* Chip reset. */
4291 REG_WR(bp, BNX2_PCICFG_MISC_CONFIG, val);
4292
594a9dfa
MC		 4293 /* Reading back any register after chip reset will hang the
4294 * bus on 5706 A0 and A1. The msleep below provides plenty
4295 * of margin for write posting.
4296 */
234754d5 4297 if ((CHIP_ID(bp) == CHIP_ID_5706_A0) ||
8e545881
AV		 4298 (CHIP_ID(bp) == CHIP_ID_5706_A1))
4299 msleep(20);
b6016b76 4300
234754d5
MC		 4301 /* Reset takes approximate 30 usec */
4302 for (i = 0; i < 10; i++) {
4303 val = REG_RD(bp, BNX2_PCICFG_MISC_CONFIG);
4304 if ((val & (BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |
4305 BNX2_PCICFG_MISC_CONFIG_CORE_RST_BSY)) == 0)
4306 break;
4307 udelay(10);
4308 }
4309
4310 if (val & (BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |
4311 BNX2_PCICFG_MISC_CONFIG_CORE_RST_BSY)) {
4312 printk(KERN_ERR PFX "Chip reset did not complete\n");
4313 return -EBUSY;
4314 }
b6016b76
MC		 4315 }
4316
4317 /* Make sure byte swapping is properly configured. */
4318 val = REG_RD(bp, BNX2_PCI_SWAP_DIAG0);
4319 if (val != 0x01020304) {
4320 printk(KERN_ERR PFX "Chip not in correct endian mode\n");
4321 return -ENODEV;
4322 }
4323
b6016b76 4324 /* Wait for the firmware to finish its initialization. */
b090ae2b
MC		 4325 rc = bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT1 | reset_code, 0);
4326 if (rc)
4327 return rc;
b6016b76 4328
0d8a6571 4329 spin_lock_bh(&bp->phy_lock);
489310a4 4330 old_port = bp->phy_port;
0d8a6571 4331 bnx2_init_remote_phy(bp);
583c28e5
MC		 4332 if ((bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) &&
4333 old_port != bp->phy_port)
0d8a6571
MC		 4334 bnx2_set_default_remote_link(bp);
4335 spin_unlock_bh(&bp->phy_lock);
4336
b6016b76
MC		 4337 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
4338 /* Adjust the voltage regular to two steps lower. The default
4339 * of this register is 0x0000000e. */
4340 REG_WR(bp, BNX2_MISC_VREG_CONTROL, 0x000000fa);
4341
4342 /* Remove bad rbuf memory from the free pool. */
4343 rc = bnx2_alloc_bad_rbuf(bp);
4344 }
4345
f86e82fb 4346 if (bp->flags & BNX2_FLAG_USING_MSIX)
b4b36042
MC		 4347 bnx2_setup_msix_tbl(bp);
4348
b6016b76
MC		 4349 return rc;
4350}
4351
4352static int
4353bnx2_init_chip(struct bnx2 *bp)
4354{
4355 u32 val;
b4b36042 4356 int rc, i;
b6016b76
MC		 4357
4358 /* Make sure the interrupt is not active. */
4359 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
4360
4361 val = BNX2_DMA_CONFIG_DATA_BYTE_SWAP |
4362 BNX2_DMA_CONFIG_DATA_WORD_SWAP |
4363#ifdef __BIG_ENDIAN
6aa20a22 4364 BNX2_DMA_CONFIG_CNTL_BYTE_SWAP |
b6016b76 4365#endif
6aa20a22 4366 BNX2_DMA_CONFIG_CNTL_WORD_SWAP |
b6016b76
MC		 4367 DMA_READ_CHANS << 12 |
4368 DMA_WRITE_CHANS << 16;
4369
4370 val |= (0x2 << 20) | (1 << 11);
4371
f86e82fb 4372 if ((bp->flags & BNX2_FLAG_PCIX) && (bp->bus_speed_mhz == 133))
b6016b76
MC		 4373 val |= (1 << 23);
4374
4375 if ((CHIP_NUM(bp) == CHIP_NUM_5706) &&
f86e82fb 4376 (CHIP_ID(bp) != CHIP_ID_5706_A0) && !(bp->flags & BNX2_FLAG_PCIX))
b6016b76
MC		 4377 val |= BNX2_DMA_CONFIG_CNTL_PING_PONG_DMA;
4378
4379 REG_WR(bp, BNX2_DMA_CONFIG, val);
4380
4381 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
4382 val = REG_RD(bp, BNX2_TDMA_CONFIG);
4383 val |= BNX2_TDMA_CONFIG_ONE_DMA;
4384 REG_WR(bp, BNX2_TDMA_CONFIG, val);
4385 }
4386
f86e82fb 4387 if (bp->flags & BNX2_FLAG_PCIX) {
b6016b76
MC		 4388 u16 val16;
4389
4390 pci_read_config_word(bp->pdev, bp->pcix_cap + PCI_X_CMD,
4391 &val16);
4392 pci_write_config_word(bp->pdev, bp->pcix_cap + PCI_X_CMD,
4393 val16 & ~PCI_X_CMD_ERO);
4394 }
4395
4396 REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS,
4397 BNX2_MISC_ENABLE_SET_BITS_HOST_COALESCE_ENABLE |
4398 BNX2_MISC_ENABLE_STATUS_BITS_RX_V2P_ENABLE |
4399 BNX2_MISC_ENABLE_STATUS_BITS_CONTEXT_ENABLE);
4400
4401 /* Initialize context mapping and zero out the quick contexts. The
4402 * context block must have already been enabled. */
641bdcd5
MC		 4403 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
4404 rc = bnx2_init_5709_context(bp);
4405 if (rc)
4406 return rc;
4407 } else
59b47d8a 4408 bnx2_init_context(bp);
b6016b76 4409
fba9fe91
MC		 4410 if ((rc = bnx2_init_cpus(bp)) != 0)
4411 return rc;
4412
b6016b76
MC		 4413 bnx2_init_nvram(bp);
4414
4415 bnx2_set_mac_addr(bp);
4416
4417 val = REG_RD(bp, BNX2_MQ_CONFIG);
4418 val &= ~BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE;
4419 val |= BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE_256;
68c9f75a
MC		 4420 if (CHIP_ID(bp) == CHIP_ID_5709_A0 || CHIP_ID(bp) == CHIP_ID_5709_A1)
4421 val |= BNX2_MQ_CONFIG_HALT_DIS;
4422
b6016b76
MC		 4423 REG_WR(bp, BNX2_MQ_CONFIG, val);
4424
4425 val = 0x10000 + (MAX_CID_CNT * MB_KERNEL_CTX_SIZE);
4426 REG_WR(bp, BNX2_MQ_KNL_BYP_WIND_START, val);
4427 REG_WR(bp, BNX2_MQ_KNL_WIND_END, val);
4428
4429 val = (BCM_PAGE_BITS - 8) << 24;
4430 REG_WR(bp, BNX2_RV2P_CONFIG, val);
4431
4432 /* Configure page size. */
4433 val = REG_RD(bp, BNX2_TBDR_CONFIG);
4434 val &= ~BNX2_TBDR_CONFIG_PAGE_SIZE;
4435 val |= (BCM_PAGE_BITS - 8) << 24 | 0x40;
4436 REG_WR(bp, BNX2_TBDR_CONFIG, val);
4437
4438 val = bp->mac_addr[0] +
4439 (bp->mac_addr[1] << 8) +
4440 (bp->mac_addr[2] << 16) +
4441 bp->mac_addr[3] +
4442 (bp->mac_addr[4] << 8) +
4443 (bp->mac_addr[5] << 16);
4444 REG_WR(bp, BNX2_EMAC_BACKOFF_SEED, val);
4445
4446 /* Program the MTU. Also include 4 bytes for CRC32. */
4447 val = bp->dev->mtu + ETH_HLEN + 4;
4448 if (val > (MAX_ETHERNET_PACKET_SIZE + 4))
4449 val |= BNX2_EMAC_RX_MTU_SIZE_JUMBO_ENA;
4450 REG_WR(bp, BNX2_EMAC_RX_MTU_SIZE, val);
4451
b4b36042
MC		 4452 for (i = 0; i < BNX2_MAX_MSIX_VEC; i++)
4453 bp->bnx2_napi[i].last_status_idx = 0;
4454
b6016b76
MC		 4455 bp->rx_mode = BNX2_EMAC_RX_MODE_SORT_MODE;
4456
4457 /* Set up how to generate a link change interrupt. */
4458 REG_WR(bp, BNX2_EMAC_ATTENTION_ENA, BNX2_EMAC_ATTENTION_ENA_LINK);
4459
4460 REG_WR(bp, BNX2_HC_STATUS_ADDR_L,
4461 (u64) bp->status_blk_mapping & 0xffffffff);
4462 REG_WR(bp, BNX2_HC_STATUS_ADDR_H, (u64) bp->status_blk_mapping >> 32);
4463
4464 REG_WR(bp, BNX2_HC_STATISTICS_ADDR_L,
4465 (u64) bp->stats_blk_mapping & 0xffffffff);
4466 REG_WR(bp, BNX2_HC_STATISTICS_ADDR_H,
4467 (u64) bp->stats_blk_mapping >> 32);
4468
6aa20a22 4469 REG_WR(bp, BNX2_HC_TX_QUICK_CONS_TRIP,
b6016b76
MC		 4470 (bp->tx_quick_cons_trip_int << 16) | bp->tx_quick_cons_trip);
4471
4472 REG_WR(bp, BNX2_HC_RX_QUICK_CONS_TRIP,
4473 (bp->rx_quick_cons_trip_int << 16) | bp->rx_quick_cons_trip);
4474
4475 REG_WR(bp, BNX2_HC_COMP_PROD_TRIP,
4476 (bp->comp_prod_trip_int << 16) | bp->comp_prod_trip);
4477
4478 REG_WR(bp, BNX2_HC_TX_TICKS, (bp->tx_ticks_int << 16) | bp->tx_ticks);
4479
4480 REG_WR(bp, BNX2_HC_RX_TICKS, (bp->rx_ticks_int << 16) | bp->rx_ticks);
4481
4482 REG_WR(bp, BNX2_HC_COM_TICKS,
4483 (bp->com_ticks_int << 16) | bp->com_ticks);
4484
4485 REG_WR(bp, BNX2_HC_CMD_TICKS,
4486 (bp->cmd_ticks_int << 16) | bp->cmd_ticks);
4487
02537b06
MC		 4488 if (CHIP_NUM(bp) == CHIP_NUM_5708)
4489 REG_WR(bp, BNX2_HC_STATS_TICKS, 0);
4490 else
7ea6920e 4491 REG_WR(bp, BNX2_HC_STATS_TICKS, bp->stats_ticks);
b6016b76
MC		 4492 REG_WR(bp, BNX2_HC_STAT_COLLECT_TICKS, 0xbb8); /* 3ms */
4493
4494 if (CHIP_ID(bp) == CHIP_ID_5706_A1)
8e6a72c4 4495 val = BNX2_HC_CONFIG_COLLECT_STATS;
b6016b76 4496 else {
8e6a72c4
MC		 4497 val = BNX2_HC_CONFIG_RX_TMR_MODE | BNX2_HC_CONFIG_TX_TMR_MODE |
4498 BNX2_HC_CONFIG_COLLECT_STATS;
b6016b76
MC		 4499 }
4500
f86e82fb 4501 if (bp->flags & BNX2_FLAG_USING_MSIX) {
6f743ca0
MC		 4502 u32 base = ((BNX2_TX_VEC - 1) * BNX2_HC_SB_CONFIG_SIZE) +
4503 BNX2_HC_SB_CONFIG_1;
4504
c76c0475
MC		 4505 REG_WR(bp, BNX2_HC_MSIX_BIT_VECTOR,
4506 BNX2_HC_MSIX_BIT_VECTOR_VAL);
4507
6f743ca0 4508 REG_WR(bp, base,
c76c0475
MC		 4509 BNX2_HC_SB_CONFIG_1_TX_TMR_MODE |
4510 BNX2_HC_SB_CONFIG_1_ONE_SHOT);
4511
6f743ca0 4512 REG_WR(bp, base + BNX2_HC_TX_QUICK_CONS_TRIP_OFF,
c76c0475
MC		 4513 (bp->tx_quick_cons_trip_int << 16) |
4514 bp->tx_quick_cons_trip);
4515
6f743ca0 4516 REG_WR(bp, base + BNX2_HC_TX_TICKS_OFF,
c76c0475
MC		 4517 (bp->tx_ticks_int << 16) | bp->tx_ticks);
4518
4519 val |= BNX2_HC_CONFIG_SB_ADDR_INC_128B;
4520 }
4521
f86e82fb 4522 if (bp->flags & BNX2_FLAG_ONE_SHOT_MSI)
8e6a72c4
MC		 4523 val |= BNX2_HC_CONFIG_ONE_SHOT;
4524
4525 REG_WR(bp, BNX2_HC_CONFIG, val);
4526
b6016b76
MC		 4527 /* Clear internal stats counters. */
4528 REG_WR(bp, BNX2_HC_COMMAND, BNX2_HC_COMMAND_CLR_STAT_NOW);
4529
da3e4fbe 4530 REG_WR(bp, BNX2_HC_ATTN_BITS_ENABLE, STATUS_ATTN_EVENTS);
b6016b76
MC		 4531
4532 /* Initialize the receive filter. */
4533 bnx2_set_rx_mode(bp->dev);
4534
0aa38df7
MC		 4535 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
4536 val = REG_RD(bp, BNX2_MISC_NEW_CORE_CTL);
4537 val |= BNX2_MISC_NEW_CORE_CTL_DMA_ENABLE;
4538 REG_WR(bp, BNX2_MISC_NEW_CORE_CTL, val);
4539 }
b090ae2b
MC		 4540 rc = bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT2 | BNX2_DRV_MSG_CODE_RESET,
4541 0);
b6016b76 4542
df149d70 4543 REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS, BNX2_MISC_ENABLE_DEFAULT);
b6016b76
MC		 4544 REG_RD(bp, BNX2_MISC_ENABLE_SET_BITS);
4545
4546 udelay(20);
4547
bf5295bb
MC		 4548 bp->hc_cmd = REG_RD(bp, BNX2_HC_COMMAND);
4549
b090ae2b 4550 return rc;
b6016b76
MC		 4551}
4552
c76c0475
MC		 4553static void
4554bnx2_clear_ring_states(struct bnx2 *bp)
4555{
4556 struct bnx2_napi *bnapi;
4557 int i;
4558
4559 for (i = 0; i < BNX2_MAX_MSIX_VEC; i++) {
4560 bnapi = &bp->bnx2_napi[i];
4561
4562 bnapi->tx_cons = 0;
4563 bnapi->hw_tx_cons = 0;
4564 bnapi->rx_prod_bseq = 0;
4565 bnapi->rx_prod = 0;
4566 bnapi->rx_cons = 0;
4567 bnapi->rx_pg_prod = 0;
4568 bnapi->rx_pg_cons = 0;
4569 }
4570}
4571
59b47d8a
MC		 4572static void
4573bnx2_init_tx_context(struct bnx2 *bp, u32 cid)
4574{
4575 u32 val, offset0, offset1, offset2, offset3;
62a8313c 4576 u32 cid_addr = GET_CID_ADDR(cid);
59b47d8a
MC		 4577
4578 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
4579 offset0 = BNX2_L2CTX_TYPE_XI;
4580 offset1 = BNX2_L2CTX_CMD_TYPE_XI;
4581 offset2 = BNX2_L2CTX_TBDR_BHADDR_HI_XI;
4582 offset3 = BNX2_L2CTX_TBDR_BHADDR_LO_XI;
4583 } else {
4584 offset0 = BNX2_L2CTX_TYPE;
4585 offset1 = BNX2_L2CTX_CMD_TYPE;
4586 offset2 = BNX2_L2CTX_TBDR_BHADDR_HI;
4587 offset3 = BNX2_L2CTX_TBDR_BHADDR_LO;
4588 }
4589 val = BNX2_L2CTX_TYPE_TYPE_L2 | BNX2_L2CTX_TYPE_SIZE_L2;
62a8313c 4590 bnx2_ctx_wr(bp, cid_addr, offset0, val);
59b47d8a
MC		 4591
4592 val = BNX2_L2CTX_CMD_TYPE_TYPE_L2 | (8 << 16);
62a8313c 4593 bnx2_ctx_wr(bp, cid_addr, offset1, val);
59b47d8a
MC		 4594
4595 val = (u64) bp->tx_desc_mapping >> 32;
62a8313c 4596 bnx2_ctx_wr(bp, cid_addr, offset2, val);
59b47d8a
MC		 4597
4598 val = (u64) bp->tx_desc_mapping & 0xffffffff;
62a8313c 4599 bnx2_ctx_wr(bp, cid_addr, offset3, val);
59b47d8a 4600}
b6016b76
MC		 4601
4602static void
4603bnx2_init_tx_ring(struct bnx2 *bp)
4604{
4605 struct tx_bd *txbd;
c76c0475
MC		 4606 u32 cid = TX_CID;
4607 struct bnx2_napi *bnapi;
4608
4609 bp->tx_vec = 0;
f86e82fb 4610 if (bp->flags & BNX2_FLAG_USING_MSIX) {
c76c0475
MC		 4611 cid = TX_TSS_CID;
4612 bp->tx_vec = BNX2_TX_VEC;
4613 REG_WR(bp, BNX2_TSCH_TSS_CFG, BNX2_TX_INT_NUM |
4614 (TX_TSS_CID << 7));
4615 }
4616 bnapi = &bp->bnx2_napi[bp->tx_vec];
b6016b76 4617
2f8af120
MC		 4618 bp->tx_wake_thresh = bp->tx_ring_size / 2;
4619
b6016b76 4620 txbd = &bp->tx_desc_ring[MAX_TX_DESC_CNT];
6aa20a22 4621
b6016b76
MC		 4622 txbd->tx_bd_haddr_hi = (u64) bp->tx_desc_mapping >> 32;
4623 txbd->tx_bd_haddr_lo = (u64) bp->tx_desc_mapping & 0xffffffff;
4624
4625 bp->tx_prod = 0;
b6016b76 4626 bp->tx_prod_bseq = 0;
6aa20a22 4627
59b47d8a
MC		 4628 bp->tx_bidx_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_TX_HOST_BIDX;
4629 bp->tx_bseq_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_TX_HOST_BSEQ;
b6016b76 4630
59b47d8a 4631 bnx2_init_tx_context(bp, cid);
b6016b76
MC		 4632}
4633
4634static void
5d5d0015
MC		 4635bnx2_init_rxbd_rings(struct rx_bd *rx_ring[], dma_addr_t dma[], u32 buf_size,
4636 int num_rings)
b6016b76 4637{
b6016b76 4638 int i;
5d5d0015 4639 struct rx_bd *rxbd;
6aa20a22 4640
5d5d0015 4641 for (i = 0; i < num_rings; i++) {
13daffa2 4642 int j;
b6016b76 4643
5d5d0015 4644 rxbd = &rx_ring[i][0];
13daffa2 4645 for (j = 0; j < MAX_RX_DESC_CNT; j++, rxbd++) {
5d5d0015 4646 rxbd->rx_bd_len = buf_size;
13daffa2
MC		 4647 rxbd->rx_bd_flags = RX_BD_FLAGS_START | RX_BD_FLAGS_END;
4648 }
5d5d0015 4649 if (i == (num_rings - 1))
13daffa2
MC		 4650 j = 0;
4651 else
4652 j = i + 1;
5d5d0015
MC		 4653 rxbd->rx_bd_haddr_hi = (u64) dma[j] >> 32;
4654 rxbd->rx_bd_haddr_lo = (u64) dma[j] & 0xffffffff;
13daffa2 4655 }
5d5d0015
MC		 4656}
4657
4658static void
4659bnx2_init_rx_ring(struct bnx2 *bp)
4660{
4661 int i;
4662 u16 prod, ring_prod;
4663 u32 val, rx_cid_addr = GET_CID_ADDR(RX_CID);
b4b36042 4664 struct bnx2_napi *bnapi = &bp->bnx2_napi[0];
5d5d0015 4665
5d5d0015
MC		 4666 bnx2_init_rxbd_rings(bp->rx_desc_ring, bp->rx_desc_mapping,
4667 bp->rx_buf_use_size, bp->rx_max_ring);
4668
83e3fc89
MC		 4669 bnx2_init_rx_context0(bp);
4670
4671 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
4672 val = REG_RD(bp, BNX2_MQ_MAP_L2_5);
4673 REG_WR(bp, BNX2_MQ_MAP_L2_5, val | BNX2_MQ_MAP_L2_5_ARM);
4674 }
4675
62a8313c 4676 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_PG_BUF_SIZE, 0);
47bf4246
MC		 4677 if (bp->rx_pg_ring_size) {
4678 bnx2_init_rxbd_rings(bp->rx_pg_desc_ring,
4679 bp->rx_pg_desc_mapping,
4680 PAGE_SIZE, bp->rx_max_pg_ring);
4681 val = (bp->rx_buf_use_size << 16) | PAGE_SIZE;
62a8313c
MC		 4682 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_PG_BUF_SIZE, val);
4683 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_RBDC_KEY,
47bf4246
MC		 4684 BNX2_L2CTX_RBDC_JUMBO_KEY);
4685
4686 val = (u64) bp->rx_pg_desc_mapping[0] >> 32;
62a8313c 4687 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_PG_BDHADDR_HI, val);
47bf4246
MC		 4688
4689 val = (u64) bp->rx_pg_desc_mapping[0] & 0xffffffff;
62a8313c 4690 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_PG_BDHADDR_LO, val);
47bf4246
MC		 4691
4692 if (CHIP_NUM(bp) == CHIP_NUM_5709)
4693 REG_WR(bp, BNX2_MQ_MAP_L2_3, BNX2_MQ_MAP_L2_3_DEFAULT);
4694 }
b6016b76 4695
13daffa2 4696 val = (u64) bp->rx_desc_mapping[0] >> 32;
62a8313c 4697 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_BDHADDR_HI, val);
b6016b76 4698
13daffa2 4699 val = (u64) bp->rx_desc_mapping[0] & 0xffffffff;
62a8313c 4700 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_BDHADDR_LO, val);
b6016b76 4701
a1f60190 4702 ring_prod = prod = bnapi->rx_pg_prod;
47bf4246
MC		 4703 for (i = 0; i < bp->rx_pg_ring_size; i++) {
4704 if (bnx2_alloc_rx_page(bp, ring_prod) < 0)
4705 break;
4706 prod = NEXT_RX_BD(prod);
4707 ring_prod = RX_PG_RING_IDX(prod);
4708 }
a1f60190 4709 bnapi->rx_pg_prod = prod;
47bf4246 4710
a1f60190 4711 ring_prod = prod = bnapi->rx_prod;
236b6394 4712 for (i = 0; i < bp->rx_ring_size; i++) {
a1f60190 4713 if (bnx2_alloc_rx_skb(bp, bnapi, ring_prod) < 0) {
b6016b76
MC		 4714 break;
4715 }
4716 prod = NEXT_RX_BD(prod);
4717 ring_prod = RX_RING_IDX(prod);
4718 }
a1f60190 4719 bnapi->rx_prod = prod;
b6016b76 4720
a1f60190
MC		 4721 REG_WR16(bp, MB_RX_CID_ADDR + BNX2_L2CTX_HOST_PG_BDIDX,
4722 bnapi->rx_pg_prod);
b6016b76
MC		 4723 REG_WR16(bp, MB_RX_CID_ADDR + BNX2_L2CTX_HOST_BDIDX, prod);
4724
a1f60190 4725 REG_WR(bp, MB_RX_CID_ADDR + BNX2_L2CTX_HOST_BSEQ, bnapi->rx_prod_bseq);
b6016b76
MC		 4726}
4727
5d5d0015 4728static u32 bnx2_find_max_ring(u32 ring_size, u32 max_size)
13daffa2 4729{
5d5d0015 4730 u32 max, num_rings = 1;
13daffa2 4731
5d5d0015
MC		 4732 while (ring_size > MAX_RX_DESC_CNT) {
4733 ring_size -= MAX_RX_DESC_CNT;
13daffa2
MC		 4734 num_rings++;
4735 }
4736 /* round to next power of 2 */
5d5d0015 4737 max = max_size;
13daffa2
MC		 4738 while ((max & num_rings) == 0)
4739 max >>= 1;
4740
4741 if (num_rings != max)
4742 max <<= 1;
4743
5d5d0015
MC		 4744 return max;
4745}
4746
4747static void
4748bnx2_set_rx_ring_size(struct bnx2 *bp, u32 size)
4749{
84eaa187 4750 u32 rx_size, rx_space, jumbo_size;
5d5d0015
MC		 4751
4752 /* 8 for CRC and VLAN */
4753 rx_size = bp->dev->mtu + ETH_HLEN + bp->rx_offset + 8;
4754
84eaa187
MC		 4755 rx_space = SKB_DATA_ALIGN(rx_size + BNX2_RX_ALIGN) + NET_SKB_PAD +
4756 sizeof(struct skb_shared_info);
4757
5d5d0015 4758 bp->rx_copy_thresh = RX_COPY_THRESH;
47bf4246
MC		 4759 bp->rx_pg_ring_size = 0;
4760 bp->rx_max_pg_ring = 0;
4761 bp->rx_max_pg_ring_idx = 0;
f86e82fb 4762 if ((rx_space > PAGE_SIZE) && !(bp->flags & BNX2_FLAG_JUMBO_BROKEN)) {
84eaa187
MC		 4763 int pages = PAGE_ALIGN(bp->dev->mtu - 40) >> PAGE_SHIFT;
4764
4765 jumbo_size = size * pages;
4766 if (jumbo_size > MAX_TOTAL_RX_PG_DESC_CNT)
4767 jumbo_size = MAX_TOTAL_RX_PG_DESC_CNT;
4768
4769 bp->rx_pg_ring_size = jumbo_size;
4770 bp->rx_max_pg_ring = bnx2_find_max_ring(jumbo_size,
4771 MAX_RX_PG_RINGS);
4772 bp->rx_max_pg_ring_idx = (bp->rx_max_pg_ring * RX_DESC_CNT) - 1;
4773 rx_size = RX_COPY_THRESH + bp->rx_offset;
4774 bp->rx_copy_thresh = 0;
4775 }
5d5d0015
MC		 4776
4777 bp->rx_buf_use_size = rx_size;
4778 /* hw alignment */
4779 bp->rx_buf_size = bp->rx_buf_use_size + BNX2_RX_ALIGN;
1db82f2a 4780 bp->rx_jumbo_thresh = rx_size - bp->rx_offset;
5d5d0015
MC		 4781 bp->rx_ring_size = size;
4782 bp->rx_max_ring = bnx2_find_max_ring(size, MAX_RX_RINGS);
13daffa2
MC		 4783 bp->rx_max_ring_idx = (bp->rx_max_ring * RX_DESC_CNT) - 1;
4784}
4785
b6016b76
MC		 4786static void
4787bnx2_free_tx_skbs(struct bnx2 *bp)
4788{
4789 int i;
4790
4791 if (bp->tx_buf_ring == NULL)
4792 return;
4793
4794 for (i = 0; i < TX_DESC_CNT; ) {
4795 struct sw_bd *tx_buf = &bp->tx_buf_ring[i];
4796 struct sk_buff *skb = tx_buf->skb;
4797 int j, last;
4798
4799 if (skb == NULL) {
4800 i++;
4801 continue;
4802 }
4803
4804 pci_unmap_single(bp->pdev, pci_unmap_addr(tx_buf, mapping),
4805 skb_headlen(skb), PCI_DMA_TODEVICE);
4806
4807 tx_buf->skb = NULL;
4808
4809 last = skb_shinfo(skb)->nr_frags;
4810 for (j = 0; j < last; j++) {
4811 tx_buf = &bp->tx_buf_ring[i + j + 1];
4812 pci_unmap_page(bp->pdev,
4813 pci_unmap_addr(tx_buf, mapping),
4814 skb_shinfo(skb)->frags[j].size,
4815 PCI_DMA_TODEVICE);
4816 }
745720e5 4817 dev_kfree_skb(skb);
b6016b76
MC		 4818 i += j + 1;
4819 }
4820
4821}
4822
4823static void
4824bnx2_free_rx_skbs(struct bnx2 *bp)
4825{
4826 int i;
4827
4828 if (bp->rx_buf_ring == NULL)
4829 return;
4830
13daffa2 4831 for (i = 0; i < bp->rx_max_ring_idx; i++) {
b6016b76
MC		 4832 struct sw_bd *rx_buf = &bp->rx_buf_ring[i];
4833 struct sk_buff *skb = rx_buf->skb;
4834
05d0f1cf 4835 if (skb == NULL)
b6016b76
MC		 4836 continue;
4837
4838 pci_unmap_single(bp->pdev, pci_unmap_addr(rx_buf, mapping),
4839 bp->rx_buf_use_size, PCI_DMA_FROMDEVICE);
4840
4841 rx_buf->skb = NULL;
4842
745720e5 4843 dev_kfree_skb(skb);
b6016b76 4844 }
47bf4246
MC		 4845 for (i = 0; i < bp->rx_max_pg_ring_idx; i++)
4846 bnx2_free_rx_page(bp, i);
b6016b76
MC		 4847}
4848
4849static void
4850bnx2_free_skbs(struct bnx2 *bp)
4851{
4852 bnx2_free_tx_skbs(bp);
4853 bnx2_free_rx_skbs(bp);
4854}
4855
4856static int
4857bnx2_reset_nic(struct bnx2 *bp, u32 reset_code)
4858{
4859 int rc;
4860
4861 rc = bnx2_reset_chip(bp, reset_code);
4862 bnx2_free_skbs(bp);
4863 if (rc)
4864 return rc;
4865
fba9fe91
MC		 4866 if ((rc = bnx2_init_chip(bp)) != 0)
4867 return rc;
4868
c76c0475 4869 bnx2_clear_ring_states(bp);
b6016b76
MC		 4870 bnx2_init_tx_ring(bp);
4871 bnx2_init_rx_ring(bp);
4872 return 0;
4873}
4874
4875static int
4876bnx2_init_nic(struct bnx2 *bp)
4877{
4878 int rc;
4879
4880 if ((rc = bnx2_reset_nic(bp, BNX2_DRV_MSG_CODE_RESET)) != 0)
4881 return rc;
4882
80be4434 4883 spin_lock_bh(&bp->phy_lock);
b6016b76
MC		 4884 bnx2_init_phy(bp);
4885 bnx2_set_link(bp);
543a827d
MC		 4886 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
4887 bnx2_remote_phy_event(bp);
0d8a6571 4888 spin_unlock_bh(&bp->phy_lock);
b6016b76
MC		 4889 return 0;
4890}
4891
4892static int
4893bnx2_test_registers(struct bnx2 *bp)
4894{
4895 int ret;
5bae30c9 4896 int i, is_5709;
f71e1309 4897 static const struct {
b6016b76
MC		 4898 u16 offset;
4899 u16 flags;
5bae30c9 4900#define BNX2_FL_NOT_5709 1
b6016b76
MC		 4901 u32 rw_mask;
4902 u32 ro_mask;
4903 } reg_tbl[] = {
4904 { 0x006c, 0, 0x00000000, 0x0000003f },
4905 { 0x0090, 0, 0xffffffff, 0x00000000 },
4906 { 0x0094, 0, 0x00000000, 0x00000000 },
4907
5bae30c9
MC		 4908 { 0x0404, BNX2_FL_NOT_5709, 0x00003f00, 0x00000000 },
4909 { 0x0418, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
4910 { 0x041c, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
4911 { 0x0420, BNX2_FL_NOT_5709, 0x00000000, 0x80ffffff },
4912 { 0x0424, BNX2_FL_NOT_5709, 0x00000000, 0x00000000 },
4913 { 0x0428, BNX2_FL_NOT_5709, 0x00000000, 0x00000001 },
4914 { 0x0450, BNX2_FL_NOT_5709, 0x00000000, 0x0000ffff },
4915 { 0x0454, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
4916 { 0x0458, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
4917
4918 { 0x0808, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
4919 { 0x0854, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
4920 { 0x0868, BNX2_FL_NOT_5709, 0x00000000, 0x77777777 },
4921 { 0x086c, BNX2_FL_NOT_5709, 0x00000000, 0x77777777 },
4922 { 0x0870, BNX2_FL_NOT_5709, 0x00000000, 0x77777777 },
4923 { 0x0874, BNX2_FL_NOT_5709, 0x00000000, 0x77777777 },
4924
4925 { 0x0c00, BNX2_FL_NOT_5709, 0x00000000, 0x00000001 },
4926 { 0x0c04, BNX2_FL_NOT_5709, 0x00000000, 0x03ff0001 },
4927 { 0x0c08, BNX2_FL_NOT_5709, 0x0f0ff073, 0x00000000 },
b6016b76
MC		 4928
4929 { 0x1000, 0, 0x00000000, 0x00000001 },
15b169cc 4930 { 0x1004, BNX2_FL_NOT_5709, 0x00000000, 0x000f0001 },
b6016b76
MC		 4931
4932 { 0x1408, 0, 0x01c00800, 0x00000000 },
4933 { 0x149c, 0, 0x8000ffff, 0x00000000 },
4934 { 0x14a8, 0, 0x00000000, 0x000001ff },
5b0c76ad 4935 { 0x14ac, 0, 0x0fffffff, 0x10000000 },
b6016b76
MC		 4936 { 0x14b0, 0, 0x00000002, 0x00000001 },
4937 { 0x14b8, 0, 0x00000000, 0x00000000 },
4938 { 0x14c0, 0, 0x00000000, 0x00000009 },
4939 { 0x14c4, 0, 0x00003fff, 0x00000000 },
4940 { 0x14cc, 0, 0x00000000, 0x00000001 },
4941 { 0x14d0, 0, 0xffffffff, 0x00000000 },
b6016b76
MC		 4942
4943 { 0x1800, 0, 0x00000000, 0x00000001 },
4944 { 0x1804, 0, 0x00000000, 0x00000003 },
b6016b76
MC		 4945
4946 { 0x2800, 0, 0x00000000, 0x00000001 },
4947 { 0x2804, 0, 0x00000000, 0x00003f01 },
4948 { 0x2808, 0, 0x0f3f3f03, 0x00000000 },
4949 { 0x2810, 0, 0xffff0000, 0x00000000 },
4950 { 0x2814, 0, 0xffff0000, 0x00000000 },
4951 { 0x2818, 0, 0xffff0000, 0x00000000 },
4952 { 0x281c, 0, 0xffff0000, 0x00000000 },
4953 { 0x2834, 0, 0xffffffff, 0x00000000 },
4954 { 0x2840, 0, 0x00000000, 0xffffffff },
4955 { 0x2844, 0, 0x00000000, 0xffffffff },
4956 { 0x2848, 0, 0xffffffff, 0x00000000 },
4957 { 0x284c, 0, 0xf800f800, 0x07ff07ff },
4958
4959 { 0x2c00, 0, 0x00000000, 0x00000011 },
4960 { 0x2c04, 0, 0x00000000, 0x00030007 },
4961
b6016b76
MC		 4962 { 0x3c00, 0, 0x00000000, 0x00000001 },
4963 { 0x3c04, 0, 0x00000000, 0x00070000 },
4964 { 0x3c08, 0, 0x00007f71, 0x07f00000 },
4965 { 0x3c0c, 0, 0x1f3ffffc, 0x00000000 },
4966 { 0x3c10, 0, 0xffffffff, 0x00000000 },
4967 { 0x3c14, 0, 0x00000000, 0xffffffff },
4968 { 0x3c18, 0, 0x00000000, 0xffffffff },
4969 { 0x3c1c, 0, 0xfffff000, 0x00000000 },
4970 { 0x3c20, 0, 0xffffff00, 0x00000000 },
b6016b76
MC		 4971
4972 { 0x5004, 0, 0x00000000, 0x0000007f },
4973 { 0x5008, 0, 0x0f0007ff, 0x00000000 },
b6016b76 4974
b6016b76
MC		 4975 { 0x5c00, 0, 0x00000000, 0x00000001 },
4976 { 0x5c04, 0, 0x00000000, 0x0003000f },
4977 { 0x5c08, 0, 0x00000003, 0x00000000 },
4978 { 0x5c0c, 0, 0x0000fff8, 0x00000000 },
4979 { 0x5c10, 0, 0x00000000, 0xffffffff },
4980 { 0x5c80, 0, 0x00000000, 0x0f7113f1 },
4981 { 0x5c84, 0, 0x00000000, 0x0000f333 },
4982 { 0x5c88, 0, 0x00000000, 0x00077373 },
4983 { 0x5c8c, 0, 0x00000000, 0x0007f737 },
4984
4985 { 0x6808, 0, 0x0000ff7f, 0x00000000 },
4986 { 0x680c, 0, 0xffffffff, 0x00000000 },
4987 { 0x6810, 0, 0xffffffff, 0x00000000 },
4988 { 0x6814, 0, 0xffffffff, 0x00000000 },
4989 { 0x6818, 0, 0xffffffff, 0x00000000 },
4990 { 0x681c, 0, 0xffffffff, 0x00000000 },
4991 { 0x6820, 0, 0x00ff00ff, 0x00000000 },
4992 { 0x6824, 0, 0x00ff00ff, 0x00000000 },
4993 { 0x6828, 0, 0x00ff00ff, 0x00000000 },
4994 { 0x682c, 0, 0x03ff03ff, 0x00000000 },
4995 { 0x6830, 0, 0x03ff03ff, 0x00000000 },
4996 { 0x6834, 0, 0x03ff03ff, 0x00000000 },
4997 { 0x6838, 0, 0x03ff03ff, 0x00000000 },
4998 { 0x683c, 0, 0x0000ffff, 0x00000000 },
4999 { 0x6840, 0, 0x00000ff0, 0x00000000 },
5000 { 0x6844, 0, 0x00ffff00, 0x00000000 },
5001 { 0x684c, 0, 0xffffffff, 0x00000000 },
5002 { 0x6850, 0, 0x7f7f7f7f, 0x00000000 },
5003 { 0x6854, 0, 0x7f7f7f7f, 0x00000000 },
5004 { 0x6858, 0, 0x7f7f7f7f, 0x00000000 },
5005 { 0x685c, 0, 0x7f7f7f7f, 0x00000000 },
5006 { 0x6908, 0, 0x00000000, 0x0001ff0f },
5007 { 0x690c, 0, 0x00000000, 0x0ffe00f0 },
5008
5009 { 0xffff, 0, 0x00000000, 0x00000000 },
5010 };
5011
5012 ret = 0;
5bae30c9
MC		 5013 is_5709 = 0;
5014 if (CHIP_NUM(bp) == CHIP_NUM_5709)
5015 is_5709 = 1;
5016
b6016b76
MC		 5017 for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
5018 u32 offset, rw_mask, ro_mask, save_val, val;
5bae30c9
MC		 5019 u16 flags = reg_tbl[i].flags;
5020
5021 if (is_5709 && (flags & BNX2_FL_NOT_5709))
5022 continue;
b6016b76
MC		 5023
5024 offset = (u32) reg_tbl[i].offset;
5025 rw_mask = reg_tbl[i].rw_mask;
5026 ro_mask = reg_tbl[i].ro_mask;
5027
14ab9b86 5028 save_val = readl(bp->regview + offset);
b6016b76 5029
14ab9b86 5030 writel(0, bp->regview + offset);
b6016b76 5031
14ab9b86 5032 val = readl(bp->regview + offset);
b6016b76
MC		 5033 if ((val & rw_mask) != 0) {
5034 goto reg_test_err;
5035 }
5036
5037 if ((val & ro_mask) != (save_val & ro_mask)) {
5038 goto reg_test_err;
5039 }
5040
14ab9b86 5041 writel(0xffffffff, bp->regview + offset);
b6016b76 5042
14ab9b86 5043 val = readl(bp->regview + offset);
b6016b76
MC		 5044 if ((val & rw_mask) != rw_mask) {
5045 goto reg_test_err;
5046 }
5047
5048 if ((val & ro_mask) != (save_val & ro_mask)) {
5049 goto reg_test_err;
5050 }
5051
14ab9b86 5052 writel(save_val, bp->regview + offset);
b6016b76
MC		 5053 continue;
5054
5055reg_test_err:
14ab9b86 5056 writel(save_val, bp->regview + offset);
b6016b76
MC		 5057 ret = -ENODEV;
5058 break;
5059 }
5060 return ret;
5061}
5062
5063static int
5064bnx2_do_mem_test(struct bnx2 *bp, u32 start, u32 size)
5065{
f71e1309 5066 static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0x55555555,
b6016b76
MC		 5067 0xaaaaaaaa , 0xaa55aa55, 0x55aa55aa };
5068 int i;
5069
5070 for (i = 0; i < sizeof(test_pattern) / 4; i++) {
5071 u32 offset;
5072
5073 for (offset = 0; offset < size; offset += 4) {
5074
2726d6e1 5075 bnx2_reg_wr_ind(bp, start + offset, test_pattern[i]);
b6016b76 5076
2726d6e1 5077 if (bnx2_reg_rd_ind(bp, start + offset) !=
b6016b76
MC		 5078 test_pattern[i]) {
5079 return -ENODEV;
5080 }
5081 }
5082 }
5083 return 0;
5084}
5085
5086static int
5087bnx2_test_memory(struct bnx2 *bp)
5088{
5089 int ret = 0;
5090 int i;
5bae30c9 5091 static struct mem_entry {
b6016b76
MC		 5092 u32 offset;
5093 u32 len;
5bae30c9 5094 } mem_tbl_5706[] = {
b6016b76 5095 { 0x60000, 0x4000 },
5b0c76ad 5096 { 0xa0000, 0x3000 },
b6016b76
MC		 5097 { 0xe0000, 0x4000 },
5098 { 0x120000, 0x4000 },
5099 { 0x1a0000, 0x4000 },
5100 { 0x160000, 0x4000 },
5101 { 0xffffffff, 0 },
5bae30c9
MC		 5102 },
5103 mem_tbl_5709[] = {
5104 { 0x60000, 0x4000 },
5105 { 0xa0000, 0x3000 },
5106 { 0xe0000, 0x4000 },
5107 { 0x120000, 0x4000 },
5108 { 0x1a0000, 0x4000 },
5109 { 0xffffffff, 0 },
b6016b76 5110 };
5bae30c9
MC		 5111 struct mem_entry *mem_tbl;
5112
5113 if (CHIP_NUM(bp) == CHIP_NUM_5709)
5114 mem_tbl = mem_tbl_5709;
5115 else
5116 mem_tbl = mem_tbl_5706;
b6016b76
MC		 5117
5118 for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
5119 if ((ret = bnx2_do_mem_test(bp, mem_tbl[i].offset,
5120 mem_tbl[i].len)) != 0) {
5121 return ret;
5122 }
5123 }
6aa20a22 5124
b6016b76
MC		 5125 return ret;
5126}
5127
bc5a0690
MC		 5128#define BNX2_MAC_LOOPBACK 0
5129#define BNX2_PHY_LOOPBACK 1
5130
b6016b76 5131static int
bc5a0690 5132bnx2_run_loopback(struct bnx2 *bp, int loopback_mode)
b6016b76
MC		 5133{
5134 unsigned int pkt_size, num_pkts, i;
5135 struct sk_buff *skb, *rx_skb;
5136 unsigned char *packet;
bc5a0690 5137 u16 rx_start_idx, rx_idx;
b6016b76
MC		 5138 dma_addr_t map;
5139 struct tx_bd *txbd;
5140 struct sw_bd *rx_buf;
5141 struct l2_fhdr *rx_hdr;
5142 int ret = -ENODEV;
c76c0475
MC		 5143 struct bnx2_napi *bnapi = &bp->bnx2_napi[0], *tx_napi;
5144
5145 tx_napi = bnapi;
f86e82fb 5146 if (bp->flags & BNX2_FLAG_USING_MSIX)
c76c0475 5147 tx_napi = &bp->bnx2_napi[BNX2_TX_VEC];
b6016b76 5148
bc5a0690
MC		 5149 if (loopback_mode == BNX2_MAC_LOOPBACK) {
5150 bp->loopback = MAC_LOOPBACK;
5151 bnx2_set_mac_loopback(bp);
5152 }
5153 else if (loopback_mode == BNX2_PHY_LOOPBACK) {
583c28e5 5154 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
489310a4
MC		 5155 return 0;
5156
80be4434 5157 bp->loopback = PHY_LOOPBACK;
bc5a0690
MC		 5158 bnx2_set_phy_loopback(bp);
5159 }
5160 else
5161 return -EINVAL;
b6016b76 5162
84eaa187 5163 pkt_size = min(bp->dev->mtu + ETH_HLEN, bp->rx_jumbo_thresh - 4);
932f3772 5164 skb = netdev_alloc_skb(bp->dev, pkt_size);
b6cbc3b6
JL		 5165 if (!skb)
5166 return -ENOMEM;
b6016b76 5167 packet = skb_put(skb, pkt_size);
6634292b 5168 memcpy(packet, bp->dev->dev_addr, 6);
b6016b76
MC		 5169 memset(packet + 6, 0x0, 8);
5170 for (i = 14; i < pkt_size; i++)
5171 packet[i] = (unsigned char) (i & 0xff);
5172
5173 map = pci_map_single(bp->pdev, skb->data, pkt_size,
5174 PCI_DMA_TODEVICE);
5175
bf5295bb
MC		 5176 REG_WR(bp, BNX2_HC_COMMAND,
5177 bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
5178
b6016b76
MC		 5179 REG_RD(bp, BNX2_HC_COMMAND);
5180
5181 udelay(5);
35efa7c1 5182 rx_start_idx = bnx2_get_hw_rx_cons(bnapi);
b6016b76 5183
b6016b76
MC		 5184 num_pkts = 0;
5185
bc5a0690 5186 txbd = &bp->tx_desc_ring[TX_RING_IDX(bp->tx_prod)];
b6016b76
MC		 5187
5188 txbd->tx_bd_haddr_hi = (u64) map >> 32;
5189 txbd->tx_bd_haddr_lo = (u64) map & 0xffffffff;
5190 txbd->tx_bd_mss_nbytes = pkt_size;
5191 txbd->tx_bd_vlan_tag_flags = TX_BD_FLAGS_START | TX_BD_FLAGS_END;
5192
5193 num_pkts++;
bc5a0690
MC		 5194 bp->tx_prod = NEXT_TX_BD(bp->tx_prod);
5195 bp->tx_prod_bseq += pkt_size;
b6016b76 5196
234754d5
MC		 5197 REG_WR16(bp, bp->tx_bidx_addr, bp->tx_prod);
5198 REG_WR(bp, bp->tx_bseq_addr, bp->tx_prod_bseq);
b6016b76
MC		 5199
5200 udelay(100);
5201
bf5295bb
MC		 5202 REG_WR(bp, BNX2_HC_COMMAND,
5203 bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
5204
b6016b76
MC		 5205 REG_RD(bp, BNX2_HC_COMMAND);
5206
5207 udelay(5);
5208
5209 pci_unmap_single(bp->pdev, map, pkt_size, PCI_DMA_TODEVICE);
745720e5 5210 dev_kfree_skb(skb);
b6016b76 5211
c76c0475 5212 if (bnx2_get_hw_tx_cons(tx_napi) != bp->tx_prod)
b6016b76 5213 goto loopback_test_done;
b6016b76 5214
35efa7c1 5215 rx_idx = bnx2_get_hw_rx_cons(bnapi);
b6016b76
MC		 5216 if (rx_idx != rx_start_idx + num_pkts) {
5217 goto loopback_test_done;
5218 }
5219
5220 rx_buf = &bp->rx_buf_ring[rx_start_idx];
5221 rx_skb = rx_buf->skb;
5222
5223 rx_hdr = (struct l2_fhdr *) rx_skb->data;
5224 skb_reserve(rx_skb, bp->rx_offset);
5225
5226 pci_dma_sync_single_for_cpu(bp->pdev,
5227 pci_unmap_addr(rx_buf, mapping),
5228 bp->rx_buf_size, PCI_DMA_FROMDEVICE);
5229
ade2bfe7 5230 if (rx_hdr->l2_fhdr_status &
b6016b76
MC		 5231 (L2_FHDR_ERRORS_BAD_CRC |
5232 L2_FHDR_ERRORS_PHY_DECODE |
5233 L2_FHDR_ERRORS_ALIGNMENT |
5234 L2_FHDR_ERRORS_TOO_SHORT |
5235 L2_FHDR_ERRORS_GIANT_FRAME)) {
5236
5237 goto loopback_test_done;
5238 }
5239
5240 if ((rx_hdr->l2_fhdr_pkt_len - 4) != pkt_size) {
5241 goto loopback_test_done;
5242 }
5243
5244 for (i = 14; i < pkt_size; i++) {
5245 if (*(rx_skb->data + i) != (unsigned char) (i & 0xff)) {
5246 goto loopback_test_done;
5247 }
5248 }
5249
5250 ret = 0;
5251
5252loopback_test_done:
5253 bp->loopback = 0;
5254 return ret;
5255}
5256
bc5a0690
MC		 5257#define BNX2_MAC_LOOPBACK_FAILED 1
5258#define BNX2_PHY_LOOPBACK_FAILED 2
5259#define BNX2_LOOPBACK_FAILED (BNX2_MAC_LOOPBACK_FAILED | \
5260 BNX2_PHY_LOOPBACK_FAILED)
5261
5262static int
5263bnx2_test_loopback(struct bnx2 *bp)
5264{
5265 int rc = 0;
5266
5267 if (!netif_running(bp->dev))
5268 return BNX2_LOOPBACK_FAILED;
5269
5270 bnx2_reset_nic(bp, BNX2_DRV_MSG_CODE_RESET);
5271 spin_lock_bh(&bp->phy_lock);
5272 bnx2_init_phy(bp);
5273 spin_unlock_bh(&bp->phy_lock);
5274 if (bnx2_run_loopback(bp, BNX2_MAC_LOOPBACK))
5275 rc |= BNX2_MAC_LOOPBACK_FAILED;
5276 if (bnx2_run_loopback(bp, BNX2_PHY_LOOPBACK))
5277 rc |= BNX2_PHY_LOOPBACK_FAILED;
5278 return rc;
5279}
5280
b6016b76
MC		 5281#define NVRAM_SIZE 0x200
5282#define CRC32_RESIDUAL 0xdebb20e3
5283
5284static int
5285bnx2_test_nvram(struct bnx2 *bp)
5286{
b491edd5 5287 __be32 buf[NVRAM_SIZE / 4];
b6016b76
MC		 5288 u8 *data = (u8 *) buf;
5289 int rc = 0;
5290 u32 magic, csum;
5291
5292 if ((rc = bnx2_nvram_read(bp, 0, data, 4)) != 0)
5293 goto test_nvram_done;
5294
5295 magic = be32_to_cpu(buf[0]);
5296 if (magic != 0x669955aa) {
5297 rc = -ENODEV;
5298 goto test_nvram_done;
5299 }
5300
5301 if ((rc = bnx2_nvram_read(bp, 0x100, data, NVRAM_SIZE)) != 0)
5302 goto test_nvram_done;
5303
5304 csum = ether_crc_le(0x100, data);
5305 if (csum != CRC32_RESIDUAL) {
5306 rc = -ENODEV;
5307 goto test_nvram_done;
5308 }
5309
5310 csum = ether_crc_le(0x100, data + 0x100);
5311 if (csum != CRC32_RESIDUAL) {
5312 rc = -ENODEV;
5313 }
5314
5315test_nvram_done:
5316 return rc;
5317}
5318
5319static int
5320bnx2_test_link(struct bnx2 *bp)
5321{
5322 u32 bmsr;
5323
583c28e5 5324 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) {
489310a4
MC		 5325 if (bp->link_up)
5326 return 0;
5327 return -ENODEV;
5328 }
c770a65c 5329 spin_lock_bh(&bp->phy_lock);
27a005b8
MC		 5330 bnx2_enable_bmsr1(bp);
5331 bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr);
5332 bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr);
5333 bnx2_disable_bmsr1(bp);
c770a65c 5334 spin_unlock_bh(&bp->phy_lock);
6aa20a22 5335
b6016b76
MC		 5336 if (bmsr & BMSR_LSTATUS) {
5337 return 0;
5338 }
5339 return -ENODEV;
5340}
5341
5342static int
5343bnx2_test_intr(struct bnx2 *bp)
5344{
5345 int i;
b6016b76
MC		 5346 u16 status_idx;
5347
5348 if (!netif_running(bp->dev))
5349 return -ENODEV;
5350
5351 status_idx = REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD) & 0xffff;
5352
5353 /* This register is not touched during run-time. */
bf5295bb 5354 REG_WR(bp, BNX2_HC_COMMAND, bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW);
b6016b76
MC		 5355 REG_RD(bp, BNX2_HC_COMMAND);
5356
5357 for (i = 0; i < 10; i++) {
5358 if ((REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD) & 0xffff) !=
5359 status_idx) {
5360
5361 break;
5362 }
5363
5364 msleep_interruptible(10);
5365 }
5366 if (i < 10)
5367 return 0;
5368
5369 return -ENODEV;
5370}
5371
38ea3686 5372/* Determining link for parallel detection. */
b2fadeae
MC		 5373static int
5374bnx2_5706_serdes_has_link(struct bnx2 *bp)
5375{
5376 u32 mode_ctl, an_dbg, exp;
5377
38ea3686
MC		 5378 if (bp->phy_flags & BNX2_PHY_FLAG_NO_PARALLEL)
5379 return 0;
5380
b2fadeae
MC		 5381 bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_MODE_CTL);
5382 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &mode_ctl);
5383
5384 if (!(mode_ctl & MISC_SHDW_MODE_CTL_SIG_DET))
5385 return 0;
5386
5387 bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_AN_DBG);
5388 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &an_dbg);
5389 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &an_dbg);
5390
f3014c0c 5391 if (an_dbg & (MISC_SHDW_AN_DBG_NOSYNC | MISC_SHDW_AN_DBG_RUDI_INVALID))
b2fadeae
MC		 5392 return 0;
5393
5394 bnx2_write_phy(bp, MII_BNX2_DSP_ADDRESS, MII_EXPAND_REG1);
5395 bnx2_read_phy(bp, MII_BNX2_DSP_RW_PORT, &exp);
5396 bnx2_read_phy(bp, MII_BNX2_DSP_RW_PORT, &exp);
5397
5398 if (exp & MII_EXPAND_REG1_RUDI_C) /* receiving CONFIG */
5399 return 0;
5400
5401 return 1;
5402}
5403
b6016b76 5404static void
48b01e2d 5405bnx2_5706_serdes_timer(struct bnx2 *bp)
b6016b76 5406{
b2fadeae
MC		 5407 int check_link = 1;
5408
48b01e2d 5409 spin_lock(&bp->phy_lock);
b2fadeae 5410 if (bp->serdes_an_pending) {
48b01e2d 5411 bp->serdes_an_pending--;
b2fadeae
MC		 5412 check_link = 0;
5413 } else if ((bp->link_up == 0) && (bp->autoneg & AUTONEG_SPEED)) {
48b01e2d 5414 u32 bmcr;
b6016b76 5415
48b01e2d 5416 bp->current_interval = bp->timer_interval;
cd339a0e 5417
ca58c3af 5418 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
b6016b76 5419
48b01e2d 5420 if (bmcr & BMCR_ANENABLE) {
b2fadeae 5421 if (bnx2_5706_serdes_has_link(bp)) {
48b01e2d
MC		 5422 bmcr &= ~BMCR_ANENABLE;
5423 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
ca58c3af 5424 bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
583c28e5 5425 bp->phy_flags |= BNX2_PHY_FLAG_PARALLEL_DETECT;
48b01e2d 5426 }
b6016b76 5427 }
48b01e2d
MC		 5428 }
5429 else if ((bp->link_up) && (bp->autoneg & AUTONEG_SPEED) &&
583c28e5 5430 (bp->phy_flags & BNX2_PHY_FLAG_PARALLEL_DETECT)) {
48b01e2d 5431 u32 phy2;
b6016b76 5432
48b01e2d
MC		 5433 bnx2_write_phy(bp, 0x17, 0x0f01);
5434 bnx2_read_phy(bp, 0x15, &phy2);
5435 if (phy2 & 0x20) {
5436 u32 bmcr;
cd339a0e 5437
ca58c3af 5438 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
48b01e2d 5439 bmcr |= BMCR_ANENABLE;
ca58c3af 5440 bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
b6016b76 5441
583c28e5 5442 bp->phy_flags &= ~BNX2_PHY_FLAG_PARALLEL_DETECT;
48b01e2d
MC		 5443 }
5444 } else
5445 bp->current_interval = bp->timer_interval;
b6016b76 5446
a2724e25 5447 if (check_link) {
b2fadeae
MC		 5448 u32 val;
5449
5450 bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_AN_DBG);
5451 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &val);
5452 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &val);
5453
a2724e25
MC		 5454 if (bp->link_up && (val & MISC_SHDW_AN_DBG_NOSYNC)) {
5455 if (!(bp->phy_flags & BNX2_PHY_FLAG_FORCED_DOWN)) {
5456 bnx2_5706s_force_link_dn(bp, 1);
5457 bp->phy_flags |= BNX2_PHY_FLAG_FORCED_DOWN;
5458 } else
5459 bnx2_set_link(bp);
5460 } else if (!bp->link_up && !(val & MISC_SHDW_AN_DBG_NOSYNC))
5461 bnx2_set_link(bp);
b2fadeae 5462 }
48b01e2d
MC		 5463 spin_unlock(&bp->phy_lock);
5464}
b6016b76 5465
f8dd064e
MC		 5466static void
5467bnx2_5708_serdes_timer(struct bnx2 *bp)
5468{
583c28e5 5469 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
0d8a6571
MC		 5470 return;
5471
583c28e5 5472 if ((bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE) == 0) {
f8dd064e
MC		 5473 bp->serdes_an_pending = 0;
5474 return;
5475 }
b6016b76 5476
f8dd064e
MC		 5477 spin_lock(&bp->phy_lock);
5478 if (bp->serdes_an_pending)
5479 bp->serdes_an_pending--;
5480 else if ((bp->link_up == 0) && (bp->autoneg & AUTONEG_SPEED)) {
5481 u32 bmcr;
b6016b76 5482
ca58c3af 5483 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
f8dd064e 5484 if (bmcr & BMCR_ANENABLE) {
605a9e20 5485 bnx2_enable_forced_2g5(bp);
f8dd064e
MC		 5486 bp->current_interval = SERDES_FORCED_TIMEOUT;
5487 } else {
605a9e20 5488 bnx2_disable_forced_2g5(bp);
f8dd064e
MC		 5489 bp->serdes_an_pending = 2;
5490 bp->current_interval = bp->timer_interval;
b6016b76 5491 }
b6016b76 5492
f8dd064e
MC		 5493 } else
5494 bp->current_interval = bp->timer_interval;
b6016b76 5495
f8dd064e
MC		 5496 spin_unlock(&bp->phy_lock);
5497}
5498
48b01e2d
MC		 5499static void
5500bnx2_timer(unsigned long data)
5501{
5502 struct bnx2 *bp = (struct bnx2 *) data;
b6016b76 5503
48b01e2d
MC		 5504 if (!netif_running(bp->dev))
5505 return;
b6016b76 5506
48b01e2d
MC		 5507 if (atomic_read(&bp->intr_sem) != 0)
5508 goto bnx2_restart_timer;
b6016b76 5509
df149d70 5510 bnx2_send_heart_beat(bp);
b6016b76 5511
2726d6e1
MC		 5512 bp->stats_blk->stat_FwRxDrop =
5513 bnx2_reg_rd_ind(bp, BNX2_FW_RX_DROP_COUNT);
b6016b76 5514
02537b06
MC		 5515 /* workaround occasional corrupted counters */
5516 if (CHIP_NUM(bp) == CHIP_NUM_5708 && bp->stats_ticks)
5517 REG_WR(bp, BNX2_HC_COMMAND, bp->hc_cmd |
5518 BNX2_HC_COMMAND_STATS_NOW);
5519
583c28e5 5520 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
f8dd064e
MC		 5521 if (CHIP_NUM(bp) == CHIP_NUM_5706)
5522 bnx2_5706_serdes_timer(bp);
27a005b8 5523 else
f8dd064e 5524 bnx2_5708_serdes_timer(bp);
b6016b76
MC		 5525 }
5526
5527bnx2_restart_timer:
cd339a0e 5528 mod_timer(&bp->timer, jiffies + bp->current_interval);
b6016b76
MC		 5529}
5530
8e6a72c4
MC		 5531static int
5532bnx2_request_irq(struct bnx2 *bp)
5533{
5534 struct net_device *dev = bp->dev;
6d866ffc 5535 unsigned long flags;
b4b36042
MC		 5536 struct bnx2_irq *irq;
5537 int rc = 0, i;
8e6a72c4 5538
f86e82fb 5539 if (bp->flags & BNX2_FLAG_USING_MSI_OR_MSIX)
6d866ffc
MC		 5540 flags = 0;
5541 else
5542 flags = IRQF_SHARED;
b4b36042
MC		 5543
5544 for (i = 0; i < bp->irq_nvecs; i++) {
5545 irq = &bp->irq_tbl[i];
c76c0475 5546 rc = request_irq(irq->vector, irq->handler, flags, irq->name,
b4b36042
MC		 5547 dev);
5548 if (rc)
5549 break;
5550 irq->requested = 1;
5551 }
8e6a72c4
MC		 5552 return rc;
5553}
5554
5555static void
5556bnx2_free_irq(struct bnx2 *bp)
5557{
5558 struct net_device *dev = bp->dev;
b4b36042
MC		 5559 struct bnx2_irq *irq;
5560 int i;
8e6a72c4 5561
b4b36042
MC		 5562 for (i = 0; i < bp->irq_nvecs; i++) {
5563 irq = &bp->irq_tbl[i];
5564 if (irq->requested)
5565 free_irq(irq->vector, dev);
5566 irq->requested = 0;
6d866ffc 5567 }
f86e82fb 5568 if (bp->flags & BNX2_FLAG_USING_MSI)
b4b36042 5569 pci_disable_msi(bp->pdev);
f86e82fb 5570 else if (bp->flags & BNX2_FLAG_USING_MSIX)
b4b36042
MC		 5571 pci_disable_msix(bp->pdev);
5572
f86e82fb 5573 bp->flags &= ~(BNX2_FLAG_USING_MSI_OR_MSIX | BNX2_FLAG_ONE_SHOT_MSI);
b4b36042
MC		 5574}
5575
5576static void
5577bnx2_enable_msix(struct bnx2 *bp)
5578{
57851d84
MC		 5579 int i, rc;
5580 struct msix_entry msix_ent[BNX2_MAX_MSIX_VEC];
5581
b4b36042
MC		 5582 bnx2_setup_msix_tbl(bp);
5583 REG_WR(bp, BNX2_PCI_MSIX_CONTROL, BNX2_MAX_MSIX_HW_VEC - 1);
5584 REG_WR(bp, BNX2_PCI_MSIX_TBL_OFF_BIR, BNX2_PCI_GRC_WINDOW2_BASE);
5585 REG_WR(bp, BNX2_PCI_MSIX_PBA_OFF_BIT, BNX2_PCI_GRC_WINDOW3_BASE);
57851d84
MC		 5586
5587 for (i = 0; i < BNX2_MAX_MSIX_VEC; i++) {
5588 msix_ent[i].entry = i;
5589 msix_ent[i].vector = 0;
5590 }
5591
5592 rc = pci_enable_msix(bp->pdev, msix_ent, BNX2_MAX_MSIX_VEC);
5593 if (rc != 0)
5594 return;
5595
5596 bp->irq_tbl[BNX2_BASE_VEC].handler = bnx2_msi_1shot;
5597 bp->irq_tbl[BNX2_TX_VEC].handler = bnx2_tx_msix;
5598
5599 strcpy(bp->irq_tbl[BNX2_BASE_VEC].name, bp->dev->name);
5600 strcat(bp->irq_tbl[BNX2_BASE_VEC].name, "-base");
5601 strcpy(bp->irq_tbl[BNX2_TX_VEC].name, bp->dev->name);
5602 strcat(bp->irq_tbl[BNX2_TX_VEC].name, "-tx");
5603
5604 bp->irq_nvecs = BNX2_MAX_MSIX_VEC;
f86e82fb 5605 bp->flags |= BNX2_FLAG_USING_MSIX | BNX2_FLAG_ONE_SHOT_MSI;
57851d84
MC		 5606 for (i = 0; i < BNX2_MAX_MSIX_VEC; i++)
5607 bp->irq_tbl[i].vector = msix_ent[i].vector;
6d866ffc
MC		 5608}
5609
5610static void
5611bnx2_setup_int_mode(struct bnx2 *bp, int dis_msi)
5612{
5613 bp->irq_tbl[0].handler = bnx2_interrupt;
5614 strcpy(bp->irq_tbl[0].name, bp->dev->name);
b4b36042
MC		 5615 bp->irq_nvecs = 1;
5616 bp->irq_tbl[0].vector = bp->pdev->irq;
5617
f86e82fb 5618 if ((bp->flags & BNX2_FLAG_MSIX_CAP) && !dis_msi)
b4b36042 5619 bnx2_enable_msix(bp);
6d866ffc 5620
f86e82fb
DM		 5621 if ((bp->flags & BNX2_FLAG_MSI_CAP) && !dis_msi &&
5622 !(bp->flags & BNX2_FLAG_USING_MSIX)) {
6d866ffc 5623 if (pci_enable_msi(bp->pdev) == 0) {
f86e82fb 5624 bp->flags |= BNX2_FLAG_USING_MSI;
6d866ffc 5625 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
f86e82fb 5626 bp->flags |= BNX2_FLAG_ONE_SHOT_MSI;
6d866ffc
MC		 5627 bp->irq_tbl[0].handler = bnx2_msi_1shot;
5628 } else
5629 bp->irq_tbl[0].handler = bnx2_msi;
b4b36042
MC		 5630
5631 bp->irq_tbl[0].vector = bp->pdev->irq;
6d866ffc
MC		 5632 }
5633 }
8e6a72c4
MC		 5634}
5635
b6016b76
MC		 5636/* Called with rtnl_lock */
5637static int
5638bnx2_open(struct net_device *dev)
5639{
972ec0d4 5640 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 5641 int rc;
5642
1b2f922f
MC		 5643 netif_carrier_off(dev);
5644
829ca9a3 5645 bnx2_set_power_state(bp, PCI_D0);
b6016b76
MC		 5646 bnx2_disable_int(bp);
5647
5648 rc = bnx2_alloc_mem(bp);
5649 if (rc)
5650 return rc;
5651
6d866ffc 5652 bnx2_setup_int_mode(bp, disable_msi);
35efa7c1 5653 bnx2_napi_enable(bp);
8e6a72c4
MC		 5654 rc = bnx2_request_irq(bp);
5655
b6016b76 5656 if (rc) {
35efa7c1 5657 bnx2_napi_disable(bp);
b6016b76
MC		 5658 bnx2_free_mem(bp);
5659 return rc;
5660 }
5661
5662 rc = bnx2_init_nic(bp);
5663
5664 if (rc) {
35efa7c1 5665 bnx2_napi_disable(bp);
8e6a72c4 5666 bnx2_free_irq(bp);
b6016b76
MC		 5667 bnx2_free_skbs(bp);
5668 bnx2_free_mem(bp);
5669 return rc;
5670 }
6aa20a22 5671
cd339a0e 5672 mod_timer(&bp->timer, jiffies + bp->current_interval);
b6016b76
MC		 5673
5674 atomic_set(&bp->intr_sem, 0);
5675
5676 bnx2_enable_int(bp);
5677
f86e82fb 5678 if (bp->flags & BNX2_FLAG_USING_MSI) {
b6016b76
MC		 5679 /* Test MSI to make sure it is working
5680 * If MSI test fails, go back to INTx mode
5681 */
5682 if (bnx2_test_intr(bp) != 0) {
5683 printk(KERN_WARNING PFX "%s: No interrupt was generated"
5684 " using MSI, switching to INTx mode. Please"
5685 " report this failure to the PCI maintainer"
5686 " and include system chipset information.\n",
5687 bp->dev->name);
5688
5689 bnx2_disable_int(bp);
8e6a72c4 5690 bnx2_free_irq(bp);
b6016b76 5691
6d866ffc
MC		 5692 bnx2_setup_int_mode(bp, 1);
5693
b6016b76
MC		 5694 rc = bnx2_init_nic(bp);
5695
8e6a72c4
MC		 5696 if (!rc)
5697 rc = bnx2_request_irq(bp);
5698
b6016b76 5699 if (rc) {
35efa7c1 5700 bnx2_napi_disable(bp);
b6016b76
MC		 5701 bnx2_free_skbs(bp);
5702 bnx2_free_mem(bp);
5703 del_timer_sync(&bp->timer);
5704 return rc;
5705 }
5706 bnx2_enable_int(bp);
5707 }
5708 }
f86e82fb 5709 if (bp->flags & BNX2_FLAG_USING_MSI)
b6016b76 5710 printk(KERN_INFO PFX "%s: using MSI\n", dev->name);
f86e82fb 5711 else if (bp->flags & BNX2_FLAG_USING_MSIX)
57851d84 5712 printk(KERN_INFO PFX "%s: using MSIX\n", dev->name);
b6016b76
MC		 5713
5714 netif_start_queue(dev);
5715
5716 return 0;
5717}
5718
5719static void
c4028958 5720bnx2_reset_task(struct work_struct *work)
b6016b76 5721{
c4028958 5722 struct bnx2 *bp = container_of(work, struct bnx2, reset_task);
b6016b76 5723
afdc08b9
MC		 5724 if (!netif_running(bp->dev))
5725 return;
5726
5727 bp->in_reset_task = 1;
b6016b76
MC		 5728 bnx2_netif_stop(bp);
5729
5730 bnx2_init_nic(bp);
5731
5732 atomic_set(&bp->intr_sem, 1);
5733 bnx2_netif_start(bp);
afdc08b9 5734 bp->in_reset_task = 0;
b6016b76
MC		 5735}
5736
5737static void
5738bnx2_tx_timeout(struct net_device *dev)
5739{
972ec0d4 5740 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 5741
5742 /* This allows the netif to be shutdown gracefully before resetting */
5743 schedule_work(&bp->reset_task);
5744}
5745
5746#ifdef BCM_VLAN
5747/* Called with rtnl_lock */
5748static void
5749bnx2_vlan_rx_register(struct net_device *dev, struct vlan_group *vlgrp)
5750{
972ec0d4 5751 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 5752
5753 bnx2_netif_stop(bp);
5754
5755 bp->vlgrp = vlgrp;
5756 bnx2_set_rx_mode(dev);
5757
5758 bnx2_netif_start(bp);
5759}
b6016b76
MC		 5760#endif
5761
932ff279 5762/* Called with netif_tx_lock.
2f8af120
MC		 5763 * bnx2_tx_int() runs without netif_tx_lock unless it needs to call
5764 * netif_wake_queue().
b6016b76
MC		 5765 */
5766static int
5767bnx2_start_xmit(struct sk_buff *skb, struct net_device *dev)
5768{
972ec0d4 5769 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 5770 dma_addr_t mapping;
5771 struct tx_bd *txbd;
5772 struct sw_bd *tx_buf;
5773 u32 len, vlan_tag_flags, last_frag, mss;
5774 u16 prod, ring_prod;
5775 int i;
57851d84 5776 struct bnx2_napi *bnapi = &bp->bnx2_napi[bp->tx_vec];
b6016b76 5777
a550c99b
MC		 5778 if (unlikely(bnx2_tx_avail(bp, bnapi) <
5779 (skb_shinfo(skb)->nr_frags + 1))) {
b6016b76
MC		 5780 netif_stop_queue(dev);
5781 printk(KERN_ERR PFX "%s: BUG! Tx ring full when queue awake!\n",
5782 dev->name);
5783
5784 return NETDEV_TX_BUSY;
5785 }
5786 len = skb_headlen(skb);
5787 prod = bp->tx_prod;
5788 ring_prod = TX_RING_IDX(prod);
5789
5790 vlan_tag_flags = 0;
84fa7933 5791 if (skb->ip_summed == CHECKSUM_PARTIAL) {
b6016b76
MC		 5792 vlan_tag_flags |= TX_BD_FLAGS_TCP_UDP_CKSUM;
5793 }
5794
79ea13ce 5795 if (bp->vlgrp && vlan_tx_tag_present(skb)) {
b6016b76
MC		 5796 vlan_tag_flags |=
5797 (TX_BD_FLAGS_VLAN_TAG | (vlan_tx_tag_get(skb) << 16));
5798 }
fde82055 5799 if ((mss = skb_shinfo(skb)->gso_size)) {
b6016b76 5800 u32 tcp_opt_len, ip_tcp_len;
eddc9ec5 5801 struct iphdr *iph;
b6016b76 5802
b6016b76
MC		 5803 vlan_tag_flags |= TX_BD_FLAGS_SW_LSO;
5804
4666f87a
MC		 5805 tcp_opt_len = tcp_optlen(skb);
5806
5807 if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6) {
5808 u32 tcp_off = skb_transport_offset(skb) -
5809 sizeof(struct ipv6hdr) - ETH_HLEN;
ab6a5bb6 5810
4666f87a
MC		 5811 vlan_tag_flags |= ((tcp_opt_len >> 2) << 8) |
5812 TX_BD_FLAGS_SW_FLAGS;
5813 if (likely(tcp_off == 0))
5814 vlan_tag_flags &= ~TX_BD_FLAGS_TCP6_OFF0_MSK;
5815 else {
5816 tcp_off >>= 3;
5817 vlan_tag_flags |= ((tcp_off & 0x3) <<
5818 TX_BD_FLAGS_TCP6_OFF0_SHL) |
5819 ((tcp_off & 0x10) <<
5820 TX_BD_FLAGS_TCP6_OFF4_SHL);
5821 mss |= (tcp_off & 0xc) << TX_BD_TCP6_OFF2_SHL;
5822 }
5823 } else {
5824 if (skb_header_cloned(skb) &&
5825 pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
5826 dev_kfree_skb(skb);
5827 return NETDEV_TX_OK;
5828 }
b6016b76 5829
4666f87a
MC		 5830 ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
5831
5832 iph = ip_hdr(skb);
5833 iph->check = 0;
5834 iph->tot_len = htons(mss + ip_tcp_len + tcp_opt_len);
5835 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
5836 iph->daddr, 0,
5837 IPPROTO_TCP,
5838 0);
5839 if (tcp_opt_len || (iph->ihl > 5)) {
5840 vlan_tag_flags |= ((iph->ihl - 5) +
5841 (tcp_opt_len >> 2)) << 8;
5842 }
b6016b76 5843 }
4666f87a 5844 } else
b6016b76 5845 mss = 0;
b6016b76
MC		 5846
5847 mapping = pci_map_single(bp->pdev, skb->data, len, PCI_DMA_TODEVICE);
6aa20a22 5848
b6016b76
MC		 5849 tx_buf = &bp->tx_buf_ring[ring_prod];
5850 tx_buf->skb = skb;
5851 pci_unmap_addr_set(tx_buf, mapping, mapping);
5852
5853 txbd = &bp->tx_desc_ring[ring_prod];
5854
5855 txbd->tx_bd_haddr_hi = (u64) mapping >> 32;
5856 txbd->tx_bd_haddr_lo = (u64) mapping & 0xffffffff;
5857 txbd->tx_bd_mss_nbytes = len | (mss << 16);
5858 txbd->tx_bd_vlan_tag_flags = vlan_tag_flags | TX_BD_FLAGS_START;
5859
5860 last_frag = skb_shinfo(skb)->nr_frags;
5861
5862 for (i = 0; i < last_frag; i++) {
5863 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5864
5865 prod = NEXT_TX_BD(prod);
5866 ring_prod = TX_RING_IDX(prod);
5867 txbd = &bp->tx_desc_ring[ring_prod];
5868
5869 len = frag->size;
5870 mapping = pci_map_page(bp->pdev, frag->page, frag->page_offset,
5871 len, PCI_DMA_TODEVICE);
5872 pci_unmap_addr_set(&bp->tx_buf_ring[ring_prod],
5873 mapping, mapping);
5874
5875 txbd->tx_bd_haddr_hi = (u64) mapping >> 32;
5876 txbd->tx_bd_haddr_lo = (u64) mapping & 0xffffffff;
5877 txbd->tx_bd_mss_nbytes = len | (mss << 16);
5878 txbd->tx_bd_vlan_tag_flags = vlan_tag_flags;
5879
5880 }
5881 txbd->tx_bd_vlan_tag_flags |= TX_BD_FLAGS_END;
5882
5883 prod = NEXT_TX_BD(prod);
5884 bp->tx_prod_bseq += skb->len;
5885
234754d5
MC		 5886 REG_WR16(bp, bp->tx_bidx_addr, prod);
5887 REG_WR(bp, bp->tx_bseq_addr, bp->tx_prod_bseq);
b6016b76
MC		 5888
5889 mmiowb();
5890
5891 bp->tx_prod = prod;
5892 dev->trans_start = jiffies;
5893
a550c99b 5894 if (unlikely(bnx2_tx_avail(bp, bnapi) <= MAX_SKB_FRAGS)) {
e89bbf10 5895 netif_stop_queue(dev);
a550c99b 5896 if (bnx2_tx_avail(bp, bnapi) > bp->tx_wake_thresh)
e89bbf10 5897 netif_wake_queue(dev);
b6016b76
MC		 5898 }
5899
5900 return NETDEV_TX_OK;
5901}
5902
5903/* Called with rtnl_lock */
5904static int
5905bnx2_close(struct net_device *dev)
5906{
972ec0d4 5907 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 5908 u32 reset_code;
5909
afdc08b9
MC		 5910 /* Calling flush_scheduled_work() may deadlock because
5911 * linkwatch_event() may be on the workqueue and it will try to get
5912 * the rtnl_lock which we are holding.
5913 */
5914 while (bp->in_reset_task)
5915 msleep(1);
5916
bea3348e 5917 bnx2_disable_int_sync(bp);
35efa7c1 5918 bnx2_napi_disable(bp);
b6016b76 5919 del_timer_sync(&bp->timer);
f86e82fb 5920 if (bp->flags & BNX2_FLAG_NO_WOL)
6c4f095e 5921 reset_code = BNX2_DRV_MSG_CODE_UNLOAD_LNK_DN;
dda1e390 5922 else if (bp->wol)
b6016b76
MC		 5923 reset_code = BNX2_DRV_MSG_CODE_SUSPEND_WOL;
5924 else
5925 reset_code = BNX2_DRV_MSG_CODE_SUSPEND_NO_WOL;
5926 bnx2_reset_chip(bp, reset_code);
8e6a72c4 5927 bnx2_free_irq(bp);
b6016b76
MC		 5928 bnx2_free_skbs(bp);
5929 bnx2_free_mem(bp);
5930 bp->link_up = 0;
5931 netif_carrier_off(bp->dev);
829ca9a3 5932 bnx2_set_power_state(bp, PCI_D3hot);
b6016b76
MC		 5933 return 0;
5934}
5935
5936#define GET_NET_STATS64(ctr) \
5937 (unsigned long) ((unsigned long) (ctr##_hi) << 32) + \
5938 (unsigned long) (ctr##_lo)
5939
5940#define GET_NET_STATS32(ctr) \
5941 (ctr##_lo)
5942
5943#if (BITS_PER_LONG == 64)
5944#define GET_NET_STATS GET_NET_STATS64
5945#else
5946#define GET_NET_STATS GET_NET_STATS32
5947#endif
5948
5949static struct net_device_stats *
5950bnx2_get_stats(struct net_device *dev)
5951{
972ec0d4 5952 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 5953 struct statistics_block *stats_blk = bp->stats_blk;
5954 struct net_device_stats *net_stats = &bp->net_stats;
5955
5956 if (bp->stats_blk == NULL) {
5957 return net_stats;
5958 }
5959 net_stats->rx_packets =
5960 GET_NET_STATS(stats_blk->stat_IfHCInUcastPkts) +
5961 GET_NET_STATS(stats_blk->stat_IfHCInMulticastPkts) +
5962 GET_NET_STATS(stats_blk->stat_IfHCInBroadcastPkts);
5963
5964 net_stats->tx_packets =
5965 GET_NET_STATS(stats_blk->stat_IfHCOutUcastPkts) +
5966 GET_NET_STATS(stats_blk->stat_IfHCOutMulticastPkts) +
5967 GET_NET_STATS(stats_blk->stat_IfHCOutBroadcastPkts);
5968
5969 net_stats->rx_bytes =
5970 GET_NET_STATS(stats_blk->stat_IfHCInOctets);
5971
5972 net_stats->tx_bytes =
5973 GET_NET_STATS(stats_blk->stat_IfHCOutOctets);
5974
6aa20a22 5975 net_stats->multicast =
b6016b76
MC		 5976 GET_NET_STATS(stats_blk->stat_IfHCOutMulticastPkts);
5977
6aa20a22 5978 net_stats->collisions =
b6016b76
MC		 5979 (unsigned long) stats_blk->stat_EtherStatsCollisions;
5980
6aa20a22 5981 net_stats->rx_length_errors =
b6016b76
MC		 5982 (unsigned long) (stats_blk->stat_EtherStatsUndersizePkts +
5983 stats_blk->stat_EtherStatsOverrsizePkts);
5984
6aa20a22 5985 net_stats->rx_over_errors =
b6016b76
MC		 5986 (unsigned long) stats_blk->stat_IfInMBUFDiscards;
5987
6aa20a22 5988 net_stats->rx_frame_errors =
b6016b76
MC		 5989 (unsigned long) stats_blk->stat_Dot3StatsAlignmentErrors;
5990
6aa20a22 5991 net_stats->rx_crc_errors =
b6016b76
MC		 5992 (unsigned long) stats_blk->stat_Dot3StatsFCSErrors;
5993
5994 net_stats->rx_errors = net_stats->rx_length_errors +
5995 net_stats->rx_over_errors + net_stats->rx_frame_errors +
5996 net_stats->rx_crc_errors;
5997
5998 net_stats->tx_aborted_errors =
5999 (unsigned long) (stats_blk->stat_Dot3StatsExcessiveCollisions +
6000 stats_blk->stat_Dot3StatsLateCollisions);
6001
5b0c76ad
MC		 6002 if ((CHIP_NUM(bp) == CHIP_NUM_5706) ||
6003 (CHIP_ID(bp) == CHIP_ID_5708_A0))
b6016b76
MC		 6004 net_stats->tx_carrier_errors = 0;
6005 else {
6006 net_stats->tx_carrier_errors =
6007 (unsigned long)
6008 stats_blk->stat_Dot3StatsCarrierSenseErrors;
6009 }
6010
6011 net_stats->tx_errors =
6aa20a22 6012 (unsigned long)
b6016b76
MC		 6013 stats_blk->stat_emac_tx_stat_dot3statsinternalmactransmiterrors
6014 +
6015 net_stats->tx_aborted_errors +
6016 net_stats->tx_carrier_errors;
6017
cea94db9
MC		 6018 net_stats->rx_missed_errors =
6019 (unsigned long) (stats_blk->stat_IfInMBUFDiscards +
6020 stats_blk->stat_FwRxDrop);
6021
b6016b76
MC		 6022 return net_stats;
6023}
6024
6025/* All ethtool functions called with rtnl_lock */
6026
6027static int
6028bnx2_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
6029{
972ec0d4 6030 struct bnx2 *bp = netdev_priv(dev);
7b6b8347 6031 int support_serdes = 0, support_copper = 0;
b6016b76
MC		 6032
6033 cmd->supported = SUPPORTED_Autoneg;
583c28e5 6034 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) {
7b6b8347
MC		 6035 support_serdes = 1;
6036 support_copper = 1;
6037 } else if (bp->phy_port == PORT_FIBRE)
6038 support_serdes = 1;
6039 else
6040 support_copper = 1;
6041
6042 if (support_serdes) {
b6016b76
MC		 6043 cmd->supported |= SUPPORTED_1000baseT_Full |
6044 SUPPORTED_FIBRE;
583c28e5 6045 if (bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE)
605a9e20 6046 cmd->supported |= SUPPORTED_2500baseX_Full;
b6016b76 6047
b6016b76 6048 }
7b6b8347 6049 if (support_copper) {
b6016b76
MC		 6050 cmd->supported |= SUPPORTED_10baseT_Half |
6051 SUPPORTED_10baseT_Full |
6052 SUPPORTED_100baseT_Half |
6053 SUPPORTED_100baseT_Full |
6054 SUPPORTED_1000baseT_Full |
6055 SUPPORTED_TP;
6056
b6016b76
MC		 6057 }
6058
7b6b8347
MC		 6059 spin_lock_bh(&bp->phy_lock);
6060 cmd->port = bp->phy_port;
b6016b76
MC		 6061 cmd->advertising = bp->advertising;
6062
6063 if (bp->autoneg & AUTONEG_SPEED) {
6064 cmd->autoneg = AUTONEG_ENABLE;
6065 }
6066 else {
6067 cmd->autoneg = AUTONEG_DISABLE;
6068 }
6069
6070 if (netif_carrier_ok(dev)) {
6071 cmd->speed = bp->line_speed;
6072 cmd->duplex = bp->duplex;
6073 }
6074 else {
6075 cmd->speed = -1;
6076 cmd->duplex = -1;
6077 }
7b6b8347 6078 spin_unlock_bh(&bp->phy_lock);
b6016b76
MC		 6079
6080 cmd->transceiver = XCVR_INTERNAL;
6081 cmd->phy_address = bp->phy_addr;
6082
6083 return 0;
6084}
6aa20a22 6085
b6016b76
MC		 6086static int
6087bnx2_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
6088{
972ec0d4 6089 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 6090 u8 autoneg = bp->autoneg;
6091 u8 req_duplex = bp->req_duplex;
6092 u16 req_line_speed = bp->req_line_speed;
6093 u32 advertising = bp->advertising;
7b6b8347
MC		 6094 int err = -EINVAL;
6095
6096 spin_lock_bh(&bp->phy_lock);
6097
6098 if (cmd->port != PORT_TP && cmd->port != PORT_FIBRE)
6099 goto err_out_unlock;
6100
583c28e5
MC		 6101 if (cmd->port != bp->phy_port &&
6102 !(bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP))
7b6b8347 6103 goto err_out_unlock;
b6016b76
MC		 6104
6105 if (cmd->autoneg == AUTONEG_ENABLE) {
6106 autoneg |= AUTONEG_SPEED;
6107
6aa20a22 6108 cmd->advertising &= ETHTOOL_ALL_COPPER_SPEED;
b6016b76
MC		 6109
6110 /* allow advertising 1 speed */
6111 if ((cmd->advertising == ADVERTISED_10baseT_Half) ||
6112 (cmd->advertising == ADVERTISED_10baseT_Full) ||
6113 (cmd->advertising == ADVERTISED_100baseT_Half) ||
6114 (cmd->advertising == ADVERTISED_100baseT_Full)) {
6115
7b6b8347
MC		 6116 if (cmd->port == PORT_FIBRE)
6117 goto err_out_unlock;
b6016b76
MC		 6118
6119 advertising = cmd->advertising;
6120
27a005b8 6121 } else if (cmd->advertising == ADVERTISED_2500baseX_Full) {
583c28e5 6122 if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE) ||
7b6b8347
MC		 6123 (cmd->port == PORT_TP))
6124 goto err_out_unlock;
6125 } else if (cmd->advertising == ADVERTISED_1000baseT_Full)
b6016b76 6126 advertising = cmd->advertising;
7b6b8347
MC		 6127 else if (cmd->advertising == ADVERTISED_1000baseT_Half)
6128 goto err_out_unlock;
b6016b76 6129 else {
7b6b8347 6130 if (cmd->port == PORT_FIBRE)
b6016b76 6131 advertising = ETHTOOL_ALL_FIBRE_SPEED;
7b6b8347 6132 else
b6016b76 6133 advertising = ETHTOOL_ALL_COPPER_SPEED;
b6016b76
MC		 6134 }
6135 advertising |= ADVERTISED_Autoneg;
6136 }
6137 else {
7b6b8347 6138 if (cmd->port == PORT_FIBRE) {
80be4434
MC		 6139 if ((cmd->speed != SPEED_1000 &&
6140 cmd->speed != SPEED_2500) ||
6141 (cmd->duplex != DUPLEX_FULL))
7b6b8347 6142 goto err_out_unlock;
80be4434
MC		 6143
6144 if (cmd->speed == SPEED_2500 &&
583c28e5 6145 !(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))
7b6b8347 6146 goto err_out_unlock;
b6016b76 6147 }
7b6b8347
MC		 6148 else if (cmd->speed == SPEED_1000 || cmd->speed == SPEED_2500)
6149 goto err_out_unlock;
6150
b6016b76
MC		 6151 autoneg &= ~AUTONEG_SPEED;
6152 req_line_speed = cmd->speed;
6153 req_duplex = cmd->duplex;
6154 advertising = 0;
6155 }
6156
6157 bp->autoneg = autoneg;
6158 bp->advertising = advertising;
6159 bp->req_line_speed = req_line_speed;
6160 bp->req_duplex = req_duplex;
6161
7b6b8347 6162 err = bnx2_setup_phy(bp, cmd->port);
b6016b76 6163
7b6b8347 6164err_out_unlock:
c770a65c 6165 spin_unlock_bh(&bp->phy_lock);
b6016b76 6166
7b6b8347 6167 return err;
b6016b76
MC		 6168}
6169
6170static void
6171bnx2_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
6172{
972ec0d4 6173 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 6174
6175 strcpy(info->driver, DRV_MODULE_NAME);
6176 strcpy(info->version, DRV_MODULE_VERSION);
6177 strcpy(info->bus_info, pci_name(bp->pdev));
58fc2ea4 6178 strcpy(info->fw_version, bp->fw_version);
b6016b76
MC		 6179}
6180
244ac4f4
MC		 6181#define BNX2_REGDUMP_LEN (32 * 1024)
6182
6183static int
6184bnx2_get_regs_len(struct net_device *dev)
6185{
6186 return BNX2_REGDUMP_LEN;
6187}
6188
6189static void
6190bnx2_get_regs(struct net_device *dev, struct ethtool_regs *regs, void *_p)
6191{
6192 u32 *p = _p, i, offset;
6193 u8 *orig_p = _p;
6194 struct bnx2 *bp = netdev_priv(dev);
6195 u32 reg_boundaries[] = { 0x0000, 0x0098, 0x0400, 0x045c,
6196 0x0800, 0x0880, 0x0c00, 0x0c10,
6197 0x0c30, 0x0d08, 0x1000, 0x101c,
6198 0x1040, 0x1048, 0x1080, 0x10a4,
6199 0x1400, 0x1490, 0x1498, 0x14f0,
6200 0x1500, 0x155c, 0x1580, 0x15dc,
6201 0x1600, 0x1658, 0x1680, 0x16d8,
6202 0x1800, 0x1820, 0x1840, 0x1854,
6203 0x1880, 0x1894, 0x1900, 0x1984,
6204 0x1c00, 0x1c0c, 0x1c40, 0x1c54,
6205 0x1c80, 0x1c94, 0x1d00, 0x1d84,
6206 0x2000, 0x2030, 0x23c0, 0x2400,
6207 0x2800, 0x2820, 0x2830, 0x2850,
6208 0x2b40, 0x2c10, 0x2fc0, 0x3058,
6209 0x3c00, 0x3c94, 0x4000, 0x4010,
6210 0x4080, 0x4090, 0x43c0, 0x4458,
6211 0x4c00, 0x4c18, 0x4c40, 0x4c54,
6212 0x4fc0, 0x5010, 0x53c0, 0x5444,
6213 0x5c00, 0x5c18, 0x5c80, 0x5c90,
6214 0x5fc0, 0x6000, 0x6400, 0x6428,
6215 0x6800, 0x6848, 0x684c, 0x6860,
6216 0x6888, 0x6910, 0x8000 };
6217
6218 regs->version = 0;
6219
6220 memset(p, 0, BNX2_REGDUMP_LEN);
6221
6222 if (!netif_running(bp->dev))
6223 return;
6224
6225 i = 0;
6226 offset = reg_boundaries[0];
6227 p += offset;
6228 while (offset < BNX2_REGDUMP_LEN) {
6229 *p++ = REG_RD(bp, offset);
6230 offset += 4;
6231 if (offset == reg_boundaries[i + 1]) {
6232 offset = reg_boundaries[i + 2];
6233 p = (u32 *) (orig_p + offset);
6234 i += 2;
6235 }
6236 }
6237}
6238
b6016b76
MC		 6239static void
6240bnx2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
6241{
972ec0d4 6242 struct bnx2 *bp = netdev_priv(dev);
b6016b76 6243
f86e82fb 6244 if (bp->flags & BNX2_FLAG_NO_WOL) {
b6016b76
MC		 6245 wol->supported = 0;
6246 wol->wolopts = 0;
6247 }
6248 else {
6249 wol->supported = WAKE_MAGIC;
6250 if (bp->wol)
6251 wol->wolopts = WAKE_MAGIC;
6252 else
6253 wol->wolopts = 0;
6254 }
6255 memset(&wol->sopass, 0, sizeof(wol->sopass));
6256}
6257
6258static int
6259bnx2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
6260{
972ec0d4 6261 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 6262
6263 if (wol->wolopts & ~WAKE_MAGIC)
6264 return -EINVAL;
6265
6266 if (wol->wolopts & WAKE_MAGIC) {
f86e82fb 6267 if (bp->flags & BNX2_FLAG_NO_WOL)
b6016b76
MC		 6268 return -EINVAL;
6269
6270 bp->wol = 1;
6271 }
6272 else {
6273 bp->wol = 0;
6274 }
6275 return 0;
6276}
6277
6278static int
6279bnx2_nway_reset(struct net_device *dev)
6280{
972ec0d4 6281 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 6282 u32 bmcr;
6283
6284 if (!(bp->autoneg & AUTONEG_SPEED)) {
6285 return -EINVAL;
6286 }
6287
c770a65c 6288 spin_lock_bh(&bp->phy_lock);
b6016b76 6289
583c28e5 6290 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) {
7b6b8347
MC		 6291 int rc;
6292
6293 rc = bnx2_setup_remote_phy(bp, bp->phy_port);
6294 spin_unlock_bh(&bp->phy_lock);
6295 return rc;
6296 }
6297
b6016b76 6298 /* Force a link down visible on the other side */
583c28e5 6299 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
ca58c3af 6300 bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK);
c770a65c 6301 spin_unlock_bh(&bp->phy_lock);
b6016b76
MC		 6302
6303 msleep(20);
6304
c770a65c 6305 spin_lock_bh(&bp->phy_lock);
f8dd064e
MC		 6306
6307 bp->current_interval = SERDES_AN_TIMEOUT;
6308 bp->serdes_an_pending = 1;
6309 mod_timer(&bp->timer, jiffies + bp->current_interval);
b6016b76
MC		 6310 }
6311
ca58c3af 6312 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
b6016b76 6313 bmcr &= ~BMCR_LOOPBACK;
ca58c3af 6314 bnx2_write_phy(bp, bp->mii_bmcr, bmcr | BMCR_ANRESTART | BMCR_ANENABLE);
b6016b76 6315
c770a65c 6316 spin_unlock_bh(&bp->phy_lock);
b6016b76
MC		 6317
6318 return 0;
6319}
6320
6321static int
6322bnx2_get_eeprom_len(struct net_device *dev)
6323{
972ec0d4 6324 struct bnx2 *bp = netdev_priv(dev);
b6016b76 6325
1122db71 6326 if (bp->flash_info == NULL)
b6016b76
MC		 6327 return 0;
6328
1122db71 6329 return (int) bp->flash_size;
b6016b76
MC		 6330}
6331
6332static int
6333bnx2_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
6334 u8 *eebuf)
6335{
972ec0d4 6336 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 6337 int rc;
6338
1064e944 6339 /* parameters already validated in ethtool_get_eeprom */
b6016b76
MC		 6340
6341 rc = bnx2_nvram_read(bp, eeprom->offset, eebuf, eeprom->len);
6342
6343 return rc;
6344}
6345
6346static int
6347bnx2_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
6348 u8 *eebuf)
6349{
972ec0d4 6350 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 6351 int rc;
6352
1064e944 6353 /* parameters already validated in ethtool_set_eeprom */
b6016b76
MC		 6354
6355 rc = bnx2_nvram_write(bp, eeprom->offset, eebuf, eeprom->len);
6356
6357 return rc;
6358}
6359
6360static int
6361bnx2_get_coalesce(struct net_device *dev, struct ethtool_coalesce *coal)
6362{
972ec0d4 6363 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 6364
6365 memset(coal, 0, sizeof(struct ethtool_coalesce));
6366
6367 coal->rx_coalesce_usecs = bp->rx_ticks;
6368 coal->rx_max_coalesced_frames = bp->rx_quick_cons_trip;
6369 coal->rx_coalesce_usecs_irq = bp->rx_ticks_int;
6370 coal->rx_max_coalesced_frames_irq = bp->rx_quick_cons_trip_int;
6371
6372 coal->tx_coalesce_usecs = bp->tx_ticks;
6373 coal->tx_max_coalesced_frames = bp->tx_quick_cons_trip;
6374 coal->tx_coalesce_usecs_irq = bp->tx_ticks_int;
6375 coal->tx_max_coalesced_frames_irq = bp->tx_quick_cons_trip_int;
6376
6377 coal->stats_block_coalesce_usecs = bp->stats_ticks;
6378
6379 return 0;
6380}
6381
6382static int
6383bnx2_set_coalesce(struct net_device *dev, struct ethtool_coalesce *coal)
6384{
972ec0d4 6385 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 6386
6387 bp->rx_ticks = (u16) coal->rx_coalesce_usecs;
6388 if (bp->rx_ticks > 0x3ff) bp->rx_ticks = 0x3ff;
6389
6aa20a22 6390 bp->rx_quick_cons_trip = (u16) coal->rx_max_coalesced_frames;
b6016b76
MC		 6391 if (bp->rx_quick_cons_trip > 0xff) bp->rx_quick_cons_trip = 0xff;
6392
6393 bp->rx_ticks_int = (u16) coal->rx_coalesce_usecs_irq;
6394 if (bp->rx_ticks_int > 0x3ff) bp->rx_ticks_int = 0x3ff;
6395
6396 bp->rx_quick_cons_trip_int = (u16) coal->rx_max_coalesced_frames_irq;
6397 if (bp->rx_quick_cons_trip_int > 0xff)
6398 bp->rx_quick_cons_trip_int = 0xff;
6399
6400 bp->tx_ticks = (u16) coal->tx_coalesce_usecs;
6401 if (bp->tx_ticks > 0x3ff) bp->tx_ticks = 0x3ff;
6402
6403 bp->tx_quick_cons_trip = (u16) coal->tx_max_coalesced_frames;
6404 if (bp->tx_quick_cons_trip > 0xff) bp->tx_quick_cons_trip = 0xff;
6405
6406 bp->tx_ticks_int = (u16) coal->tx_coalesce_usecs_irq;
6407 if (bp->tx_ticks_int > 0x3ff) bp->tx_ticks_int = 0x3ff;
6408
6409 bp->tx_quick_cons_trip_int = (u16) coal->tx_max_coalesced_frames_irq;
6410 if (bp->tx_quick_cons_trip_int > 0xff) bp->tx_quick_cons_trip_int =
6411 0xff;
6412
6413 bp->stats_ticks = coal->stats_block_coalesce_usecs;
02537b06
MC		 6414 if (CHIP_NUM(bp) == CHIP_NUM_5708) {
6415 if (bp->stats_ticks != 0 && bp->stats_ticks != USEC_PER_SEC)
6416 bp->stats_ticks = USEC_PER_SEC;
6417 }
7ea6920e
MC		 6418 if (bp->stats_ticks > BNX2_HC_STATS_TICKS_HC_STAT_TICKS)
6419 bp->stats_ticks = BNX2_HC_STATS_TICKS_HC_STAT_TICKS;
6420 bp->stats_ticks &= BNX2_HC_STATS_TICKS_HC_STAT_TICKS;
b6016b76
MC		 6421
6422 if (netif_running(bp->dev)) {
6423 bnx2_netif_stop(bp);
6424 bnx2_init_nic(bp);
6425 bnx2_netif_start(bp);
6426 }
6427
6428 return 0;
6429}
6430
6431static void
6432bnx2_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
6433{
972ec0d4 6434 struct bnx2 *bp = netdev_priv(dev);
b6016b76 6435
13daffa2 6436 ering->rx_max_pending = MAX_TOTAL_RX_DESC_CNT;
b6016b76 6437 ering->rx_mini_max_pending = 0;
47bf4246 6438 ering->rx_jumbo_max_pending = MAX_TOTAL_RX_PG_DESC_CNT;
b6016b76
MC		 6439
6440 ering->rx_pending = bp->rx_ring_size;
6441 ering->rx_mini_pending = 0;
47bf4246 6442 ering->rx_jumbo_pending = bp->rx_pg_ring_size;
b6016b76
MC		 6443
6444 ering->tx_max_pending = MAX_TX_DESC_CNT;
6445 ering->tx_pending = bp->tx_ring_size;
6446}
6447
6448static int
5d5d0015 6449bnx2_change_ring_size(struct bnx2 *bp, u32 rx, u32 tx)
b6016b76 6450{
13daffa2
MC		 6451 if (netif_running(bp->dev)) {
6452 bnx2_netif_stop(bp);
6453 bnx2_reset_chip(bp, BNX2_DRV_MSG_CODE_RESET);
6454 bnx2_free_skbs(bp);
6455 bnx2_free_mem(bp);
6456 }
6457
5d5d0015
MC		 6458 bnx2_set_rx_ring_size(bp, rx);
6459 bp->tx_ring_size = tx;
b6016b76
MC		 6460
6461 if (netif_running(bp->dev)) {
13daffa2
MC		 6462 int rc;
6463
6464 rc = bnx2_alloc_mem(bp);
6465 if (rc)
6466 return rc;
b6016b76
MC		 6467 bnx2_init_nic(bp);
6468 bnx2_netif_start(bp);
6469 }
b6016b76
MC		 6470 return 0;
6471}
6472
5d5d0015
MC		 6473static int
6474bnx2_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
6475{
6476 struct bnx2 *bp = netdev_priv(dev);
6477 int rc;
6478
6479 if ((ering->rx_pending > MAX_TOTAL_RX_DESC_CNT) ||
6480 (ering->tx_pending > MAX_TX_DESC_CNT) ||
6481 (ering->tx_pending <= MAX_SKB_FRAGS)) {
6482
6483 return -EINVAL;
6484 }
6485 rc = bnx2_change_ring_size(bp, ering->rx_pending, ering->tx_pending);
6486 return rc;
6487}
6488
b6016b76
MC		 6489static void
6490bnx2_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
6491{
972ec0d4 6492 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 6493
6494 epause->autoneg = ((bp->autoneg & AUTONEG_FLOW_CTRL) != 0);
6495 epause->rx_pause = ((bp->flow_ctrl & FLOW_CTRL_RX) != 0);
6496 epause->tx_pause = ((bp->flow_ctrl & FLOW_CTRL_TX) != 0);
6497}
6498
6499static int
6500bnx2_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
6501{
972ec0d4 6502 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 6503
6504 bp->req_flow_ctrl = 0;
6505 if (epause->rx_pause)
6506 bp->req_flow_ctrl |= FLOW_CTRL_RX;
6507 if (epause->tx_pause)
6508 bp->req_flow_ctrl |= FLOW_CTRL_TX;
6509
6510 if (epause->autoneg) {
6511 bp->autoneg |= AUTONEG_FLOW_CTRL;
6512 }
6513 else {
6514 bp->autoneg &= ~AUTONEG_FLOW_CTRL;
6515 }
6516
c770a65c 6517 spin_lock_bh(&bp->phy_lock);
b6016b76 6518
0d8a6571 6519 bnx2_setup_phy(bp, bp->phy_port);
b6016b76 6520
c770a65c 6521 spin_unlock_bh(&bp->phy_lock);
b6016b76
MC		 6522
6523 return 0;
6524}
6525
6526static u32
6527bnx2_get_rx_csum(struct net_device *dev)
6528{
972ec0d4 6529 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 6530
6531 return bp->rx_csum;
6532}
6533
6534static int
6535bnx2_set_rx_csum(struct net_device *dev, u32 data)
6536{
972ec0d4 6537 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 6538
6539 bp->rx_csum = data;
6540 return 0;
6541}
6542
b11d6213
MC		 6543static int
6544bnx2_set_tso(struct net_device *dev, u32 data)
6545{
4666f87a
MC		 6546 struct bnx2 *bp = netdev_priv(dev);
6547
6548 if (data) {
b11d6213 6549 dev->features |= NETIF_F_TSO | NETIF_F_TSO_ECN;
4666f87a
MC		 6550 if (CHIP_NUM(bp) == CHIP_NUM_5709)
6551 dev->features |= NETIF_F_TSO6;
6552 } else
6553 dev->features &= ~(NETIF_F_TSO | NETIF_F_TSO6 |
6554 NETIF_F_TSO_ECN);
b11d6213
MC		 6555 return 0;
6556}
6557
cea94db9 6558#define BNX2_NUM_STATS 46
b6016b76 6559
14ab9b86 6560static struct {
b6016b76
MC		 6561 char string[ETH_GSTRING_LEN];
6562} bnx2_stats_str_arr[BNX2_NUM_STATS] = {
6563 { "rx_bytes" },
6564 { "rx_error_bytes" },
6565 { "tx_bytes" },
6566 { "tx_error_bytes" },
6567 { "rx_ucast_packets" },
6568 { "rx_mcast_packets" },
6569 { "rx_bcast_packets" },
6570 { "tx_ucast_packets" },
6571 { "tx_mcast_packets" },
6572 { "tx_bcast_packets" },
6573 { "tx_mac_errors" },
6574 { "tx_carrier_errors" },
6575 { "rx_crc_errors" },
6576 { "rx_align_errors" },
6577 { "tx_single_collisions" },
6578 { "tx_multi_collisions" },
6579 { "tx_deferred" },
6580 { "tx_excess_collisions" },
6581 { "tx_late_collisions" },
6582 { "tx_total_collisions" },
6583 { "rx_fragments" },
6584 { "rx_jabbers" },
6585 { "rx_undersize_packets" },
6586 { "rx_oversize_packets" },
6587 { "rx_64_byte_packets" },
6588 { "rx_65_to_127_byte_packets" },
6589 { "rx_128_to_255_byte_packets" },
6590 { "rx_256_to_511_byte_packets" },
6591 { "rx_512_to_1023_byte_packets" },
6592 { "rx_1024_to_1522_byte_packets" },
6593 { "rx_1523_to_9022_byte_packets" },
6594 { "tx_64_byte_packets" },
6595 { "tx_65_to_127_byte_packets" },
6596 { "tx_128_to_255_byte_packets" },
6597 { "tx_256_to_511_byte_packets" },
6598 { "tx_512_to_1023_byte_packets" },
6599 { "tx_1024_to_1522_byte_packets" },
6600 { "tx_1523_to_9022_byte_packets" },
6601 { "rx_xon_frames" },
6602 { "rx_xoff_frames" },
6603 { "tx_xon_frames" },
6604 { "tx_xoff_frames" },
6605 { "rx_mac_ctrl_frames" },
6606 { "rx_filtered_packets" },
6607 { "rx_discards" },
cea94db9 6608 { "rx_fw_discards" },
b6016b76
MC		 6609};
6610
6611#define STATS_OFFSET32(offset_name) (offsetof(struct statistics_block, offset_name) / 4)
6612
f71e1309 6613static const unsigned long bnx2_stats_offset_arr[BNX2_NUM_STATS] = {
b6016b76
MC		 6614 STATS_OFFSET32(stat_IfHCInOctets_hi),
6615 STATS_OFFSET32(stat_IfHCInBadOctets_hi),
6616 STATS_OFFSET32(stat_IfHCOutOctets_hi),
6617 STATS_OFFSET32(stat_IfHCOutBadOctets_hi),
6618 STATS_OFFSET32(stat_IfHCInUcastPkts_hi),
6619 STATS_OFFSET32(stat_IfHCInMulticastPkts_hi),
6620 STATS_OFFSET32(stat_IfHCInBroadcastPkts_hi),
6621 STATS_OFFSET32(stat_IfHCOutUcastPkts_hi),
6622 STATS_OFFSET32(stat_IfHCOutMulticastPkts_hi),
6623 STATS_OFFSET32(stat_IfHCOutBroadcastPkts_hi),
6624 STATS_OFFSET32(stat_emac_tx_stat_dot3statsinternalmactransmiterrors),
6aa20a22
JG		 6625 STATS_OFFSET32(stat_Dot3StatsCarrierSenseErrors),
6626 STATS_OFFSET32(stat_Dot3StatsFCSErrors),
6627 STATS_OFFSET32(stat_Dot3StatsAlignmentErrors),
6628 STATS_OFFSET32(stat_Dot3StatsSingleCollisionFrames),
6629 STATS_OFFSET32(stat_Dot3StatsMultipleCollisionFrames),
6630 STATS_OFFSET32(stat_Dot3StatsDeferredTransmissions),
6631 STATS_OFFSET32(stat_Dot3StatsExcessiveCollisions),
6632 STATS_OFFSET32(stat_Dot3StatsLateCollisions),
6633 STATS_OFFSET32(stat_EtherStatsCollisions),
6634 STATS_OFFSET32(stat_EtherStatsFragments),
6635 STATS_OFFSET32(stat_EtherStatsJabbers),
6636 STATS_OFFSET32(stat_EtherStatsUndersizePkts),
6637 STATS_OFFSET32(stat_EtherStatsOverrsizePkts),
6638 STATS_OFFSET32(stat_EtherStatsPktsRx64Octets),
6639 STATS_OFFSET32(stat_EtherStatsPktsRx65Octetsto127Octets),
6640 STATS_OFFSET32(stat_EtherStatsPktsRx128Octetsto255Octets),
6641 STATS_OFFSET32(stat_EtherStatsPktsRx256Octetsto511Octets),
6642 STATS_OFFSET32(stat_EtherStatsPktsRx512Octetsto1023Octets),
6643 STATS_OFFSET32(stat_EtherStatsPktsRx1024Octetsto1522Octets),
6644 STATS_OFFSET32(stat_EtherStatsPktsRx1523Octetsto9022Octets),
6645 STATS_OFFSET32(stat_EtherStatsPktsTx64Octets),
6646 STATS_OFFSET32(stat_EtherStatsPktsTx65Octetsto127Octets),
6647 STATS_OFFSET32(stat_EtherStatsPktsTx128Octetsto255Octets),
6648 STATS_OFFSET32(stat_EtherStatsPktsTx256Octetsto511Octets),
6649 STATS_OFFSET32(stat_EtherStatsPktsTx512Octetsto1023Octets),
6650 STATS_OFFSET32(stat_EtherStatsPktsTx1024Octetsto1522Octets),
6651 STATS_OFFSET32(stat_EtherStatsPktsTx1523Octetsto9022Octets),
6652 STATS_OFFSET32(stat_XonPauseFramesReceived),
6653 STATS_OFFSET32(stat_XoffPauseFramesReceived),
6654 STATS_OFFSET32(stat_OutXonSent),
6655 STATS_OFFSET32(stat_OutXoffSent),
6656 STATS_OFFSET32(stat_MacControlFramesReceived),
6657 STATS_OFFSET32(stat_IfInFramesL2FilterDiscards),
6658 STATS_OFFSET32(stat_IfInMBUFDiscards),
cea94db9 6659 STATS_OFFSET32(stat_FwRxDrop),
b6016b76
MC		 6660};
6661
6662/* stat_IfHCInBadOctets and stat_Dot3StatsCarrierSenseErrors are
6663 * skipped because of errata.
6aa20a22 6664 */
14ab9b86 6665static u8 bnx2_5706_stats_len_arr[BNX2_NUM_STATS] = {
b6016b76
MC		 6666 8,0,8,8,8,8,8,8,8,8,
6667 4,0,4,4,4,4,4,4,4,4,
6668 4,4,4,4,4,4,4,4,4,4,
6669 4,4,4,4,4,4,4,4,4,4,
cea94db9 6670 4,4,4,4,4,4,
b6016b76
MC		 6671};
6672
5b0c76ad
MC		 6673static u8 bnx2_5708_stats_len_arr[BNX2_NUM_STATS] = {
6674 8,0,8,8,8,8,8,8,8,8,
6675 4,4,4,4,4,4,4,4,4,4,
6676 4,4,4,4,4,4,4,4,4,4,
6677 4,4,4,4,4,4,4,4,4,4,
cea94db9 6678 4,4,4,4,4,4,
5b0c76ad
MC		 6679};
6680
b6016b76
MC		 6681#define BNX2_NUM_TESTS 6
6682
14ab9b86 6683static struct {
b6016b76
MC		 6684 char string[ETH_GSTRING_LEN];
6685} bnx2_tests_str_arr[BNX2_NUM_TESTS] = {
6686 { "register_test (offline)" },
6687 { "memory_test (offline)" },
6688 { "loopback_test (offline)" },
6689 { "nvram_test (online)" },
6690 { "interrupt_test (online)" },
6691 { "link_test (online)" },
6692};
6693
6694static int
b9f2c044 6695bnx2_get_sset_count(struct net_device *dev, int sset)
b6016b76 6696{
b9f2c044
JG		 6697 switch (sset) {
6698 case ETH_SS_TEST:
6699 return BNX2_NUM_TESTS;
6700 case ETH_SS_STATS:
6701 return BNX2_NUM_STATS;
6702 default:
6703 return -EOPNOTSUPP;
6704 }
b6016b76
MC		 6705}
6706
6707static void
6708bnx2_self_test(struct net_device *dev, struct ethtool_test *etest, u64 *buf)
6709{
972ec0d4 6710 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 6711
6712 memset(buf, 0, sizeof(u64) * BNX2_NUM_TESTS);
6713 if (etest->flags & ETH_TEST_FL_OFFLINE) {
80be4434
MC		 6714 int i;
6715
b6016b76
MC		 6716 bnx2_netif_stop(bp);
6717 bnx2_reset_chip(bp, BNX2_DRV_MSG_CODE_DIAG);
6718 bnx2_free_skbs(bp);
6719
6720 if (bnx2_test_registers(bp) != 0) {
6721 buf[0] = 1;
6722 etest->flags |= ETH_TEST_FL_FAILED;
6723 }
6724 if (bnx2_test_memory(bp) != 0) {
6725 buf[1] = 1;
6726 etest->flags |= ETH_TEST_FL_FAILED;
6727 }
bc5a0690 6728 if ((buf[2] = bnx2_test_loopback(bp)) != 0)
b6016b76 6729 etest->flags |= ETH_TEST_FL_FAILED;
b6016b76
MC		 6730
6731 if (!netif_running(bp->dev)) {
6732 bnx2_reset_chip(bp, BNX2_DRV_MSG_CODE_RESET);
6733 }
6734 else {
6735 bnx2_init_nic(bp);
6736 bnx2_netif_start(bp);
6737 }
6738
6739 /* wait for link up */
80be4434
MC		 6740 for (i = 0; i < 7; i++) {
6741 if (bp->link_up)
6742 break;
6743 msleep_interruptible(1000);
6744 }
b6016b76
MC		 6745 }
6746
6747 if (bnx2_test_nvram(bp) != 0) {
6748 buf[3] = 1;
6749 etest->flags |= ETH_TEST_FL_FAILED;
6750 }
6751 if (bnx2_test_intr(bp) != 0) {
6752 buf[4] = 1;
6753 etest->flags |= ETH_TEST_FL_FAILED;
6754 }
6755
6756 if (bnx2_test_link(bp) != 0) {
6757 buf[5] = 1;
6758 etest->flags |= ETH_TEST_FL_FAILED;
6759
6760 }
6761}
6762
6763static void
6764bnx2_get_strings(struct net_device *dev, u32 stringset, u8 *buf)
6765{
6766 switch (stringset) {
6767 case ETH_SS_STATS:
6768 memcpy(buf, bnx2_stats_str_arr,
6769 sizeof(bnx2_stats_str_arr));
6770 break;
6771 case ETH_SS_TEST:
6772 memcpy(buf, bnx2_tests_str_arr,
6773 sizeof(bnx2_tests_str_arr));
6774 break;
6775 }
6776}
6777
b6016b76
MC		 6778static void
6779bnx2_get_ethtool_stats(struct net_device *dev,
6780 struct ethtool_stats *stats, u64 *buf)
6781{
972ec0d4 6782 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 6783 int i;
6784 u32 *hw_stats = (u32 *) bp->stats_blk;
14ab9b86 6785 u8 *stats_len_arr = NULL;
b6016b76
MC		 6786
6787 if (hw_stats == NULL) {
6788 memset(buf, 0, sizeof(u64) * BNX2_NUM_STATS);
6789 return;
6790 }
6791
5b0c76ad
MC		 6792 if ((CHIP_ID(bp) == CHIP_ID_5706_A0) ||
6793 (CHIP_ID(bp) == CHIP_ID_5706_A1) ||
6794 (CHIP_ID(bp) == CHIP_ID_5706_A2) ||
6795 (CHIP_ID(bp) == CHIP_ID_5708_A0))
b6016b76 6796 stats_len_arr = bnx2_5706_stats_len_arr;
5b0c76ad
MC		 6797 else
6798 stats_len_arr = bnx2_5708_stats_len_arr;
b6016b76
MC		 6799
6800 for (i = 0; i < BNX2_NUM_STATS; i++) {
6801 if (stats_len_arr[i] == 0) {
6802 /* skip this counter */
6803 buf[i] = 0;
6804 continue;
6805 }
6806 if (stats_len_arr[i] == 4) {
6807 /* 4-byte counter */
6808 buf[i] = (u64)
6809 *(hw_stats + bnx2_stats_offset_arr[i]);
6810 continue;
6811 }
6812 /* 8-byte counter */
6813 buf[i] = (((u64) *(hw_stats +
6814 bnx2_stats_offset_arr[i])) << 32) +
6815 *(hw_stats + bnx2_stats_offset_arr[i] + 1);
6816 }
6817}
6818
6819static int
6820bnx2_phys_id(struct net_device *dev, u32 data)
6821{
972ec0d4 6822 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 6823 int i;
6824 u32 save;
6825
6826 if (data == 0)
6827 data = 2;
6828
6829 save = REG_RD(bp, BNX2_MISC_CFG);
6830 REG_WR(bp, BNX2_MISC_CFG, BNX2_MISC_CFG_LEDMODE_MAC);
6831
6832 for (i = 0; i < (data * 2); i++) {
6833 if ((i % 2) == 0) {
6834 REG_WR(bp, BNX2_EMAC_LED, BNX2_EMAC_LED_OVERRIDE);
6835 }
6836 else {
6837 REG_WR(bp, BNX2_EMAC_LED, BNX2_EMAC_LED_OVERRIDE |
6838 BNX2_EMAC_LED_1000MB_OVERRIDE |
6839 BNX2_EMAC_LED_100MB_OVERRIDE |
6840 BNX2_EMAC_LED_10MB_OVERRIDE |
6841 BNX2_EMAC_LED_TRAFFIC_OVERRIDE |
6842 BNX2_EMAC_LED_TRAFFIC);
6843 }
6844 msleep_interruptible(500);
6845 if (signal_pending(current))
6846 break;
6847 }
6848 REG_WR(bp, BNX2_EMAC_LED, 0);
6849 REG_WR(bp, BNX2_MISC_CFG, save);
6850 return 0;
6851}
6852
4666f87a
MC		 6853static int
6854bnx2_set_tx_csum(struct net_device *dev, u32 data)
6855{
6856 struct bnx2 *bp = netdev_priv(dev);
6857
6858 if (CHIP_NUM(bp) == CHIP_NUM_5709)
6460d948 6859 return (ethtool_op_set_tx_ipv6_csum(dev, data));
4666f87a
MC		 6860 else
6861 return (ethtool_op_set_tx_csum(dev, data));
6862}
6863
7282d491 6864static const struct ethtool_ops bnx2_ethtool_ops = {
b6016b76
MC		 6865 .get_settings = bnx2_get_settings,
6866 .set_settings = bnx2_set_settings,
6867 .get_drvinfo = bnx2_get_drvinfo,
244ac4f4
MC		 6868 .get_regs_len = bnx2_get_regs_len,
6869 .get_regs = bnx2_get_regs,
b6016b76
MC		 6870 .get_wol = bnx2_get_wol,
6871 .set_wol = bnx2_set_wol,
6872 .nway_reset = bnx2_nway_reset,
6873 .get_link = ethtool_op_get_link,
6874 .get_eeprom_len = bnx2_get_eeprom_len,
6875 .get_eeprom = bnx2_get_eeprom,
6876 .set_eeprom = bnx2_set_eeprom,
6877 .get_coalesce = bnx2_get_coalesce,
6878 .set_coalesce = bnx2_set_coalesce,
6879 .get_ringparam = bnx2_get_ringparam,
6880 .set_ringparam = bnx2_set_ringparam,
6881 .get_pauseparam = bnx2_get_pauseparam,
6882 .set_pauseparam = bnx2_set_pauseparam,
6883 .get_rx_csum = bnx2_get_rx_csum,
6884 .set_rx_csum = bnx2_set_rx_csum,
4666f87a 6885 .set_tx_csum = bnx2_set_tx_csum,
b6016b76 6886 .set_sg = ethtool_op_set_sg,
b11d6213 6887 .set_tso = bnx2_set_tso,
b6016b76
MC		 6888 .self_test = bnx2_self_test,
6889 .get_strings = bnx2_get_strings,
6890 .phys_id = bnx2_phys_id,
b6016b76 6891 .get_ethtool_stats = bnx2_get_ethtool_stats,
b9f2c044 6892 .get_sset_count = bnx2_get_sset_count,
b6016b76
MC		 6893};
6894
6895/* Called with rtnl_lock */
6896static int
6897bnx2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
6898{
14ab9b86 6899 struct mii_ioctl_data *data = if_mii(ifr);
972ec0d4 6900 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 6901 int err;
6902
6903 switch(cmd) {
6904 case SIOCGMIIPHY:
6905 data->phy_id = bp->phy_addr;
6906
6907 /* fallthru */
6908 case SIOCGMIIREG: {
6909 u32 mii_regval;
6910
583c28e5 6911 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
7b6b8347
MC		 6912 return -EOPNOTSUPP;
6913
dad3e452
MC		 6914 if (!netif_running(dev))
6915 return -EAGAIN;
6916
c770a65c 6917 spin_lock_bh(&bp->phy_lock);
b6016b76 6918 err = bnx2_read_phy(bp, data->reg_num & 0x1f, &mii_regval);
c770a65c 6919 spin_unlock_bh(&bp->phy_lock);
b6016b76
MC		 6920
6921 data->val_out = mii_regval;
6922
6923 return err;
6924 }
6925
6926 case SIOCSMIIREG:
6927 if (!capable(CAP_NET_ADMIN))
6928 return -EPERM;
6929
583c28e5 6930 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
7b6b8347
MC		 6931 return -EOPNOTSUPP;
6932
dad3e452
MC		 6933 if (!netif_running(dev))
6934 return -EAGAIN;
6935
c770a65c 6936 spin_lock_bh(&bp->phy_lock);
b6016b76 6937 err = bnx2_write_phy(bp, data->reg_num & 0x1f, data->val_in);
c770a65c 6938 spin_unlock_bh(&bp->phy_lock);
b6016b76
MC		 6939
6940 return err;
6941
6942 default:
6943 /* do nothing */
6944 break;
6945 }
6946 return -EOPNOTSUPP;
6947}
6948
6949/* Called with rtnl_lock */
6950static int
6951bnx2_change_mac_addr(struct net_device *dev, void *p)
6952{
6953 struct sockaddr *addr = p;
972ec0d4 6954 struct bnx2 *bp = netdev_priv(dev);
b6016b76 6955
73eef4cd
MC		 6956 if (!is_valid_ether_addr(addr->sa_data))
6957 return -EINVAL;
6958
b6016b76
MC		 6959 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
6960 if (netif_running(dev))
6961 bnx2_set_mac_addr(bp);
6962
6963 return 0;
6964}
6965
6966/* Called with rtnl_lock */
6967static int
6968bnx2_change_mtu(struct net_device *dev, int new_mtu)
6969{
972ec0d4 6970 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 6971
6972 if (((new_mtu + ETH_HLEN) > MAX_ETHERNET_JUMBO_PACKET_SIZE) ||
6973 ((new_mtu + ETH_HLEN) < MIN_ETHERNET_PACKET_SIZE))
6974 return -EINVAL;
6975
6976 dev->mtu = new_mtu;
5d5d0015 6977 return (bnx2_change_ring_size(bp, bp->rx_ring_size, bp->tx_ring_size));
b6016b76
MC		 6978}
6979
6980#if defined(HAVE_POLL_CONTROLLER) || defined(CONFIG_NET_POLL_CONTROLLER)
6981static void
6982poll_bnx2(struct net_device *dev)
6983{
972ec0d4 6984 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 6985
6986 disable_irq(bp->pdev->irq);
7d12e780 6987 bnx2_interrupt(bp->pdev->irq, dev);
b6016b76
MC		 6988 enable_irq(bp->pdev->irq);
6989}
6990#endif
6991
253c8b75
MC		 6992static void __devinit
6993bnx2_get_5709_media(struct bnx2 *bp)
6994{
6995 u32 val = REG_RD(bp, BNX2_MISC_DUAL_MEDIA_CTRL);
6996 u32 bond_id = val & BNX2_MISC_DUAL_MEDIA_CTRL_BOND_ID;
6997 u32 strap;
6998
6999 if (bond_id == BNX2_MISC_DUAL_MEDIA_CTRL_BOND_ID_C)
7000 return;
7001 else if (bond_id == BNX2_MISC_DUAL_MEDIA_CTRL_BOND_ID_S) {
583c28e5 7002 bp->phy_flags |= BNX2_PHY_FLAG_SERDES;
253c8b75
MC		 7003 return;
7004 }
7005
7006 if (val & BNX2_MISC_DUAL_MEDIA_CTRL_STRAP_OVERRIDE)
7007 strap = (val & BNX2_MISC_DUAL_MEDIA_CTRL_PHY_CTRL) >> 21;
7008 else
7009 strap = (val & BNX2_MISC_DUAL_MEDIA_CTRL_PHY_CTRL_STRAP) >> 8;
7010
7011 if (PCI_FUNC(bp->pdev->devfn) == 0) {
7012 switch (strap) {
7013 case 0x4:
7014 case 0x5:
7015 case 0x6:
583c28e5 7016 bp->phy_flags |= BNX2_PHY_FLAG_SERDES;
253c8b75
MC		 7017 return;
7018 }
7019 } else {
7020 switch (strap) {
7021 case 0x1:
7022 case 0x2:
7023 case 0x4:
583c28e5 7024 bp->phy_flags |= BNX2_PHY_FLAG_SERDES;
253c8b75
MC		 7025 return;
7026 }
7027 }
7028}
7029
883e5151
MC		 7030static void __devinit
7031bnx2_get_pci_speed(struct bnx2 *bp)
7032{
7033 u32 reg;
7034
7035 reg = REG_RD(bp, BNX2_PCICFG_MISC_STATUS);
7036 if (reg & BNX2_PCICFG_MISC_STATUS_PCIX_DET) {
7037 u32 clkreg;
7038
f86e82fb 7039 bp->flags |= BNX2_FLAG_PCIX;
883e5151
MC		 7040
7041 clkreg = REG_RD(bp, BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS);
7042
7043 clkreg &= BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET;
7044 switch (clkreg) {
7045 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ:
7046 bp->bus_speed_mhz = 133;
7047 break;
7048
7049 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ:
7050 bp->bus_speed_mhz = 100;
7051 break;
7052
7053 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ:
7054 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ:
7055 bp->bus_speed_mhz = 66;
7056 break;
7057
7058 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ:
7059 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ:
7060 bp->bus_speed_mhz = 50;
7061 break;
7062
7063 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_LOW:
7064 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ:
7065 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ:
7066 bp->bus_speed_mhz = 33;
7067 break;
7068 }
7069 }
7070 else {
7071 if (reg & BNX2_PCICFG_MISC_STATUS_M66EN)
7072 bp->bus_speed_mhz = 66;
7073 else
7074 bp->bus_speed_mhz = 33;
7075 }
7076
7077 if (reg & BNX2_PCICFG_MISC_STATUS_32BIT_DET)
f86e82fb 7078 bp->flags |= BNX2_FLAG_PCI_32BIT;
883e5151
MC		 7079
7080}
7081
b6016b76
MC		 7082static int __devinit
7083bnx2_init_board(struct pci_dev *pdev, struct net_device *dev)
7084{
7085 struct bnx2 *bp;
7086 unsigned long mem_len;
58fc2ea4 7087 int rc, i, j;
b6016b76 7088 u32 reg;
40453c83 7089 u64 dma_mask, persist_dma_mask;
b6016b76 7090
b6016b76 7091 SET_NETDEV_DEV(dev, &pdev->dev);
972ec0d4 7092 bp = netdev_priv(dev);
b6016b76
MC		 7093
7094 bp->flags = 0;
7095 bp->phy_flags = 0;
7096
7097 /* enable device (incl. PCI PM wakeup), and bus-mastering */
7098 rc = pci_enable_device(pdev);
7099 if (rc) {
898eb71c 7100 dev_err(&pdev->dev, "Cannot enable PCI device, aborting.\n");
b6016b76
MC		 7101 goto err_out;
7102 }
7103
7104 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
9b91cf9d 7105 dev_err(&pdev->dev,
2e8a538d 7106 "Cannot find PCI device base address, aborting.\n");
b6016b76
MC		 7107 rc = -ENODEV;
7108 goto err_out_disable;
7109 }
7110
7111 rc = pci_request_regions(pdev, DRV_MODULE_NAME);
7112 if (rc) {
9b91cf9d 7113 dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting.\n");
b6016b76
MC		 7114 goto err_out_disable;
7115 }
7116
7117 pci_set_master(pdev);
7118
7119 bp->pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
7120 if (bp->pm_cap == 0) {
9b91cf9d 7121 dev_err(&pdev->dev,
2e8a538d 7122 "Cannot find power management capability, aborting.\n");
b6016b76
MC		 7123 rc = -EIO;
7124 goto err_out_release;
7125 }
7126
b6016b76
MC		 7127 bp->dev = dev;
7128 bp->pdev = pdev;
7129
7130 spin_lock_init(&bp->phy_lock);
1b8227c4 7131 spin_lock_init(&bp->indirect_lock);
c4028958 7132 INIT_WORK(&bp->reset_task, bnx2_reset_task);
b6016b76
MC		 7133
7134 dev->base_addr = dev->mem_start = pci_resource_start(pdev, 0);
59b47d8a 7135 mem_len = MB_GET_CID_ADDR(TX_TSS_CID + 1);
b6016b76
MC		 7136 dev->mem_end = dev->mem_start + mem_len;
7137 dev->irq = pdev->irq;
7138
7139 bp->regview = ioremap_nocache(dev->base_addr, mem_len);
7140
7141 if (!bp->regview) {
9b91cf9d 7142 dev_err(&pdev->dev, "Cannot map register space, aborting.\n");
b6016b76
MC		 7143 rc = -ENOMEM;
7144 goto err_out_release;
7145 }
7146
7147 /* Configure byte swap and enable write to the reg_window registers.
7148 * Rely on CPU to do target byte swapping on big endian systems
7149 * The chip's target access swapping will not swap all accesses
7150 */
7151 pci_write_config_dword(bp->pdev, BNX2_PCICFG_MISC_CONFIG,
7152 BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
7153 BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP);
7154
829ca9a3 7155 bnx2_set_power_state(bp, PCI_D0);
b6016b76
MC		 7156
7157 bp->chip_id = REG_RD(bp, BNX2_MISC_ID);
7158
883e5151
MC		 7159 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
7160 if (pci_find_capability(pdev, PCI_CAP_ID_EXP) == 0) {
7161 dev_err(&pdev->dev,
7162 "Cannot find PCIE capability, aborting.\n");
7163 rc = -EIO;
7164 goto err_out_unmap;
7165 }
f86e82fb 7166 bp->flags |= BNX2_FLAG_PCIE;
2dd201d7 7167 if (CHIP_REV(bp) == CHIP_REV_Ax)
f86e82fb 7168 bp->flags |= BNX2_FLAG_JUMBO_BROKEN;
883e5151 7169 } else {
59b47d8a
MC		 7170 bp->pcix_cap = pci_find_capability(pdev, PCI_CAP_ID_PCIX);
7171 if (bp->pcix_cap == 0) {
7172 dev_err(&pdev->dev,
7173 "Cannot find PCIX capability, aborting.\n");
7174 rc = -EIO;
7175 goto err_out_unmap;
7176 }
7177 }
7178
b4b36042
MC		 7179 if (CHIP_NUM(bp) == CHIP_NUM_5709 && CHIP_REV(bp) != CHIP_REV_Ax) {
7180 if (pci_find_capability(pdev, PCI_CAP_ID_MSIX))
f86e82fb 7181 bp->flags |= BNX2_FLAG_MSIX_CAP;
b4b36042
MC		 7182 }
7183
8e6a72c4
MC		 7184 if (CHIP_ID(bp) != CHIP_ID_5706_A0 && CHIP_ID(bp) != CHIP_ID_5706_A1) {
7185 if (pci_find_capability(pdev, PCI_CAP_ID_MSI))
f86e82fb 7186 bp->flags |= BNX2_FLAG_MSI_CAP;
8e6a72c4
MC		 7187 }
7188
40453c83
MC		 7189 /* 5708 cannot support DMA addresses > 40-bit. */
7190 if (CHIP_NUM(bp) == CHIP_NUM_5708)
7191 persist_dma_mask = dma_mask = DMA_40BIT_MASK;
7192 else
7193 persist_dma_mask = dma_mask = DMA_64BIT_MASK;
7194
7195 /* Configure DMA attributes. */
7196 if (pci_set_dma_mask(pdev, dma_mask) == 0) {
7197 dev->features |= NETIF_F_HIGHDMA;
7198 rc = pci_set_consistent_dma_mask(pdev, persist_dma_mask);
7199 if (rc) {
7200 dev_err(&pdev->dev,
7201 "pci_set_consistent_dma_mask failed, aborting.\n");
7202 goto err_out_unmap;
7203 }
7204 } else if ((rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK)) != 0) {
7205 dev_err(&pdev->dev, "System does not support DMA, aborting.\n");
7206 goto err_out_unmap;
7207 }
7208
f86e82fb 7209 if (!(bp->flags & BNX2_FLAG_PCIE))
883e5151 7210 bnx2_get_pci_speed(bp);
b6016b76
MC		 7211
7212 /* 5706A0 may falsely detect SERR and PERR. */
7213 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
7214 reg = REG_RD(bp, PCI_COMMAND);
7215 reg &= ~(PCI_COMMAND_SERR | PCI_COMMAND_PARITY);
7216 REG_WR(bp, PCI_COMMAND, reg);
7217 }
7218 else if ((CHIP_ID(bp) == CHIP_ID_5706_A1) &&
f86e82fb 7219 !(bp->flags & BNX2_FLAG_PCIX)) {
b6016b76 7220
9b91cf9d 7221 dev_err(&pdev->dev,
2e8a538d 7222 "5706 A1 can only be used in a PCIX bus, aborting.\n");
b6016b76
MC		 7223 goto err_out_unmap;
7224 }
7225
7226 bnx2_init_nvram(bp);
7227
2726d6e1 7228 reg = bnx2_reg_rd_ind(bp, BNX2_SHM_HDR_SIGNATURE);
e3648b3d
MC		 7229
7230 if ((reg & BNX2_SHM_HDR_SIGNATURE_SIG_MASK) ==
24cb230b
MC		 7231 BNX2_SHM_HDR_SIGNATURE_SIG) {
7232 u32 off = PCI_FUNC(pdev->devfn) << 2;
7233
2726d6e1 7234 bp->shmem_base = bnx2_reg_rd_ind(bp, BNX2_SHM_HDR_ADDR_0 + off);
24cb230b 7235 } else
e3648b3d
MC		 7236 bp->shmem_base = HOST_VIEW_SHMEM_BASE;
7237
b6016b76
MC		 7238 /* Get the permanent MAC address. First we need to make sure the
7239 * firmware is actually running.
7240 */
2726d6e1 7241 reg = bnx2_shmem_rd(bp, BNX2_DEV_INFO_SIGNATURE);
b6016b76
MC		 7242
7243 if ((reg & BNX2_DEV_INFO_SIGNATURE_MAGIC_MASK) !=
7244 BNX2_DEV_INFO_SIGNATURE_MAGIC) {
9b91cf9d 7245 dev_err(&pdev->dev, "Firmware not running, aborting.\n");
b6016b76
MC		 7246 rc = -ENODEV;
7247 goto err_out_unmap;
7248 }
7249
2726d6e1 7250 reg = bnx2_shmem_rd(bp, BNX2_DEV_INFO_BC_REV);
58fc2ea4
MC		 7251 for (i = 0, j = 0; i < 3; i++) {
7252 u8 num, k, skip0;
7253
7254 num = (u8) (reg >> (24 - (i * 8)));
7255 for (k = 100, skip0 = 1; k >= 1; num %= k, k /= 10) {
7256 if (num >= k || !skip0 || k == 1) {
7257 bp->fw_version[j++] = (num / k) + '0';
7258 skip0 = 0;
7259 }
7260 }
7261 if (i != 2)
7262 bp->fw_version[j++] = '.';
7263 }
2726d6e1 7264 reg = bnx2_shmem_rd(bp, BNX2_PORT_FEATURE);
846f5c62
MC		 7265 if (reg & BNX2_PORT_FEATURE_WOL_ENABLED)
7266 bp->wol = 1;
7267
7268 if (reg & BNX2_PORT_FEATURE_ASF_ENABLED) {
f86e82fb 7269 bp->flags |= BNX2_FLAG_ASF_ENABLE;
c2d3db8c
MC		 7270
7271 for (i = 0; i < 30; i++) {
2726d6e1 7272 reg = bnx2_shmem_rd(bp, BNX2_BC_STATE_CONDITION);
c2d3db8c
MC		 7273 if (reg & BNX2_CONDITION_MFW_RUN_MASK)
7274 break;
7275 msleep(10);
7276 }
7277 }
2726d6e1 7278 reg = bnx2_shmem_rd(bp, BNX2_BC_STATE_CONDITION);
58fc2ea4
MC		 7279 reg &= BNX2_CONDITION_MFW_RUN_MASK;
7280 if (reg != BNX2_CONDITION_MFW_RUN_UNKNOWN &&
7281 reg != BNX2_CONDITION_MFW_RUN_NONE) {
7282 int i;
2726d6e1 7283 u32 addr = bnx2_shmem_rd(bp, BNX2_MFW_VER_PTR);
58fc2ea4
MC		 7284
7285 bp->fw_version[j++] = ' ';
7286 for (i = 0; i < 3; i++) {
2726d6e1 7287 reg = bnx2_reg_rd_ind(bp, addr + i * 4);
58fc2ea4
MC		 7288 reg = swab32(reg);
7289 memcpy(&bp->fw_version[j], &reg, 4);
7290 j += 4;
7291 }
7292 }
b6016b76 7293
2726d6e1 7294 reg = bnx2_shmem_rd(bp, BNX2_PORT_HW_CFG_MAC_UPPER);
b6016b76
MC		 7295 bp->mac_addr[0] = (u8) (reg >> 8);
7296 bp->mac_addr[1] = (u8) reg;
7297
2726d6e1 7298 reg = bnx2_shmem_rd(bp, BNX2_PORT_HW_CFG_MAC_LOWER);
b6016b76
MC		 7299 bp->mac_addr[2] = (u8) (reg >> 24);
7300 bp->mac_addr[3] = (u8) (reg >> 16);
7301 bp->mac_addr[4] = (u8) (reg >> 8);
7302 bp->mac_addr[5] = (u8) reg;
7303
5d5d0015
MC		 7304 bp->rx_offset = sizeof(struct l2_fhdr) + 2;
7305
b6016b76 7306 bp->tx_ring_size = MAX_TX_DESC_CNT;
932f3772 7307 bnx2_set_rx_ring_size(bp, 255);
b6016b76
MC		 7308
7309 bp->rx_csum = 1;
7310
b6016b76
MC		 7311 bp->tx_quick_cons_trip_int = 20;
7312 bp->tx_quick_cons_trip = 20;
7313 bp->tx_ticks_int = 80;
7314 bp->tx_ticks = 80;
6aa20a22 7315
b6016b76
MC		 7316 bp->rx_quick_cons_trip_int = 6;
7317 bp->rx_quick_cons_trip = 6;
7318 bp->rx_ticks_int = 18;
7319 bp->rx_ticks = 18;
7320
7ea6920e 7321 bp->stats_ticks = USEC_PER_SEC & BNX2_HC_STATS_TICKS_HC_STAT_TICKS;
b6016b76
MC		 7322
7323 bp->timer_interval = HZ;
cd339a0e 7324 bp->current_interval = HZ;
b6016b76 7325
5b0c76ad
MC		 7326 bp->phy_addr = 1;
7327
b6016b76 7328 /* Disable WOL support if we are running on a SERDES chip. */
253c8b75
MC		 7329 if (CHIP_NUM(bp) == CHIP_NUM_5709)
7330 bnx2_get_5709_media(bp);
7331 else if (CHIP_BOND_ID(bp) & CHIP_BOND_ID_SERDES_BIT)
583c28e5 7332 bp->phy_flags |= BNX2_PHY_FLAG_SERDES;
bac0dff6 7333
0d8a6571 7334 bp->phy_port = PORT_TP;
583c28e5 7335 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
0d8a6571 7336 bp->phy_port = PORT_FIBRE;
2726d6e1 7337 reg = bnx2_shmem_rd(bp, BNX2_SHARED_HW_CFG_CONFIG);
846f5c62 7338 if (!(reg & BNX2_SHARED_HW_CFG_GIG_LINK_ON_VAUX)) {
f86e82fb 7339 bp->flags |= BNX2_FLAG_NO_WOL;
846f5c62
MC		 7340 bp->wol = 0;
7341 }
38ea3686
MC		 7342 if (CHIP_NUM(bp) == CHIP_NUM_5706) {
7343 /* Don't do parallel detect on this board because of
7344 * some board problems. The link will not go down
7345 * if we do parallel detect.
7346 */
7347 if (pdev->subsystem_vendor == PCI_VENDOR_ID_HP &&
7348 pdev->subsystem_device == 0x310c)
7349 bp->phy_flags |= BNX2_PHY_FLAG_NO_PARALLEL;
7350 } else {
5b0c76ad 7351 bp->phy_addr = 2;
5b0c76ad 7352 if (reg & BNX2_SHARED_HW_CFG_PHY_2_5G)
583c28e5 7353 bp->phy_flags |= BNX2_PHY_FLAG_2_5G_CAPABLE;
5b0c76ad 7354 }
0d8a6571
MC		 7355 bnx2_init_remote_phy(bp);
7356
261dd5ca
MC		 7357 } else if (CHIP_NUM(bp) == CHIP_NUM_5706 ||
7358 CHIP_NUM(bp) == CHIP_NUM_5708)
583c28e5 7359 bp->phy_flags |= BNX2_PHY_FLAG_CRC_FIX;
fb0c18bd
MC		 7360 else if (CHIP_NUM(bp) == CHIP_NUM_5709 &&
7361 (CHIP_REV(bp) == CHIP_REV_Ax ||
7362 CHIP_REV(bp) == CHIP_REV_Bx))
583c28e5 7363 bp->phy_flags |= BNX2_PHY_FLAG_DIS_EARLY_DAC;
b6016b76 7364
16088272
MC		 7365 if ((CHIP_ID(bp) == CHIP_ID_5708_A0) ||
7366 (CHIP_ID(bp) == CHIP_ID_5708_B0) ||
846f5c62 7367 (CHIP_ID(bp) == CHIP_ID_5708_B1)) {
f86e82fb 7368 bp->flags |= BNX2_FLAG_NO_WOL;
846f5c62
MC		 7369 bp->wol = 0;
7370 }
dda1e390 7371
b6016b76
MC		 7372 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
7373 bp->tx_quick_cons_trip_int =
7374 bp->tx_quick_cons_trip;
7375 bp->tx_ticks_int = bp->tx_ticks;
7376 bp->rx_quick_cons_trip_int =
7377 bp->rx_quick_cons_trip;
7378 bp->rx_ticks_int = bp->rx_ticks;
7379 bp->comp_prod_trip_int = bp->comp_prod_trip;
7380 bp->com_ticks_int = bp->com_ticks;
7381 bp->cmd_ticks_int = bp->cmd_ticks;
7382 }
7383
f9317a40
MC		 7384 /* Disable MSI on 5706 if AMD 8132 bridge is found.
7385 *
7386 * MSI is defined to be 32-bit write. The 5706 does 64-bit MSI writes
7387 * with byte enables disabled on the unused 32-bit word. This is legal
7388 * but causes problems on the AMD 8132 which will eventually stop
7389 * responding after a while.
7390 *
7391 * AMD believes this incompatibility is unique to the 5706, and
88187dfa 7392 * prefers to locally disable MSI rather than globally disabling it.
f9317a40
MC		 7393 */
7394 if (CHIP_NUM(bp) == CHIP_NUM_5706 && disable_msi == 0) {
7395 struct pci_dev *amd_8132 = NULL;
7396
7397 while ((amd_8132 = pci_get_device(PCI_VENDOR_ID_AMD,
7398 PCI_DEVICE_ID_AMD_8132_BRIDGE,
7399 amd_8132))) {
f9317a40 7400
44c10138
AK		 7401 if (amd_8132->revision >= 0x10 &&
7402 amd_8132->revision <= 0x13) {
f9317a40
MC		 7403 disable_msi = 1;
7404 pci_dev_put(amd_8132);
7405 break;
7406 }
7407 }
7408 }
7409
deaf391b 7410 bnx2_set_default_link(bp);
b6016b76
MC		 7411 bp->req_flow_ctrl = FLOW_CTRL_RX | FLOW_CTRL_TX;
7412
cd339a0e
MC		 7413 init_timer(&bp->timer);
7414 bp->timer.expires = RUN_AT(bp->timer_interval);
7415 bp->timer.data = (unsigned long) bp;
7416 bp->timer.function = bnx2_timer;
7417
b6016b76
MC		 7418 return 0;
7419
7420err_out_unmap:
7421 if (bp->regview) {
7422 iounmap(bp->regview);
73eef4cd 7423 bp->regview = NULL;
b6016b76
MC		 7424 }
7425
7426err_out_release:
7427 pci_release_regions(pdev);
7428
7429err_out_disable:
7430 pci_disable_device(pdev);
7431 pci_set_drvdata(pdev, NULL);
7432
7433err_out:
7434 return rc;
7435}
7436
883e5151
MC		 7437static char * __devinit
7438bnx2_bus_string(struct bnx2 *bp, char *str)
7439{
7440 char *s = str;
7441
f86e82fb 7442 if (bp->flags & BNX2_FLAG_PCIE) {
883e5151
MC		 7443 s += sprintf(s, "PCI Express");
7444 } else {
7445 s += sprintf(s, "PCI");
f86e82fb 7446 if (bp->flags & BNX2_FLAG_PCIX)
883e5151 7447 s += sprintf(s, "-X");
f86e82fb 7448 if (bp->flags & BNX2_FLAG_PCI_32BIT)
883e5151
MC		 7449 s += sprintf(s, " 32-bit");
7450 else
7451 s += sprintf(s, " 64-bit");
7452 s += sprintf(s, " %dMHz", bp->bus_speed_mhz);
7453 }
7454 return str;
7455}
7456
2ba582b7 7457static void __devinit
35efa7c1
MC		 7458bnx2_init_napi(struct bnx2 *bp)
7459{
b4b36042
MC		 7460 int i;
7461 struct bnx2_napi *bnapi;
35efa7c1 7462
b4b36042
MC		 7463 for (i = 0; i < BNX2_MAX_MSIX_VEC; i++) {
7464 bnapi = &bp->bnx2_napi[i];
7465 bnapi->bp = bp;
7466 }
7467 netif_napi_add(bp->dev, &bp->bnx2_napi[0].napi, bnx2_poll, 64);
57851d84
MC		 7468 netif_napi_add(bp->dev, &bp->bnx2_napi[BNX2_TX_VEC].napi, bnx2_tx_poll,
7469 64);
35efa7c1
MC		 7470}
7471
b6016b76
MC		 7472static int __devinit
7473bnx2_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
7474{
7475 static int version_printed = 0;
7476 struct net_device *dev = NULL;
7477 struct bnx2 *bp;
0795af57 7478 int rc;
883e5151 7479 char str[40];
0795af57 7480 DECLARE_MAC_BUF(mac);
b6016b76
MC		 7481
7482 if (version_printed++ == 0)
7483 printk(KERN_INFO "%s", version);
7484
7485 /* dev zeroed in init_etherdev */
7486 dev = alloc_etherdev(sizeof(*bp));
7487
7488 if (!dev)
7489 return -ENOMEM;
7490
7491 rc = bnx2_init_board(pdev, dev);
7492 if (rc < 0) {
7493 free_netdev(dev);
7494 return rc;
7495 }
7496
7497 dev->open = bnx2_open;
7498 dev->hard_start_xmit = bnx2_start_xmit;
7499 dev->stop = bnx2_close;
7500 dev->get_stats = bnx2_get_stats;
7501 dev->set_multicast_list = bnx2_set_rx_mode;
7502 dev->do_ioctl = bnx2_ioctl;
7503 dev->set_mac_address = bnx2_change_mac_addr;
7504 dev->change_mtu = bnx2_change_mtu;
7505 dev->tx_timeout = bnx2_tx_timeout;
7506 dev->watchdog_timeo = TX_TIMEOUT;
7507#ifdef BCM_VLAN
7508 dev->vlan_rx_register = bnx2_vlan_rx_register;
b6016b76 7509#endif
b6016b76 7510 dev->ethtool_ops = &bnx2_ethtool_ops;
b6016b76 7511
972ec0d4 7512 bp = netdev_priv(dev);
35efa7c1 7513 bnx2_init_napi(bp);
b6016b76
MC		 7514
7515#if defined(HAVE_POLL_CONTROLLER) || defined(CONFIG_NET_POLL_CONTROLLER)
7516 dev->poll_controller = poll_bnx2;
7517#endif
7518
1b2f922f
MC		 7519 pci_set_drvdata(pdev, dev);
7520
7521 memcpy(dev->dev_addr, bp->mac_addr, 6);
7522 memcpy(dev->perm_addr, bp->mac_addr, 6);
7523 bp->name = board_info[ent->driver_data].name;
7524
d212f87b 7525 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
4666f87a 7526 if (CHIP_NUM(bp) == CHIP_NUM_5709)
d212f87b
SH		 7527 dev->features |= NETIF_F_IPV6_CSUM;
7528
1b2f922f
MC		 7529#ifdef BCM_VLAN
7530 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
7531#endif
7532 dev->features |= NETIF_F_TSO | NETIF_F_TSO_ECN;
4666f87a
MC		 7533 if (CHIP_NUM(bp) == CHIP_NUM_5709)
7534 dev->features |= NETIF_F_TSO6;
1b2f922f 7535
b6016b76 7536 if ((rc = register_netdev(dev))) {
9b91cf9d 7537 dev_err(&pdev->dev, "Cannot register net device\n");
b6016b76
MC		 7538 if (bp->regview)
7539 iounmap(bp->regview);
7540 pci_release_regions(pdev);
7541 pci_disable_device(pdev);
7542 pci_set_drvdata(pdev, NULL);
7543 free_netdev(dev);
7544 return rc;
7545 }
7546
883e5151 7547 printk(KERN_INFO "%s: %s (%c%d) %s found at mem %lx, "
0795af57 7548 "IRQ %d, node addr %s\n",
b6016b76
MC		 7549 dev->name,
7550 bp->name,
7551 ((CHIP_ID(bp) & 0xf000) >> 12) + 'A',
7552 ((CHIP_ID(bp) & 0x0ff0) >> 4),
883e5151 7553 bnx2_bus_string(bp, str),
b6016b76 7554 dev->base_addr,
0795af57 7555 bp->pdev->irq, print_mac(mac, dev->dev_addr));
b6016b76 7556
b6016b76
MC		 7557 return 0;
7558}
7559
7560static void __devexit
7561bnx2_remove_one(struct pci_dev *pdev)
7562{
7563 struct net_device *dev = pci_get_drvdata(pdev);
972ec0d4 7564 struct bnx2 *bp = netdev_priv(dev);
b6016b76 7565
afdc08b9
MC		 7566 flush_scheduled_work();
7567
b6016b76
MC		 7568 unregister_netdev(dev);
7569
7570 if (bp->regview)
7571 iounmap(bp->regview);
7572
7573 free_netdev(dev);
7574 pci_release_regions(pdev);
7575 pci_disable_device(pdev);
7576 pci_set_drvdata(pdev, NULL);
7577}
7578
7579static int
829ca9a3 7580bnx2_suspend(struct pci_dev *pdev, pm_message_t state)
b6016b76
MC		 7581{
7582 struct net_device *dev = pci_get_drvdata(pdev);
972ec0d4 7583 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 7584 u32 reset_code;
7585
6caebb02
MC		 7586 /* PCI register 4 needs to be saved whether netif_running() or not.
7587 * MSI address and data need to be saved if using MSI and
7588 * netif_running().
7589 */
7590 pci_save_state(pdev);
b6016b76
MC		 7591 if (!netif_running(dev))
7592 return 0;
7593
1d60290f 7594 flush_scheduled_work();
b6016b76
MC		 7595 bnx2_netif_stop(bp);
7596 netif_device_detach(dev);
7597 del_timer_sync(&bp->timer);
f86e82fb 7598 if (bp->flags & BNX2_FLAG_NO_WOL)
6c4f095e 7599 reset_code = BNX2_DRV_MSG_CODE_UNLOAD_LNK_DN;
dda1e390 7600 else if (bp->wol)
b6016b76
MC		 7601 reset_code = BNX2_DRV_MSG_CODE_SUSPEND_WOL;
7602 else
7603 reset_code = BNX2_DRV_MSG_CODE_SUSPEND_NO_WOL;
7604 bnx2_reset_chip(bp, reset_code);
7605 bnx2_free_skbs(bp);
829ca9a3 7606 bnx2_set_power_state(bp, pci_choose_state(pdev, state));
b6016b76
MC		 7607 return 0;
7608}
7609
7610static int
7611bnx2_resume(struct pci_dev *pdev)
7612{
7613 struct net_device *dev = pci_get_drvdata(pdev);
972ec0d4 7614 struct bnx2 *bp = netdev_priv(dev);
b6016b76 7615
6caebb02 7616 pci_restore_state(pdev);
b6016b76
MC		 7617 if (!netif_running(dev))
7618 return 0;
7619
829ca9a3 7620 bnx2_set_power_state(bp, PCI_D0);
b6016b76
MC		 7621 netif_device_attach(dev);
7622 bnx2_init_nic(bp);
7623 bnx2_netif_start(bp);
7624 return 0;
7625}
7626
7627static struct pci_driver bnx2_pci_driver = {
14ab9b86
PH		 7628 .name = DRV_MODULE_NAME,
7629 .id_table = bnx2_pci_tbl,
7630 .probe = bnx2_init_one,
7631 .remove = __devexit_p(bnx2_remove_one),
7632 .suspend = bnx2_suspend,
7633 .resume = bnx2_resume,
b6016b76
MC		 7634};
7635
7636static int __init bnx2_init(void)
7637{
29917620 7638 return pci_register_driver(&bnx2_pci_driver);
b6016b76
MC		 7639}
7640
7641static void __exit bnx2_cleanup(void)
7642{
7643 pci_unregister_driver(&bnx2_pci_driver);
7644}
7645
7646module_init(bnx2_init);
7647module_exit(bnx2_cleanup);
7648
7649
7650
Linux kernel - Deliverables
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