Commit | Line | Data |
---|---|---|
a2fbb9ea ET |
1 | /* bnx2x.h: Broadcom Everest network driver. |
2 | * | |
3359fced | 3 | * Copyright (c) 2007-2010 Broadcom Corporation |
a2fbb9ea ET |
4 | * |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License as published by | |
7 | * the Free Software Foundation. | |
8 | * | |
24e3fcef EG |
9 | * Maintained by: Eilon Greenstein <eilong@broadcom.com> |
10 | * Written by: Eliezer Tamir | |
a2fbb9ea ET |
11 | * Based on code from Michael Chan's bnx2 driver |
12 | */ | |
13 | ||
14 | #ifndef BNX2X_H | |
15 | #define BNX2X_H | |
16 | ||
34f80b04 EG |
17 | /* compilation time flags */ |
18 | ||
19 | /* define this to make the driver freeze on error to allow getting debug info | |
20 | * (you will need to reboot afterwards) */ | |
21 | /* #define BNX2X_STOP_ON_ERROR */ | |
22 | ||
0793f83f DK |
23 | #define DRV_MODULE_VERSION "1.60.00-6" |
24 | #define DRV_MODULE_RELDATE "2010/11/29" | |
de0c62db DK |
25 | #define BNX2X_BC_VER 0x040200 |
26 | ||
1ac218c8 VZ |
27 | #define BNX2X_MULTI_QUEUE |
28 | ||
29 | #define BNX2X_NEW_NAPI | |
30 | ||
31 | ||
993ac7b5 MC |
32 | #if defined(CONFIG_CNIC) || defined(CONFIG_CNIC_MODULE) |
33 | #define BCM_CNIC 1 | |
5d1e859c | 34 | #include "../cnic_if.h" |
993ac7b5 | 35 | #endif |
0c6671b0 | 36 | |
1ac218c8 VZ |
37 | #ifdef BCM_CNIC |
38 | #define BNX2X_MIN_MSIX_VEC_CNT 3 | |
39 | #define BNX2X_MSIX_VEC_FP_START 2 | |
40 | #else | |
41 | #define BNX2X_MIN_MSIX_VEC_CNT 2 | |
42 | #define BNX2X_MSIX_VEC_FP_START 1 | |
43 | #endif | |
01cd4528 EG |
44 | |
45 | #include <linux/mdio.h> | |
9f6c9258 | 46 | #include <linux/pci.h> |
359d8b15 EG |
47 | #include "bnx2x_reg.h" |
48 | #include "bnx2x_fw_defs.h" | |
49 | #include "bnx2x_hsi.h" | |
50 | #include "bnx2x_link.h" | |
6c719d00 | 51 | #include "bnx2x_stats.h" |
359d8b15 | 52 | |
a2fbb9ea ET |
53 | /* error/debug prints */ |
54 | ||
34f80b04 | 55 | #define DRV_MODULE_NAME "bnx2x" |
a2fbb9ea ET |
56 | |
57 | /* for messages that are currently off */ | |
34f80b04 EG |
58 | #define BNX2X_MSG_OFF 0 |
59 | #define BNX2X_MSG_MCP 0x010000 /* was: NETIF_MSG_HW */ | |
60 | #define BNX2X_MSG_STATS 0x020000 /* was: NETIF_MSG_TIMER */ | |
61 | #define BNX2X_MSG_NVM 0x040000 /* was: NETIF_MSG_HW */ | |
62 | #define BNX2X_MSG_DMAE 0x080000 /* was: NETIF_MSG_HW */ | |
f1410647 ET |
63 | #define BNX2X_MSG_SP 0x100000 /* was: NETIF_MSG_INTR */ |
64 | #define BNX2X_MSG_FP 0x200000 /* was: NETIF_MSG_INTR */ | |
a2fbb9ea | 65 | |
34f80b04 | 66 | #define DP_LEVEL KERN_NOTICE /* was: KERN_DEBUG */ |
a2fbb9ea ET |
67 | |
68 | /* regular debug print */ | |
7995c64e JP |
69 | #define DP(__mask, __fmt, __args...) \ |
70 | do { \ | |
71 | if (bp->msg_enable & (__mask)) \ | |
72 | printk(DP_LEVEL "[%s:%d(%s)]" __fmt, \ | |
73 | __func__, __LINE__, \ | |
74 | bp->dev ? (bp->dev->name) : "?", \ | |
75 | ##__args); \ | |
76 | } while (0) | |
a2fbb9ea | 77 | |
34f80b04 | 78 | /* errors debug print */ |
7995c64e JP |
79 | #define BNX2X_DBG_ERR(__fmt, __args...) \ |
80 | do { \ | |
81 | if (netif_msg_probe(bp)) \ | |
82 | pr_err("[%s:%d(%s)]" __fmt, \ | |
83 | __func__, __LINE__, \ | |
84 | bp->dev ? (bp->dev->name) : "?", \ | |
85 | ##__args); \ | |
86 | } while (0) | |
a2fbb9ea | 87 | |
34f80b04 | 88 | /* for errors (never masked) */ |
7995c64e JP |
89 | #define BNX2X_ERR(__fmt, __args...) \ |
90 | do { \ | |
91 | pr_err("[%s:%d(%s)]" __fmt, \ | |
92 | __func__, __LINE__, \ | |
93 | bp->dev ? (bp->dev->name) : "?", \ | |
94 | ##__args); \ | |
cdaa7cb8 VZ |
95 | } while (0) |
96 | ||
97 | #define BNX2X_ERROR(__fmt, __args...) do { \ | |
98 | pr_err("[%s:%d]" __fmt, __func__, __LINE__, ##__args); \ | |
99 | } while (0) | |
100 | ||
f1410647 | 101 | |
a2fbb9ea | 102 | /* before we have a dev->name use dev_info() */ |
7995c64e JP |
103 | #define BNX2X_DEV_INFO(__fmt, __args...) \ |
104 | do { \ | |
105 | if (netif_msg_probe(bp)) \ | |
106 | dev_info(&bp->pdev->dev, __fmt, ##__args); \ | |
107 | } while (0) | |
a2fbb9ea | 108 | |
6c719d00 | 109 | void bnx2x_panic_dump(struct bnx2x *bp); |
a2fbb9ea ET |
110 | |
111 | #ifdef BNX2X_STOP_ON_ERROR | |
112 | #define bnx2x_panic() do { \ | |
113 | bp->panic = 1; \ | |
114 | BNX2X_ERR("driver assert\n"); \ | |
34f80b04 | 115 | bnx2x_int_disable(bp); \ |
a2fbb9ea ET |
116 | bnx2x_panic_dump(bp); \ |
117 | } while (0) | |
118 | #else | |
119 | #define bnx2x_panic() do { \ | |
e3553b29 | 120 | bp->panic = 1; \ |
a2fbb9ea ET |
121 | BNX2X_ERR("driver assert\n"); \ |
122 | bnx2x_panic_dump(bp); \ | |
123 | } while (0) | |
124 | #endif | |
125 | ||
523224a3 | 126 | #define bnx2x_mc_addr(ha) ((ha)->addr) |
a2fbb9ea | 127 | |
34f80b04 EG |
128 | #define U64_LO(x) (u32)(((u64)(x)) & 0xffffffff) |
129 | #define U64_HI(x) (u32)(((u64)(x)) >> 32) | |
130 | #define HILO_U64(hi, lo) ((((u64)(hi)) << 32) + (lo)) | |
a2fbb9ea | 131 | |
a2fbb9ea | 132 | |
523224a3 | 133 | #define REG_ADDR(bp, offset) ((bp->regview) + (offset)) |
a2fbb9ea | 134 | |
34f80b04 EG |
135 | #define REG_RD(bp, offset) readl(REG_ADDR(bp, offset)) |
136 | #define REG_RD8(bp, offset) readb(REG_ADDR(bp, offset)) | |
523224a3 | 137 | #define REG_RD16(bp, offset) readw(REG_ADDR(bp, offset)) |
34f80b04 EG |
138 | |
139 | #define REG_WR(bp, offset, val) writel((u32)val, REG_ADDR(bp, offset)) | |
a2fbb9ea | 140 | #define REG_WR8(bp, offset, val) writeb((u8)val, REG_ADDR(bp, offset)) |
34f80b04 | 141 | #define REG_WR16(bp, offset, val) writew((u16)val, REG_ADDR(bp, offset)) |
a2fbb9ea | 142 | |
34f80b04 EG |
143 | #define REG_RD_IND(bp, offset) bnx2x_reg_rd_ind(bp, offset) |
144 | #define REG_WR_IND(bp, offset, val) bnx2x_reg_wr_ind(bp, offset, val) | |
a2fbb9ea | 145 | |
c18487ee YR |
146 | #define REG_RD_DMAE(bp, offset, valp, len32) \ |
147 | do { \ | |
148 | bnx2x_read_dmae(bp, offset, len32);\ | |
573f2035 | 149 | memcpy(valp, bnx2x_sp(bp, wb_data[0]), (len32) * 4); \ |
c18487ee YR |
150 | } while (0) |
151 | ||
34f80b04 | 152 | #define REG_WR_DMAE(bp, offset, valp, len32) \ |
a2fbb9ea | 153 | do { \ |
573f2035 | 154 | memcpy(bnx2x_sp(bp, wb_data[0]), valp, (len32) * 4); \ |
a2fbb9ea ET |
155 | bnx2x_write_dmae(bp, bnx2x_sp_mapping(bp, wb_data), \ |
156 | offset, len32); \ | |
157 | } while (0) | |
158 | ||
523224a3 DK |
159 | #define REG_WR_DMAE_LEN(bp, offset, valp, len32) \ |
160 | REG_WR_DMAE(bp, offset, valp, len32) | |
161 | ||
3359fced | 162 | #define VIRT_WR_DMAE_LEN(bp, data, addr, len32, le32_swap) \ |
573f2035 EG |
163 | do { \ |
164 | memcpy(GUNZIP_BUF(bp), data, (len32) * 4); \ | |
165 | bnx2x_write_big_buf_wb(bp, addr, len32); \ | |
166 | } while (0) | |
167 | ||
34f80b04 EG |
168 | #define SHMEM_ADDR(bp, field) (bp->common.shmem_base + \ |
169 | offsetof(struct shmem_region, field)) | |
170 | #define SHMEM_RD(bp, field) REG_RD(bp, SHMEM_ADDR(bp, field)) | |
171 | #define SHMEM_WR(bp, field, val) REG_WR(bp, SHMEM_ADDR(bp, field), val) | |
a2fbb9ea | 172 | |
2691d51d EG |
173 | #define SHMEM2_ADDR(bp, field) (bp->common.shmem2_base + \ |
174 | offsetof(struct shmem2_region, field)) | |
175 | #define SHMEM2_RD(bp, field) REG_RD(bp, SHMEM2_ADDR(bp, field)) | |
176 | #define SHMEM2_WR(bp, field, val) REG_WR(bp, SHMEM2_ADDR(bp, field), val) | |
523224a3 DK |
177 | #define MF_CFG_ADDR(bp, field) (bp->common.mf_cfg_base + \ |
178 | offsetof(struct mf_cfg, field)) | |
f85582f8 | 179 | #define MF2_CFG_ADDR(bp, field) (bp->common.mf2_cfg_base + \ |
f2e0899f | 180 | offsetof(struct mf2_cfg, field)) |
2691d51d | 181 | |
523224a3 DK |
182 | #define MF_CFG_RD(bp, field) REG_RD(bp, MF_CFG_ADDR(bp, field)) |
183 | #define MF_CFG_WR(bp, field, val) REG_WR(bp,\ | |
184 | MF_CFG_ADDR(bp, field), (val)) | |
f2e0899f | 185 | #define MF2_CFG_RD(bp, field) REG_RD(bp, MF2_CFG_ADDR(bp, field)) |
f85582f8 | 186 | |
f2e0899f DK |
187 | #define SHMEM2_HAS(bp, field) ((bp)->common.shmem2_base && \ |
188 | (SHMEM2_RD((bp), size) > \ | |
189 | offsetof(struct shmem2_region, field))) | |
72fd0718 | 190 | |
345b5d52 | 191 | #define EMAC_RD(bp, reg) REG_RD(bp, emac_base + reg) |
3196a88a | 192 | #define EMAC_WR(bp, reg, val) REG_WR(bp, emac_base + reg, val) |
a2fbb9ea | 193 | |
523224a3 DK |
194 | /* SP SB indices */ |
195 | ||
196 | /* General SP events - stats query, cfc delete, etc */ | |
197 | #define HC_SP_INDEX_ETH_DEF_CONS 3 | |
198 | ||
199 | /* EQ completions */ | |
200 | #define HC_SP_INDEX_EQ_CONS 7 | |
201 | ||
202 | /* iSCSI L2 */ | |
203 | #define HC_SP_INDEX_ETH_ISCSI_CQ_CONS 5 | |
204 | #define HC_SP_INDEX_ETH_ISCSI_RX_CQ_CONS 1 | |
205 | ||
206 | /** | |
207 | * CIDs and CLIDs: | |
208 | * CLIDs below is a CLID for func 0, then the CLID for other | |
209 | * functions will be calculated by the formula: | |
210 | * | |
211 | * FUNC_N_CLID_X = N * NUM_SPECIAL_CLIENTS + FUNC_0_CLID_X | |
212 | * | |
213 | */ | |
214 | /* iSCSI L2 */ | |
215 | #define BNX2X_ISCSI_ETH_CL_ID 17 | |
216 | #define BNX2X_ISCSI_ETH_CID 17 | |
217 | ||
218 | /** Additional rings budgeting */ | |
219 | #ifdef BCM_CNIC | |
220 | #define CNIC_CONTEXT_USE 1 | |
221 | #else | |
222 | #define CNIC_CONTEXT_USE 0 | |
223 | #endif /* BCM_CNIC */ | |
224 | ||
72fd0718 VZ |
225 | #define AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR \ |
226 | AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR | |
227 | ||
523224a3 DK |
228 | #define SM_RX_ID 0 |
229 | #define SM_TX_ID 1 | |
a2fbb9ea | 230 | |
7a9b2557 | 231 | /* fast path */ |
a2fbb9ea | 232 | |
a2fbb9ea | 233 | struct sw_rx_bd { |
34f80b04 | 234 | struct sk_buff *skb; |
1a983142 | 235 | DEFINE_DMA_UNMAP_ADDR(mapping); |
a2fbb9ea ET |
236 | }; |
237 | ||
238 | struct sw_tx_bd { | |
34f80b04 EG |
239 | struct sk_buff *skb; |
240 | u16 first_bd; | |
ca00392c EG |
241 | u8 flags; |
242 | /* Set on the first BD descriptor when there is a split BD */ | |
243 | #define BNX2X_TSO_SPLIT_BD (1<<0) | |
a2fbb9ea ET |
244 | }; |
245 | ||
7a9b2557 VZ |
246 | struct sw_rx_page { |
247 | struct page *page; | |
1a983142 | 248 | DEFINE_DMA_UNMAP_ADDR(mapping); |
7a9b2557 VZ |
249 | }; |
250 | ||
ca00392c EG |
251 | union db_prod { |
252 | struct doorbell_set_prod data; | |
253 | u32 raw; | |
254 | }; | |
255 | ||
7a9b2557 VZ |
256 | |
257 | /* MC hsi */ | |
258 | #define BCM_PAGE_SHIFT 12 | |
259 | #define BCM_PAGE_SIZE (1 << BCM_PAGE_SHIFT) | |
260 | #define BCM_PAGE_MASK (~(BCM_PAGE_SIZE - 1)) | |
261 | #define BCM_PAGE_ALIGN(addr) (((addr) + BCM_PAGE_SIZE - 1) & BCM_PAGE_MASK) | |
262 | ||
263 | #define PAGES_PER_SGE_SHIFT 0 | |
264 | #define PAGES_PER_SGE (1 << PAGES_PER_SGE_SHIFT) | |
4f40f2cb EG |
265 | #define SGE_PAGE_SIZE PAGE_SIZE |
266 | #define SGE_PAGE_SHIFT PAGE_SHIFT | |
5b6402d1 | 267 | #define SGE_PAGE_ALIGN(addr) PAGE_ALIGN((typeof(PAGE_SIZE))(addr)) |
7a9b2557 VZ |
268 | |
269 | /* SGE ring related macros */ | |
270 | #define NUM_RX_SGE_PAGES 2 | |
271 | #define RX_SGE_CNT (BCM_PAGE_SIZE / sizeof(struct eth_rx_sge)) | |
272 | #define MAX_RX_SGE_CNT (RX_SGE_CNT - 2) | |
33471629 | 273 | /* RX_SGE_CNT is promised to be a power of 2 */ |
7a9b2557 VZ |
274 | #define RX_SGE_MASK (RX_SGE_CNT - 1) |
275 | #define NUM_RX_SGE (RX_SGE_CNT * NUM_RX_SGE_PAGES) | |
276 | #define MAX_RX_SGE (NUM_RX_SGE - 1) | |
277 | #define NEXT_SGE_IDX(x) ((((x) & RX_SGE_MASK) == \ | |
278 | (MAX_RX_SGE_CNT - 1)) ? (x) + 3 : (x) + 1) | |
279 | #define RX_SGE(x) ((x) & MAX_RX_SGE) | |
280 | ||
281 | /* SGE producer mask related macros */ | |
282 | /* Number of bits in one sge_mask array element */ | |
283 | #define RX_SGE_MASK_ELEM_SZ 64 | |
284 | #define RX_SGE_MASK_ELEM_SHIFT 6 | |
285 | #define RX_SGE_MASK_ELEM_MASK ((u64)RX_SGE_MASK_ELEM_SZ - 1) | |
286 | ||
287 | /* Creates a bitmask of all ones in less significant bits. | |
288 | idx - index of the most significant bit in the created mask */ | |
289 | #define RX_SGE_ONES_MASK(idx) \ | |
290 | (((u64)0x1 << (((idx) & RX_SGE_MASK_ELEM_MASK) + 1)) - 1) | |
291 | #define RX_SGE_MASK_ELEM_ONE_MASK ((u64)(~0)) | |
292 | ||
293 | /* Number of u64 elements in SGE mask array */ | |
294 | #define RX_SGE_MASK_LEN ((NUM_RX_SGE_PAGES * RX_SGE_CNT) / \ | |
295 | RX_SGE_MASK_ELEM_SZ) | |
296 | #define RX_SGE_MASK_LEN_MASK (RX_SGE_MASK_LEN - 1) | |
297 | #define NEXT_SGE_MASK_ELEM(el) (((el) + 1) & RX_SGE_MASK_LEN_MASK) | |
298 | ||
523224a3 DK |
299 | union host_hc_status_block { |
300 | /* pointer to fp status block e1x */ | |
301 | struct host_hc_status_block_e1x *e1x_sb; | |
f2e0899f DK |
302 | /* pointer to fp status block e2 */ |
303 | struct host_hc_status_block_e2 *e2_sb; | |
523224a3 | 304 | }; |
7a9b2557 | 305 | |
a2fbb9ea ET |
306 | struct bnx2x_fastpath { |
307 | ||
d6214d7a | 308 | #define BNX2X_NAPI_WEIGHT 128 |
34f80b04 | 309 | struct napi_struct napi; |
f85582f8 | 310 | union host_hc_status_block status_blk; |
523224a3 DK |
311 | /* chip independed shortcuts into sb structure */ |
312 | __le16 *sb_index_values; | |
313 | __le16 *sb_running_index; | |
314 | /* chip independed shortcut into rx_prods_offset memory */ | |
315 | u32 ustorm_rx_prods_offset; | |
316 | ||
34f80b04 | 317 | dma_addr_t status_blk_mapping; |
a2fbb9ea | 318 | |
34f80b04 | 319 | struct sw_tx_bd *tx_buf_ring; |
a2fbb9ea | 320 | |
ca00392c | 321 | union eth_tx_bd_types *tx_desc_ring; |
34f80b04 | 322 | dma_addr_t tx_desc_mapping; |
a2fbb9ea | 323 | |
7a9b2557 VZ |
324 | struct sw_rx_bd *rx_buf_ring; /* BDs mappings ring */ |
325 | struct sw_rx_page *rx_page_ring; /* SGE pages mappings ring */ | |
a2fbb9ea ET |
326 | |
327 | struct eth_rx_bd *rx_desc_ring; | |
34f80b04 | 328 | dma_addr_t rx_desc_mapping; |
a2fbb9ea ET |
329 | |
330 | union eth_rx_cqe *rx_comp_ring; | |
34f80b04 EG |
331 | dma_addr_t rx_comp_mapping; |
332 | ||
7a9b2557 VZ |
333 | /* SGE ring */ |
334 | struct eth_rx_sge *rx_sge_ring; | |
335 | dma_addr_t rx_sge_mapping; | |
336 | ||
337 | u64 sge_mask[RX_SGE_MASK_LEN]; | |
338 | ||
34f80b04 EG |
339 | int state; |
340 | #define BNX2X_FP_STATE_CLOSED 0 | |
341 | #define BNX2X_FP_STATE_IRQ 0x80000 | |
342 | #define BNX2X_FP_STATE_OPENING 0x90000 | |
343 | #define BNX2X_FP_STATE_OPEN 0xa0000 | |
344 | #define BNX2X_FP_STATE_HALTING 0xb0000 | |
345 | #define BNX2X_FP_STATE_HALTED 0xc0000 | |
523224a3 DK |
346 | #define BNX2X_FP_STATE_TERMINATING 0xd0000 |
347 | #define BNX2X_FP_STATE_TERMINATED 0xe0000 | |
34f80b04 | 348 | |
f85582f8 DK |
349 | u8 index; /* number in fp array */ |
350 | u8 cl_id; /* eth client id */ | |
523224a3 DK |
351 | u8 cl_qzone_id; |
352 | u8 fw_sb_id; /* status block number in FW */ | |
353 | u8 igu_sb_id; /* status block number in HW */ | |
354 | u32 cid; | |
34f80b04 | 355 | |
ca00392c EG |
356 | union db_prod tx_db; |
357 | ||
34f80b04 EG |
358 | u16 tx_pkt_prod; |
359 | u16 tx_pkt_cons; | |
360 | u16 tx_bd_prod; | |
361 | u16 tx_bd_cons; | |
4781bfad | 362 | __le16 *tx_cons_sb; |
34f80b04 | 363 | |
523224a3 | 364 | __le16 fp_hc_idx; |
34f80b04 EG |
365 | |
366 | u16 rx_bd_prod; | |
367 | u16 rx_bd_cons; | |
368 | u16 rx_comp_prod; | |
369 | u16 rx_comp_cons; | |
7a9b2557 VZ |
370 | u16 rx_sge_prod; |
371 | /* The last maximal completed SGE */ | |
372 | u16 last_max_sge; | |
4781bfad | 373 | __le16 *rx_cons_sb; |
523224a3 | 374 | |
34f80b04 | 375 | unsigned long tx_pkt, |
a2fbb9ea | 376 | rx_pkt, |
66e855f3 | 377 | rx_calls; |
ab6ad5a4 | 378 | |
7a9b2557 VZ |
379 | /* TPA related */ |
380 | struct sw_rx_bd tpa_pool[ETH_MAX_AGGREGATION_QUEUES_E1H]; | |
381 | u8 tpa_state[ETH_MAX_AGGREGATION_QUEUES_E1H]; | |
382 | #define BNX2X_TPA_START 1 | |
383 | #define BNX2X_TPA_STOP 2 | |
384 | u8 disable_tpa; | |
385 | #ifdef BNX2X_STOP_ON_ERROR | |
386 | u64 tpa_queue_used; | |
387 | #endif | |
a2fbb9ea | 388 | |
de832a55 EG |
389 | struct tstorm_per_client_stats old_tclient; |
390 | struct ustorm_per_client_stats old_uclient; | |
391 | struct xstorm_per_client_stats old_xclient; | |
392 | struct bnx2x_eth_q_stats eth_q_stats; | |
393 | ||
ca00392c EG |
394 | /* The size is calculated using the following: |
395 | sizeof name field from netdev structure + | |
396 | 4 ('-Xx-' string) + | |
397 | 4 (for the digits and to make it DWORD aligned) */ | |
398 | #define FP_NAME_SIZE (sizeof(((struct net_device *)0)->name) + 8) | |
399 | char name[FP_NAME_SIZE]; | |
34f80b04 | 400 | struct bnx2x *bp; /* parent */ |
a2fbb9ea ET |
401 | }; |
402 | ||
34f80b04 | 403 | #define bnx2x_fp(bp, nr, var) (bp->fp[nr].var) |
7a9b2557 VZ |
404 | |
405 | ||
406 | /* MC hsi */ | |
407 | #define MAX_FETCH_BD 13 /* HW max BDs per packet */ | |
408 | #define RX_COPY_THRESH 92 | |
409 | ||
410 | #define NUM_TX_RINGS 16 | |
ca00392c | 411 | #define TX_DESC_CNT (BCM_PAGE_SIZE / sizeof(union eth_tx_bd_types)) |
7a9b2557 VZ |
412 | #define MAX_TX_DESC_CNT (TX_DESC_CNT - 1) |
413 | #define NUM_TX_BD (TX_DESC_CNT * NUM_TX_RINGS) | |
414 | #define MAX_TX_BD (NUM_TX_BD - 1) | |
415 | #define MAX_TX_AVAIL (MAX_TX_DESC_CNT * NUM_TX_RINGS - 2) | |
523224a3 DK |
416 | #define INIT_JUMBO_TX_RING_SIZE MAX_TX_AVAIL |
417 | #define INIT_TX_RING_SIZE MAX_TX_AVAIL | |
7a9b2557 VZ |
418 | #define NEXT_TX_IDX(x) ((((x) & MAX_TX_DESC_CNT) == \ |
419 | (MAX_TX_DESC_CNT - 1)) ? (x) + 2 : (x) + 1) | |
420 | #define TX_BD(x) ((x) & MAX_TX_BD) | |
421 | #define TX_BD_POFF(x) ((x) & MAX_TX_DESC_CNT) | |
422 | ||
423 | /* The RX BD ring is special, each bd is 8 bytes but the last one is 16 */ | |
424 | #define NUM_RX_RINGS 8 | |
425 | #define RX_DESC_CNT (BCM_PAGE_SIZE / sizeof(struct eth_rx_bd)) | |
426 | #define MAX_RX_DESC_CNT (RX_DESC_CNT - 2) | |
427 | #define RX_DESC_MASK (RX_DESC_CNT - 1) | |
428 | #define NUM_RX_BD (RX_DESC_CNT * NUM_RX_RINGS) | |
429 | #define MAX_RX_BD (NUM_RX_BD - 1) | |
430 | #define MAX_RX_AVAIL (MAX_RX_DESC_CNT * NUM_RX_RINGS - 2) | |
25141580 | 431 | #define MIN_RX_AVAIL 128 |
523224a3 DK |
432 | #define INIT_JUMBO_RX_RING_SIZE MAX_RX_AVAIL |
433 | #define INIT_RX_RING_SIZE MAX_RX_AVAIL | |
7a9b2557 VZ |
434 | #define NEXT_RX_IDX(x) ((((x) & RX_DESC_MASK) == \ |
435 | (MAX_RX_DESC_CNT - 1)) ? (x) + 3 : (x) + 1) | |
436 | #define RX_BD(x) ((x) & MAX_RX_BD) | |
437 | ||
438 | /* As long as CQE is 4 times bigger than BD entry we have to allocate | |
439 | 4 times more pages for CQ ring in order to keep it balanced with | |
440 | BD ring */ | |
441 | #define NUM_RCQ_RINGS (NUM_RX_RINGS * 4) | |
442 | #define RCQ_DESC_CNT (BCM_PAGE_SIZE / sizeof(union eth_rx_cqe)) | |
443 | #define MAX_RCQ_DESC_CNT (RCQ_DESC_CNT - 1) | |
444 | #define NUM_RCQ_BD (RCQ_DESC_CNT * NUM_RCQ_RINGS) | |
445 | #define MAX_RCQ_BD (NUM_RCQ_BD - 1) | |
446 | #define MAX_RCQ_AVAIL (MAX_RCQ_DESC_CNT * NUM_RCQ_RINGS - 2) | |
447 | #define NEXT_RCQ_IDX(x) ((((x) & MAX_RCQ_DESC_CNT) == \ | |
448 | (MAX_RCQ_DESC_CNT - 1)) ? (x) + 2 : (x) + 1) | |
449 | #define RCQ_BD(x) ((x) & MAX_RCQ_BD) | |
450 | ||
451 | ||
33471629 | 452 | /* This is needed for determining of last_max */ |
34f80b04 | 453 | #define SUB_S16(a, b) (s16)((s16)(a) - (s16)(b)) |
a2fbb9ea | 454 | |
7a9b2557 VZ |
455 | #define __SGE_MASK_SET_BIT(el, bit) \ |
456 | do { \ | |
457 | el = ((el) | ((u64)0x1 << (bit))); \ | |
458 | } while (0) | |
459 | ||
460 | #define __SGE_MASK_CLEAR_BIT(el, bit) \ | |
461 | do { \ | |
462 | el = ((el) & (~((u64)0x1 << (bit)))); \ | |
463 | } while (0) | |
464 | ||
465 | #define SGE_MASK_SET_BIT(fp, idx) \ | |
466 | __SGE_MASK_SET_BIT(fp->sge_mask[(idx) >> RX_SGE_MASK_ELEM_SHIFT], \ | |
467 | ((idx) & RX_SGE_MASK_ELEM_MASK)) | |
468 | ||
469 | #define SGE_MASK_CLEAR_BIT(fp, idx) \ | |
470 | __SGE_MASK_CLEAR_BIT(fp->sge_mask[(idx) >> RX_SGE_MASK_ELEM_SHIFT], \ | |
471 | ((idx) & RX_SGE_MASK_ELEM_MASK)) | |
472 | ||
473 | ||
474 | /* used on a CID received from the HW */ | |
475 | #define SW_CID(x) (le32_to_cpu(x) & \ | |
476 | (COMMON_RAMROD_ETH_RX_CQE_CID >> 7)) | |
477 | #define CQE_CMD(x) (le32_to_cpu(x) >> \ | |
478 | COMMON_RAMROD_ETH_RX_CQE_CMD_ID_SHIFT) | |
479 | ||
bb2a0f7a YG |
480 | #define BD_UNMAP_ADDR(bd) HILO_U64(le32_to_cpu((bd)->addr_hi), \ |
481 | le32_to_cpu((bd)->addr_lo)) | |
482 | #define BD_UNMAP_LEN(bd) (le16_to_cpu((bd)->nbytes)) | |
483 | ||
523224a3 DK |
484 | #define BNX2X_DB_MIN_SHIFT 3 /* 8 bytes */ |
485 | #define BNX2X_DB_SHIFT 7 /* 128 bytes*/ | |
7a9b2557 VZ |
486 | #define DPM_TRIGER_TYPE 0x40 |
487 | #define DOORBELL(bp, cid, val) \ | |
488 | do { \ | |
523224a3 | 489 | writel((u32)(val), bp->doorbells + (bp->db_size * (cid)) + \ |
7a9b2557 VZ |
490 | DPM_TRIGER_TYPE); \ |
491 | } while (0) | |
492 | ||
493 | ||
494 | /* TX CSUM helpers */ | |
495 | #define SKB_CS_OFF(skb) (offsetof(struct tcphdr, check) - \ | |
496 | skb->csum_offset) | |
497 | #define SKB_CS(skb) (*(u16 *)(skb_transport_header(skb) + \ | |
498 | skb->csum_offset)) | |
499 | ||
500 | #define pbd_tcp_flags(skb) (ntohl(tcp_flag_word(tcp_hdr(skb)))>>16 & 0xff) | |
501 | ||
502 | #define XMIT_PLAIN 0 | |
503 | #define XMIT_CSUM_V4 0x1 | |
504 | #define XMIT_CSUM_V6 0x2 | |
505 | #define XMIT_CSUM_TCP 0x4 | |
506 | #define XMIT_GSO_V4 0x8 | |
507 | #define XMIT_GSO_V6 0x10 | |
508 | ||
509 | #define XMIT_CSUM (XMIT_CSUM_V4 | XMIT_CSUM_V6) | |
510 | #define XMIT_GSO (XMIT_GSO_V4 | XMIT_GSO_V6) | |
511 | ||
512 | ||
34f80b04 | 513 | /* stuff added to make the code fit 80Col */ |
a2fbb9ea | 514 | |
34f80b04 | 515 | #define CQE_TYPE(cqe_fp_flags) ((cqe_fp_flags) & ETH_FAST_PATH_RX_CQE_TYPE) |
a2fbb9ea | 516 | |
7a9b2557 VZ |
517 | #define TPA_TYPE_START ETH_FAST_PATH_RX_CQE_START_FLG |
518 | #define TPA_TYPE_END ETH_FAST_PATH_RX_CQE_END_FLG | |
519 | #define TPA_TYPE(cqe_fp_flags) ((cqe_fp_flags) & \ | |
520 | (TPA_TYPE_START | TPA_TYPE_END)) | |
521 | ||
1adcd8be EG |
522 | #define ETH_RX_ERROR_FALGS ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG |
523 | ||
524 | #define BNX2X_IP_CSUM_ERR(cqe) \ | |
525 | (!((cqe)->fast_path_cqe.status_flags & \ | |
526 | ETH_FAST_PATH_RX_CQE_IP_XSUM_NO_VALIDATION_FLG) && \ | |
527 | ((cqe)->fast_path_cqe.type_error_flags & \ | |
528 | ETH_FAST_PATH_RX_CQE_IP_BAD_XSUM_FLG)) | |
529 | ||
530 | #define BNX2X_L4_CSUM_ERR(cqe) \ | |
531 | (!((cqe)->fast_path_cqe.status_flags & \ | |
532 | ETH_FAST_PATH_RX_CQE_L4_XSUM_NO_VALIDATION_FLG) && \ | |
533 | ((cqe)->fast_path_cqe.type_error_flags & \ | |
534 | ETH_FAST_PATH_RX_CQE_L4_BAD_XSUM_FLG)) | |
535 | ||
536 | #define BNX2X_RX_CSUM_OK(cqe) \ | |
537 | (!(BNX2X_L4_CSUM_ERR(cqe) || BNX2X_IP_CSUM_ERR(cqe))) | |
7a9b2557 | 538 | |
052a38e0 EG |
539 | #define BNX2X_PRS_FLAG_OVERETH_IPV4(flags) \ |
540 | (((le16_to_cpu(flags) & \ | |
541 | PARSING_FLAGS_OVER_ETHERNET_PROTOCOL) >> \ | |
542 | PARSING_FLAGS_OVER_ETHERNET_PROTOCOL_SHIFT) \ | |
543 | == PRS_FLAG_OVERETH_IPV4) | |
7a9b2557 | 544 | #define BNX2X_RX_SUM_FIX(cqe) \ |
052a38e0 | 545 | BNX2X_PRS_FLAG_OVERETH_IPV4(cqe->fast_path_cqe.pars_flags.flags) |
7a9b2557 | 546 | |
523224a3 DK |
547 | #define U_SB_ETH_RX_CQ_INDEX 1 |
548 | #define U_SB_ETH_RX_BD_INDEX 2 | |
549 | #define C_SB_ETH_TX_CQ_INDEX 5 | |
a2fbb9ea | 550 | |
34f80b04 | 551 | #define BNX2X_RX_SB_INDEX \ |
523224a3 | 552 | (&fp->sb_index_values[U_SB_ETH_RX_CQ_INDEX]) |
a2fbb9ea | 553 | |
34f80b04 | 554 | #define BNX2X_TX_SB_INDEX \ |
523224a3 | 555 | (&fp->sb_index_values[C_SB_ETH_TX_CQ_INDEX]) |
7a9b2557 VZ |
556 | |
557 | /* end of fast path */ | |
558 | ||
34f80b04 | 559 | /* common */ |
a2fbb9ea | 560 | |
34f80b04 | 561 | struct bnx2x_common { |
a2fbb9ea | 562 | |
ad8d3948 | 563 | u32 chip_id; |
a2fbb9ea | 564 | /* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */ |
34f80b04 | 565 | #define CHIP_ID(bp) (bp->common.chip_id & 0xfffffff0) |
ad8d3948 | 566 | |
34f80b04 | 567 | #define CHIP_NUM(bp) (bp->common.chip_id >> 16) |
ad8d3948 EG |
568 | #define CHIP_NUM_57710 0x164e |
569 | #define CHIP_NUM_57711 0x164f | |
570 | #define CHIP_NUM_57711E 0x1650 | |
f2e0899f DK |
571 | #define CHIP_NUM_57712 0x1662 |
572 | #define CHIP_NUM_57712E 0x1663 | |
ad8d3948 EG |
573 | #define CHIP_IS_E1(bp) (CHIP_NUM(bp) == CHIP_NUM_57710) |
574 | #define CHIP_IS_57711(bp) (CHIP_NUM(bp) == CHIP_NUM_57711) | |
575 | #define CHIP_IS_57711E(bp) (CHIP_NUM(bp) == CHIP_NUM_57711E) | |
f2e0899f DK |
576 | #define CHIP_IS_57712(bp) (CHIP_NUM(bp) == CHIP_NUM_57712) |
577 | #define CHIP_IS_57712E(bp) (CHIP_NUM(bp) == CHIP_NUM_57712E) | |
ad8d3948 EG |
578 | #define CHIP_IS_E1H(bp) (CHIP_IS_57711(bp) || \ |
579 | CHIP_IS_57711E(bp)) | |
f2e0899f DK |
580 | #define CHIP_IS_E2(bp) (CHIP_IS_57712(bp) || \ |
581 | CHIP_IS_57712E(bp)) | |
582 | #define CHIP_IS_E1x(bp) (CHIP_IS_E1((bp)) || CHIP_IS_E1H((bp))) | |
583 | #define IS_E1H_OFFSET (CHIP_IS_E1H(bp) || CHIP_IS_E2(bp)) | |
ad8d3948 | 584 | |
34f80b04 | 585 | #define CHIP_REV(bp) (bp->common.chip_id & 0x0000f000) |
ad8d3948 EG |
586 | #define CHIP_REV_Ax 0x00000000 |
587 | /* assume maximum 5 revisions */ | |
588 | #define CHIP_REV_IS_SLOW(bp) (CHIP_REV(bp) > 0x00005000) | |
589 | /* Emul versions are A=>0xe, B=>0xc, C=>0xa, D=>8, E=>6 */ | |
590 | #define CHIP_REV_IS_EMUL(bp) ((CHIP_REV_IS_SLOW(bp)) && \ | |
591 | !(CHIP_REV(bp) & 0x00001000)) | |
592 | /* FPGA versions are A=>0xf, B=>0xd, C=>0xb, D=>9, E=>7 */ | |
593 | #define CHIP_REV_IS_FPGA(bp) ((CHIP_REV_IS_SLOW(bp)) && \ | |
594 | (CHIP_REV(bp) & 0x00001000)) | |
595 | ||
596 | #define CHIP_TIME(bp) ((CHIP_REV_IS_EMUL(bp)) ? 2000 : \ | |
597 | ((CHIP_REV_IS_FPGA(bp)) ? 200 : 1)) | |
598 | ||
34f80b04 EG |
599 | #define CHIP_METAL(bp) (bp->common.chip_id & 0x00000ff0) |
600 | #define CHIP_BOND_ID(bp) (bp->common.chip_id & 0x0000000f) | |
a2fbb9ea | 601 | |
34f80b04 EG |
602 | int flash_size; |
603 | #define NVRAM_1MB_SIZE 0x20000 /* 1M bit in bytes */ | |
604 | #define NVRAM_TIMEOUT_COUNT 30000 | |
605 | #define NVRAM_PAGE_SIZE 256 | |
a2fbb9ea | 606 | |
34f80b04 | 607 | u32 shmem_base; |
2691d51d | 608 | u32 shmem2_base; |
523224a3 | 609 | u32 mf_cfg_base; |
f2e0899f | 610 | u32 mf2_cfg_base; |
34f80b04 EG |
611 | |
612 | u32 hw_config; | |
c18487ee | 613 | |
34f80b04 | 614 | u32 bc_ver; |
523224a3 DK |
615 | |
616 | u8 int_block; | |
617 | #define INT_BLOCK_HC 0 | |
f2e0899f DK |
618 | #define INT_BLOCK_IGU 1 |
619 | #define INT_BLOCK_MODE_NORMAL 0 | |
620 | #define INT_BLOCK_MODE_BW_COMP 2 | |
621 | #define CHIP_INT_MODE_IS_NBC(bp) \ | |
622 | (CHIP_IS_E2(bp) && \ | |
623 | !((bp)->common.int_block & INT_BLOCK_MODE_BW_COMP)) | |
624 | #define CHIP_INT_MODE_IS_BC(bp) (!CHIP_INT_MODE_IS_NBC(bp)) | |
625 | ||
523224a3 | 626 | u8 chip_port_mode; |
f2e0899f DK |
627 | #define CHIP_4_PORT_MODE 0x0 |
628 | #define CHIP_2_PORT_MODE 0x1 | |
523224a3 | 629 | #define CHIP_PORT_MODE_NONE 0x2 |
f2e0899f DK |
630 | #define CHIP_MODE(bp) (bp->common.chip_port_mode) |
631 | #define CHIP_MODE_IS_4_PORT(bp) (CHIP_MODE(bp) == CHIP_4_PORT_MODE) | |
34f80b04 | 632 | }; |
c18487ee | 633 | |
f2e0899f DK |
634 | /* IGU MSIX STATISTICS on 57712: 64 for VFs; 4 for PFs; 4 for Attentions */ |
635 | #define BNX2X_IGU_STAS_MSG_VF_CNT 64 | |
636 | #define BNX2X_IGU_STAS_MSG_PF_CNT 4 | |
34f80b04 EG |
637 | |
638 | /* end of common */ | |
639 | ||
640 | /* port */ | |
641 | ||
642 | struct bnx2x_port { | |
643 | u32 pmf; | |
c18487ee | 644 | |
a22f0788 | 645 | u32 link_config[LINK_CONFIG_SIZE]; |
a2fbb9ea | 646 | |
a22f0788 | 647 | u32 supported[LINK_CONFIG_SIZE]; |
34f80b04 EG |
648 | /* link settings - missing defines */ |
649 | #define SUPPORTED_2500baseX_Full (1 << 15) | |
650 | ||
a22f0788 | 651 | u32 advertising[LINK_CONFIG_SIZE]; |
a2fbb9ea | 652 | /* link settings - missing defines */ |
34f80b04 | 653 | #define ADVERTISED_2500baseX_Full (1 << 15) |
a2fbb9ea | 654 | |
34f80b04 | 655 | u32 phy_addr; |
c18487ee YR |
656 | |
657 | /* used to synchronize phy accesses */ | |
658 | struct mutex phy_mutex; | |
46c6a674 | 659 | int need_hw_lock; |
c18487ee | 660 | |
34f80b04 | 661 | u32 port_stx; |
a2fbb9ea | 662 | |
34f80b04 EG |
663 | struct nig_stats old_nig_stats; |
664 | }; | |
a2fbb9ea | 665 | |
34f80b04 EG |
666 | /* end of port */ |
667 | ||
523224a3 DK |
668 | /* e1h Classification CAM line allocations */ |
669 | enum { | |
670 | CAM_ETH_LINE = 0, | |
671 | CAM_ISCSI_ETH_LINE, | |
672 | CAM_MAX_PF_LINE = CAM_ISCSI_ETH_LINE | |
673 | }; | |
0793f83f DK |
674 | /* number of MACs per function in NIG memory - used for SI mode */ |
675 | #define NIG_LLH_FUNC_MEM_SIZE 16 | |
676 | /* number of entries in NIG_REG_LLHX_FUNC_MEM */ | |
677 | #define NIG_LLH_FUNC_MEM_MAX_OFFSET 8 | |
bb2a0f7a | 678 | |
523224a3 | 679 | #define BNX2X_VF_ID_INVALID 0xFF |
34f80b04 | 680 | |
523224a3 DK |
681 | /* |
682 | * The total number of L2 queues, MSIX vectors and HW contexts (CIDs) is | |
683 | * control by the number of fast-path status blocks supported by the | |
684 | * device (HW/FW). Each fast-path status block (FP-SB) aka non-default | |
685 | * status block represents an independent interrupts context that can | |
686 | * serve a regular L2 networking queue. However special L2 queues such | |
687 | * as the FCoE queue do not require a FP-SB and other components like | |
688 | * the CNIC may consume FP-SB reducing the number of possible L2 queues | |
689 | * | |
690 | * If the maximum number of FP-SB available is X then: | |
691 | * a. If CNIC is supported it consumes 1 FP-SB thus the max number of | |
692 | * regular L2 queues is Y=X-1 | |
693 | * b. in MF mode the actual number of L2 queues is Y= (X-1/MF_factor) | |
694 | * c. If the FCoE L2 queue is supported the actual number of L2 queues | |
695 | * is Y+1 | |
696 | * d. The number of irqs (MSIX vectors) is either Y+1 (one extra for | |
697 | * slow-path interrupts) or Y+2 if CNIC is supported (one additional | |
698 | * FP interrupt context for the CNIC). | |
699 | * e. The number of HW context (CID count) is always X or X+1 if FCoE | |
700 | * L2 queue is supported. the cid for the FCoE L2 queue is always X. | |
701 | */ | |
702 | ||
703 | #define FP_SB_MAX_E1x 16 /* fast-path interrupt contexts E1x */ | |
f2e0899f | 704 | #define FP_SB_MAX_E2 16 /* fast-path interrupt contexts E2 */ |
523224a3 DK |
705 | |
706 | /* | |
707 | * cid_cnt paramter below refers to the value returned by | |
708 | * 'bnx2x_get_l2_cid_count()' routine | |
709 | */ | |
710 | ||
711 | /* | |
712 | * The number of FP context allocated by the driver == max number of regular | |
713 | * L2 queues + 1 for the FCoE L2 queue | |
714 | */ | |
715 | #define L2_FP_COUNT(cid_cnt) ((cid_cnt) - CNIC_CONTEXT_USE) | |
34f80b04 EG |
716 | |
717 | union cdu_context { | |
718 | struct eth_context eth; | |
719 | char pad[1024]; | |
720 | }; | |
721 | ||
523224a3 DK |
722 | /* CDU host DB constants */ |
723 | #define CDU_ILT_PAGE_SZ_HW 3 | |
724 | #define CDU_ILT_PAGE_SZ (4096 << CDU_ILT_PAGE_SZ_HW) /* 32K */ | |
725 | #define ILT_PAGE_CIDS (CDU_ILT_PAGE_SZ / sizeof(union cdu_context)) | |
726 | ||
727 | #ifdef BCM_CNIC | |
728 | #define CNIC_ISCSI_CID_MAX 256 | |
729 | #define CNIC_CID_MAX (CNIC_ISCSI_CID_MAX) | |
730 | #define CNIC_ILT_LINES DIV_ROUND_UP(CNIC_CID_MAX, ILT_PAGE_CIDS) | |
731 | #endif | |
732 | ||
733 | #define QM_ILT_PAGE_SZ_HW 3 | |
734 | #define QM_ILT_PAGE_SZ (4096 << QM_ILT_PAGE_SZ_HW) /* 32K */ | |
735 | #define QM_CID_ROUND 1024 | |
736 | ||
737 | #ifdef BCM_CNIC | |
738 | /* TM (timers) host DB constants */ | |
739 | #define TM_ILT_PAGE_SZ_HW 2 | |
740 | #define TM_ILT_PAGE_SZ (4096 << TM_ILT_PAGE_SZ_HW) /* 16K */ | |
741 | /* #define TM_CONN_NUM (CNIC_STARTING_CID+CNIC_ISCSI_CXT_MAX) */ | |
742 | #define TM_CONN_NUM 1024 | |
743 | #define TM_ILT_SZ (8 * TM_CONN_NUM) | |
744 | #define TM_ILT_LINES DIV_ROUND_UP(TM_ILT_SZ, TM_ILT_PAGE_SZ) | |
745 | ||
746 | /* SRC (Searcher) host DB constants */ | |
747 | #define SRC_ILT_PAGE_SZ_HW 3 | |
748 | #define SRC_ILT_PAGE_SZ (4096 << SRC_ILT_PAGE_SZ_HW) /* 32K */ | |
749 | #define SRC_HASH_BITS 10 | |
750 | #define SRC_CONN_NUM (1 << SRC_HASH_BITS) /* 1024 */ | |
751 | #define SRC_ILT_SZ (sizeof(struct src_ent) * SRC_CONN_NUM) | |
752 | #define SRC_T2_SZ SRC_ILT_SZ | |
753 | #define SRC_ILT_LINES DIV_ROUND_UP(SRC_ILT_SZ, SRC_ILT_PAGE_SZ) | |
754 | #endif | |
755 | ||
bb2a0f7a | 756 | #define MAX_DMAE_C 8 |
34f80b04 EG |
757 | |
758 | /* DMA memory not used in fastpath */ | |
759 | struct bnx2x_slowpath { | |
34f80b04 EG |
760 | struct eth_stats_query fw_stats; |
761 | struct mac_configuration_cmd mac_config; | |
762 | struct mac_configuration_cmd mcast_config; | |
523224a3 | 763 | struct client_init_ramrod_data client_init_data; |
34f80b04 EG |
764 | |
765 | /* used by dmae command executer */ | |
766 | struct dmae_command dmae[MAX_DMAE_C]; | |
767 | ||
bb2a0f7a YG |
768 | u32 stats_comp; |
769 | union mac_stats mac_stats; | |
770 | struct nig_stats nig_stats; | |
771 | struct host_port_stats port_stats; | |
772 | struct host_func_stats func_stats; | |
6fe49bb9 | 773 | struct host_func_stats func_stats_base; |
34f80b04 EG |
774 | |
775 | u32 wb_comp; | |
34f80b04 EG |
776 | u32 wb_data[4]; |
777 | }; | |
778 | ||
779 | #define bnx2x_sp(bp, var) (&bp->slowpath->var) | |
780 | #define bnx2x_sp_mapping(bp, var) \ | |
781 | (bp->slowpath_mapping + offsetof(struct bnx2x_slowpath, var)) | |
782 | ||
783 | ||
784 | /* attn group wiring */ | |
785 | #define MAX_DYNAMIC_ATTN_GRPS 8 | |
786 | ||
787 | struct attn_route { | |
f2e0899f | 788 | u32 sig[5]; |
34f80b04 EG |
789 | }; |
790 | ||
523224a3 DK |
791 | struct iro { |
792 | u32 base; | |
793 | u16 m1; | |
794 | u16 m2; | |
795 | u16 m3; | |
796 | u16 size; | |
797 | }; | |
798 | ||
799 | struct hw_context { | |
800 | union cdu_context *vcxt; | |
801 | dma_addr_t cxt_mapping; | |
802 | size_t size; | |
803 | }; | |
804 | ||
805 | /* forward */ | |
806 | struct bnx2x_ilt; | |
807 | ||
72fd0718 VZ |
808 | typedef enum { |
809 | BNX2X_RECOVERY_DONE, | |
810 | BNX2X_RECOVERY_INIT, | |
811 | BNX2X_RECOVERY_WAIT, | |
812 | } bnx2x_recovery_state_t; | |
813 | ||
523224a3 DK |
814 | /** |
815 | * Event queue (EQ or event ring) MC hsi | |
816 | * NUM_EQ_PAGES and EQ_DESC_CNT_PAGE must be power of 2 | |
817 | */ | |
818 | #define NUM_EQ_PAGES 1 | |
819 | #define EQ_DESC_CNT_PAGE (BCM_PAGE_SIZE / sizeof(union event_ring_elem)) | |
820 | #define EQ_DESC_MAX_PAGE (EQ_DESC_CNT_PAGE - 1) | |
821 | #define NUM_EQ_DESC (EQ_DESC_CNT_PAGE * NUM_EQ_PAGES) | |
822 | #define EQ_DESC_MASK (NUM_EQ_DESC - 1) | |
823 | #define MAX_EQ_AVAIL (EQ_DESC_MAX_PAGE * NUM_EQ_PAGES - 2) | |
824 | ||
825 | /* depends on EQ_DESC_CNT_PAGE being a power of 2 */ | |
826 | #define NEXT_EQ_IDX(x) ((((x) & EQ_DESC_MAX_PAGE) == \ | |
827 | (EQ_DESC_MAX_PAGE - 1)) ? (x) + 2 : (x) + 1) | |
828 | ||
829 | /* depends on the above and on NUM_EQ_PAGES being a power of 2 */ | |
830 | #define EQ_DESC(x) ((x) & EQ_DESC_MASK) | |
831 | ||
832 | #define BNX2X_EQ_INDEX \ | |
833 | (&bp->def_status_blk->sp_sb.\ | |
834 | index_values[HC_SP_INDEX_EQ_CONS]) | |
835 | ||
34f80b04 EG |
836 | struct bnx2x { |
837 | /* Fields used in the tx and intr/napi performance paths | |
838 | * are grouped together in the beginning of the structure | |
839 | */ | |
523224a3 | 840 | struct bnx2x_fastpath *fp; |
34f80b04 EG |
841 | void __iomem *regview; |
842 | void __iomem *doorbells; | |
523224a3 | 843 | u16 db_size; |
34f80b04 EG |
844 | |
845 | struct net_device *dev; | |
846 | struct pci_dev *pdev; | |
847 | ||
523224a3 DK |
848 | struct iro *iro_arr; |
849 | #define IRO (bp->iro_arr) | |
850 | ||
34f80b04 | 851 | atomic_t intr_sem; |
72fd0718 VZ |
852 | |
853 | bnx2x_recovery_state_t recovery_state; | |
854 | int is_leader; | |
523224a3 | 855 | struct msix_entry *msix_table; |
8badd27a EG |
856 | #define INT_MODE_INTx 1 |
857 | #define INT_MODE_MSI 2 | |
34f80b04 EG |
858 | |
859 | int tx_ring_size; | |
860 | ||
34f80b04 | 861 | u32 rx_csum; |
437cf2f1 | 862 | u32 rx_buf_size; |
523224a3 DK |
863 | /* L2 header size + 2*VLANs (8 bytes) + LLC SNAP (8 bytes) */ |
864 | #define ETH_OVREHEAD (ETH_HLEN + 8 + 8) | |
34f80b04 EG |
865 | #define ETH_MIN_PACKET_SIZE 60 |
866 | #define ETH_MAX_PACKET_SIZE 1500 | |
867 | #define ETH_MAX_JUMBO_PACKET_SIZE 9600 | |
a2fbb9ea | 868 | |
0f00846d EG |
869 | /* Max supported alignment is 256 (8 shift) */ |
870 | #define BNX2X_RX_ALIGN_SHIFT ((L1_CACHE_SHIFT < 8) ? \ | |
871 | L1_CACHE_SHIFT : 8) | |
872 | #define BNX2X_RX_ALIGN (1 << BNX2X_RX_ALIGN_SHIFT) | |
523224a3 | 873 | #define BNX2X_PXP_DRAM_ALIGN (BNX2X_RX_ALIGN_SHIFT - 5) |
0f00846d | 874 | |
523224a3 DK |
875 | struct host_sp_status_block *def_status_blk; |
876 | #define DEF_SB_IGU_ID 16 | |
877 | #define DEF_SB_ID HC_SP_SB_ID | |
878 | __le16 def_idx; | |
4781bfad | 879 | __le16 def_att_idx; |
34f80b04 EG |
880 | u32 attn_state; |
881 | struct attn_route attn_group[MAX_DYNAMIC_ATTN_GRPS]; | |
34f80b04 EG |
882 | |
883 | /* slow path ring */ | |
884 | struct eth_spe *spq; | |
885 | dma_addr_t spq_mapping; | |
886 | u16 spq_prod_idx; | |
887 | struct eth_spe *spq_prod_bd; | |
888 | struct eth_spe *spq_last_bd; | |
4781bfad | 889 | __le16 *dsb_sp_prod; |
8fe23fbd | 890 | atomic_t spq_left; /* serialize spq */ |
34f80b04 EG |
891 | /* used to synchronize spq accesses */ |
892 | spinlock_t spq_lock; | |
893 | ||
523224a3 DK |
894 | /* event queue */ |
895 | union event_ring_elem *eq_ring; | |
896 | dma_addr_t eq_mapping; | |
897 | u16 eq_prod; | |
898 | u16 eq_cons; | |
899 | __le16 *eq_cons_sb; | |
900 | ||
bb2a0f7a YG |
901 | /* Flags for marking that there is a STAT_QUERY or |
902 | SET_MAC ramrod pending */ | |
e665bfda MC |
903 | int stats_pending; |
904 | int set_mac_pending; | |
34f80b04 | 905 | |
33471629 | 906 | /* End of fields used in the performance code paths */ |
34f80b04 EG |
907 | |
908 | int panic; | |
7995c64e | 909 | int msg_enable; |
34f80b04 EG |
910 | |
911 | u32 flags; | |
912 | #define PCIX_FLAG 1 | |
913 | #define PCI_32BIT_FLAG 2 | |
1c06328c | 914 | #define ONE_PORT_FLAG 4 |
34f80b04 EG |
915 | #define NO_WOL_FLAG 8 |
916 | #define USING_DAC_FLAG 0x10 | |
917 | #define USING_MSIX_FLAG 0x20 | |
8badd27a | 918 | #define USING_MSI_FLAG 0x40 |
d6214d7a | 919 | |
7a9b2557 | 920 | #define TPA_ENABLE_FLAG 0x80 |
34f80b04 | 921 | #define NO_MCP_FLAG 0x100 |
d6214d7a | 922 | #define DISABLE_MSI_FLAG 0x200 |
34f80b04 | 923 | #define BP_NOMCP(bp) (bp->flags & NO_MCP_FLAG) |
f34d28ea | 924 | #define MF_FUNC_DIS 0x1000 |
34f80b04 | 925 | |
f2e0899f DK |
926 | int pf_num; /* absolute PF number */ |
927 | int pfid; /* per-path PF number */ | |
523224a3 | 928 | int base_fw_ndsb; |
f2e0899f DK |
929 | #define BP_PATH(bp) (!CHIP_IS_E2(bp) ? \ |
930 | 0 : (bp->pf_num & 1)) | |
931 | #define BP_PORT(bp) (bp->pfid & 1) | |
932 | #define BP_FUNC(bp) (bp->pfid) | |
933 | #define BP_ABS_FUNC(bp) (bp->pf_num) | |
934 | #define BP_E1HVN(bp) (bp->pfid >> 1) | |
935 | #define BP_VN(bp) (CHIP_MODE_IS_4_PORT(bp) ? \ | |
936 | 0 : BP_E1HVN(bp)) | |
34f80b04 | 937 | #define BP_L_ID(bp) (BP_E1HVN(bp) << 2) |
f2e0899f DK |
938 | #define BP_FW_MB_IDX(bp) (BP_PORT(bp) +\ |
939 | BP_VN(bp) * (CHIP_IS_E1x(bp) ? 2 : 1)) | |
34f80b04 | 940 | |
37b091ba MC |
941 | #ifdef BCM_CNIC |
942 | #define BCM_CNIC_CID_START 16 | |
943 | #define BCM_ISCSI_ETH_CL_ID 17 | |
944 | #endif | |
945 | ||
34f80b04 EG |
946 | int pm_cap; |
947 | int pcie_cap; | |
8d5726c4 | 948 | int mrrs; |
34f80b04 | 949 | |
1cf167f2 | 950 | struct delayed_work sp_task; |
72fd0718 | 951 | struct delayed_work reset_task; |
34f80b04 | 952 | struct timer_list timer; |
34f80b04 EG |
953 | int current_interval; |
954 | ||
955 | u16 fw_seq; | |
956 | u16 fw_drv_pulse_wr_seq; | |
957 | u32 func_stx; | |
958 | ||
959 | struct link_params link_params; | |
960 | struct link_vars link_vars; | |
01cd4528 | 961 | struct mdio_if_info mdio; |
a2fbb9ea | 962 | |
34f80b04 EG |
963 | struct bnx2x_common common; |
964 | struct bnx2x_port port; | |
965 | ||
8a1c38d1 EG |
966 | struct cmng_struct_per_port cmng; |
967 | u32 vn_weight_sum; | |
968 | ||
f2e0899f DK |
969 | u32 mf_config[E1HVN_MAX]; |
970 | u32 mf2_config[E2_FUNC_MAX]; | |
fb3bff17 DK |
971 | u16 mf_ov; |
972 | u8 mf_mode; | |
f85582f8 | 973 | #define IS_MF(bp) (bp->mf_mode != 0) |
0793f83f DK |
974 | #define IS_MF_SI(bp) (bp->mf_mode == MULTI_FUNCTION_SI) |
975 | #define IS_MF_SD(bp) (bp->mf_mode == MULTI_FUNCTION_SD) | |
a2fbb9ea | 976 | |
f1410647 ET |
977 | u8 wol; |
978 | ||
34f80b04 | 979 | int rx_ring_size; |
a2fbb9ea | 980 | |
34f80b04 EG |
981 | u16 tx_quick_cons_trip_int; |
982 | u16 tx_quick_cons_trip; | |
983 | u16 tx_ticks_int; | |
984 | u16 tx_ticks; | |
a2fbb9ea | 985 | |
34f80b04 EG |
986 | u16 rx_quick_cons_trip_int; |
987 | u16 rx_quick_cons_trip; | |
988 | u16 rx_ticks_int; | |
989 | u16 rx_ticks; | |
cdaa7cb8 VZ |
990 | /* Maximal coalescing timeout in us */ |
991 | #define BNX2X_MAX_COALESCE_TOUT (0xf0*12) | |
a2fbb9ea | 992 | |
34f80b04 | 993 | u32 lin_cnt; |
a2fbb9ea | 994 | |
34f80b04 | 995 | int state; |
356e2385 | 996 | #define BNX2X_STATE_CLOSED 0 |
34f80b04 EG |
997 | #define BNX2X_STATE_OPENING_WAIT4_LOAD 0x1000 |
998 | #define BNX2X_STATE_OPENING_WAIT4_PORT 0x2000 | |
a2fbb9ea | 999 | #define BNX2X_STATE_OPEN 0x3000 |
34f80b04 | 1000 | #define BNX2X_STATE_CLOSING_WAIT4_HALT 0x4000 |
a2fbb9ea ET |
1001 | #define BNX2X_STATE_CLOSING_WAIT4_DELETE 0x5000 |
1002 | #define BNX2X_STATE_CLOSING_WAIT4_UNLOAD 0x6000 | |
523224a3 | 1003 | #define BNX2X_STATE_FUNC_STARTED 0x7000 |
34f80b04 EG |
1004 | #define BNX2X_STATE_DIAG 0xe000 |
1005 | #define BNX2X_STATE_ERROR 0xf000 | |
a2fbb9ea | 1006 | |
555f6c78 | 1007 | int multi_mode; |
54b9ddaa | 1008 | int num_queues; |
5d7cd496 DK |
1009 | int disable_tpa; |
1010 | int int_mode; | |
a2fbb9ea | 1011 | |
523224a3 DK |
1012 | struct tstorm_eth_mac_filter_config mac_filters; |
1013 | #define BNX2X_ACCEPT_NONE 0x0000 | |
1014 | #define BNX2X_ACCEPT_UNICAST 0x0001 | |
1015 | #define BNX2X_ACCEPT_MULTICAST 0x0002 | |
1016 | #define BNX2X_ACCEPT_ALL_UNICAST 0x0004 | |
1017 | #define BNX2X_ACCEPT_ALL_MULTICAST 0x0008 | |
1018 | #define BNX2X_ACCEPT_BROADCAST 0x0010 | |
0793f83f | 1019 | #define BNX2X_ACCEPT_UNMATCHED_UCAST 0x0020 |
523224a3 DK |
1020 | #define BNX2X_PROMISCUOUS_MODE 0x10000 |
1021 | ||
34f80b04 EG |
1022 | u32 rx_mode; |
1023 | #define BNX2X_RX_MODE_NONE 0 | |
1024 | #define BNX2X_RX_MODE_NORMAL 1 | |
1025 | #define BNX2X_RX_MODE_ALLMULTI 2 | |
1026 | #define BNX2X_RX_MODE_PROMISC 3 | |
1027 | #define BNX2X_MAX_MULTICAST 64 | |
1028 | #define BNX2X_MAX_EMUL_MULTI 16 | |
a2fbb9ea | 1029 | |
523224a3 DK |
1030 | u8 igu_dsb_id; |
1031 | u8 igu_base_sb; | |
1032 | u8 igu_sb_cnt; | |
34f80b04 | 1033 | dma_addr_t def_status_blk_mapping; |
a2fbb9ea | 1034 | |
34f80b04 EG |
1035 | struct bnx2x_slowpath *slowpath; |
1036 | dma_addr_t slowpath_mapping; | |
523224a3 DK |
1037 | struct hw_context context; |
1038 | ||
1039 | struct bnx2x_ilt *ilt; | |
1040 | #define BP_ILT(bp) ((bp)->ilt) | |
1041 | #define ILT_MAX_LINES 128 | |
1042 | ||
1043 | int l2_cid_count; | |
1044 | #define L2_ILT_LINES(bp) (DIV_ROUND_UP((bp)->l2_cid_count, \ | |
1045 | ILT_PAGE_CIDS)) | |
1046 | #define BNX2X_DB_SIZE(bp) ((bp)->l2_cid_count * (1 << BNX2X_DB_SHIFT)) | |
1047 | ||
1048 | int qm_cid_count; | |
a2fbb9ea | 1049 | |
a18f5128 EG |
1050 | int dropless_fc; |
1051 | ||
37b091ba MC |
1052 | #ifdef BCM_CNIC |
1053 | u32 cnic_flags; | |
1054 | #define BNX2X_CNIC_FLAG_MAC_SET 1 | |
37b091ba MC |
1055 | void *t2; |
1056 | dma_addr_t t2_mapping; | |
37b091ba MC |
1057 | struct cnic_ops *cnic_ops; |
1058 | void *cnic_data; | |
1059 | u32 cnic_tag; | |
1060 | struct cnic_eth_dev cnic_eth_dev; | |
523224a3 | 1061 | union host_hc_status_block cnic_sb; |
37b091ba | 1062 | dma_addr_t cnic_sb_mapping; |
523224a3 DK |
1063 | #define CNIC_SB_ID(bp) ((bp)->base_fw_ndsb + BP_L_ID(bp)) |
1064 | #define CNIC_IGU_SB_ID(bp) ((bp)->igu_base_sb) | |
37b091ba MC |
1065 | struct eth_spe *cnic_kwq; |
1066 | struct eth_spe *cnic_kwq_prod; | |
1067 | struct eth_spe *cnic_kwq_cons; | |
1068 | struct eth_spe *cnic_kwq_last; | |
1069 | u16 cnic_kwq_pending; | |
1070 | u16 cnic_spq_pending; | |
1071 | struct mutex cnic_mutex; | |
1072 | u8 iscsi_mac[6]; | |
1073 | #endif | |
1074 | ||
ad8d3948 EG |
1075 | int dmae_ready; |
1076 | /* used to synchronize dmae accesses */ | |
1077 | struct mutex dmae_mutex; | |
ad8d3948 | 1078 | |
c4ff7cbf EG |
1079 | /* used to protect the FW mail box */ |
1080 | struct mutex fw_mb_mutex; | |
1081 | ||
bb2a0f7a YG |
1082 | /* used to synchronize stats collecting */ |
1083 | int stats_state; | |
a13773a5 VZ |
1084 | |
1085 | /* used for synchronization of concurrent threads statistics handling */ | |
1086 | spinlock_t stats_lock; | |
1087 | ||
bb2a0f7a YG |
1088 | /* used by dmae command loader */ |
1089 | struct dmae_command stats_dmae; | |
1090 | int executer_idx; | |
ad8d3948 | 1091 | |
bb2a0f7a | 1092 | u16 stats_counter; |
bb2a0f7a YG |
1093 | struct bnx2x_eth_stats eth_stats; |
1094 | ||
1095 | struct z_stream_s *strm; | |
1096 | void *gunzip_buf; | |
1097 | dma_addr_t gunzip_mapping; | |
1098 | int gunzip_outlen; | |
ad8d3948 | 1099 | #define FW_BUF_SIZE 0x8000 |
573f2035 EG |
1100 | #define GUNZIP_BUF(bp) (bp->gunzip_buf) |
1101 | #define GUNZIP_PHYS(bp) (bp->gunzip_mapping) | |
1102 | #define GUNZIP_OUTLEN(bp) (bp->gunzip_outlen) | |
a2fbb9ea | 1103 | |
ab6ad5a4 | 1104 | struct raw_op *init_ops; |
94a78b79 | 1105 | /* Init blocks offsets inside init_ops */ |
ab6ad5a4 | 1106 | u16 *init_ops_offsets; |
94a78b79 | 1107 | /* Data blob - has 32 bit granularity */ |
ab6ad5a4 | 1108 | u32 *init_data; |
94a78b79 | 1109 | /* Zipped PRAM blobs - raw data */ |
ab6ad5a4 EG |
1110 | const u8 *tsem_int_table_data; |
1111 | const u8 *tsem_pram_data; | |
1112 | const u8 *usem_int_table_data; | |
1113 | const u8 *usem_pram_data; | |
1114 | const u8 *xsem_int_table_data; | |
1115 | const u8 *xsem_pram_data; | |
1116 | const u8 *csem_int_table_data; | |
1117 | const u8 *csem_pram_data; | |
573f2035 EG |
1118 | #define INIT_OPS(bp) (bp->init_ops) |
1119 | #define INIT_OPS_OFFSETS(bp) (bp->init_ops_offsets) | |
1120 | #define INIT_DATA(bp) (bp->init_data) | |
1121 | #define INIT_TSEM_INT_TABLE_DATA(bp) (bp->tsem_int_table_data) | |
1122 | #define INIT_TSEM_PRAM_DATA(bp) (bp->tsem_pram_data) | |
1123 | #define INIT_USEM_INT_TABLE_DATA(bp) (bp->usem_int_table_data) | |
1124 | #define INIT_USEM_PRAM_DATA(bp) (bp->usem_pram_data) | |
1125 | #define INIT_XSEM_INT_TABLE_DATA(bp) (bp->xsem_int_table_data) | |
1126 | #define INIT_XSEM_PRAM_DATA(bp) (bp->xsem_pram_data) | |
1127 | #define INIT_CSEM_INT_TABLE_DATA(bp) (bp->csem_int_table_data) | |
1128 | #define INIT_CSEM_PRAM_DATA(bp) (bp->csem_pram_data) | |
1129 | ||
34f24c7f | 1130 | char fw_ver[32]; |
ab6ad5a4 | 1131 | const struct firmware *firmware; |
a2fbb9ea ET |
1132 | }; |
1133 | ||
523224a3 DK |
1134 | /** |
1135 | * Init queue/func interface | |
1136 | */ | |
1137 | /* queue init flags */ | |
1138 | #define QUEUE_FLG_TPA 0x0001 | |
1139 | #define QUEUE_FLG_CACHE_ALIGN 0x0002 | |
1140 | #define QUEUE_FLG_STATS 0x0004 | |
1141 | #define QUEUE_FLG_OV 0x0008 | |
1142 | #define QUEUE_FLG_VLAN 0x0010 | |
1143 | #define QUEUE_FLG_COS 0x0020 | |
1144 | #define QUEUE_FLG_HC 0x0040 | |
1145 | #define QUEUE_FLG_DHC 0x0080 | |
1146 | #define QUEUE_FLG_OOO 0x0100 | |
1147 | ||
1148 | #define QUEUE_DROP_IP_CS_ERR TSTORM_ETH_CLIENT_CONFIG_DROP_IP_CS_ERR | |
1149 | #define QUEUE_DROP_TCP_CS_ERR TSTORM_ETH_CLIENT_CONFIG_DROP_TCP_CS_ERR | |
1150 | #define QUEUE_DROP_TTL0 TSTORM_ETH_CLIENT_CONFIG_DROP_TTL0 | |
1151 | #define QUEUE_DROP_UDP_CS_ERR TSTORM_ETH_CLIENT_CONFIG_DROP_UDP_CS_ERR | |
1152 | ||
1153 | ||
1154 | ||
1155 | /* rss capabilities */ | |
1156 | #define RSS_IPV4_CAP 0x0001 | |
1157 | #define RSS_IPV4_TCP_CAP 0x0002 | |
1158 | #define RSS_IPV6_CAP 0x0004 | |
1159 | #define RSS_IPV6_TCP_CAP 0x0008 | |
a2fbb9ea | 1160 | |
54b9ddaa VZ |
1161 | #define BNX2X_NUM_QUEUES(bp) (bp->num_queues) |
1162 | #define is_multi(bp) (BNX2X_NUM_QUEUES(bp) > 1) | |
3196a88a | 1163 | |
f2e0899f DK |
1164 | #define BNX2X_MAX_QUEUES(bp) (bp->igu_sb_cnt - CNIC_CONTEXT_USE) |
1165 | #define is_eth_multi(bp) (BNX2X_NUM_ETH_QUEUES(bp) > 1) | |
523224a3 DK |
1166 | |
1167 | #define RSS_IPV4_CAP_MASK \ | |
1168 | TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY | |
1169 | ||
1170 | #define RSS_IPV4_TCP_CAP_MASK \ | |
1171 | TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY | |
1172 | ||
1173 | #define RSS_IPV6_CAP_MASK \ | |
1174 | TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY | |
1175 | ||
1176 | #define RSS_IPV6_TCP_CAP_MASK \ | |
1177 | TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY | |
1178 | ||
1179 | /* func init flags */ | |
030f3356 DK |
1180 | #define FUNC_FLG_STATS 0x0001 |
1181 | #define FUNC_FLG_TPA 0x0002 | |
1182 | #define FUNC_FLG_SPQ 0x0004 | |
1183 | #define FUNC_FLG_LEADING 0x0008 /* PF only */ | |
523224a3 DK |
1184 | |
1185 | struct rxq_pause_params { | |
1186 | u16 bd_th_lo; | |
1187 | u16 bd_th_hi; | |
1188 | u16 rcq_th_lo; | |
1189 | u16 rcq_th_hi; | |
1190 | u16 sge_th_lo; /* valid iff QUEUE_FLG_TPA */ | |
1191 | u16 sge_th_hi; /* valid iff QUEUE_FLG_TPA */ | |
1192 | u16 pri_map; | |
1193 | }; | |
1194 | ||
1195 | struct bnx2x_rxq_init_params { | |
1196 | /* cxt*/ | |
1197 | struct eth_context *cxt; | |
1198 | ||
1199 | /* dma */ | |
1200 | dma_addr_t dscr_map; | |
1201 | dma_addr_t sge_map; | |
1202 | dma_addr_t rcq_map; | |
1203 | dma_addr_t rcq_np_map; | |
1204 | ||
1205 | u16 flags; | |
1206 | u16 drop_flags; | |
1207 | u16 mtu; | |
1208 | u16 buf_sz; | |
1209 | u16 fw_sb_id; | |
1210 | u16 cl_id; | |
1211 | u16 spcl_id; | |
1212 | u16 cl_qzone_id; | |
1213 | ||
1214 | /* valid iff QUEUE_FLG_STATS */ | |
1215 | u16 stat_id; | |
1216 | ||
1217 | /* valid iff QUEUE_FLG_TPA */ | |
1218 | u16 tpa_agg_sz; | |
1219 | u16 sge_buf_sz; | |
1220 | u16 max_sges_pkt; | |
1221 | ||
1222 | /* valid iff QUEUE_FLG_CACHE_ALIGN */ | |
1223 | u8 cache_line_log; | |
1224 | ||
1225 | u8 sb_cq_index; | |
1226 | u32 cid; | |
1227 | ||
1228 | /* desired interrupts per sec. valid iff QUEUE_FLG_HC */ | |
1229 | u32 hc_rate; | |
1230 | }; | |
1231 | ||
1232 | struct bnx2x_txq_init_params { | |
1233 | /* cxt*/ | |
1234 | struct eth_context *cxt; | |
1235 | ||
1236 | /* dma */ | |
1237 | dma_addr_t dscr_map; | |
1238 | ||
1239 | u16 flags; | |
1240 | u16 fw_sb_id; | |
1241 | u8 sb_cq_index; | |
1242 | u8 cos; /* valid iff QUEUE_FLG_COS */ | |
1243 | u16 stat_id; /* valid iff QUEUE_FLG_STATS */ | |
1244 | u16 traffic_type; | |
1245 | u32 cid; | |
1246 | u16 hc_rate; /* desired interrupts per sec.*/ | |
1247 | /* valid iff QUEUE_FLG_HC */ | |
1248 | ||
1249 | }; | |
1250 | ||
1251 | struct bnx2x_client_ramrod_params { | |
1252 | int *pstate; | |
1253 | int state; | |
1254 | u16 index; | |
1255 | u16 cl_id; | |
1256 | u32 cid; | |
1257 | u8 poll; | |
1258 | #define CLIENT_IS_LEADING_RSS 0x02 | |
1259 | u8 flags; | |
1260 | }; | |
1261 | ||
1262 | struct bnx2x_client_init_params { | |
1263 | struct rxq_pause_params pause; | |
1264 | struct bnx2x_rxq_init_params rxq_params; | |
1265 | struct bnx2x_txq_init_params txq_params; | |
1266 | struct bnx2x_client_ramrod_params ramrod_params; | |
1267 | }; | |
1268 | ||
1269 | struct bnx2x_rss_params { | |
1270 | int mode; | |
1271 | u16 cap; | |
1272 | u16 result_mask; | |
1273 | }; | |
1274 | ||
1275 | struct bnx2x_func_init_params { | |
1276 | ||
1277 | /* rss */ | |
1278 | struct bnx2x_rss_params *rss; /* valid iff FUNC_FLG_RSS */ | |
1279 | ||
1280 | /* dma */ | |
1281 | dma_addr_t fw_stat_map; /* valid iff FUNC_FLG_STATS */ | |
1282 | dma_addr_t spq_map; /* valid iff FUNC_FLG_SPQ */ | |
1283 | ||
1284 | u16 func_flgs; | |
1285 | u16 func_id; /* abs fid */ | |
1286 | u16 pf_id; | |
1287 | u16 spq_prod; /* valid iff FUNC_FLG_SPQ */ | |
1288 | }; | |
1289 | ||
555f6c78 EG |
1290 | #define for_each_queue(bp, var) \ |
1291 | for (var = 0; var < BNX2X_NUM_QUEUES(bp); var++) | |
3196a88a | 1292 | #define for_each_nondefault_queue(bp, var) \ |
54b9ddaa | 1293 | for (var = 1; var < BNX2X_NUM_QUEUES(bp); var++) |
3196a88a EG |
1294 | |
1295 | ||
f85582f8 DK |
1296 | #define WAIT_RAMROD_POLL 0x01 |
1297 | #define WAIT_RAMROD_COMMON 0x02 | |
f85582f8 DK |
1298 | |
1299 | /* dmae */ | |
c18487ee YR |
1300 | void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32); |
1301 | void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr, | |
1302 | u32 len32); | |
f85582f8 DK |
1303 | void bnx2x_post_dmae(struct bnx2x *bp, struct dmae_command *dmae, int idx); |
1304 | u32 bnx2x_dmae_opcode_add_comp(u32 opcode, u8 comp_type); | |
1305 | u32 bnx2x_dmae_opcode_clr_src_reset(u32 opcode); | |
1306 | u32 bnx2x_dmae_opcode(struct bnx2x *bp, u8 src_type, u8 dst_type, | |
1307 | bool with_comp, u8 comp_type); | |
1308 | ||
4acac6a5 | 1309 | int bnx2x_get_gpio(struct bnx2x *bp, int gpio_num, u8 port); |
17de50b7 | 1310 | int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode, u8 port); |
4acac6a5 | 1311 | int bnx2x_set_gpio_int(struct bnx2x *bp, int gpio_num, u32 mode, u8 port); |
a22f0788 | 1312 | u32 bnx2x_fw_command(struct bnx2x *bp, u32 command, u32 param); |
f85582f8 | 1313 | |
de0c62db DK |
1314 | void bnx2x_calc_fc_adv(struct bnx2x *bp); |
1315 | int bnx2x_sp_post(struct bnx2x *bp, int command, int cid, | |
1316 | u32 data_hi, u32 data_lo, int common); | |
1317 | void bnx2x_update_coalesce(struct bnx2x *bp); | |
a22f0788 | 1318 | int bnx2x_get_link_cfg_idx(struct bnx2x *bp); |
f85582f8 | 1319 | |
34f80b04 EG |
1320 | static inline u32 reg_poll(struct bnx2x *bp, u32 reg, u32 expected, int ms, |
1321 | int wait) | |
1322 | { | |
1323 | u32 val; | |
1324 | ||
1325 | do { | |
1326 | val = REG_RD(bp, reg); | |
1327 | if (val == expected) | |
1328 | break; | |
1329 | ms -= wait; | |
1330 | msleep(wait); | |
1331 | ||
1332 | } while (ms > 0); | |
1333 | ||
1334 | return val; | |
1335 | } | |
f85582f8 | 1336 | |
523224a3 DK |
1337 | #define BNX2X_ILT_ZALLOC(x, y, size) \ |
1338 | do { \ | |
1339 | x = pci_alloc_consistent(bp->pdev, size, y); \ | |
1340 | if (x) \ | |
1341 | memset(x, 0, size); \ | |
1342 | } while (0) | |
1343 | ||
1344 | #define BNX2X_ILT_FREE(x, y, size) \ | |
1345 | do { \ | |
1346 | if (x) { \ | |
1347 | pci_free_consistent(bp->pdev, size, x, y); \ | |
1348 | x = NULL; \ | |
1349 | y = 0; \ | |
1350 | } \ | |
1351 | } while (0) | |
1352 | ||
1353 | #define ILOG2(x) (ilog2((x))) | |
1354 | ||
1355 | #define ILT_NUM_PAGE_ENTRIES (3072) | |
1356 | /* In 57710/11 we use whole table since we have 8 func | |
f85582f8 DK |
1357 | * In 57712 we have only 4 func, but use same size per func, then only half of |
1358 | * the table in use | |
523224a3 DK |
1359 | */ |
1360 | #define ILT_PER_FUNC (ILT_NUM_PAGE_ENTRIES/8) | |
1361 | ||
1362 | #define FUNC_ILT_BASE(func) (func * ILT_PER_FUNC) | |
1363 | /* | |
1364 | * the phys address is shifted right 12 bits and has an added | |
1365 | * 1=valid bit added to the 53rd bit | |
1366 | * then since this is a wide register(TM) | |
1367 | * we split it into two 32 bit writes | |
1368 | */ | |
1369 | #define ONCHIP_ADDR1(x) ((u32)(((u64)x >> 12) & 0xFFFFFFFF)) | |
1370 | #define ONCHIP_ADDR2(x) ((u32)((1 << 20) | ((u64)x >> 44))) | |
34f80b04 | 1371 | |
34f80b04 EG |
1372 | /* load/unload mode */ |
1373 | #define LOAD_NORMAL 0 | |
1374 | #define LOAD_OPEN 1 | |
1375 | #define LOAD_DIAG 2 | |
1376 | #define UNLOAD_NORMAL 0 | |
1377 | #define UNLOAD_CLOSE 1 | |
f85582f8 | 1378 | #define UNLOAD_RECOVERY 2 |
34f80b04 | 1379 | |
bb2a0f7a | 1380 | |
ad8d3948 | 1381 | /* DMAE command defines */ |
f2e0899f DK |
1382 | #define DMAE_TIMEOUT -1 |
1383 | #define DMAE_PCI_ERROR -2 /* E2 and onward */ | |
1384 | #define DMAE_NOT_RDY -3 | |
1385 | #define DMAE_PCI_ERR_FLAG 0x80000000 | |
1386 | ||
1387 | #define DMAE_SRC_PCI 0 | |
1388 | #define DMAE_SRC_GRC 1 | |
1389 | ||
1390 | #define DMAE_DST_NONE 0 | |
1391 | #define DMAE_DST_PCI 1 | |
1392 | #define DMAE_DST_GRC 2 | |
1393 | ||
1394 | #define DMAE_COMP_PCI 0 | |
1395 | #define DMAE_COMP_GRC 1 | |
1396 | ||
1397 | /* E2 and onward - PCI error handling in the completion */ | |
1398 | ||
1399 | #define DMAE_COMP_REGULAR 0 | |
1400 | #define DMAE_COM_SET_ERR 1 | |
ad8d3948 | 1401 | |
f2e0899f DK |
1402 | #define DMAE_CMD_SRC_PCI (DMAE_SRC_PCI << \ |
1403 | DMAE_COMMAND_SRC_SHIFT) | |
1404 | #define DMAE_CMD_SRC_GRC (DMAE_SRC_GRC << \ | |
1405 | DMAE_COMMAND_SRC_SHIFT) | |
ad8d3948 | 1406 | |
f2e0899f DK |
1407 | #define DMAE_CMD_DST_PCI (DMAE_DST_PCI << \ |
1408 | DMAE_COMMAND_DST_SHIFT) | |
1409 | #define DMAE_CMD_DST_GRC (DMAE_DST_GRC << \ | |
1410 | DMAE_COMMAND_DST_SHIFT) | |
1411 | ||
1412 | #define DMAE_CMD_C_DST_PCI (DMAE_COMP_PCI << \ | |
1413 | DMAE_COMMAND_C_DST_SHIFT) | |
1414 | #define DMAE_CMD_C_DST_GRC (DMAE_COMP_GRC << \ | |
1415 | DMAE_COMMAND_C_DST_SHIFT) | |
ad8d3948 EG |
1416 | |
1417 | #define DMAE_CMD_C_ENABLE DMAE_COMMAND_C_TYPE_ENABLE | |
1418 | ||
1419 | #define DMAE_CMD_ENDIANITY_NO_SWAP (0 << DMAE_COMMAND_ENDIANITY_SHIFT) | |
1420 | #define DMAE_CMD_ENDIANITY_B_SWAP (1 << DMAE_COMMAND_ENDIANITY_SHIFT) | |
1421 | #define DMAE_CMD_ENDIANITY_DW_SWAP (2 << DMAE_COMMAND_ENDIANITY_SHIFT) | |
1422 | #define DMAE_CMD_ENDIANITY_B_DW_SWAP (3 << DMAE_COMMAND_ENDIANITY_SHIFT) | |
1423 | ||
1424 | #define DMAE_CMD_PORT_0 0 | |
1425 | #define DMAE_CMD_PORT_1 DMAE_COMMAND_PORT | |
1426 | ||
1427 | #define DMAE_CMD_SRC_RESET DMAE_COMMAND_SRC_RESET | |
1428 | #define DMAE_CMD_DST_RESET DMAE_COMMAND_DST_RESET | |
1429 | #define DMAE_CMD_E1HVN_SHIFT DMAE_COMMAND_E1HVN_SHIFT | |
1430 | ||
f2e0899f DK |
1431 | #define DMAE_SRC_PF 0 |
1432 | #define DMAE_SRC_VF 1 | |
1433 | ||
1434 | #define DMAE_DST_PF 0 | |
1435 | #define DMAE_DST_VF 1 | |
1436 | ||
1437 | #define DMAE_C_SRC 0 | |
1438 | #define DMAE_C_DST 1 | |
1439 | ||
ad8d3948 | 1440 | #define DMAE_LEN32_RD_MAX 0x80 |
02e3c6cb | 1441 | #define DMAE_LEN32_WR_MAX(bp) (CHIP_IS_E1(bp) ? 0x400 : 0x2000) |
ad8d3948 | 1442 | |
f2e0899f DK |
1443 | #define DMAE_COMP_VAL 0x60d0d0ae /* E2 and on - upper bit |
1444 | indicates eror */ | |
ad8d3948 EG |
1445 | |
1446 | #define MAX_DMAE_C_PER_PORT 8 | |
ab6ad5a4 | 1447 | #define INIT_DMAE_C(bp) (BP_PORT(bp) * MAX_DMAE_C_PER_PORT + \ |
ad8d3948 | 1448 | BP_E1HVN(bp)) |
ab6ad5a4 | 1449 | #define PMF_DMAE_C(bp) (BP_PORT(bp) * MAX_DMAE_C_PER_PORT + \ |
ad8d3948 EG |
1450 | E1HVN_MAX) |
1451 | ||
25047950 ET |
1452 | /* PCIE link and speed */ |
1453 | #define PCICFG_LINK_WIDTH 0x1f00000 | |
1454 | #define PCICFG_LINK_WIDTH_SHIFT 20 | |
1455 | #define PCICFG_LINK_SPEED 0xf0000 | |
1456 | #define PCICFG_LINK_SPEED_SHIFT 16 | |
a2fbb9ea | 1457 | |
bb2a0f7a | 1458 | |
d3d4f495 | 1459 | #define BNX2X_NUM_TESTS 7 |
bb2a0f7a | 1460 | |
b5bf9068 EG |
1461 | #define BNX2X_PHY_LOOPBACK 0 |
1462 | #define BNX2X_MAC_LOOPBACK 1 | |
1463 | #define BNX2X_PHY_LOOPBACK_FAILED 1 | |
1464 | #define BNX2X_MAC_LOOPBACK_FAILED 2 | |
bb2a0f7a YG |
1465 | #define BNX2X_LOOPBACK_FAILED (BNX2X_MAC_LOOPBACK_FAILED | \ |
1466 | BNX2X_PHY_LOOPBACK_FAILED) | |
96fc1784 | 1467 | |
7a9b2557 VZ |
1468 | |
1469 | #define STROM_ASSERT_ARRAY_SIZE 50 | |
1470 | ||
96fc1784 | 1471 | |
34f80b04 | 1472 | /* must be used on a CID before placing it on a HW ring */ |
ab6ad5a4 EG |
1473 | #define HW_CID(bp, x) ((BP_PORT(bp) << 23) | \ |
1474 | (BP_E1HVN(bp) << 17) | (x)) | |
7a9b2557 VZ |
1475 | |
1476 | #define SP_DESC_CNT (BCM_PAGE_SIZE / sizeof(struct eth_spe)) | |
1477 | #define MAX_SP_DESC_CNT (SP_DESC_CNT - 1) | |
1478 | ||
1479 | ||
523224a3 | 1480 | #define BNX2X_BTR 4 |
7a9b2557 | 1481 | #define MAX_SPQ_PENDING 8 |
a2fbb9ea | 1482 | |
a2fbb9ea | 1483 | |
34f80b04 EG |
1484 | /* CMNG constants |
1485 | derived from lab experiments, and not from system spec calculations !!! */ | |
1486 | #define DEF_MIN_RATE 100 | |
1487 | /* resolution of the rate shaping timer - 100 usec */ | |
1488 | #define RS_PERIODIC_TIMEOUT_USEC 100 | |
1489 | /* resolution of fairness algorithm in usecs - | |
33471629 | 1490 | coefficient for calculating the actual t fair */ |
34f80b04 EG |
1491 | #define T_FAIR_COEF 10000000 |
1492 | /* number of bytes in single QM arbitration cycle - | |
33471629 | 1493 | coefficient for calculating the fairness timer */ |
34f80b04 EG |
1494 | #define QM_ARB_BYTES 40000 |
1495 | #define FAIR_MEM 2 | |
1496 | ||
1497 | ||
1498 | #define ATTN_NIG_FOR_FUNC (1L << 8) | |
1499 | #define ATTN_SW_TIMER_4_FUNC (1L << 9) | |
1500 | #define GPIO_2_FUNC (1L << 10) | |
1501 | #define GPIO_3_FUNC (1L << 11) | |
1502 | #define GPIO_4_FUNC (1L << 12) | |
1503 | #define ATTN_GENERAL_ATTN_1 (1L << 13) | |
1504 | #define ATTN_GENERAL_ATTN_2 (1L << 14) | |
1505 | #define ATTN_GENERAL_ATTN_3 (1L << 15) | |
1506 | #define ATTN_GENERAL_ATTN_4 (1L << 13) | |
1507 | #define ATTN_GENERAL_ATTN_5 (1L << 14) | |
1508 | #define ATTN_GENERAL_ATTN_6 (1L << 15) | |
1509 | ||
1510 | #define ATTN_HARD_WIRED_MASK 0xff00 | |
1511 | #define ATTENTION_ID 4 | |
a2fbb9ea ET |
1512 | |
1513 | ||
34f80b04 EG |
1514 | /* stuff added to make the code fit 80Col */ |
1515 | ||
1516 | #define BNX2X_PMF_LINK_ASSERT \ | |
1517 | GENERAL_ATTEN_OFFSET(LINK_SYNC_ATTENTION_BIT_FUNC_0 + BP_FUNC(bp)) | |
1518 | ||
a2fbb9ea ET |
1519 | #define BNX2X_MC_ASSERT_BITS \ |
1520 | (GENERAL_ATTEN_OFFSET(TSTORM_FATAL_ASSERT_ATTENTION_BIT) | \ | |
1521 | GENERAL_ATTEN_OFFSET(USTORM_FATAL_ASSERT_ATTENTION_BIT) | \ | |
1522 | GENERAL_ATTEN_OFFSET(CSTORM_FATAL_ASSERT_ATTENTION_BIT) | \ | |
1523 | GENERAL_ATTEN_OFFSET(XSTORM_FATAL_ASSERT_ATTENTION_BIT)) | |
1524 | ||
1525 | #define BNX2X_MCP_ASSERT \ | |
1526 | GENERAL_ATTEN_OFFSET(MCP_FATAL_ASSERT_ATTENTION_BIT) | |
1527 | ||
34f80b04 EG |
1528 | #define BNX2X_GRC_TIMEOUT GENERAL_ATTEN_OFFSET(LATCHED_ATTN_TIMEOUT_GRC) |
1529 | #define BNX2X_GRC_RSV (GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCR) | \ | |
1530 | GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCT) | \ | |
1531 | GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCN) | \ | |
1532 | GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCU) | \ | |
1533 | GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCP) | \ | |
1534 | GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RSVD_GRC)) | |
1535 | ||
a2fbb9ea ET |
1536 | #define HW_INTERRUT_ASSERT_SET_0 \ |
1537 | (AEU_INPUTS_ATTN_BITS_TSDM_HW_INTERRUPT | \ | |
1538 | AEU_INPUTS_ATTN_BITS_TCM_HW_INTERRUPT | \ | |
1539 | AEU_INPUTS_ATTN_BITS_TSEMI_HW_INTERRUPT | \ | |
1540 | AEU_INPUTS_ATTN_BITS_PBF_HW_INTERRUPT) | |
34f80b04 | 1541 | #define HW_PRTY_ASSERT_SET_0 (AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR | \ |
a2fbb9ea ET |
1542 | AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR | \ |
1543 | AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR | \ | |
1544 | AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR |\ | |
1545 | AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR) | |
1546 | #define HW_INTERRUT_ASSERT_SET_1 \ | |
1547 | (AEU_INPUTS_ATTN_BITS_QM_HW_INTERRUPT | \ | |
1548 | AEU_INPUTS_ATTN_BITS_TIMERS_HW_INTERRUPT | \ | |
1549 | AEU_INPUTS_ATTN_BITS_XSDM_HW_INTERRUPT | \ | |
1550 | AEU_INPUTS_ATTN_BITS_XCM_HW_INTERRUPT | \ | |
1551 | AEU_INPUTS_ATTN_BITS_XSEMI_HW_INTERRUPT | \ | |
1552 | AEU_INPUTS_ATTN_BITS_USDM_HW_INTERRUPT | \ | |
1553 | AEU_INPUTS_ATTN_BITS_UCM_HW_INTERRUPT | \ | |
1554 | AEU_INPUTS_ATTN_BITS_USEMI_HW_INTERRUPT | \ | |
1555 | AEU_INPUTS_ATTN_BITS_UPB_HW_INTERRUPT | \ | |
1556 | AEU_INPUTS_ATTN_BITS_CSDM_HW_INTERRUPT | \ | |
1557 | AEU_INPUTS_ATTN_BITS_CCM_HW_INTERRUPT) | |
34f80b04 | 1558 | #define HW_PRTY_ASSERT_SET_1 (AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR |\ |
a2fbb9ea ET |
1559 | AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR | \ |
1560 | AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR | \ | |
1561 | AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR | \ | |
ab6ad5a4 EG |
1562 | AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR |\ |
1563 | AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR |\ | |
a2fbb9ea ET |
1564 | AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR | \ |
1565 | AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR | \ | |
1566 | AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR | \ | |
1567 | AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR | \ | |
1568 | AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR) | |
1569 | #define HW_INTERRUT_ASSERT_SET_2 \ | |
1570 | (AEU_INPUTS_ATTN_BITS_CSEMI_HW_INTERRUPT | \ | |
1571 | AEU_INPUTS_ATTN_BITS_CDU_HW_INTERRUPT | \ | |
1572 | AEU_INPUTS_ATTN_BITS_DMAE_HW_INTERRUPT | \ | |
1573 | AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_HW_INTERRUPT |\ | |
1574 | AEU_INPUTS_ATTN_BITS_MISC_HW_INTERRUPT) | |
34f80b04 | 1575 | #define HW_PRTY_ASSERT_SET_2 (AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR | \ |
a2fbb9ea ET |
1576 | AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR | \ |
1577 | AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR |\ | |
1578 | AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR | \ | |
1579 | AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR | \ | |
1580 | AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR | \ | |
1581 | AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR) | |
1582 | ||
72fd0718 VZ |
1583 | #define HW_PRTY_ASSERT_SET_3 (AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY | \ |
1584 | AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY | \ | |
1585 | AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY | \ | |
1586 | AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY) | |
a2fbb9ea | 1587 | |
c68ed255 | 1588 | #define RSS_FLAGS(bp) \ |
34f80b04 EG |
1589 | (TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY | \ |
1590 | TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY | \ | |
1591 | TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY | \ | |
1592 | TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY | \ | |
555f6c78 EG |
1593 | (bp->multi_mode << \ |
1594 | TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_MODE_SHIFT)) | |
34f80b04 | 1595 | #define MULTI_MASK 0x7f |
a2fbb9ea | 1596 | |
a2fbb9ea | 1597 | #define BNX2X_SP_DSB_INDEX \ |
523224a3 DK |
1598 | (&bp->def_status_blk->sp_sb.\ |
1599 | index_values[HC_SP_INDEX_ETH_DEF_CONS]) | |
f85582f8 | 1600 | |
523224a3 DK |
1601 | #define SET_FLAG(value, mask, flag) \ |
1602 | do {\ | |
1603 | (value) &= ~(mask);\ | |
1604 | (value) |= ((flag) << (mask##_SHIFT));\ | |
1605 | } while (0) | |
a2fbb9ea | 1606 | |
523224a3 DK |
1607 | #define GET_FLAG(value, mask) \ |
1608 | (((value) &= (mask)) >> (mask##_SHIFT)) | |
a2fbb9ea | 1609 | |
f2e0899f DK |
1610 | #define GET_FIELD(value, fname) \ |
1611 | (((value) & (fname##_MASK)) >> (fname##_SHIFT)) | |
1612 | ||
a2fbb9ea | 1613 | #define CAM_IS_INVALID(x) \ |
523224a3 DK |
1614 | (GET_FLAG(x.flags, \ |
1615 | MAC_CONFIGURATION_ENTRY_ACTION_TYPE) == \ | |
1616 | (T_ETH_MAC_COMMAND_INVALIDATE)) | |
a2fbb9ea ET |
1617 | |
1618 | #define CAM_INVALIDATE(x) \ | |
34f80b04 EG |
1619 | (x.target_table_entry.flags = TSTORM_CAM_TARGET_TABLE_ENTRY_ACTION_TYPE) |
1620 | ||
1621 | ||
1622 | /* Number of u32 elements in MC hash array */ | |
1623 | #define MC_HASH_SIZE 8 | |
1624 | #define MC_HASH_OFFSET(bp, i) (BAR_TSTRORM_INTMEM + \ | |
1625 | TSTORM_APPROXIMATE_MATCH_MULTICAST_FILTERING_OFFSET(BP_FUNC(bp)) + i*4) | |
a2fbb9ea ET |
1626 | |
1627 | ||
34f80b04 EG |
1628 | #ifndef PXP2_REG_PXP2_INT_STS |
1629 | #define PXP2_REG_PXP2_INT_STS PXP2_REG_PXP2_INT_STS_0 | |
1630 | #endif | |
1631 | ||
f2e0899f DK |
1632 | #ifndef ETH_MAX_RX_CLIENTS_E2 |
1633 | #define ETH_MAX_RX_CLIENTS_E2 ETH_MAX_RX_CLIENTS_E1H | |
1634 | #endif | |
f85582f8 | 1635 | |
34f24c7f VZ |
1636 | #define BNX2X_VPD_LEN 128 |
1637 | #define VENDOR_ID_LEN 4 | |
1638 | ||
523224a3 DK |
1639 | /* Congestion management fairness mode */ |
1640 | #define CMNG_FNS_NONE 0 | |
1641 | #define CMNG_FNS_MINMAX 1 | |
1642 | ||
1643 | #define HC_SEG_ACCESS_DEF 0 /*Driver decision 0-3*/ | |
1644 | #define HC_SEG_ACCESS_ATTN 4 | |
1645 | #define HC_SEG_ACCESS_NORM 0 /*Driver decision 0-1*/ | |
1646 | ||
b0efbb99 DK |
1647 | #ifdef BNX2X_MAIN |
1648 | #define BNX2X_EXTERN | |
1649 | #else | |
1650 | #define BNX2X_EXTERN extern | |
1651 | #endif | |
1652 | ||
f2e0899f | 1653 | BNX2X_EXTERN int load_count[2][3]; /* per path: 0-common, 1-port0, 2-port1 */ |
b0efbb99 | 1654 | |
de0c62db DK |
1655 | extern void bnx2x_set_ethtool_ops(struct net_device *netdev); |
1656 | ||
a2fbb9ea | 1657 | #endif /* bnx2x.h */ |