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9f6c9258 DK |
1 | /* bnx2x_cmn.h: Broadcom Everest network driver. |
2 | * | |
5de92408 | 3 | * Copyright (c) 2007-2011 Broadcom Corporation |
9f6c9258 DK |
4 | * |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License as published by | |
7 | * the Free Software Foundation. | |
8 | * | |
9 | * Maintained by: Eilon Greenstein <eilong@broadcom.com> | |
10 | * Written by: Eliezer Tamir | |
11 | * Based on code from Michael Chan's bnx2 driver | |
12 | * UDP CSUM errata workaround by Arik Gendelman | |
13 | * Slowpath and fastpath rework by Vladislav Zolotarov | |
14 | * Statistics and Link management by Yitchak Gertner | |
15 | * | |
16 | */ | |
17 | #ifndef BNX2X_CMN_H | |
18 | #define BNX2X_CMN_H | |
19 | ||
20 | #include <linux/types.h> | |
619c5cb6 | 21 | #include <linux/pci.h> |
9f6c9258 DK |
22 | #include <linux/netdevice.h> |
23 | ||
24 | ||
25 | #include "bnx2x.h" | |
26 | ||
619c5cb6 VZ |
27 | /* This is used as a replacement for an MCP if it's not present */ |
28 | extern int load_count[2][3]; /* per-path: 0-common, 1-port0, 2-port1 */ | |
29 | ||
d6214d7a | 30 | extern int num_queues; |
9f6c9258 | 31 | |
b3b83c3f DK |
32 | /************************ Macros ********************************/ |
33 | #define BNX2X_PCI_FREE(x, y, size) \ | |
34 | do { \ | |
35 | if (x) { \ | |
36 | dma_free_coherent(&bp->pdev->dev, size, (void *)x, y); \ | |
37 | x = NULL; \ | |
38 | y = 0; \ | |
39 | } \ | |
40 | } while (0) | |
41 | ||
42 | #define BNX2X_FREE(x) \ | |
43 | do { \ | |
44 | if (x) { \ | |
45 | kfree((void *)x); \ | |
46 | x = NULL; \ | |
47 | } \ | |
48 | } while (0) | |
49 | ||
50 | #define BNX2X_PCI_ALLOC(x, y, size) \ | |
51 | do { \ | |
52 | x = dma_alloc_coherent(&bp->pdev->dev, size, y, GFP_KERNEL); \ | |
53 | if (x == NULL) \ | |
54 | goto alloc_mem_err; \ | |
55 | memset((void *)x, 0, size); \ | |
56 | } while (0) | |
57 | ||
58 | #define BNX2X_ALLOC(x, size) \ | |
59 | do { \ | |
60 | x = kzalloc(size, GFP_KERNEL); \ | |
61 | if (x == NULL) \ | |
62 | goto alloc_mem_err; \ | |
63 | } while (0) | |
64 | ||
9f6c9258 DK |
65 | /*********************** Interfaces **************************** |
66 | * Functions that need to be implemented by each driver version | |
67 | */ | |
619c5cb6 VZ |
68 | /* Init */ |
69 | ||
70 | /** | |
71 | * bnx2x_send_unload_req - request unload mode from the MCP. | |
72 | * | |
73 | * @bp: driver handle | |
74 | * @unload_mode: requested function's unload mode | |
75 | * | |
76 | * Return unload mode returned by the MCP: COMMON, PORT or FUNC. | |
77 | */ | |
78 | u32 bnx2x_send_unload_req(struct bnx2x *bp, int unload_mode); | |
79 | ||
80 | /** | |
81 | * bnx2x_send_unload_done - send UNLOAD_DONE command to the MCP. | |
82 | * | |
83 | * @bp: driver handle | |
84 | */ | |
85 | void bnx2x_send_unload_done(struct bnx2x *bp); | |
86 | ||
87 | /** | |
88 | * bnx2x_config_rss_pf - configure RSS parameters. | |
89 | * | |
90 | * @bp: driver handle | |
91 | * @ind_table: indirection table to configure | |
92 | * @config_hash: re-configure RSS hash keys configuration | |
93 | */ | |
94 | int bnx2x_config_rss_pf(struct bnx2x *bp, u8 *ind_table, bool config_hash); | |
95 | ||
96 | /** | |
97 | * bnx2x__init_func_obj - init function object | |
98 | * | |
99 | * @bp: driver handle | |
100 | * | |
101 | * Initializes the Function Object with the appropriate | |
102 | * parameters which include a function slow path driver | |
103 | * interface. | |
104 | */ | |
105 | void bnx2x__init_func_obj(struct bnx2x *bp); | |
106 | ||
107 | /** | |
108 | * bnx2x_setup_queue - setup eth queue. | |
109 | * | |
110 | * @bp: driver handle | |
111 | * @fp: pointer to the fastpath structure | |
112 | * @leading: boolean | |
113 | * | |
114 | */ | |
115 | int bnx2x_setup_queue(struct bnx2x *bp, struct bnx2x_fastpath *fp, | |
116 | bool leading); | |
117 | ||
118 | /** | |
119 | * bnx2x_setup_leading - bring up a leading eth queue. | |
120 | * | |
121 | * @bp: driver handle | |
122 | */ | |
123 | int bnx2x_setup_leading(struct bnx2x *bp); | |
124 | ||
125 | /** | |
126 | * bnx2x_fw_command - send the MCP a request | |
127 | * | |
128 | * @bp: driver handle | |
129 | * @command: request | |
130 | * @param: request's parameter | |
131 | * | |
132 | * block until there is a reply | |
133 | */ | |
134 | u32 bnx2x_fw_command(struct bnx2x *bp, u32 command, u32 param); | |
9f6c9258 DK |
135 | |
136 | /** | |
e8920674 | 137 | * bnx2x_initial_phy_init - initialize link parameters structure variables. |
9f6c9258 | 138 | * |
e8920674 DK |
139 | * @bp: driver handle |
140 | * @load_mode: current mode | |
9f6c9258 DK |
141 | */ |
142 | u8 bnx2x_initial_phy_init(struct bnx2x *bp, int load_mode); | |
143 | ||
144 | /** | |
e8920674 | 145 | * bnx2x_link_set - configure hw according to link parameters structure. |
9f6c9258 | 146 | * |
e8920674 | 147 | * @bp: driver handle |
9f6c9258 DK |
148 | */ |
149 | void bnx2x_link_set(struct bnx2x *bp); | |
150 | ||
151 | /** | |
e8920674 | 152 | * bnx2x_link_test - query link status. |
9f6c9258 | 153 | * |
e8920674 DK |
154 | * @bp: driver handle |
155 | * @is_serdes: bool | |
9f6c9258 | 156 | * |
e8920674 | 157 | * Returns 0 if link is UP. |
9f6c9258 | 158 | */ |
a22f0788 | 159 | u8 bnx2x_link_test(struct bnx2x *bp, u8 is_serdes); |
9f6c9258 | 160 | |
619c5cb6 VZ |
161 | /** |
162 | * bnx2x_drv_pulse - write driver pulse to shmem | |
163 | * | |
164 | * @bp: driver handle | |
165 | * | |
166 | * writes the value in bp->fw_drv_pulse_wr_seq to drv_pulse mbox | |
167 | * in the shmem. | |
168 | */ | |
169 | void bnx2x_drv_pulse(struct bnx2x *bp); | |
170 | ||
171 | /** | |
172 | * bnx2x_igu_ack_sb - update IGU with current SB value | |
173 | * | |
174 | * @bp: driver handle | |
175 | * @igu_sb_id: SB id | |
176 | * @segment: SB segment | |
177 | * @index: SB index | |
178 | * @op: SB operation | |
179 | * @update: is HW update required | |
180 | */ | |
181 | void bnx2x_igu_ack_sb(struct bnx2x *bp, u8 igu_sb_id, u8 segment, | |
182 | u16 index, u8 op, u8 update); | |
183 | ||
9f6c9258 | 184 | /** |
e8920674 | 185 | * bnx2x__link_status_update - handles link status change. |
9f6c9258 | 186 | * |
e8920674 | 187 | * @bp: driver handle |
9f6c9258 DK |
188 | */ |
189 | void bnx2x__link_status_update(struct bnx2x *bp); | |
190 | ||
f85582f8 | 191 | /** |
e8920674 | 192 | * bnx2x_link_report - report link status to upper layer. |
f85582f8 | 193 | * |
e8920674 | 194 | * @bp: driver handle |
f85582f8 DK |
195 | */ |
196 | void bnx2x_link_report(struct bnx2x *bp); | |
197 | ||
2ae17f66 VZ |
198 | /* None-atomic version of bnx2x_link_report() */ |
199 | void __bnx2x_link_report(struct bnx2x *bp); | |
200 | ||
0793f83f | 201 | /** |
e8920674 | 202 | * bnx2x_get_mf_speed - calculate MF speed. |
0793f83f | 203 | * |
e8920674 | 204 | * @bp: driver handle |
0793f83f | 205 | * |
e8920674 | 206 | * Takes into account current linespeed and MF configuration. |
0793f83f DK |
207 | */ |
208 | u16 bnx2x_get_mf_speed(struct bnx2x *bp); | |
209 | ||
9f6c9258 | 210 | /** |
e8920674 | 211 | * bnx2x_msix_sp_int - MSI-X slowpath interrupt handler |
9f6c9258 | 212 | * |
e8920674 DK |
213 | * @irq: irq number |
214 | * @dev_instance: private instance | |
9f6c9258 DK |
215 | */ |
216 | irqreturn_t bnx2x_msix_sp_int(int irq, void *dev_instance); | |
217 | ||
218 | /** | |
e8920674 | 219 | * bnx2x_interrupt - non MSI-X interrupt handler |
9f6c9258 | 220 | * |
e8920674 DK |
221 | * @irq: irq number |
222 | * @dev_instance: private instance | |
9f6c9258 DK |
223 | */ |
224 | irqreturn_t bnx2x_interrupt(int irq, void *dev_instance); | |
225 | #ifdef BCM_CNIC | |
226 | ||
227 | /** | |
e8920674 | 228 | * bnx2x_cnic_notify - send command to cnic driver |
9f6c9258 | 229 | * |
e8920674 DK |
230 | * @bp: driver handle |
231 | * @cmd: command | |
9f6c9258 DK |
232 | */ |
233 | int bnx2x_cnic_notify(struct bnx2x *bp, int cmd); | |
234 | ||
235 | /** | |
e8920674 | 236 | * bnx2x_setup_cnic_irq_info - provides cnic with IRQ information |
9f6c9258 | 237 | * |
e8920674 | 238 | * @bp: driver handle |
9f6c9258 DK |
239 | */ |
240 | void bnx2x_setup_cnic_irq_info(struct bnx2x *bp); | |
241 | #endif | |
242 | ||
243 | /** | |
e8920674 | 244 | * bnx2x_int_enable - enable HW interrupts. |
9f6c9258 | 245 | * |
e8920674 | 246 | * @bp: driver handle |
9f6c9258 DK |
247 | */ |
248 | void bnx2x_int_enable(struct bnx2x *bp); | |
249 | ||
250 | /** | |
e8920674 DK |
251 | * bnx2x_int_disable_sync - disable interrupts. |
252 | * | |
253 | * @bp: driver handle | |
254 | * @disable_hw: true, disable HW interrupts. | |
9f6c9258 | 255 | * |
e8920674 DK |
256 | * This function ensures that there are no |
257 | * ISRs or SP DPCs (sp_task) are running after it returns. | |
9f6c9258 DK |
258 | */ |
259 | void bnx2x_int_disable_sync(struct bnx2x *bp, int disable_hw); | |
260 | ||
9f6c9258 | 261 | /** |
e8920674 DK |
262 | * bnx2x_nic_init - init driver internals. |
263 | * | |
264 | * @bp: driver handle | |
265 | * @load_code: COMMON, PORT or FUNCTION | |
266 | * | |
267 | * Initializes: | |
9f6c9258 DK |
268 | * - rings |
269 | * - status blocks | |
270 | * - etc. | |
9f6c9258 DK |
271 | */ |
272 | void bnx2x_nic_init(struct bnx2x *bp, u32 load_code); | |
273 | ||
274 | /** | |
e8920674 | 275 | * bnx2x_alloc_mem - allocate driver's memory. |
9f6c9258 | 276 | * |
e8920674 | 277 | * @bp: driver handle |
9f6c9258 DK |
278 | */ |
279 | int bnx2x_alloc_mem(struct bnx2x *bp); | |
280 | ||
281 | /** | |
e8920674 | 282 | * bnx2x_free_mem - release driver's memory. |
9f6c9258 | 283 | * |
e8920674 | 284 | * @bp: driver handle |
9f6c9258 DK |
285 | */ |
286 | void bnx2x_free_mem(struct bnx2x *bp); | |
287 | ||
9f6c9258 | 288 | /** |
e8920674 | 289 | * bnx2x_set_num_queues - set number of queues according to mode. |
9f6c9258 | 290 | * |
e8920674 | 291 | * @bp: driver handle |
9f6c9258 | 292 | */ |
d6214d7a | 293 | void bnx2x_set_num_queues(struct bnx2x *bp); |
9f6c9258 DK |
294 | |
295 | /** | |
e8920674 DK |
296 | * bnx2x_chip_cleanup - cleanup chip internals. |
297 | * | |
298 | * @bp: driver handle | |
299 | * @unload_mode: COMMON, PORT, FUNCTION | |
300 | * | |
9f6c9258 | 301 | * - Cleanup MAC configuration. |
e8920674 | 302 | * - Closes clients. |
9f6c9258 | 303 | * - etc. |
9f6c9258 DK |
304 | */ |
305 | void bnx2x_chip_cleanup(struct bnx2x *bp, int unload_mode); | |
306 | ||
307 | /** | |
e8920674 | 308 | * bnx2x_acquire_hw_lock - acquire HW lock. |
9f6c9258 | 309 | * |
e8920674 DK |
310 | * @bp: driver handle |
311 | * @resource: resource bit which was locked | |
9f6c9258 DK |
312 | */ |
313 | int bnx2x_acquire_hw_lock(struct bnx2x *bp, u32 resource); | |
314 | ||
315 | /** | |
e8920674 | 316 | * bnx2x_release_hw_lock - release HW lock. |
9f6c9258 | 317 | * |
e8920674 DK |
318 | * @bp: driver handle |
319 | * @resource: resource bit which was locked | |
9f6c9258 DK |
320 | */ |
321 | int bnx2x_release_hw_lock(struct bnx2x *bp, u32 resource); | |
322 | ||
323 | /** | |
e8920674 DK |
324 | * bnx2x_set_eth_mac - configure eth MAC address in the HW |
325 | * | |
326 | * @bp: driver handle | |
327 | * @set: set or clear | |
9f6c9258 | 328 | * |
e8920674 | 329 | * Configures according to the value in netdev->dev_addr. |
9f6c9258 | 330 | */ |
619c5cb6 | 331 | int bnx2x_set_eth_mac(struct bnx2x *bp, bool set); |
9f6c9258 | 332 | |
ec6ba945 | 333 | /** |
619c5cb6 | 334 | * bnx2x_set_rx_mode - set MAC filtering configurations. |
ec6ba945 | 335 | * |
619c5cb6 | 336 | * @dev: netdevice |
ec6ba945 | 337 | * |
619c5cb6 VZ |
338 | * called with netif_tx_lock from dev_mcast.c |
339 | * If bp->state is OPEN, should be called with | |
340 | * netif_addr_lock_bh() | |
ec6ba945 | 341 | */ |
619c5cb6 | 342 | void bnx2x_set_rx_mode(struct net_device *dev); |
ec6ba945 VZ |
343 | |
344 | /** | |
619c5cb6 | 345 | * bnx2x_set_storm_rx_mode - configure MAC filtering rules in a FW. |
ec6ba945 | 346 | * |
e8920674 | 347 | * @bp: driver handle |
619c5cb6 VZ |
348 | * |
349 | * If bp->state is OPEN, should be called with | |
350 | * netif_addr_lock_bh(). | |
ec6ba945 | 351 | */ |
619c5cb6 | 352 | void bnx2x_set_storm_rx_mode(struct bnx2x *bp); |
ec6ba945 | 353 | |
9f6c9258 | 354 | /** |
619c5cb6 | 355 | * bnx2x_set_q_rx_mode - configures rx_mode for a single queue. |
9f6c9258 | 356 | * |
619c5cb6 VZ |
357 | * @bp: driver handle |
358 | * @cl_id: client id | |
359 | * @rx_mode_flags: rx mode configuration | |
360 | * @rx_accept_flags: rx accept configuration | |
361 | * @tx_accept_flags: tx accept configuration (tx switch) | |
362 | * @ramrod_flags: ramrod configuration | |
9f6c9258 | 363 | */ |
619c5cb6 VZ |
364 | void bnx2x_set_q_rx_mode(struct bnx2x *bp, u8 cl_id, |
365 | unsigned long rx_mode_flags, | |
366 | unsigned long rx_accept_flags, | |
367 | unsigned long tx_accept_flags, | |
368 | unsigned long ramrod_flags); | |
9f6c9258 | 369 | |
9f6c9258 DK |
370 | /* Parity errors related */ |
371 | void bnx2x_inc_load_cnt(struct bnx2x *bp); | |
372 | u32 bnx2x_dec_load_cnt(struct bnx2x *bp); | |
373 | bool bnx2x_chk_parity_attn(struct bnx2x *bp); | |
374 | bool bnx2x_reset_is_done(struct bnx2x *bp); | |
375 | void bnx2x_disable_close_the_gate(struct bnx2x *bp); | |
376 | ||
9f6c9258 | 377 | /** |
e8920674 | 378 | * bnx2x_sp_event - handle ramrods completion. |
9f6c9258 | 379 | * |
e8920674 DK |
380 | * @fp: fastpath handle for the event |
381 | * @rr_cqe: eth_rx_cqe | |
9f6c9258 | 382 | */ |
f85582f8 | 383 | void bnx2x_sp_event(struct bnx2x_fastpath *fp, union eth_rx_cqe *rr_cqe); |
9f6c9258 | 384 | |
523224a3 | 385 | /** |
e8920674 | 386 | * bnx2x_ilt_set_info - prepare ILT configurations. |
523224a3 | 387 | * |
e8920674 | 388 | * @bp: driver handle |
523224a3 DK |
389 | */ |
390 | void bnx2x_ilt_set_info(struct bnx2x *bp); | |
9f6c9258 | 391 | |
e4901dde | 392 | /** |
e8920674 | 393 | * bnx2x_dcbx_init - initialize dcbx protocol. |
e4901dde | 394 | * |
e8920674 | 395 | * @bp: driver handle |
e4901dde VZ |
396 | */ |
397 | void bnx2x_dcbx_init(struct bnx2x *bp); | |
398 | ||
f85582f8 | 399 | /** |
e8920674 | 400 | * bnx2x_set_power_state - set power state to the requested value. |
f85582f8 | 401 | * |
e8920674 DK |
402 | * @bp: driver handle |
403 | * @state: required state D0 or D3hot | |
f85582f8 | 404 | * |
e8920674 | 405 | * Currently only D0 and D3hot are supported. |
f85582f8 DK |
406 | */ |
407 | int bnx2x_set_power_state(struct bnx2x *bp, pci_power_t state); | |
408 | ||
e3835b99 | 409 | /** |
e8920674 | 410 | * bnx2x_update_max_mf_config - update MAX part of MF configuration in HW. |
e3835b99 | 411 | * |
e8920674 DK |
412 | * @bp: driver handle |
413 | * @value: new value | |
e3835b99 DK |
414 | */ |
415 | void bnx2x_update_max_mf_config(struct bnx2x *bp, u32 value); | |
619c5cb6 VZ |
416 | /* Error handling */ |
417 | void bnx2x_panic_dump(struct bnx2x *bp); | |
e3835b99 | 418 | |
7a25cc73 DK |
419 | void bnx2x_fw_dump_lvl(struct bnx2x *bp, const char *lvl); |
420 | ||
f85582f8 DK |
421 | /* dev_close main block */ |
422 | int bnx2x_nic_unload(struct bnx2x *bp, int unload_mode); | |
423 | ||
424 | /* dev_open main block */ | |
425 | int bnx2x_nic_load(struct bnx2x *bp, int load_mode); | |
426 | ||
427 | /* hard_xmit callback */ | |
428 | netdev_tx_t bnx2x_start_xmit(struct sk_buff *skb, struct net_device *dev); | |
429 | ||
8307fa3e VZ |
430 | /* select_queue callback */ |
431 | u16 bnx2x_select_queue(struct net_device *dev, struct sk_buff *skb); | |
432 | ||
a9fccec7 DK |
433 | /* reload helper */ |
434 | int bnx2x_reload_if_running(struct net_device *dev); | |
435 | ||
f85582f8 DK |
436 | int bnx2x_change_mac_addr(struct net_device *dev, void *p); |
437 | ||
438 | /* NAPI poll Rx part */ | |
439 | int bnx2x_rx_int(struct bnx2x_fastpath *fp, int budget); | |
440 | ||
619c5cb6 VZ |
441 | void bnx2x_update_rx_prod(struct bnx2x *bp, struct bnx2x_fastpath *fp, |
442 | u16 bd_prod, u16 rx_comp_prod, u16 rx_sge_prod); | |
443 | ||
f85582f8 DK |
444 | /* NAPI poll Tx part */ |
445 | int bnx2x_tx_int(struct bnx2x_fastpath *fp); | |
446 | ||
447 | /* suspend/resume callbacks */ | |
448 | int bnx2x_suspend(struct pci_dev *pdev, pm_message_t state); | |
449 | int bnx2x_resume(struct pci_dev *pdev); | |
450 | ||
451 | /* Release IRQ vectors */ | |
452 | void bnx2x_free_irq(struct bnx2x *bp); | |
453 | ||
b3b83c3f DK |
454 | void bnx2x_free_fp_mem(struct bnx2x *bp); |
455 | int bnx2x_alloc_fp_mem(struct bnx2x *bp); | |
f85582f8 DK |
456 | void bnx2x_init_rx_rings(struct bnx2x *bp); |
457 | void bnx2x_free_skbs(struct bnx2x *bp); | |
458 | void bnx2x_netif_stop(struct bnx2x *bp, int disable_hw); | |
459 | void bnx2x_netif_start(struct bnx2x *bp); | |
460 | ||
d6214d7a | 461 | /** |
e8920674 | 462 | * bnx2x_enable_msix - set msix configuration. |
d6214d7a | 463 | * |
e8920674 | 464 | * @bp: driver handle |
d6214d7a | 465 | * |
e8920674 DK |
466 | * fills msix_table, requests vectors, updates num_queues |
467 | * according to number of available vectors. | |
d6214d7a DK |
468 | */ |
469 | int bnx2x_enable_msix(struct bnx2x *bp); | |
470 | ||
471 | /** | |
e8920674 | 472 | * bnx2x_enable_msi - request msi mode from OS, updated internals accordingly |
d6214d7a | 473 | * |
e8920674 | 474 | * @bp: driver handle |
d6214d7a DK |
475 | */ |
476 | int bnx2x_enable_msi(struct bnx2x *bp); | |
477 | ||
d6214d7a | 478 | /** |
e8920674 | 479 | * bnx2x_poll - NAPI callback |
d6214d7a | 480 | * |
e8920674 DK |
481 | * @napi: napi structure |
482 | * @budget: | |
d6214d7a | 483 | * |
d6214d7a DK |
484 | */ |
485 | int bnx2x_poll(struct napi_struct *napi, int budget); | |
f85582f8 DK |
486 | |
487 | /** | |
e8920674 | 488 | * bnx2x_alloc_mem_bp - allocate memories outsize main driver structure |
f85582f8 | 489 | * |
e8920674 | 490 | * @bp: driver handle |
f85582f8 DK |
491 | */ |
492 | int __devinit bnx2x_alloc_mem_bp(struct bnx2x *bp); | |
e8920674 DK |
493 | |
494 | /** | |
495 | * bnx2x_free_mem_bp - release memories outsize main driver structure | |
496 | * | |
497 | * @bp: driver handle | |
498 | */ | |
f85582f8 DK |
499 | void bnx2x_free_mem_bp(struct bnx2x *bp); |
500 | ||
501 | /** | |
e8920674 | 502 | * bnx2x_change_mtu - change mtu netdev callback |
f85582f8 | 503 | * |
e8920674 DK |
504 | * @dev: net device |
505 | * @new_mtu: requested mtu | |
f85582f8 | 506 | * |
f85582f8 DK |
507 | */ |
508 | int bnx2x_change_mtu(struct net_device *dev, int new_mtu); | |
509 | ||
66371c44 MM |
510 | u32 bnx2x_fix_features(struct net_device *dev, u32 features); |
511 | int bnx2x_set_features(struct net_device *dev, u32 features); | |
512 | ||
f85582f8 | 513 | /** |
e8920674 | 514 | * bnx2x_tx_timeout - tx timeout netdev callback |
f85582f8 | 515 | * |
e8920674 | 516 | * @dev: net device |
f85582f8 DK |
517 | */ |
518 | void bnx2x_tx_timeout(struct net_device *dev); | |
519 | ||
619c5cb6 VZ |
520 | /*********************** Inlines **********************************/ |
521 | /*********************** Fast path ********************************/ | |
9f6c9258 DK |
522 | static inline void bnx2x_update_fpsb_idx(struct bnx2x_fastpath *fp) |
523 | { | |
9f6c9258 | 524 | barrier(); /* status block is written to by the chip */ |
523224a3 | 525 | fp->fp_hc_idx = fp->sb_running_index[SM_RX_ID]; |
9f6c9258 DK |
526 | } |
527 | ||
619c5cb6 VZ |
528 | static inline void bnx2x_update_rx_prod_gen(struct bnx2x *bp, |
529 | struct bnx2x_fastpath *fp, u16 bd_prod, | |
530 | u16 rx_comp_prod, u16 rx_sge_prod, u32 start) | |
9f6c9258 DK |
531 | { |
532 | struct ustorm_eth_rx_producers rx_prods = {0}; | |
619c5cb6 | 533 | u32 i; |
9f6c9258 DK |
534 | |
535 | /* Update producers */ | |
536 | rx_prods.bd_prod = bd_prod; | |
537 | rx_prods.cqe_prod = rx_comp_prod; | |
538 | rx_prods.sge_prod = rx_sge_prod; | |
539 | ||
540 | /* | |
541 | * Make sure that the BD and SGE data is updated before updating the | |
542 | * producers since FW might read the BD/SGE right after the producer | |
543 | * is updated. | |
544 | * This is only applicable for weak-ordered memory model archs such | |
545 | * as IA-64. The following barrier is also mandatory since FW will | |
546 | * assumes BDs must have buffers. | |
547 | */ | |
548 | wmb(); | |
549 | ||
619c5cb6 VZ |
550 | for (i = 0; i < sizeof(rx_prods)/4; i++) |
551 | REG_WR(bp, start + i*4, ((u32 *)&rx_prods)[i]); | |
9f6c9258 DK |
552 | |
553 | mmiowb(); /* keep prod updates ordered */ | |
554 | ||
555 | DP(NETIF_MSG_RX_STATUS, | |
556 | "queue[%d]: wrote bd_prod %u cqe_prod %u sge_prod %u\n", | |
557 | fp->index, bd_prod, rx_comp_prod, rx_sge_prod); | |
558 | } | |
559 | ||
f2e0899f DK |
560 | static inline void bnx2x_igu_ack_sb_gen(struct bnx2x *bp, u8 igu_sb_id, |
561 | u8 segment, u16 index, u8 op, | |
562 | u8 update, u32 igu_addr) | |
563 | { | |
564 | struct igu_regular cmd_data = {0}; | |
565 | ||
566 | cmd_data.sb_id_and_flags = | |
567 | ((index << IGU_REGULAR_SB_INDEX_SHIFT) | | |
568 | (segment << IGU_REGULAR_SEGMENT_ACCESS_SHIFT) | | |
569 | (update << IGU_REGULAR_BUPDATE_SHIFT) | | |
570 | (op << IGU_REGULAR_ENABLE_INT_SHIFT)); | |
571 | ||
572 | DP(NETIF_MSG_HW, "write 0x%08x to IGU addr 0x%x\n", | |
573 | cmd_data.sb_id_and_flags, igu_addr); | |
574 | REG_WR(bp, igu_addr, cmd_data.sb_id_and_flags); | |
575 | ||
576 | /* Make sure that ACK is written */ | |
577 | mmiowb(); | |
578 | barrier(); | |
579 | } | |
580 | ||
619c5cb6 | 581 | static inline void bnx2x_igu_clear_sb_gen(struct bnx2x *bp, u8 func, |
f2e0899f DK |
582 | u8 idu_sb_id, bool is_Pf) |
583 | { | |
584 | u32 data, ctl, cnt = 100; | |
585 | u32 igu_addr_data = IGU_REG_COMMAND_REG_32LSB_DATA; | |
586 | u32 igu_addr_ctl = IGU_REG_COMMAND_REG_CTRL; | |
587 | u32 igu_addr_ack = IGU_REG_CSTORM_TYPE_0_SB_CLEANUP + (idu_sb_id/32)*4; | |
588 | u32 sb_bit = 1 << (idu_sb_id%32); | |
619c5cb6 | 589 | u32 func_encode = func | |
f2e0899f DK |
590 | ((is_Pf == true ? 1 : 0) << IGU_FID_ENCODE_IS_PF_SHIFT); |
591 | u32 addr_encode = IGU_CMD_E2_PROD_UPD_BASE + idu_sb_id; | |
592 | ||
593 | /* Not supported in BC mode */ | |
594 | if (CHIP_INT_MODE_IS_BC(bp)) | |
595 | return; | |
596 | ||
597 | data = (IGU_USE_REGISTER_cstorm_type_0_sb_cleanup | |
598 | << IGU_REGULAR_CLEANUP_TYPE_SHIFT) | | |
599 | IGU_REGULAR_CLEANUP_SET | | |
600 | IGU_REGULAR_BCLEANUP; | |
601 | ||
602 | ctl = addr_encode << IGU_CTRL_REG_ADDRESS_SHIFT | | |
603 | func_encode << IGU_CTRL_REG_FID_SHIFT | | |
604 | IGU_CTRL_CMD_TYPE_WR << IGU_CTRL_REG_TYPE_SHIFT; | |
9f6c9258 | 605 | |
f2e0899f DK |
606 | DP(NETIF_MSG_HW, "write 0x%08x to IGU(via GRC) addr 0x%x\n", |
607 | data, igu_addr_data); | |
608 | REG_WR(bp, igu_addr_data, data); | |
609 | mmiowb(); | |
610 | barrier(); | |
611 | DP(NETIF_MSG_HW, "write 0x%08x to IGU(via GRC) addr 0x%x\n", | |
612 | ctl, igu_addr_ctl); | |
613 | REG_WR(bp, igu_addr_ctl, ctl); | |
614 | mmiowb(); | |
615 | barrier(); | |
9f6c9258 | 616 | |
f2e0899f DK |
617 | /* wait for clean up to finish */ |
618 | while (!(REG_RD(bp, igu_addr_ack) & sb_bit) && --cnt) | |
619 | msleep(20); | |
620 | ||
621 | ||
622 | if (!(REG_RD(bp, igu_addr_ack) & sb_bit)) { | |
623 | DP(NETIF_MSG_HW, "Unable to finish IGU cleanup: " | |
624 | "idu_sb_id %d offset %d bit %d (cnt %d)\n", | |
625 | idu_sb_id, idu_sb_id/32, idu_sb_id%32, cnt); | |
626 | } | |
627 | } | |
628 | ||
629 | static inline void bnx2x_hc_ack_sb(struct bnx2x *bp, u8 sb_id, | |
630 | u8 storm, u16 index, u8 op, u8 update) | |
9f6c9258 DK |
631 | { |
632 | u32 hc_addr = (HC_REG_COMMAND_REG + BP_PORT(bp)*32 + | |
633 | COMMAND_REG_INT_ACK); | |
634 | struct igu_ack_register igu_ack; | |
635 | ||
636 | igu_ack.status_block_index = index; | |
637 | igu_ack.sb_id_and_flags = | |
638 | ((sb_id << IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT) | | |
639 | (storm << IGU_ACK_REGISTER_STORM_ID_SHIFT) | | |
640 | (update << IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT) | | |
641 | (op << IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT)); | |
642 | ||
643 | DP(BNX2X_MSG_OFF, "write 0x%08x to HC addr 0x%x\n", | |
644 | (*(u32 *)&igu_ack), hc_addr); | |
645 | REG_WR(bp, hc_addr, (*(u32 *)&igu_ack)); | |
646 | ||
647 | /* Make sure that ACK is written */ | |
648 | mmiowb(); | |
649 | barrier(); | |
650 | } | |
f2e0899f | 651 | |
f2e0899f DK |
652 | static inline void bnx2x_ack_sb(struct bnx2x *bp, u8 igu_sb_id, u8 storm, |
653 | u16 index, u8 op, u8 update) | |
654 | { | |
655 | if (bp->common.int_block == INT_BLOCK_HC) | |
656 | bnx2x_hc_ack_sb(bp, igu_sb_id, storm, index, op, update); | |
657 | else { | |
658 | u8 segment; | |
659 | ||
660 | if (CHIP_INT_MODE_IS_BC(bp)) | |
661 | segment = storm; | |
662 | else if (igu_sb_id != bp->igu_dsb_id) | |
663 | segment = IGU_SEG_ACCESS_DEF; | |
664 | else if (storm == ATTENTION_ID) | |
665 | segment = IGU_SEG_ACCESS_ATTN; | |
666 | else | |
667 | segment = IGU_SEG_ACCESS_DEF; | |
668 | bnx2x_igu_ack_sb(bp, igu_sb_id, segment, index, op, update); | |
669 | } | |
670 | } | |
671 | ||
672 | static inline u16 bnx2x_hc_ack_int(struct bnx2x *bp) | |
9f6c9258 DK |
673 | { |
674 | u32 hc_addr = (HC_REG_COMMAND_REG + BP_PORT(bp)*32 + | |
675 | COMMAND_REG_SIMD_MASK); | |
676 | u32 result = REG_RD(bp, hc_addr); | |
677 | ||
678 | DP(BNX2X_MSG_OFF, "read 0x%08x from HC addr 0x%x\n", | |
679 | result, hc_addr); | |
680 | ||
f2e0899f | 681 | barrier(); |
9f6c9258 DK |
682 | return result; |
683 | } | |
684 | ||
f2e0899f DK |
685 | static inline u16 bnx2x_igu_ack_int(struct bnx2x *bp) |
686 | { | |
687 | u32 igu_addr = (BAR_IGU_INTMEM + IGU_REG_SISR_MDPC_WMASK_LSB_UPPER*8); | |
688 | u32 result = REG_RD(bp, igu_addr); | |
689 | ||
690 | DP(NETIF_MSG_HW, "read 0x%08x from IGU addr 0x%x\n", | |
691 | result, igu_addr); | |
692 | ||
693 | barrier(); | |
694 | return result; | |
695 | } | |
696 | ||
697 | static inline u16 bnx2x_ack_int(struct bnx2x *bp) | |
698 | { | |
699 | barrier(); | |
700 | if (bp->common.int_block == INT_BLOCK_HC) | |
701 | return bnx2x_hc_ack_int(bp); | |
702 | else | |
703 | return bnx2x_igu_ack_int(bp); | |
704 | } | |
705 | ||
9f6c9258 DK |
706 | static inline int bnx2x_has_tx_work_unload(struct bnx2x_fastpath *fp) |
707 | { | |
708 | /* Tell compiler that consumer and producer can change */ | |
709 | barrier(); | |
807540ba | 710 | return fp->tx_pkt_prod != fp->tx_pkt_cons; |
9f6c9258 DK |
711 | } |
712 | ||
713 | static inline u16 bnx2x_tx_avail(struct bnx2x_fastpath *fp) | |
714 | { | |
715 | s16 used; | |
716 | u16 prod; | |
717 | u16 cons; | |
718 | ||
719 | prod = fp->tx_bd_prod; | |
720 | cons = fp->tx_bd_cons; | |
721 | ||
722 | /* NUM_TX_RINGS = number of "next-page" entries | |
723 | It will be used as a threshold */ | |
724 | used = SUB_S16(prod, cons) + (s16)NUM_TX_RINGS; | |
725 | ||
726 | #ifdef BNX2X_STOP_ON_ERROR | |
727 | WARN_ON(used < 0); | |
728 | WARN_ON(used > fp->bp->tx_ring_size); | |
729 | WARN_ON((fp->bp->tx_ring_size - used) > MAX_TX_AVAIL); | |
730 | #endif | |
731 | ||
732 | return (s16)(fp->bp->tx_ring_size) - used; | |
733 | } | |
734 | ||
735 | static inline int bnx2x_has_tx_work(struct bnx2x_fastpath *fp) | |
736 | { | |
737 | u16 hw_cons; | |
738 | ||
739 | /* Tell compiler that status block fields can change */ | |
740 | barrier(); | |
741 | hw_cons = le16_to_cpu(*fp->tx_cons_sb); | |
742 | return hw_cons != fp->tx_pkt_cons; | |
743 | } | |
744 | ||
523224a3 DK |
745 | static inline int bnx2x_has_rx_work(struct bnx2x_fastpath *fp) |
746 | { | |
747 | u16 rx_cons_sb; | |
748 | ||
749 | /* Tell compiler that status block fields can change */ | |
750 | barrier(); | |
751 | rx_cons_sb = le16_to_cpu(*fp->rx_cons_sb); | |
752 | if ((rx_cons_sb & MAX_RCQ_DESC_CNT) == MAX_RCQ_DESC_CNT) | |
753 | rx_cons_sb++; | |
754 | return (fp->rx_comp_cons != rx_cons_sb); | |
755 | } | |
f85582f8 | 756 | |
f2e0899f | 757 | /** |
619c5cb6 | 758 | * bnx2x_tx_disable - disables tx from stack point of view |
f2e0899f | 759 | * |
e8920674 | 760 | * @bp: driver handle |
f2e0899f DK |
761 | */ |
762 | static inline void bnx2x_tx_disable(struct bnx2x *bp) | |
763 | { | |
764 | netif_tx_disable(bp->dev); | |
765 | netif_carrier_off(bp->dev); | |
766 | } | |
767 | ||
9f6c9258 DK |
768 | static inline void bnx2x_free_rx_sge(struct bnx2x *bp, |
769 | struct bnx2x_fastpath *fp, u16 index) | |
770 | { | |
771 | struct sw_rx_page *sw_buf = &fp->rx_page_ring[index]; | |
772 | struct page *page = sw_buf->page; | |
773 | struct eth_rx_sge *sge = &fp->rx_sge_ring[index]; | |
774 | ||
775 | /* Skip "next page" elements */ | |
776 | if (!page) | |
777 | return; | |
778 | ||
779 | dma_unmap_page(&bp->pdev->dev, dma_unmap_addr(sw_buf, mapping), | |
4bca60f4 | 780 | SGE_PAGE_SIZE*PAGES_PER_SGE, DMA_FROM_DEVICE); |
9f6c9258 DK |
781 | __free_pages(page, PAGES_PER_SGE_SHIFT); |
782 | ||
783 | sw_buf->page = NULL; | |
784 | sge->addr_hi = 0; | |
785 | sge->addr_lo = 0; | |
786 | } | |
787 | ||
d6214d7a DK |
788 | static inline void bnx2x_add_all_napi(struct bnx2x *bp) |
789 | { | |
790 | int i; | |
523224a3 | 791 | |
d6214d7a | 792 | /* Add NAPI objects */ |
619c5cb6 | 793 | for_each_rx_queue(bp, i) |
d6214d7a DK |
794 | netif_napi_add(bp->dev, &bnx2x_fp(bp, i, napi), |
795 | bnx2x_poll, BNX2X_NAPI_WEIGHT); | |
796 | } | |
523224a3 | 797 | |
d6214d7a DK |
798 | static inline void bnx2x_del_all_napi(struct bnx2x *bp) |
799 | { | |
800 | int i; | |
801 | ||
619c5cb6 | 802 | for_each_rx_queue(bp, i) |
d6214d7a DK |
803 | netif_napi_del(&bnx2x_fp(bp, i, napi)); |
804 | } | |
523224a3 | 805 | |
d6214d7a DK |
806 | static inline void bnx2x_disable_msi(struct bnx2x *bp) |
807 | { | |
808 | if (bp->flags & USING_MSIX_FLAG) { | |
809 | pci_disable_msix(bp->pdev); | |
810 | bp->flags &= ~USING_MSIX_FLAG; | |
811 | } else if (bp->flags & USING_MSI_FLAG) { | |
812 | pci_disable_msi(bp->pdev); | |
813 | bp->flags &= ~USING_MSI_FLAG; | |
814 | } | |
815 | } | |
816 | ||
817 | static inline int bnx2x_calc_num_queues(struct bnx2x *bp) | |
818 | { | |
819 | return num_queues ? | |
820 | min_t(int, num_queues, BNX2X_MAX_QUEUES(bp)) : | |
821 | min_t(int, num_online_cpus(), BNX2X_MAX_QUEUES(bp)); | |
822 | } | |
523224a3 DK |
823 | |
824 | static inline void bnx2x_clear_sge_mask_next_elems(struct bnx2x_fastpath *fp) | |
9f6c9258 | 825 | { |
523224a3 | 826 | int i, j; |
9f6c9258 | 827 | |
523224a3 DK |
828 | for (i = 1; i <= NUM_RX_SGE_PAGES; i++) { |
829 | int idx = RX_SGE_CNT * i - 1; | |
830 | ||
831 | for (j = 0; j < 2; j++) { | |
619c5cb6 | 832 | BIT_VEC64_CLEAR_BIT(fp->sge_mask, idx); |
523224a3 DK |
833 | idx--; |
834 | } | |
835 | } | |
836 | } | |
837 | ||
838 | static inline void bnx2x_init_sge_ring_bit_mask(struct bnx2x_fastpath *fp) | |
839 | { | |
840 | /* Set the mask to all 1-s: it's faster to compare to 0 than to 0xf-s */ | |
841 | memset(fp->sge_mask, 0xff, | |
619c5cb6 | 842 | (NUM_RX_SGE >> BIT_VEC64_ELEM_SHIFT)*sizeof(u64)); |
523224a3 DK |
843 | |
844 | /* Clear the two last indices in the page to 1: | |
845 | these are the indices that correspond to the "next" element, | |
846 | hence will never be indicated and should be removed from | |
847 | the calculations. */ | |
848 | bnx2x_clear_sge_mask_next_elems(fp); | |
9f6c9258 DK |
849 | } |
850 | ||
851 | static inline int bnx2x_alloc_rx_sge(struct bnx2x *bp, | |
852 | struct bnx2x_fastpath *fp, u16 index) | |
853 | { | |
854 | struct page *page = alloc_pages(GFP_ATOMIC, PAGES_PER_SGE_SHIFT); | |
855 | struct sw_rx_page *sw_buf = &fp->rx_page_ring[index]; | |
856 | struct eth_rx_sge *sge = &fp->rx_sge_ring[index]; | |
857 | dma_addr_t mapping; | |
858 | ||
859 | if (unlikely(page == NULL)) | |
860 | return -ENOMEM; | |
861 | ||
862 | mapping = dma_map_page(&bp->pdev->dev, page, 0, | |
863 | SGE_PAGE_SIZE*PAGES_PER_SGE, DMA_FROM_DEVICE); | |
864 | if (unlikely(dma_mapping_error(&bp->pdev->dev, mapping))) { | |
865 | __free_pages(page, PAGES_PER_SGE_SHIFT); | |
866 | return -ENOMEM; | |
867 | } | |
868 | ||
869 | sw_buf->page = page; | |
870 | dma_unmap_addr_set(sw_buf, mapping, mapping); | |
871 | ||
872 | sge->addr_hi = cpu_to_le32(U64_HI(mapping)); | |
873 | sge->addr_lo = cpu_to_le32(U64_LO(mapping)); | |
874 | ||
875 | return 0; | |
876 | } | |
f85582f8 | 877 | |
9f6c9258 DK |
878 | static inline int bnx2x_alloc_rx_skb(struct bnx2x *bp, |
879 | struct bnx2x_fastpath *fp, u16 index) | |
880 | { | |
881 | struct sk_buff *skb; | |
882 | struct sw_rx_bd *rx_buf = &fp->rx_buf_ring[index]; | |
883 | struct eth_rx_bd *rx_bd = &fp->rx_desc_ring[index]; | |
884 | dma_addr_t mapping; | |
885 | ||
a8c94b91 | 886 | skb = netdev_alloc_skb(bp->dev, fp->rx_buf_size); |
9f6c9258 DK |
887 | if (unlikely(skb == NULL)) |
888 | return -ENOMEM; | |
889 | ||
a8c94b91 | 890 | mapping = dma_map_single(&bp->pdev->dev, skb->data, fp->rx_buf_size, |
9f6c9258 DK |
891 | DMA_FROM_DEVICE); |
892 | if (unlikely(dma_mapping_error(&bp->pdev->dev, mapping))) { | |
40955532 | 893 | dev_kfree_skb_any(skb); |
9f6c9258 DK |
894 | return -ENOMEM; |
895 | } | |
896 | ||
897 | rx_buf->skb = skb; | |
898 | dma_unmap_addr_set(rx_buf, mapping, mapping); | |
899 | ||
900 | rx_bd->addr_hi = cpu_to_le32(U64_HI(mapping)); | |
901 | rx_bd->addr_lo = cpu_to_le32(U64_LO(mapping)); | |
902 | ||
903 | return 0; | |
904 | } | |
905 | ||
906 | /* note that we are not allocating a new skb, | |
907 | * we are just moving one from cons to prod | |
908 | * we are not creating a new mapping, | |
909 | * so there is no need to check for dma_mapping_error(). | |
910 | */ | |
911 | static inline void bnx2x_reuse_rx_skb(struct bnx2x_fastpath *fp, | |
749a8503 | 912 | u16 cons, u16 prod) |
9f6c9258 DK |
913 | { |
914 | struct bnx2x *bp = fp->bp; | |
915 | struct sw_rx_bd *cons_rx_buf = &fp->rx_buf_ring[cons]; | |
916 | struct sw_rx_bd *prod_rx_buf = &fp->rx_buf_ring[prod]; | |
917 | struct eth_rx_bd *cons_bd = &fp->rx_desc_ring[cons]; | |
918 | struct eth_rx_bd *prod_bd = &fp->rx_desc_ring[prod]; | |
919 | ||
920 | dma_sync_single_for_device(&bp->pdev->dev, | |
921 | dma_unmap_addr(cons_rx_buf, mapping), | |
922 | RX_COPY_THRESH, DMA_FROM_DEVICE); | |
923 | ||
9f6c9258 DK |
924 | dma_unmap_addr_set(prod_rx_buf, mapping, |
925 | dma_unmap_addr(cons_rx_buf, mapping)); | |
619c5cb6 | 926 | prod_rx_buf->skb = cons_rx_buf->skb; |
9f6c9258 DK |
927 | *prod_bd = *cons_bd; |
928 | } | |
f85582f8 | 929 | |
619c5cb6 VZ |
930 | /************************* Init ******************************************/ |
931 | ||
932 | /** | |
933 | * bnx2x_func_start - init function | |
934 | * | |
935 | * @bp: driver handle | |
936 | * | |
937 | * Must be called before sending CLIENT_SETUP for the first client. | |
938 | */ | |
939 | static inline int bnx2x_func_start(struct bnx2x *bp) | |
940 | { | |
941 | struct bnx2x_func_state_params func_params = {0}; | |
942 | struct bnx2x_func_start_params *start_params = | |
943 | &func_params.params.start; | |
944 | ||
945 | /* Prepare parameters for function state transitions */ | |
946 | __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags); | |
947 | ||
948 | func_params.f_obj = &bp->func_obj; | |
949 | func_params.cmd = BNX2X_F_CMD_START; | |
950 | ||
951 | /* Function parameters */ | |
952 | start_params->mf_mode = bp->mf_mode; | |
953 | start_params->sd_vlan_tag = bp->mf_ov; | |
954 | start_params->network_cos_mode = OVERRIDE_COS; | |
955 | ||
956 | return bnx2x_func_state_change(bp, &func_params); | |
957 | } | |
958 | ||
959 | ||
960 | /** | |
961 | * bnx2x_set_fw_mac_addr - fill in a MAC address in FW format | |
962 | * | |
963 | * @fw_hi: pointer to upper part | |
964 | * @fw_mid: pointer to middle part | |
965 | * @fw_lo: pointer to lower part | |
966 | * @mac: pointer to MAC address | |
967 | */ | |
968 | static inline void bnx2x_set_fw_mac_addr(u16 *fw_hi, u16 *fw_mid, u16 *fw_lo, | |
969 | u8 *mac) | |
970 | { | |
971 | ((u8 *)fw_hi)[0] = mac[1]; | |
972 | ((u8 *)fw_hi)[1] = mac[0]; | |
973 | ((u8 *)fw_mid)[0] = mac[3]; | |
974 | ((u8 *)fw_mid)[1] = mac[2]; | |
975 | ((u8 *)fw_lo)[0] = mac[5]; | |
976 | ((u8 *)fw_lo)[1] = mac[4]; | |
977 | } | |
978 | ||
523224a3 DK |
979 | static inline void bnx2x_free_rx_sge_range(struct bnx2x *bp, |
980 | struct bnx2x_fastpath *fp, int last) | |
9f6c9258 | 981 | { |
523224a3 | 982 | int i; |
9f6c9258 | 983 | |
b3b83c3f DK |
984 | if (fp->disable_tpa) |
985 | return; | |
986 | ||
523224a3 DK |
987 | for (i = 0; i < last; i++) |
988 | bnx2x_free_rx_sge(bp, fp, i); | |
9f6c9258 DK |
989 | } |
990 | ||
9f6c9258 DK |
991 | static inline void bnx2x_free_tpa_pool(struct bnx2x *bp, |
992 | struct bnx2x_fastpath *fp, int last) | |
993 | { | |
994 | int i; | |
995 | ||
996 | for (i = 0; i < last; i++) { | |
619c5cb6 VZ |
997 | struct bnx2x_agg_info *tpa_info = &fp->tpa_info[i]; |
998 | struct sw_rx_bd *first_buf = &tpa_info->first_buf; | |
999 | struct sk_buff *skb = first_buf->skb; | |
9f6c9258 DK |
1000 | |
1001 | if (skb == NULL) { | |
1002 | DP(NETIF_MSG_IFDOWN, "tpa bin %d empty on free\n", i); | |
1003 | continue; | |
1004 | } | |
619c5cb6 | 1005 | if (tpa_info->tpa_state == BNX2X_TPA_START) |
9f6c9258 | 1006 | dma_unmap_single(&bp->pdev->dev, |
619c5cb6 | 1007 | dma_unmap_addr(first_buf, mapping), |
a8c94b91 | 1008 | fp->rx_buf_size, DMA_FROM_DEVICE); |
9f6c9258 | 1009 | dev_kfree_skb(skb); |
619c5cb6 | 1010 | first_buf->skb = NULL; |
9f6c9258 DK |
1011 | } |
1012 | } | |
1013 | ||
b3b83c3f | 1014 | static inline void bnx2x_init_tx_ring_one(struct bnx2x_fastpath *fp) |
9f6c9258 | 1015 | { |
b3b83c3f | 1016 | int i; |
9f6c9258 | 1017 | |
b3b83c3f DK |
1018 | for (i = 1; i <= NUM_TX_RINGS; i++) { |
1019 | struct eth_tx_next_bd *tx_next_bd = | |
1020 | &fp->tx_desc_ring[TX_DESC_CNT * i - 1].next_bd; | |
9f6c9258 | 1021 | |
b3b83c3f DK |
1022 | tx_next_bd->addr_hi = |
1023 | cpu_to_le32(U64_HI(fp->tx_desc_mapping + | |
1024 | BCM_PAGE_SIZE*(i % NUM_TX_RINGS))); | |
1025 | tx_next_bd->addr_lo = | |
1026 | cpu_to_le32(U64_LO(fp->tx_desc_mapping + | |
1027 | BCM_PAGE_SIZE*(i % NUM_TX_RINGS))); | |
1028 | } | |
9f6c9258 | 1029 | |
b3b83c3f DK |
1030 | SET_FLAG(fp->tx_db.data.header.header, DOORBELL_HDR_DB_TYPE, 1); |
1031 | fp->tx_db.data.zero_fill1 = 0; | |
1032 | fp->tx_db.data.prod = 0; | |
9f6c9258 | 1033 | |
b3b83c3f DK |
1034 | fp->tx_pkt_prod = 0; |
1035 | fp->tx_pkt_cons = 0; | |
1036 | fp->tx_bd_prod = 0; | |
1037 | fp->tx_bd_cons = 0; | |
1038 | fp->tx_pkt = 0; | |
1039 | } | |
9f6c9258 | 1040 | |
b3b83c3f DK |
1041 | static inline void bnx2x_init_tx_rings(struct bnx2x *bp) |
1042 | { | |
1043 | int i; | |
1044 | ||
1045 | for_each_tx_queue(bp, i) | |
1046 | bnx2x_init_tx_ring_one(&bp->fp[i]); | |
9f6c9258 | 1047 | } |
f85582f8 | 1048 | |
523224a3 | 1049 | static inline void bnx2x_set_next_page_rx_bd(struct bnx2x_fastpath *fp) |
9f6c9258 | 1050 | { |
523224a3 | 1051 | int i; |
9f6c9258 | 1052 | |
523224a3 DK |
1053 | for (i = 1; i <= NUM_RX_RINGS; i++) { |
1054 | struct eth_rx_bd *rx_bd; | |
1055 | ||
1056 | rx_bd = &fp->rx_desc_ring[RX_DESC_CNT * i - 2]; | |
1057 | rx_bd->addr_hi = | |
1058 | cpu_to_le32(U64_HI(fp->rx_desc_mapping + | |
1059 | BCM_PAGE_SIZE*(i % NUM_RX_RINGS))); | |
1060 | rx_bd->addr_lo = | |
1061 | cpu_to_le32(U64_LO(fp->rx_desc_mapping + | |
1062 | BCM_PAGE_SIZE*(i % NUM_RX_RINGS))); | |
1063 | } | |
9f6c9258 DK |
1064 | } |
1065 | ||
523224a3 DK |
1066 | static inline void bnx2x_set_next_page_sgl(struct bnx2x_fastpath *fp) |
1067 | { | |
1068 | int i; | |
1069 | ||
1070 | for (i = 1; i <= NUM_RX_SGE_PAGES; i++) { | |
1071 | struct eth_rx_sge *sge; | |
1072 | ||
1073 | sge = &fp->rx_sge_ring[RX_SGE_CNT * i - 2]; | |
1074 | sge->addr_hi = | |
1075 | cpu_to_le32(U64_HI(fp->rx_sge_mapping + | |
1076 | BCM_PAGE_SIZE*(i % NUM_RX_SGE_PAGES))); | |
1077 | ||
1078 | sge->addr_lo = | |
1079 | cpu_to_le32(U64_LO(fp->rx_sge_mapping + | |
1080 | BCM_PAGE_SIZE*(i % NUM_RX_SGE_PAGES))); | |
1081 | } | |
1082 | } | |
1083 | ||
1084 | static inline void bnx2x_set_next_page_rx_cq(struct bnx2x_fastpath *fp) | |
1085 | { | |
1086 | int i; | |
1087 | for (i = 1; i <= NUM_RCQ_RINGS; i++) { | |
1088 | struct eth_rx_cqe_next_page *nextpg; | |
1089 | ||
1090 | nextpg = (struct eth_rx_cqe_next_page *) | |
1091 | &fp->rx_comp_ring[RCQ_DESC_CNT * i - 1]; | |
1092 | nextpg->addr_hi = | |
1093 | cpu_to_le32(U64_HI(fp->rx_comp_mapping + | |
1094 | BCM_PAGE_SIZE*(i % NUM_RCQ_RINGS))); | |
1095 | nextpg->addr_lo = | |
1096 | cpu_to_le32(U64_LO(fp->rx_comp_mapping + | |
1097 | BCM_PAGE_SIZE*(i % NUM_RCQ_RINGS))); | |
1098 | } | |
1099 | } | |
1100 | ||
b3b83c3f DK |
1101 | /* Returns the number of actually allocated BDs */ |
1102 | static inline int bnx2x_alloc_rx_bds(struct bnx2x_fastpath *fp, | |
1103 | int rx_ring_size) | |
1104 | { | |
1105 | struct bnx2x *bp = fp->bp; | |
1106 | u16 ring_prod, cqe_ring_prod; | |
1107 | int i; | |
1108 | ||
1109 | fp->rx_comp_cons = 0; | |
1110 | cqe_ring_prod = ring_prod = 0; | |
1111 | ||
1112 | /* This routine is called only during fo init so | |
1113 | * fp->eth_q_stats.rx_skb_alloc_failed = 0 | |
1114 | */ | |
1115 | for (i = 0; i < rx_ring_size; i++) { | |
1116 | if (bnx2x_alloc_rx_skb(bp, fp, ring_prod) < 0) { | |
1117 | fp->eth_q_stats.rx_skb_alloc_failed++; | |
1118 | continue; | |
1119 | } | |
1120 | ring_prod = NEXT_RX_IDX(ring_prod); | |
1121 | cqe_ring_prod = NEXT_RCQ_IDX(cqe_ring_prod); | |
1122 | WARN_ON(ring_prod <= (i - fp->eth_q_stats.rx_skb_alloc_failed)); | |
1123 | } | |
1124 | ||
1125 | if (fp->eth_q_stats.rx_skb_alloc_failed) | |
1126 | BNX2X_ERR("was only able to allocate " | |
1127 | "%d rx skbs on queue[%d]\n", | |
1128 | (i - fp->eth_q_stats.rx_skb_alloc_failed), fp->index); | |
1129 | ||
1130 | fp->rx_bd_prod = ring_prod; | |
1131 | /* Limit the CQE producer by the CQE ring size */ | |
1132 | fp->rx_comp_prod = min_t(u16, NUM_RCQ_RINGS*RCQ_DESC_CNT, | |
1133 | cqe_ring_prod); | |
1134 | fp->rx_pkt = fp->rx_calls = 0; | |
1135 | ||
1136 | return i - fp->eth_q_stats.rx_skb_alloc_failed; | |
1137 | } | |
1138 | ||
619c5cb6 VZ |
1139 | /* Statistics ID are global per chip/path, while Client IDs for E1x are per |
1140 | * port. | |
1141 | */ | |
1142 | static inline u8 bnx2x_stats_id(struct bnx2x_fastpath *fp) | |
1143 | { | |
1144 | if (!CHIP_IS_E1x(fp->bp)) | |
1145 | return fp->cl_id; | |
1146 | else | |
1147 | return fp->cl_id + BP_PORT(fp->bp) * FP_SB_MAX_E1x; | |
1148 | } | |
1149 | ||
1150 | static inline void bnx2x_init_vlan_mac_fp_objs(struct bnx2x_fastpath *fp, | |
1151 | bnx2x_obj_type obj_type) | |
1152 | { | |
1153 | struct bnx2x *bp = fp->bp; | |
1154 | ||
1155 | /* Configure classification DBs */ | |
1156 | bnx2x_init_mac_obj(bp, &fp->mac_obj, fp->cl_id, fp->cid, | |
1157 | BP_FUNC(bp), bnx2x_sp(bp, mac_rdata), | |
1158 | bnx2x_sp_mapping(bp, mac_rdata), | |
1159 | BNX2X_FILTER_MAC_PENDING, | |
1160 | &bp->sp_state, obj_type, | |
1161 | &bp->macs_pool); | |
1162 | } | |
1163 | ||
1164 | /** | |
1165 | * bnx2x_get_path_func_num - get number of active functions | |
1166 | * | |
1167 | * @bp: driver handle | |
1168 | * | |
1169 | * Calculates the number of active (not hidden) functions on the | |
1170 | * current path. | |
1171 | */ | |
1172 | static inline u8 bnx2x_get_path_func_num(struct bnx2x *bp) | |
1173 | { | |
1174 | u8 func_num = 0, i; | |
1175 | ||
1176 | /* 57710 has only one function per-port */ | |
1177 | if (CHIP_IS_E1(bp)) | |
1178 | return 1; | |
1179 | ||
1180 | /* Calculate a number of functions enabled on the current | |
1181 | * PATH/PORT. | |
1182 | */ | |
1183 | if (CHIP_REV_IS_SLOW(bp)) { | |
1184 | if (IS_MF(bp)) | |
1185 | func_num = 4; | |
1186 | else | |
1187 | func_num = 2; | |
1188 | } else { | |
1189 | for (i = 0; i < E1H_FUNC_MAX / 2; i++) { | |
1190 | u32 func_config = | |
1191 | MF_CFG_RD(bp, | |
1192 | func_mf_config[BP_PORT(bp) + 2 * i]. | |
1193 | config); | |
1194 | func_num += | |
1195 | ((func_config & FUNC_MF_CFG_FUNC_HIDE) ? 0 : 1); | |
1196 | } | |
1197 | } | |
1198 | ||
1199 | WARN_ON(!func_num); | |
1200 | ||
1201 | return func_num; | |
1202 | } | |
1203 | ||
1204 | static inline void bnx2x_init_bp_objs(struct bnx2x *bp) | |
1205 | { | |
1206 | /* RX_MODE controlling object */ | |
1207 | bnx2x_init_rx_mode_obj(bp, &bp->rx_mode_obj); | |
1208 | ||
1209 | /* multicast configuration controlling object */ | |
1210 | bnx2x_init_mcast_obj(bp, &bp->mcast_obj, bp->fp->cl_id, bp->fp->cid, | |
1211 | BP_FUNC(bp), BP_FUNC(bp), | |
1212 | bnx2x_sp(bp, mcast_rdata), | |
1213 | bnx2x_sp_mapping(bp, mcast_rdata), | |
1214 | BNX2X_FILTER_MCAST_PENDING, &bp->sp_state, | |
1215 | BNX2X_OBJ_TYPE_RX); | |
1216 | ||
1217 | /* Setup CAM credit pools */ | |
1218 | bnx2x_init_mac_credit_pool(bp, &bp->macs_pool, BP_FUNC(bp), | |
1219 | bnx2x_get_path_func_num(bp)); | |
1220 | ||
1221 | /* RSS configuration object */ | |
1222 | bnx2x_init_rss_config_obj(bp, &bp->rss_conf_obj, bp->fp->cl_id, | |
1223 | bp->fp->cid, BP_FUNC(bp), BP_FUNC(bp), | |
1224 | bnx2x_sp(bp, rss_rdata), | |
1225 | bnx2x_sp_mapping(bp, rss_rdata), | |
1226 | BNX2X_FILTER_RSS_CONF_PENDING, &bp->sp_state, | |
1227 | BNX2X_OBJ_TYPE_RX); | |
1228 | } | |
1229 | ||
1230 | static inline u8 bnx2x_fp_qzone_id(struct bnx2x_fastpath *fp) | |
1231 | { | |
1232 | if (CHIP_IS_E1x(fp->bp)) | |
1233 | return fp->cl_id + BP_PORT(fp->bp) * ETH_MAX_RX_CLIENTS_E1H; | |
1234 | else | |
1235 | return fp->cl_id; | |
1236 | } | |
1237 | ||
1238 | static inline u32 bnx2x_rx_ustorm_prods_offset(struct bnx2x_fastpath *fp) | |
1239 | { | |
1240 | struct bnx2x *bp = fp->bp; | |
1241 | ||
1242 | if (!CHIP_IS_E1x(bp)) | |
1243 | return USTORM_RX_PRODS_E2_OFFSET(fp->cl_qzone_id); | |
1244 | else | |
1245 | return USTORM_RX_PRODS_E1X_OFFSET(BP_PORT(bp), fp->cl_id); | |
1246 | } | |
1247 | ||
1248 | ||
ec6ba945 | 1249 | #ifdef BCM_CNIC |
619c5cb6 VZ |
1250 | static inline u8 bnx2x_cnic_eth_cl_id(struct bnx2x *bp, u8 cl_idx) |
1251 | { | |
1252 | return bp->cnic_base_cl_id + cl_idx + | |
1253 | (bp->pf_num >> 1) * NONE_ETH_CONTEXT_USE; | |
1254 | } | |
1255 | ||
1256 | static inline u8 bnx2x_cnic_fw_sb_id(struct bnx2x *bp) | |
1257 | { | |
1258 | ||
1259 | /* the 'first' id is allocated for the cnic */ | |
1260 | return bp->base_fw_ndsb; | |
1261 | } | |
1262 | ||
1263 | static inline u8 bnx2x_cnic_igu_sb_id(struct bnx2x *bp) | |
1264 | { | |
1265 | return bp->igu_base_sb; | |
1266 | } | |
1267 | ||
1268 | ||
ec6ba945 VZ |
1269 | static inline void bnx2x_init_fcoe_fp(struct bnx2x *bp) |
1270 | { | |
619c5cb6 VZ |
1271 | struct bnx2x_fastpath *fp = bnx2x_fcoe_fp(bp); |
1272 | unsigned long q_type = 0; | |
1273 | ||
1274 | bnx2x_fcoe(bp, cl_id) = bnx2x_cnic_eth_cl_id(bp, | |
1275 | BNX2X_FCOE_ETH_CL_ID_IDX); | |
1276 | /** Current BNX2X_FCOE_ETH_CID deffinition implies not more than | |
1277 | * 16 ETH clients per function when CNIC is enabled! | |
1278 | * | |
1279 | * Fix it ASAP!!! | |
1280 | */ | |
ec6ba945 VZ |
1281 | bnx2x_fcoe(bp, cid) = BNX2X_FCOE_ETH_CID; |
1282 | bnx2x_fcoe(bp, fw_sb_id) = DEF_SB_ID; | |
1283 | bnx2x_fcoe(bp, igu_sb_id) = bp->igu_dsb_id; | |
1284 | bnx2x_fcoe(bp, bp) = bp; | |
ec6ba945 VZ |
1285 | bnx2x_fcoe(bp, index) = FCOE_IDX; |
1286 | bnx2x_fcoe(bp, rx_cons_sb) = BNX2X_FCOE_L2_RX_INDEX; | |
1287 | bnx2x_fcoe(bp, tx_cons_sb) = BNX2X_FCOE_L2_TX_INDEX; | |
1288 | /* qZone id equals to FW (per path) client id */ | |
619c5cb6 | 1289 | bnx2x_fcoe(bp, cl_qzone_id) = bnx2x_fp_qzone_id(fp); |
ec6ba945 | 1290 | /* init shortcut */ |
619c5cb6 VZ |
1291 | bnx2x_fcoe(bp, ustorm_rx_prods_offset) = |
1292 | bnx2x_rx_ustorm_prods_offset(fp); | |
1293 | ||
1294 | /* Configure Queue State object */ | |
1295 | __set_bit(BNX2X_Q_TYPE_HAS_RX, &q_type); | |
1296 | __set_bit(BNX2X_Q_TYPE_HAS_TX, &q_type); | |
1297 | bnx2x_init_queue_obj(bp, &fp->q_obj, fp->cl_id, fp->cid, BP_FUNC(bp), | |
1298 | bnx2x_sp(bp, q_rdata), bnx2x_sp_mapping(bp, q_rdata), | |
1299 | q_type); | |
1300 | ||
1301 | DP(NETIF_MSG_IFUP, "queue[%d]: bnx2x_init_sb(%p,%p) cl_id %d fw_sb %d " | |
1302 | "igu_sb %d\n", | |
1303 | fp->index, bp, fp->status_blk.e2_sb, fp->cl_id, fp->fw_sb_id, | |
1304 | fp->igu_sb_id); | |
ec6ba945 VZ |
1305 | } |
1306 | #endif | |
523224a3 | 1307 | |
619c5cb6 VZ |
1308 | static inline int bnx2x_clean_tx_queue(struct bnx2x *bp, |
1309 | struct bnx2x_fastpath *fp) | |
1310 | { | |
1311 | int cnt = 1000; | |
1312 | ||
1313 | while (bnx2x_has_tx_work_unload(fp)) { | |
1314 | if (!cnt) { | |
1315 | BNX2X_ERR("timeout waiting for queue[%d]: " | |
1316 | "fp->tx_pkt_prod(%d) != fp->tx_pkt_cons(%d)\n", | |
1317 | fp->index, fp->tx_pkt_prod, fp->tx_pkt_cons); | |
1318 | #ifdef BNX2X_STOP_ON_ERROR | |
1319 | bnx2x_panic(); | |
1320 | return -EBUSY; | |
1321 | #else | |
1322 | break; | |
1323 | #endif | |
1324 | } | |
1325 | cnt--; | |
1326 | usleep_range(1000, 1000); | |
1327 | } | |
1328 | ||
1329 | return 0; | |
1330 | } | |
1331 | ||
1ac9e428 YR |
1332 | int bnx2x_get_link_cfg_idx(struct bnx2x *bp); |
1333 | ||
523224a3 DK |
1334 | static inline void __storm_memset_struct(struct bnx2x *bp, |
1335 | u32 addr, size_t size, u32 *data) | |
1336 | { | |
1337 | int i; | |
1338 | for (i = 0; i < size/4; i++) | |
1339 | REG_WR(bp, addr + (i * 4), data[i]); | |
1340 | } | |
1341 | ||
619c5cb6 VZ |
1342 | static inline void storm_memset_func_cfg(struct bnx2x *bp, |
1343 | struct tstorm_eth_function_common_config *tcfg, | |
1344 | u16 abs_fid) | |
523224a3 | 1345 | { |
619c5cb6 | 1346 | size_t size = sizeof(struct tstorm_eth_function_common_config); |
523224a3 DK |
1347 | |
1348 | u32 addr = BAR_TSTRORM_INTMEM + | |
619c5cb6 | 1349 | TSTORM_FUNCTION_COMMON_CONFIG_OFFSET(abs_fid); |
523224a3 | 1350 | |
619c5cb6 | 1351 | __storm_memset_struct(bp, addr, size, (u32 *)tcfg); |
523224a3 DK |
1352 | } |
1353 | ||
1354 | static inline void storm_memset_cmng(struct bnx2x *bp, | |
1355 | struct cmng_struct_per_port *cmng, | |
1356 | u8 port) | |
1357 | { | |
619c5cb6 | 1358 | size_t size = sizeof(struct cmng_struct_per_port); |
523224a3 DK |
1359 | |
1360 | u32 addr = BAR_XSTRORM_INTMEM + | |
1361 | XSTORM_CMNG_PER_PORT_VARS_OFFSET(port); | |
1362 | ||
1363 | __storm_memset_struct(bp, addr, size, (u32 *)cmng); | |
619c5cb6 VZ |
1364 | } |
1365 | ||
1366 | /** | |
1367 | * bnx2x_wait_sp_comp - wait for the outstanding SP commands. | |
1368 | * | |
1369 | * @bp: driver handle | |
1370 | * @mask: bits that need to be cleared | |
1371 | */ | |
1372 | static inline bool bnx2x_wait_sp_comp(struct bnx2x *bp, unsigned long mask) | |
1373 | { | |
1374 | int tout = 5000; /* Wait for 5 secs tops */ | |
1375 | ||
1376 | while (tout--) { | |
1377 | smp_mb(); | |
1378 | netif_addr_lock_bh(bp->dev); | |
1379 | if (!(bp->sp_state & mask)) { | |
1380 | netif_addr_unlock_bh(bp->dev); | |
1381 | return true; | |
1382 | } | |
1383 | netif_addr_unlock_bh(bp->dev); | |
3b7f817e | 1384 | |
619c5cb6 VZ |
1385 | usleep_range(1000, 1000); |
1386 | } | |
1387 | ||
1388 | smp_mb(); | |
1389 | ||
1390 | netif_addr_lock_bh(bp->dev); | |
1391 | if (bp->sp_state & mask) { | |
1392 | BNX2X_ERR("Filtering completion timed out. sp_state 0x%lx, " | |
1393 | "mask 0x%lx\n", bp->sp_state, mask); | |
1394 | netif_addr_unlock_bh(bp->dev); | |
1395 | return false; | |
1396 | } | |
1397 | netif_addr_unlock_bh(bp->dev); | |
3b7f817e | 1398 | |
619c5cb6 | 1399 | return true; |
523224a3 | 1400 | } |
f85582f8 | 1401 | |
619c5cb6 VZ |
1402 | /** |
1403 | * bnx2x_set_ctx_validation - set CDU context validation values | |
1404 | * | |
1405 | * @bp: driver handle | |
1406 | * @cxt: context of the connection on the host memory | |
1407 | * @cid: SW CID of the connection to be configured | |
1408 | */ | |
1409 | void bnx2x_set_ctx_validation(struct bnx2x *bp, struct eth_context *cxt, | |
1410 | u32 cid); | |
1411 | ||
1412 | void bnx2x_update_coalesce_sb_index(struct bnx2x *bp, u8 fw_sb_id, | |
1413 | u8 sb_index, u8 disable, u16 usec); | |
9f6c9258 DK |
1414 | void bnx2x_acquire_phy_lock(struct bnx2x *bp); |
1415 | void bnx2x_release_phy_lock(struct bnx2x *bp); | |
1416 | ||
faa6fcbb | 1417 | /** |
e8920674 | 1418 | * bnx2x_extract_max_cfg - extract MAX BW part from MF configuration. |
faa6fcbb | 1419 | * |
e8920674 DK |
1420 | * @bp: driver handle |
1421 | * @mf_cfg: MF configuration | |
faa6fcbb | 1422 | * |
faa6fcbb DK |
1423 | */ |
1424 | static inline u16 bnx2x_extract_max_cfg(struct bnx2x *bp, u32 mf_cfg) | |
1425 | { | |
1426 | u16 max_cfg = (mf_cfg & FUNC_MF_CFG_MAX_BW_MASK) >> | |
1427 | FUNC_MF_CFG_MAX_BW_SHIFT; | |
1428 | if (!max_cfg) { | |
1429 | BNX2X_ERR("Illegal configuration detected for Max BW - " | |
1430 | "using 100 instead\n"); | |
1431 | max_cfg = 100; | |
1432 | } | |
1433 | return max_cfg; | |
1434 | } | |
1435 | ||
9f6c9258 | 1436 | #endif /* BNX2X_CMN_H */ |