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bnx2x: add a select queue callback
[deliverable/linux.git] / drivers / net / bnx2x / bnx2x_cmn.h
CommitLineData
9f6c9258
DK		 1/* bnx2x_cmn.h: Broadcom Everest network driver.
2 *
3 * Copyright (c) 2007-2010 Broadcom Corporation
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
8 *
9 * Maintained by: Eilon Greenstein <eilong@broadcom.com>
10 * Written by: Eliezer Tamir
11 * Based on code from Michael Chan's bnx2 driver
12 * UDP CSUM errata workaround by Arik Gendelman
13 * Slowpath and fastpath rework by Vladislav Zolotarov
14 * Statistics and Link management by Yitchak Gertner
15 *
16 */
17#ifndef BNX2X_CMN_H
18#define BNX2X_CMN_H
19
20#include <linux/types.h>
21#include <linux/netdevice.h>
22
23
24#include "bnx2x.h"
25
d6214d7a 26extern int num_queues;
9f6c9258
DK		 27
28/*********************** Interfaces ****************************
29 * Functions that need to be implemented by each driver version
30 */
31
32/**
33 * Initialize link parameters structure variables.
34 *
35 * @param bp
36 * @param load_mode
37 *
38 * @return u8
39 */
40u8 bnx2x_initial_phy_init(struct bnx2x *bp, int load_mode);
41
42/**
43 * Configure hw according to link parameters structure.
44 *
45 * @param bp
46 */
47void bnx2x_link_set(struct bnx2x *bp);
48
49/**
50 * Query link status
51 *
52 * @param bp
a22f0788 53 * @param is_serdes
9f6c9258
DK		 54 *
55 * @return 0 - link is UP
56 */
a22f0788 57u8 bnx2x_link_test(struct bnx2x *bp, u8 is_serdes);
9f6c9258
DK		 58
59/**
60 * Handles link status change
61 *
62 * @param bp
63 */
64void bnx2x__link_status_update(struct bnx2x *bp);
65
f85582f8
DK		 66/**
67 * Report link status to upper layer
68 *
69 * @param bp
70 *
71 * @return int
72 */
73void bnx2x_link_report(struct bnx2x *bp);
74
0793f83f
DK		 75/**
76 * calculates MF speed according to current linespeed and MF
77 * configuration
78 *
79 * @param bp
80 *
81 * @return u16
82 */
83u16 bnx2x_get_mf_speed(struct bnx2x *bp);
84
9f6c9258
DK		 85/**
86 * MSI-X slowpath interrupt handler
87 *
88 * @param irq
89 * @param dev_instance
90 *
91 * @return irqreturn_t
92 */
93irqreturn_t bnx2x_msix_sp_int(int irq, void *dev_instance);
94
95/**
96 * non MSI-X interrupt handler
97 *
98 * @param irq
99 * @param dev_instance
100 *
101 * @return irqreturn_t
102 */
103irqreturn_t bnx2x_interrupt(int irq, void *dev_instance);
104#ifdef BCM_CNIC
105
106/**
107 * Send command to cnic driver
108 *
109 * @param bp
110 * @param cmd
111 */
112int bnx2x_cnic_notify(struct bnx2x *bp, int cmd);
113
114/**
115 * Provides cnic information for proper interrupt handling
116 *
117 * @param bp
118 */
119void bnx2x_setup_cnic_irq_info(struct bnx2x *bp);
120#endif
121
122/**
123 * Enable HW interrupts.
124 *
125 * @param bp
126 */
127void bnx2x_int_enable(struct bnx2x *bp);
128
129/**
130 * Disable interrupts. This function ensures that there are no
131 * ISRs or SP DPCs (sp_task) are running after it returns.
132 *
133 * @param bp
134 * @param disable_hw if true, disable HW interrupts.
135 */
136void bnx2x_int_disable_sync(struct bnx2x *bp, int disable_hw);
137
6891dd25
DK		 138/**
139 * Loads device firmware
140 *
141 * @param bp
142 *
143 * @return int
144 */
145int bnx2x_init_firmware(struct bnx2x *bp);
146
9f6c9258
DK		 147/**
148 * Init HW blocks according to current initialization stage:
149 * COMMON, PORT or FUNCTION.
150 *
151 * @param bp
152 * @param load_code: COMMON, PORT or FUNCTION
153 *
154 * @return int
155 */
156int bnx2x_init_hw(struct bnx2x *bp, u32 load_code);
157
158/**
159 * Init driver internals:
160 * - rings
161 * - status blocks
162 * - etc.
163 *
164 * @param bp
165 * @param load_code COMMON, PORT or FUNCTION
166 */
167void bnx2x_nic_init(struct bnx2x *bp, u32 load_code);
168
169/**
170 * Allocate driver's memory.
171 *
172 * @param bp
173 *
174 * @return int
175 */
176int bnx2x_alloc_mem(struct bnx2x *bp);
177
178/**
179 * Release driver's memory.
180 *
181 * @param bp
182 */
183void bnx2x_free_mem(struct bnx2x *bp);
184
185/**
523224a3 186 * Setup eth Client.
9f6c9258
DK		 187 *
188 * @param bp
523224a3
DK		 189 * @param fp
190 * @param is_leading
9f6c9258
DK		 191 *
192 * @return int
193 */
523224a3
DK		 194int bnx2x_setup_client(struct bnx2x *bp, struct bnx2x_fastpath *fp,
195 int is_leading);
9f6c9258 196
9f6c9258 197/**
d6214d7a 198 * Set number of queues according to mode
9f6c9258
DK		 199 *
200 * @param bp
201 *
202 */
d6214d7a 203void bnx2x_set_num_queues(struct bnx2x *bp);
9f6c9258
DK		 204
205/**
206 * Cleanup chip internals:
207 * - Cleanup MAC configuration.
208 * - Close clients.
209 * - etc.
210 *
211 * @param bp
212 * @param unload_mode
213 */
214void bnx2x_chip_cleanup(struct bnx2x *bp, int unload_mode);
215
216/**
217 * Acquire HW lock.
218 *
219 * @param bp
220 * @param resource Resource bit which was locked
221 *
222 * @return int
223 */
224int bnx2x_acquire_hw_lock(struct bnx2x *bp, u32 resource);
225
226/**
227 * Release HW lock.
228 *
229 * @param bp driver handle
230 * @param resource Resource bit which was locked
231 *
232 * @return int
233 */
234int bnx2x_release_hw_lock(struct bnx2x *bp, u32 resource);
235
236/**
237 * Configure eth MAC address in the HW according to the value in
f85582f8 238 * netdev->dev_addr.
9f6c9258
DK		 239 *
240 * @param bp driver handle
241 * @param set
242 */
523224a3 243void bnx2x_set_eth_mac(struct bnx2x *bp, int set);
9f6c9258 244
ec6ba945
VZ		 245#ifdef BCM_CNIC
246/**
247 * Set/Clear FIP MAC(s) at the next enties in the CAM after the ETH
248 * MAC(s). This function will wait until the ramdord completion
249 * returns.
250 *
251 * @param bp driver handle
252 * @param set set or clear the CAM entry
253 *
254 * @return 0 if cussess, -ENODEV if ramrod doesn't return.
255 */
256int bnx2x_set_fip_eth_mac_addr(struct bnx2x *bp, int set);
257
258/**
259 * Set/Clear ALL_ENODE mcast MAC.
260 *
261 * @param bp
262 * @param set
263 *
264 * @return int
265 */
266int bnx2x_set_all_enode_macs(struct bnx2x *bp, int set);
267#endif
268
9f6c9258 269/**
f85582f8 270 * Set MAC filtering configurations.
9f6c9258 271 *
f85582f8 272 * @remarks called with netif_tx_lock from dev_mcast.c
9f6c9258 273 *
f85582f8 274 * @param dev net_device
9f6c9258
DK		 275 */
276void bnx2x_set_rx_mode(struct net_device *dev);
277
278/**
279 * Configure MAC filtering rules in a FW.
280 *
281 * @param bp driver handle
282 */
283void bnx2x_set_storm_rx_mode(struct bnx2x *bp);
284
285/* Parity errors related */
286void bnx2x_inc_load_cnt(struct bnx2x *bp);
287u32 bnx2x_dec_load_cnt(struct bnx2x *bp);
288bool bnx2x_chk_parity_attn(struct bnx2x *bp);
289bool bnx2x_reset_is_done(struct bnx2x *bp);
290void bnx2x_disable_close_the_gate(struct bnx2x *bp);
291
292/**
293 * Perform statistics handling according to event
294 *
295 * @param bp driver handle
f85582f8 296 * @param event bnx2x_stats_event
9f6c9258
DK		 297 */
298void bnx2x_stats_handle(struct bnx2x *bp, enum bnx2x_stats_event event);
299
9f6c9258 300/**
f85582f8 301 * Handle ramrods completion
9f6c9258
DK		 302 *
303 * @param fp fastpath handle for the event
304 * @param rr_cqe eth_rx_cqe
305 */
f85582f8 306void bnx2x_sp_event(struct bnx2x_fastpath *fp, union eth_rx_cqe *rr_cqe);
9f6c9258 307
523224a3
DK		 308/**
309 * Init/halt function before/after sending
310 * CLIENT_SETUP/CFC_DEL for the first/last client.
311 *
312 * @param bp
313 *
314 * @return int
315 */
316int bnx2x_func_start(struct bnx2x *bp);
523224a3
DK		 317
318/**
319 * Prepare ILT configurations according to current driver
320 * parameters.
321 *
322 * @param bp
323 */
324void bnx2x_ilt_set_info(struct bnx2x *bp);
9f6c9258 325
f85582f8
DK		 326/**
327 * Set power state to the requested value. Currently only D0 and
328 * D3hot are supported.
329 *
330 * @param bp
331 * @param state D0 or D3hot
332 *
333 * @return int
334 */
335int bnx2x_set_power_state(struct bnx2x *bp, pci_power_t state);
336
337/* dev_close main block */
338int bnx2x_nic_unload(struct bnx2x *bp, int unload_mode);
339
340/* dev_open main block */
341int bnx2x_nic_load(struct bnx2x *bp, int load_mode);
342
343/* hard_xmit callback */
344netdev_tx_t bnx2x_start_xmit(struct sk_buff *skb, struct net_device *dev);
345
8307fa3e
VZ		 346/* select_queue callback */
347u16 bnx2x_select_queue(struct net_device *dev, struct sk_buff *skb);
348
f85582f8
DK		 349int bnx2x_change_mac_addr(struct net_device *dev, void *p);
350
351/* NAPI poll Rx part */
352int bnx2x_rx_int(struct bnx2x_fastpath *fp, int budget);
353
354/* NAPI poll Tx part */
355int bnx2x_tx_int(struct bnx2x_fastpath *fp);
356
357/* suspend/resume callbacks */
358int bnx2x_suspend(struct pci_dev *pdev, pm_message_t state);
359int bnx2x_resume(struct pci_dev *pdev);
360
361/* Release IRQ vectors */
362void bnx2x_free_irq(struct bnx2x *bp);
363
364void bnx2x_init_rx_rings(struct bnx2x *bp);
365void bnx2x_free_skbs(struct bnx2x *bp);
366void bnx2x_netif_stop(struct bnx2x *bp, int disable_hw);
367void bnx2x_netif_start(struct bnx2x *bp);
368
d6214d7a
DK		 369/**
370 * Fill msix_table, request vectors, update num_queues according
371 * to number of available vectors
372 *
373 * @param bp
374 *
375 * @return int
376 */
377int bnx2x_enable_msix(struct bnx2x *bp);
378
379/**
380 * Request msi mode from OS, updated internals accordingly
381 *
382 * @param bp
383 *
384 * @return int
385 */
386int bnx2x_enable_msi(struct bnx2x *bp);
387
d6214d7a
DK		 388/**
389 * NAPI callback
390 *
391 * @param napi
392 * @param budget
393 *
394 * @return int
395 */
396int bnx2x_poll(struct napi_struct *napi, int budget);
f85582f8
DK		 397
398/**
399 * Allocate/release memories outsize main driver structure
400 *
401 * @param bp
402 *
403 * @return int
404 */
405int __devinit bnx2x_alloc_mem_bp(struct bnx2x *bp);
406void bnx2x_free_mem_bp(struct bnx2x *bp);
407
408/**
409 * Change mtu netdev callback
410 *
411 * @param dev
412 * @param new_mtu
413 *
414 * @return int
415 */
416int bnx2x_change_mtu(struct net_device *dev, int new_mtu);
417
418/**
419 * tx timeout netdev callback
420 *
421 * @param dev
422 * @param new_mtu
423 *
424 * @return int
425 */
426void bnx2x_tx_timeout(struct net_device *dev);
427
428#ifdef BCM_VLAN
429/**
430 * vlan rx register netdev callback
431 *
432 * @param dev
433 * @param new_mtu
434 *
435 * @return int
436 */
437void bnx2x_vlan_rx_register(struct net_device *dev,
438 struct vlan_group *vlgrp);
439
440#endif
441
9f6c9258
DK		 442static inline void bnx2x_update_fpsb_idx(struct bnx2x_fastpath *fp)
443{
9f6c9258 444 barrier(); /* status block is written to by the chip */
523224a3 445 fp->fp_hc_idx = fp->sb_running_index[SM_RX_ID];
9f6c9258
DK		 446}
447
448static inline void bnx2x_update_rx_prod(struct bnx2x *bp,
449 struct bnx2x_fastpath *fp,
450 u16 bd_prod, u16 rx_comp_prod,
451 u16 rx_sge_prod)
452{
453 struct ustorm_eth_rx_producers rx_prods = {0};
454 int i;
455
456 /* Update producers */
457 rx_prods.bd_prod = bd_prod;
458 rx_prods.cqe_prod = rx_comp_prod;
459 rx_prods.sge_prod = rx_sge_prod;
460
461 /*
462 * Make sure that the BD and SGE data is updated before updating the
463 * producers since FW might read the BD/SGE right after the producer
464 * is updated.
465 * This is only applicable for weak-ordered memory model archs such
466 * as IA-64. The following barrier is also mandatory since FW will
467 * assumes BDs must have buffers.
468 */
469 wmb();
470
471 for (i = 0; i < sizeof(struct ustorm_eth_rx_producers)/4; i++)
523224a3
DK		 472 REG_WR(bp,
473 BAR_USTRORM_INTMEM + fp->ustorm_rx_prods_offset + i*4,
9f6c9258
DK		 474 ((u32 *)&rx_prods)[i]);
475
476 mmiowb(); /* keep prod updates ordered */
477
478 DP(NETIF_MSG_RX_STATUS,
479 "queue[%d]: wrote bd_prod %u cqe_prod %u sge_prod %u\n",
480 fp->index, bd_prod, rx_comp_prod, rx_sge_prod);
481}
482
f2e0899f
DK		 483static inline void bnx2x_igu_ack_sb_gen(struct bnx2x *bp, u8 igu_sb_id,
484 u8 segment, u16 index, u8 op,
485 u8 update, u32 igu_addr)
486{
487 struct igu_regular cmd_data = {0};
488
489 cmd_data.sb_id_and_flags =
490 ((index << IGU_REGULAR_SB_INDEX_SHIFT) |
491 (segment << IGU_REGULAR_SEGMENT_ACCESS_SHIFT) |
492 (update << IGU_REGULAR_BUPDATE_SHIFT) |
493 (op << IGU_REGULAR_ENABLE_INT_SHIFT));
494
495 DP(NETIF_MSG_HW, "write 0x%08x to IGU addr 0x%x\n",
496 cmd_data.sb_id_and_flags, igu_addr);
497 REG_WR(bp, igu_addr, cmd_data.sb_id_and_flags);
498
499 /* Make sure that ACK is written */
500 mmiowb();
501 barrier();
502}
503
504static inline void bnx2x_igu_clear_sb_gen(struct bnx2x *bp,
505 u8 idu_sb_id, bool is_Pf)
506{
507 u32 data, ctl, cnt = 100;
508 u32 igu_addr_data = IGU_REG_COMMAND_REG_32LSB_DATA;
509 u32 igu_addr_ctl = IGU_REG_COMMAND_REG_CTRL;
510 u32 igu_addr_ack = IGU_REG_CSTORM_TYPE_0_SB_CLEANUP + (idu_sb_id/32)*4;
511 u32 sb_bit = 1 << (idu_sb_id%32);
512 u32 func_encode = BP_FUNC(bp) |
513 ((is_Pf == true ? 1 : 0) << IGU_FID_ENCODE_IS_PF_SHIFT);
514 u32 addr_encode = IGU_CMD_E2_PROD_UPD_BASE + idu_sb_id;
515
516 /* Not supported in BC mode */
517 if (CHIP_INT_MODE_IS_BC(bp))
518 return;
519
520 data = (IGU_USE_REGISTER_cstorm_type_0_sb_cleanup
521 << IGU_REGULAR_CLEANUP_TYPE_SHIFT) |
522 IGU_REGULAR_CLEANUP_SET |
523 IGU_REGULAR_BCLEANUP;
524
525 ctl = addr_encode << IGU_CTRL_REG_ADDRESS_SHIFT |
526 func_encode << IGU_CTRL_REG_FID_SHIFT |
527 IGU_CTRL_CMD_TYPE_WR << IGU_CTRL_REG_TYPE_SHIFT;
9f6c9258 528
f2e0899f
DK		 529 DP(NETIF_MSG_HW, "write 0x%08x to IGU(via GRC) addr 0x%x\n",
530 data, igu_addr_data);
531 REG_WR(bp, igu_addr_data, data);
532 mmiowb();
533 barrier();
534 DP(NETIF_MSG_HW, "write 0x%08x to IGU(via GRC) addr 0x%x\n",
535 ctl, igu_addr_ctl);
536 REG_WR(bp, igu_addr_ctl, ctl);
537 mmiowb();
538 barrier();
9f6c9258 539
f2e0899f
DK		 540 /* wait for clean up to finish */
541 while (!(REG_RD(bp, igu_addr_ack) & sb_bit) && --cnt)
542 msleep(20);
543
544
545 if (!(REG_RD(bp, igu_addr_ack) & sb_bit)) {
546 DP(NETIF_MSG_HW, "Unable to finish IGU cleanup: "
547 "idu_sb_id %d offset %d bit %d (cnt %d)\n",
548 idu_sb_id, idu_sb_id/32, idu_sb_id%32, cnt);
549 }
550}
551
552static inline void bnx2x_hc_ack_sb(struct bnx2x *bp, u8 sb_id,
553 u8 storm, u16 index, u8 op, u8 update)
9f6c9258
DK		 554{
555 u32 hc_addr = (HC_REG_COMMAND_REG + BP_PORT(bp)*32 +
556 COMMAND_REG_INT_ACK);
557 struct igu_ack_register igu_ack;
558
559 igu_ack.status_block_index = index;
560 igu_ack.sb_id_and_flags =
561 ((sb_id << IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT) |
562 (storm << IGU_ACK_REGISTER_STORM_ID_SHIFT) |
563 (update << IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT) |
564 (op << IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT));
565
566 DP(BNX2X_MSG_OFF, "write 0x%08x to HC addr 0x%x\n",
567 (*(u32 *)&igu_ack), hc_addr);
568 REG_WR(bp, hc_addr, (*(u32 *)&igu_ack));
569
570 /* Make sure that ACK is written */
571 mmiowb();
572 barrier();
573}
f2e0899f
DK		 574
575static inline void bnx2x_igu_ack_sb(struct bnx2x *bp, u8 igu_sb_id, u8 segment,
576 u16 index, u8 op, u8 update)
577{
578 u32 igu_addr = BAR_IGU_INTMEM + (IGU_CMD_INT_ACK_BASE + igu_sb_id)*8;
579
580 bnx2x_igu_ack_sb_gen(bp, igu_sb_id, segment, index, op, update,
581 igu_addr);
582}
583
584static inline void bnx2x_ack_sb(struct bnx2x *bp, u8 igu_sb_id, u8 storm,
585 u16 index, u8 op, u8 update)
586{
587 if (bp->common.int_block == INT_BLOCK_HC)
588 bnx2x_hc_ack_sb(bp, igu_sb_id, storm, index, op, update);
589 else {
590 u8 segment;
591
592 if (CHIP_INT_MODE_IS_BC(bp))
593 segment = storm;
594 else if (igu_sb_id != bp->igu_dsb_id)
595 segment = IGU_SEG_ACCESS_DEF;
596 else if (storm == ATTENTION_ID)
597 segment = IGU_SEG_ACCESS_ATTN;
598 else
599 segment = IGU_SEG_ACCESS_DEF;
600 bnx2x_igu_ack_sb(bp, igu_sb_id, segment, index, op, update);
601 }
602}
603
604static inline u16 bnx2x_hc_ack_int(struct bnx2x *bp)
9f6c9258
DK		 605{
606 u32 hc_addr = (HC_REG_COMMAND_REG + BP_PORT(bp)*32 +
607 COMMAND_REG_SIMD_MASK);
608 u32 result = REG_RD(bp, hc_addr);
609
610 DP(BNX2X_MSG_OFF, "read 0x%08x from HC addr 0x%x\n",
611 result, hc_addr);
612
f2e0899f 613 barrier();
9f6c9258
DK		 614 return result;
615}
616
f2e0899f
DK		 617static inline u16 bnx2x_igu_ack_int(struct bnx2x *bp)
618{
619 u32 igu_addr = (BAR_IGU_INTMEM + IGU_REG_SISR_MDPC_WMASK_LSB_UPPER*8);
620 u32 result = REG_RD(bp, igu_addr);
621
622 DP(NETIF_MSG_HW, "read 0x%08x from IGU addr 0x%x\n",
623 result, igu_addr);
624
625 barrier();
626 return result;
627}
628
629static inline u16 bnx2x_ack_int(struct bnx2x *bp)
630{
631 barrier();
632 if (bp->common.int_block == INT_BLOCK_HC)
633 return bnx2x_hc_ack_int(bp);
634 else
635 return bnx2x_igu_ack_int(bp);
636}
637
9f6c9258
DK		 638static inline int bnx2x_has_tx_work_unload(struct bnx2x_fastpath *fp)
639{
640 /* Tell compiler that consumer and producer can change */
641 barrier();
807540ba 642 return fp->tx_pkt_prod != fp->tx_pkt_cons;
9f6c9258
DK		 643}
644
645static inline u16 bnx2x_tx_avail(struct bnx2x_fastpath *fp)
646{
647 s16 used;
648 u16 prod;
649 u16 cons;
650
651 prod = fp->tx_bd_prod;
652 cons = fp->tx_bd_cons;
653
654 /* NUM_TX_RINGS = number of "next-page" entries
655 It will be used as a threshold */
656 used = SUB_S16(prod, cons) + (s16)NUM_TX_RINGS;
657
658#ifdef BNX2X_STOP_ON_ERROR
659 WARN_ON(used < 0);
660 WARN_ON(used > fp->bp->tx_ring_size);
661 WARN_ON((fp->bp->tx_ring_size - used) > MAX_TX_AVAIL);
662#endif
663
664 return (s16)(fp->bp->tx_ring_size) - used;
665}
666
667static inline int bnx2x_has_tx_work(struct bnx2x_fastpath *fp)
668{
669 u16 hw_cons;
670
671 /* Tell compiler that status block fields can change */
672 barrier();
673 hw_cons = le16_to_cpu(*fp->tx_cons_sb);
674 return hw_cons != fp->tx_pkt_cons;
675}
676
523224a3
DK		 677static inline int bnx2x_has_rx_work(struct bnx2x_fastpath *fp)
678{
679 u16 rx_cons_sb;
680
681 /* Tell compiler that status block fields can change */
682 barrier();
683 rx_cons_sb = le16_to_cpu(*fp->rx_cons_sb);
684 if ((rx_cons_sb & MAX_RCQ_DESC_CNT) == MAX_RCQ_DESC_CNT)
685 rx_cons_sb++;
686 return (fp->rx_comp_cons != rx_cons_sb);
687}
f85582f8 688
f2e0899f
DK		 689/**
690 * disables tx from stack point of view
691 *
692 * @param bp
693 */
694static inline void bnx2x_tx_disable(struct bnx2x *bp)
695{
696 netif_tx_disable(bp->dev);
697 netif_carrier_off(bp->dev);
698}
699
9f6c9258
DK		 700static inline void bnx2x_free_rx_sge(struct bnx2x *bp,
701 struct bnx2x_fastpath *fp, u16 index)
702{
703 struct sw_rx_page *sw_buf = &fp->rx_page_ring[index];
704 struct page *page = sw_buf->page;
705 struct eth_rx_sge *sge = &fp->rx_sge_ring[index];
706
707 /* Skip "next page" elements */
708 if (!page)
709 return;
710
711 dma_unmap_page(&bp->pdev->dev, dma_unmap_addr(sw_buf, mapping),
4bca60f4 712 SGE_PAGE_SIZE*PAGES_PER_SGE, DMA_FROM_DEVICE);
9f6c9258
DK		 713 __free_pages(page, PAGES_PER_SGE_SHIFT);
714
715 sw_buf->page = NULL;
716 sge->addr_hi = 0;
717 sge->addr_lo = 0;
718}
719
d6214d7a
DK		 720static inline void bnx2x_add_all_napi(struct bnx2x *bp)
721{
722 int i;
523224a3 723
d6214d7a 724 /* Add NAPI objects */
ec6ba945 725 for_each_napi_queue(bp, i)
d6214d7a
DK		 726 netif_napi_add(bp->dev, &bnx2x_fp(bp, i, napi),
727 bnx2x_poll, BNX2X_NAPI_WEIGHT);
728}
523224a3 729
d6214d7a
DK		 730static inline void bnx2x_del_all_napi(struct bnx2x *bp)
731{
732 int i;
733
ec6ba945 734 for_each_napi_queue(bp, i)
d6214d7a
DK		 735 netif_napi_del(&bnx2x_fp(bp, i, napi));
736}
523224a3 737
d6214d7a
DK		 738static inline void bnx2x_disable_msi(struct bnx2x *bp)
739{
740 if (bp->flags & USING_MSIX_FLAG) {
741 pci_disable_msix(bp->pdev);
742 bp->flags &= ~USING_MSIX_FLAG;
743 } else if (bp->flags & USING_MSI_FLAG) {
744 pci_disable_msi(bp->pdev);
745 bp->flags &= ~USING_MSI_FLAG;
746 }
747}
748
749static inline int bnx2x_calc_num_queues(struct bnx2x *bp)
750{
751 return num_queues ?
752 min_t(int, num_queues, BNX2X_MAX_QUEUES(bp)) :
753 min_t(int, num_online_cpus(), BNX2X_MAX_QUEUES(bp));
754}
523224a3
DK		 755
756static inline void bnx2x_clear_sge_mask_next_elems(struct bnx2x_fastpath *fp)
9f6c9258 757{
523224a3 758 int i, j;
9f6c9258 759
523224a3
DK		 760 for (i = 1; i <= NUM_RX_SGE_PAGES; i++) {
761 int idx = RX_SGE_CNT * i - 1;
762
763 for (j = 0; j < 2; j++) {
764 SGE_MASK_CLEAR_BIT(fp, idx);
765 idx--;
766 }
767 }
768}
769
770static inline void bnx2x_init_sge_ring_bit_mask(struct bnx2x_fastpath *fp)
771{
772 /* Set the mask to all 1-s: it's faster to compare to 0 than to 0xf-s */
773 memset(fp->sge_mask, 0xff,
774 (NUM_RX_SGE >> RX_SGE_MASK_ELEM_SHIFT)*sizeof(u64));
775
776 /* Clear the two last indices in the page to 1:
777 these are the indices that correspond to the "next" element,
778 hence will never be indicated and should be removed from
779 the calculations. */
780 bnx2x_clear_sge_mask_next_elems(fp);
9f6c9258
DK		 781}
782
783static inline int bnx2x_alloc_rx_sge(struct bnx2x *bp,
784 struct bnx2x_fastpath *fp, u16 index)
785{
786 struct page *page = alloc_pages(GFP_ATOMIC, PAGES_PER_SGE_SHIFT);
787 struct sw_rx_page *sw_buf = &fp->rx_page_ring[index];
788 struct eth_rx_sge *sge = &fp->rx_sge_ring[index];
789 dma_addr_t mapping;
790
791 if (unlikely(page == NULL))
792 return -ENOMEM;
793
794 mapping = dma_map_page(&bp->pdev->dev, page, 0,
795 SGE_PAGE_SIZE*PAGES_PER_SGE, DMA_FROM_DEVICE);
796 if (unlikely(dma_mapping_error(&bp->pdev->dev, mapping))) {
797 __free_pages(page, PAGES_PER_SGE_SHIFT);
798 return -ENOMEM;
799 }
800
801 sw_buf->page = page;
802 dma_unmap_addr_set(sw_buf, mapping, mapping);
803
804 sge->addr_hi = cpu_to_le32(U64_HI(mapping));
805 sge->addr_lo = cpu_to_le32(U64_LO(mapping));
806
807 return 0;
808}
f85582f8 809
9f6c9258
DK		 810static inline int bnx2x_alloc_rx_skb(struct bnx2x *bp,
811 struct bnx2x_fastpath *fp, u16 index)
812{
813 struct sk_buff *skb;
814 struct sw_rx_bd *rx_buf = &fp->rx_buf_ring[index];
815 struct eth_rx_bd *rx_bd = &fp->rx_desc_ring[index];
816 dma_addr_t mapping;
817
818 skb = netdev_alloc_skb(bp->dev, bp->rx_buf_size);
819 if (unlikely(skb == NULL))
820 return -ENOMEM;
821
822 mapping = dma_map_single(&bp->pdev->dev, skb->data, bp->rx_buf_size,
823 DMA_FROM_DEVICE);
824 if (unlikely(dma_mapping_error(&bp->pdev->dev, mapping))) {
825 dev_kfree_skb(skb);
826 return -ENOMEM;
827 }
828
829 rx_buf->skb = skb;
830 dma_unmap_addr_set(rx_buf, mapping, mapping);
831
832 rx_bd->addr_hi = cpu_to_le32(U64_HI(mapping));
833 rx_bd->addr_lo = cpu_to_le32(U64_LO(mapping));
834
835 return 0;
836}
837
838/* note that we are not allocating a new skb,
839 * we are just moving one from cons to prod
840 * we are not creating a new mapping,
841 * so there is no need to check for dma_mapping_error().
842 */
843static inline void bnx2x_reuse_rx_skb(struct bnx2x_fastpath *fp,
749a8503 844 u16 cons, u16 prod)
9f6c9258
DK		 845{
846 struct bnx2x *bp = fp->bp;
847 struct sw_rx_bd *cons_rx_buf = &fp->rx_buf_ring[cons];
848 struct sw_rx_bd *prod_rx_buf = &fp->rx_buf_ring[prod];
849 struct eth_rx_bd *cons_bd = &fp->rx_desc_ring[cons];
850 struct eth_rx_bd *prod_bd = &fp->rx_desc_ring[prod];
851
852 dma_sync_single_for_device(&bp->pdev->dev,
853 dma_unmap_addr(cons_rx_buf, mapping),
854 RX_COPY_THRESH, DMA_FROM_DEVICE);
855
856 prod_rx_buf->skb = cons_rx_buf->skb;
857 dma_unmap_addr_set(prod_rx_buf, mapping,
858 dma_unmap_addr(cons_rx_buf, mapping));
859 *prod_bd = *cons_bd;
860}
f85582f8 861
523224a3
DK		 862static inline void bnx2x_free_rx_sge_range(struct bnx2x *bp,
863 struct bnx2x_fastpath *fp, int last)
9f6c9258 864{
523224a3 865 int i;
9f6c9258 866
523224a3
DK		 867 for (i = 0; i < last; i++)
868 bnx2x_free_rx_sge(bp, fp, i);
9f6c9258
DK		 869}
870
9f6c9258
DK		 871static inline void bnx2x_free_tpa_pool(struct bnx2x *bp,
872 struct bnx2x_fastpath *fp, int last)
873{
874 int i;
875
876 for (i = 0; i < last; i++) {
877 struct sw_rx_bd *rx_buf = &(fp->tpa_pool[i]);
878 struct sk_buff *skb = rx_buf->skb;
879
880 if (skb == NULL) {
881 DP(NETIF_MSG_IFDOWN, "tpa bin %d empty on free\n", i);
882 continue;
883 }
884
885 if (fp->tpa_state[i] == BNX2X_TPA_START)
886 dma_unmap_single(&bp->pdev->dev,
887 dma_unmap_addr(rx_buf, mapping),
888 bp->rx_buf_size, DMA_FROM_DEVICE);
889
890 dev_kfree_skb(skb);
891 rx_buf->skb = NULL;
892 }
893}
894
895
523224a3 896static inline void bnx2x_init_tx_rings(struct bnx2x *bp)
9f6c9258
DK		 897{
898 int i, j;
899
ec6ba945 900 for_each_tx_queue(bp, j) {
9f6c9258
DK		 901 struct bnx2x_fastpath *fp = &bp->fp[j];
902
903 for (i = 1; i <= NUM_TX_RINGS; i++) {
904 struct eth_tx_next_bd *tx_next_bd =
905 &fp->tx_desc_ring[TX_DESC_CNT * i - 1].next_bd;
906
907 tx_next_bd->addr_hi =
908 cpu_to_le32(U64_HI(fp->tx_desc_mapping +
909 BCM_PAGE_SIZE*(i % NUM_TX_RINGS)));
910 tx_next_bd->addr_lo =
911 cpu_to_le32(U64_LO(fp->tx_desc_mapping +
912 BCM_PAGE_SIZE*(i % NUM_TX_RINGS)));
913 }
914
523224a3 915 SET_FLAG(fp->tx_db.data.header.header, DOORBELL_HDR_DB_TYPE, 1);
9f6c9258
DK		 916 fp->tx_db.data.zero_fill1 = 0;
917 fp->tx_db.data.prod = 0;
918
919 fp->tx_pkt_prod = 0;
920 fp->tx_pkt_cons = 0;
921 fp->tx_bd_prod = 0;
922 fp->tx_bd_cons = 0;
9f6c9258
DK		 923 fp->tx_pkt = 0;
924 }
925}
f85582f8 926
523224a3 927static inline void bnx2x_set_next_page_rx_bd(struct bnx2x_fastpath *fp)
9f6c9258 928{
523224a3 929 int i;
9f6c9258 930
523224a3
DK		 931 for (i = 1; i <= NUM_RX_RINGS; i++) {
932 struct eth_rx_bd *rx_bd;
933
934 rx_bd = &fp->rx_desc_ring[RX_DESC_CNT * i - 2];
935 rx_bd->addr_hi =
936 cpu_to_le32(U64_HI(fp->rx_desc_mapping +
937 BCM_PAGE_SIZE*(i % NUM_RX_RINGS)));
938 rx_bd->addr_lo =
939 cpu_to_le32(U64_LO(fp->rx_desc_mapping +
940 BCM_PAGE_SIZE*(i % NUM_RX_RINGS)));
941 }
9f6c9258
DK		 942}
943
523224a3
DK		 944static inline void bnx2x_set_next_page_sgl(struct bnx2x_fastpath *fp)
945{
946 int i;
947
948 for (i = 1; i <= NUM_RX_SGE_PAGES; i++) {
949 struct eth_rx_sge *sge;
950
951 sge = &fp->rx_sge_ring[RX_SGE_CNT * i - 2];
952 sge->addr_hi =
953 cpu_to_le32(U64_HI(fp->rx_sge_mapping +
954 BCM_PAGE_SIZE*(i % NUM_RX_SGE_PAGES)));
955
956 sge->addr_lo =
957 cpu_to_le32(U64_LO(fp->rx_sge_mapping +
958 BCM_PAGE_SIZE*(i % NUM_RX_SGE_PAGES)));
959 }
960}
961
962static inline void bnx2x_set_next_page_rx_cq(struct bnx2x_fastpath *fp)
963{
964 int i;
965 for (i = 1; i <= NUM_RCQ_RINGS; i++) {
966 struct eth_rx_cqe_next_page *nextpg;
967
968 nextpg = (struct eth_rx_cqe_next_page *)
969 &fp->rx_comp_ring[RCQ_DESC_CNT * i - 1];
970 nextpg->addr_hi =
971 cpu_to_le32(U64_HI(fp->rx_comp_mapping +
972 BCM_PAGE_SIZE*(i % NUM_RCQ_RINGS)));
973 nextpg->addr_lo =
974 cpu_to_le32(U64_LO(fp->rx_comp_mapping +
975 BCM_PAGE_SIZE*(i % NUM_RCQ_RINGS)));
976 }
977}
978
ec6ba945
VZ		 979#ifdef BCM_CNIC
980static inline void bnx2x_init_fcoe_fp(struct bnx2x *bp)
981{
982 bnx2x_fcoe(bp, cl_id) = BNX2X_FCOE_ETH_CL_ID +
983 BP_E1HVN(bp) * NONE_ETH_CONTEXT_USE;
984 bnx2x_fcoe(bp, cid) = BNX2X_FCOE_ETH_CID;
985 bnx2x_fcoe(bp, fw_sb_id) = DEF_SB_ID;
986 bnx2x_fcoe(bp, igu_sb_id) = bp->igu_dsb_id;
987 bnx2x_fcoe(bp, bp) = bp;
988 bnx2x_fcoe(bp, state) = BNX2X_FP_STATE_CLOSED;
989 bnx2x_fcoe(bp, index) = FCOE_IDX;
990 bnx2x_fcoe(bp, rx_cons_sb) = BNX2X_FCOE_L2_RX_INDEX;
991 bnx2x_fcoe(bp, tx_cons_sb) = BNX2X_FCOE_L2_TX_INDEX;
992 /* qZone id equals to FW (per path) client id */
993 bnx2x_fcoe(bp, cl_qzone_id) = bnx2x_fcoe(bp, cl_id) +
994 BP_PORT(bp)*(CHIP_IS_E2(bp) ? ETH_MAX_RX_CLIENTS_E2 :
995 ETH_MAX_RX_CLIENTS_E1H);
996 /* init shortcut */
997 bnx2x_fcoe(bp, ustorm_rx_prods_offset) = CHIP_IS_E2(bp) ?
998 USTORM_RX_PRODS_E2_OFFSET(bnx2x_fcoe(bp, cl_qzone_id)) :
999 USTORM_RX_PRODS_E1X_OFFSET(BP_PORT(bp), bnx2x_fcoe_fp(bp)->cl_id);
523224a3 1000
ec6ba945
VZ		 1001}
1002#endif
523224a3
DK		 1003
1004static inline void __storm_memset_struct(struct bnx2x *bp,
1005 u32 addr, size_t size, u32 *data)
1006{
1007 int i;
1008 for (i = 0; i < size/4; i++)
1009 REG_WR(bp, addr + (i * 4), data[i]);
1010}
1011
1012static inline void storm_memset_mac_filters(struct bnx2x *bp,
1013 struct tstorm_eth_mac_filter_config *mac_filters,
1014 u16 abs_fid)
1015{
1016 size_t size = sizeof(struct tstorm_eth_mac_filter_config);
1017
1018 u32 addr = BAR_TSTRORM_INTMEM +
1019 TSTORM_MAC_FILTER_CONFIG_OFFSET(abs_fid);
1020
1021 __storm_memset_struct(bp, addr, size, (u32 *)mac_filters);
1022}
1023
1024static inline void storm_memset_cmng(struct bnx2x *bp,
1025 struct cmng_struct_per_port *cmng,
1026 u8 port)
1027{
1028 size_t size = sizeof(struct cmng_struct_per_port);
1029
1030 u32 addr = BAR_XSTRORM_INTMEM +
1031 XSTORM_CMNG_PER_PORT_VARS_OFFSET(port);
1032
1033 __storm_memset_struct(bp, addr, size, (u32 *)cmng);
1034}
f85582f8 1035
9f6c9258
DK		 1036/* HW Lock for shared dual port PHYs */
1037void bnx2x_acquire_phy_lock(struct bnx2x *bp);
1038void bnx2x_release_phy_lock(struct bnx2x *bp);
1039
9f6c9258 1040#endif /* BNX2X_CMN_H */
Linux kernel - Deliverables
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