projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
net: fix nla_policy_len to actually _iterate_ over the policy
[deliverable/linux.git] / drivers / net / bnx2x / bnx2x_cmn.h
CommitLineData
9f6c9258
DK		 1/* bnx2x_cmn.h: Broadcom Everest network driver.
2 *
3 * Copyright (c) 2007-2010 Broadcom Corporation
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
8 *
9 * Maintained by: Eilon Greenstein <eilong@broadcom.com>
10 * Written by: Eliezer Tamir
11 * Based on code from Michael Chan's bnx2 driver
12 * UDP CSUM errata workaround by Arik Gendelman
13 * Slowpath and fastpath rework by Vladislav Zolotarov
14 * Statistics and Link management by Yitchak Gertner
15 *
16 */
17#ifndef BNX2X_CMN_H
18#define BNX2X_CMN_H
19
20#include <linux/types.h>
21#include <linux/netdevice.h>
22
23
24#include "bnx2x.h"
25
d6214d7a 26extern int num_queues;
9f6c9258
DK		 27
28/*********************** Interfaces ****************************
29 * Functions that need to be implemented by each driver version
30 */
31
32/**
33 * Initialize link parameters structure variables.
34 *
35 * @param bp
36 * @param load_mode
37 *
38 * @return u8
39 */
40u8 bnx2x_initial_phy_init(struct bnx2x *bp, int load_mode);
41
42/**
43 * Configure hw according to link parameters structure.
44 *
45 * @param bp
46 */
47void bnx2x_link_set(struct bnx2x *bp);
48
49/**
50 * Query link status
51 *
52 * @param bp
a22f0788 53 * @param is_serdes
9f6c9258
DK		 54 *
55 * @return 0 - link is UP
56 */
a22f0788 57u8 bnx2x_link_test(struct bnx2x *bp, u8 is_serdes);
9f6c9258
DK		 58
59/**
60 * Handles link status change
61 *
62 * @param bp
63 */
64void bnx2x__link_status_update(struct bnx2x *bp);
65
f85582f8
DK		 66/**
67 * Report link status to upper layer
68 *
69 * @param bp
70 *
71 * @return int
72 */
73void bnx2x_link_report(struct bnx2x *bp);
74
0793f83f
DK		 75/**
76 * calculates MF speed according to current linespeed and MF
77 * configuration
78 *
79 * @param bp
80 *
81 * @return u16
82 */
83u16 bnx2x_get_mf_speed(struct bnx2x *bp);
84
9f6c9258
DK		 85/**
86 * MSI-X slowpath interrupt handler
87 *
88 * @param irq
89 * @param dev_instance
90 *
91 * @return irqreturn_t
92 */
93irqreturn_t bnx2x_msix_sp_int(int irq, void *dev_instance);
94
95/**
96 * non MSI-X interrupt handler
97 *
98 * @param irq
99 * @param dev_instance
100 *
101 * @return irqreturn_t
102 */
103irqreturn_t bnx2x_interrupt(int irq, void *dev_instance);
104#ifdef BCM_CNIC
105
106/**
107 * Send command to cnic driver
108 *
109 * @param bp
110 * @param cmd
111 */
112int bnx2x_cnic_notify(struct bnx2x *bp, int cmd);
113
114/**
115 * Provides cnic information for proper interrupt handling
116 *
117 * @param bp
118 */
119void bnx2x_setup_cnic_irq_info(struct bnx2x *bp);
120#endif
121
122/**
123 * Enable HW interrupts.
124 *
125 * @param bp
126 */
127void bnx2x_int_enable(struct bnx2x *bp);
128
129/**
130 * Disable interrupts. This function ensures that there are no
131 * ISRs or SP DPCs (sp_task) are running after it returns.
132 *
133 * @param bp
134 * @param disable_hw if true, disable HW interrupts.
135 */
136void bnx2x_int_disable_sync(struct bnx2x *bp, int disable_hw);
137
6891dd25
DK		 138/**
139 * Loads device firmware
140 *
141 * @param bp
142 *
143 * @return int
144 */
145int bnx2x_init_firmware(struct bnx2x *bp);
146
9f6c9258
DK		 147/**
148 * Init HW blocks according to current initialization stage:
149 * COMMON, PORT or FUNCTION.
150 *
151 * @param bp
152 * @param load_code: COMMON, PORT or FUNCTION
153 *
154 * @return int
155 */
156int bnx2x_init_hw(struct bnx2x *bp, u32 load_code);
157
158/**
159 * Init driver internals:
160 * - rings
161 * - status blocks
162 * - etc.
163 *
164 * @param bp
165 * @param load_code COMMON, PORT or FUNCTION
166 */
167void bnx2x_nic_init(struct bnx2x *bp, u32 load_code);
168
169/**
170 * Allocate driver's memory.
171 *
172 * @param bp
173 *
174 * @return int
175 */
176int bnx2x_alloc_mem(struct bnx2x *bp);
177
178/**
179 * Release driver's memory.
180 *
181 * @param bp
182 */
183void bnx2x_free_mem(struct bnx2x *bp);
184
185/**
523224a3 186 * Setup eth Client.
9f6c9258
DK		 187 *
188 * @param bp
523224a3
DK		 189 * @param fp
190 * @param is_leading
9f6c9258
DK		 191 *
192 * @return int
193 */
523224a3
DK		 194int bnx2x_setup_client(struct bnx2x *bp, struct bnx2x_fastpath *fp,
195 int is_leading);
9f6c9258 196
9f6c9258 197/**
d6214d7a 198 * Set number of queues according to mode
9f6c9258
DK		 199 *
200 * @param bp
201 *
202 */
d6214d7a 203void bnx2x_set_num_queues(struct bnx2x *bp);
9f6c9258
DK		 204
205/**
206 * Cleanup chip internals:
207 * - Cleanup MAC configuration.
208 * - Close clients.
209 * - etc.
210 *
211 * @param bp
212 * @param unload_mode
213 */
214void bnx2x_chip_cleanup(struct bnx2x *bp, int unload_mode);
215
216/**
217 * Acquire HW lock.
218 *
219 * @param bp
220 * @param resource Resource bit which was locked
221 *
222 * @return int
223 */
224int bnx2x_acquire_hw_lock(struct bnx2x *bp, u32 resource);
225
226/**
227 * Release HW lock.
228 *
229 * @param bp driver handle
230 * @param resource Resource bit which was locked
231 *
232 * @return int
233 */
234int bnx2x_release_hw_lock(struct bnx2x *bp, u32 resource);
235
236/**
237 * Configure eth MAC address in the HW according to the value in
f85582f8 238 * netdev->dev_addr.
9f6c9258
DK		 239 *
240 * @param bp driver handle
241 * @param set
242 */
523224a3 243void bnx2x_set_eth_mac(struct bnx2x *bp, int set);
9f6c9258 244
ec6ba945
VZ		 245#ifdef BCM_CNIC
246/**
247 * Set/Clear FIP MAC(s) at the next enties in the CAM after the ETH
248 * MAC(s). This function will wait until the ramdord completion
249 * returns.
250 *
251 * @param bp driver handle
252 * @param set set or clear the CAM entry
253 *
254 * @return 0 if cussess, -ENODEV if ramrod doesn't return.
255 */
256int bnx2x_set_fip_eth_mac_addr(struct bnx2x *bp, int set);
257
258/**
259 * Set/Clear ALL_ENODE mcast MAC.
260 *
261 * @param bp
262 * @param set
263 *
264 * @return int
265 */
266int bnx2x_set_all_enode_macs(struct bnx2x *bp, int set);
267#endif
268
9f6c9258 269/**
f85582f8 270 * Set MAC filtering configurations.
9f6c9258 271 *
f85582f8 272 * @remarks called with netif_tx_lock from dev_mcast.c
9f6c9258 273 *
f85582f8 274 * @param dev net_device
9f6c9258
DK		 275 */
276void bnx2x_set_rx_mode(struct net_device *dev);
277
278/**
279 * Configure MAC filtering rules in a FW.
280 *
281 * @param bp driver handle
282 */
283void bnx2x_set_storm_rx_mode(struct bnx2x *bp);
284
285/* Parity errors related */
286void bnx2x_inc_load_cnt(struct bnx2x *bp);
287u32 bnx2x_dec_load_cnt(struct bnx2x *bp);
288bool bnx2x_chk_parity_attn(struct bnx2x *bp);
289bool bnx2x_reset_is_done(struct bnx2x *bp);
290void bnx2x_disable_close_the_gate(struct bnx2x *bp);
291
292/**
293 * Perform statistics handling according to event
294 *
295 * @param bp driver handle
f85582f8 296 * @param event bnx2x_stats_event
9f6c9258
DK		 297 */
298void bnx2x_stats_handle(struct bnx2x *bp, enum bnx2x_stats_event event);
299
9f6c9258 300/**
f85582f8 301 * Handle ramrods completion
9f6c9258
DK		 302 *
303 * @param fp fastpath handle for the event
304 * @param rr_cqe eth_rx_cqe
305 */
f85582f8 306void bnx2x_sp_event(struct bnx2x_fastpath *fp, union eth_rx_cqe *rr_cqe);
9f6c9258 307
523224a3
DK		 308/**
309 * Init/halt function before/after sending
310 * CLIENT_SETUP/CFC_DEL for the first/last client.
311 *
312 * @param bp
313 *
314 * @return int
315 */
316int bnx2x_func_start(struct bnx2x *bp);
523224a3
DK		 317
318/**
319 * Prepare ILT configurations according to current driver
320 * parameters.
321 *
322 * @param bp
323 */
324void bnx2x_ilt_set_info(struct bnx2x *bp);
9f6c9258 325
e4901dde
VZ		 326/**
327 * Inintialize dcbx protocol
328 *
329 * @param bp
330 */
331void bnx2x_dcbx_init(struct bnx2x *bp);
332
f85582f8
DK		 333/**
334 * Set power state to the requested value. Currently only D0 and
335 * D3hot are supported.
336 *
337 * @param bp
338 * @param state D0 or D3hot
339 *
340 * @return int
341 */
342int bnx2x_set_power_state(struct bnx2x *bp, pci_power_t state);
343
344/* dev_close main block */
345int bnx2x_nic_unload(struct bnx2x *bp, int unload_mode);
346
347/* dev_open main block */
348int bnx2x_nic_load(struct bnx2x *bp, int load_mode);
349
350/* hard_xmit callback */
351netdev_tx_t bnx2x_start_xmit(struct sk_buff *skb, struct net_device *dev);
352
8307fa3e
VZ		 353/* select_queue callback */
354u16 bnx2x_select_queue(struct net_device *dev, struct sk_buff *skb);
355
f85582f8
DK		 356int bnx2x_change_mac_addr(struct net_device *dev, void *p);
357
358/* NAPI poll Rx part */
359int bnx2x_rx_int(struct bnx2x_fastpath *fp, int budget);
360
361/* NAPI poll Tx part */
362int bnx2x_tx_int(struct bnx2x_fastpath *fp);
363
364/* suspend/resume callbacks */
365int bnx2x_suspend(struct pci_dev *pdev, pm_message_t state);
366int bnx2x_resume(struct pci_dev *pdev);
367
368/* Release IRQ vectors */
369void bnx2x_free_irq(struct bnx2x *bp);
370
371void bnx2x_init_rx_rings(struct bnx2x *bp);
372void bnx2x_free_skbs(struct bnx2x *bp);
373void bnx2x_netif_stop(struct bnx2x *bp, int disable_hw);
374void bnx2x_netif_start(struct bnx2x *bp);
375
d6214d7a
DK		 376/**
377 * Fill msix_table, request vectors, update num_queues according
378 * to number of available vectors
379 *
380 * @param bp
381 *
382 * @return int
383 */
384int bnx2x_enable_msix(struct bnx2x *bp);
385
386/**
387 * Request msi mode from OS, updated internals accordingly
388 *
389 * @param bp
390 *
391 * @return int
392 */
393int bnx2x_enable_msi(struct bnx2x *bp);
394
d6214d7a
DK		 395/**
396 * NAPI callback
397 *
398 * @param napi
399 * @param budget
400 *
401 * @return int
402 */
403int bnx2x_poll(struct napi_struct *napi, int budget);
f85582f8
DK		 404
405/**
406 * Allocate/release memories outsize main driver structure
407 *
408 * @param bp
409 *
410 * @return int
411 */
412int __devinit bnx2x_alloc_mem_bp(struct bnx2x *bp);
413void bnx2x_free_mem_bp(struct bnx2x *bp);
414
415/**
416 * Change mtu netdev callback
417 *
418 * @param dev
419 * @param new_mtu
420 *
421 * @return int
422 */
423int bnx2x_change_mtu(struct net_device *dev, int new_mtu);
424
425/**
426 * tx timeout netdev callback
427 *
428 * @param dev
429 * @param new_mtu
430 *
431 * @return int
432 */
433void bnx2x_tx_timeout(struct net_device *dev);
434
435#ifdef BCM_VLAN
436/**
437 * vlan rx register netdev callback
438 *
439 * @param dev
440 * @param new_mtu
441 *
442 * @return int
443 */
444void bnx2x_vlan_rx_register(struct net_device *dev,
445 struct vlan_group *vlgrp);
446
447#endif
448
9f6c9258
DK		 449static inline void bnx2x_update_fpsb_idx(struct bnx2x_fastpath *fp)
450{
9f6c9258 451 barrier(); /* status block is written to by the chip */
523224a3 452 fp->fp_hc_idx = fp->sb_running_index[SM_RX_ID];
9f6c9258
DK		 453}
454
455static inline void bnx2x_update_rx_prod(struct bnx2x *bp,
456 struct bnx2x_fastpath *fp,
457 u16 bd_prod, u16 rx_comp_prod,
458 u16 rx_sge_prod)
459{
460 struct ustorm_eth_rx_producers rx_prods = {0};
461 int i;
462
463 /* Update producers */
464 rx_prods.bd_prod = bd_prod;
465 rx_prods.cqe_prod = rx_comp_prod;
466 rx_prods.sge_prod = rx_sge_prod;
467
468 /*
469 * Make sure that the BD and SGE data is updated before updating the
470 * producers since FW might read the BD/SGE right after the producer
471 * is updated.
472 * This is only applicable for weak-ordered memory model archs such
473 * as IA-64. The following barrier is also mandatory since FW will
474 * assumes BDs must have buffers.
475 */
476 wmb();
477
478 for (i = 0; i < sizeof(struct ustorm_eth_rx_producers)/4; i++)
523224a3
DK		 479 REG_WR(bp,
480 BAR_USTRORM_INTMEM + fp->ustorm_rx_prods_offset + i*4,
9f6c9258
DK		 481 ((u32 *)&rx_prods)[i]);
482
483 mmiowb(); /* keep prod updates ordered */
484
485 DP(NETIF_MSG_RX_STATUS,
486 "queue[%d]: wrote bd_prod %u cqe_prod %u sge_prod %u\n",
487 fp->index, bd_prod, rx_comp_prod, rx_sge_prod);
488}
489
f2e0899f
DK		 490static inline void bnx2x_igu_ack_sb_gen(struct bnx2x *bp, u8 igu_sb_id,
491 u8 segment, u16 index, u8 op,
492 u8 update, u32 igu_addr)
493{
494 struct igu_regular cmd_data = {0};
495
496 cmd_data.sb_id_and_flags =
497 ((index << IGU_REGULAR_SB_INDEX_SHIFT) |
498 (segment << IGU_REGULAR_SEGMENT_ACCESS_SHIFT) |
499 (update << IGU_REGULAR_BUPDATE_SHIFT) |
500 (op << IGU_REGULAR_ENABLE_INT_SHIFT));
501
502 DP(NETIF_MSG_HW, "write 0x%08x to IGU addr 0x%x\n",
503 cmd_data.sb_id_and_flags, igu_addr);
504 REG_WR(bp, igu_addr, cmd_data.sb_id_and_flags);
505
506 /* Make sure that ACK is written */
507 mmiowb();
508 barrier();
509}
510
511static inline void bnx2x_igu_clear_sb_gen(struct bnx2x *bp,
512 u8 idu_sb_id, bool is_Pf)
513{
514 u32 data, ctl, cnt = 100;
515 u32 igu_addr_data = IGU_REG_COMMAND_REG_32LSB_DATA;
516 u32 igu_addr_ctl = IGU_REG_COMMAND_REG_CTRL;
517 u32 igu_addr_ack = IGU_REG_CSTORM_TYPE_0_SB_CLEANUP + (idu_sb_id/32)*4;
518 u32 sb_bit = 1 << (idu_sb_id%32);
519 u32 func_encode = BP_FUNC(bp) |
520 ((is_Pf == true ? 1 : 0) << IGU_FID_ENCODE_IS_PF_SHIFT);
521 u32 addr_encode = IGU_CMD_E2_PROD_UPD_BASE + idu_sb_id;
522
523 /* Not supported in BC mode */
524 if (CHIP_INT_MODE_IS_BC(bp))
525 return;
526
527 data = (IGU_USE_REGISTER_cstorm_type_0_sb_cleanup
528 << IGU_REGULAR_CLEANUP_TYPE_SHIFT) |
529 IGU_REGULAR_CLEANUP_SET |
530 IGU_REGULAR_BCLEANUP;
531
532 ctl = addr_encode << IGU_CTRL_REG_ADDRESS_SHIFT |
533 func_encode << IGU_CTRL_REG_FID_SHIFT |
534 IGU_CTRL_CMD_TYPE_WR << IGU_CTRL_REG_TYPE_SHIFT;
9f6c9258 535
f2e0899f
DK		 536 DP(NETIF_MSG_HW, "write 0x%08x to IGU(via GRC) addr 0x%x\n",
537 data, igu_addr_data);
538 REG_WR(bp, igu_addr_data, data);
539 mmiowb();
540 barrier();
541 DP(NETIF_MSG_HW, "write 0x%08x to IGU(via GRC) addr 0x%x\n",
542 ctl, igu_addr_ctl);
543 REG_WR(bp, igu_addr_ctl, ctl);
544 mmiowb();
545 barrier();
9f6c9258 546
f2e0899f
DK		 547 /* wait for clean up to finish */
548 while (!(REG_RD(bp, igu_addr_ack) & sb_bit) && --cnt)
549 msleep(20);
550
551
552 if (!(REG_RD(bp, igu_addr_ack) & sb_bit)) {
553 DP(NETIF_MSG_HW, "Unable to finish IGU cleanup: "
554 "idu_sb_id %d offset %d bit %d (cnt %d)\n",
555 idu_sb_id, idu_sb_id/32, idu_sb_id%32, cnt);
556 }
557}
558
559static inline void bnx2x_hc_ack_sb(struct bnx2x *bp, u8 sb_id,
560 u8 storm, u16 index, u8 op, u8 update)
9f6c9258
DK		 561{
562 u32 hc_addr = (HC_REG_COMMAND_REG + BP_PORT(bp)*32 +
563 COMMAND_REG_INT_ACK);
564 struct igu_ack_register igu_ack;
565
566 igu_ack.status_block_index = index;
567 igu_ack.sb_id_and_flags =
568 ((sb_id << IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT) |
569 (storm << IGU_ACK_REGISTER_STORM_ID_SHIFT) |
570 (update << IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT) |
571 (op << IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT));
572
573 DP(BNX2X_MSG_OFF, "write 0x%08x to HC addr 0x%x\n",
574 (*(u32 *)&igu_ack), hc_addr);
575 REG_WR(bp, hc_addr, (*(u32 *)&igu_ack));
576
577 /* Make sure that ACK is written */
578 mmiowb();
579 barrier();
580}
f2e0899f
DK		 581
582static inline void bnx2x_igu_ack_sb(struct bnx2x *bp, u8 igu_sb_id, u8 segment,
583 u16 index, u8 op, u8 update)
584{
585 u32 igu_addr = BAR_IGU_INTMEM + (IGU_CMD_INT_ACK_BASE + igu_sb_id)*8;
586
587 bnx2x_igu_ack_sb_gen(bp, igu_sb_id, segment, index, op, update,
588 igu_addr);
589}
590
591static inline void bnx2x_ack_sb(struct bnx2x *bp, u8 igu_sb_id, u8 storm,
592 u16 index, u8 op, u8 update)
593{
594 if (bp->common.int_block == INT_BLOCK_HC)
595 bnx2x_hc_ack_sb(bp, igu_sb_id, storm, index, op, update);
596 else {
597 u8 segment;
598
599 if (CHIP_INT_MODE_IS_BC(bp))
600 segment = storm;
601 else if (igu_sb_id != bp->igu_dsb_id)
602 segment = IGU_SEG_ACCESS_DEF;
603 else if (storm == ATTENTION_ID)
604 segment = IGU_SEG_ACCESS_ATTN;
605 else
606 segment = IGU_SEG_ACCESS_DEF;
607 bnx2x_igu_ack_sb(bp, igu_sb_id, segment, index, op, update);
608 }
609}
610
611static inline u16 bnx2x_hc_ack_int(struct bnx2x *bp)
9f6c9258
DK		 612{
613 u32 hc_addr = (HC_REG_COMMAND_REG + BP_PORT(bp)*32 +
614 COMMAND_REG_SIMD_MASK);
615 u32 result = REG_RD(bp, hc_addr);
616
617 DP(BNX2X_MSG_OFF, "read 0x%08x from HC addr 0x%x\n",
618 result, hc_addr);
619
f2e0899f 620 barrier();
9f6c9258
DK		 621 return result;
622}
623
f2e0899f
DK		 624static inline u16 bnx2x_igu_ack_int(struct bnx2x *bp)
625{
626 u32 igu_addr = (BAR_IGU_INTMEM + IGU_REG_SISR_MDPC_WMASK_LSB_UPPER*8);
627 u32 result = REG_RD(bp, igu_addr);
628
629 DP(NETIF_MSG_HW, "read 0x%08x from IGU addr 0x%x\n",
630 result, igu_addr);
631
632 barrier();
633 return result;
634}
635
636static inline u16 bnx2x_ack_int(struct bnx2x *bp)
637{
638 barrier();
639 if (bp->common.int_block == INT_BLOCK_HC)
640 return bnx2x_hc_ack_int(bp);
641 else
642 return bnx2x_igu_ack_int(bp);
643}
644
9f6c9258
DK		 645static inline int bnx2x_has_tx_work_unload(struct bnx2x_fastpath *fp)
646{
647 /* Tell compiler that consumer and producer can change */
648 barrier();
807540ba 649 return fp->tx_pkt_prod != fp->tx_pkt_cons;
9f6c9258
DK		 650}
651
652static inline u16 bnx2x_tx_avail(struct bnx2x_fastpath *fp)
653{
654 s16 used;
655 u16 prod;
656 u16 cons;
657
658 prod = fp->tx_bd_prod;
659 cons = fp->tx_bd_cons;
660
661 /* NUM_TX_RINGS = number of "next-page" entries
662 It will be used as a threshold */
663 used = SUB_S16(prod, cons) + (s16)NUM_TX_RINGS;
664
665#ifdef BNX2X_STOP_ON_ERROR
666 WARN_ON(used < 0);
667 WARN_ON(used > fp->bp->tx_ring_size);
668 WARN_ON((fp->bp->tx_ring_size - used) > MAX_TX_AVAIL);
669#endif
670
671 return (s16)(fp->bp->tx_ring_size) - used;
672}
673
674static inline int bnx2x_has_tx_work(struct bnx2x_fastpath *fp)
675{
676 u16 hw_cons;
677
678 /* Tell compiler that status block fields can change */
679 barrier();
680 hw_cons = le16_to_cpu(*fp->tx_cons_sb);
681 return hw_cons != fp->tx_pkt_cons;
682}
683
523224a3
DK		 684static inline int bnx2x_has_rx_work(struct bnx2x_fastpath *fp)
685{
686 u16 rx_cons_sb;
687
688 /* Tell compiler that status block fields can change */
689 barrier();
690 rx_cons_sb = le16_to_cpu(*fp->rx_cons_sb);
691 if ((rx_cons_sb & MAX_RCQ_DESC_CNT) == MAX_RCQ_DESC_CNT)
692 rx_cons_sb++;
693 return (fp->rx_comp_cons != rx_cons_sb);
694}
f85582f8 695
f2e0899f
DK		 696/**
697 * disables tx from stack point of view
698 *
699 * @param bp
700 */
701static inline void bnx2x_tx_disable(struct bnx2x *bp)
702{
703 netif_tx_disable(bp->dev);
704 netif_carrier_off(bp->dev);
705}
706
9f6c9258
DK		 707static inline void bnx2x_free_rx_sge(struct bnx2x *bp,
708 struct bnx2x_fastpath *fp, u16 index)
709{
710 struct sw_rx_page *sw_buf = &fp->rx_page_ring[index];
711 struct page *page = sw_buf->page;
712 struct eth_rx_sge *sge = &fp->rx_sge_ring[index];
713
714 /* Skip "next page" elements */
715 if (!page)
716 return;
717
718 dma_unmap_page(&bp->pdev->dev, dma_unmap_addr(sw_buf, mapping),
4bca60f4 719 SGE_PAGE_SIZE*PAGES_PER_SGE, DMA_FROM_DEVICE);
9f6c9258
DK		 720 __free_pages(page, PAGES_PER_SGE_SHIFT);
721
722 sw_buf->page = NULL;
723 sge->addr_hi = 0;
724 sge->addr_lo = 0;
725}
726
d6214d7a
DK		 727static inline void bnx2x_add_all_napi(struct bnx2x *bp)
728{
729 int i;
523224a3 730
d6214d7a 731 /* Add NAPI objects */
ec6ba945 732 for_each_napi_queue(bp, i)
d6214d7a
DK		 733 netif_napi_add(bp->dev, &bnx2x_fp(bp, i, napi),
734 bnx2x_poll, BNX2X_NAPI_WEIGHT);
735}
523224a3 736
d6214d7a
DK		 737static inline void bnx2x_del_all_napi(struct bnx2x *bp)
738{
739 int i;
740
ec6ba945 741 for_each_napi_queue(bp, i)
d6214d7a
DK		 742 netif_napi_del(&bnx2x_fp(bp, i, napi));
743}
523224a3 744
d6214d7a
DK		 745static inline void bnx2x_disable_msi(struct bnx2x *bp)
746{
747 if (bp->flags & USING_MSIX_FLAG) {
748 pci_disable_msix(bp->pdev);
749 bp->flags &= ~USING_MSIX_FLAG;
750 } else if (bp->flags & USING_MSI_FLAG) {
751 pci_disable_msi(bp->pdev);
752 bp->flags &= ~USING_MSI_FLAG;
753 }
754}
755
756static inline int bnx2x_calc_num_queues(struct bnx2x *bp)
757{
758 return num_queues ?
759 min_t(int, num_queues, BNX2X_MAX_QUEUES(bp)) :
760 min_t(int, num_online_cpus(), BNX2X_MAX_QUEUES(bp));
761}
523224a3
DK		 762
763static inline void bnx2x_clear_sge_mask_next_elems(struct bnx2x_fastpath *fp)
9f6c9258 764{
523224a3 765 int i, j;
9f6c9258 766
523224a3
DK		 767 for (i = 1; i <= NUM_RX_SGE_PAGES; i++) {
768 int idx = RX_SGE_CNT * i - 1;
769
770 for (j = 0; j < 2; j++) {
771 SGE_MASK_CLEAR_BIT(fp, idx);
772 idx--;
773 }
774 }
775}
776
777static inline void bnx2x_init_sge_ring_bit_mask(struct bnx2x_fastpath *fp)
778{
779 /* Set the mask to all 1-s: it's faster to compare to 0 than to 0xf-s */
780 memset(fp->sge_mask, 0xff,
781 (NUM_RX_SGE >> RX_SGE_MASK_ELEM_SHIFT)*sizeof(u64));
782
783 /* Clear the two last indices in the page to 1:
784 these are the indices that correspond to the "next" element,
785 hence will never be indicated and should be removed from
786 the calculations. */
787 bnx2x_clear_sge_mask_next_elems(fp);
9f6c9258
DK		 788}
789
790static inline int bnx2x_alloc_rx_sge(struct bnx2x *bp,
791 struct bnx2x_fastpath *fp, u16 index)
792{
793 struct page *page = alloc_pages(GFP_ATOMIC, PAGES_PER_SGE_SHIFT);
794 struct sw_rx_page *sw_buf = &fp->rx_page_ring[index];
795 struct eth_rx_sge *sge = &fp->rx_sge_ring[index];
796 dma_addr_t mapping;
797
798 if (unlikely(page == NULL))
799 return -ENOMEM;
800
801 mapping = dma_map_page(&bp->pdev->dev, page, 0,
802 SGE_PAGE_SIZE*PAGES_PER_SGE, DMA_FROM_DEVICE);
803 if (unlikely(dma_mapping_error(&bp->pdev->dev, mapping))) {
804 __free_pages(page, PAGES_PER_SGE_SHIFT);
805 return -ENOMEM;
806 }
807
808 sw_buf->page = page;
809 dma_unmap_addr_set(sw_buf, mapping, mapping);
810
811 sge->addr_hi = cpu_to_le32(U64_HI(mapping));
812 sge->addr_lo = cpu_to_le32(U64_LO(mapping));
813
814 return 0;
815}
f85582f8 816
9f6c9258
DK		 817static inline int bnx2x_alloc_rx_skb(struct bnx2x *bp,
818 struct bnx2x_fastpath *fp, u16 index)
819{
820 struct sk_buff *skb;
821 struct sw_rx_bd *rx_buf = &fp->rx_buf_ring[index];
822 struct eth_rx_bd *rx_bd = &fp->rx_desc_ring[index];
823 dma_addr_t mapping;
824
825 skb = netdev_alloc_skb(bp->dev, bp->rx_buf_size);
826 if (unlikely(skb == NULL))
827 return -ENOMEM;
828
829 mapping = dma_map_single(&bp->pdev->dev, skb->data, bp->rx_buf_size,
830 DMA_FROM_DEVICE);
831 if (unlikely(dma_mapping_error(&bp->pdev->dev, mapping))) {
832 dev_kfree_skb(skb);
833 return -ENOMEM;
834 }
835
836 rx_buf->skb = skb;
837 dma_unmap_addr_set(rx_buf, mapping, mapping);
838
839 rx_bd->addr_hi = cpu_to_le32(U64_HI(mapping));
840 rx_bd->addr_lo = cpu_to_le32(U64_LO(mapping));
841
842 return 0;
843}
844
845/* note that we are not allocating a new skb,
846 * we are just moving one from cons to prod
847 * we are not creating a new mapping,
848 * so there is no need to check for dma_mapping_error().
849 */
850static inline void bnx2x_reuse_rx_skb(struct bnx2x_fastpath *fp,
749a8503 851 u16 cons, u16 prod)
9f6c9258
DK		 852{
853 struct bnx2x *bp = fp->bp;
854 struct sw_rx_bd *cons_rx_buf = &fp->rx_buf_ring[cons];
855 struct sw_rx_bd *prod_rx_buf = &fp->rx_buf_ring[prod];
856 struct eth_rx_bd *cons_bd = &fp->rx_desc_ring[cons];
857 struct eth_rx_bd *prod_bd = &fp->rx_desc_ring[prod];
858
859 dma_sync_single_for_device(&bp->pdev->dev,
860 dma_unmap_addr(cons_rx_buf, mapping),
861 RX_COPY_THRESH, DMA_FROM_DEVICE);
862
863 prod_rx_buf->skb = cons_rx_buf->skb;
864 dma_unmap_addr_set(prod_rx_buf, mapping,
865 dma_unmap_addr(cons_rx_buf, mapping));
866 *prod_bd = *cons_bd;
867}
f85582f8 868
523224a3
DK		 869static inline void bnx2x_free_rx_sge_range(struct bnx2x *bp,
870 struct bnx2x_fastpath *fp, int last)
9f6c9258 871{
523224a3 872 int i;
9f6c9258 873
523224a3
DK		 874 for (i = 0; i < last; i++)
875 bnx2x_free_rx_sge(bp, fp, i);
9f6c9258
DK		 876}
877
9f6c9258
DK		 878static inline void bnx2x_free_tpa_pool(struct bnx2x *bp,
879 struct bnx2x_fastpath *fp, int last)
880{
881 int i;
882
883 for (i = 0; i < last; i++) {
884 struct sw_rx_bd *rx_buf = &(fp->tpa_pool[i]);
885 struct sk_buff *skb = rx_buf->skb;
886
887 if (skb == NULL) {
888 DP(NETIF_MSG_IFDOWN, "tpa bin %d empty on free\n", i);
889 continue;
890 }
891
892 if (fp->tpa_state[i] == BNX2X_TPA_START)
893 dma_unmap_single(&bp->pdev->dev,
894 dma_unmap_addr(rx_buf, mapping),
895 bp->rx_buf_size, DMA_FROM_DEVICE);
896
897 dev_kfree_skb(skb);
898 rx_buf->skb = NULL;
899 }
900}
901
902
523224a3 903static inline void bnx2x_init_tx_rings(struct bnx2x *bp)
9f6c9258
DK		 904{
905 int i, j;
906
ec6ba945 907 for_each_tx_queue(bp, j) {
9f6c9258
DK		 908 struct bnx2x_fastpath *fp = &bp->fp[j];
909
910 for (i = 1; i <= NUM_TX_RINGS; i++) {
911 struct eth_tx_next_bd *tx_next_bd =
912 &fp->tx_desc_ring[TX_DESC_CNT * i - 1].next_bd;
913
914 tx_next_bd->addr_hi =
915 cpu_to_le32(U64_HI(fp->tx_desc_mapping +
916 BCM_PAGE_SIZE*(i % NUM_TX_RINGS)));
917 tx_next_bd->addr_lo =
918 cpu_to_le32(U64_LO(fp->tx_desc_mapping +
919 BCM_PAGE_SIZE*(i % NUM_TX_RINGS)));
920 }
921
523224a3 922 SET_FLAG(fp->tx_db.data.header.header, DOORBELL_HDR_DB_TYPE, 1);
9f6c9258
DK		 923 fp->tx_db.data.zero_fill1 = 0;
924 fp->tx_db.data.prod = 0;
925
926 fp->tx_pkt_prod = 0;
927 fp->tx_pkt_cons = 0;
928 fp->tx_bd_prod = 0;
929 fp->tx_bd_cons = 0;
9f6c9258
DK		 930 fp->tx_pkt = 0;
931 }
932}
f85582f8 933
523224a3 934static inline void bnx2x_set_next_page_rx_bd(struct bnx2x_fastpath *fp)
9f6c9258 935{
523224a3 936 int i;
9f6c9258 937
523224a3
DK		 938 for (i = 1; i <= NUM_RX_RINGS; i++) {
939 struct eth_rx_bd *rx_bd;
940
941 rx_bd = &fp->rx_desc_ring[RX_DESC_CNT * i - 2];
942 rx_bd->addr_hi =
943 cpu_to_le32(U64_HI(fp->rx_desc_mapping +
944 BCM_PAGE_SIZE*(i % NUM_RX_RINGS)));
945 rx_bd->addr_lo =
946 cpu_to_le32(U64_LO(fp->rx_desc_mapping +
947 BCM_PAGE_SIZE*(i % NUM_RX_RINGS)));
948 }
9f6c9258
DK		 949}
950
523224a3
DK		 951static inline void bnx2x_set_next_page_sgl(struct bnx2x_fastpath *fp)
952{
953 int i;
954
955 for (i = 1; i <= NUM_RX_SGE_PAGES; i++) {
956 struct eth_rx_sge *sge;
957
958 sge = &fp->rx_sge_ring[RX_SGE_CNT * i - 2];
959 sge->addr_hi =
960 cpu_to_le32(U64_HI(fp->rx_sge_mapping +
961 BCM_PAGE_SIZE*(i % NUM_RX_SGE_PAGES)));
962
963 sge->addr_lo =
964 cpu_to_le32(U64_LO(fp->rx_sge_mapping +
965 BCM_PAGE_SIZE*(i % NUM_RX_SGE_PAGES)));
966 }
967}
968
969static inline void bnx2x_set_next_page_rx_cq(struct bnx2x_fastpath *fp)
970{
971 int i;
972 for (i = 1; i <= NUM_RCQ_RINGS; i++) {
973 struct eth_rx_cqe_next_page *nextpg;
974
975 nextpg = (struct eth_rx_cqe_next_page *)
976 &fp->rx_comp_ring[RCQ_DESC_CNT * i - 1];
977 nextpg->addr_hi =
978 cpu_to_le32(U64_HI(fp->rx_comp_mapping +
979 BCM_PAGE_SIZE*(i % NUM_RCQ_RINGS)));
980 nextpg->addr_lo =
981 cpu_to_le32(U64_LO(fp->rx_comp_mapping +
982 BCM_PAGE_SIZE*(i % NUM_RCQ_RINGS)));
983 }
984}
985
ec6ba945
VZ		 986#ifdef BCM_CNIC
987static inline void bnx2x_init_fcoe_fp(struct bnx2x *bp)
988{
989 bnx2x_fcoe(bp, cl_id) = BNX2X_FCOE_ETH_CL_ID +
990 BP_E1HVN(bp) * NONE_ETH_CONTEXT_USE;
991 bnx2x_fcoe(bp, cid) = BNX2X_FCOE_ETH_CID;
992 bnx2x_fcoe(bp, fw_sb_id) = DEF_SB_ID;
993 bnx2x_fcoe(bp, igu_sb_id) = bp->igu_dsb_id;
994 bnx2x_fcoe(bp, bp) = bp;
995 bnx2x_fcoe(bp, state) = BNX2X_FP_STATE_CLOSED;
996 bnx2x_fcoe(bp, index) = FCOE_IDX;
997 bnx2x_fcoe(bp, rx_cons_sb) = BNX2X_FCOE_L2_RX_INDEX;
998 bnx2x_fcoe(bp, tx_cons_sb) = BNX2X_FCOE_L2_TX_INDEX;
999 /* qZone id equals to FW (per path) client id */
1000 bnx2x_fcoe(bp, cl_qzone_id) = bnx2x_fcoe(bp, cl_id) +
1001 BP_PORT(bp)*(CHIP_IS_E2(bp) ? ETH_MAX_RX_CLIENTS_E2 :
1002 ETH_MAX_RX_CLIENTS_E1H);
1003 /* init shortcut */
1004 bnx2x_fcoe(bp, ustorm_rx_prods_offset) = CHIP_IS_E2(bp) ?
1005 USTORM_RX_PRODS_E2_OFFSET(bnx2x_fcoe(bp, cl_qzone_id)) :
1006 USTORM_RX_PRODS_E1X_OFFSET(BP_PORT(bp), bnx2x_fcoe_fp(bp)->cl_id);
523224a3 1007
ec6ba945
VZ		 1008}
1009#endif
523224a3
DK		 1010
1011static inline void __storm_memset_struct(struct bnx2x *bp,
1012 u32 addr, size_t size, u32 *data)
1013{
1014 int i;
1015 for (i = 0; i < size/4; i++)
1016 REG_WR(bp, addr + (i * 4), data[i]);
1017}
1018
1019static inline void storm_memset_mac_filters(struct bnx2x *bp,
1020 struct tstorm_eth_mac_filter_config *mac_filters,
1021 u16 abs_fid)
1022{
1023 size_t size = sizeof(struct tstorm_eth_mac_filter_config);
1024
1025 u32 addr = BAR_TSTRORM_INTMEM +
1026 TSTORM_MAC_FILTER_CONFIG_OFFSET(abs_fid);
1027
1028 __storm_memset_struct(bp, addr, size, (u32 *)mac_filters);
1029}
1030
1031static inline void storm_memset_cmng(struct bnx2x *bp,
1032 struct cmng_struct_per_port *cmng,
1033 u8 port)
1034{
1035 size_t size = sizeof(struct cmng_struct_per_port);
1036
1037 u32 addr = BAR_XSTRORM_INTMEM +
1038 XSTORM_CMNG_PER_PORT_VARS_OFFSET(port);
1039
1040 __storm_memset_struct(bp, addr, size, (u32 *)cmng);
1041}
f85582f8 1042
9f6c9258
DK		 1043/* HW Lock for shared dual port PHYs */
1044void bnx2x_acquire_phy_lock(struct bnx2x *bp);
1045void bnx2x_release_phy_lock(struct bnx2x *bp);
1046
9f6c9258 1047#endif /* BNX2X_CMN_H */
Linux kernel - Deliverables
This page took 0.134788 seconds and 5 git commands to generate.